157 files changed, 222515 insertions, 0 deletions

diff --git a/README.txt b/README.txt
new file mode 100644
index 0000000000000..553c46df946a8
--- /dev/null
+++ b/README.txt
@@ -0,0 +1,43 @@
+Readme for the Octeon Executive Library
+
+
+The Octeon Executive Library provides runtime support and hardware 
+abstraction for the Octeon processor.  The executive is composed of the 
+libcvmx.a library as well as header files that provide  
+functionality with inline functions.
+
+
+Usage:
+
+The libcvmx.a library is built for every application as part of the
+application build. (Please refer to the 'related pages' section of the 
+HTML documentation for more information on the build system.)  
+Applications using the executive should include the header files from
+$OCTEON_ROOT/target/include and link against the library that is built in 
+the local obj directory. Each file using the executive 
+should include the following two header files in order:
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+
+The cvmx-config.h file contains configuration information for the 
+executive and is generated by the cvmx-config script from an 
+'executive-config.h' file. A sample version of this file is provided 
+in the executive directory as 'executive-config.h.template'.  
+
+Copy this file to 'executive-config.h' into the 'config' subdirectory 
+of the application directory and customize as required by the application. 
+Applications that don't use any simple executive functionality can omit 
+the cvmx-config.h header file. Please refer to the examples for a 
+demonstration of where to put the executive-config.h file and for an
+example of generated cvmx-config.h.
+
+For file specific information please see the documentation within the 
+source files or the HTML documentation provided in docs/html/index.html.
+The HTML documentation is automatically generated by Doxygen from the 
+source files.
+
+
+
+==========================================================================
+Please see the release notes for version specific information.
diff --git a/cvmip.h b/cvmip.h
new file mode 100644
index 0000000000000..a8ac16d5bdaa8
--- /dev/null
+++ b/cvmip.h
@@ -0,0 +1,207 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Cavium Networks Internet Protocol (IP)
+ *
+ * Definitions for the Internet Protocol (IP) support.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMIP_H__
+#define __CVMIP_H__
+
+
+/*
+ * IP protocol values (1 byte)
+ *
+ */
+#define  CVMIP_PROTO_ICMP  1    /* Internet Control Message Protocol */
+#define  CVMIP_PROTO_TCP   6    /* Transmission Control Protocol */
+#define  CVMIP_PROTO_UDP  17    /* User Datagram Protocol */
+#define  CVMIP_PROTO_ESP  50    /* Encapsulated Security Payload */
+#define  CVMIP_PROTO_AH   51    /* Authentication Header */
+
+
+/**
+ * network packet header definitions
+ * (originally from octane_hw.h)
+ *
+ */
+
+/**
+ * UDP Packet header
+ */
+typedef struct {
+   union {
+      int32_t           s32     ;
+      uint32_t          u32     ;
+      struct {
+         uint16_t        src_prt ;
+         uint16_t        dst_prt ;
+      } s;
+   } prts;
+   uint16_t            len     ;
+   uint16_t            chksum  ;
+} cvmip_udp_hdr_t;
+
+/**
+ * TCP Packet header
+ */
+typedef struct {
+   uint16_t            src_prt ;
+   uint16_t            dst_prt ;
+   uint32_t            seq     ;
+   uint32_t            ack_seq ;
+   uint32_t            hlen    :4;
+   uint32_t            rsvd    :6;
+   uint32_t            urg     :1;
+   uint32_t            ack     :1;
+   uint32_t            psh     :1;
+   uint32_t            rst     :1;
+   uint32_t            syn     :1;
+   uint32_t            fin     :1;
+   uint16_t            win_sz  ;
+   uint16_t            chksum  ;
+   uint16_t            urg_ptr ;
+   uint32_t            junk    ;
+} cvmip_tcp_hdr_t;
+
+/**
+ * L4 Packet header
+ */
+typedef union {
+   cvmip_udp_hdr_t udphdr;
+   cvmip_tcp_hdr_t tcphdr;
+   struct {
+      union {
+         int32_t           s32    ;
+         uint32_t          u32    ;
+         struct {
+            uint16_t        src_prt;
+            uint16_t        dst_prt;
+         } s;
+      } prts;
+      uint16_t            len     ;
+      uint16_t            chksum  ;
+      char              dat[48] ; // 48 for IPv6 with no extension hdrs, 64 for IPv4 without options
+   } udp;
+   struct {
+      uint16_t            src_prt ;
+      uint16_t            dst_prt ;
+      uint32_t            seq     ;
+      uint32_t            ack_seq ;
+      uint32_t            hlen    :4;
+      uint32_t            rsvd    :6;
+      uint32_t            urg     :1;
+      uint32_t            ack     :1;
+      uint32_t            psh     :1;
+      uint32_t            rst     :1;
+      uint32_t            syn     :1;
+      uint32_t            fin     :1;
+      uint16_t            win_sz  ;
+      uint16_t            chksum  ;
+      uint16_t            urg_ptr ;
+      char              dat[36] ; // 36 for IPv6 with no extension hdrs, 52 for IPv6 without options
+   } tcp;
+} cvmip_l4_info_t;
+
+/**
+ * Special struct to add a pad to IPv4 header
+ */
+typedef struct {
+   uint32_t            pad;
+
+   uint32_t            version : 4;
+   uint32_t            hl      : 4;
+   uint8_t             tos     ;
+   uint16_t            len     ;
+
+   uint16_t            id      ;
+   uint32_t            mbz     : 1;
+   uint32_t            df      : 1;
+   uint32_t            mf      : 1;
+   uint32_t            off     :13;
+
+   uint8_t             ttl     ;
+   uint8_t             protocol;
+   uint16_t            chksum  ;
+
+   union {
+      uint64_t          u64;
+      struct {
+         uint32_t        src;
+         uint32_t        dst;
+      } s;
+   } src_dst;
+} cvmip_ipv4_hdr_t;
+
+/**
+ * IPv6 Packet header
+ */
+typedef struct {
+
+   uint32_t            version : 4;
+   uint32_t            v6class : 8;
+   uint32_t            flow    :20;
+
+   uint16_t            len     ;    // includes extension headers plus payload (add 40 to be equiv to v4 len field)
+   uint8_t             next_hdr;    // equivalent to the v4 protocol field
+   uint8_t             hop_lim ;    // equivalent to the v4 TTL field
+
+   union {
+      uint64_t          u64[4];
+      struct {
+         uint64_t        src[2];
+         uint64_t        dst[2];
+      } s;
+   } src_dst;
+
+} cvmip_ipv6_hdr_t;
+
+
+#endif /* __CVMIP_H__ */
diff --git a/cvmx-abi.h b/cvmx-abi.h
new file mode 100644
index 0000000000000..0711558d768f3
--- /dev/null
+++ b/cvmx-abi.h
@@ -0,0 +1,92 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file defines macros for use in determining the current calling ABI.
+ *
+ * <hr>$Revision: 41586 $<hr>
+*/
+
+#ifndef __CVMX_ABI_H__
+#define __CVMX_ABI_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Check for N32 ABI, defined for 32-bit Simple Exec applications
+   and Linux N32 ABI.*/
+#if (defined _ABIN32 && _MIPS_SIM == _ABIN32)
+#define CVMX_ABI_N32
+/* Check for N64 ABI, defined for 64-bit Linux toolchain. */
+#elif (defined _ABI64 && _MIPS_SIM == _ABI64)
+#define CVMX_ABI_N64
+/* Check for O32 ABI, defined for Linux 032 ABI, not supported yet. */
+#elif (defined _ABIO32 && _MIPS_SIM == _ABIO32)
+#define CVMX_ABI_O32
+/* Check for EABI ABI, defined for 64-bit Simple Exec applications. */
+#else
+#define CVMX_ABI_EABI
+#endif
+
+#ifndef __BYTE_ORDER
+    #if defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
+        #define __BYTE_ORDER __BIG_ENDIAN
+    #elif !defined(__BIG_ENDIAN) && defined(__LITTLE_ENDIAN)
+        #define __BYTE_ORDER __LITTLE_ENDIAN
+        #define __BIG_ENDIAN 4321
+    #elif !defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
+        #define __BIG_ENDIAN 4321
+        #define __BYTE_ORDER __BIG_ENDIAN
+    #else
+        #error Unable to determine Endian mode
+    #endif
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_ABI_H__ */
diff --git a/cvmx-access-native.h b/cvmx-access-native.h
new file mode 100644
index 0000000000000..c16ca9e96a2e9
--- /dev/null
+++ b/cvmx-access-native.h
@@ -0,0 +1,667 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Functions for accessing memory and CSRs on Octeon when we are compiling
+ * natively.
+ *
+ * <hr>$Revision: 38306 $<hr>
+*/
+#ifndef __CVMX_ACCESS_NATIVE_H__
+#define __CVMX_ACCESS_NATIVE_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Returns the Octeon processor ID.
+ *
+ * @return Octeon processor ID from COP0
+ */
+static inline uint32_t cvmx_get_proc_id(void)
+{
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+    extern uint32_t cvmx_app_init_processor_id;
+    return cvmx_app_init_processor_id;
+#else
+    uint32_t id;
+    asm ("mfc0 %0, $15,0" : "=r" (id));
+    return id;
+#endif
+}
+
+/**
+ * Convert a memory pointer (void*) into a hardware compatable
+ * memory address (uint64_t). Octeon hardware widgets don't
+ * understand logical addresses.
+ *
+ * @param ptr    C style memory pointer
+ * @return Hardware physical address
+ */
+static inline uint64_t cvmx_ptr_to_phys(void *ptr)
+{
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+        cvmx_warn_if(ptr==NULL, "cvmx_ptr_to_phys() passed a NULL pointer\n");
+
+#ifdef CVMX_BUILD_FOR_UBOOT
+    /* U-boot is a special case, as it is running in error level, which disables the TLB completely.
+    ** U-boot may use kseg0 addresses, or may directly use physical addresses already */
+    return(CAST64(ptr) & 0x7FFFFFFF);
+#endif
+
+#ifdef __linux__
+    if (sizeof(void*) == 8)
+    {
+        /* We're running in 64 bit mode. Normally this means that we can use
+            40 bits of address space (the hardware limit). Unfortunately there
+            is one case were we need to limit this to 30 bits, sign extended
+            32 bit. Although these are 64 bits wide, only 30 bits can be used */
+        if ((CAST64(ptr) >> 62) == 3)
+            return CAST64(ptr) & cvmx_build_mask(30);
+        else
+            return CAST64(ptr) & cvmx_build_mask(40);
+    }
+    else
+    {
+#ifdef __KERNEL__
+	return (long)(ptr) & 0x1fffffff;
+#else
+        extern uint64_t linux_mem32_offset;
+        if (cvmx_likely(ptr))
+            return CAST64(ptr) - linux_mem32_offset;
+        else
+            return 0;
+#endif
+    }
+#elif defined(_WRS_KERNEL)
+	return (long)(ptr) & 0x7fffffff;
+#elif defined(VXWORKS_USER_MAPPINGS)
+    /* This mapping mode is used in vxWorks 5.5 to support 2GB of ram. The
+        2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
+    uint64_t address = (long)ptr;
+    if (address & 0x80000000)
+        return address & 0x1fffffff;    /* KSEG pointers directly map the lower 256MB and bootbus */
+    else if ((address >= 0x10000000) && (address < 0x20000000))
+        return address + 0x400000000ull;   /* 256MB-512MB is a virtual mapping for the 2nd 256MB */
+    else
+        return address; /* Looks to be a 1:1 mapped userspace pointer */
+#else
+#if CVMX_USE_1_TO_1_TLB_MAPPINGS
+    /* We are assumung we're running the Simple Executive standalone. In this
+        mode the TLB is setup to perform 1:1 mapping and 32 bit sign extended
+        addresses are never used. Since we know all this, save the masking
+        cycles and do nothing */
+    return CAST64(ptr);
+#else
+
+    if (sizeof(void*) == 8)
+    {
+        /* We're running in 64 bit mode. Normally this means that we can use
+            40 bits of address space (the hardware limit). Unfortunately there
+            is one case were we need to limit this to 30 bits, sign extended
+            32 bit. Although these are 64 bits wide, only 30 bits can be used */
+        if ((CAST64(ptr) >> 62) == 3)
+            return CAST64(ptr) & cvmx_build_mask(30);
+        else
+            return CAST64(ptr) & cvmx_build_mask(40);
+    }
+    else
+	return (long)(ptr) & 0x7fffffff;
+
+#endif
+#endif
+}
+
+
+/**
+ * Convert a hardware physical address (uint64_t) into a
+ * memory pointer (void *).
+ *
+ * @param physical_address
+ *               Hardware physical address to memory
+ * @return Pointer to memory
+ */
+static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
+{
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+        cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
+
+#ifdef CVMX_BUILD_FOR_UBOOT
+    /* U-boot is a special case, as it is running in error level, which disables the TLB completely.
+    ** U-boot may use kseg0 addresses, or may directly use physical addresses already */
+    if (physical_address >= 0x80000000)
+        return NULL;
+    else
+        return CASTPTR(void, (physical_address & 0x7FFFFFFF));
+#endif
+
+#ifdef __linux__
+    if (sizeof(void*) == 8)
+    {
+        /* Just set the top bit, avoiding any TLB uglyness */
+        return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
+    }
+    else
+    {
+#ifdef __KERNEL__
+	return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
+#else
+        extern uint64_t linux_mem32_offset;
+        if (cvmx_likely(physical_address))
+            return CASTPTR(void, physical_address + linux_mem32_offset);
+        else
+            return NULL;
+#endif
+    }
+#elif defined(_WRS_KERNEL)
+	return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
+#elif defined(VXWORKS_USER_MAPPINGS)
+    /* This mapping mode is used in vxWorks 5.5 to support 2GB of ram. The
+        2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
+    if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
+        return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
+    else if ((physical_address >= 0x410000000ull) && (physical_address < 0x420000000ull))
+        return CASTPTR(void, physical_address - 0x400000000ull);
+    else
+        return CASTPTR(void, physical_address);
+#else
+
+#if CVMX_USE_1_TO_1_TLB_MAPPINGS
+        /* We are assumung we're running the Simple Executive standalone. In this
+            mode the TLB is setup to perform 1:1 mapping and 32 bit sign extended
+            addresses are never used. Since we know all this, save bit insert
+            cycles and do nothing */
+    return CASTPTR(void, physical_address);
+#else
+    /* Set the XKPHYS/KSEG0 bit as appropriate based on ABI */
+    if (sizeof(void*) == 8)
+        return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
+    else
+	return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
+
+#endif
+
+#endif
+}
+
+
+/* The following #if controls the definition of the macro
+    CVMX_BUILD_WRITE64. This macro is used to build a store operation to
+    a full 64bit address. With a 64bit ABI, this can be done with a simple
+    pointer access. 32bit ABIs require more complicated assembly */
+#if defined(CVMX_ABI_N64) || defined(CVMX_ABI_EABI)
+
+/* We have a full 64bit ABI. Writing to a 64bit address can be done with
+    a simple volatile pointer */
+#define CVMX_BUILD_WRITE64(TYPE, ST)                                    \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)     \
+{                                                                       \
+    *CASTPTR(volatile TYPE##_t, addr) = val;                            \
+}
+
+#elif defined(CVMX_ABI_N32)
+
+/* The N32 ABI passes all 64bit quantities in a single register, so it is
+    possible to use the arguments directly. We have to use inline assembly
+    for the actual store since a pointer would truncate the address */
+#define CVMX_BUILD_WRITE64(TYPE, ST)                                    \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)     \
+{                                                                       \
+    asm volatile (ST " %[v], 0(%[c])" ::[v] "r" (val), [c] "r" (addr)); \
+}
+
+#elif defined(CVMX_ABI_O32)
+
+#ifdef __KERNEL__
+#define CVMX_BUILD_WRITE64(TYPE, LT) extern void cvmx_write64_##TYPE(uint64_t csr_addr, TYPE##_t val);
+#else
+
+/* Ok, now the ugly stuff starts. O32 splits 64bit quantities into two
+    separate registers. Assembly must be used to put them back together
+    before they're used. What should be a simple store becomes a
+    convoluted mess of shifts and ors */
+#define CVMX_BUILD_WRITE64(TYPE, ST)                                    \
+static inline void cvmx_write64_##TYPE(uint64_t csr_addr, TYPE##_t val) \
+{                                                                       \
+    if (sizeof(TYPE##_t) == 8)                                          \
+    {                                                                   \
+        uint32_t csr_addrh = csr_addr>>32;                              \
+        uint32_t csr_addrl = csr_addr;                                  \
+        uint32_t valh = (uint64_t)val>>32;                              \
+        uint32_t vall = val;                                            \
+        uint32_t tmp1;                                                  \
+        uint32_t tmp2;                                                  \
+        uint32_t tmp3;                                                  \
+                                                                        \
+        asm volatile (                                                  \
+            ".set push\n"                                             \
+            ".set mips64\n"                                             \
+            "dsll   %[tmp1], %[valh], 32\n"                             \
+            "dsll   %[tmp2], %[csrh], 32\n"                             \
+            "dsll   %[tmp3], %[vall], 32\n"                             \
+            "dsrl   %[tmp3], %[tmp3], 32\n"                             \
+            "or     %[tmp1], %[tmp1], %[tmp3]\n"                        \
+            "dsll   %[tmp3], %[csrl], 32\n"                             \
+            "dsrl   %[tmp3], %[tmp3], 32\n"                             \
+            "or     %[tmp2], %[tmp2], %[tmp3]\n"                        \
+            ST "    %[tmp1], 0(%[tmp2])\n"                              \
+            ".set pop\n"                                             \
+            : [tmp1] "=&r" (tmp1), [tmp2] "=&r" (tmp2), [tmp3] "=&r" (tmp3)\
+            : [valh] "r" (valh), [vall] "r" (vall),                     \
+              [csrh] "r" (csr_addrh), [csrl] "r" (csr_addrl)            \
+        );                                                              \
+    }                                                                   \
+    else                                                                \
+    {                                                                   \
+        uint32_t csr_addrh = csr_addr>>32;                              \
+        uint32_t csr_addrl = csr_addr;                                  \
+        uint32_t tmp1;                                                  \
+        uint32_t tmp2;                                                  \
+                                                                        \
+        asm volatile (                                                  \
+            ".set push\n"                                             \
+            ".set mips64\n"                                             \
+            "dsll   %[tmp1], %[csrh], 32\n"                             \
+            "dsll   %[tmp2], %[csrl], 32\n"                             \
+            "dsrl   %[tmp2], %[tmp2], 32\n"                             \
+            "or     %[tmp1], %[tmp1], %[tmp2]\n"                        \
+            ST "    %[val], 0(%[tmp1])\n"                               \
+            ".set pop\n"                                             \
+            : [tmp1] "=&r" (tmp1), [tmp2] "=&r" (tmp2)                  \
+            : [val] "r" (val), [csrh] "r" (csr_addrh),                  \
+              [csrl] "r" (csr_addrl)                                    \
+        );                                                              \
+    }                                                                   \
+}
+
+#endif
+
+#else
+
+/* cvmx-abi.h didn't recognize the ABI. Force the compile to fail. */
+#error: Unsupported ABI
+
+#endif
+
+/* The following #if controls the definition of the macro
+    CVMX_BUILD_READ64. This macro is used to build a load operation from
+    a full 64bit address. With a 64bit ABI, this can be done with a simple
+    pointer access. 32bit ABIs require more complicated assembly */
+#if defined(CVMX_ABI_N64) || defined(CVMX_ABI_EABI)
+
+/* We have a full 64bit ABI. Writing to a 64bit address can be done with
+    a simple volatile pointer */
+#define CVMX_BUILD_READ64(TYPE, LT)                                     \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr)                \
+{                                                                       \
+    return *CASTPTR(volatile TYPE##_t, addr);                           \
+}
+
+#elif defined(CVMX_ABI_N32)
+
+/* The N32 ABI passes all 64bit quantities in a single register, so it is
+    possible to use the arguments directly. We have to use inline assembly
+    for the actual store since a pointer would truncate the address */
+#define CVMX_BUILD_READ64(TYPE, LT)                                     \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr)                \
+{                                                                       \
+    TYPE##_t val;                                                       \
+    asm volatile (LT " %[v], 0(%[c])": [v] "=r" (val) : [c] "r" (addr));\
+    return val;                                                         \
+}
+
+#elif defined(CVMX_ABI_O32)
+
+#ifdef __KERNEL__
+#define CVMX_BUILD_READ64(TYPE, LT) extern TYPE##_t cvmx_read64_##TYPE(uint64_t csr_addr);
+#else
+
+/* Ok, now the ugly stuff starts. O32 splits 64bit quantities into two
+    separate registers. Assembly must be used to put them back together
+    before they're used. What should be a simple load becomes a
+    convoluted mess of shifts and ors */
+#define CVMX_BUILD_READ64(TYPE, LT)                                     \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t csr_addr)            \
+{                                                                       \
+    if (sizeof(TYPE##_t) == 8)                                          \
+    {                                                                   \
+        uint32_t csr_addrh = csr_addr>>32;                              \
+        uint32_t csr_addrl = csr_addr;                                  \
+        uint32_t valh;                                                  \
+        uint32_t vall;                                                  \
+                                                                        \
+        asm volatile (                                                  \
+            ".set push\n"                                               \
+            ".set mips64\n"                                             \
+            "dsll   %[valh], %[csrh], 32\n"                             \
+            "dsll   %[vall], %[csrl], 32\n"                             \
+            "dsrl   %[vall], %[vall], 32\n"                             \
+            "or     %[valh], %[valh], %[vall]\n"                        \
+            LT "    %[vall], 0(%[valh])\n"                              \
+            "dsrl   %[valh], %[vall], 32\n"                             \
+            "sll    %[vall], 0\n"                                       \
+            "sll    %[valh], 0\n"                                       \
+            ".set pop\n"                                                \
+            : [valh] "=&r" (valh), [vall] "=&r" (vall)                  \
+            : [csrh] "r" (csr_addrh), [csrl] "r" (csr_addrl)            \
+        );                                                              \
+        return ((uint64_t)valh<<32) | vall;                             \
+    }                                                                   \
+    else                                                                \
+    {                                                                   \
+        uint32_t csr_addrh = csr_addr>>32;                              \
+        uint32_t csr_addrl = csr_addr;                                  \
+        TYPE##_t val;                                                   \
+        uint32_t tmp;                                                   \
+                                                                        \
+        asm volatile (                                                  \
+            ".set push\n"                                             \
+            ".set mips64\n"                                             \
+            "dsll   %[val], %[csrh], 32\n"                              \
+            "dsll   %[tmp], %[csrl], 32\n"                              \
+            "dsrl   %[tmp], %[tmp], 32\n"                               \
+            "or     %[val], %[val], %[tmp]\n"                           \
+            LT "    %[val], 0(%[val])\n"                                \
+            ".set pop\n"                                             \
+            : [val] "=&r" (val), [tmp] "=&r" (tmp)                      \
+            : [csrh] "r" (csr_addrh), [csrl] "r" (csr_addrl)            \
+        );                                                              \
+        return val;                                                     \
+    }                                                                   \
+}
+
+#endif /* __KERNEL__ */
+
+#else
+
+/* cvmx-abi.h didn't recognize the ABI. Force the compile to fail. */
+#error: Unsupported ABI
+
+#endif
+
+/* The following defines 8 functions for writing to a 64bit address. Each
+    takes two arguments, the address and the value to write.
+    cvmx_write64_int64      cvmx_write64_uint64
+    cvmx_write64_int32      cvmx_write64_uint32
+    cvmx_write64_int16      cvmx_write64_uint16
+    cvmx_write64_int8       cvmx_write64_uint8 */
+CVMX_BUILD_WRITE64(int64, "sd");
+CVMX_BUILD_WRITE64(int32, "sw");
+CVMX_BUILD_WRITE64(int16, "sh");
+CVMX_BUILD_WRITE64(int8, "sb");
+CVMX_BUILD_WRITE64(uint64, "sd");
+CVMX_BUILD_WRITE64(uint32, "sw");
+CVMX_BUILD_WRITE64(uint16, "sh");
+CVMX_BUILD_WRITE64(uint8, "sb");
+
+/* The following defines 8 functions for reading from a 64bit address. Each
+    takes the address as the only argument
+    cvmx_read64_int64       cvmx_read64_uint64
+    cvmx_read64_int32       cvmx_read64_uint32
+    cvmx_read64_int16       cvmx_read64_uint16
+    cvmx_read64_int8        cvmx_read64_uint8 */
+CVMX_BUILD_READ64(int64, "ld");
+CVMX_BUILD_READ64(int32, "lw");
+CVMX_BUILD_READ64(int16, "lh");
+CVMX_BUILD_READ64(int8, "lb");
+CVMX_BUILD_READ64(uint64, "ld");
+CVMX_BUILD_READ64(uint32, "lw");
+CVMX_BUILD_READ64(uint16, "lhu");
+CVMX_BUILD_READ64(uint8, "lbu");
+
+static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
+{
+    cvmx_write64_uint64(csr_addr, val);
+
+    /* Perform an immediate read after every write to an RSL register to force
+        the write to complete. It doesn't matter what RSL read we do, so we
+        choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
+    if ((csr_addr >> 40) == (0x800118))
+        cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT);
+}
+
+static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
+{
+    cvmx_write64_uint64(io_addr, val);
+}
+
+static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
+{
+    return cvmx_read64_uint64(csr_addr);
+}
+
+static inline void cvmx_send_single(uint64_t data)
+{
+    const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
+    cvmx_write64_uint64(CVMX_IOBDMA_SENDSINGLE, data);
+}
+
+static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
+{
+    union
+    {
+        uint64_t    u64;
+        struct {
+            uint64_t    scraddr : 8;
+            uint64_t    len     : 8;
+            uint64_t    addr    :48;
+        } s;
+    } addr;
+    addr.u64 = csr_addr;
+    addr.s.scraddr = scraddr >> 3;
+    addr.s.len = 1;
+    cvmx_send_single(addr.u64);
+}
+
+
+/**
+ * Number of the Core on which the program is currently running. 
+ *
+ * @return Number of cores
+ */
+static inline unsigned int cvmx_get_core_num(void)
+{
+    unsigned int core_num;
+    CVMX_RDHWRNV(core_num, 0);
+    return core_num;
+}
+
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for POP instruction.
+ *
+ * @param val    32 bit value to count set bits in
+ *
+ * @return Number of bits set
+ */
+static inline uint32_t cvmx_pop(uint32_t val)
+{
+    uint32_t pop;
+    CVMX_POP(pop, val);
+    return pop;
+}
+
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for DPOP instruction.
+ *
+ * @param val    64 bit value to count set bits in
+ *
+ * @return Number of bits set
+ */
+static inline int cvmx_dpop(uint64_t val)
+{
+    int pop;
+    CVMX_DPOP(pop, val);
+    return pop;
+}
+
+
+/**
+ * Provide current cycle counter as a return value
+ *
+ * @return current cycle counter
+ */
+static inline uint64_t cvmx_get_cycle(void)
+{
+#if defined(CVMX_ABI_O32)
+    uint32_t tmp_low, tmp_hi;
+
+    asm volatile (
+               "   .set push                    \n"
+               "   .set mips64r2                \n"
+               "   .set noreorder               \n"
+               "   rdhwr %[tmpl], $31           \n"
+               "   dsrl  %[tmph], %[tmpl], 32   \n"
+               "   sll   %[tmpl], 0             \n"
+               "   sll   %[tmph], 0             \n"
+               "   .set pop                 \n"
+                  : [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
+
+    return(((uint64_t)tmp_hi << 32) + tmp_low);
+#else
+    uint64_t cycle;
+    CVMX_RDHWR(cycle, 31);
+    return(cycle);
+#endif
+}
+
+
+/**
+ * Reads a chip global cycle counter.  This counts CPU cycles since
+ * chip reset.  The counter is 64 bit.
+ * This register does not exist on CN38XX pass 1 silicion
+ *
+ * @return Global chip cycle count since chip reset.
+ */
+static inline uint64_t cvmx_get_cycle_global(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+        return 0;
+    else
+        return cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
+}
+
+
+/**
+ * Wait for the specified number of cycle
+ *
+ * @param cycles
+ */
+static inline void cvmx_wait(uint64_t cycles)
+{
+    uint64_t done = cvmx_get_cycle() + cycles;
+
+    while (cvmx_get_cycle() < done)
+    {
+        /* Spin */
+    }
+}
+
+
+/**
+ * Wait for the specified number of micro seconds
+ *
+ * @param usec   micro seconds to wait
+ */
+static inline void cvmx_wait_usec(uint64_t usec)
+{
+    uint64_t done = cvmx_get_cycle() + usec * cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+    while (cvmx_get_cycle() < done)
+    {
+        /* Spin */
+    }
+}
+
+
+/**
+ * Perform a soft reset of Octeon
+ *
+ * @return
+ */
+static inline void cvmx_reset_octeon(void)
+{
+    cvmx_ciu_soft_rst_t ciu_soft_rst;
+    ciu_soft_rst.u64 = 0;
+    ciu_soft_rst.s.soft_rst = 1;
+    cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
+}
+
+
+/**
+ * Read a byte of fuse data
+ * @param byte_addr   address to read
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline uint8_t cvmx_fuse_read_byte(int byte_addr)
+{
+    cvmx_mio_fus_rcmd_t read_cmd;
+
+    read_cmd.u64 = 0;
+    read_cmd.s.addr = byte_addr;
+    read_cmd.s.pend = 1;
+    cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
+    while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) && read_cmd.s.pend)
+        ;
+    return(read_cmd.s.dat);
+}
+
+
+/**
+ * Read a single fuse bit
+ *
+ * @param fuse   Fuse number (0-1024)
+ *
+ * @return fuse value: 0 or 1
+ */
+static inline int cvmx_fuse_read(int fuse)
+{
+    return((cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_ACCESS_NATIVE_H__ */
+
diff --git a/cvmx-access.h b/cvmx-access.h
new file mode 100644
index 0000000000000..d0da7caea22a8
--- /dev/null
+++ b/cvmx-access.h
@@ -0,0 +1,228 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Function prototypes for accessing memory and CSRs on Octeon.
+ *
+ * <hr>$Revision: 38306 $<hr>
+*/
+#ifndef __CVMX_ACCESS_H__
+#define __CVMX_ACCESS_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* We're going to assume that if we are compiling for Mips then we must be
+    running natively on Octoen. It is possible that this code could be
+    compiled on a non Octeon Mips that is acting as a PCI/PCIe host. In this
+    case this assumption will be wrong and cause issues We can't key off of
+    __octeon__ since some people use stock gcc toolchains */
+#if defined(__mips__) && !defined(CVMX_BUILD_FOR_LINUX_HOST)
+    #define CVMX_FUNCTION static inline
+#else
+    #define CVMX_FUNCTION extern
+#endif
+
+/**
+ * simprintf uses simulator tricks to speed up printouts.  The format
+ * and args are passed to the simulator and processed natively on the host.
+ * Simprintf is limited to 7 arguments, and they all must use %ll (long long)
+ * format specifiers to be displayed correctly.
+ *
+ * @param format
+ *
+ * @return
+ */
+EXTERN_ASM void simprintf(const char *format, ...);
+
+/**
+ * This function performs some default initialization of the Octeon executive.
+ * It initializes the cvmx_bootmem memory allocator with the list of physical
+ * memory provided by the bootloader, and creates 1-1 TLB mappings for this
+ * memory. This function should be called on all cores that will use either the
+ * bootmem allocator or the 1-1 TLB mappings. Applications which require a
+ * different configuration can replace this function with a suitable application
+ * specific one.
+ *
+ * @return 0 on success
+ *         -1 on failure
+ */
+extern int cvmx_user_app_init(void);
+
+/**
+ * Returns the Octeon processor ID.
+ *
+ * @return Octeon processor ID from COP0
+ */
+CVMX_FUNCTION uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
+
+/**
+ * Convert a memory pointer (void*) into a hardware compatable
+ * memory address (uint64_t). Octeon hardware widgets don't
+ * understand logical addresses.
+ *
+ * @param ptr    C style memory pointer
+ * @return Hardware physical address
+ */
+CVMX_FUNCTION uint64_t cvmx_ptr_to_phys(void *ptr);
+
+/**
+ * Convert a hardware physical address (uint64_t) into a
+ * memory pointer (void *).
+ *
+ * @param physical_address
+ *               Hardware physical address to memory
+ * @return Pointer to memory
+ */
+CVMX_FUNCTION void *cvmx_phys_to_ptr(uint64_t physical_address);
+
+CVMX_FUNCTION void cvmx_write64_int64(uint64_t address, int64_t value);
+CVMX_FUNCTION void cvmx_write64_uint64(uint64_t address, uint64_t value);
+CVMX_FUNCTION void cvmx_write64_int32(uint64_t address, int32_t value);
+CVMX_FUNCTION void cvmx_write64_uint32(uint64_t address, uint32_t value);
+CVMX_FUNCTION void cvmx_write64_int16(uint64_t address, int16_t value);
+CVMX_FUNCTION void cvmx_write64_uint16(uint64_t address, uint16_t value);
+CVMX_FUNCTION void cvmx_write64_int8(uint64_t address, int8_t value);
+CVMX_FUNCTION void cvmx_write64_uint8(uint64_t address, uint8_t value);
+CVMX_FUNCTION void cvmx_write_csr(uint64_t csr_addr, uint64_t val);
+CVMX_FUNCTION void cvmx_write_io(uint64_t io_addr, uint64_t val);
+
+CVMX_FUNCTION int64_t cvmx_read64_int64(uint64_t address);
+CVMX_FUNCTION uint64_t cvmx_read64_uint64(uint64_t address);
+CVMX_FUNCTION int32_t cvmx_read64_int32(uint64_t address);
+CVMX_FUNCTION uint32_t cvmx_read64_uint32(uint64_t address);
+CVMX_FUNCTION int16_t cvmx_read64_int16(uint64_t address);
+CVMX_FUNCTION uint16_t cvmx_read64_uint16(uint64_t address);
+CVMX_FUNCTION int8_t cvmx_read64_int8(uint64_t address);
+CVMX_FUNCTION uint8_t cvmx_read64_uint8(uint64_t address);
+CVMX_FUNCTION uint64_t cvmx_read_csr(uint64_t csr_addr);
+
+CVMX_FUNCTION void cvmx_send_single(uint64_t data);
+CVMX_FUNCTION void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr);
+
+/**
+ * Number of the Core on which the program is currently running. 
+ *
+ * @return Number of cores
+ */
+CVMX_FUNCTION unsigned int cvmx_get_core_num(void);
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for POP instruction.
+ *
+ * @param val    32 bit value to count set bits in
+ *
+ * @return Number of bits set
+ */
+CVMX_FUNCTION uint32_t cvmx_pop(uint32_t val);
+
+/**
+ * Returns the number of bits set in the provided value.
+ * Simple wrapper for DPOP instruction.
+ *
+ * @param val    64 bit value to count set bits in
+ *
+ * @return Number of bits set
+ */
+CVMX_FUNCTION int cvmx_dpop(uint64_t val);
+
+/**
+ * Provide current cycle counter as a return value
+ *
+ * @return current cycle counter
+ */
+CVMX_FUNCTION uint64_t cvmx_get_cycle(void);
+
+/**
+ * Reads a chip global cycle counter.  This counts CPU cycles since
+ * chip reset.  The counter is 64 bit.
+ * This register does not exist on CN38XX pass 1 silicion
+ *
+ * @return Global chip cycle count since chip reset.
+ */
+CVMX_FUNCTION uint64_t cvmx_get_cycle_global(void);
+
+/**
+ * Wait for the specified number of cycle
+ *
+ * @param cycles
+ */
+CVMX_FUNCTION void cvmx_wait(uint64_t cycles);
+
+/**
+ * Wait for the specified number of micro seconds
+ *
+ * @param usec   micro seconds to wait
+ */
+CVMX_FUNCTION void cvmx_wait_usec(uint64_t usec);
+
+/**
+ * Perform a soft reset of Octeon
+ *
+ * @return
+ */
+CVMX_FUNCTION void cvmx_reset_octeon(void);
+
+/**
+ * Read a byte of fuse data
+ * @param byte_addr   address to read
+ *
+ * @return fuse value: 0 or 1
+ */
+CVMX_FUNCTION uint8_t cvmx_fuse_read_byte(int byte_addr);
+
+/**
+ * Read a single fuse bit
+ *
+ * @param fuse   Fuse number (0-1024)
+ *
+ * @return fuse value: 0 or 1
+ */
+CVMX_FUNCTION int cvmx_fuse_read(int fuse);
+
+#undef CVMX_FUNCTION
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_ACCESS_H__ */
+
diff --git a/cvmx-address.h b/cvmx-address.h
new file mode 100644
index 0000000000000..096a68ab958ff
--- /dev/null
+++ b/cvmx-address.h
@@ -0,0 +1,253 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Typedefs and defines for working with Octeon physical addresses.
+ *
+ * <hr>$Revision: 38306 $<hr>
+*/
+#ifndef __CVMX_ADDRESS_H__
+#define __CVMX_ADDRESS_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+   CVMX_MIPS_SPACE_XKSEG = 3LL,
+   CVMX_MIPS_SPACE_XKPHYS = 2LL,
+   CVMX_MIPS_SPACE_XSSEG = 1LL,
+   CVMX_MIPS_SPACE_XUSEG = 0LL
+} cvmx_mips_space_t;
+
+typedef enum {
+   CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
+   CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
+   CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
+   CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
+} cvmx_mips_xkseg_space_t;
+
+// decodes <14:13> of a kseg3 window address
+typedef enum {
+   CVMX_ADD_WIN_SCR = 0L,
+   CVMX_ADD_WIN_DMA = 1L,   // see cvmx_add_win_dma_dec_t for further decode
+   CVMX_ADD_WIN_UNUSED = 2L,
+   CVMX_ADD_WIN_UNUSED2 = 3L
+} cvmx_add_win_dec_t;
+
+// decode within DMA space
+typedef enum {
+   CVMX_ADD_WIN_DMA_ADD = 0L,     // add store data to the write buffer entry, allocating it if necessary
+   CVMX_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM
+                                     // store data must be normal DRAM memory space address in this case
+   CVMX_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command
+                                     // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents
+   CVMX_ADD_WIN_DMA_SENDIO = 3L,  // send out the write buffer entry as an IO write
+                                     // store data must be normal IO space address in this case
+   CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus
+                                        // no write buffer data needed/used
+} cvmx_add_win_dma_dec_t;
+
+
+
+/**
+ *   Physical Address Decode
+ *
+ * Octeon-I HW never interprets this X (<39:36> reserved
+ * for future expansion), software should set to 0.
+ *
+ *  - 0x0 XXX0 0000 0000 to      DRAM         Cached
+ *  - 0x0 XXX0 0FFF FFFF
+ *
+ *  - 0x0 XXX0 1000 0000 to      Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
+ *  - 0x0 XXX0 1FFF FFFF         + EJTAG                           to 0x1 00X0 1FFF FFFF)
+ *
+ *  - 0x0 XXX0 2000 0000 to      DRAM         Cached
+ *  - 0x0 XXXF FFFF FFFF
+ *
+ *  - 0x1 00X0 0000 0000 to      Boot Bus     Uncached
+ *  - 0x1 00XF FFFF FFFF
+ *
+ *  - 0x1 01X0 0000 0000 to      Other NCB    Uncached
+ *  - 0x1 FFXF FFFF FFFF         devices
+ *
+ * Decode of all Octeon addresses
+ */
+typedef union {
+
+   uint64_t         u64;
+
+   struct {
+      cvmx_mips_space_t          R   : 2;
+      uint64_t               offset :62;
+   } sva; // mapped or unmapped virtual address
+
+   struct {
+      uint64_t               zeroes :33;
+      uint64_t               offset :31;
+   } suseg; // mapped USEG virtual addresses (typically)
+
+   struct {
+      uint64_t                ones  :33;
+      cvmx_mips_xkseg_space_t   sp   : 2;
+      uint64_t               offset :29;
+   } sxkseg; // mapped or unmapped virtual address
+
+   struct {
+      cvmx_mips_space_t          R   : 2; // CVMX_MIPS_SPACE_XKPHYS in this case
+      uint64_t                 cca  : 3; // ignored by octeon
+      uint64_t                 mbz  :10;
+      uint64_t                  pa  :49; // physical address
+   } sxkphys; // physical address accessed through xkphys unmapped virtual address
+
+   struct {
+      uint64_t                 mbz  :15;
+      uint64_t                is_io : 1; // if set, the address is uncached and resides on MCB bus
+      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
+      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
+      uint64_t               offset :36;
+   } sphys; // physical address
+
+   struct {
+      uint64_t               zeroes :24; // techically, <47:40> are dont-cares
+      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
+      uint64_t               offset :36;
+   } smem; // physical mem address
+
+   struct {
+      uint64_t                 mem_region  :2;
+      uint64_t                 mbz  :13;
+      uint64_t                is_io : 1; // 1 in this case
+      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
+      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
+      uint64_t               offset :36;
+   } sio; // physical IO address
+
+   struct {
+      uint64_t                ones   : 49;
+      cvmx_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_SCR (0) in this case
+      uint64_t                addr   : 13;
+   } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3
+
+   // there should only be stores to IOBDMA space, no loads
+   struct {
+      uint64_t                ones   : 49;
+      cvmx_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_DMA (1) in this case
+      uint64_t                unused2: 3;
+      cvmx_add_win_dma_dec_t type : 3;
+      uint64_t                addr   : 7;
+   } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3
+
+   struct {
+      uint64_t                didspace : 24;
+      uint64_t                unused   : 40;
+   } sfilldidspace;
+
+} cvmx_addr_t;
+
+/* These macros for used by 32 bit applications */
+
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add)          (((int32_t)segment << 31) | (int32_t)(add))
+
+/* Currently all IOs are performed using XKPHYS addressing. Linux uses the
+    CvmMemCtl register to enable XKPHYS addressing to IO space from user mode.
+    Future OSes may need to change the upper bits of IO addresses. The
+    following define controls the upper two bits for all IO addresses generated
+    by the simple executive library */
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add)          ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add)                CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+#define CVMX_ADDR_DIDSPACE(did)             (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
+#define CVMX_ADDR_DID(did)                  (CVMX_ADDR_DIDSPACE(did) << 40)
+#define CVMX_FULL_DID(did,subdid)           (((did) << 3) | (subdid))
+
+
+// from include/ncb_rsl_id.v
+#define CVMX_OCT_DID_MIS 0ULL   // misc stuff
+#define CVMX_OCT_DID_GMX0 1ULL
+#define CVMX_OCT_DID_GMX1 2ULL
+#define CVMX_OCT_DID_PCI 3ULL
+#define CVMX_OCT_DID_KEY 4ULL
+#define CVMX_OCT_DID_FPA 5ULL
+#define CVMX_OCT_DID_DFA 6ULL
+#define CVMX_OCT_DID_ZIP 7ULL
+#define CVMX_OCT_DID_RNG 8ULL
+#define CVMX_OCT_DID_IPD 9ULL
+#define CVMX_OCT_DID_PKT 10ULL
+#define CVMX_OCT_DID_TIM 11ULL
+#define CVMX_OCT_DID_TAG 12ULL
+// the rest are not on the IO bus
+#define CVMX_OCT_DID_L2C 16ULL
+#define CVMX_OCT_DID_LMC 17ULL
+#define CVMX_OCT_DID_SPX0 18ULL
+#define CVMX_OCT_DID_SPX1 19ULL
+#define CVMX_OCT_DID_PIP 20ULL
+#define CVMX_OCT_DID_ASX0 22ULL
+#define CVMX_OCT_DID_ASX1 23ULL
+#define CVMX_OCT_DID_IOB 30ULL
+
+#define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT,2ULL)
+#define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG,0ULL)
+#define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG,1ULL)
+#define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
+#define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
+#define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
+#define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
+#define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
+#define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
+#define CVMX_OCT_DID_KEY_RW         CVMX_FULL_DID(CVMX_OCT_DID_KEY,0ULL)
+#define CVMX_OCT_DID_PCI_6          CVMX_FULL_DID(CVMX_OCT_DID_PCI,6ULL)
+#define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS,0ULL)
+#define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI,0ULL)
+#define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD,7ULL)
+#define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA,7ULL)
+#define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
+#define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_ADDRESS_H__ */
+
diff --git a/cvmx-app-init-linux.c b/cvmx-app-init-linux.c
new file mode 100644
index 0000000000000..ed83b50dbe781
--- /dev/null
+++ b/cvmx-app-init-linux.c
@@ -0,0 +1,457 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ * Simple executive application initialization for Linux user space. This
+ * file should be used instead of cvmx-app-init.c for running simple executive
+ * applications under Linux in userspace. The following are some of the key
+ * points to remember when writing applications to run both under the
+ * standalone simple executive and userspace under Linux.
+ *
+ * -# Application main must be called "appmain" under Linux. Use and ifdef
+ *      based on __linux__ to determine the proper name.
+ * -# Be careful to use cvmx_ptr_to_phys() and cvmx_phys_to_ptr. The simple
+ *      executive 1-1 TLB mappings allow you to be sloppy and interchange
+ *      hardware addresses with virtual address. This isn't true under Linux.
+ * -# If you're talking directly to hardware, be careful. The normal Linux
+ *      protections are circumvented. If you do something bad, Linux won't
+ *      save you.
+ * -# Most hardware can only be initialized once. Unless you're very careful,
+ *      this also means you Linux application can only run once.
+ *
+ * <hr>$Revision: 41757 $<hr>
+ *
+ */
+#define _GNU_SOURCE
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <signal.h>
+#include <sys/statfs.h>
+#include <sys/wait.h>
+#include <sys/sysmips.h>
+#include <sched.h>
+#include <octeon-app-init.h>
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-atomic.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-coremask.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-bootmem.h"
+
+int octeon_model_version_check(uint32_t chip_id);
+
+#define OCTEON_ECLOCK_MULT_INPUT_X16    ((int)(33.4*16))
+
+/* Applications using the simple executive libraries under Linux userspace must
+    rename their "main" function to match the prototype below. This allows the
+    simple executive to perform needed memory initialization and process
+    creation before the application runs. */
+extern int appmain(int argc, const char *argv[]);
+
+/* These two external addresses provide the beginning and end markers for the
+    CVMX_SHARED section. These are defined by the cvmx-shared.ld linker script.
+    If they aren't defined, you probably forgot to link using this script. */
+extern void __cvmx_shared_start;
+extern void __cvmx_shared_end;
+extern uint64_t linux_mem32_min;
+extern uint64_t linux_mem32_max;
+extern uint64_t linux_mem32_wired;
+extern uint64_t linux_mem32_offset;
+
+#define MIPS_CAVIUM_XKPHYS_READ	   2010	/* XKPHYS */
+#define MIPS_CAVIUM_XKPHYS_WRITE	   2011	/* XKPHYS */
+
+static CVMX_SHARED int32_t warn_count;
+
+/**
+ * This function performs some default initialization of the Octeon executive.  It initializes
+ * the cvmx_bootmem memory allocator with the list of physical memory shared by the bootloader.
+ * This function should be called on all cores that will use the bootmem allocator.
+ * Applications which require a different configuration can replace this function with a suitable application
+ * specific one.
+ *
+ * @return 0 on success
+ *         -1 on failure
+ */
+int cvmx_user_app_init(void)
+{
+    return 0;
+}
+
+
+/**
+ * Simulator magic is not supported in user mode under Linux.
+ * This version of simprintf simply calls the underlying C
+ * library printf for output. It also makes sure that two
+ * calls to simprintf provide atomic output.
+ *
+ * @param fmt    Format string in the same format as printf.
+ */
+void simprintf(const char *fmt, ...)
+{
+    CVMX_SHARED static cvmx_spinlock_t simprintf_lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER;
+    va_list ap;
+
+    cvmx_spinlock_lock(&simprintf_lock);
+    printf("SIMPRINTF(%d): ", (int)cvmx_get_core_num());
+    va_start(ap, fmt);
+    vprintf(fmt, ap);
+    va_end(ap);
+    cvmx_spinlock_unlock(&simprintf_lock);
+}
+
+
+/**
+ * Setup the CVMX_SHARED data section to be shared across
+ * all processors running this application. A memory mapped
+ * region is allocated using shm_open and mmap. The current
+ * contents of the CVMX_SHARED section are copied into the
+ * region. Then the new region is remapped to replace the
+ * existing CVMX_SHARED data.
+ *
+ * This function will display a message and abort the
+ * application under any error conditions. The Linux tmpfs
+ * filesystem must be mounted under /dev/shm.
+ */
+static void setup_cvmx_shared(void)
+{
+    const char *SHM_NAME = "cvmx_shared";
+    unsigned long shared_size = &__cvmx_shared_end - &__cvmx_shared_start;
+    int fd;
+
+    /* If there isn't and shared data we can skip all this */
+    if (shared_size)
+    {
+        char shm_name[30];
+        printf("CVMX_SHARED: %p-%p\n", &__cvmx_shared_start, &__cvmx_shared_end);
+
+#ifdef __UCLIBC__
+	const char *defaultdir = "/dev/shm/";
+	struct statfs f;
+	int pid;
+	/* The canonical place is /dev/shm. */
+	if (statfs (defaultdir, &f) == 0)
+	{
+	    pid = getpid();
+	    sprintf (shm_name, "%s%s-%d", defaultdir, SHM_NAME, pid);
+	}
+	else
+	{
+	    perror("/dev/shm is not mounted");
+	    exit(-1);
+	}
+
+	/* shm_open(), shm_unlink() are not implemented in uClibc. Do the
+	   same thing using open() and close() system calls.  */
+	fd = open (shm_name, O_RDWR | O_CREAT | O_TRUNC, 0);
+
+	if (fd < 0)
+	{
+	    perror("Failed to open CVMX_SHARED(shm_name)");
+	    exit(errno);
+	}
+
+	unlink (shm_name);
+#else
+	sprintf(shm_name, "%s-%d", SHM_NAME, getpid());
+        /* Open a new shared memory region for use as CVMX_SHARED */
+        fd = shm_open(shm_name, O_RDWR | O_CREAT | O_TRUNC, 0);
+        if (fd <0)
+        {
+            perror("Failed to setup CVMX_SHARED(shm_open)");
+            exit(errno);
+        }
+
+        /* We don't want the file on the filesystem. Immediately unlink it so
+            another application can create its own shared region */
+        shm_unlink(shm_name);
+#endif
+
+        /* Resize the region to match the size of CVMX_SHARED */
+        ftruncate(fd, shared_size);
+
+        /* Map the region into some random location temporarily so we can
+            copy the shared data to it */
+        void *ptr = mmap(NULL, shared_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+        if (ptr == NULL)
+        {
+            perror("Failed to setup CVMX_SHARED(mmap copy)");
+            exit(errno);
+        }
+
+        /* Copy CVMX_SHARED to the new shared region so we don't lose
+            initializers */
+        memcpy(ptr, &__cvmx_shared_start, shared_size);
+        munmap(ptr, shared_size);
+
+        /* Remap the shared region to replace the old CVMX_SHARED region */
+        ptr = mmap(&__cvmx_shared_start, shared_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, fd, 0);
+        if (ptr == NULL)
+        {
+            perror("Failed to setup CVMX_SHARED(mmap final)");
+            exit(errno);
+        }
+
+        /* Once mappings are setup, the file handle isn't needed anymore */
+        close(fd);
+    }
+}
+
+
+/**
+ * Shutdown and free the shared CVMX_SHARED region setup by
+ * setup_cvmx_shared.
+ */
+static void shutdown_cvmx_shared(void)
+{
+    unsigned long shared_size = &__cvmx_shared_end - &__cvmx_shared_start;
+    if (shared_size)
+        munmap(&__cvmx_shared_start, shared_size);
+}
+
+
+/**
+ * Setup access to the CONFIG_CAVIUM_RESERVE32 memory section
+ * created by the kernel. This memory is used for shared
+ * hardware buffers with 32 bit userspace applications.
+ */
+static void setup_reserve32(void)
+{
+    if (linux_mem32_min && linux_mem32_max)
+    {
+        int region_size = linux_mem32_max - linux_mem32_min + 1;
+        int mmap_flags = MAP_SHARED;
+        void *linux_mem32_base_ptr = NULL;
+
+        /* Although not strictly necessary, we are going to mmap() the wired
+            TLB region so it is in the process page tables. These pages will
+            never fault in, but they will allow GDB to access the wired
+            region. We need the mappings to exactly match the wired TLB
+            entry. */
+        if (linux_mem32_wired)
+        {
+            mmap_flags |= MAP_FIXED;
+            linux_mem32_base_ptr = CASTPTR(void, (1ull<<31) - region_size);
+        }
+
+        int fd = open("/dev/mem", O_RDWR);
+        if (fd < 0)
+        {
+            perror("ERROR opening /dev/mem");
+            exit(-1);
+        }
+
+        linux_mem32_base_ptr = mmap64(linux_mem32_base_ptr,
+                                          region_size,
+                                          PROT_READ | PROT_WRITE,
+                                          mmap_flags,
+                                          fd,
+                                          linux_mem32_min);
+        close(fd);
+
+        if (MAP_FAILED == linux_mem32_base_ptr)
+        {
+            perror("Error mapping reserve32");
+            exit(-1);
+        }
+
+        linux_mem32_offset = CAST64(linux_mem32_base_ptr) - linux_mem32_min;
+    }
+}
+
+
+/**
+ * Main entrypoint of the application. Here we setup shared
+ * memory and fork processes for each cpu. This simulates the
+ * normal simple executive environment of one process per
+ * cpu core.
+ *
+ * @param argc   Number of command line arguments
+ * @param argv   The command line arguments
+ * @return Return value for the process
+ */
+int main(int argc, const char *argv[])
+{
+    CVMX_SHARED static cvmx_spinlock_t mask_lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER;
+    CVMX_SHARED static int32_t pending_fork;
+    unsigned long cpumask;
+    unsigned long cpu;
+    int lastcpu = 0;
+
+    cvmx_sysinfo_linux_userspace_initialize();
+
+    if (sizeof(void*) == 4)
+    {
+        if (linux_mem32_min)
+            setup_reserve32();
+        else
+        {
+            printf("\nFailed to access 32bit shared memory region. Most likely the Kernel\n"
+                   "has not been configured for 32bit shared memory access. Check the\n"
+                   "kernel configuration.\n"
+                   "Aborting...\n\n");
+            exit(-1);
+        }
+    }
+
+    setup_cvmx_shared();
+    cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_ptr);
+
+    /* Check to make sure the Chip version matches the configured version */
+    octeon_model_version_check(cvmx_get_proc_id());
+
+    /* Get the list of logical cpus we should run on */
+    if (sched_getaffinity(0, sizeof(cpumask), (cpu_set_t*)&cpumask))
+    {
+        perror("sched_getaffinity failed");
+        exit(errno);
+    }
+
+    cvmx_sysinfo_t *system_info = cvmx_sysinfo_get();
+
+    cvmx_atomic_set32(&pending_fork, 1);
+    for (cpu=0; cpu<16; cpu++)
+    {
+        if (cpumask & (1<<cpu))
+        {
+            /* Turn off the bit for this CPU number. We've counted him */
+            cpumask ^= (1<<cpu);
+            /* If this is the last CPU to run on, use this process instead of forking another one */
+            if (cpumask == 0)
+            {
+                lastcpu = 1;
+                break;
+            }
+            /* Increment the number of CPUs running this app */
+            cvmx_atomic_add32(&pending_fork, 1);
+            /* Flush all IO streams before the fork. Otherwise any buffered
+                data in the C library will be duplicated. This results in
+                duplicate output from a single print */
+            fflush(NULL);
+            /* Fork a process for the new CPU */
+            int pid = fork();
+            if (pid == 0)
+            {
+                break;
+            }
+            else if (pid == -1)
+            {
+                perror("Fork failed");
+                exit(errno);
+            }
+        }
+    }
+
+    /* Set affinity to lock me to the correct CPU */
+    cpumask = (1<<cpu);
+    if (sched_setaffinity(0, sizeof(cpumask), (cpu_set_t*)&cpumask))
+    {
+        perror("sched_setaffinity failed");
+        exit(errno);
+    }
+
+    cvmx_spinlock_lock(&mask_lock);
+    system_info->core_mask |= 1<<cvmx_get_core_num();
+    cvmx_atomic_add32(&pending_fork, -1);
+    if (cvmx_atomic_get32(&pending_fork) == 0)
+        cvmx_dprintf("Active coremask = 0x%x\n", system_info->core_mask);
+    if (lastcpu)
+        system_info->init_core = cvmx_get_core_num();
+    cvmx_spinlock_unlock(&mask_lock);
+
+    /* Spinning waiting for forks to complete */
+    while (cvmx_atomic_get32(&pending_fork)) {}
+
+    cvmx_coremask_barrier_sync(system_info->core_mask);
+
+    int ret = sysmips(MIPS_CAVIUM_XKPHYS_WRITE, getpid(), 3, 0);
+    if (ret != 0) {
+	 int32_t w = cvmx_atomic_fetch_and_add32(&warn_count, 1);
+	 if (!w) {
+	      switch(errno) {
+	      case EINVAL:
+		   perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed.\n"
+			  "  Did you configure your kernel with both:\n"
+			  "     CONFIG_CAVIUM_OCTEON_USER_MEM_PER_PROCESS *and*\n"
+			  "     CONFIG_CAVIUM_OCTEON_USER_IO_PER_PROCESS?");
+		   break;
+	      case EPERM:
+		   perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed.\n"
+			  "  Are you running as root?");
+		   break;
+	      default:
+		   perror("sysmips(MIPS_CAVIUM_XKPHYS_WRITE) failed");
+		   break;
+	      }
+	 }
+    }
+
+    int result = appmain(argc, argv);
+
+    /* Wait for all forks to complete. This needs to be the core that started
+        all of the forks. It may not be the lowest numbered core! */
+    if (cvmx_get_core_num() == system_info->init_core)
+    {
+        int num_waits;
+        CVMX_POP(num_waits, system_info->core_mask);
+        num_waits--;
+        while (num_waits--)
+        {
+            if (wait(NULL) == -1)
+                perror("CVMX: Wait for forked child failed\n");
+        }
+    }
+
+    shutdown_cvmx_shared();
+
+    return result;
+}
diff --git a/cvmx-app-init.c b/cvmx-app-init.c
new file mode 100644
index 0000000000000..87692186a4953
--- /dev/null
+++ b/cvmx-app-init.c
@@ -0,0 +1,616 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include <octeon-app-init.h>
+#include "cvmx-sysinfo.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-uart.h"
+#include "cvmx-ciu.h"
+#include "cvmx-coremask.h"
+#include "cvmx-core.h"
+#include "cvmx-interrupt.h"
+#include "cvmx-ebt3000.h"
+#include "../../bootloader/u-boot/include/octeon_mem_map.h"
+
+int cvmx_debug_uart;
+
+/**
+ * @file
+ *
+ * Main entry point for all simple executive based programs.
+ */
+
+
+extern void cvmx_interrupt_initialize(void);
+
+
+
+/**
+ * Main entry point for all simple executive based programs.
+ * This is the first C function called. It completes
+ * initialization, calls main, and performs C level cleanup.
+ *
+ * @param app_desc_addr
+ *               Address of the application description structure passed
+ *               brom the boot loader.
+ */
+EXTERN_ASM void __cvmx_app_init(uint64_t app_desc_addr);
+
+
+/**
+ * Set up sysinfo structure from boot descriptor versions 6 and higher.
+ * In these versions, the interesting data in not in the boot info structure
+ * defined by the toolchain, but is in the cvmx_bootinfo structure defined in
+ * the simple exec.
+ *
+ * @param app_desc_ptr
+ *               pointer to boot descriptor block
+ *
+ * @param sys_info_ptr
+ *               pointer to sysinfo structure to fill in
+ */
+static void process_boot_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr, cvmx_sysinfo_t *sys_info_ptr)
+{
+    cvmx_bootinfo_t *cvmx_bootinfo_ptr = CASTPTR(cvmx_bootinfo_t, app_desc_ptr->cvmx_desc_vaddr);
+
+    /* copy application information for simple exec use */
+    /* Populate the sys_info structure from the boot descriptor block created by the bootloader.
+    ** The boot descriptor block is put in the top of the heap, so it will be overwritten when the
+    ** heap is fully used.  Information that is to be used must be copied before that.
+    ** Applications should only use the sys_info structure, not the boot descriptor
+    */
+    if (cvmx_bootinfo_ptr->major_version == 1)
+    {
+        sys_info_ptr->core_mask = cvmx_bootinfo_ptr->core_mask;
+        sys_info_ptr->heap_base = cvmx_bootinfo_ptr->heap_base;
+        sys_info_ptr->heap_size = cvmx_bootinfo_ptr->heap_end - cvmx_bootinfo_ptr->heap_base;
+        sys_info_ptr->stack_top = cvmx_bootinfo_ptr->stack_top;
+        sys_info_ptr->stack_size = cvmx_bootinfo_ptr->stack_size;
+        sys_info_ptr->init_core = cvmx_get_core_num();
+        sys_info_ptr->phy_mem_desc_ptr = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, cvmx_bootinfo_ptr->phy_mem_desc_addr));
+        sys_info_ptr->exception_base_addr = cvmx_bootinfo_ptr->exception_base_addr;
+        sys_info_ptr->cpu_clock_hz  = cvmx_bootinfo_ptr->eclock_hz;
+        sys_info_ptr->dram_data_rate_hz  = cvmx_bootinfo_ptr->dclock_hz * 2;
+
+        sys_info_ptr->board_type = cvmx_bootinfo_ptr->board_type;
+        sys_info_ptr->board_rev_major = cvmx_bootinfo_ptr->board_rev_major;
+        sys_info_ptr->board_rev_minor = cvmx_bootinfo_ptr->board_rev_minor;
+        memcpy(sys_info_ptr->mac_addr_base, cvmx_bootinfo_ptr->mac_addr_base, 6);
+        sys_info_ptr->mac_addr_count = cvmx_bootinfo_ptr->mac_addr_count;
+        memcpy(sys_info_ptr->board_serial_number, cvmx_bootinfo_ptr->board_serial_number, CVMX_BOOTINFO_OCTEON_SERIAL_LEN);
+        sys_info_ptr->console_uart_num = 0;
+        if (cvmx_bootinfo_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1)
+            sys_info_ptr->console_uart_num = 1;
+
+        if (cvmx_bootinfo_ptr->dram_size > 16*1024*1024)
+            sys_info_ptr->system_dram_size = (uint64_t)cvmx_bootinfo_ptr->dram_size;  /* older bootloaders incorrectly gave this in bytes, so don't convert */
+        else
+            sys_info_ptr->system_dram_size = (uint64_t)cvmx_bootinfo_ptr->dram_size * 1024 * 1024;  /* convert from Megabytes to bytes */
+        if (cvmx_bootinfo_ptr->minor_version >= 1)
+        {
+            sys_info_ptr->compact_flash_common_base_addr = cvmx_bootinfo_ptr->compact_flash_common_base_addr;
+            sys_info_ptr->compact_flash_attribute_base_addr = cvmx_bootinfo_ptr->compact_flash_attribute_base_addr;
+            sys_info_ptr->led_display_base_addr = cvmx_bootinfo_ptr->led_display_base_addr;
+        }
+        else if (sys_info_ptr->board_type == CVMX_BOARD_TYPE_EBT3000 ||
+                 sys_info_ptr->board_type == CVMX_BOARD_TYPE_EBT5800)
+        {
+            /* Default these variables so that users of structure can be the same no
+            ** matter what version fo boot info block the bootloader passes */
+            sys_info_ptr->compact_flash_common_base_addr = 0x1d000000 + 0x800;
+            sys_info_ptr->compact_flash_attribute_base_addr = 0x1d010000;
+            if (sys_info_ptr->board_rev_major == 1)
+                sys_info_ptr->led_display_base_addr = 0x1d020000;
+            else
+                sys_info_ptr->led_display_base_addr = 0x1d020000 + 0xf8;
+        }
+        else
+        {
+            sys_info_ptr->compact_flash_common_base_addr = 0;
+            sys_info_ptr->compact_flash_attribute_base_addr = 0;
+            sys_info_ptr->led_display_base_addr = 0;
+        }
+
+        if (cvmx_bootinfo_ptr->minor_version >= 2)
+        {
+            sys_info_ptr->dfa_ref_clock_hz = cvmx_bootinfo_ptr->dfa_ref_clock_hz;
+            sys_info_ptr->bootloader_config_flags = cvmx_bootinfo_ptr->config_flags;
+        }
+        else
+        {
+            sys_info_ptr->dfa_ref_clock_hz = 0;
+            sys_info_ptr->bootloader_config_flags = 0;
+            if (app_desc_ptr->flags & OCTEON_BL_FLAG_DEBUG)
+                sys_info_ptr->bootloader_config_flags |= CVMX_BOOTINFO_CFG_FLAG_DEBUG;
+            if (app_desc_ptr->flags & OCTEON_BL_FLAG_NO_MAGIC)
+                sys_info_ptr->bootloader_config_flags |= CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC;
+        }
+
+    }
+    else
+    {
+        printf("ERROR: Incompatible CVMX descriptor passed by bootloader: %d.%d\n",
+               (int)cvmx_bootinfo_ptr->major_version, (int)cvmx_bootinfo_ptr->minor_version);
+        while (1);
+    }
+}
+
+
+/**
+ * Interrupt handler for debugger Control-C interrupts.
+ *
+ * @param irq_number IRQ interrupt number
+ * @param registers  CPU registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+static void process_debug_interrupt(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    int uart = irq_number - CVMX_IRQ_UART0;
+    cvmx_uart_lsr_t lsrval;
+
+    /* Check for a Control-C interrupt from the debugger. This loop will eat
+        all input received on the uart */
+    lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart));
+    while (lsrval.s.dr)
+    {
+        int c = cvmx_read_csr(CVMX_MIO_UARTX_RBR(uart));
+        if (c == '\003')
+        {
+            register uint64_t tmp;
+            fflush(stderr);
+            fflush(stdout);
+            /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
+                set the MCD0 to be not masked by this core so we know
+                the signal is received by someone */
+            asm volatile (
+                "dmfc0 %0, $22\n"
+                "ori   %0, %0, 0x1110\n"
+                "dmtc0 %0, $22\n"
+                : "=r" (tmp));
+        }
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart));
+    }
+}
+
+/**
+ * Interrupt handler for calling exit on Control-C interrupts.
+ *
+ * @param irq_number IRQ interrupt number
+ * @param registers  CPU registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+static void process_break_interrupt(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    /* Exclude new functionality when building with older toolchains */
+#if OCTEON_APP_INIT_H_VERSION >= 3
+    int uart = irq_number - CVMX_IRQ_UART0;
+    cvmx_uart_lsr_t lsrval;
+
+    /* Check for a Control-C interrupt from the console. This loop will eat
+        all input received on the uart */
+    lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart));
+    while (lsrval.s.dr)
+    {
+        int c = cvmx_read_csr(CVMX_MIO_UARTX_RBR(uart));
+        if (c == '\003')
+        {
+            register uint64_t tmp;
+
+	    /* Wait for an another Control-C if right now we have no
+	       access to the console.  After this point we hold the
+	       lock and use a different lock to synchronize between
+	       the memfile dumps from different cores.  As a
+	       consequence regular printfs *don't* work after this
+	       point! */
+	    if (__octeon_uart_trylock () == 1)
+		return;
+
+            /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also
+	       set the MCD0 to be not masked by this core so we know
+	       the signal is received by someone */
+            asm volatile (
+                "dmfc0 %0, $22\n"
+                "ori   %0, %0, 0x1110\n"
+                "dmtc0 %0, $22\n"
+                : "=r" (tmp));
+        }
+        lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(uart));
+    }
+#endif
+}
+
+/**
+ * This is the debug exception handler with "break".  Before calling exit to
+ * dump the profile-feedback output it releases the lock on the console.
+ * This way if there is buffered data in stdout it can still be flushed.
+ * stdio is required to flush all output during an fread.
+ */
+
+static void exit_on_break(void)
+{
+#if OCTEON_APP_INIT_H_VERSION >= 4
+    unsigned int coremask = cvmx_sysinfo_get()->core_mask;
+
+    cvmx_coremask_barrier_sync(coremask);
+    if (cvmx_coremask_first_core(coremask))
+      __octeon_uart_unlock();
+#endif
+
+    exit(0);
+}
+
+/* Add string signature to applications so that we can easily tell what
+** Octeon revision they were compiled for. Don't make static to avoid unused
+** variable warning. */
+#define xstr(s) str(s)
+#define str(s) #s
+
+int octeon_model_version_check(uint32_t chip_id);
+
+#define OMS xstr(OCTEON_MODEL)
+char octeon_rev_signature[] =
+#ifdef USE_RUNTIME_MODEL_CHECKS
+    "Compiled for runtime Octeon model checking";
+#else
+    "Compiled for Octeon processor id: "OMS;
+#endif
+
+void __cvmx_app_init(uint64_t app_desc_addr)
+{
+    /* App descriptor used by bootloader */
+    octeon_boot_descriptor_t *app_desc_ptr = CASTPTR(octeon_boot_descriptor_t, app_desc_addr);
+
+    /* app info structure used by the simple exec */
+    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+
+    if (cvmx_coremask_first_core(app_desc_ptr->core_mask))
+    {
+        /* do once per application setup  */
+        if (app_desc_ptr->desc_version < 6)
+        {
+            printf("Obsolete bootloader, can't run application\n");
+            while (1)
+                ;
+        }
+        else
+        {
+            /* Handle all newer versions here.... */
+            if (app_desc_ptr->desc_version > 7)
+            {
+                printf("Warning: newer boot descripter version than expected\n");
+            }
+            process_boot_desc_ver_6(app_desc_ptr,sys_info_ptr);
+
+        }
+    }
+    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+
+    /* All cores need to enable MCD0 signals if the debugger flag is set */
+    if (sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG)
+    {
+        /* Set all cores to stop on MCD0 signals */
+        uint64_t tmp;
+        asm volatile(
+            "dmfc0 %0, $22, 0\n"
+            "or %0, %0, 0x1100\n"
+            "dmtc0 %0, $22, 0\n" : "=r" (tmp));
+    }
+
+    cvmx_interrupt_initialize();
+
+    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+    {
+        /* Check to make sure the Chip version matches the configured version */
+        uint32_t chip_id = cvmx_get_proc_id();
+	int debugflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG;
+	int breakflag = sys_info_ptr->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_BREAK;
+	int uart;
+
+        /* Intialize the bootmem allocator with the descriptor that was provided by
+        ** the bootloader
+        ** IMPORTANT:  All printfs must happen after this since PCI console uses named
+        ** blocks.
+        */
+        cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_ptr);
+
+        /* Make sure we can properly run on this chip */
+        octeon_model_version_check(chip_id);
+
+	/* Default to the second uart port.  Set this even if debug was
+	   not passed.  The idea is that if the program crashes one would
+	   be able to break in on uart1 even without debug.  */
+	cvmx_debug_uart = 1;
+        /* If the debugger flag is set, setup the uart Control-C interrupt
+            handler */
+        if (debugflag)
+        {
+            /* Search through the arguments for a debug=X */
+            unsigned int i;
+            for (i=0; i<app_desc_ptr->argc; i++)
+            {
+                const char *argv = CASTPTR(const char, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, app_desc_ptr->argv[i]));
+                if (strncmp(argv, "debug=", 6) == 0)
+                {
+                    /* Use the supplied uart as an override */
+                    cvmx_debug_uart = atoi(argv+6);
+                    break;
+                }
+            }
+	    cvmx_interrupt_register(CVMX_IRQ_UART0+cvmx_debug_uart, process_debug_interrupt, NULL);
+	    uart = cvmx_debug_uart;
+	}
+	else if (breakflag)
+	{
+            unsigned int i;
+	    int32_t *trampoline = CASTPTR(int32_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, BOOTLOADER_DEBUG_TRAMPOLINE));
+	    /* Default to the first uart port. */
+	    uart = 0;
+
+            /* Search through the arguments for a break=X */
+            for (i = 0; i < app_desc_ptr->argc; i++)
+            {
+                const char *argv = CASTPTR(const char, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, app_desc_ptr->argv[i]));
+                if (strncmp(argv, "break=", 6) == 0)
+                {
+                    /* Use the supplied uart as an override */
+                    uart = atoi(argv+6);
+                    break;
+                }
+            }
+
+	    /* On debug exception, call exit_on_break from all cores. */
+	    *trampoline = (int32_t)(long)&exit_on_break;
+	    cvmx_interrupt_register(CVMX_IRQ_UART0 + uart, process_break_interrupt, NULL);
+	}
+	if (debugflag || breakflag)
+	{
+            /* Enable uart interrupts for debugger Control-C processing */
+            cvmx_uart_ier_t ier;
+            ier.u64 = cvmx_read_csr(CVMX_MIO_UARTX_IER(uart));
+            ier.s.erbfi = 1;
+            cvmx_write_csr(CVMX_MIO_UARTX_IER(uart), ier.u64);
+
+            cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0+uart);
+        }
+    }
+
+    /* Clear BEV now that we have installed exception handlers. */
+    uint64_t tmp;
+    asm volatile (
+               "   .set push                  \n"
+               "   .set mips64                  \n"
+               "   .set noreorder               \n"
+               "   .set noat               \n"
+               "   mfc0 %[tmp], $12, 0          \n"
+               "   li   $at, 1 << 22            \n"
+               "   not  $at, $at                \n"
+               "   and  %[tmp], $at             \n"
+               "   mtc0 %[tmp], $12, 0          \n"
+               "   .set pop                  \n"
+                  : [tmp] "=&r" (tmp) : );
+
+    /* Set all cores to stop on MCD0 signals */
+    asm volatile(
+        "dmfc0 %0, $22, 0\n"
+        "or %0, %0, 0x1100\n"
+        "dmtc0 %0, $22, 0\n" : "=r" (tmp));
+
+    CVMX_SYNC;
+    /* Synchronise all cores at this point */
+    cvmx_coremask_barrier_sync(app_desc_ptr->core_mask);
+
+}
+
+int cvmx_user_app_init(void)
+{
+    uint64_t bist_val;
+    uint64_t mask;
+    int bist_errors = 0;
+    uint64_t tmp;
+    uint64_t base_addr;
+
+
+    /* Put message on LED display */
+    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+      ebt3000_str_write("CVMX    ");
+
+    /* Check BIST results for COP0 registers, some values only meaningful in pass 2 */
+    CVMX_MF_CACHE_ERR(bist_val);
+    mask = (1ULL<<32) | (1ULL<<33) | (1ULL<<34) | (1ULL<<35) | (1ULL<<36);
+    bist_val &= mask;
+    if (bist_val)
+    {
+        printf("BIST FAILURE: COP0_CACHE_ERR: 0x%llx\n", (unsigned long long)bist_val);
+        bist_errors++;
+    }
+    /* Clear parity error bits */
+    CVMX_MF_CACHE_ERR(bist_val);
+    bist_val &= ~0x7ull;
+    CVMX_MT_CACHE_ERR(bist_val);
+
+
+    mask = 0xfc00000000000000ull;
+    CVMX_MF_CVM_MEM_CTL(bist_val);
+    bist_val &=  mask;
+    if (bist_val)
+    {
+        printf("BIST FAILURE: COP0_CVM_MEM_CTL: 0x%llx\n", (unsigned long long)bist_val);
+        bist_errors++;
+    }
+
+    /* Clear DCACHE parity error bit */
+    bist_val = 0;
+    CVMX_MF_DCACHE_ERR(bist_val);
+
+    mask =     0x18ull;
+    bist_val = cvmx_read_csr(CVMX_L2D_ERR);
+    if (bist_val & mask)
+    {
+        printf("ERROR: ECC error detected in L2 Data, L2D_ERR: 0x%llx\n", (unsigned long long)bist_val);
+        cvmx_write_csr(CVMX_L2D_ERR, bist_val); /* Clear error bits if set */
+    }
+    bist_val = cvmx_read_csr(CVMX_L2T_ERR);
+    if (bist_val & mask)
+    {
+        printf("ERROR: ECC error detected in L2 Tags, L2T_ERR: 0x%llx\n", (unsigned long long)bist_val);
+        cvmx_write_csr(CVMX_L2T_ERR, bist_val); /* Clear error bits if set */
+    }
+
+
+    /* Set up 4 cache lines of local memory, make available from Kernel space */
+    CVMX_MF_CVM_MEM_CTL(tmp);
+    tmp &= ~0x1ffull;
+    tmp |= 0x104ull;
+    CVMX_MT_CVM_MEM_CTL(tmp);
+
+
+#if CVMX_USE_1_TO_1_TLB_MAPPINGS
+
+    /* Check to see if the bootloader is indicating that the application is outside
+    ** of the 0x10000000 0x20000000 range, in which case we can't use 1-1 mappings */
+    if (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING)
+    {
+        printf("ERROR: 1-1 TLB mappings configured and oversize application loaded.\n");
+        printf("ERROR: Either 1-1 TLB mappings must be disabled or application size reduced.\n");
+        while (1)
+            ;
+    }
+
+
+    /* Create 1-1 Mappings for all DRAM up to 8 gigs, excluding the low 1 Megabyte.  This area
+    ** is reserved for the bootloader and exception vectors.  By not mapping this area, NULL pointer
+    ** dereferences will be caught with TLB exceptions.  Exception handlers should be written
+    ** using XKPHYS or KSEG0 addresses. */
+#if CVMX_NULL_POINTER_PROTECT
+    /* Exclude low 1 MByte from mapping to detect NULL pointer accesses.
+    ** The only down side of this is it uses more TLB mappings */
+    cvmx_core_add_fixed_tlb_mapping_bits(0x0, 0x0, 0x100000  | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, CVMX_TLB_PAGEMASK_1M);
+    cvmx_core_add_fixed_tlb_mapping(0x200000, 0x200000, 0x300000, CVMX_TLB_PAGEMASK_1M);
+    cvmx_core_add_fixed_tlb_mapping(0x400000, 0x400000, 0x500000, CVMX_TLB_PAGEMASK_1M);
+    cvmx_core_add_fixed_tlb_mapping(0x600000, 0x600000, 0x700000, CVMX_TLB_PAGEMASK_1M);
+
+    cvmx_core_add_fixed_tlb_mapping(0x800000,  0x800000,  0xC00000, CVMX_TLB_PAGEMASK_4M);
+    cvmx_core_add_fixed_tlb_mapping(0x1000000, 0x1000000, 0x1400000, CVMX_TLB_PAGEMASK_4M);
+    cvmx_core_add_fixed_tlb_mapping(0x1800000, 0x1800000, 0x1c00000, CVMX_TLB_PAGEMASK_4M);
+
+    cvmx_core_add_fixed_tlb_mapping(0x2000000, 0x2000000, 0x3000000, CVMX_TLB_PAGEMASK_16M);
+    cvmx_core_add_fixed_tlb_mapping(0x4000000, 0x4000000, 0x5000000, CVMX_TLB_PAGEMASK_16M);
+    cvmx_core_add_fixed_tlb_mapping(0x6000000, 0x6000000, 0x7000000, CVMX_TLB_PAGEMASK_16M);
+#else
+    /* Map entire low 128 Megs, including 0x0 */
+    cvmx_core_add_fixed_tlb_mapping(0x0, 0x0, 0x4000000ULL, CVMX_TLB_PAGEMASK_64M);
+#endif
+    cvmx_core_add_fixed_tlb_mapping(0x8000000ULL, 0x8000000ULL, 0xc000000ULL, CVMX_TLB_PAGEMASK_64M);
+
+    /* Create 1-1 mapping for next 256 megs
+    ** bottom page is not valid */
+    cvmx_core_add_fixed_tlb_mapping_bits(0x400000000ULL, 0, 0x410000000ULL  | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, CVMX_TLB_PAGEMASK_256M);
+
+    /* Map from 0.5 up to the installed memory size in 512 MByte chunks.  If this loop runs out of memory,
+    ** the NULL pointer detection can be disabled to free up more TLB entries. */
+    if (cvmx_sysinfo_get()->system_dram_size > 0x20000000ULL)
+    {
+        for (base_addr = 0x20000000ULL; base_addr <= (cvmx_sysinfo_get()->system_dram_size - 0x20000000ULL); base_addr += 0x20000000ULL)
+        {
+            if (0 > cvmx_core_add_fixed_tlb_mapping(base_addr,  base_addr,  base_addr + 0x10000000ULL, CVMX_TLB_PAGEMASK_256M))
+            {
+                printf("ERROR adding 1-1 TLB mapping for address 0x%llx\n", (unsigned long long)base_addr);
+                while (1);    /* Hang here, as expected memory mappings aren't set up if this fails */
+            }
+        }
+    }
+
+
+#endif
+
+
+    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+    cvmx_bootmem_init(sys_info_ptr->phy_mem_desc_ptr);
+
+    return(0);
+}
+
+void __cvmx_app_exit(void)
+{
+    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+    {
+       uint64_t val;
+       uint64_t mask, expected;
+       int bist_errors = 0;
+
+       mask =     0x1ull;
+       expected = 0x0ull;
+       CVMX_MF_DCACHE_ERR(val);
+       val = (val & mask) ^ expected;
+       if (val)
+       {
+           printf("DCACHE Parity error: 0x%llx\n", (unsigned long long)val);
+           bist_errors++;
+       }
+
+       mask =     0x18ull;
+       expected = 0x0ull;
+       val = cvmx_read_csr(CVMX_L2D_ERR);
+       val = (val & mask) ^ expected;
+       if (val)
+       {
+           printf("L2 Parity error: 0x%llx\n", (unsigned long long)val);
+           bist_errors++;
+       }
+
+
+       while (1)
+           ;
+
+    }
+}
+
+
+
diff --git a/cvmx-app-init.h b/cvmx-app-init.h
new file mode 100644
index 0000000000000..cfe65fb4dbbda
--- /dev/null
+++ b/cvmx-app-init.h
@@ -0,0 +1,295 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ * Header file for simple executive application initialization.  This defines
+ * part of the ABI between the bootloader and the application.
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_APP_INIT_H__
+#define __CVMX_APP_INIT_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/* Current major and minor versions of the CVMX bootinfo block that is passed
+** from the bootloader to the application.  This is versioned so that applications
+** can properly handle multiple bootloader versions. */
+#define CVMX_BOOTINFO_MAJ_VER 1
+#define CVMX_BOOTINFO_MIN_VER 2
+
+
+#if (CVMX_BOOTINFO_MAJ_VER == 1)
+#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
+/* This structure is populated by the bootloader.  For binary
+** compatibility the only changes that should be made are
+** adding members to the end of the structure, and the minor
+** version should be incremented at that time.
+** If an incompatible change is made, the major version
+** must be incremented, and the minor version should be reset
+** to 0.
+*/
+typedef struct
+{
+    uint32_t major_version;
+    uint32_t minor_version;
+
+    uint64_t stack_top;
+    uint64_t heap_base;
+    uint64_t heap_end;
+    uint64_t desc_vaddr;
+
+    uint32_t exception_base_addr;
+    uint32_t stack_size;
+    uint32_t flags;
+    uint32_t core_mask;
+    uint32_t dram_size;  /**< DRAM size in megabytes */
+    uint32_t phy_mem_desc_addr;  /**< physical address of free memory descriptor block*/
+    uint32_t debugger_flags_base_addr;  /**< used to pass flags from app to debugger */
+    uint32_t eclock_hz;  /**< CPU clock speed, in hz */
+    uint32_t dclock_hz;  /**< DRAM clock speed, in hz */
+    uint32_t reserved0;
+    uint16_t board_type;
+    uint8_t board_rev_major;
+    uint8_t board_rev_minor;
+    uint16_t reserved1;
+    uint8_t reserved2;
+    uint8_t reserved3;
+    char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+    uint8_t mac_addr_base[6];
+    uint8_t mac_addr_count;
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+    /* Several boards support compact flash on the Octeon boot bus.  The CF
+    ** memory spaces may be mapped to different addresses on different boards.
+    ** These are the physical addresses, so care must be taken to use the correct
+    ** XKPHYS/KSEG0 addressing depending on the application's ABI.
+    ** These values will be 0 if CF is not present */
+    uint64_t compact_flash_common_base_addr;
+    uint64_t compact_flash_attribute_base_addr;
+    /* Base address of the LED display (as on EBT3000 board)
+    ** This will be 0 if LED display not present. */
+    uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+    uint32_t dfa_ref_clock_hz;  /**< DFA reference clock in hz (if applicable)*/
+    uint32_t config_flags;  /**< flags indicating various configuration options.  These flags supercede
+                            ** the 'flags' variable and should be used instead if available */
+#endif
+
+
+} cvmx_bootinfo_t;
+
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST			(1ull << 0)
+#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET		(1ull << 1)
+#define CVMX_BOOTINFO_CFG_FLAG_DEBUG			(1ull << 2)
+#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC			(1ull << 3)
+/* This flag is set if the TLB mappings are not contained in the
+** 0x10000000 - 0x20000000 boot bus region. */
+#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING     (1ull << 4)
+#define CVMX_BOOTINFO_CFG_FLAG_BREAK			(1ull << 5)
+
+#endif /*   (CVMX_BOOTINFO_MAJ_VER == 1) */
+
+
+/* Type defines for board and chip types */
+enum cvmx_board_types_enum {
+    CVMX_BOARD_TYPE_NULL           =  0,
+    CVMX_BOARD_TYPE_SIM            =  1,
+    CVMX_BOARD_TYPE_EBT3000        =  2,
+    CVMX_BOARD_TYPE_KODAMA         =  3,
+    CVMX_BOARD_TYPE_NIAGARA        =  4,	/* Obsolete, no longer supported */
+    CVMX_BOARD_TYPE_NAC38          =  5,	/* formerly NAO38 */
+    CVMX_BOARD_TYPE_THUNDER        =  6,
+    CVMX_BOARD_TYPE_TRANTOR        =  7,	/* Obsolete, no longer supported */
+    CVMX_BOARD_TYPE_EBH3000        =  8,
+    CVMX_BOARD_TYPE_EBH3100        =  9,
+    CVMX_BOARD_TYPE_HIKARI         = 10,
+    CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
+    CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
+    CVMX_BOARD_TYPE_KBP            = 13,
+    CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,  /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
+    CVMX_BOARD_TYPE_EBT5800        = 15,
+    CVMX_BOARD_TYPE_NICPRO2        = 16,
+    CVMX_BOARD_TYPE_EBH5600        = 17,
+    CVMX_BOARD_TYPE_EBH5601        = 18,
+    CVMX_BOARD_TYPE_EBH5200        = 19,
+    CVMX_BOARD_TYPE_BBGW_REF       = 20,
+    CVMX_BOARD_TYPE_NIC_XLE_4G     = 21,
+    CVMX_BOARD_TYPE_EBT5600        = 22,
+    CVMX_BOARD_TYPE_EBH5201        = 23,
+    CVMX_BOARD_TYPE_EBT5200        = 24,
+    CVMX_BOARD_TYPE_CB5600         = 25,
+    CVMX_BOARD_TYPE_CB5601         = 26,
+    CVMX_BOARD_TYPE_CB5200         = 27,
+    CVMX_BOARD_TYPE_GENERIC        = 28,   /* Special 'generic' board type, supports many boards */
+    CVMX_BOARD_TYPE_MAX,
+
+    /* The range from CVMX_BOARD_TYPE_MAX to CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved
+    ** for future SDK use. */
+
+    /* Set aside a range for customer boards.  These numbers are managed
+    ** by Cavium.
+    */
+    CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
+    CVMX_BOARD_TYPE_CUST_WSX16       = 10001,
+    CVMX_BOARD_TYPE_CUST_NS0216      = 10002,
+    CVMX_BOARD_TYPE_CUST_NB5         = 10003,
+    CVMX_BOARD_TYPE_CUST_WMR500      = 10004,
+    CVMX_BOARD_TYPE_CUST_ITB101      = 10005,
+    CVMX_BOARD_TYPE_CUST_NTE102      = 10006,
+    CVMX_BOARD_TYPE_CUST_AGS103      = 10007,
+    CVMX_BOARD_TYPE_CUST_GST104      = 10008,
+    CVMX_BOARD_TYPE_CUST_GCT105      = 10009,
+    CVMX_BOARD_TYPE_CUST_AGS106      = 10010,
+    CVMX_BOARD_TYPE_CUST_SGM107      = 10011,
+    CVMX_BOARD_TYPE_CUST_GCT108      = 10012,
+    CVMX_BOARD_TYPE_CUST_AGS109      = 10013,
+    CVMX_BOARD_TYPE_CUST_GCT110      = 10014,
+    CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
+
+    /* Set aside a range for customer private use.  The SDK won't
+    ** use any numbers in this range. */
+    CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
+    CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
+
+    /* The remaining range is reserved for future use. */
+};
+enum cvmx_chip_types_enum {
+    CVMX_CHIP_TYPE_NULL = 0,
+    CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
+    CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
+    CVMX_CHIP_TYPE_MAX,
+};
+
+/* Compatability alias for NAC38 name change, planned to be removed from SDK 1.7 */
+#define CVMX_BOARD_TYPE_NAO38	CVMX_BOARD_TYPE_NAC38
+
+/* Functions to return string based on type */
+#define ENUM_BRD_TYPE_CASE(x)   case x: return(#x + 16);   /* Skip CVMX_BOARD_TYPE_ */
+static inline const char *cvmx_board_type_to_string(enum cvmx_board_types_enum type)
+{
+    switch (type)
+    {
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
+
+        /* Customer boards listed here */
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
+
+        /* Customer private range */
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
+        ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
+    }
+    return "Unsupported Board";
+}
+
+#define ENUM_CHIP_TYPE_CASE(x)   case x: return(#x + 15);   /* Skip CVMX_CHIP_TYPE */
+static inline const char *cvmx_chip_type_to_string(enum cvmx_chip_types_enum type)
+{
+    switch (type)
+    {
+        ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
+        ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
+        ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
+        ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
+    }
+    return "Unsupported Chip";
+}
+
+
+extern int cvmx_debug_uart;
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_APP_INIT_H__ */
diff --git a/cvmx-asm.h b/cvmx-asm.h
new file mode 100644
index 0000000000000..2406677efca58
--- /dev/null
+++ b/cvmx-asm.h
@@ -0,0 +1,513 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This is file defines ASM primitives for the executive.
+
+ * <hr>$Revision: 42280 $<hr>
+ *
+ *
+ */
+#ifndef __CVMX_ASM_H__
+#define __CVMX_ASM_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* turn the variable name into a string */
+#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
+#define CVMX_TMP_STR2(x) #x
+
+/* other useful stuff */
+#define CVMX_BREAK asm volatile ("break")
+#define CVMX_SYNC asm volatile ("sync" : : :"memory")
+/* String version of SYNCW macro for using in inline asm constructs */
+#define CVMX_SYNCW_STR "syncw\nsyncw\n"
+#ifdef __OCTEON__
+    #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
+    #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : :"memory")
+    #define CVMX_SYNCIOALL asm volatile ("nop")   /* Deprecated, will be removed in future release */
+    /* We actually use two syncw instructions in a row when we need a write
+        memory barrier. This is because the CN3XXX series of Octeons have
+        errata Core-401. This can cause a single syncw to not enforce
+        ordering under very rare conditions. Even if it is rare, better safe
+        than sorry */
+    #define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : :"memory")
+#if defined(VXWORKS) || defined(__linux__)
+    /* Define new sync instructions to be normal SYNC instructions for
+        operating systems that use threads */
+    #define CVMX_SYNCWS CVMX_SYNCW
+    #define CVMX_SYNCS  CVMX_SYNC
+    #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+#else
+    #if defined(CVMX_BUILD_FOR_TOOLCHAIN)
+        /* While building simple exec toolchain, always use syncw to
+           support all Octeon models. */
+        #define CVMX_SYNCWS CVMX_SYNCW
+        #define CVMX_SYNCS  CVMX_SYNC
+        #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+    #else
+        /* Again, just like syncw, we may need two syncws instructions in a row due
+            errata Core-401 */
+        #define CVMX_SYNCWS asm volatile ("syncws\nsyncws\n" : : :"memory")
+        #define CVMX_SYNCS asm volatile ("syncs" : : :"memory")
+        #define CVMX_SYNCWS_STR "syncws\nsyncws\n"
+    #endif
+#endif
+#else
+    /* Not using a Cavium compiler, always use the slower sync so the assembler stays happy */
+    #define CVMX_SYNCIO asm volatile ("nop")   /* Deprecated, will be removed in future release */
+    #define CVMX_SYNCIOBDMA asm volatile ("sync" : : :"memory")
+    #define CVMX_SYNCIOALL asm volatile ("nop")   /* Deprecated, will be removed in future release */
+    #define CVMX_SYNCW asm volatile ("sync" : : :"memory")
+    #define CVMX_SYNCWS CVMX_SYNCW
+    #define CVMX_SYNCS  CVMX_SYNC
+    #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
+#endif
+#define CVMX_SYNCI(address, offset) asm volatile ("synci " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) )
+#define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0)
+#define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128)
+// a normal prefetch
+#define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset)
+// normal prefetches that use the pref instruction
+#define CVMX_PREFETCH_PREFX(X, address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (X))
+#define CVMX_PREFETCH_PREF0(address, offset) CVMX_PREFETCH_PREFX(0, address, offset)
+#define CVMX_PREFETCH_PREF1(address, offset) CVMX_PREFETCH_PREFX(1, address, offset)
+#define CVMX_PREFETCH_PREF6(address, offset) CVMX_PREFETCH_PREFX(6, address, offset)
+#define CVMX_PREFETCH_PREF7(address, offset) CVMX_PREFETCH_PREFX(7, address, offset)
+// prefetch into L1, do not put the block in the L2
+#define CVMX_PREFETCH_NOTL2(address, offset) CVMX_PREFETCH_PREFX(4, address, offset)
+#define CVMX_PREFETCH_NOTL22(address, offset) CVMX_PREFETCH_PREFX(5, address, offset)
+// prefetch into L2, do not put the block in the L1
+#define CVMX_PREFETCH_L2(address, offset) CVMX_PREFETCH_PREFX(28, address, offset)
+// CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable (actually old value or zero) until
+// that byte is stored to (by this or another processor. Note that the value of each byte is not only
+// unpredictable, but may also change again - up until the point when one of the cores stores to the
+// byte.
+#define CVMX_PREPARE_FOR_STORE(address, offset) CVMX_PREFETCH_PREFX(30, address, offset)
+// This is a command headed to the L2 controller to tell it to clear its dirty bit for a
+// block. Basically, SW is telling HW that the current version of the block will not be
+// used.
+#define CVMX_DONT_WRITE_BACK(address, offset) CVMX_PREFETCH_PREFX(29, address, offset)
+
+#define CVMX_ICACHE_INVALIDATE  { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }    // flush stores, invalidate entire icache
+#define CVMX_ICACHE_INVALIDATE2 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } // flush stores, invalidate entire icache
+#define CVMX_DCACHE_INVALIDATE  { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } // complete prefetches, invalidate entire dcache
+
+/* new instruction to make RC4 run faster */
+#define CVMX_BADDU(result, input1, input2) asm ("baddu %[rd],%[rs],%[rt]" : [rd] "=d" (result) : [rs] "d" (input1) , [rt] "d" (input2))
+
+// misc v2 stuff
+#define CVMX_ROTR(result, input1, shiftconst) asm ("rotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1))
+#define CVMX_ROTRV(result, input1, input2) asm ("rotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2))
+#define CVMX_DROTR(result, input1, shiftconst) asm ("drotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1))
+#define CVMX_DROTRV(result, input1, input2) asm ("drotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2))
+#define CVMX_SEB(result, input1) asm ("seb %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_SEH(result, input1) asm ("seh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_DSBH(result, input1) asm ("dsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_DSHD(result, input1) asm ("dshd %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+#define CVMX_WSBH(result, input1) asm ("wsbh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1))
+
+// Endian swap
+#define CVMX_ES64(result, input) \
+        do {\
+        CVMX_DSBH(result, input); \
+        CVMX_DSHD(result, result); \
+        } while (0)
+#define CVMX_ES32(result, input) \
+        do {\
+        CVMX_WSBH(result, input); \
+        CVMX_ROTR(result, result, 16); \
+        } while (0)
+
+
+/* extract and insert - NOTE that pos and len variables must be constants! */
+/* the P variants take len rather than lenm1 */
+/* the M1 variants take lenm1 rather than len */
+#define CVMX_EXTS(result,input,pos,lenm1) asm ("exts %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_EXTSP(result,input,pos,len) CVMX_EXTS(result,input,pos,(len)-1)
+
+#define CVMX_DEXT(result,input,pos,len) asm ("dext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_DEXTM1(result,input,pos,lenm1) CVMX_DEXT(result,input,pos,(lenm1)+1)
+
+#define CVMX_EXT(result,input,pos,len) asm ("ext %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_EXTM1(result,input,pos,lenm1) CVMX_EXT(result,input,pos,(lenm1)+1)
+
+// removed
+// #define CVMX_EXTU(result,input,pos,lenm1) asm ("extu %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input))
+// #define CVMX_EXTUP(result,input,pos,len) CVMX_EXTU(result,input,pos,(len)-1)
+
+#define CVMX_CINS(result,input,pos,lenm1) asm ("cins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : [rs] "d" (input))
+#define CVMX_CINSP(result,input,pos,len) CVMX_CINS(result,input,pos,(len)-1)
+
+#define CVMX_DINS(result,input,pos,len) asm ("dins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result))
+#define CVMX_DINSM1(result,input,pos,lenm1) CVMX_DINS(result,input,pos,(lenm1)+1)
+#define CVMX_DINSC(result,pos,len) asm ("dins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result))
+#define CVMX_DINSCM1(result,pos,lenm1) CVMX_DINSC(result,pos,(lenm1)+1)
+
+#define CVMX_INS(result,input,pos,len) asm ("ins %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result))
+#define CVMX_INSM1(result,input,pos,lenm1) CVMX_INS(result,input,pos,(lenm1)+1)
+#define CVMX_INSC(result,pos,len) asm ("ins %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(len): [rt] "=d" (result): "[rt]" (result))
+#define CVMX_INSCM1(result,pos,lenm1) CVMX_INSC(result,pos,(lenm1)+1)
+
+// removed
+// #define CVMX_INS0(result,input,pos,lenm1) asm("ins0 %[rt],%[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1): [rt] "=d" (result): [rs] "d" (input), "[rt]" (result))
+// #define CVMX_INS0P(result,input,pos,len) CVMX_INS0(result,input,pos,(len)-1)
+// #define CVMX_INS0C(result,pos,lenm1) asm ("ins0 %[rt],$0," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(lenm1) : [rt] "=d" (result) : "[rt]" (result))
+// #define CVMX_INS0CP(result,pos,len) CVMX_INS0C(result,pos,(len)-1)
+
+#define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DCLZ(result, input) asm ("dclz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_CLO(result, input) asm ("clo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DCLO(result, input) asm ("dclo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_POP(result, input) asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+#define CVMX_DPOP(result, input) asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
+
+#ifdef CVMX_ABI_O32
+
+  /* rdhwr $31 is the 64 bit cmvcount register, it needs to be split
+     into one or two (depending on the width of the result) properly
+     sign extended registers.  All other registers are 32 bits wide
+     and already properly sign extended. */
+#  define CVMX_RDHWRX(result, regstr, ASM_STMT) ({			\
+  if (regstr == 31) {							\
+    if (sizeof(result) == 8) {						\
+      ASM_STMT (".set\tpush\n"						\
+		"\t.set\tmips64r2\n"					\
+		"\trdhwr\t%L0,$31\n"					\
+		"\tdsra\t%M0,%L0,32\n"					\
+		"\tsll\t%L0,%L0,0\n"					\
+		"\t.set\tpop": "=d"(result));				\
+    } else {								\
+      unsigned long _v;							\
+      ASM_STMT ("rdhwr\t%0,$31\n"					\
+		"\tsll\t%0,%0,0" : "=d"(_v));				\
+      result = (typeof(result))_v;					\
+    }									\
+  } else {								\
+    unsigned long _v;							\
+    ASM_STMT ("rdhwr\t%0,$" CVMX_TMP_STR(regstr) : "=d"(_v));		\
+    result = (typeof(result))_v;					\
+  }})
+  
+
+
+#  define CVMX_RDHWR(result, regstr) CVMX_RDHWRX(result, regstr, asm volatile)
+#  define CVMX_RDHWRNV(result, regstr) CVMX_RDHWRX(result, regstr, asm)
+#else
+#  define CVMX_RDHWR(result, regstr) asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+#  define CVMX_RDHWRNV(result, regstr) asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
+#endif
+
+// some new cop0-like stuff
+#define CVMX_DI(result) asm volatile ("di %[rt]" : [rt] "=d" (result))
+#define CVMX_DI_NULL asm volatile ("di")
+#define CVMX_EI(result) asm volatile ("ei %[rt]" : [rt] "=d" (result))
+#define CVMX_EI_NULL asm volatile ("ei")
+#define CVMX_EHB asm volatile ("ehb")
+
+/* mul stuff */
+#define CVMX_MTM0(m) asm volatile ("mtm0 %[rs]" : : [rs] "d" (m))
+#define CVMX_MTM1(m) asm volatile ("mtm1 %[rs]" : : [rs] "d" (m))
+#define CVMX_MTM2(m) asm volatile ("mtm2 %[rs]" : : [rs] "d" (m))
+#define CVMX_MTP0(p) asm volatile ("mtp0 %[rs]" : : [rs] "d" (p))
+#define CVMX_MTP1(p) asm volatile ("mtp1 %[rs]" : : [rs] "d" (p))
+#define CVMX_MTP2(p) asm volatile ("mtp2 %[rs]" : : [rs] "d" (p))
+#define CVMX_VMULU(dest,mpcand,accum) asm volatile ("vmulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum))
+#define CVMX_VMM0(dest,mpcand,accum) asm volatile ("vmm0 %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum))
+#define CVMX_V3MULU(dest,mpcand,accum) asm volatile ("v3mulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum))
+
+/* branch stuff */
+// these are hard to make work because the compiler does not realize that the
+// instruction is a branch so may optimize away the label
+// the labels to these next two macros must not include a ":" at the end
+#define CVMX_BBIT1(var, pos, label) asm volatile ("bbit1 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var))
+#define CVMX_BBIT0(var, pos, label) asm volatile ("bbit0 %[rs]," CVMX_TMP_STR(pos) "," CVMX_TMP_STR(label) : : [rs] "d" (var))
+// the label to this macro must include a ":" at the end
+#define CVMX_ASM_LABEL(label) label \
+                             asm volatile (CVMX_TMP_STR(label) : : )
+
+//
+// Low-latency memory stuff
+//
+// set can be 0-1
+#define CVMX_MT_LLM_READ_ADDR(set,val)    asm volatile ("dmtc2 %[rt],0x0400+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_WRITE_ADDR_INTERNAL(set,val)   asm volatile ("dmtc2 %[rt],0x0401+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_READ64_ADDR(set,val)  asm volatile ("dmtc2 %[rt],0x0404+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(set,val) asm volatile ("dmtc2 %[rt],0x0405+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MT_LLM_DATA(set,val)         asm volatile ("dmtc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : : [rt] "d" (val))
+#define CVMX_MF_LLM_DATA(set,val)         asm volatile ("dmfc2 %[rt],0x0402+(8*(" CVMX_TMP_STR(set) "))" : [rt] "=d" (val) : )
+
+
+// load linked, store conditional
+#define CVMX_LL(dest, address, offset) asm volatile ("ll %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) )
+#define CVMX_LLD(dest, address, offset) asm volatile ("lld %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) )
+#define CVMX_SC(srcdest, address, offset) asm volatile ("sc %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) )
+#define CVMX_SCD(srcdest, address, offset) asm volatile ("scd %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) )
+
+// load/store word left/right
+#define CVMX_LWR(srcdest, address, offset) asm volatile ("lwr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) )
+#define CVMX_LWL(srcdest, address, offset) asm volatile ("lwl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) )
+#define CVMX_LDR(srcdest, address, offset) asm volatile ("ldr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) )
+#define CVMX_LDL(srcdest, address, offset) asm volatile ("ldl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) )
+
+#define CVMX_SWR(src, address, offset) asm volatile ("swr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) )
+#define CVMX_SWL(src, address, offset) asm volatile ("swl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) )
+#define CVMX_SDR(src, address, offset) asm volatile ("sdr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) )
+#define CVMX_SDL(src, address, offset) asm volatile ("sdl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) )
+
+
+
+//
+// Useful crypto ASM's
+//
+
+// CRC
+
+#define CVMX_MT_CRC_POLYNOMIAL(val)         asm volatile ("dmtc2 %[rt],0x4200" : : [rt] "d" (val))
+#define CVMX_MT_CRC_IV(val)                 asm volatile ("dmtc2 %[rt],0x0201" : : [rt] "d" (val))
+#define CVMX_MT_CRC_LEN(val)                asm volatile ("dmtc2 %[rt],0x1202" : : [rt] "d" (val))
+#define CVMX_MT_CRC_BYTE(val)               asm volatile ("dmtc2 %[rt],0x0204" : : [rt] "d" (val))
+#define CVMX_MT_CRC_HALF(val)               asm volatile ("dmtc2 %[rt],0x0205" : : [rt] "d" (val))
+#define CVMX_MT_CRC_WORD(val)               asm volatile ("dmtc2 %[rt],0x0206" : : [rt] "d" (val))
+#define CVMX_MT_CRC_DWORD(val)              asm volatile ("dmtc2 %[rt],0x1207" : : [rt] "d" (val))
+#define CVMX_MT_CRC_VAR(val)                asm volatile ("dmtc2 %[rt],0x1208" : : [rt] "d" (val))
+#define CVMX_MT_CRC_POLYNOMIAL_REFLECT(val) asm volatile ("dmtc2 %[rt],0x4210" : : [rt] "d" (val))
+#define CVMX_MT_CRC_IV_REFLECT(val)         asm volatile ("dmtc2 %[rt],0x0211" : : [rt] "d" (val))
+#define CVMX_MT_CRC_BYTE_REFLECT(val)       asm volatile ("dmtc2 %[rt],0x0214" : : [rt] "d" (val))
+#define CVMX_MT_CRC_HALF_REFLECT(val)       asm volatile ("dmtc2 %[rt],0x0215" : : [rt] "d" (val))
+#define CVMX_MT_CRC_WORD_REFLECT(val)       asm volatile ("dmtc2 %[rt],0x0216" : : [rt] "d" (val))
+#define CVMX_MT_CRC_DWORD_REFLECT(val)      asm volatile ("dmtc2 %[rt],0x1217" : : [rt] "d" (val))
+#define CVMX_MT_CRC_VAR_REFLECT(val)        asm volatile ("dmtc2 %[rt],0x1218" : : [rt] "d" (val))
+
+#define CVMX_MF_CRC_POLYNOMIAL(val)         asm volatile ("dmfc2 %[rt],0x0200" : [rt] "=d" (val) : )
+#define CVMX_MF_CRC_IV(val)                 asm volatile ("dmfc2 %[rt],0x0201" : [rt] "=d" (val) : )
+#define CVMX_MF_CRC_IV_REFLECT(val)         asm volatile ("dmfc2 %[rt],0x0203" : [rt] "=d" (val) : )
+#define CVMX_MF_CRC_LEN(val)                asm volatile ("dmfc2 %[rt],0x0202" : [rt] "=d" (val) : )
+
+// MD5 and SHA-1
+
+// pos can be 0-6
+#define CVMX_MT_HSH_DAT(val,pos)    asm volatile ("dmtc2 %[rt],0x0040+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+#define CVMX_MT_HSH_DATZ(pos)       asm volatile ("dmtc2    $0,0x0040+" CVMX_TMP_STR(pos) :                 :               )
+// pos can be 0-14
+#define CVMX_MT_HSH_DATW(val,pos)   asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+#define CVMX_MT_HSH_DATWZ(pos)      asm volatile ("dmtc2    $0,0x0240+" CVMX_TMP_STR(pos) :                 :               )
+#define CVMX_MT_HSH_STARTMD5(val)   asm volatile ("dmtc2 %[rt],0x4047"                   :                 : [rt] "d" (val))
+#define CVMX_MT_HSH_STARTSHA(val)   asm volatile ("dmtc2 %[rt],0x4057"                   :                 : [rt] "d" (val))
+#define CVMX_MT_HSH_STARTSHA256(val)   asm volatile ("dmtc2 %[rt],0x404f"                   :                 : [rt] "d" (val))
+#define CVMX_MT_HSH_STARTSHA512(val)   asm volatile ("dmtc2 %[rt],0x424f"                   :                 : [rt] "d" (val))
+// pos can be 0-3
+#define CVMX_MT_HSH_IV(val,pos)     asm volatile ("dmtc2 %[rt],0x0048+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+// pos can be 0-7
+#define CVMX_MT_HSH_IVW(val,pos)     asm volatile ("dmtc2 %[rt],0x0250+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+
+// pos can be 0-6
+#define CVMX_MF_HSH_DAT(val,pos)    asm volatile ("dmfc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-14
+#define CVMX_MF_HSH_DATW(val,pos)   asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-3
+#define CVMX_MF_HSH_IV(val,pos)     asm volatile ("dmfc2 %[rt],0x0048+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-7
+#define CVMX_MF_HSH_IVW(val,pos)     asm volatile ("dmfc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+
+// 3DES
+
+// pos can be 0-2
+#define CVMX_MT_3DES_KEY(val,pos)   asm volatile ("dmtc2 %[rt],0x0080+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+#define CVMX_MT_3DES_IV(val)        asm volatile ("dmtc2 %[rt],0x0084"                   :                 : [rt] "d" (val))
+#define CVMX_MT_3DES_ENC_CBC(val)   asm volatile ("dmtc2 %[rt],0x4088"                   :                 : [rt] "d" (val))
+#define CVMX_MT_3DES_ENC(val)       asm volatile ("dmtc2 %[rt],0x408a"                   :                 : [rt] "d" (val))
+#define CVMX_MT_3DES_DEC_CBC(val)   asm volatile ("dmtc2 %[rt],0x408c"                   :                 : [rt] "d" (val))
+#define CVMX_MT_3DES_DEC(val)       asm volatile ("dmtc2 %[rt],0x408e"                   :                 : [rt] "d" (val))
+#define CVMX_MT_3DES_RESULT(val)    asm volatile ("dmtc2 %[rt],0x0098"                   :                 : [rt] "d" (val))
+
+// pos can be 0-2
+#define CVMX_MF_3DES_KEY(val,pos)   asm volatile ("dmfc2 %[rt],0x0080+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+#define CVMX_MF_3DES_IV(val)        asm volatile ("dmfc2 %[rt],0x0084"                   : [rt] "=d" (val) :               )
+#define CVMX_MF_3DES_RESULT(val)    asm volatile ("dmfc2 %[rt],0x0088"                   : [rt] "=d" (val) :               )
+
+// KASUMI
+
+// pos can be 0-1
+#define CVMX_MT_KAS_KEY(val,pos)    CVMX_MT_3DES_KEY(val,pos)
+#define CVMX_MT_KAS_ENC_CBC(val)    asm volatile ("dmtc2 %[rt],0x4089"                   :                 : [rt] "d" (val))
+#define CVMX_MT_KAS_ENC(val)        asm volatile ("dmtc2 %[rt],0x408b"                   :                 : [rt] "d" (val))
+#define CVMX_MT_KAS_RESULT(val)     CVMX_MT_3DES_RESULT(val)
+
+// pos can be 0-1
+#define CVMX_MF_KAS_KEY(val,pos)    CVMX_MF_3DES_KEY(val,pos)
+#define CVMX_MF_KAS_RESULT(val)     CVMX_MF_3DES_RESULT(val)
+
+// AES
+
+#define CVMX_MT_AES_ENC_CBC0(val)   asm volatile ("dmtc2 %[rt],0x0108"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_ENC_CBC1(val)   asm volatile ("dmtc2 %[rt],0x3109"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_ENC0(val)       asm volatile ("dmtc2 %[rt],0x010a"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_ENC1(val)       asm volatile ("dmtc2 %[rt],0x310b"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_DEC_CBC0(val)   asm volatile ("dmtc2 %[rt],0x010c"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_DEC_CBC1(val)   asm volatile ("dmtc2 %[rt],0x310d"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_DEC0(val)       asm volatile ("dmtc2 %[rt],0x010e"                   :                 : [rt] "d" (val))
+#define CVMX_MT_AES_DEC1(val)       asm volatile ("dmtc2 %[rt],0x310f"                   :                 : [rt] "d" (val))
+// pos can be 0-3
+#define CVMX_MT_AES_KEY(val,pos)    asm volatile ("dmtc2 %[rt],0x0104+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+// pos can be 0-1
+#define CVMX_MT_AES_IV(val,pos)     asm volatile ("dmtc2 %[rt],0x0102+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+#define CVMX_MT_AES_KEYLENGTH(val)  asm volatile ("dmtc2 %[rt],0x0110"                   :                 : [rt] "d" (val)) // write the keylen
+// pos can be 0-1
+#define CVMX_MT_AES_RESULT(val,pos) asm volatile ("dmtc2 %[rt],0x0100+" CVMX_TMP_STR(pos) :                 : [rt] "d" (val))
+
+// pos can be 0-1
+#define CVMX_MF_AES_RESULT(val,pos) asm volatile ("dmfc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-1
+#define CVMX_MF_AES_IV(val,pos)     asm volatile ("dmfc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+// pos can be 0-3
+#define CVMX_MF_AES_KEY(val,pos)    asm volatile ("dmfc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : [rt] "=d" (val) :               )
+#define CVMX_MF_AES_KEYLENGTH(val)  asm volatile ("dmfc2 %[rt],0x0110"                   : [rt] "=d" (val) :               ) // read the keylen
+#define CVMX_MF_AES_DAT0(val)       asm volatile ("dmfc2 %[rt],0x0111"                   : [rt] "=d" (val) :               ) // first piece of input data
+/* GFM COP2 macros */
+/* index can be 0 or 1 */
+#define CVMX_MF_GFM_MUL(val, index)     asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(index) : [rt] "=d" (val) :               )
+#define CVMX_MF_GFM_POLY(val)           asm volatile ("dmfc2 %[rt],0x025e"                      : [rt] "=d" (val) :               )
+#define CVMX_MF_GFM_RESINP(val, index)  asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(index) : [rt] "=d" (val) :               )
+
+#define CVMX_MT_GFM_MUL(val, index)     asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(index) :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_POLY(val)           asm volatile ("dmtc2 %[rt],0x025e"                      :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_RESINP(val, index)  asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(index) :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_XOR0(val)           asm volatile ("dmtc2 %[rt],0x025c"                      :                 : [rt] "d" (val))
+#define CVMX_MT_GFM_XORMUL1(val)        asm volatile ("dmtc2 %[rt],0x425d"                      :                 : [rt] "d" (val))
+
+
+/* check_ordering stuff */
+#if 0
+#define CVMX_MF_CHORD(dest)         asm volatile ("dmfc2 %[rt],0x400" : [rt] "=d" (dest) : )
+#else
+#define CVMX_MF_CHORD(dest)         CVMX_RDHWR(dest, 30)
+#endif
+
+#if 0
+#define CVMX_MF_CYCLE(dest)         asm volatile ("dmfc0 %[rt],$9,6" : [rt] "=d" (dest) : ) // Use (64-bit) CvmCount register rather than Count
+#else
+#define CVMX_MF_CYCLE(dest)         CVMX_RDHWR(dest, 31) /* reads the current (64-bit) CvmCount value */
+#endif
+
+#define CVMX_MT_CYCLE(src)         asm volatile ("dmtc0 %[rt],$9,6" :: [rt] "d" (src))
+
+#define CVMX_MF_CACHE_ERR(val)            asm volatile ("dmfc0 %[rt],$27,0" :  [rt] "=d" (val):)
+#define CVMX_MF_DCACHE_ERR(val)           asm volatile ("dmfc0 %[rt],$27,1" :  [rt] "=d" (val):)
+#define CVMX_MF_CVM_MEM_CTL(val)          asm volatile ("dmfc0 %[rt],$11,7" :  [rt] "=d" (val):)
+#define CVMX_MF_CVM_CTL(val)              asm volatile ("dmfc0 %[rt],$9,7"  :  [rt] "=d" (val):)
+#define CVMX_MT_CACHE_ERR(val)            asm volatile ("dmtc0 %[rt],$27,0" : : [rt] "d" (val))
+#define CVMX_MT_DCACHE_ERR(val)           asm volatile ("dmtc0 %[rt],$27,1" : : [rt] "d" (val))
+#define CVMX_MT_CVM_MEM_CTL(val)          asm volatile ("dmtc0 %[rt],$11,7" : : [rt] "d" (val))
+#define CVMX_MT_CVM_CTL(val)              asm volatile ("dmtc0 %[rt],$9,7"  : : [rt] "d" (val))
+
+/* Macros for TLB */
+#define CVMX_TLBWI                       asm volatile ("tlbwi" : : )
+#define CVMX_TLBWR                       asm volatile ("tlbwr" : : )
+#define CVMX_TLBR                        asm volatile ("tlbr" : : )
+#define CVMX_MT_ENTRY_HIGH(val)          asm volatile ("dmtc0 %[rt],$10,0" : : [rt] "d" (val))
+#define CVMX_MT_ENTRY_LO_0(val)          asm volatile ("dmtc0 %[rt],$2,0" : : [rt] "d" (val))
+#define CVMX_MT_ENTRY_LO_1(val)          asm volatile ("dmtc0 %[rt],$3,0" : : [rt] "d" (val))
+#define CVMX_MT_PAGEMASK(val)            asm volatile ("mtc0 %[rt],$5,0" : : [rt] "d" (val))
+#define CVMX_MT_PAGEGRAIN(val)           asm volatile ("mtc0 %[rt],$5,1" : : [rt] "d" (val))
+#define CVMX_MT_TLB_INDEX(val)           asm volatile ("mtc0 %[rt],$0,0" : : [rt] "d" (val))
+#define CVMX_MT_TLB_CONTEXT(val)         asm volatile ("dmtc0 %[rt],$4,0" : : [rt] "d" (val))
+#define CVMX_MT_TLB_WIRED(val)           asm volatile ("mtc0 %[rt],$6,0" : : [rt] "d" (val))
+#define CVMX_MT_TLB_RANDOM(val)          asm volatile ("mtc0 %[rt],$1,0" : : [rt] "d" (val))
+#define CVMX_MF_ENTRY_LO_0(val)          asm volatile ("dmfc0 %[rt],$2,0" :  [rt] "=d" (val):)
+#define CVMX_MF_ENTRY_LO_1(val)          asm volatile ("dmfc0 %[rt],$3,0" :  [rt] "=d" (val):)
+#define CVMX_MF_ENTRY_HIGH(val)          asm volatile ("dmfc0 %[rt],$10,0" :  [rt] "=d" (val):)
+#define CVMX_MF_PAGEMASK(val)            asm volatile ("mfc0 %[rt],$5,0" :  [rt] "=d" (val):)
+#define CVMX_MF_PAGEGRAIN(val)           asm volatile ("mfc0 %[rt],$5,1" :  [rt] "=d" (val):)
+#define CVMX_MF_TLB_WIRED(val)           asm volatile ("mfc0 %[rt],$6,0" :  [rt] "=d" (val):)
+#define CVMX_MF_TLB_RANDOM(val)          asm volatile ("mfc0 %[rt],$1,0" :  [rt] "=d" (val):)
+#define TLB_DIRTY   (0x1ULL<<2)
+#define TLB_VALID   (0x1ULL<<1)
+#define TLB_GLOBAL  (0x1ULL<<0)
+
+
+
+/* assembler macros to guarantee byte loads/stores are used */
+/* for an unaligned 16-bit access (these use AT register) */
+/* we need the hidden argument (__a) so that GCC gets the dependencies right */
+#define CVMX_LOADUNA_INT16(result, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("ulh %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset]), "m"(__a[offset + 1])); }
+#define CVMX_LOADUNA_UINT16(result, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("ulhu %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1])); }
+#define CVMX_STOREUNA_INT16(data, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("ush %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : "=m"(__a[offset + 0]), "=m"(__a[offset + 1]): [rsrc] "d" (data), [rbase] "d" (__a)); }
+
+#define CVMX_LOADUNA_INT32(result, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("ulw %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \
+	       [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3])); }
+#define CVMX_STOREUNA_INT32(data, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("usw %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \
+	       "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]) : \
+	       [rsrc] "d" (data), [rbase] "d" (__a)); }
+
+#define CVMX_LOADUNA_INT64(result, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("uld %[rdest], " CVMX_TMP_STR(offset) "(%[rbase])" : [rdest] "=d" (result) : \
+	       [rbase] "d" (__a), "m"(__a[offset + 0]), "m"(__a[offset + 1]), "m"(__a[offset + 2]), "m"(__a[offset + 3]), \
+	       "m"(__a[offset + 4]), "m"(__a[offset + 5]), "m"(__a[offset + 6]), "m"(__a[offset + 7])); }
+#define CVMX_STOREUNA_INT64(data, address, offset) \
+	{ char *__a = (char *)(address); \
+	  asm ("usd %[rsrc], " CVMX_TMP_STR(offset) "(%[rbase])" : \
+	       "=m"(__a[offset + 0]), "=m"(__a[offset + 1]), "=m"(__a[offset + 2]), "=m"(__a[offset + 3]), \
+	       "=m"(__a[offset + 4]), "=m"(__a[offset + 5]), "=m"(__a[offset + 6]), "=m"(__a[offset + 7]) : \
+	       [rsrc] "d" (data), [rbase] "d" (__a)); }
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_ASM_H__ */
diff --git a/cvmx-asx.h b/cvmx-asx.h
new file mode 100644
index 0000000000000..4a49a04b4c894
--- /dev/null
+++ b/cvmx-asx.h
@@ -0,0 +1,66 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the ASX hardware.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_ASX_H__
+#define __CVMX_ASX_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-atomic.h b/cvmx-atomic.h
new file mode 100644
index 0000000000000..6446130be32d7
--- /dev/null
+++ b/cvmx-atomic.h
@@ -0,0 +1,666 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides atomic operations
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+
+#ifndef __CVMX_ATOMIC_H__
+#define __CVMX_ATOMIC_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Atomically adds a signed value to a 32 bit (aligned) memory location.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.  (This should NOT be used for reference counting -
+ * use the standard version instead.)
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ */
+static inline void cvmx_atomic_add32_nosync(int32_t *ptr, int32_t incr)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+    {
+	uint32_t tmp;
+
+        __asm__ __volatile__(
+        ".set noreorder         \n"
+        "1: ll   %[tmp], %[val] \n"
+        "   addu %[tmp], %[inc] \n"
+        "   sc   %[tmp], %[val] \n"
+        "   beqz %[tmp], 1b     \n"
+        "   nop                 \n"
+        ".set reorder           \n"
+        : [val] "+m" (*ptr), [tmp] "=&r" (tmp)
+        : [inc] "r" (incr)
+        : "memory");
+    }
+    else
+    {
+        __asm__ __volatile__(
+        "   saa %[inc], (%[base]) \n"
+        : "+m" (*ptr)
+        : [inc] "r" (incr), [base] "r" (ptr)
+        : "memory");
+    }
+}
+
+/**
+ * Atomically adds a signed value to a 32 bit (aligned) memory location.
+ *
+ * Memory access ordering is enforced before/after the atomic operation,
+ * so no additional 'sync' instructions are required.
+ *
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ */
+static inline void cvmx_atomic_add32(int32_t *ptr, int32_t incr)
+{
+    CVMX_SYNCWS;
+    cvmx_atomic_add32_nosync(ptr, incr);
+    CVMX_SYNCWS;
+}
+
+/**
+ * Atomically sets a 32 bit (aligned) memory location to a value
+ *
+ * @param ptr    address of memory to set
+ * @param value  value to set memory location to.
+ */
+static inline void cvmx_atomic_set32(int32_t *ptr, int32_t value)
+{
+    CVMX_SYNCWS;
+    *ptr = value;
+    CVMX_SYNCWS;
+}
+
+/**
+ * Returns the current value of a 32 bit (aligned) memory
+ * location.
+ *
+ * @param ptr    Address of memory to get
+ * @return Value of the memory
+ */
+static inline int32_t cvmx_atomic_get32(int32_t *ptr)
+{
+    return *(volatile int32_t *)ptr;
+}
+
+/**
+ * Atomically adds a signed value to a 64 bit (aligned) memory location.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.  (This should NOT be used for reference counting -
+ * use the standard version instead.)
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ */
+static inline void cvmx_atomic_add64_nosync(int64_t *ptr, int64_t incr)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+    {
+	uint64_t tmp;
+        __asm__ __volatile__(
+        ".set noreorder         \n"
+        "1: lld  %[tmp], %[val] \n"
+        "   daddu %[tmp], %[inc] \n"
+        "   scd  %[tmp], %[val] \n"
+        "   beqz %[tmp], 1b     \n"
+        "   nop                 \n"
+        ".set reorder           \n"
+        : [val] "+m" (*ptr), [tmp] "=&r" (tmp)
+        : [inc] "r" (incr)
+        : "memory");
+    }
+    else
+    {
+        __asm__ __volatile__(
+        "   saad %[inc], (%[base])  \n"
+        : "+m" (*ptr)
+        : [inc] "r" (incr), [base] "r" (ptr)
+        : "memory");
+    }
+}
+
+/**
+ * Atomically adds a signed value to a 64 bit (aligned) memory location.
+ *
+ * Memory access ordering is enforced before/after the atomic operation,
+ * so no additional 'sync' instructions are required.
+ *
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ */
+static inline void cvmx_atomic_add64(int64_t *ptr, int64_t incr)
+{
+    CVMX_SYNCWS;
+    cvmx_atomic_add64_nosync(ptr, incr);
+    CVMX_SYNCWS;
+}
+
+/**
+ * Atomically sets a 64 bit (aligned) memory location to a value
+ *
+ * @param ptr    address of memory to set
+ * @param value  value to set memory location to.
+ */
+static inline void cvmx_atomic_set64(int64_t *ptr, int64_t value)
+{
+    CVMX_SYNCWS;
+    *ptr = value;
+    CVMX_SYNCWS;
+}
+
+/**
+ * Returns the current value of a 64 bit (aligned) memory
+ * location.
+ *
+ * @param ptr    Address of memory to get
+ * @return Value of the memory
+ */
+static inline int64_t cvmx_atomic_get64(int64_t *ptr)
+{
+    return *(volatile int64_t *)ptr;
+}
+
+/**
+ * Atomically compares the old value with the value at ptr, and if they match,
+ * stores new_val to ptr.
+ * If *ptr and old don't match, function returns failure immediately.
+ * If *ptr and old match, function spins until *ptr updated to new atomically, or
+ *  until *ptr and old no longer match
+ *
+ * Does no memory synchronization.
+ *
+ * @return 1 on success (match and store)
+ *         0 on no match
+ */
+static inline uint32_t cvmx_atomic_compare_and_store32_nosync(uint32_t *ptr, uint32_t old_val, uint32_t new_val)
+{
+    uint32_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: ll   %[tmp], %[val] \n"
+    "   li   %[ret], 0     \n"
+    "   bne  %[tmp], %[old], 2f \n"
+    "   move %[tmp], %[new_val] \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   li   %[ret], 1      \n"
+    "2: nop               \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [old] "r" (old_val), [new_val] "r" (new_val)
+    : "memory");
+
+    return(ret);
+
+}
+
+/**
+ * Atomically compares the old value with the value at ptr, and if they match,
+ * stores new_val to ptr.
+ * If *ptr and old don't match, function returns failure immediately.
+ * If *ptr and old match, function spins until *ptr updated to new atomically, or
+ *  until *ptr and old no longer match
+ *
+ * Does memory synchronization that is required to use this as a locking primitive.
+ *
+ * @return 1 on success (match and store)
+ *         0 on no match
+ */
+static inline uint32_t cvmx_atomic_compare_and_store32(uint32_t *ptr, uint32_t old_val, uint32_t new_val)
+{
+    uint32_t ret;
+    CVMX_SYNCWS;
+    ret = cvmx_atomic_compare_and_store32_nosync(ptr, old_val, new_val);
+    CVMX_SYNCWS;
+    return ret;
+
+
+}
+
+/**
+ * Atomically compares the old value with the value at ptr, and if they match,
+ * stores new_val to ptr.
+ * If *ptr and old don't match, function returns failure immediately.
+ * If *ptr and old match, function spins until *ptr updated to new atomically, or
+ *  until *ptr and old no longer match
+ *
+ * Does no memory synchronization.
+ *
+ * @return 1 on success (match and store)
+ *         0 on no match
+ */
+static inline uint64_t cvmx_atomic_compare_and_store64_nosync(uint64_t *ptr, uint64_t old_val, uint64_t new_val)
+{
+    uint64_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: lld  %[tmp], %[val] \n"
+    "   li   %[ret], 0     \n"
+    "   bne  %[tmp], %[old], 2f \n"
+    "   move %[tmp], %[new_val] \n"
+    "   scd  %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   li   %[ret], 1      \n"
+    "2: nop               \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [old] "r" (old_val), [new_val] "r" (new_val)
+    : "memory");
+
+    return(ret);
+
+}
+
+/**
+ * Atomically compares the old value with the value at ptr, and if they match,
+ * stores new_val to ptr.
+ * If *ptr and old don't match, function returns failure immediately.
+ * If *ptr and old match, function spins until *ptr updated to new atomically, or
+ *  until *ptr and old no longer match
+ *
+ * Does memory synchronization that is required to use this as a locking primitive.
+ *
+ * @return 1 on success (match and store)
+ *         0 on no match
+ */
+static inline uint64_t cvmx_atomic_compare_and_store64(uint64_t *ptr, uint64_t old_val, uint64_t new_val)
+{
+    uint64_t ret;
+    CVMX_SYNCWS;
+    ret = cvmx_atomic_compare_and_store64_nosync(ptr, old_val, new_val);
+    CVMX_SYNCWS;
+    return ret;
+}
+
+/**
+ * Atomically adds a signed value to a 64 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.  (This should NOT be used for reference counting -
+ * use the standard version instead.)
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ *
+ * @return Value of memory location before increment
+ */
+static inline int64_t cvmx_atomic_fetch_and_add64_nosync(int64_t *ptr, int64_t incr)
+{
+    uint64_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder          \n"
+    "1: lld   %[tmp], %[val] \n"
+    "   move  %[ret], %[tmp] \n"
+    "   daddu %[tmp], %[inc] \n"
+    "   scd   %[tmp], %[val] \n"
+    "   beqz  %[tmp], 1b     \n"
+    "   nop                  \n"
+    ".set reorder            \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [inc] "r" (incr)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically adds a signed value to a 64 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * Memory access ordering is enforced before/after the atomic operation,
+ * so no additional 'sync' instructions are required.
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ *
+ * @return Value of memory location before increment
+ */
+static inline int64_t cvmx_atomic_fetch_and_add64(int64_t *ptr, int64_t incr)
+{
+    uint64_t ret;
+    CVMX_SYNCWS;
+    ret = cvmx_atomic_fetch_and_add64_nosync(ptr, incr);
+    CVMX_SYNCWS;
+    return ret;
+}
+
+/**
+ * Atomically adds a signed value to a 32 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.  (This should NOT be used for reference counting -
+ * use the standard version instead.)
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ *
+ * @return Value of memory location before increment
+ */
+static inline int32_t cvmx_atomic_fetch_and_add32_nosync(int32_t *ptr, int32_t incr)
+{
+    uint32_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: ll   %[tmp], %[val] \n"
+    "   move %[ret], %[tmp] \n"
+    "   addu %[tmp], %[inc] \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [inc] "r" (incr)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically adds a signed value to a 32 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * Memory access ordering is enforced before/after the atomic operation,
+ * so no additional 'sync' instructions are required.
+ *
+ * @param ptr    address in memory to add incr to
+ * @param incr   amount to increment memory location by (signed)
+ *
+ * @return Value of memory location before increment
+ */
+static inline int32_t cvmx_atomic_fetch_and_add32(int32_t *ptr, int32_t incr)
+{
+    uint32_t ret;
+    CVMX_SYNCWS;
+    ret = cvmx_atomic_fetch_and_add32_nosync(ptr, incr);
+    CVMX_SYNCWS;
+    return ret;
+}
+
+/**
+ * Atomically set bits in a 64 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.
+ *
+ * @param ptr    address in memory
+ * @param mask   mask of bits to set
+ *
+ * @return Value of memory location before setting bits
+ */
+static inline uint64_t cvmx_atomic_fetch_and_bset64_nosync(uint64_t *ptr, uint64_t mask)
+{
+    uint64_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: lld  %[tmp], %[val] \n"
+    "   move %[ret], %[tmp] \n"
+    "   or   %[tmp], %[msk] \n"
+    "   scd  %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [msk] "r" (mask)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically set bits in a 32 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.
+ *
+ * @param ptr    address in memory
+ * @param mask   mask of bits to set
+ *
+ * @return Value of memory location before setting bits
+ */
+static inline uint32_t cvmx_atomic_fetch_and_bset32_nosync(uint32_t *ptr, uint32_t mask)
+{
+    uint32_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: ll   %[tmp], %[val] \n"
+    "   move %[ret], %[tmp] \n"
+    "   or   %[tmp], %[msk] \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [msk] "r" (mask)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically clear bits in a 64 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.
+ *
+ * @param ptr    address in memory
+ * @param mask   mask of bits to clear
+ *
+ * @return Value of memory location before clearing bits
+ */
+static inline uint64_t cvmx_atomic_fetch_and_bclr64_nosync(uint64_t *ptr, uint64_t mask)
+{
+    uint64_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "   nor  %[msk], 0      \n"
+    "1: lld  %[tmp], %[val] \n"
+    "   move %[ret], %[tmp] \n"
+    "   and  %[tmp], %[msk] \n"
+    "   scd  %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [msk] "r" (mask)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically clear bits in a 32 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.
+ *
+ * @param ptr    address in memory
+ * @param mask   mask of bits to clear
+ *
+ * @return Value of memory location before clearing bits
+ */
+static inline uint32_t cvmx_atomic_fetch_and_bclr32_nosync(uint32_t *ptr, uint32_t mask)
+{
+    uint32_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "   nor  %[msk], 0      \n"
+    "1: ll   %[tmp], %[val] \n"
+    "   move %[ret], %[tmp] \n"
+    "   and  %[tmp], %[msk] \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [msk] "r" (mask)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically swaps value in 64 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.
+ *
+ * @param ptr       address in memory
+ * @param new_val   new value to write
+ *
+ * @return Value of memory location before swap operation
+ */
+static inline uint64_t cvmx_atomic_swap64_nosync(uint64_t *ptr, uint64_t new_val)
+{
+    uint64_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: lld  %[ret], %[val] \n"
+    "   move %[tmp], %[new_val] \n"
+    "   scd  %[tmp], %[val] \n"
+    "   beqz %[tmp],  1b    \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [new_val] "r"  (new_val)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * Atomically swaps value in 32 bit (aligned) memory location,
+ * and returns previous value.
+ *
+ * This version does not perform 'sync' operations to enforce memory
+ * operations.  This should only be used when there are no memory operation
+ * ordering constraints.
+ *
+ * @param ptr       address in memory
+ * @param new_val   new value to write
+ *
+ * @return Value of memory location before swap operation
+ */
+static inline uint32_t cvmx_atomic_swap32_nosync(uint32_t *ptr, uint32_t new_val)
+{
+    uint32_t tmp, ret;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: ll   %[ret], %[val] \n"
+    "   move %[tmp], %[new_val] \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp],  1b    \n"
+    "   nop                 \n"
+    ".set reorder           \n"
+    : [val] "+m" (*ptr), [tmp] "=&r" (tmp), [ret] "=&r" (ret)
+    : [new_val] "r"  (new_val)
+    : "memory");
+
+    return (ret);
+}
+
+/**
+ * This atomic operation is now named cvmx_atomic_compare_and_store32_nosync
+ * and the (deprecated) macro is provided for backward compatibility.
+ * @deprecated
+ */
+#define cvmx_atomic_compare_and_store_nosync32 cvmx_atomic_compare_and_store32_nosync
+
+/**
+ * This atomic operation is now named cvmx_atomic_compare_and_store64_nosync
+ * and the (deprecated) macro is provided for backward compatibility.
+ * @deprecated
+ */
+#define cvmx_atomic_compare_and_store_nosync64 cvmx_atomic_compare_and_store64_nosync
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_ATOMIC_H__ */
diff --git a/cvmx-bootloader.h b/cvmx-bootloader.h
new file mode 100644
index 0000000000000..c1097aa339913
--- /dev/null
+++ b/cvmx-bootloader.h
@@ -0,0 +1,147 @@
+/***********************license start***************
+ *  Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+#ifndef __CVMX_BOOTLOADER__
+#define __CVMX_BOOTLOADER__
+
+
+
+/**
+ * @file
+ *
+ * Bootloader definitions that are shared with other programs
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+/* The bootloader_header_t structure defines the header that is present
+** at the start of binary u-boot images.  This header is used to locate the bootloader
+** image in NAND, and also to allow verification of images for normal NOR booting.
+** This structure is placed at the beginning of a bootloader binary image, and remains
+** in the executable code.
+*/
+#define BOOTLOADER_HEADER_MAGIC 0x424f4f54  /* "BOOT" in ASCII */
+
+#define BOOTLOADER_HEADER_COMMENT_LEN  64
+#define BOOTLOADER_HEADER_VERSION_LEN  64
+#define BOOTLOADER_HEADER_MAX_SIZE      0x200 /* limited by the space to the next exception handler */
+
+#define BOOTLOADER_HEADER_CURRENT_MAJOR_REV 1
+#define BOOTLOADER_HEADER_CURRENT_MINOR_REV 1 
+
+/* offsets to struct bootloader_header fields for assembly use */
+#define MAGIC_OFFST     8
+#define HCRC_OFFST      12
+#define HLEN_OFFST      16
+#define DLEN_OFFST      24
+#define DCRC_OFFST      28
+#define GOT_OFFST       48
+
+#define LOOKUP_STEP 8192
+
+#ifndef __ASSEMBLY__
+typedef struct bootloader_header
+{
+    uint32_t    jump_instr; /* Jump to executable code following the
+                            ** header.  This allows this header to
+                            ** be (and remain) part of the executable image)
+                            */
+    uint32_t    nop_instr;  /* Must be 0x0 */
+    uint32_t    magic; /* Magic number to identify header */
+    uint32_t    hcrc;  /* CRC of all of header excluding this field */ 
+
+    uint16_t    hlen;  /* Length of header in bytes */
+    uint16_t    maj_rev;  /* Major revision */
+    uint16_t    min_rev;  /* Minor revision */
+    uint16_t    board_type;  /* Board type that the image is for */
+
+    uint32_t    dlen;  /* Length of data (immediately following header) in bytes */
+    uint32_t    dcrc;  /* CRC of data */
+    uint64_t    address;  /* Mips virtual address */
+    uint32_t    flags;
+    uint16_t    image_type;  /* Defined in bootloader_image_t enum */
+    uint16_t    resv0;       /* pad */
+ 
+    /* The next 4 fields are placed in compile-time, not by the utility */
+    uint32_t    got_address;   /* compiled got address position in the image */
+    uint32_t    got_num_entries; /* number of got entries */
+    uint32_t    compiled_start;  /* compaled start of the image address */
+    uint32_t    image_start;     /* relocated start of image address */
+
+    char        comment_string[BOOTLOADER_HEADER_COMMENT_LEN];  /* Optional, for descriptive purposes */
+    char        version_string[BOOTLOADER_HEADER_VERSION_LEN];  /* Optional, for descriptive purposes */
+} __attribute__((packed)) bootloader_header_t;
+
+
+
+/* Defines for flag field */
+#define BL_HEADER_FLAG_FAILSAFE         (1)
+
+
+typedef enum
+{
+    BL_HEADER_IMAGE_UKNOWN = 0x0,
+    BL_HEADER_IMAGE_STAGE2,  /* Binary bootloader stage2 image (NAND boot) */
+    BL_HEADER_IMAGE_STAGE3,  /* Binary bootloader stage3 image (NAND boot)*/
+    BL_HEADER_IMAGE_NOR,     /* Binary bootloader for NOR boot */
+    BL_HEADER_IMAGE_PCIBOOT,     /* Binary bootloader for PCI boot */
+    BL_HEADER_IMAGE_UBOOT_ENV,  /* Environment for u-boot */
+    BL_HEADER_IMAGE_MAX,
+    /* Range for customer private use.  Will not be used by Cavium Networks */
+    BL_HEADER_IMAGE_CUST_RESERVED_MIN = 0x1000,
+    BL_HEADER_IMAGE_CUST_RESERVED_MAX = 0x1fff,
+} bootloader_image_t;
+
+#endif /* __ASSEMBLY__ */
+
+/* Maximum address searched for NAND boot images and environments.  This is used
+** by stage1 and stage2. */
+#define MAX_NAND_SEARCH_ADDR   0x400000
+
+
+/* Defines for RAM based environment set by the host or the previous bootloader
+** in a chain boot configuration. */
+
+#define U_BOOT_RAM_ENV_ADDR     (0x1000)
+#define U_BOOT_RAM_ENV_SIZE     (0x1000)
+#define U_BOOT_RAM_ENV_CRC_SIZE (0x4)
+
+#endif /* __CVMX_BOOTLOADER__ */
diff --git a/cvmx-bootmem.c b/cvmx-bootmem.c
new file mode 100644
index 0000000000000..55aea601b70d5
--- /dev/null
+++ b/cvmx-bootmem.c
@@ -0,0 +1,952 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ * Simple allocate only memory allocator.  Used to allocate memory at application
+ * start time.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-bootmem.h"
+
+
+//#define DEBUG
+
+
+#undef	MAX
+#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
+
+#undef	MIN
+#define MIN(a, b)  (((a) < (b)) ? (a) : (b))
+
+#define ALIGN_ADDR_UP(addr, align)     (((addr) + (~(align))) & (align))
+
+static CVMX_SHARED cvmx_bootmem_desc_t *cvmx_bootmem_desc = NULL;
+
+/* See header file for descriptions of functions */
+
+/* Wrapper functions are provided for reading/writing the size and next block
+** values as these may not be directly addressible (in 32 bit applications, for instance.)
+*/
+/* Offsets of data elements in bootmem list, must match cvmx_bootmem_block_header_t */
+#define NEXT_OFFSET 0
+#define SIZE_OFFSET 8
+static void cvmx_bootmem_phy_set_size(uint64_t addr, uint64_t size)
+{
+    cvmx_write64_uint64((addr + SIZE_OFFSET) | (1ull << 63), size);
+}
+static void cvmx_bootmem_phy_set_next(uint64_t addr, uint64_t next)
+{
+    cvmx_write64_uint64((addr + NEXT_OFFSET) | (1ull << 63), next);
+}
+static uint64_t cvmx_bootmem_phy_get_size(uint64_t addr)
+{
+    return(cvmx_read64_uint64((addr + SIZE_OFFSET) | (1ull << 63)));
+}
+static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr)
+{
+    return(cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63)));
+}
+
+
+/* This functions takes an address range and adjusts it as necessary to
+** match the ABI that is currently being used.  This is required to ensure
+** that bootmem_alloc* functions only return valid pointers for 32 bit ABIs */
+static int __cvmx_validate_mem_range(uint64_t *min_addr_ptr, uint64_t *max_addr_ptr)
+{
+
+#if defined(__linux__) && defined(CVMX_ABI_N32)
+    {
+        extern uint64_t linux_mem32_min;
+        extern uint64_t linux_mem32_max;
+        /* For 32 bit Linux apps, we need to restrict the allocations to the range
+        ** of memory configured for access from userspace.  Also, we need to add mappings
+        ** for the data structures that we access.*/
+
+        /* Narrow range requests to be bounded by the 32 bit limits.  octeon_phy_mem_block_alloc()
+        ** will reject inconsistent req_size/range requests, so we don't repeat those checks here.
+        ** If max unspecified, set to 32 bit maximum. */
+        *min_addr_ptr = MIN(MAX(*min_addr_ptr, linux_mem32_min), linux_mem32_max);
+        if (!*max_addr_ptr)
+            *max_addr_ptr = linux_mem32_max;
+        else
+            *max_addr_ptr = MAX(MIN(*max_addr_ptr, linux_mem32_max), linux_mem32_min);
+    }
+#elif defined(CVMX_ABI_N32)
+    {
+        uint32_t max_phys = 0x0FFFFFFF;  /* Max physical address when 1-1 mappings not used */
+#if CVMX_USE_1_TO_1_TLB_MAPPINGS
+        max_phys = 0x7FFFFFFF;
+#endif
+        /* We are are running standalone simple executive, so we need to limit the range
+        ** that we allocate from */
+
+        /* Narrow range requests to be bounded by the 32 bit limits.  octeon_phy_mem_block_alloc()
+        ** will reject inconsistent req_size/range requests, so we don't repeat those checks here.
+        ** If max unspecified, set to 32 bit maximum. */
+        *min_addr_ptr = MIN(MAX(*min_addr_ptr, 0x0), max_phys);
+        if (!*max_addr_ptr)
+            *max_addr_ptr = max_phys;
+        else
+            *max_addr_ptr = MAX(MIN(*max_addr_ptr, max_phys), 0x0);
+    }
+#endif
+
+    return 0;
+}
+
+
+void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_t min_addr, uint64_t max_addr)
+{
+    int64_t address;
+
+    __cvmx_validate_mem_range(&min_addr, &max_addr);
+    address = cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, 0);
+
+    if (address > 0)
+        return cvmx_phys_to_ptr(address);
+    else
+        return NULL;
+}
+
+void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, uint64_t alignment)
+{
+    return cvmx_bootmem_alloc_range(size, alignment, address, address + size);
+}
+
+
+void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
+{
+    return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
+}
+
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, char *name)
+{
+    int64_t addr;
+
+    __cvmx_validate_mem_range(&min_addr, &max_addr);
+    addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, align, name, 0);
+    if (addr >= 0)
+        return cvmx_phys_to_ptr(addr);
+    else
+        return NULL;
+
+}
+void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, char *name)
+{
+    return(cvmx_bootmem_alloc_named_range(size, address, address + size, 0, name));
+}
+void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
+{
+    return(cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name));
+}
+
+int cvmx_bootmem_free_named(char *name)
+{
+    return(cvmx_bootmem_phy_named_block_free(name, 0));
+}
+
+cvmx_bootmem_named_block_desc_t * cvmx_bootmem_find_named_block(char *name)
+{
+    return(cvmx_bootmem_phy_named_block_find(name, 0));
+}
+
+void cvmx_bootmem_print_named(void)
+{
+    cvmx_bootmem_phy_named_block_print();
+}
+
+#if defined(__linux__) && defined(CVMX_ABI_N32)
+cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
+#endif
+
+int cvmx_bootmem_init(void *mem_desc_ptr)
+{
+    /* Verify that the size of cvmx_spinlock_t meets our assumptions */
+    if (sizeof(cvmx_spinlock_t) != 4)
+    {
+        cvmx_dprintf("ERROR: Unexpected size of cvmx_spinlock_t\n");
+        return(-1);
+    }
+
+    /* Here we set the global pointer to the bootmem descriptor block.  This pointer will
+    ** be used directly, so we will set it up to be directly usable by the application.
+    ** It is set up as follows for the various runtime/ABI combinations:
+    ** Linux 64 bit: Set XKPHYS bit
+    ** Linux 32 bit: use mmap to create mapping, use virtual address
+    ** CVMX 64 bit:  use physical address directly
+    ** CVMX 32 bit:  use physical address directly
+    ** Note that the CVMX environment assumes the use of 1-1 TLB mappings so that the physical addresses
+    ** can be used directly
+    */
+    if (!cvmx_bootmem_desc)
+    {
+#if defined(CVMX_BUILD_FOR_LINUX_USER) && defined(CVMX_ABI_N32)
+        void *base_ptr;
+        /* For 32 bit, we need to use mmap to create a mapping for the bootmem descriptor */
+        int dm_fd = open("/dev/mem", O_RDWR);
+        if (dm_fd < 0)
+        {
+            cvmx_dprintf("ERROR opening /dev/mem for boot descriptor mapping\n");
+            return(-1);
+        }
+
+        base_ptr = mmap(NULL,
+                        sizeof(cvmx_bootmem_desc_t) + sysconf(_SC_PAGESIZE),
+                        PROT_READ | PROT_WRITE,
+                        MAP_SHARED,
+                        dm_fd,
+                        ((off_t)mem_desc_ptr) & ~(sysconf(_SC_PAGESIZE) - 1));
+
+        if (MAP_FAILED == base_ptr)
+        {
+            cvmx_dprintf("Error mapping bootmem descriptor!\n");
+            close(dm_fd);
+            return(-1);
+        }
+
+        /* Adjust pointer to point to bootmem_descriptor, rather than start of page it is in */
+        cvmx_bootmem_desc =  (cvmx_bootmem_desc_t*)((char*)base_ptr + (((off_t)mem_desc_ptr) & (sysconf(_SC_PAGESIZE) - 1)));
+
+        /* Also setup mapping for named memory block desc. while we are at it.  Here we must keep another
+        ** pointer around, as the value in the bootmem descriptor is shared with other applications. */
+        base_ptr = mmap(NULL,
+                        sizeof(cvmx_bootmem_named_block_desc_t) * cvmx_bootmem_desc->named_block_num_blocks + sysconf(_SC_PAGESIZE),
+                        PROT_READ | PROT_WRITE,
+                        MAP_SHARED,
+                        dm_fd,
+                        ((off_t)cvmx_bootmem_desc->named_block_array_addr) & ~(sysconf(_SC_PAGESIZE) - 1));
+
+        close(dm_fd);
+
+        if (MAP_FAILED == base_ptr)
+        {
+            cvmx_dprintf("Error mapping named block descriptor!\n");
+            return(-1);
+        }
+
+        /* Adjust pointer to point to named block array, rather than start of page it is in */
+        linux32_named_block_array_ptr = (cvmx_bootmem_named_block_desc_t*)((char*)base_ptr + (((off_t)cvmx_bootmem_desc->named_block_array_addr) & (sysconf(_SC_PAGESIZE) - 1)));
+
+#elif (defined(CVMX_BUILD_FOR_LINUX_KERNEL) || defined(CVMX_BUILD_FOR_LINUX_USER)) && defined(CVMX_ABI_64)
+        /* Set XKPHYS bit */
+        cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr));
+#else
+        cvmx_bootmem_desc = (cvmx_bootmem_desc_t*)mem_desc_ptr;
+#endif
+    }
+
+
+    return(0);
+}
+
+
+uint64_t cvmx_bootmem_available_mem(uint64_t min_block_size)
+{
+    return(cvmx_bootmem_phy_available_mem(min_block_size));
+}
+
+
+
+
+
+/*********************************************************************
+** The cvmx_bootmem_phy* functions below return 64 bit physical addresses,
+** and expose more features that the cvmx_bootmem_functions above.  These are
+** required for full memory space access in 32 bit applications, as well as for
+** using some advance features.
+** Most applications should not need to use these.
+**
+**/
+
+
+int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t address_max, uint64_t alignment, uint32_t flags)
+{
+
+    uint64_t head_addr;
+    uint64_t ent_addr;
+    uint64_t prev_addr = 0;  /* points to previous list entry, NULL current entry is head of list */
+    uint64_t new_ent_addr = 0;
+    uint64_t desired_min_addr;
+    uint64_t alignment_mask = ~(alignment - 1);
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_alloc: req_size: 0x%llx, min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n",
+           (unsigned long long)req_size, (unsigned long long)address_min, (unsigned long long)address_max, (unsigned long long)alignment);
+#endif
+
+    if (cvmx_bootmem_desc->major_version > 3)
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+        goto error_out;
+    }
+
+    /* Do a variety of checks to validate the arguments.  The allocator code will later assume
+    ** that these checks have been made.  We validate that the requested constraints are not
+    ** self-contradictory before we look through the list of available memory
+    */
+
+    /* 0 is not a valid req_size for this allocator */
+    if (!req_size)
+        goto error_out;
+
+    /* Round req_size up to mult of minimum alignment bytes */
+    req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
+
+    /* Convert !0 address_min and 0 address_max to special case of range that specifies an exact
+    ** memory block to allocate.  Do this before other checks and adjustments so that this tranformation will be validated */
+    if (address_min && !address_max)
+        address_max = address_min + req_size;
+    else if (!address_min && !address_max)
+        address_max = ~0ull;   /* If no limits given, use max limits */
+
+
+
+
+    /* Enforce minimum alignment (this also keeps the minimum free block
+    ** req_size the same as the alignment req_size */
+    if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE)
+    {
+        alignment = CVMX_BOOTMEM_ALIGNMENT_SIZE;
+    }
+    alignment_mask = ~(alignment - 1);
+
+    /* Adjust address minimum based on requested alignment (round up to meet alignment).  Do this here so we can
+    ** reject impossible requests up front. (NOP for address_min == 0) */
+    if (alignment)
+        address_min = (address_min + (alignment - 1)) & ~(alignment - 1);
+
+
+    /* Reject inconsistent args.  We have adjusted these, so this may fail due to our internal changes
+    ** even if this check would pass for the values the user supplied. */
+    if (req_size > address_max - address_min)
+        goto error_out;
+
+    /* Walk through the list entries - first fit found is returned */
+
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    head_addr = cvmx_bootmem_desc->head_addr;
+    ent_addr = head_addr;
+    while (ent_addr)
+    {
+        uint64_t usable_base, usable_max;
+        uint64_t ent_size = cvmx_bootmem_phy_get_size(ent_addr);
+
+        if (cvmx_bootmem_phy_get_next(ent_addr) && ent_addr > cvmx_bootmem_phy_get_next(ent_addr))
+        {
+            cvmx_dprintf("Internal bootmem_alloc() error: ent: 0x%llx, next: 0x%llx\n",
+                   (unsigned long long)ent_addr, (unsigned long long)cvmx_bootmem_phy_get_next(ent_addr));
+            goto error_out;
+        }
+
+        /* Determine if this is an entry that can satisify the request */
+        /* Check to make sure entry is large enough to satisfy request */
+        usable_base = ALIGN_ADDR_UP(MAX(address_min, ent_addr), alignment_mask);
+        usable_max = MIN(address_max, ent_addr + ent_size);
+        /* We should be able to allocate block at address usable_base */
+
+        desired_min_addr = usable_base;
+
+        /* Determine if request can be satisfied from the current entry */
+        if ((((ent_addr + ent_size) > usable_base && ent_addr < address_max))
+            && req_size <= usable_max - usable_base)
+        {
+            /* We have found an entry that has room to satisfy the request, so allocate it from this entry */
+
+            /* If end CVMX_BOOTMEM_FLAG_END_ALLOC set, then allocate from the end of this block
+            ** rather than the beginning */
+            if (flags & CVMX_BOOTMEM_FLAG_END_ALLOC)
+            {
+                desired_min_addr = usable_max - req_size;
+                /* Align desired address down to required alignment */
+                desired_min_addr &= alignment_mask;
+            }
+
+            /* Match at start of entry */
+            if (desired_min_addr == ent_addr)
+            {
+                if (req_size < ent_size)
+                {
+                    /* big enough to create a new block from top portion of block */
+                    new_ent_addr = ent_addr + req_size;
+                    cvmx_bootmem_phy_set_next(new_ent_addr, cvmx_bootmem_phy_get_next(ent_addr));
+                    cvmx_bootmem_phy_set_size(new_ent_addr, ent_size - req_size);
+
+                    /* Adjust next pointer as following code uses this */
+                    cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr);
+                }
+
+                /* adjust prev ptr or head to remove this entry from list */
+                if (prev_addr)
+                {
+                    cvmx_bootmem_phy_set_next(prev_addr, cvmx_bootmem_phy_get_next(ent_addr));
+                }
+                else
+                {
+                    /* head of list being returned, so update head ptr */
+                    cvmx_bootmem_desc->head_addr = cvmx_bootmem_phy_get_next(ent_addr);
+                }
+                if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+                return(desired_min_addr);
+            }
+
+
+            /* block returned doesn't start at beginning of entry, so we know
+            ** that we will be splitting a block off the front of this one.  Create a new block
+            ** from the beginning, add to list, and go to top of loop again.
+            **
+            ** create new block from high portion of block, so that top block
+            ** starts at desired addr
+            **/
+            new_ent_addr = desired_min_addr;
+            cvmx_bootmem_phy_set_next(new_ent_addr, cvmx_bootmem_phy_get_next(ent_addr));
+            cvmx_bootmem_phy_set_size(new_ent_addr, cvmx_bootmem_phy_get_size(ent_addr) - (desired_min_addr - ent_addr));
+            cvmx_bootmem_phy_set_size(ent_addr, desired_min_addr - ent_addr);
+            cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr);
+            /* Loop again to handle actual alloc from new block */
+        }
+
+        prev_addr = ent_addr;
+        ent_addr = cvmx_bootmem_phy_get_next(ent_addr);
+    }
+error_out:
+    /* We didn't find anything, so return error */
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    return(-1);
+}
+
+
+
+int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
+{
+    uint64_t cur_addr;
+    uint64_t prev_addr = 0;  /* zero is invalid */
+    int retval = 0;
+
+#ifdef DEBUG
+    cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n", (unsigned long long)phy_addr, (unsigned long long)size);
+#endif
+    if (cvmx_bootmem_desc->major_version > 3)
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+        return(0);
+    }
+
+    /* 0 is not a valid size for this allocator */
+    if (!size)
+        return(0);
+
+
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    cur_addr = cvmx_bootmem_desc->head_addr;
+    if (cur_addr == 0 || phy_addr < cur_addr)
+    {
+        /* add at front of list - special case with changing head ptr */
+        if (cur_addr && phy_addr + size > cur_addr)
+            goto bootmem_free_done; /* error, overlapping section */
+        else if (phy_addr + size == cur_addr)
+        {
+            /* Add to front of existing first block */
+            cvmx_bootmem_phy_set_next(phy_addr, cvmx_bootmem_phy_get_next(cur_addr));
+            cvmx_bootmem_phy_set_size(phy_addr, cvmx_bootmem_phy_get_size(cur_addr) + size);
+            cvmx_bootmem_desc->head_addr = phy_addr;
+
+        }
+        else
+        {
+            /* New block before first block */
+            cvmx_bootmem_phy_set_next(phy_addr, cur_addr);  /* OK if cur_addr is 0 */
+            cvmx_bootmem_phy_set_size(phy_addr, size);
+            cvmx_bootmem_desc->head_addr = phy_addr;
+        }
+        retval = 1;
+        goto bootmem_free_done;
+    }
+
+    /* Find place in list to add block */
+    while (cur_addr && phy_addr > cur_addr)
+    {
+        prev_addr = cur_addr;
+        cur_addr = cvmx_bootmem_phy_get_next(cur_addr);
+    }
+
+    if (!cur_addr)
+    {
+        /* We have reached the end of the list, add on to end, checking
+        ** to see if we need to combine with last block
+        **/
+        if (prev_addr +  cvmx_bootmem_phy_get_size(prev_addr) == phy_addr)
+        {
+            cvmx_bootmem_phy_set_size(prev_addr, cvmx_bootmem_phy_get_size(prev_addr) + size);
+        }
+        else
+        {
+            cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
+            cvmx_bootmem_phy_set_size(phy_addr, size);
+            cvmx_bootmem_phy_set_next(phy_addr, 0);
+        }
+        retval = 1;
+        goto bootmem_free_done;
+    }
+    else
+    {
+        /* insert between prev and cur nodes, checking for merge with either/both */
+
+        if (prev_addr +  cvmx_bootmem_phy_get_size(prev_addr) == phy_addr)
+        {
+            /* Merge with previous */
+            cvmx_bootmem_phy_set_size(prev_addr, cvmx_bootmem_phy_get_size(prev_addr) + size);
+            if (phy_addr + size == cur_addr)
+            {
+                /* Also merge with current */
+                cvmx_bootmem_phy_set_size(prev_addr, cvmx_bootmem_phy_get_size(cur_addr) + cvmx_bootmem_phy_get_size(prev_addr));
+                cvmx_bootmem_phy_set_next(prev_addr, cvmx_bootmem_phy_get_next(cur_addr));
+            }
+            retval = 1;
+            goto bootmem_free_done;
+        }
+        else if (phy_addr + size == cur_addr)
+        {
+            /* Merge with current */
+            cvmx_bootmem_phy_set_size(phy_addr, cvmx_bootmem_phy_get_size(cur_addr) + size);
+            cvmx_bootmem_phy_set_next(phy_addr, cvmx_bootmem_phy_get_next(cur_addr));
+            cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
+            retval = 1;
+            goto bootmem_free_done;
+        }
+
+        /* It is a standalone block, add in between prev and cur */
+        cvmx_bootmem_phy_set_size(phy_addr, size);
+        cvmx_bootmem_phy_set_next(phy_addr, cur_addr);
+        cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
+
+
+    }
+    retval = 1;
+
+bootmem_free_done:
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    return(retval);
+
+}
+
+
+
+void cvmx_bootmem_phy_list_print(void)
+{
+    uint64_t addr;
+
+    addr = cvmx_bootmem_desc->head_addr;
+    cvmx_dprintf("\n\n\nPrinting bootmem block list, descriptor: %p,  head is 0x%llx\n",
+           cvmx_bootmem_desc, (unsigned long long)addr);
+    cvmx_dprintf("Descriptor version: %d.%d\n", (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version);
+    if (cvmx_bootmem_desc->major_version > 3)
+    {
+        cvmx_dprintf("Warning: Bootmem descriptor version is newer than expected\n");
+    }
+    if (!addr)
+    {
+        cvmx_dprintf("mem list is empty!\n");
+    }
+    while (addr)
+    {
+        cvmx_dprintf("Block address: 0x%08qx, size: 0x%08qx, next: 0x%08qx\n",
+               (unsigned long long)addr,
+               (unsigned long long)cvmx_bootmem_phy_get_size(addr),
+               (unsigned long long)cvmx_bootmem_phy_get_next(addr));
+        addr = cvmx_bootmem_phy_get_next(addr);
+    }
+    cvmx_dprintf("\n\n");
+
+}
+
+
+uint64_t cvmx_bootmem_phy_available_mem(uint64_t min_block_size)
+{
+    uint64_t addr;
+
+    uint64_t available_mem = 0;
+
+    cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    addr = cvmx_bootmem_desc->head_addr;
+    while (addr)
+    {
+        if (cvmx_bootmem_phy_get_size(addr) >= min_block_size)
+            available_mem += cvmx_bootmem_phy_get_size(addr);
+        addr = cvmx_bootmem_phy_get_next(addr);
+    }
+    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+    return(available_mem);
+
+}
+
+
+
+cvmx_bootmem_named_block_desc_t * cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags)
+{
+    unsigned int i;
+    cvmx_bootmem_named_block_desc_t *named_block_array_ptr;
+
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name);
+#endif
+    /* Lock the structure to make sure that it is not being changed while we are
+    ** examining it.
+    */
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+#if defined(__linux__) && !defined(CONFIG_OCTEON_U_BOOT)
+#ifdef CVMX_ABI_N32
+    /* Need to use mmapped named block pointer in 32 bit linux apps */
+extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
+    named_block_array_ptr = linux32_named_block_array_ptr;
+#else
+    /* Use XKPHYS for 64 bit linux */
+    named_block_array_ptr = (cvmx_bootmem_named_block_desc_t *)cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
+#endif
+#else
+    /* Simple executive case. (and u-boot)
+    ** This could be in the low 1 meg of memory that is not 1-1 mapped, so we need use XKPHYS/KSEG0 addressing for it */
+    named_block_array_ptr = CASTPTR(cvmx_bootmem_named_block_desc_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,cvmx_bootmem_desc->named_block_array_addr));
+#endif
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n", named_block_array_ptr);
+#endif
+    if (cvmx_bootmem_desc->major_version == 3)
+    {
+        for (i = 0; i < cvmx_bootmem_desc->named_block_num_blocks; i++)
+        {
+            if ((name && named_block_array_ptr[i].size && !strncmp(name, named_block_array_ptr[i].name, cvmx_bootmem_desc->named_block_name_len - 1))
+                || (!name && !named_block_array_ptr[i].size))
+            {
+                if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+                return(&(named_block_array_ptr[i]));
+            }
+        }
+    }
+    else
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+    }
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+    return(NULL);
+}
+
+int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
+{
+    cvmx_bootmem_named_block_desc_t *named_block_ptr;
+
+    if (cvmx_bootmem_desc->major_version != 3)
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+        return(0);
+    }
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name);
+#endif
+
+    /* Take lock here, as name lookup/block free/name free need to be atomic */
+    cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+    named_block_ptr = cvmx_bootmem_phy_named_block_find(name, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+    if (named_block_ptr)
+    {
+#ifdef DEBUG
+        cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s, base: 0x%llx, size: 0x%llx\n", name, (unsigned long long)named_block_ptr->base_addr, (unsigned long long)named_block_ptr->size);
+#endif
+        __cvmx_bootmem_phy_free(named_block_ptr->base_addr, named_block_ptr->size, CVMX_BOOTMEM_FLAG_NO_LOCKING);
+        named_block_ptr->size = 0;
+        /* Set size to zero to indicate block not used. */
+    }
+
+    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+    return(!!named_block_ptr);  /* 0 on failure, 1 on success */
+}
+
+
+
+
+
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t alignment, char *name, uint32_t flags)
+{
+    int64_t addr_allocated;
+    cvmx_bootmem_named_block_desc_t *named_block_desc_ptr;
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: 0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
+                 (unsigned long long)size,
+                 (unsigned long long)min_addr,
+                 (unsigned long long)max_addr,
+                 (unsigned long long)alignment,
+                 name);
+#endif
+    if (cvmx_bootmem_desc->major_version != 3)
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+        return(-1);
+    }
+
+
+    /* Take lock here, as name lookup/block alloc/name add need to be atomic */
+
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+    /* Get pointer to first available named block descriptor */
+    named_block_desc_ptr = cvmx_bootmem_phy_named_block_find(NULL, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+    /* Check to see if name already in use, return error if name
+    ** not available or no more room for blocks.
+    */
+    if (cvmx_bootmem_phy_named_block_find(name, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr)
+    {
+        if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+            cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+        return(-1);
+    }
+
+
+    /* Round size up to mult of minimum alignment bytes
+    ** We need the actual size allocated to allow for blocks to be coallesced
+    ** when they are freed.  The alloc routine does the same rounding up
+    ** on all allocations. */
+    size = (size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
+
+    addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+    if (addr_allocated >= 0)
+    {
+        named_block_desc_ptr->base_addr = addr_allocated;
+        named_block_desc_ptr->size = size;
+        strncpy(named_block_desc_ptr->name, name, cvmx_bootmem_desc->named_block_name_len);
+        named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
+    }
+
+    if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+    return(addr_allocated);
+}
+
+
+
+
+void cvmx_bootmem_phy_named_block_print(void)
+{
+    unsigned int i;
+    int printed = 0;
+
+#if defined(__linux__) && !defined(CONFIG_OCTEON_U_BOOT)
+#ifdef CVMX_ABI_N32
+    /* Need to use mmapped named block pointer in 32 bit linux apps */
+extern cvmx_bootmem_named_block_desc_t *linux32_named_block_array_ptr;
+    cvmx_bootmem_named_block_desc_t *named_block_array_ptr = linux32_named_block_array_ptr;
+#else
+    /* Use XKPHYS for 64 bit linux */
+    cvmx_bootmem_named_block_desc_t *named_block_array_ptr = (cvmx_bootmem_named_block_desc_t *)cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
+#endif
+#else
+    /* Simple executive case. (and u-boot)
+    ** This could be in the low 1 meg of memory that is not 1-1 mapped, so we need use XKPHYS/KSEG0 addressing for it */
+    cvmx_bootmem_named_block_desc_t *named_block_array_ptr = CASTPTR(cvmx_bootmem_named_block_desc_t, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,cvmx_bootmem_desc->named_block_array_addr));
+#endif
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_named_block_print, desc addr: %p\n", cvmx_bootmem_desc);
+#endif
+    if (cvmx_bootmem_desc->major_version != 3)
+    {
+        cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: %d.%d at addr: %p\n",
+               (int)cvmx_bootmem_desc->major_version, (int)cvmx_bootmem_desc->minor_version, cvmx_bootmem_desc);
+        return;
+    }
+    cvmx_dprintf("List of currently allocated named bootmem blocks:\n");
+    for (i = 0; i < cvmx_bootmem_desc->named_block_num_blocks; i++)
+    {
+        if (named_block_array_ptr[i].size)
+        {
+            printed++;
+            cvmx_dprintf("Name: %s, address: 0x%08qx, size: 0x%08qx, index: %d\n",
+                   named_block_array_ptr[i].name,
+                   (unsigned long long)named_block_array_ptr[i].base_addr,
+                   (unsigned long long)named_block_array_ptr[i].size,
+                   i);
+
+        }
+    }
+    if (!printed)
+    {
+        cvmx_dprintf("No named bootmem blocks exist.\n");
+    }
+
+}
+
+
+/* Real physical addresses of memory regions */
+#define OCTEON_DDR0_BASE    (0x0ULL)
+#define OCTEON_DDR0_SIZE    (0x010000000ULL)
+#define OCTEON_DDR1_BASE    (0x410000000ULL)
+#define OCTEON_DDR1_SIZE    (0x010000000ULL)
+#define OCTEON_DDR2_BASE    (0x020000000ULL)
+#define OCTEON_DDR2_SIZE    (0x3e0000000ULL)
+#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
+int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_bytes, cvmx_bootmem_desc_t *desc_buffer)
+{
+    uint64_t cur_block_addr;
+    int64_t addr;
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_mem_list_init (arg desc ptr: %p, cvmx_bootmem_desc: %p)\n", desc_buffer, cvmx_bootmem_desc);
+#endif
+
+    /* Descriptor buffer needs to be in 32 bit addressable space to be compatible with
+    ** 32 bit applications */
+    if (!desc_buffer)
+    {
+        cvmx_dprintf("ERROR: no memory for cvmx_bootmem descriptor provided\n");
+        return 0;
+    }
+
+    if (mem_size > OCTEON_MAX_PHY_MEM_SIZE)
+    {
+        mem_size = OCTEON_MAX_PHY_MEM_SIZE;
+        cvmx_dprintf("ERROR: requested memory size too large, truncating to maximum size\n");
+    }
+
+    if (cvmx_bootmem_desc)
+        return 1;
+
+    /* Initialize cvmx pointer to descriptor */
+    cvmx_bootmem_init(desc_buffer);
+
+    /* Set up global pointer to start of list, exclude low 64k for exception vectors, space for global descriptor */
+    memset(cvmx_bootmem_desc, 0x0, sizeof(cvmx_bootmem_desc_t));
+    /* Set version of bootmem descriptor */
+    cvmx_bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
+    cvmx_bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
+
+    cur_block_addr = cvmx_bootmem_desc->head_addr = (OCTEON_DDR0_BASE + low_reserved_bytes);
+
+    cvmx_bootmem_desc->head_addr = 0;
+
+    if (mem_size <= OCTEON_DDR0_SIZE)
+    {
+        __cvmx_bootmem_phy_free(cur_block_addr, mem_size - low_reserved_bytes, 0);
+        goto frees_done;
+    }
+
+    __cvmx_bootmem_phy_free(cur_block_addr, OCTEON_DDR0_SIZE - low_reserved_bytes, 0);
+
+    mem_size -= OCTEON_DDR0_SIZE;
+
+    /* Add DDR2 block next if present */
+    if (mem_size > OCTEON_DDR1_SIZE)
+    {
+        __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
+        __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, mem_size - OCTEON_DDR1_SIZE, 0);
+    }
+    else
+    {
+        __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
+
+    }
+frees_done:
+
+    /* Initialize the named block structure */
+    cvmx_bootmem_desc->named_block_name_len = CVMX_BOOTMEM_NAME_LEN;
+    cvmx_bootmem_desc->named_block_num_blocks = CVMX_BOOTMEM_NUM_NAMED_BLOCKS;
+    cvmx_bootmem_desc->named_block_array_addr = 0;
+
+    /* Allocate this near the top of the low 256 MBytes of memory */
+    addr = cvmx_bootmem_phy_alloc(CVMX_BOOTMEM_NUM_NAMED_BLOCKS * sizeof(cvmx_bootmem_named_block_desc_t),0, 0x10000000, 0 ,CVMX_BOOTMEM_FLAG_END_ALLOC);
+    if (addr >= 0)
+        cvmx_bootmem_desc->named_block_array_addr = addr;
+
+#ifdef DEBUG
+    cvmx_dprintf("cvmx_bootmem_phy_mem_list_init: named_block_array_addr: 0x%llx)\n", (unsigned long long)cvmx_bootmem_desc->named_block_array_addr);
+#endif
+    if (!cvmx_bootmem_desc->named_block_array_addr)
+    {
+        cvmx_dprintf("FATAL ERROR: unable to allocate memory for bootmem descriptor!\n");
+        return(0);
+    }
+    memset((void *)(unsigned long)cvmx_bootmem_desc->named_block_array_addr, 0x0, CVMX_BOOTMEM_NUM_NAMED_BLOCKS * sizeof(cvmx_bootmem_named_block_desc_t));
+
+    return(1);
+}
+
+
+void cvmx_bootmem_lock(void)
+{
+    cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+}
+
+void cvmx_bootmem_unlock(void)
+{
+    cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+}
+
+void *__cvmx_bootmem_internal_get_desc_ptr(void)
+{
+    return(cvmx_bootmem_desc);
+}
diff --git a/cvmx-bootmem.h b/cvmx-bootmem.h
new file mode 100644
index 0000000000000..b44ea02752bb4
--- /dev/null
+++ b/cvmx-bootmem.h
@@ -0,0 +1,429 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ * Simple allocate only memory allocator.  Used to allocate memory at application
+ * start time.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_BOOTMEM_H__
+#define __CVMX_BOOTMEM_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_BOOTMEM_NAME_LEN 128   /* Must be multiple of 8, changing breaks ABI */
+#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64  /* Can change without breaking ABI */
+#define CVMX_BOOTMEM_ALIGNMENT_SIZE     (16ull)  /* minimum alignment of bootmem alloced blocks */
+
+/* Flags for cvmx_bootmem_phy_mem* functions */
+#define CVMX_BOOTMEM_FLAG_END_ALLOC    (1 << 0)     /* Allocate from end of block instead of beginning */
+#define CVMX_BOOTMEM_FLAG_NO_LOCKING   (1 << 1)     /* Don't do any locking. */
+
+
+/* First bytes of each free physical block of memory contain this structure,
+ * which is used to maintain the free memory list.  Since the bootloader is
+ * only 32 bits, there is a union providing 64 and 32 bit versions.  The
+ * application init code converts addresses to 64 bit addresses before the
+ * application starts.
+ */
+typedef struct
+{
+    /* Note: these are referenced from assembly routines in the bootloader, so this structure
+    ** should not be changed without changing those routines as well. */
+    uint64_t next_block_addr;
+    uint64_t size;
+
+} cvmx_bootmem_block_header_t;
+
+
+/* Structure for named memory blocks
+** Number of descriptors
+** available can be changed without affecting compatiblity,
+** but name length changes require a bump in the bootmem
+** descriptor version
+** Note: This structure must be naturally 64 bit aligned, as a single
+** memory image will be used by both 32 and 64 bit programs.
+*/
+typedef struct
+{
+    uint64_t base_addr;     /**< Base address of named block */
+    uint64_t size;          /**< Size actually allocated for named block (may differ from requested) */
+    char name[CVMX_BOOTMEM_NAME_LEN];   /**< name of named block */
+} cvmx_bootmem_named_block_desc_t;
+
+
+
+/* Current descriptor versions */
+#define CVMX_BOOTMEM_DESC_MAJ_VER   3   /* CVMX bootmem descriptor major version */
+#define CVMX_BOOTMEM_DESC_MIN_VER   0   /* CVMX bootmem descriptor minor version */
+
+/* First three members of cvmx_bootmem_desc_t are left in original
+** positions for backwards compatibility.
+*/
+typedef struct
+{
+    uint32_t    lock;       /**< spinlock to control access to list */
+    uint32_t    flags;      /**< flags for indicating various conditions */
+    uint64_t    head_addr;
+
+    uint32_t    major_version;  /**< incremented changed when incompatible changes made */
+    uint32_t    minor_version;  /**< incremented changed when compatible changes made, reset to zero when major incremented */
+    uint64_t    app_data_addr;
+    uint64_t    app_data_size;
+
+    uint32_t    named_block_num_blocks;  /**< number of elements in named blocks array */
+    uint32_t    named_block_name_len;    /**< length of name array in bootmem blocks */
+    uint64_t    named_block_array_addr;  /**< address of named memory block descriptors */
+
+} cvmx_bootmem_desc_t;
+
+
+/**
+ * Initialize the boot alloc memory structures. This is
+ * normally called inside of cvmx_user_app_init()
+ *
+ * @param mem_desc_ptr	Address of the free memory list
+ * @return
+ */
+extern int cvmx_bootmem_init(void *mem_desc_ptr);
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader.
+ * This is an allocate-only algorithm, so freeing memory is not possible.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
+
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader at a specific
+ * address. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated at the specified address.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param address   Physical address to allocate memory at.  If this memory is not
+ *                  available, the allocation fails.
+ * @param alignment Alignment required - must be power of 2
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, uint64_t alignment);
+
+
+
+/**
+ * Allocate a block of memory from the free list that was
+ * passed to the application by the bootloader within a specified
+ * address range. This is an allocate-only algorithm, so
+ * freeing memory is not possible. Allocation will fail if
+ * memory cannot be allocated in the requested range.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param min_addr  defines the minimum address of the range
+ * @param max_addr  defines the maximum address of the range
+ * @param alignment Alignment required - must be power of 2
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, uint64_t min_addr, uint64_t max_addr);
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param alignment Alignment required - must be power of 2
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name);
+
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param address   Physical address to allocate memory at.  If this memory is not
+ *                  available, the allocation fails.
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, char *name);
+
+
+
+/**
+ * Allocate a block of memory from a specific range of the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ * If request cannot be satisfied within the address range specified, NULL is returned
+ *
+ * @param size      Size in bytes of block to allocate
+ * @param min_addr  minimum address of range
+ * @param max_addr  maximum address of range
+ * @param align  Alignment of memory to be allocated. (must be a power of 2)
+ * @param name      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, char *name);
+
+/**
+ * Frees a previously allocated named bootmem block.
+ *
+ * @param name   name of block to free
+ *
+ * @return 0 on failure,
+ *         !0 on success
+ */
+extern int cvmx_bootmem_free_named(char *name);
+
+
+/**
+ * Finds a named bootmem block by name.
+ *
+ * @param name   name of block to free
+ *
+ * @return pointer to named block descriptor on success
+ *         0 on failure
+ */
+cvmx_bootmem_named_block_desc_t * cvmx_bootmem_find_named_block(char *name);
+
+
+
+/**
+ * Returns the size of available memory in bytes, only
+ * counting blocks that are at least as big as the minimum block
+ * size.
+ *
+ * @param min_block_size
+ *               Minimum block size to count in total.
+ *
+ * @return Number of bytes available for allocation that meet the block size requirement
+ */
+uint64_t cvmx_bootmem_available_mem(uint64_t min_block_size);
+
+
+
+/**
+ * Prints out the list of named blocks that have been allocated
+ * along with their addresses and sizes.
+ * This is primarily used for debugging purposes
+ */
+void cvmx_bootmem_print_named(void);
+
+
+/**
+ * Allocates a block of physical memory from the free list, at (optional) requested address and alignment.
+ *
+ * @param req_size  size of region to allocate.  All requests are rounded up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
+ * @param address_min
+ *                  Minimum address that block can occupy.
+ * @param address_max
+ *                  Specifies the maximum address_min (inclusive) that the allocation can use.
+ * @param alignment Requested alignment of the block.  If this alignment cannot be met, the allocation fails.
+ *                  This must be a power of 2.
+ *                  (Note: Alignment of CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and internally enforced.  Requested alignments of
+ *                  less than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint64_t address_max, uint64_t alignment, uint32_t flags);
+
+
+
+/**
+ * Allocates a named block of physical memory from the free list, at (optional) requested address and alignment.
+ *
+ * @param size      size of region to allocate.  All requests are rounded up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
+ * @param min_addr
+ *                  Minimum address that block can occupy.
+ * @param max_addr
+ *                  Specifies the maximum address_min (inclusive) that the allocation can use.
+ * @param alignment Requested alignment of the block.  If this alignment cannot be met, the allocation fails.
+ *                  This must be a power of 2.
+ *                  (Note: Alignment of CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and internally enforced.  Requested alignments of
+ *                  less than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param name      name to assign to named block
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t alignment, char *name, uint32_t flags);
+
+
+/**
+ * Finds a named memory block by name.
+ * Also used for finding an unused entry in the named block table.
+ *
+ * @param name   Name of memory block to find.
+ *               If NULL pointer given, then finds unused descriptor, if available.
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return Pointer to memory block descriptor, NULL if not found.
+ *         If NULL returned when name parameter is NULL, then no memory
+ *         block descriptors are available.
+ */
+cvmx_bootmem_named_block_desc_t * cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
+
+
+/**
+ * Returns the size of available memory in bytes, only
+ * counting blocks that are at least as big as the minimum block
+ * size.
+ *
+ * @param min_block_size
+ *               Minimum block size to count in total.
+ *
+ * @return Number of bytes available for allocation that meet the block size requirement
+ */
+uint64_t cvmx_bootmem_phy_available_mem(uint64_t min_block_size);
+
+/**
+ * Frees a named block.
+ *
+ * @param name   name of block to free
+ * @param flags  flags for passing options
+ *
+ * @return 0 on failure
+ *         1 on success
+ */
+int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
+
+/**
+ * Frees a block to the bootmem allocator list.  This must
+ * be used with care, as the size provided must match the size
+ * of the block that was allocated, or the list will become
+ * corrupted.
+ *
+ * IMPORTANT:  This is only intended to be used as part of named block
+ * frees and initial population of the free memory list.
+ *                                                      *
+ *
+ * @param phy_addr physical address of block
+ * @param size     size of block in bytes.
+ * @param flags    flags for passing options
+ *
+ * @return 1 on success,
+ *         0 on failure
+ */
+int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
+
+
+/**
+ * Prints the list of currently allocated named blocks
+ *
+ */
+void cvmx_bootmem_phy_named_block_print(void);
+
+
+/**
+ * Prints the list of available memory.
+ *
+ */
+void cvmx_bootmem_phy_list_print(void);
+
+
+
+/**
+ * This function initializes the free memory list used by cvmx_bootmem.
+ * This must be called before any allocations can be done.
+ *
+ * @param mem_size Total memory available, in bytes
+ * @param low_reserved_bytes
+ *                 Number of bytes to reserve (leave out of free list) at address 0x0.
+ * @param desc_buffer
+ *                 Buffer for the bootmem descriptor.  This must be a 32 bit addressable
+ *                 address.
+ *
+ * @return 1 on success
+ *         0 on failure
+ */
+int64_t cvmx_bootmem_phy_mem_list_init(uint64_t mem_size, uint32_t low_reserved_bytes, cvmx_bootmem_desc_t *desc_buffer);
+
+/**
+ * Locks the bootmem allocator.  This is useful in certain situations
+ * where multiple allocations must be made without being interrupted.
+ * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
+ *
+ */
+void cvmx_bootmem_lock(void);
+
+/**
+ * Unlocks the bootmem allocator.  This is useful in certain situations
+ * where multiple allocations must be made without being interrupted.
+ * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
+ *
+ */
+void cvmx_bootmem_unlock(void);
+
+/**
+ * Internal use function to get the current descriptor pointer */
+void *__cvmx_bootmem_internal_get_desc_ptr(void);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /*   __CVMX_BOOTMEM_H__ */
diff --git a/cvmx-ciu.h b/cvmx-ciu.h
new file mode 100644
index 0000000000000..aca6c4fa96863
--- /dev/null
+++ b/cvmx-ciu.h
@@ -0,0 +1,65 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Interrupt Unit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_CIU_H__
+#define __CVMX_CIU_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/cvmx-cmd-queue.c b/cvmx-cmd-queue.c
new file mode 100644
index 0000000000000..5da42e845bba7
--- /dev/null
+++ b/cvmx-cmd-queue.c
@@ -0,0 +1,309 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support functions for managing command queues used for
+ * various hardware blocks.
+ *
+ * <hr>$Revision: 42150 $<hr>
+ */
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-fpa.h"
+#include "cvmx-cmd-queue.h"
+#include "cvmx-bootmem.h"
+
+/**
+ * This application uses this pointer to access the global queue
+ * state. It points to a bootmem named block.
+ */
+CVMX_SHARED __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr = NULL;
+
+
+/**
+ * @INTERNAL
+ * Initialize the Global queue state pointer.
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
+{
+    char *alloc_name = "cvmx_cmd_queues";
+#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
+    extern uint64_t octeon_reserve32_memory;
+#endif
+
+    if (cvmx_likely(__cvmx_cmd_queue_state_ptr))
+        return CVMX_CMD_QUEUE_SUCCESS;
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+#if CONFIG_CAVIUM_RESERVE32
+    if (octeon_reserve32_memory)
+        __cvmx_cmd_queue_state_ptr = cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr),
+                                                              octeon_reserve32_memory,
+                                                              octeon_reserve32_memory + (CONFIG_CAVIUM_RESERVE32<<20) - 1,
+                                                              128, alloc_name);
+    else
+#endif
+        __cvmx_cmd_queue_state_ptr = cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), 128, alloc_name);
+#else
+    __cvmx_cmd_queue_state_ptr = cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), 128, alloc_name);
+#endif
+    if (__cvmx_cmd_queue_state_ptr)
+        memset(__cvmx_cmd_queue_state_ptr, 0, sizeof(*__cvmx_cmd_queue_state_ptr));
+    else
+    {
+        cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
+        if (block_desc)
+            __cvmx_cmd_queue_state_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
+        else
+        {
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n", alloc_name);
+            return CVMX_CMD_QUEUE_NO_MEMORY;
+        }
+    }
+    return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+
+/**
+ * Initialize a command queue for use. The initial FPA buffer is
+ * allocated and the hardware unit is configured to point to the
+ * new command queue.
+ *
+ * @param queue_id  Hardware command queue to initialize.
+ * @param max_depth Maximum outstanding commands that can be queued.
+ * @param fpa_pool  FPA pool the command queues should come from.
+ * @param pool_size Size of each buffer in the FPA pool (bytes)
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, int max_depth, int fpa_pool, int pool_size)
+{
+    __cvmx_cmd_queue_state_t *qstate;
+    cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr();
+    if (result != CVMX_CMD_QUEUE_SUCCESS)
+        return result;
+
+    qstate = __cvmx_cmd_queue_get_state(queue_id);
+    if (qstate == NULL)
+        return CVMX_CMD_QUEUE_INVALID_PARAM;
+
+    /* We artificially limit max_depth to 1<<20 words. It is an arbitrary limit */
+    if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH)
+    {
+        if ((max_depth < 0) || (max_depth > 1<<20))
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+    else if (max_depth != 0)
+        return CVMX_CMD_QUEUE_INVALID_PARAM;
+
+    if ((fpa_pool < 0) || (fpa_pool > 7))
+        return CVMX_CMD_QUEUE_INVALID_PARAM;
+    if ((pool_size < 128) || (pool_size > 65536))
+        return CVMX_CMD_QUEUE_INVALID_PARAM;
+
+    /* See if someone else has already initialized the queue */
+    if (qstate->base_ptr_div128)
+    {
+        if (max_depth != (int)qstate->max_depth)
+        {
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initalized with different max_depth (%d).\n", (int)qstate->max_depth);
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+        }
+        if (fpa_pool != qstate->fpa_pool)
+        {
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initalized with different FPA pool (%u).\n", qstate->fpa_pool);
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+        }
+        if ((pool_size>>3)-1 != qstate->pool_size_m1)
+        {
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Queue already initalized with different FPA pool size (%u).\n", (qstate->pool_size_m1+1)<<3);
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+        }
+        CVMX_SYNCWS;
+        return CVMX_CMD_QUEUE_ALREADY_SETUP;
+    }
+    else
+    {
+        cvmx_fpa_ctl_status_t status;
+        void *buffer;
+
+        status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
+        if (!status.s.enb)
+        {
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: FPA is not enabled.\n");
+            return CVMX_CMD_QUEUE_NO_MEMORY;
+        }
+        buffer = cvmx_fpa_alloc(fpa_pool);
+        if (buffer == NULL)
+        {
+            cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: Unable to allocate initial buffer.\n");
+            return CVMX_CMD_QUEUE_NO_MEMORY;
+        }
+
+        memset(qstate, 0, sizeof(*qstate));
+        qstate->max_depth = max_depth;
+        qstate->fpa_pool = fpa_pool;
+        qstate->pool_size_m1 = (pool_size>>3)-1;
+        qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128;
+        /* We zeroed the now serving field so we need to also zero the ticket */
+        __cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0;
+        CVMX_SYNCWS;
+        return CVMX_CMD_QUEUE_SUCCESS;
+    }
+}
+
+
+/**
+ * Shutdown a queue a free it's command buffers to the FPA. The
+ * hardware connected to the queue must be stopped before this
+ * function is called.
+ *
+ * @param queue_id Queue to shutdown
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id)
+{
+    __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+    if (qptr == NULL)
+    {
+        cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to get queue information.\n");
+        return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+
+    if (cvmx_cmd_queue_length(queue_id) > 0)
+    {
+        cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still has data in it.\n");
+        return CVMX_CMD_QUEUE_FULL;
+    }
+
+    __cvmx_cmd_queue_lock(queue_id, qptr);
+    if (qptr->base_ptr_div128)
+    {
+        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7), qptr->fpa_pool, 0);
+        qptr->base_ptr_div128 = 0;
+    }
+    __cvmx_cmd_queue_unlock(qptr);
+
+    return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+
+/**
+ * Return the number of command words pending in the queue. This
+ * function may be relatively slow for some hardware units.
+ *
+ * @param queue_id Hardware command queue to query
+ *
+ * @return Number of outstanding commands
+ */
+int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
+{
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+    {
+        if (__cvmx_cmd_queue_get_state(queue_id) == NULL)
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+
+    /* The cast is here so gcc with check that all values in the
+        cvmx_cmd_queue_id_t enumeration are here */
+    switch ((cvmx_cmd_queue_id_t)(queue_id & 0xff0000))
+    {
+        case CVMX_CMD_QUEUE_PKO_BASE:
+            /* FIXME: Need atomic lock on CVMX_PKO_REG_READ_IDX. Right now we
+                are normally called with the queue lock, so that is a SLIGHT
+                amount of protection */
+            cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff);
+            if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+            {
+                cvmx_pko_mem_debug9_t debug9;
+                debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
+                return debug9.cn38xx.doorbell;
+            }
+            else
+            {
+                cvmx_pko_mem_debug8_t debug8;
+                debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
+                return debug8.cn58xx.doorbell;
+            }
+        case CVMX_CMD_QUEUE_ZIP:
+        case CVMX_CMD_QUEUE_DFA:
+        case CVMX_CMD_QUEUE_RAID:
+            // FIXME: Implement other lengths
+            return 0;
+        case CVMX_CMD_QUEUE_DMA_BASE:
+            {
+                cvmx_npei_dmax_counts_t dmax_counts;
+                dmax_counts.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS(queue_id & 0x7));
+                return dmax_counts.s.dbell;
+            }
+        case CVMX_CMD_QUEUE_END:
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+    return CVMX_CMD_QUEUE_INVALID_PARAM;
+}
+
+
+/**
+ * Return the command buffer to be written to. The purpose of this
+ * function is to allow CVMX routine access t othe low level buffer
+ * for initial hardware setup. User applications should not call this
+ * function directly.
+ *
+ * @param queue_id Command queue to query
+ *
+ * @return Command buffer or NULL on failure
+ */
+void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id)
+{
+    __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+    if (qptr && qptr->base_ptr_div128)
+        return cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+    else
+        return NULL;
+}
+
diff --git a/cvmx-cmd-queue.h b/cvmx-cmd-queue.h
new file mode 100644
index 0000000000000..3a928d136629e
--- /dev/null
+++ b/cvmx-cmd-queue.h
@@ -0,0 +1,604 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support functions for managing command queues used for
+ * various hardware blocks.
+ *
+ * The common command queue infrastructure abstracts out the
+ * software necessary for adding to Octeon's chained queue
+ * structures. These structures are used for commands to the
+ * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
+ * hardware unit takes commands and CSRs of different types,
+ * they all use basic linked command buffers to store the
+ * pending request. In general, users of the CVMX API don't
+ * call cvmx-cmd-queue functions directly. Instead the hardware
+ * unit specific wrapper should be used. The wrappers perform
+ * unit specific validation and CSR writes to submit the
+ * commands.
+ *
+ * Even though most software will never directly interact with
+ * cvmx-cmd-queue, knowledge of its internal working can help
+ * in diagnosing performance problems and help with debugging.
+ *
+ * Command queue pointers are stored in a global named block
+ * called "cvmx_cmd_queues". Except for the PKO queues, each
+ * hardware queue is stored in its own cache line to reduce SMP
+ * contention on spin locks. The PKO queues are stored such that
+ * every 16th queue is next to each other in memory. This scheme
+ * allows for queues being in separate cache lines when there
+ * are low number of queues per port. With 16 queues per port,
+ * the first queue for each port is in the same cache area. The
+ * second queues for each port are in another area, etc. This
+ * allows software to implement very efficient lockless PKO with
+ * 16 queues per port using a minimum of cache lines per core.
+ * All queues for a given core will be isolated in the same
+ * cache area.
+ *
+ * In addition to the memory pointer layout, cvmx-cmd-queue
+ * provides an optimized fair ll/sc locking mechanism for the
+ * queues. The lock uses a "ticket / now serving" model to
+ * maintain fair order on contended locks. In addition, it uses
+ * predicted locking time to limit cache contention. When a core
+ * know it must wait in line for a lock, it spins on the
+ * internal cycle counter to completely eliminate any causes of
+ * bus traffic.
+ *
+ * <hr> $Revision: 42150 $ <hr>
+ */
+
+#ifndef __CVMX_CMD_QUEUE_H__
+#define __CVMX_CMD_QUEUE_H__
+
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx-fpa.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * By default we disable the max depth support. Most programs
+ * don't use it and it slows down the command queue processing
+ * significantly.
+ */
+#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
+#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
+#endif
+
+/**
+ * Enumeration representing all hardware blocks that use command
+ * queues. Each hardware block has up to 65536 sub identifiers for
+ * multiple command queues. Not all chips support all hardware
+ * units.
+ */
+typedef enum
+{
+    CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
+#define CVMX_CMD_QUEUE_PKO(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
+    CVMX_CMD_QUEUE_ZIP      = 0x10000,
+    CVMX_CMD_QUEUE_DFA      = 0x20000,
+    CVMX_CMD_QUEUE_RAID     = 0x30000,
+    CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
+#define CVMX_CMD_QUEUE_DMA(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
+    CVMX_CMD_QUEUE_END      = 0x50000,
+} cvmx_cmd_queue_id_t;
+
+/**
+ * Command write operations can fail if the comamnd queue needs
+ * a new buffer and the associated FPA pool is empty. It can also
+ * fail if the number of queued command words reaches the maximum
+ * set at initialization.
+ */
+typedef enum
+{
+    CVMX_CMD_QUEUE_SUCCESS = 0,
+    CVMX_CMD_QUEUE_NO_MEMORY = -1,
+    CVMX_CMD_QUEUE_FULL = -2,
+    CVMX_CMD_QUEUE_INVALID_PARAM = -3,
+    CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
+} cvmx_cmd_queue_result_t;
+
+typedef struct
+{
+    uint8_t  now_serving;           /**< You have lock when this is your ticket */
+    uint64_t unused1        : 24;
+    uint32_t max_depth;             /**< Maximum outstanding command words */
+    uint64_t fpa_pool       : 3;    /**< FPA pool buffers come from */
+    uint64_t base_ptr_div128: 29;   /**< Top of command buffer pointer shifted 7 */
+    uint64_t unused2        : 6;
+    uint64_t pool_size_m1   : 13;   /**< FPA buffer size in 64bit words minus 1 */
+    uint64_t index          : 13;   /**< Number of comamnds already used in buffer */
+} __cvmx_cmd_queue_state_t;
+
+/**
+ * This structure contains the global state of all comamnd queues.
+ * It is stored in a bootmem named block and shared by all
+ * applications running on Octeon. Tickets are stored in a differnet
+ * cahce line that queue information to reduce the contention on the
+ * ll/sc used to get a ticket. If this is not the case, the update
+ * of queue state causes the ll/sc to fail quite often.
+ */
+typedef struct
+{
+    uint64_t                 ticket[(CVMX_CMD_QUEUE_END>>16) * 256];
+    __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END>>16) * 256];
+} __cvmx_cmd_queue_all_state_t;
+
+/**
+ * Initialize a command queue for use. The initial FPA buffer is
+ * allocated and the hardware unit is configured to point to the
+ * new command queue.
+ *
+ * @param queue_id  Hardware command queue to initialize.
+ * @param max_depth Maximum outstanding commands that can be queued.
+ * @param fpa_pool  FPA pool the command queues should come from.
+ * @param pool_size Size of each buffer in the FPA pool (bytes)
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, int max_depth, int fpa_pool, int pool_size);
+
+/**
+ * Shutdown a queue a free it's command buffers to the FPA. The
+ * hardware connected to the queue must be stopped before this
+ * function is called.
+ *
+ * @param queue_id Queue to shutdown
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Return the number of command words pending in the queue. This
+ * function may be relatively slow for some hardware units.
+ *
+ * @param queue_id Hardware command queue to query
+ *
+ * @return Number of outstanding commands
+ */
+int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Return the command buffer to be written to. The purpose of this
+ * function is to allow CVMX routine access t othe low level buffer
+ * for initial hardware setup. User applications should not call this
+ * function directly.
+ *
+ * @param queue_id Command queue to query
+ *
+ * @return Command buffer or NULL on failure
+ */
+void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * @INTERNAL
+ * Get the index into the state arrays for the supplied queue id.
+ *
+ * @param queue_id Queue ID to get an index for
+ *
+ * @return Index into the state arrays
+ */
+static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
+{
+    /* Warning: This code currently only works with devices that have 256 queues
+        or less. Devices with more than 16 queues are layed out in memory to allow
+        cores quick access to every 16th queue. This reduces cache thrashing
+        when you are running 16 queues per port to support lockless operation */
+    int unit = queue_id>>16;
+    int q = (queue_id >> 4) & 0xf;
+    int core = queue_id & 0xf;
+    return unit*256 + core*16 + q;
+}
+
+
+/**
+ * @INTERNAL
+ * Lock the supplied queue so nobody else is updating it at the same
+ * time as us.
+ *
+ * @param queue_id Queue ID to lock
+ * @param qptr     Pointer to the queue's global state
+ */
+static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, __cvmx_cmd_queue_state_t *qptr)
+{
+    extern CVMX_SHARED __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
+    int tmp;
+    int my_ticket;
+    CVMX_PREFETCH(qptr, 0);
+    asm volatile (
+        ".set push\n"
+        ".set noreorder\n"
+        "1:\n"
+        "ll     %[my_ticket], %[ticket_ptr]\n"          /* Atomic add one to ticket_ptr */
+        "li     %[ticket], 1\n"                         /*    and store the original value */
+        "baddu  %[ticket], %[my_ticket]\n"              /*    in my_ticket */
+        "sc     %[ticket], %[ticket_ptr]\n"
+        "beqz   %[ticket], 1b\n"
+        " nop\n"
+        "lbu    %[ticket], %[now_serving]\n"            /* Load the current now_serving ticket */
+        "2:\n"
+        "beq    %[ticket], %[my_ticket], 4f\n"          /* Jump out if now_serving == my_ticket */
+        " subu   %[ticket], %[my_ticket], %[ticket]\n"  /* Find out how many tickets are in front of me */
+        "subu  %[ticket], 1\n"                          /* Use tickets in front of me minus one to delay */
+        "cins   %[ticket], %[ticket], 5, 7\n"           /* Delay will be ((tickets in front)-1)*32 loops */
+        "3:\n"
+        "bnez   %[ticket], 3b\n"                        /* Loop here until our ticket might be up */
+        " subu  %[ticket], 1\n"
+        "b      2b\n"                                   /* Jump back up to check out ticket again */
+        " lbu   %[ticket], %[now_serving]\n"            /* Load the current now_serving ticket */
+        "4:\n"
+        ".set pop\n"
+        : [ticket_ptr] "=m" (__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
+          [now_serving] "=m" (qptr->now_serving),
+          [ticket] "=r" (tmp),
+          [my_ticket] "=r" (my_ticket)
+    );
+}
+
+
+/**
+ * @INTERNAL
+ * Unlock the queue, flushing all writes.
+ *
+ * @param qptr   Queue to unlock
+ */
+static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
+{
+    qptr->now_serving++;
+    CVMX_SYNCWS;
+}
+
+
+/**
+ * @INTERNAL
+ * Get the queue state structure for the given queue id
+ *
+ * @param queue_id Queue id to get
+ *
+ * @return Queue structure or NULL on failure
+ */
+static inline __cvmx_cmd_queue_state_t *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
+{
+    extern CVMX_SHARED __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+    {
+        if (cvmx_unlikely(queue_id >= CVMX_CMD_QUEUE_END))
+            return NULL;
+        if (cvmx_unlikely((queue_id & 0xffff) >= 256))
+            return NULL;
+    }
+    return &__cvmx_cmd_queue_state_ptr->state[__cvmx_cmd_queue_get_index(queue_id)];
+}
+
+
+/**
+ * Write an arbitrary number of command words to a command queue.
+ * This is a generic function; the fixed number of comamnd word
+ * functions yield higher performance.
+ *
+ * @param queue_id  Hardware command queue to write to
+ * @param use_locking
+ *                  Use internal locking to ensure exclusive access for queue
+ *                  updates. If you don't use this locking you must ensure
+ *                  exclusivity some other way. Locking is strongly recommended.
+ * @param cmd_count Number of command words to write
+ * @param cmds      Array of comamnds to write
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t queue_id, int use_locking, int cmd_count, uint64_t *cmds)
+{
+    __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+    {
+        if (cvmx_unlikely(qptr == NULL))
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+        if (cvmx_unlikely((cmd_count < 1) || (cmd_count > 32)))
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+        if (cvmx_unlikely(cmds == NULL))
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+
+    /* Make sure nobody else is updating the same queue */
+    if (cvmx_likely(use_locking))
+        __cvmx_cmd_queue_lock(queue_id, qptr);
+
+    /* If a max queue length was specified then make sure we don't
+        exceed it. If any part of the command would be below the limit
+        we allow it */
+    if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && cvmx_unlikely(qptr->max_depth))
+    {
+        if (cvmx_unlikely(cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth))
+        {
+            if (cvmx_likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+            return CVMX_CMD_QUEUE_FULL;
+        }
+    }
+
+    /* Normally there is plenty of room in the current buffer for the command */
+    if (cvmx_likely(qptr->index + cmd_count < qptr->pool_size_m1))
+    {
+        uint64_t *ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+        ptr += qptr->index;
+        qptr->index += cmd_count;
+        while (cmd_count--)
+            *ptr++ = *cmds++;
+    }
+    else
+    {
+        uint64_t *ptr;
+        int count;
+        /* We need a new comamnd buffer. Fail if there isn't one available */
+        uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
+        if (cvmx_unlikely(new_buffer == NULL))
+        {
+            if (cvmx_likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+            return CVMX_CMD_QUEUE_NO_MEMORY;
+        }
+        ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+        /* Figure out how many command words will fit in this buffer. One
+            location will be needed for the next buffer pointer */
+        count = qptr->pool_size_m1 - qptr->index;
+        ptr += qptr->index;
+        cmd_count-=count;
+        while (count--)
+            *ptr++ = *cmds++;
+        *ptr = cvmx_ptr_to_phys(new_buffer);
+        /* The current buffer is full and has a link to the next buffer. Time
+            to write the rest of the commands into the new buffer */
+        qptr->base_ptr_div128 = *ptr >> 7;
+        qptr->index = cmd_count;
+        ptr = new_buffer;
+        while (cmd_count--)
+            *ptr++ = *cmds++;
+    }
+
+    /* All updates are complete. Release the lock and return */
+    if (cvmx_likely(use_locking))
+        __cvmx_cmd_queue_unlock(qptr);
+    return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+
+/**
+ * Simple function to write two command words to a command
+ * queue.
+ *
+ * @param queue_id Hardware command queue to write to
+ * @param use_locking
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.
+ * @param cmd1     Command
+ * @param cmd2     Command
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t queue_id, int use_locking, uint64_t cmd1, uint64_t cmd2)
+{
+    __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+    {
+        if (cvmx_unlikely(qptr == NULL))
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+
+    /* Make sure nobody else is updating the same queue */
+    if (cvmx_likely(use_locking))
+        __cvmx_cmd_queue_lock(queue_id, qptr);
+
+    /* If a max queue length was specified then make sure we don't
+        exceed it. If any part of the command would be below the limit
+        we allow it */
+    if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && cvmx_unlikely(qptr->max_depth))
+    {
+        if (cvmx_unlikely(cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth))
+        {
+            if (cvmx_likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+            return CVMX_CMD_QUEUE_FULL;
+        }
+    }
+
+    /* Normally there is plenty of room in the current buffer for the command */
+    if (cvmx_likely(qptr->index + 2 < qptr->pool_size_m1))
+    {
+        uint64_t *ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+        ptr += qptr->index;
+        qptr->index += 2;
+        ptr[0] = cmd1;
+        ptr[1] = cmd2;
+    }
+    else
+    {
+        uint64_t *ptr;
+        /* Figure out how many command words will fit in this buffer. One
+            location will be needed for the next buffer pointer */
+        int count = qptr->pool_size_m1 - qptr->index;
+        /* We need a new comamnd buffer. Fail if there isn't one available */
+        uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
+        if (cvmx_unlikely(new_buffer == NULL))
+        {
+            if (cvmx_likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+            return CVMX_CMD_QUEUE_NO_MEMORY;
+        }
+        count--;
+        ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+        ptr += qptr->index;
+        *ptr++ = cmd1;
+        if (cvmx_likely(count))
+            *ptr++ = cmd2;
+        *ptr = cvmx_ptr_to_phys(new_buffer);
+        /* The current buffer is full and has a link to the next buffer. Time
+            to write the rest of the commands into the new buffer */
+        qptr->base_ptr_div128 = *ptr >> 7;
+        qptr->index = 0;
+        if (cvmx_unlikely(count == 0))
+        {
+            qptr->index = 1;
+            new_buffer[0] = cmd2;
+        }
+    }
+
+    /* All updates are complete. Release the lock and return */
+    if (cvmx_likely(use_locking))
+        __cvmx_cmd_queue_unlock(qptr);
+    return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+
+/**
+ * Simple function to write three command words to a command
+ * queue.
+ *
+ * @param queue_id Hardware command queue to write to
+ * @param use_locking
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.
+ * @param cmd1     Command
+ * @param cmd2     Command
+ * @param cmd3     Command
+ *
+ * @return CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t queue_id, int use_locking, uint64_t cmd1, uint64_t cmd2, uint64_t cmd3)
+{
+    __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+    if (CVMX_ENABLE_PARAMETER_CHECKING)
+    {
+        if (cvmx_unlikely(qptr == NULL))
+            return CVMX_CMD_QUEUE_INVALID_PARAM;
+    }
+
+    /* Make sure nobody else is updating the same queue */
+    if (cvmx_likely(use_locking))
+        __cvmx_cmd_queue_lock(queue_id, qptr);
+
+    /* If a max queue length was specified then make sure we don't
+        exceed it. If any part of the command would be below the limit
+        we allow it */
+    if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && cvmx_unlikely(qptr->max_depth))
+    {
+        if (cvmx_unlikely(cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth))
+        {
+            if (cvmx_likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+            return CVMX_CMD_QUEUE_FULL;
+        }
+    }
+
+    /* Normally there is plenty of room in the current buffer for the command */
+    if (cvmx_likely(qptr->index + 3 < qptr->pool_size_m1))
+    {
+        uint64_t *ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+        ptr += qptr->index;
+        qptr->index += 3;
+        ptr[0] = cmd1;
+        ptr[1] = cmd2;
+        ptr[2] = cmd3;
+    }
+    else
+    {
+        uint64_t *ptr;
+        /* Figure out how many command words will fit in this buffer. One
+            location will be needed for the next buffer pointer */
+        int count = qptr->pool_size_m1 - qptr->index;
+        /* We need a new comamnd buffer. Fail if there isn't one available */
+        uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
+        if (cvmx_unlikely(new_buffer == NULL))
+        {
+            if (cvmx_likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+            return CVMX_CMD_QUEUE_NO_MEMORY;
+        }
+        count--;
+        ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
+        ptr += qptr->index;
+        *ptr++ = cmd1;
+        if (count)
+        {
+            *ptr++ = cmd2;
+            if (count > 1)
+                *ptr++ = cmd3;
+        }
+        *ptr = cvmx_ptr_to_phys(new_buffer);
+        /* The current buffer is full and has a link to the next buffer. Time
+            to write the rest of the commands into the new buffer */
+        qptr->base_ptr_div128 = *ptr >> 7;
+        qptr->index = 0;
+        ptr = new_buffer;
+        if (count == 0)
+        {
+            *ptr++ = cmd2;
+            qptr->index++;
+        }
+        if (count < 2)
+        {
+            *ptr++ = cmd3;
+            qptr->index++;
+        }
+    }
+
+    /* All updates are complete. Release the lock and return */
+    if (cvmx_likely(use_locking))
+        __cvmx_cmd_queue_unlock(qptr);
+    return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_CMD_QUEUE_H__ */
diff --git a/cvmx-cn3010-evb-hs5.c b/cvmx-cn3010-evb-hs5.c
new file mode 100644
index 0000000000000..3a3c43e241e46
--- /dev/null
+++ b/cvmx-cn3010-evb-hs5.c
@@ -0,0 +1,214 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the EBH-30xx specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include <time.h>
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-cn3010-evb-hs5.h"
+#include "cvmx-twsi.h"
+
+
+static inline uint8_t bin2bcd(uint8_t bin)
+{
+    return (bin / 10) << 4 | (bin % 10);
+}
+
+static inline uint8_t bcd2bin(uint8_t bcd)
+{
+    return (bcd >> 4) * 10 + (bcd & 0xf);
+}
+
+#define TM_CHECK(_expr, _msg) \
+        do { \
+            if (_expr) { \
+                cvmx_dprintf("Warning: RTC has invalid %s field\n", (_msg)); \
+                rc = -1; \
+            } \
+        } while(0);
+
+static int validate_tm_struct(struct tm * tms)
+{
+    int rc = 0;
+
+    if (!tms)
+	return -1;
+
+    TM_CHECK(tms->tm_sec < 0  || tms->tm_sec > 60,  "second"); /* + Leap sec */
+    TM_CHECK(tms->tm_min < 0  || tms->tm_min > 59,  "minute");
+    TM_CHECK(tms->tm_hour < 0 || tms->tm_hour > 23, "hour");
+    TM_CHECK(tms->tm_mday < 1 || tms->tm_mday > 31, "day");
+    TM_CHECK(tms->tm_wday < 0 || tms->tm_wday > 6,  "day of week");
+    TM_CHECK(tms->tm_mon < 0  || tms->tm_mon > 11,  "month");
+    TM_CHECK(tms->tm_year < 0 || tms->tm_year > 200,"year");
+
+    return rc;
+}
+
+/*
+ * Board-specifc RTC read
+ * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ * and converted internally to calendar format.
+ */
+uint32_t cvmx_rtc_ds1337_read(void)
+{
+    int       i, retry;
+    uint32_t  time;
+    uint8_t   reg[8];
+    uint8_t   sec;
+    struct tm tms;
+
+
+    memset(&reg, 0, sizeof(reg));
+    memset(&tms, 0, sizeof(struct tm));
+
+    for(retry=0; retry<2; retry++)
+    {
+	/* Lockless read: detects the infrequent roll-over and retries */
+	reg[0] = cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0);
+	for(i=1; i<7; i++)
+	    reg[i] = cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1337_ADDR);
+
+	sec = cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0);
+	if ((sec & 0xf) == (reg[0] & 0xf))
+	    break; /* Time did not roll-over, value is correct */
+    }
+
+    tms.tm_sec  = bcd2bin(reg[0] & 0x7f);
+    tms.tm_min  = bcd2bin(reg[1] & 0x7f);
+    tms.tm_hour = bcd2bin(reg[2] & 0x3f);
+    if ((reg[2] & 0x40) && (reg[2] & 0x20))   /* AM/PM format and is PM time */
+    {
+	tms.tm_hour = (tms.tm_hour + 12) % 24;
+    }
+    tms.tm_wday = (reg[3] & 0x7) - 1;         /* Day of week field is 0..6 */
+    tms.tm_mday = bcd2bin(reg[4] & 0x3f);
+    tms.tm_mon  = bcd2bin(reg[5] & 0x1f) - 1; /* Month field is 0..11 */
+    tms.tm_year = ((reg[5] & 0x80) ? 100 : 0) + bcd2bin(reg[6]);
+
+
+    if (validate_tm_struct(&tms))
+	cvmx_dprintf("Warning: RTC calendar is not configured properly\n");
+
+    time = mktime(&tms);
+
+    return time;
+}
+
+/*
+ * Board-specific RTC write
+ * Time returned is in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ */
+int cvmx_rtc_ds1337_write(uint32_t time)
+{
+    int       i, rc, retry;
+    struct tm tms;
+    uint8_t   reg[8];
+    uint8_t   sec;
+    time_t    time_from_epoch = time;
+
+
+    localtime_r(&time_from_epoch, &tms);
+
+    if (validate_tm_struct(&tms))
+    {
+	cvmx_dprintf("Error: RTC was passed wrong calendar values, write failed\n");
+	goto tm_invalid;
+    }
+
+    reg[0] = bin2bcd(tms.tm_sec);
+    reg[1] = bin2bcd(tms.tm_min);
+    reg[2] = bin2bcd(tms.tm_hour);      /* Force 0..23 format even if using AM/PM */
+    reg[3] = bin2bcd(tms.tm_wday + 1);
+    reg[4] = bin2bcd(tms.tm_mday);
+    reg[5] = bin2bcd(tms.tm_mon + 1);
+    if (tms.tm_year >= 100)             /* Set century bit*/
+    {
+	reg[5] |= 0x80;
+    }
+    reg[6] = bin2bcd(tms.tm_year % 100);
+
+    /* Lockless write: detects the infrequent roll-over and retries */
+    for(retry=0; retry<2; retry++)
+    {
+	rc = 0;
+	for(i=0; i<7; i++)
+	{
+	    rc |= cvmx_twsi_write8(CVMX_RTC_DS1337_ADDR, i, reg[i]);
+	}
+
+	sec = cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0);
+	if ((sec & 0xf) == (reg[0] & 0xf))
+	    break; /* Time did not roll-over, value is correct */
+    }
+
+    return (rc ? -1 : 0);
+
+ tm_invalid:
+    return -1;
+}
+
+#ifdef CVMX_RTC_DEBUG
+
+void cvmx_rtc_ds1337_dump_state(void)
+{
+    int i = 0;
+
+    printf("RTC:\n");
+    printf("%d : %02X ", i, cvmx_twsi_read8(CVMX_RTC_DS1337_ADDR, 0x0));
+    for(i=1; i<16; i++) {
+	printf("%02X ", cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1337_ADDR));
+    }
+    printf("\n");
+}
+
+#endif /* CVMX_RTC_DEBUG */
diff --git a/cvmx-cn3010-evb-hs5.h b/cvmx-cn3010-evb-hs5.h
new file mode 100644
index 0000000000000..af65496a7b5c0
--- /dev/null
+++ b/cvmx-cn3010-evb-hs5.h
@@ -0,0 +1,69 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+#ifndef __CVMX_CN3010_EVB_HS5_H__
+#define __CVMX_CN3010_EVB_HS5_H__
+
+/**
+ * @file
+ *
+ * Interface to the EBH-30xx specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_RTC_DS1337_ADDR   (0x68)
+
+uint32_t cvmx_rtc_ds1337_read(void);
+int      cvmx_rtc_ds1337_write(uint32_t time);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_CN3010_EVB_HS5_H__ */
diff --git a/cvmx-compactflash.c b/cvmx-compactflash.c
new file mode 100644
index 0000000000000..eca620a6c06ed
--- /dev/null
+++ b/cvmx-compactflash.c
@@ -0,0 +1,431 @@
+/***********************license start***************
+ *  Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-compactflash.h"
+
+
+#ifndef MAX
+#define	MAX(a,b) (((a)>(b))?(a):(b))
+#endif
+#define FLASH_RoundUP(_Dividend, _Divisor) (((_Dividend)+(_Divisor-1))/(_Divisor))
+/**
+ * Convert nanosecond based time to setting used in the
+ * boot bus timing register, based on timing multiple
+ * 
+ * 
+ */
+static uint32_t ns_to_tim_reg(int tim_mult, uint32_t nsecs)
+{
+	uint32_t val;
+
+	/* Compute # of eclock periods to get desired duration in nanoseconds */
+	val = FLASH_RoundUP(nsecs * (cvmx_sysinfo_get()->cpu_clock_hz/1000000), 1000);
+	
+	/* Factor in timing multiple, if not 1 */
+	if (tim_mult != 1)
+		val = FLASH_RoundUP(val, tim_mult);
+	
+	return (val);
+}
+
+uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data, int *mwdma_mode_ptr)
+{
+
+	cvmx_mio_boot_dma_timx_t dma_tim;
+	int oe_a;
+	int oe_n;
+	int dma_acks;
+	int dma_ackh;
+	int dma_arq;
+	int pause;
+	int To,Tkr,Td;
+	int mwdma_mode = -1;
+        uint16_t word53_field_valid;
+        uint16_t word63_mwdma;
+        uint16_t word163_adv_timing_info;
+
+        if (!ident_data)
+            return 0;
+
+        word53_field_valid = ident_data[53];
+        word63_mwdma = ident_data[63]; 
+        word163_adv_timing_info = ident_data[163];
+
+	dma_tim.u64 = 0;
+
+	/* Check for basic MWDMA modes */
+	if (word53_field_valid & 0x2)
+	{
+		if (word63_mwdma & 0x4)
+			mwdma_mode = 2;
+		else if (word63_mwdma & 0x2)
+			mwdma_mode = 1;
+		else if (word63_mwdma & 0x1)
+			mwdma_mode = 0;
+	}
+
+	/* Check for advanced MWDMA modes */
+	switch ((word163_adv_timing_info >> 3) & 0x7)
+	{
+		case 1:
+			mwdma_mode = 3;
+			break;
+		case 2:
+			mwdma_mode = 4;
+			break;
+		default:
+			break;
+
+	}
+	/* DMA is not supported by this card */
+	if (mwdma_mode < 0)
+            return 0;
+
+	/* Now set up the DMA timing */
+	switch (tim_mult)
+	{
+		case 1:
+		    dma_tim.s.tim_mult = 1;
+		    break;
+		case 2:
+		    dma_tim.s.tim_mult = 2;
+		    break;
+		case 4:
+		    dma_tim.s.tim_mult = 0;
+		    break;
+		case 8:
+		    dma_tim.s.tim_mult = 3;
+		    break;
+		default:
+		    cvmx_dprintf("ERROR: invalid boot bus dma tim_mult setting\n");
+		    break;
+	}
+
+
+	switch (mwdma_mode)
+	{
+		case 4:
+			To = 80;
+			Td = 55;
+			Tkr = 20;
+			
+			oe_a = Td + 20;  // Td (Seem to need more margin here....
+			oe_n = MAX(To - oe_a, Tkr);  // Tkr from cf spec, lengthened to meet To
+			
+			// oe_n + oe_h must be >= To (cycle time)
+			dma_acks = 0; //Ti
+			dma_ackh = 5; // Tj
+			
+			dma_arq = 8;  // not spec'ed, value in eclocks, not affected by tim_mult
+			pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
+			break;
+		case 3:
+			To = 100;
+			Td = 65;
+			Tkr = 20;
+			
+			oe_a = Td + 20;  // Td (Seem to need more margin here....
+			oe_n = MAX(To - oe_a, Tkr);  // Tkr from cf spec, lengthened to meet To
+			
+			// oe_n + oe_h must be >= To (cycle time)
+			dma_acks = 0; //Ti
+			dma_ackh = 5; // Tj
+			
+			dma_arq = 8;  // not spec'ed, value in eclocks, not affected by tim_mult
+			pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
+			break;
+		case 2:
+			// +20 works
+			// +10 works
+			// + 10 + 0 fails
+			// n=40, a=80 works
+			To = 120;
+			Td = 70;
+			Tkr = 25;
+
+                        // oe_a 0 fudge doesn't work; 10 seems to
+			oe_a = Td + 20 + 10;  // Td (Seem to need more margin here....
+			oe_n = MAX(To - oe_a, Tkr) + 10;  // Tkr from cf spec, lengthened to meet To
+                        // oe_n 0 fudge fails;;; 10 boots
+
+                        // 20 ns fudge needed on dma_acks
+			// oe_n + oe_h must be >= To (cycle time)
+			dma_acks = 0 + 20; //Ti
+			dma_ackh = 5; // Tj
+			
+			dma_arq = 8;  // not spec'ed, value in eclocks, not affected by tim_mult
+			pause = 25 - dma_arq * 1000/(cvmx_sysinfo_get()->cpu_clock_hz/1000000); // Tz
+                        // no fudge needed on pause
+			
+			break;
+		case 1:
+		case 0:
+		default:
+			cvmx_dprintf("ERROR: Unsupported DMA mode: %d\n", mwdma_mode);
+			return(-1);
+			break;
+	}
+
+        if (mwdma_mode_ptr)
+            *mwdma_mode_ptr = mwdma_mode;
+	
+	dma_tim.s.dmack_pi = 1;
+	
+	dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
+	dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
+	
+	dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, dma_acks);
+	dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh); 
+	
+	dma_tim.s.dmarq = dma_arq;
+	dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
+	
+	dma_tim.s.rd_dly = 0; /* Sample right on edge */
+	
+	/*  writes only */
+	dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
+	dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
+	
+#if 0
+	cvmx_dprintf("ns to ticks (mult %d) of %d is: %d\n", TIM_MULT, 60, ns_to_tim_reg(60));
+	cvmx_dprintf("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
+	   dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
+#endif
+
+	return(dma_tim.u64);
+
+
+}
+
+
+/**
+ * Setup timing and region config to support a specific IDE PIO
+ * mode over the bootbus.
+ *
+ * @param cs0      Bootbus region number connected to CS0 on the IDE device
+ * @param cs1      Bootbus region number connected to CS1 on the IDE device
+ * @param pio_mode PIO mode to set (0-6)
+ */
+void cvmx_compactflash_set_piomode(int cs0, int cs1, int pio_mode)
+{
+    cvmx_mio_boot_reg_cfgx_t mio_boot_reg_cfg;
+    cvmx_mio_boot_reg_timx_t mio_boot_reg_tim;
+    int cs;
+    int clocks_us;                      /* Number of clock cycles per microsec */
+    int tim_mult;
+    int use_iordy;                      /* Set for PIO0-4, not set for PIO5-6 */
+    int t1;                             /* These t names are timing parameters from the ATA spec */
+    int t2;
+    int t2i;
+    int t4;
+    int t6;
+    int t6z;
+    int t9;
+
+    /* PIO modes 0-4 all allow the device to deassert IORDY to slow down
+        the host */
+    use_iordy = 1;
+
+    /* Use the PIO mode to determine timing parameters */
+    switch(pio_mode) {
+        case 6:
+            /* CF spec say IORDY should be ignore in PIO 5 */
+            use_iordy = 0;
+            t1 = 10;
+            t2 = 55;
+            t2i = 20;
+            t4 = 5;
+            t6 = 5;
+            t6z = 20;
+            t9 = 10;
+            break;
+        case 5:
+            /* CF spec say IORDY should be ignore in PIO 6 */
+            use_iordy = 0;
+            t1 = 15;
+            t2 = 65;
+            t2i = 25;
+            t4 = 5;
+            t6 = 5;
+            t6z = 20;
+            t9 = 10;
+            break;
+        case 4:
+            t1 = 25;
+            t2 = 70;
+            t2i = 25;
+            t4 = 10;
+            t6 = 5;
+            t6z = 30;
+            t9 = 10;
+            break;
+        case 3:
+            t1 = 30;
+            t2 = 80;
+            t2i = 70;
+            t4 = 10;
+            t6 = 5;
+            t6z = 30;
+            t9 = 10;
+            break;
+        case 2:
+            t1 = 30;
+            t2 = 100;
+            t2i = 0;
+            t4 = 15;
+            t6 = 5;
+            t6z = 30;
+            t9 = 10;
+            break;
+        case 1:
+            t1 = 50;
+            t2 = 125;
+            t2i = 0;
+            t4 = 20;
+            t6 = 5;
+            t6z = 30;
+            t9 = 15;
+            break;
+        default:
+            t1 = 70;
+            t2 = 165;
+            t2i = 0;
+            t4 = 30;
+            t6 = 5;
+            t6z = 30;
+            t9 = 20;
+            break;
+    }
+    /* Convert times in ns to clock cycles, rounding up */
+    clocks_us = FLASH_RoundUP((uint64_t)cvmx_sysinfo_get()->cpu_clock_hz, 1000000);
+
+    /* Convert times in clock cycles, rounding up. Octeon parameters are in
+        minus one notation, so take off one after the conversion */
+    t1 = FLASH_RoundUP(t1 * clocks_us, 1000);
+    if (t1)
+        t1--;
+    t2 = FLASH_RoundUP(t2 * clocks_us, 1000);
+    if (t2)
+        t2--;
+    t2i = FLASH_RoundUP(t2i * clocks_us, 1000);
+    if (t2i)
+        t2i--;
+    t4 = FLASH_RoundUP(t4 * clocks_us, 1000);
+    if (t4)
+        t4--;
+    t6 = FLASH_RoundUP(t6 * clocks_us, 1000);
+    if (t6)
+        t6--;
+    t6z = FLASH_RoundUP(t6z * clocks_us, 1000);
+    if (t6z)
+        t6z--;
+    t9 = FLASH_RoundUP(t9 * clocks_us, 1000);
+    if (t9)
+        t9--;
+
+    /* Start using a scale factor of one cycle. Keep doubling it until
+        the parameters fit in their fields. Since t2 is the largest number,
+        we only need to check it */
+    tim_mult = 1;
+    while (t2 >= 1<<6)
+    {
+        t1 = FLASH_RoundUP(t1, 2);
+        t2 = FLASH_RoundUP(t2, 2);
+        t2i = FLASH_RoundUP(t2i, 2);
+        t4 = FLASH_RoundUP(t4, 2);
+        t6 = FLASH_RoundUP(t6, 2);
+        t6z = FLASH_RoundUP(t6z, 2);
+        t9 = FLASH_RoundUP(t9, 2);
+        tim_mult *= 2;
+    }
+
+    cs = cs0;
+    do {
+        mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
+        mio_boot_reg_cfg.s.dmack = 0;   /* Don't assert DMACK on access */
+        switch(tim_mult) {
+            case 1:
+                mio_boot_reg_cfg.s.tim_mult = 1;
+                break;
+            case 2:
+                mio_boot_reg_cfg.s.tim_mult = 2;
+                break;
+            case 4:
+                mio_boot_reg_cfg.s.tim_mult = 0;
+                break;
+            case 8:
+            default:
+                mio_boot_reg_cfg.s.tim_mult = 3;
+                break;
+        }
+        mio_boot_reg_cfg.s.rd_dly = 0;  /* Sample on falling edge of BOOT_OE */
+        mio_boot_reg_cfg.s.sam = 0;     /* Don't combine write and output enable */
+        mio_boot_reg_cfg.s.we_ext = 0;  /* No write enable extension */
+        mio_boot_reg_cfg.s.oe_ext = 0;  /* No read enable extension */
+        mio_boot_reg_cfg.s.en = 1;      /* Enable this region */
+        mio_boot_reg_cfg.s.orbit = 0;   /* Don't combine with previos region */
+        mio_boot_reg_cfg.s.width = 1;   /* 16 bits wide */
+        cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), mio_boot_reg_cfg.u64);
+        if(cs == cs0)
+            cs = cs1;
+        else
+            cs = cs0;
+    } while(cs != cs0);
+
+    mio_boot_reg_tim.u64 = 0;
+    mio_boot_reg_tim.s.pagem = 0;       /* Disable page mode */
+    mio_boot_reg_tim.s.waitm = use_iordy;    /* Enable dynamic timing */
+    mio_boot_reg_tim.s.pages = 0;       /* Pages are disabled */
+    mio_boot_reg_tim.s.ale = 8;         /* If someone uses ALE, this seems to work */
+    mio_boot_reg_tim.s.page = 0;        /* Not used */
+    mio_boot_reg_tim.s.wait = 0;        /* Time after IORDY to coninue to assert the data */
+    mio_boot_reg_tim.s.pause = 0;       /* Time after CE that signals stay valid */
+    mio_boot_reg_tim.s.wr_hld = t9;     /* How long to hold after a write */
+    mio_boot_reg_tim.s.rd_hld = t9;     /* How long to wait after a read for device to tristate */
+    mio_boot_reg_tim.s.we = t2;         /* How long write enable is asserted */
+    mio_boot_reg_tim.s.oe = t2;         /* How long read enable is asserted */
+    mio_boot_reg_tim.s.ce = t1;         /* Time after CE that read/write starts */
+    mio_boot_reg_tim.s.adr = 1;         /* Time before CE that address is valid */
+
+    /* Program the bootbus region timing for both chip selects */
+    cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs0), mio_boot_reg_tim.u64);
+    cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs1), mio_boot_reg_tim.u64);
+}
diff --git a/cvmx-compactflash.h b/cvmx-compactflash.h
new file mode 100644
index 0000000000000..dd6d9cfae68ff
--- /dev/null
+++ b/cvmx-compactflash.h
@@ -0,0 +1,76 @@
+/***********************license start***************
+ *  Copyright (c) 2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+#ifndef __CVMX_COMPACTFLASH_H__
+#define __CVMX_COMPACTFLASH_H__
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * This function takes values from the compact flash device
+ * identify response, and returns the appropriate value to write
+ * into the boot bus DMA timing register.
+ *
+ * @param tim_mult   Eclock timing multiple to use
+ * @param ident_data Data returned by the 'identify' command.  This is used to
+ *                   determine the DMA modes supported by the card, if any.
+ * @param mwdma_mode_ptr
+ *                   Optional pointer to return MWDMA mode in
+ *
+ * @return 64 bit value to write to DMA timing register
+ */
+extern uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data, int *mwdma_mode_ptr);
+
+/**
+ * Setup timing and region config to support a specific IDE PIO
+ * mode over the bootbus.
+ *
+ * @param cs0      Bootbus region number connected to CS0 on the IDE device
+ * @param cs1      Bootbus region number connected to CS1 on the IDE device
+ * @param pio_mode PIO mode to set (0-6)
+ */
+extern void cvmx_compactflash_set_piomode(int cs0, int cs1, int pio_mode);
+
+#ifdef	__cplusplus
+}
+#endif
+#endif   /* __CVMX_COMPACTFLASH_H__ */
diff --git a/cvmx-core.c b/cvmx-core.c
new file mode 100644
index 0000000000000..43d8eee00dc1d
--- /dev/null
+++ b/cvmx-core.c
@@ -0,0 +1,147 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Module to support operations on core such as TLB config, etc.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-core.h"
+
+
+/**
+ * Adds a wired TLB entry, and returns the index of the entry added.
+ * Parameters are written to TLB registers without further processing.
+ *
+ * @param hi     HI register value
+ * @param lo0    lo0 register value
+ * @param lo1    lo1 register value
+ * @param page_mask   pagemask register value
+ *
+ * @return Success: TLB index used (0-31) or (0-63) for OCTEON Plus
+ *         Failure: -1
+ */
+int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask)
+{
+    uint32_t index;
+    uint32_t index_limit = 31;
+
+    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+    {
+        index_limit=63;
+    }
+
+    CVMX_MF_TLB_WIRED(index);
+    if (index >= index_limit)
+    {
+        return(-1);
+    }
+    CVMX_MT_ENTRY_HIGH(hi);
+    CVMX_MT_ENTRY_LO_0(lo0);
+    CVMX_MT_ENTRY_LO_1(lo1);
+    CVMX_MT_PAGEMASK(page_mask);
+    CVMX_MT_TLB_INDEX(index);
+    CVMX_MT_TLB_WIRED(index + 1);
+    CVMX_EHB;
+    CVMX_TLBWI;
+    CVMX_EHB;
+    return(index);
+}
+
+
+
+/**
+ * Adds a fixed (wired) TLB mapping.  Returns TLB index used or -1 on error.
+ * This is a wrapper around cvmx_core_add_wired_tlb_entry()
+ *
+ * @param vaddr      Virtual address to map
+ * @param page0_addr page 0 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
+ * @param page1_addr page1 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
+ * @param page_mask  page mask.
+ *
+ * @return Success: TLB index used (0-31)
+ *         Failure: -1
+ */
+int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
+{
+
+    if ((vaddr & (page_mask | 0x7ff))
+        || ((page0_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1))
+        || ((page1_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1)))
+    {
+        cvmx_dprintf("Error adding tlb mapping: invalid address alignment at vaddr: 0x%llx\n", (unsigned long long)vaddr);
+        return(-1);
+    }
+
+
+    return(cvmx_core_add_wired_tlb_entry(vaddr,
+                                         (page0_addr >> 6) | (page0_addr & 0x7),
+                                         (page1_addr >> 6) | (page1_addr & 0x7),
+                                         page_mask));
+
+}
+/**
+ * Adds a fixed (wired) TLB mapping.  Returns TLB index used or -1 on error.
+ * Assumes both pages are valid.  Use cvmx_core_add_fixed_tlb_mapping_bits for more control.
+ * This is a wrapper around cvmx_core_add_wired_tlb_entry()
+ *
+ * @param vaddr      Virtual address to map
+ * @param page0_addr page 0 physical address
+ * @param page1_addr page1 physical address
+ * @param page_mask  page mask.
+ *
+ * @return Success: TLB index used (0-31)
+ *         Failure: -1
+ */
+int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
+{
+
+    return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask));
+
+}
diff --git a/cvmx-core.h b/cvmx-core.h
new file mode 100644
index 0000000000000..e498c572e7178
--- /dev/null
+++ b/cvmx-core.h
@@ -0,0 +1,166 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Module to support operations on core such as TLB config, etc.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+
+#ifndef __CVMX_CORE_H__
+#define __CVMX_CORE_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * The types of performance counters supported per cpu
+ */
+typedef enum
+{
+    CVMX_CORE_PERF_NONE      = 0,    /**< Turn off the performance counter */
+    CVMX_CORE_PERF_CLK       = 1,    /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */
+    CVMX_CORE_PERF_ISSUE     = 2,    /**< Instructions issued but not retired */
+    CVMX_CORE_PERF_RET       = 3,    /**< Instructions retired */
+    CVMX_CORE_PERF_NISSUE    = 4,    /**< Cycles no issue */
+    CVMX_CORE_PERF_SISSUE    = 5,    /**< Cycles single issue */
+    CVMX_CORE_PERF_DISSUE    = 6,    /**< Cycles dual issue */
+    CVMX_CORE_PERF_IFI       = 7,    /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */
+    CVMX_CORE_PERF_BR        = 8,    /**< Branches retired */
+    CVMX_CORE_PERF_BRMIS     = 9,    /**< Branch mispredicts */
+    CVMX_CORE_PERF_J         = 10,   /**< Jumps retired */
+    CVMX_CORE_PERF_JMIS      = 11,   /**< Jumps mispredicted */
+    CVMX_CORE_PERF_REPLAY    = 12,   /**< Mem Replays */
+    CVMX_CORE_PERF_IUNA      = 13,   /**< Cycles idle due to unaligned_replays */
+    CVMX_CORE_PERF_TRAP      = 14,   /**< trap_6a signal */
+    CVMX_CORE_PERF_UULOAD    = 16,   /**< Unexpected unaligned loads (REPUN=1) */
+    CVMX_CORE_PERF_UUSTORE   = 17,   /**< Unexpected unaligned store (REPUN=1) */
+    CVMX_CORE_PERF_ULOAD     = 18,   /**< Unaligned loads (REPUN=1 or USEUN=1) */
+    CVMX_CORE_PERF_USTORE    = 19,   /**< Unaligned store (REPUN=1 or USEUN=1) */
+    CVMX_CORE_PERF_EC        = 20,   /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_CORE_PERF_MC        = 21,   /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_CORE_PERF_CC        = 22,   /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_CORE_PERF_CSRC      = 23,   /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_CORE_PERF_CFETCH    = 24,   /**< Icache committed fetches (demand+prefetch) */
+    CVMX_CORE_PERF_CPREF     = 25,   /**< Icache committed prefetches */
+    CVMX_CORE_PERF_ICA       = 26,   /**< Icache aliases */
+    CVMX_CORE_PERF_II        = 27,   /**< Icache invalidates */
+    CVMX_CORE_PERF_IP        = 28,   /**< Icache parity error */
+    CVMX_CORE_PERF_CIMISS    = 29,   /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_CORE_PERF_WBUF      = 32,   /**< Number of write buffer entries created */
+    CVMX_CORE_PERF_WDAT      = 33,   /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_CORE_PERF_WBUFLD    = 34,   /**< Number of write buffer entries forced out by loads */
+    CVMX_CORE_PERF_WBUFFL    = 35,   /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
+    CVMX_CORE_PERF_WBUFTR    = 36,   /**< Number of stores that found no available write buffer entries */
+    CVMX_CORE_PERF_BADD      = 37,   /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_CORE_PERF_BADDL2    = 38,   /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_CORE_PERF_BFILL     = 39,   /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_CORE_PERF_DDIDS     = 40,   /**< Number of Dstream DIDs created */
+    CVMX_CORE_PERF_IDIDS     = 41,   /**< Number of Istream DIDs created */
+    CVMX_CORE_PERF_DIDNA     = 42,   /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
+    CVMX_CORE_PERF_LDS       = 43,   /**< Number of load issues */
+    CVMX_CORE_PERF_LMLDS     = 44,   /**< Number of local memory load */
+    CVMX_CORE_PERF_IOLDS     = 45,   /**< Number of I/O load issues */
+    CVMX_CORE_PERF_DMLDS     = 46,   /**< Number of loads that were not prefetches and missed in the cache */
+    CVMX_CORE_PERF_STS       = 48,   /**< Number of store issues */
+    CVMX_CORE_PERF_LMSTS     = 49,   /**< Number of local memory store issues */
+    CVMX_CORE_PERF_IOSTS     = 50,   /**< Number of I/O store issues */
+    CVMX_CORE_PERF_IOBDMA    = 51,   /**< Number of IOBDMAs */
+    CVMX_CORE_PERF_DTLB      = 53,   /**< Number of dstream TLB refill, invalid, or modified exceptions */
+    CVMX_CORE_PERF_DTLBAD    = 54,   /**< Number of dstream TLB address errors */
+    CVMX_CORE_PERF_ITLB      = 55,   /**< Number of istream TLB refill, invalid, or address error exceptions */
+    CVMX_CORE_PERF_SYNC      = 56,   /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_CORE_PERF_SYNCIOB   = 57,   /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_CORE_PERF_SYNCW     = 58,   /**< Number of SYNCWs */
+    CVMX_CORE_PERF_MAX               /**< This not a counter, just a marker for the highest number */
+} cvmx_core_perf_t;
+
+/**
+ * Bit description of the COP0 counter control register
+ */
+typedef union
+{
+    uint32_t u32;
+    struct
+    {
+        uint32_t m              : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
+        uint32_t w              : 1; /**< Set to 1 indicating coutners are 64 bit */
+        uint32_t reserved_11_29 :19;
+        cvmx_core_perf_t event  : 6; /**< Selects the event to be counted by the corresponding Counter Register */
+        uint32_t ie             : 1; /**< Count in interrupt context */
+        uint32_t u              : 1; /**< Count in user mode */
+        uint32_t s              : 1; /**< Count in supervisor mode */
+        uint32_t k              : 1; /**< Count in kernel mode */
+        uint32_t ex             : 1; /**< Count in exception context */
+    } s;
+} cvmx_core_perf_control_t;
+
+typedef enum {
+    CVMX_TLB_PAGEMASK_4K   = 0x3     << 11,
+    CVMX_TLB_PAGEMASK_16K  = 0xF     << 11,
+    CVMX_TLB_PAGEMASK_64K  = 0x3F    << 11,
+    CVMX_TLB_PAGEMASK_256K = 0xFF    << 11,
+    CVMX_TLB_PAGEMASK_1M   = 0x3FF   << 11,
+    CVMX_TLB_PAGEMASK_4M   = 0xFFF   << 11,
+    CVMX_TLB_PAGEMASK_16M  = 0x3FFF  << 11,
+    CVMX_TLB_PAGEMASK_64M  = 0xFFFF  << 11,
+    CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11,
+} cvmx_tlb_pagemask_t;
+
+
+int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask);
+
+
+int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
+int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_CORE_H__ */
diff --git a/cvmx-coremask.c b/cvmx-coremask.c
new file mode 100644
index 0000000000000..5574c83b66b7c
--- /dev/null
+++ b/cvmx-coremask.c
@@ -0,0 +1,132 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Module to support operations on bitmap of cores. Coremask can be used to
+ * select a specific core, a group of cores, or all available cores, for
+ * initialization and differentiation of roles within a single shared binary
+ * executable image.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-coremask.h"
+
+
+#define  CVMX_COREMASK_MAX_SYNCS  20  /* maximum number of coremasks for barrier sync */
+
+/**
+ * This structure defines the private state maintained by coremask module.
+ *
+ */
+CVMX_SHARED static struct {
+
+    cvmx_spinlock_t            lock;       /**< mutex spinlock */
+
+    struct {
+
+        unsigned int           coremask;   /**< coremask specified for barrier */
+        unsigned int           checkin;    /**< bitmask of cores checking in */
+        volatile unsigned int  exit;       /**< variable to poll for exit condition */
+
+    } s[CVMX_COREMASK_MAX_SYNCS];
+
+} state = {
+
+    { CVMX_SPINLOCK_UNLOCKED_VAL },
+
+    { { 0, 0, 0 } },
+};
+
+
+/**
+ * Wait (stall) until all cores in the given coremask has reached this point
+ * in the program execution before proceeding.
+ *
+ * @param  coremask  the group of cores performing the barrier sync
+ *
+ */
+void cvmx_coremask_barrier_sync(unsigned int coremask)
+{
+    int i;
+    unsigned int target;
+
+    assert(coremask != 0);
+
+    cvmx_spinlock_lock(&state.lock);
+
+    for (i = 0; i < CVMX_COREMASK_MAX_SYNCS; i++) {
+
+        if (state.s[i].coremask == 0) {
+            /* end of existing coremask list, create new entry, fall-thru */
+            state.s[i].coremask = coremask;
+        }
+
+        if (state.s[i].coremask == coremask) {
+
+            target = state.s[i].exit + 1;  /* wrap-around at 32b */
+
+            state.s[i].checkin |= cvmx_coremask_core(cvmx_get_core_num());
+            if (state.s[i].checkin == coremask) {
+                state.s[i].checkin = 0;
+                state.s[i].exit = target;  /* signal exit condition */
+            }
+            cvmx_spinlock_unlock(&state.lock);
+
+            while (state.s[i].exit != target)
+                ;
+
+            return;
+        }
+    }
+
+    /* error condition - coremask array overflowed */
+    cvmx_spinlock_unlock(&state.lock);
+    assert(0);
+}
diff --git a/cvmx-coremask.h b/cvmx-coremask.h
new file mode 100644
index 0000000000000..132e462211027
--- /dev/null
+++ b/cvmx-coremask.h
@@ -0,0 +1,161 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Module to support operations on bitmap of cores. Coremask can be used to
+ * select a specific core, a group of cores, or all available cores, for
+ * initialization and differentiation of roles within a single shared binary
+ * executable image.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+
+#ifndef __CVMX_COREMASK_H__
+#define __CVMX_COREMASK_H__
+
+#include "cvmx-asm.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * coremask is simply unsigned int (32 bits).
+ *
+ * NOTE: supports up to 32 cores maximum.
+ *
+ * union of coremasks is simply bitwise-or.
+ * intersection of coremasks is simply bitwise-and.
+ *
+ */
+
+#define  CVMX_COREMASK_MAX  0xFFFFFFFFu    /* maximum supported mask */
+
+
+/**
+ * Compute coremask for a specific core.
+ *
+ * @param  core_id  The core ID
+ *
+ * @return  coremask for a specific core
+ *
+ */
+static inline unsigned int cvmx_coremask_core(unsigned int core_id)
+{
+    return (1u << core_id);
+}
+
+/**
+ * Compute coremask for num_cores cores starting with core 0.
+ *
+ * @param  num_cores  number of cores
+ *
+ * @return  coremask for num_cores cores
+ *
+ */
+static inline unsigned int cvmx_coremask_numcores(unsigned int num_cores)
+{
+    return (CVMX_COREMASK_MAX >> (32 - num_cores));
+}
+
+/**
+ * Compute coremask for a range of cores from core low to core high.
+ *
+ * @param  low   first core in the range
+ * @param  high  last core in the range
+ *
+ * @return  coremask for the range of cores
+ *
+ */
+static inline unsigned int cvmx_coremask_range(unsigned int low, unsigned int high)
+{
+    return ((CVMX_COREMASK_MAX >> (31 - high + low)) << low);
+}
+
+
+/**
+ * Test to see if current core is a member of coremask.
+ *
+ * @param  coremask  the coremask to test against
+ *
+ * @return  1 if current core is a member of coremask, 0 otherwise
+ *
+ */
+static inline int cvmx_coremask_is_member(unsigned int coremask)
+{
+    return ((cvmx_coremask_core(cvmx_get_core_num()) & coremask) != 0);
+}
+
+/**
+ * Test to see if current core is first core in coremask.
+ *
+ * @param  coremask  the coremask to test against
+ *
+ * @return  1 if current core is first core in the coremask, 0 otherwise
+ *
+ */
+static inline int cvmx_coremask_first_core(unsigned int coremask)
+{
+    return cvmx_coremask_is_member(coremask)
+        && ((cvmx_get_core_num() == 0) ||
+            ((cvmx_coremask_numcores(cvmx_get_core_num()) & coremask) == 0));
+}
+
+/**
+ * Wait (stall) until all cores in the given coremask has reached this point
+ * in the program execution before proceeding.
+ *
+ * @param  coremask  the group of cores performing the barrier sync
+ *
+ */
+extern void cvmx_coremask_barrier_sync(unsigned int coremask);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_COREMASK_H__ */
diff --git a/cvmx-csr-addresses.h b/cvmx-csr-addresses.h
new file mode 100644
index 0000000000000..e9ba13ef6eb62
--- /dev/null
+++ b/cvmx-csr-addresses.h
@@ -0,0 +1,15490 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and for
+ * Octeon. Include cvmx-csr.h instead of this file directly.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#ifndef __CVMX_CSR_ADDRESSES_H__
+#define __CVMX_CSR_ADDRESSES_H__
+
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#include "cvmx-warn.h"
+#endif
+
+#define CVMX_AGL_GMX_BAD_REG CVMX_AGL_GMX_BAD_REG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_BAD_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_BAD_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000518ull);
+}
+
+#define CVMX_AGL_GMX_BIST CVMX_AGL_GMX_BIST_FUNC()
+static inline uint64_t CVMX_AGL_GMX_BIST_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_BIST not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000400ull);
+}
+
+#define CVMX_AGL_GMX_DRV_CTL CVMX_AGL_GMX_DRV_CTL_FUNC()
+static inline uint64_t CVMX_AGL_GMX_DRV_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_DRV_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00007F0ull);
+}
+
+#define CVMX_AGL_GMX_INF_MODE CVMX_AGL_GMX_INF_MODE_FUNC()
+static inline uint64_t CVMX_AGL_GMX_INF_MODE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_INF_MODE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00007F8ull);
+}
+
+static inline uint64_t CVMX_AGL_GMX_PRTX_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_PRTX_CFG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000010ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000180ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000188ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000190ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM3(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000198ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM4(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM5(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CAM_EN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CAM_EN(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000108ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_ADR_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_ADR_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000100ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_DECISION(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_DECISION(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000040ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CHK(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CHK(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000020ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000018ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MAX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MAX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000030ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_FRM_MIN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_FRM_MIN(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000028ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_IFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_IFG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000058ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_INT_EN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000008ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_INT_REG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_INT_REG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000000ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_JABBER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_JABBER(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000038ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000068ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000050ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000088ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000098ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000080ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000090ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RXX_UDD_SKP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RXX_UDD_SKP(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000048ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RX_BP_DROPX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RX_BP_DROPX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000420ull) + (offset&1)*8;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RX_BP_OFFX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RX_BP_OFFX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000460ull) + (offset&1)*8;
+}
+
+static inline uint64_t CVMX_AGL_GMX_RX_BP_ONX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_RX_BP_ONX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000440ull) + (offset&1)*8;
+}
+
+#define CVMX_AGL_GMX_RX_PRT_INFO CVMX_AGL_GMX_RX_PRT_INFO_FUNC()
+static inline uint64_t CVMX_AGL_GMX_RX_PRT_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_RX_PRT_INFO not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00004E8ull);
+}
+
+#define CVMX_AGL_GMX_RX_TX_STATUS CVMX_AGL_GMX_RX_TX_STATUS_FUNC()
+static inline uint64_t CVMX_AGL_GMX_RX_TX_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_RX_TX_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00007E8ull);
+}
+
+static inline uint64_t CVMX_AGL_GMX_SMACX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_SMACX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000230ull) + (offset&1)*2048;
+}
+
+#define CVMX_AGL_GMX_STAT_BP CVMX_AGL_GMX_STAT_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_STAT_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_STAT_BP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000520ull);
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_APPEND(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_APPEND(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000218ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000270ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_MIN_PKT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_MIN_PKT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000240ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000248ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000238ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_TOGO(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_TOGO(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000258ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_PAUSE_ZERO(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_PAUSE_ZERO(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000260ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_SOFT_PAUSE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_SOFT_PAUSE(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000250ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000280ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000288ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000290ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT3(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000298ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT4(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT5(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT6(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT6(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT7(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT7(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT8(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT8(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STAT9(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STAT9(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_STATS_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_STATS_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000268ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_AGL_GMX_TXX_THRESH(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_AGL_GMX_TXX_THRESH(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000210ull) + (offset&1)*2048;
+}
+
+#define CVMX_AGL_GMX_TX_BP CVMX_AGL_GMX_TX_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_BP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00004D0ull);
+}
+
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_COL_ATTEMPT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_COL_ATTEMPT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000498ull);
+}
+
+#define CVMX_AGL_GMX_TX_IFG CVMX_AGL_GMX_TX_IFG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_IFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_IFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000488ull);
+}
+
+#define CVMX_AGL_GMX_TX_INT_EN CVMX_AGL_GMX_TX_INT_EN_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_INT_EN not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000508ull);
+}
+
+#define CVMX_AGL_GMX_TX_INT_REG CVMX_AGL_GMX_TX_INT_REG_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_INT_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_INT_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000500ull);
+}
+
+#define CVMX_AGL_GMX_TX_JAM CVMX_AGL_GMX_TX_JAM_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_JAM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_JAM not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E0000490ull);
+}
+
+#define CVMX_AGL_GMX_TX_LFSR CVMX_AGL_GMX_TX_LFSR_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_LFSR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_LFSR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00004F8ull);
+}
+
+#define CVMX_AGL_GMX_TX_OVR_BP CVMX_AGL_GMX_TX_OVR_BP_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_OVR_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_OVR_BP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00004C8ull);
+}
+
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00004A0ull);
+}
+
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC()
+static inline uint64_t CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800E00004A8ull);
+}
+
+#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
+static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
+}
+
+#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
+static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
+}
+
+static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000180ull) + (block_id&0)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000188ull) + (block_id&0)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000190ull) + (block_id&0)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + (block_id&1)*0x8000000ull;
+}
+
+#define CVMX_CIU_BIST CVMX_CIU_BIST_FUNC()
+static inline uint64_t CVMX_CIU_BIST_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000730ull);
+}
+
+#define CVMX_CIU_DINT CVMX_CIU_DINT_FUNC()
+static inline uint64_t CVMX_CIU_DINT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000720ull);
+}
+
+#define CVMX_CIU_FUSE CVMX_CIU_FUSE_FUNC()
+static inline uint64_t CVMX_CIU_FUSE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000728ull);
+}
+
+#define CVMX_CIU_GSTOP CVMX_CIU_GSTOP_FUNC()
+static inline uint64_t CVMX_CIU_GSTOP_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000710ull);
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
+        cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000200ull) + (offset&63)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+        cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000002200ull) + (offset&63)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+        cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000006200ull) + (offset&63)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
+        cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000208ull) + (offset&63)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+        cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000002208ull) + (offset&63)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32)))))
+        cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000006208ull) + (offset&63)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + (offset&15)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + (offset&15)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + (offset&15)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + (offset&15)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + (offset&15)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + (offset&15)*16;
+}
+
+static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32)))))
+        cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000000ull) + (offset&63)*8;
+}
+
+static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + (offset&15)*8;
+}
+
+#define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
+static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000108ull);
+}
+
+static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset&15)*8;
+}
+
+static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset&15)*8;
+}
+
+#define CVMX_CIU_NMI CVMX_CIU_NMI_FUNC()
+static inline uint64_t CVMX_CIU_NMI_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000718ull);
+}
+
+#define CVMX_CIU_PCI_INTA CVMX_CIU_PCI_INTA_FUNC()
+static inline uint64_t CVMX_CIU_PCI_INTA_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000750ull);
+}
+
+#define CVMX_CIU_PP_DBG CVMX_CIU_PP_DBG_FUNC()
+static inline uint64_t CVMX_CIU_PP_DBG_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000708ull);
+}
+
+static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset&15)*8;
+}
+
+#define CVMX_CIU_PP_RST CVMX_CIU_PP_RST_FUNC()
+static inline uint64_t CVMX_CIU_PP_RST_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000700ull);
+}
+
+#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
+static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000760ull);
+}
+
+#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
+static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000768ull);
+}
+
+#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
+static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000770ull);
+}
+
+#define CVMX_CIU_SOFT_BIST CVMX_CIU_SOFT_BIST_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_BIST_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000738ull);
+}
+
+#define CVMX_CIU_SOFT_PRST CVMX_CIU_SOFT_PRST_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000748ull);
+}
+
+#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000758ull);
+}
+
+#define CVMX_CIU_SOFT_RST CVMX_CIU_SOFT_RST_FUNC()
+static inline uint64_t CVMX_CIU_SOFT_RST_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000740ull);
+}
+
+static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000480ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset&15)*8;
+}
+
+#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC()
+static inline uint64_t CVMX_DBG_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DBG_DATA not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000001E8ull);
+}
+
+#define CVMX_DFA_BST0 CVMX_DFA_BST0_FUNC()
+static inline uint64_t CVMX_DFA_BST0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_BST0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800300007F0ull);
+}
+
+#define CVMX_DFA_BST1 CVMX_DFA_BST1_FUNC()
+static inline uint64_t CVMX_DFA_BST1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_BST1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800300007F8ull);
+}
+
+#define CVMX_DFA_CFG CVMX_DFA_CFG_FUNC()
+static inline uint64_t CVMX_DFA_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_CFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000000ull);
+}
+
+#define CVMX_DFA_DBELL CVMX_DFA_DBELL_FUNC()
+static inline uint64_t CVMX_DFA_DBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_DBELL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001370000000000ull);
+}
+
+#define CVMX_DFA_DDR2_ADDR CVMX_DFA_DDR2_ADDR_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_ADDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000210ull);
+}
+
+#define CVMX_DFA_DDR2_BUS CVMX_DFA_DDR2_BUS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_BUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_BUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000080ull);
+}
+
+#define CVMX_DFA_DDR2_CFG CVMX_DFA_DDR2_CFG_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_CFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000208ull);
+}
+
+#define CVMX_DFA_DDR2_COMP CVMX_DFA_DDR2_COMP_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_COMP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_COMP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000090ull);
+}
+
+#define CVMX_DFA_DDR2_EMRS CVMX_DFA_DDR2_EMRS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_EMRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_EMRS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000268ull);
+}
+
+#define CVMX_DFA_DDR2_FCNT CVMX_DFA_DDR2_FCNT_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_FCNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_FCNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000078ull);
+}
+
+#define CVMX_DFA_DDR2_MRS CVMX_DFA_DDR2_MRS_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_MRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_MRS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000260ull);
+}
+
+#define CVMX_DFA_DDR2_OPT CVMX_DFA_DDR2_OPT_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_OPT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_OPT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000070ull);
+}
+
+#define CVMX_DFA_DDR2_PLL CVMX_DFA_DDR2_PLL_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_PLL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_PLL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000088ull);
+}
+
+#define CVMX_DFA_DDR2_TMG CVMX_DFA_DDR2_TMG_FUNC()
+static inline uint64_t CVMX_DFA_DDR2_TMG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_DDR2_TMG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000218ull);
+}
+
+#define CVMX_DFA_DIFCTL CVMX_DFA_DIFCTL_FUNC()
+static inline uint64_t CVMX_DFA_DIFCTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_DIFCTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001370600000000ull);
+}
+
+#define CVMX_DFA_DIFRDPTR CVMX_DFA_DIFRDPTR_FUNC()
+static inline uint64_t CVMX_DFA_DIFRDPTR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_DIFRDPTR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001370200000000ull);
+}
+
+#define CVMX_DFA_ECLKCFG CVMX_DFA_ECLKCFG_FUNC()
+static inline uint64_t CVMX_DFA_ECLKCFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_DFA_ECLKCFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000200ull);
+}
+
+#define CVMX_DFA_ERR CVMX_DFA_ERR_FUNC()
+static inline uint64_t CVMX_DFA_ERR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_ERR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000028ull);
+}
+
+#define CVMX_DFA_MEMCFG0 CVMX_DFA_MEMCFG0_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_MEMCFG0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000008ull);
+}
+
+#define CVMX_DFA_MEMCFG1 CVMX_DFA_MEMCFG1_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_MEMCFG1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000010ull);
+}
+
+#define CVMX_DFA_MEMCFG2 CVMX_DFA_MEMCFG2_FUNC()
+static inline uint64_t CVMX_DFA_MEMCFG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_MEMCFG2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000060ull);
+}
+
+#define CVMX_DFA_MEMFADR CVMX_DFA_MEMFADR_FUNC()
+static inline uint64_t CVMX_DFA_MEMFADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_MEMFADR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000030ull);
+}
+
+#define CVMX_DFA_MEMFCR CVMX_DFA_MEMFCR_FUNC()
+static inline uint64_t CVMX_DFA_MEMFCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_MEMFCR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000038ull);
+}
+
+#define CVMX_DFA_MEMRLD CVMX_DFA_MEMRLD_FUNC()
+static inline uint64_t CVMX_DFA_MEMRLD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_MEMRLD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000018ull);
+}
+
+#define CVMX_DFA_NCBCTL CVMX_DFA_NCBCTL_FUNC()
+static inline uint64_t CVMX_DFA_NCBCTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_NCBCTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000020ull);
+}
+
+#define CVMX_DFA_RODT_COMP_CTL CVMX_DFA_RODT_COMP_CTL_FUNC()
+static inline uint64_t CVMX_DFA_RODT_COMP_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_RODT_COMP_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000068ull);
+}
+
+#define CVMX_DFA_SBD_DBG0 CVMX_DFA_SBD_DBG0_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_SBD_DBG0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000040ull);
+}
+
+#define CVMX_DFA_SBD_DBG1 CVMX_DFA_SBD_DBG1_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_SBD_DBG1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000048ull);
+}
+
+#define CVMX_DFA_SBD_DBG2 CVMX_DFA_SBD_DBG2_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_SBD_DBG2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000050ull);
+}
+
+#define CVMX_DFA_SBD_DBG3 CVMX_DFA_SBD_DBG3_FUNC()
+static inline uint64_t CVMX_DFA_SBD_DBG3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_DFA_SBD_DBG3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180030000058ull);
+}
+
+#define CVMX_FPA_BIST_STATUS CVMX_FPA_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_BIST_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800280000E8ull);
+}
+
+#define CVMX_FPA_CTL_STATUS CVMX_FPA_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_CTL_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180028000050ull);
+}
+
+#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC()
+static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180028000000ull);
+}
+
+#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC()
+static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180028000058ull);
+}
+
+#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
+#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
+#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
+#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
+#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
+#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
+#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
+static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7))))))
+        cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180028000008ull) + (offset&7)*8 - 8*1;
+}
+
+static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7))))))
+        cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180028000060ull) + (offset&7)*8 - 8*1;
+}
+
+#define CVMX_FPA_INT_ENB CVMX_FPA_INT_ENB_FUNC()
+static inline uint64_t CVMX_FPA_INT_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180028000048ull);
+}
+
+#define CVMX_FPA_INT_SUM CVMX_FPA_INT_SUM_FUNC()
+static inline uint64_t CVMX_FPA_INT_SUM_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180028000040ull);
+}
+
+#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
+#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
+#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
+#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
+#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
+#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
+#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
+#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
+static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180028000098ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + (offset&7)*8;
+}
+
+#define CVMX_FPA_QUE_ACT CVMX_FPA_QUE_ACT_FUNC()
+static inline uint64_t CVMX_FPA_QUE_ACT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180028000138ull);
+}
+
+#define CVMX_FPA_QUE_EXP CVMX_FPA_QUE_EXP_FUNC()
+static inline uint64_t CVMX_FPA_QUE_EXP_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180028000130ull);
+}
+
+#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC()
+static inline uint64_t CVMX_FPA_WART_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800280000D8ull);
+}
+
+#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC()
+static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800280000E0ull);
+}
+
+static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_BAD_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_BIST(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_CLK_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_HG2_CONTROL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_INF_MODE(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_NXA_ADR(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000580ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_PRTX_CFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_ADR_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_DECISION(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_FRM_CHK(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_FRM_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000030ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000028ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_IFG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_INT_EN(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_INT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_JABBER(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000060ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RXX_UDD_SKP(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RX_BP_DROPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RX_BP_OFFX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_RX_BP_ONX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset&3) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_RX_HG2_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PASS_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_GMXX_RX_PASS_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080005F8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 15)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((offset&15) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_RX_PRTS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_RX_PRT_INFO(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_TX_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_RX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id&0)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_RX_XAUI_BAD_COL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_RX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_SMACX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_STAT_BP(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_APPEND(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_BURST(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset == 0)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset == 0)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_CBFC_XON(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + ((offset&0) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000208ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_MIN_PKT(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_SLOT(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT0(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT1(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT2(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT3(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT4(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT5(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT6(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT7(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT8(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STAT9(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_STATS_CTL(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TXX_THRESH(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset&3) + (block_id&1)*0x10000ull)*2048;
+}
+
+static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_BP(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 1)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 1)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000780ull) + ((offset&1) + (block_id&0)*0x0ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_COL_ATTEMPT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_CORRUPT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_HG2_REG1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_HG2_REG2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_IFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_INT_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_INT_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_JAM(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_LFSR(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_OVR_BP(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_DMAC(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_PAUSE_PKT_TYPE(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_PRTS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_GMXX_TX_SPI_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004C0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_DRAIN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_GMXX_TX_SPI_DRAIN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004E0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_MAX(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_GMXX_TX_SPI_MAX(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004B0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000680ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_GMXX_TX_SPI_THRESH(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_GMXX_TX_SPI_THRESH(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800080004B8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_TX_XAUI_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_GMXX_XAUI_EXT_LOOPBACK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000800ull) + (offset&15)*8;
+}
+
+#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
+}
+
+static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + (offset&3)*8;
+}
+
+#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
+static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
+}
+
+#define CVMX_GPIO_INT_CLR CVMX_GPIO_INT_CLR_FUNC()
+static inline uint64_t CVMX_GPIO_INT_CLR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000898ull);
+}
+
+#define CVMX_GPIO_RX_DAT CVMX_GPIO_RX_DAT_FUNC()
+static inline uint64_t CVMX_GPIO_RX_DAT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000880ull);
+}
+
+#define CVMX_GPIO_TX_CLR CVMX_GPIO_TX_CLR_FUNC()
+static inline uint64_t CVMX_GPIO_TX_CLR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000890ull);
+}
+
+#define CVMX_GPIO_TX_SET CVMX_GPIO_TX_SET_FUNC()
+static inline uint64_t CVMX_GPIO_TX_SET_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001070000000888ull);
+}
+
+static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23))))))
+        cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000000900ull) + (offset&31)*8 - 8*16;
+}
+
+#define CVMX_IOB_BIST_STATUS CVMX_IOB_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_IOB_BIST_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F00007F8ull);
+}
+
+#define CVMX_IOB_CTL_STATUS CVMX_IOB_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_IOB_CTL_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000050ull);
+}
+
+#define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000028ull);
+}
+
+#define CVMX_IOB_FAU_TIMEOUT CVMX_IOB_FAU_TIMEOUT_FUNC()
+static inline uint64_t CVMX_IOB_FAU_TIMEOUT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000000ull);
+}
+
+#define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000010ull);
+}
+
+#define CVMX_IOB_INB_CONTROL_MATCH CVMX_IOB_INB_CONTROL_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000078ull);
+}
+
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_INB_CONTROL_MATCH_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000088ull);
+}
+
+#define CVMX_IOB_INB_DATA_MATCH CVMX_IOB_INB_DATA_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_INB_DATA_MATCH_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000070ull);
+}
+
+#define CVMX_IOB_INB_DATA_MATCH_ENB CVMX_IOB_INB_DATA_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_INB_DATA_MATCH_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000080ull);
+}
+
+#define CVMX_IOB_INT_ENB CVMX_IOB_INT_ENB_FUNC()
+static inline uint64_t CVMX_IOB_INT_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000060ull);
+}
+
+#define CVMX_IOB_INT_SUM CVMX_IOB_INT_SUM_FUNC()
+static inline uint64_t CVMX_IOB_INT_SUM_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000058ull);
+}
+
+#define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000020ull);
+}
+
+#define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000008ull);
+}
+
+#define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000040ull);
+}
+
+#define CVMX_IOB_OUTB_CONTROL_MATCH CVMX_IOB_OUTB_CONTROL_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000098ull);
+}
+
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_CONTROL_MATCH_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F00000A8ull);
+}
+
+#define CVMX_IOB_OUTB_DATA_MATCH CVMX_IOB_OUTB_DATA_MATCH_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000090ull);
+}
+
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_DATA_MATCH_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F00000A0ull);
+}
+
+#define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000048ull);
+}
+
+#define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000038ull);
+}
+
+#define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC()
+static inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F0000018ull);
+}
+
+#define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC()
+static inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800F0000068ull);
+}
+
+#define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC()
+static inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800F00000B0ull);
+}
+
+#define CVMX_IPD_1ST_MBUFF_SKIP CVMX_IPD_1ST_MBUFF_SKIP_FUNC()
+static inline uint64_t CVMX_IPD_1ST_MBUFF_SKIP_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000000ull);
+}
+
+#define CVMX_IPD_1st_NEXT_PTR_BACK CVMX_IPD_1st_NEXT_PTR_BACK_FUNC()
+static inline uint64_t CVMX_IPD_1st_NEXT_PTR_BACK_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000150ull);
+}
+
+#define CVMX_IPD_2nd_NEXT_PTR_BACK CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC()
+static inline uint64_t CVMX_IPD_2nd_NEXT_PTR_BACK_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000158ull);
+}
+
+#define CVMX_IPD_BIST_STATUS CVMX_IPD_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_IPD_BIST_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F00000007F8ull);
+}
+
+#define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC()
+static inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000328ull);
+}
+
+#define CVMX_IPD_CLK_COUNT CVMX_IPD_CLK_COUNT_FUNC()
+static inline uint64_t CVMX_IPD_CLK_COUNT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000338ull);
+}
+
+#define CVMX_IPD_CTL_STATUS CVMX_IPD_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_IPD_CTL_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000018ull);
+}
+
+#define CVMX_IPD_INT_ENB CVMX_IPD_INT_ENB_FUNC()
+static inline uint64_t CVMX_IPD_INT_ENB_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000160ull);
+}
+
+#define CVMX_IPD_INT_SUM CVMX_IPD_INT_SUM_FUNC()
+static inline uint64_t CVMX_IPD_INT_SUM_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000168ull);
+}
+
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC()
+static inline uint64_t CVMX_IPD_NOT_1ST_MBUFF_SKIP_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000008ull);
+}
+
+#define CVMX_IPD_PACKET_MBUFF_SIZE CVMX_IPD_PACKET_MBUFF_SIZE_FUNC()
+static inline uint64_t CVMX_IPD_PACKET_MBUFF_SIZE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000010ull);
+}
+
+#define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC()
+static inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000358ull);
+}
+
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
+        cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + (offset&63)*8;
+}
+
+static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + (offset&63)*8 - 8*36;
+}
+
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + (offset&63)*8 - 8*36;
+}
+
+static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35))))))
+        cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + (offset&63)*8;
+}
+
+static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4)))))
+        cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4)))))
+        cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319))))))
+        cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + (offset&511)*8;
+}
+
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000348ull);
+}
+
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000350ull);
+}
+
+#define CVMX_IPD_PTR_COUNT CVMX_IPD_PTR_COUNT_FUNC()
+static inline uint64_t CVMX_IPD_PTR_COUNT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000320ull);
+}
+
+#define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC()
+static inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000340ull);
+}
+
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + (offset&7)*8;
+}
+
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC()
+static inline uint64_t CVMX_IPD_QUE0_FREE_PAGE_CNT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000330ull);
+}
+
+#define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC()
+static inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F00000002D8ull);
+}
+
+#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC()
+static inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F00000003A8ull);
+}
+
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + (offset&7)*8;
+}
+
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_BP_PAGE_CNT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000148ull);
+}
+
+#define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000170ull);
+}
+
+#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC()
+static inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00014F0000000800ull);
+}
+
+#define CVMX_IPD_WQE_FPA_QUEUE CVMX_IPD_WQE_FPA_QUEUE_FUNC()
+static inline uint64_t CVMX_IPD_WQE_FPA_QUEUE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000020ull);
+}
+
+#define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC()
+static inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00014F0000000360ull);
+}
+
+#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
+static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180020000018ull);
+}
+
+#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180020000010ull);
+}
+
+#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
+static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180020000008ull);
+}
+
+#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
+static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180020000000ull);
+}
+
+#define CVMX_L2C_BST0 CVMX_L2C_BST0_FUNC()
+static inline uint64_t CVMX_L2C_BST0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007F8ull);
+}
+
+#define CVMX_L2C_BST1 CVMX_L2C_BST1_FUNC()
+static inline uint64_t CVMX_L2C_BST1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007F0ull);
+}
+
+#define CVMX_L2C_BST2 CVMX_L2C_BST2_FUNC()
+static inline uint64_t CVMX_L2C_BST2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007E8ull);
+}
+
+#define CVMX_L2C_CFG CVMX_L2C_CFG_FUNC()
+static inline uint64_t CVMX_L2C_CFG_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000000ull);
+}
+
+#define CVMX_L2C_DBG CVMX_L2C_DBG_FUNC()
+static inline uint64_t CVMX_L2C_DBG_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000030ull);
+}
+
+#define CVMX_L2C_DUT CVMX_L2C_DUT_FUNC()
+static inline uint64_t CVMX_L2C_DUT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000050ull);
+}
+
+#define CVMX_L2C_GRPWRR0 CVMX_L2C_GRPWRR0_FUNC()
+static inline uint64_t CVMX_L2C_GRPWRR0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_GRPWRR0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000C8ull);
+}
+
+#define CVMX_L2C_GRPWRR1 CVMX_L2C_GRPWRR1_FUNC()
+static inline uint64_t CVMX_L2C_GRPWRR1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_GRPWRR1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000D0ull);
+}
+
+#define CVMX_L2C_INT_EN CVMX_L2C_INT_EN_FUNC()
+static inline uint64_t CVMX_L2C_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_INT_EN not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180080000100ull);
+}
+
+#define CVMX_L2C_INT_STAT CVMX_L2C_INT_STAT_FUNC()
+static inline uint64_t CVMX_L2C_INT_STAT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_INT_STAT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000F8ull);
+}
+
+#define CVMX_L2C_LCKBASE CVMX_L2C_LCKBASE_FUNC()
+static inline uint64_t CVMX_L2C_LCKBASE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000058ull);
+}
+
+#define CVMX_L2C_LCKOFF CVMX_L2C_LCKOFF_FUNC()
+static inline uint64_t CVMX_L2C_LCKOFF_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000060ull);
+}
+
+#define CVMX_L2C_LFB0 CVMX_L2C_LFB0_FUNC()
+static inline uint64_t CVMX_L2C_LFB0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000038ull);
+}
+
+#define CVMX_L2C_LFB1 CVMX_L2C_LFB1_FUNC()
+static inline uint64_t CVMX_L2C_LFB1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000040ull);
+}
+
+#define CVMX_L2C_LFB2 CVMX_L2C_LFB2_FUNC()
+static inline uint64_t CVMX_L2C_LFB2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000048ull);
+}
+
+#define CVMX_L2C_LFB3 CVMX_L2C_LFB3_FUNC()
+static inline uint64_t CVMX_L2C_LFB3_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800000B8ull);
+}
+
+#define CVMX_L2C_OOB CVMX_L2C_OOB_FUNC()
+static inline uint64_t CVMX_L2C_OOB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_OOB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000D8ull);
+}
+
+#define CVMX_L2C_OOB1 CVMX_L2C_OOB1_FUNC()
+static inline uint64_t CVMX_L2C_OOB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_OOB1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000E0ull);
+}
+
+#define CVMX_L2C_OOB2 CVMX_L2C_OOB2_FUNC()
+static inline uint64_t CVMX_L2C_OOB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_OOB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000E8ull);
+}
+
+#define CVMX_L2C_OOB3 CVMX_L2C_OOB3_FUNC()
+static inline uint64_t CVMX_L2C_OOB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_OOB3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000F0ull);
+}
+
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_PFCTL CVMX_L2C_PFCTL_FUNC()
+static inline uint64_t CVMX_L2C_PFCTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000090ull);
+}
+
+static inline uint64_t CVMX_L2C_PFCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_L2C_PFCX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180080000098ull) + (offset&3)*8;
+}
+
+#define CVMX_L2C_PPGRP CVMX_L2C_PPGRP_FUNC()
+static inline uint64_t CVMX_L2C_PPGRP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_L2C_PPGRP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800800000C0ull);
+}
+
+#define CVMX_L2C_SPAR0 CVMX_L2C_SPAR0_FUNC()
+static inline uint64_t CVMX_L2C_SPAR0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000068ull);
+}
+
+#define CVMX_L2C_SPAR1 CVMX_L2C_SPAR1_FUNC()
+static inline uint64_t CVMX_L2C_SPAR1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_L2C_SPAR1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180080000070ull);
+}
+
+#define CVMX_L2C_SPAR2 CVMX_L2C_SPAR2_FUNC()
+static inline uint64_t CVMX_L2C_SPAR2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_L2C_SPAR2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180080000078ull);
+}
+
+#define CVMX_L2C_SPAR3 CVMX_L2C_SPAR3_FUNC()
+static inline uint64_t CVMX_L2C_SPAR3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_L2C_SPAR3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180080000080ull);
+}
+
+#define CVMX_L2C_SPAR4 CVMX_L2C_SPAR4_FUNC()
+static inline uint64_t CVMX_L2C_SPAR4_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000088ull);
+}
+
+#define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
+static inline uint64_t CVMX_L2D_BST0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000780ull);
+}
+
+#define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
+static inline uint64_t CVMX_L2D_BST1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000788ull);
+}
+
+#define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
+static inline uint64_t CVMX_L2D_BST2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000790ull);
+}
+
+#define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
+static inline uint64_t CVMX_L2D_BST3_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000798ull);
+}
+
+#define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
+static inline uint64_t CVMX_L2D_ERR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000010ull);
+}
+
+#define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
+static inline uint64_t CVMX_L2D_FADR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000018ull);
+}
+
+#define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
+static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000020ull);
+}
+
+#define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
+static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000028ull);
+}
+
+#define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
+static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
+}
+
+#define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
+static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
+}
+
+#define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
+static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
+}
+
+#define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
+static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
+}
+
+#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC()
+static inline uint64_t CVMX_L2T_ERR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180080000008ull);
+}
+
+#define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC()
+static inline uint64_t CVMX_LED_BLINK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_BLINK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A48ull);
+}
+
+#define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC()
+static inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A08ull);
+}
+
+#define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC()
+static inline uint64_t CVMX_LED_CYLON_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_CYLON not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001AF8ull);
+}
+
+#define CVMX_LED_DBG CVMX_LED_DBG_FUNC()
+static inline uint64_t CVMX_LED_DBG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_DBG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A18ull);
+}
+
+#define CVMX_LED_EN CVMX_LED_EN_FUNC()
+static inline uint64_t CVMX_LED_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_EN not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A00ull);
+}
+
+#define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC()
+static inline uint64_t CVMX_LED_POLARITY_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A50ull);
+}
+
+#define CVMX_LED_PRT CVMX_LED_PRT_FUNC()
+static inline uint64_t CVMX_LED_PRT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_PRT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A10ull);
+}
+
+#define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC()
+static inline uint64_t CVMX_LED_PRT_FMT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A30ull);
+}
+
+static inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + (offset&1)*8;
+}
+
+static inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + (offset&1)*8;
+}
+
+static inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + (offset&1)*16;
+}
+
+static inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + (offset&1)*16;
+}
+
+static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_BIST_RESULT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000F8ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_COMP_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_COMP_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000028ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000010ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_CTL1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_CTL1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000090ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DCLK_CNT_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_DCLK_CNT_HI(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000070ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DCLK_CNT_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_DCLK_CNT_LO(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000068ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DCLK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_LMCX_DCLK_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000B8ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DDR2_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_DDR2_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000018ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DELAY_CFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_DELAY_CFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000088ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DLL_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_DLL_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000C0ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_DUAL_MEMCFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_ECC_SYND(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_FADR(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_IFB_CNT_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_IFB_CNT_HI(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000050ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_IFB_CNT_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_IFB_CNT_LO(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000048ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_MEM_CFG0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_MEM_CFG0(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000000ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_MEM_CFG1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_MEM_CFG1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000008ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_NXM(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_OPS_CNT_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_OPS_CNT_HI(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000060ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_OPS_CNT_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_OPS_CNT_LO(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000058ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_PLL_BWCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_PLL_BWCTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000040ull) + (block_id&0)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_PLL_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_PLL_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000A8ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_PLL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_PLL_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000B0ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_READ_LEVEL_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_READ_LEVEL_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000140ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_READ_LEVEL_DBG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_READ_LEVEL_DBG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000148ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_READ_LEVEL_RANKX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_LMCX_READ_LEVEL_RANKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000100ull) + ((offset&3) + (block_id&1)*0xC000000ull)*8;
+}
+
+static inline uint64_t CVMX_LMCX_RODT_COMP_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_RODT_COMP_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800880000A0ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_RODT_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_RODT_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000078ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_WODT_CTL0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_WODT_CTL0(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000030ull) + (block_id&1)*0x60000000ull;
+}
+
+static inline uint64_t CVMX_LMCX_WODT_CTL1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0)))))
+        cvmx_warn("CVMX_LMCX_WODT_CTL1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180088000080ull) + (block_id&1)*0x60000000ull;
+}
+
+#define CVMX_MIO_BOOT_BIST_STAT CVMX_MIO_BOOT_BIST_STAT_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_BIST_STAT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800000000F8ull);
+}
+
+#define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800000000B8ull);
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000100ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000138ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000150ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000120ull) + (offset&3)*8;
+}
+
+#define CVMX_MIO_BOOT_ERR CVMX_MIO_BOOT_ERR_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_ERR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800000000A0ull);
+}
+
+#define CVMX_MIO_BOOT_INT CVMX_MIO_BOOT_INT_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_INT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800000000A8ull);
+}
+
+#define CVMX_MIO_BOOT_LOC_ADR CVMX_MIO_BOOT_LOC_ADR_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_LOC_ADR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000000090ull);
+}
+
+static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000080ull) + (offset&1)*8;
+}
+
+#define CVMX_MIO_BOOT_LOC_DAT CVMX_MIO_BOOT_LOC_DAT_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_LOC_DAT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000000098ull);
+}
+
+#define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800000000C0ull);
+}
+
+static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000000ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000040ull) + (offset&7)*8;
+}
+
+#define CVMX_MIO_BOOT_THR CVMX_MIO_BOOT_THR_FUNC()
+static inline uint64_t CVMX_MIO_BOOT_THR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800000000B0ull);
+}
+
+static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001520ull) + (offset&3)*8;
+}
+
+#define CVMX_MIO_FUS_DAT0 CVMX_MIO_FUS_DAT0_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001400ull);
+}
+
+#define CVMX_MIO_FUS_DAT1 CVMX_MIO_FUS_DAT1_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001408ull);
+}
+
+#define CVMX_MIO_FUS_DAT2 CVMX_MIO_FUS_DAT2_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001410ull);
+}
+
+#define CVMX_MIO_FUS_DAT3 CVMX_MIO_FUS_DAT3_FUNC()
+static inline uint64_t CVMX_MIO_FUS_DAT3_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001418ull);
+}
+
+#define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC()
+static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001550ull);
+}
+
+#define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001420ull);
+}
+
+#define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001580ull);
+}
+
+#define CVMX_MIO_FUS_PROG CVMX_MIO_FUS_PROG_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PROG_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001510ull);
+}
+
+#define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC()
+static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001518ull);
+}
+
+#define CVMX_MIO_FUS_RCMD CVMX_MIO_FUS_RCMD_FUNC()
+static inline uint64_t CVMX_MIO_FUS_RCMD_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001500ull);
+}
+
+#define CVMX_MIO_FUS_SPR_REPAIR_RES CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC()
+static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_RES_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001548ull);
+}
+
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC()
+static inline uint64_t CVMX_MIO_FUS_SPR_REPAIR_SUM_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001540ull);
+}
+
+#define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC()
+static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001578ull);
+}
+
+#define CVMX_MIO_FUS_WADR CVMX_MIO_FUS_WADR_FUNC()
+static inline uint64_t CVMX_MIO_FUS_WADR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180000001508ull);
+}
+
+#define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000168ull);
+}
+
+#define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000170ull);
+}
+
+#define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC()
+static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000178ull);
+}
+
+#define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC()
+static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001448ull);
+}
+
+#define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC()
+static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)))
+        cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001440ull);
+}
+
+static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001010ull) + (offset&1)*512;
+}
+
+static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001000ull) + (offset&1)*512;
+}
+
+static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001018ull) + (offset&1)*512;
+}
+
+static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001008ull) + (offset&1)*512;
+}
+
+#define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC()
+static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000488ull);
+}
+
+#define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000480ull);
+}
+
+#define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000520ull);
+}
+
+#define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000450ull);
+}
+
+#define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC()
+static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000708ull);
+}
+
+#define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC()
+static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000408ull);
+}
+
+#define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000410ull);
+}
+
+#define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000418ull);
+}
+
+#define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000428ull);
+}
+
+#define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000420ull);
+}
+
+#define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000430ull);
+}
+
+#define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000400ull);
+}
+
+#define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000608ull);
+}
+
+#define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC()
+static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000530ull);
+}
+
+#define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000620ull);
+}
+
+#define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000438ull);
+}
+
+#define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000630ull);
+}
+
+#define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000610ull);
+}
+
+#define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000638ull);
+}
+
+#define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC()
+static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000618ull);
+}
+
+#define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC()
+static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000700ull);
+}
+
+#define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC()
+static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000600ull);
+}
+
+#define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000528ull);
+}
+
+#define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000440ull);
+}
+
+#define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC()
+static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000538ull);
+}
+
+static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000888ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000880ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000920ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000850ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000808ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000810ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000818ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000828ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000820ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000830ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000800ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000930ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000838ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000928ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000840ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000000938ull) + (offset&1)*1024;
+}
+
+static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100078ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100020ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100050ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100030ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100028ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100010ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100018ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100048ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100040ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100038ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100000ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100008ull) + (offset&1)*2048;
+}
+
+static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000100058ull) + (offset&1)*2048;
+}
+
+#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
+static inline uint64_t CVMX_MPI_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000001000ull);
+}
+
+static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
+        cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000001080ull) + (offset&15)*8;
+}
+
+#define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
+static inline uint64_t CVMX_MPI_STS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000001008ull);
+}
+
+#define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
+static inline uint64_t CVMX_MPI_TX_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000001010ull);
+}
+
+#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
+static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000018ull);
+}
+
+#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
+static inline uint64_t CVMX_NDF_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000000ull);
+}
+
+#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
+static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000030ull);
+}
+
+#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
+static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000010ull);
+}
+
+#define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
+static inline uint64_t CVMX_NDF_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000020ull);
+}
+
+#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
+static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000028ull);
+}
+
+#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
+static inline uint64_t CVMX_NDF_MISC_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000008ull);
+}
+
+#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
+static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070001000038ull);
+}
+
+static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000000ull + (offset&31)*16;
+}
+
+#define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n");
+#endif
+    return 0x0000000000000580ull;
+}
+
+#define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC()
+static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n");
+#endif
+    return 0x0000000000000680ull;
+}
+
+#define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n");
+#endif
+    return 0x0000000000000250ull;
+}
+
+#define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n");
+#endif
+    return 0x0000000000000260ull;
+}
+
+#define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n");
+#endif
+    return 0x0000000000000570ull;
+}
+
+#define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC()
+static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n");
+#endif
+    return 0x0000000000003C00ull;
+}
+
+#define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n");
+#endif
+    return 0x00000000000005F0ull;
+}
+
+#define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n");
+#endif
+    return 0x0000000000000510ull;
+}
+
+#define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n");
+#endif
+    return 0x0000000000000500ull;
+}
+
+#define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
+#endif
+    return 0x00000000000005C0ull;
+}
+
+#define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
+#endif
+    return 0x00000000000005D0ull;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000450ull + (offset&7)*16;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000003B0ull + (offset&7)*16;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000400ull + (offset&7)*16;
+}
+
+static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000004A0ull + (offset&7)*16;
+}
+
+#define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n");
+#endif
+    return 0x00000000000005E0ull;
+}
+
+#define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n");
+#endif
+    return 0x00000000000003A0ull;
+}
+
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
+#endif
+    return 0x00000000000005B0ull;
+}
+
+#define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n");
+#endif
+    return 0x00000000000006C0ull;
+}
+
+#define CVMX_NPEI_DMA_STATE1_P1 CVMX_NPEI_DMA_STATE1_P1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE1_P1_FUNC(void)
+{
+    return 0x0000000000000680ull;
+}
+
+#define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n");
+#endif
+    return 0x00000000000006D0ull;
+}
+
+#define CVMX_NPEI_DMA_STATE2_P1 CVMX_NPEI_DMA_STATE2_P1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE2_P1_FUNC(void)
+{
+    return 0x0000000000000690ull;
+}
+
+#define CVMX_NPEI_DMA_STATE3_P1 CVMX_NPEI_DMA_STATE3_P1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE3_P1_FUNC(void)
+{
+    return 0x00000000000006A0ull;
+}
+
+#define CVMX_NPEI_DMA_STATE4_P1 CVMX_NPEI_DMA_STATE4_P1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE4_P1_FUNC(void)
+{
+    return 0x00000000000006B0ull;
+}
+
+#define CVMX_NPEI_DMA_STATE5_P1 CVMX_NPEI_DMA_STATE5_P1_FUNC()
+static inline uint64_t CVMX_NPEI_DMA_STATE5_P1_FUNC(void)
+{
+    return 0x00000000000006C0ull;
+}
+
+#define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000000560ull;
+}
+
+#define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n");
+#endif
+    return 0x0000000000003CE0ull;
+}
+
+#define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC()
+static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n");
+#endif
+    return 0x0000000000000550ull;
+}
+
+#define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000000540ull;
+}
+
+#define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n");
+#endif
+    return 0x0000000000003CD0ull;
+}
+
+#define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC()
+static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n");
+#endif
+    return 0x0000000000000590ull;
+}
+
+#define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC()
+static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n");
+#endif
+    return 0x0000000000000530ull;
+}
+
+#define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n");
+#endif
+    return 0x0000000000003CC0ull;
+}
+
+#define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
+#endif
+    return 0x0000000000000600ull;
+}
+
+#define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
+#endif
+    return 0x0000000000000610ull;
+}
+
+#define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
+#endif
+    return 0x00000000000004F0ull;
+}
+
+static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27))))))
+        cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000340ull + (offset&31)*16 - 16*12;
+}
+
+#define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n");
+#endif
+    return 0x0000000000003C50ull;
+}
+
+#define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n");
+#endif
+    return 0x0000000000003C60ull;
+}
+
+#define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n");
+#endif
+    return 0x0000000000003C70ull;
+}
+
+#define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n");
+#endif
+    return 0x0000000000003C80ull;
+}
+
+#define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n");
+#endif
+    return 0x0000000000003C10ull;
+}
+
+#define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n");
+#endif
+    return 0x0000000000003C20ull;
+}
+
+#define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n");
+#endif
+    return 0x0000000000003C30ull;
+}
+
+#define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n");
+#endif
+    return 0x0000000000003C40ull;
+}
+
+#define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n");
+#endif
+    return 0x0000000000003CA0ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
+#endif
+    return 0x0000000000003CF0ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
+#endif
+    return 0x0000000000003D00ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
+#endif
+    return 0x0000000000003D10ull;
+}
+
+#define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
+#endif
+    return 0x0000000000003D20ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
+#endif
+    return 0x0000000000003D30ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
+#endif
+    return 0x0000000000003D40ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
+#endif
+    return 0x0000000000003D50ull;
+}
+
+#define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
+#endif
+    return 0x0000000000003D60ull;
+}
+
+#define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n");
+#endif
+    return 0x0000000000003C90ull;
+}
+
+#define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
+#endif
+    return 0x0000000000003D70ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n");
+#endif
+    return 0x0000000000003CB0ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+#endif
+    return 0x0000000000000650ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+#endif
+    return 0x0000000000000660ull;
+}
+
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+#endif
+    return 0x0000000000000670ull;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000002400ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000002800ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000002C00ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000003000ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000003400ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000003800ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000001400ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000001800ull + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000001C00ull + (offset&31)*16;
+}
+
+#define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n");
+#endif
+    return 0x0000000000001110ull;
+}
+
+#define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000001130ull;
+}
+
+#define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
+#endif
+    return 0x00000000000010B0ull;
+}
+
+#define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
+#endif
+    return 0x00000000000010A0ull;
+}
+
+#define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
+#endif
+    return 0x0000000000001090ull;
+}
+
+#define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n");
+#endif
+    return 0x0000000000001080ull;
+}
+
+#define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
+#endif
+    return 0x0000000000001150ull;
+}
+
+#define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000001000ull;
+}
+
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+#endif
+    return 0x0000000000001190ull;
+}
+
+#define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
+#endif
+    return 0x0000000000001020ull;
+}
+
+#define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n");
+#endif
+    return 0x0000000000001100ull;
+}
+
+#define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n");
+#endif
+    return 0x00000000000006B0ull;
+}
+
+static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000002000ull + (offset&31)*16;
+}
+
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+#endif
+    return 0x00000000000006A0ull;
+}
+
+#define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
+#endif
+    return 0x00000000000011A0ull;
+}
+
+#define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n");
+#endif
+    return 0x0000000000001070ull;
+}
+
+#define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
+#endif
+    return 0x0000000000001160ull;
+}
+
+#define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n");
+#endif
+    return 0x00000000000010D0ull;
+}
+
+#define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000001010ull;
+}
+
+#define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n");
+#endif
+    return 0x00000000000010E0ull;
+}
+
+#define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
+#endif
+    return 0x0000000000000690ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n");
+#endif
+    return 0x0000000000001050ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
+#endif
+    return 0x0000000000001180ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n");
+#endif
+    return 0x0000000000001040ull;
+}
+
+#define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n");
+#endif
+    return 0x0000000000001030ull;
+}
+
+#define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n");
+#endif
+    return 0x0000000000001120ull;
+}
+
+#define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000001140ull;
+}
+
+#define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
+#endif
+    return 0x0000000000000520ull;
+}
+
+#define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n");
+#endif
+    return 0x0000000000000270ull;
+}
+
+#define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC()
+static inline uint64_t CVMX_NPEI_STATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n");
+#endif
+    return 0x0000000000000620ull;
+}
+
+#define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC()
+static inline uint64_t CVMX_NPEI_STATE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n");
+#endif
+    return 0x0000000000000630ull;
+}
+
+#define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC()
+static inline uint64_t CVMX_NPEI_STATE3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n");
+#endif
+    return 0x0000000000000640ull;
+}
+
+#define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n");
+#endif
+    return 0x0000000000000380ull;
+}
+
+#define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n");
+#endif
+    return 0x0000000000000210ull;
+}
+
+#define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n");
+#endif
+    return 0x0000000000000240ull;
+}
+
+#define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n");
+#endif
+    return 0x0000000000000200ull;
+}
+
+#define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n");
+#endif
+    return 0x0000000000000220ull;
+}
+
+#define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n");
+#endif
+    return 0x0000000000000230ull;
+}
+
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + (offset&3)*16;
+}
+
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + (offset&3)*8;
+}
+
+#define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000003F8ull);
+}
+
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + (offset&3)*8;
+}
+
+#define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC()
+static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000218ull);
+}
+
+#define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000010ull);
+}
+
+#define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000008ull);
+}
+
+#define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000128ull);
+}
+
+#define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC()
+static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000148ull);
+}
+
+#define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC()
+static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000158ull);
+}
+
+#define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC()
+static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000140ull);
+}
+
+#define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC()
+static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000150ull);
+}
+
+#define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC()
+static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000120ull);
+}
+
+#define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC()
+static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000110ull);
+}
+
+#define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000138ull);
+}
+
+#define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC()
+static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000020ull);
+}
+
+#define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC()
+static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000018ull);
+}
+
+#define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC()
+static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000118ull);
+}
+
+#define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC()
+static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000108ull);
+}
+
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6))))))
+        cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + (offset&7)*8 - 8*3;
+}
+
+#define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n");
+#endif
+    return 0x0000000000000190ull;
+}
+
+#define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001190ull);
+}
+
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + (offset&3)*8;
+}
+
+#define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000100ull);
+}
+
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + (offset&31)*4;
+}
+
+#define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000011C0ull);
+}
+
+#define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC()
+static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000000D8ull);
+}
+
+#define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001800ull);
+}
+
+#define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001804ull);
+}
+
+#define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001808ull);
+}
+
+#define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000180Cull);
+}
+
+#define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001810ull);
+}
+
+#define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001814ull);
+}
+
+#define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001818ull);
+}
+
+#define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000181Cull);
+}
+
+#define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001820ull);
+}
+
+#define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001824ull);
+}
+
+#define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001828ull);
+}
+
+#define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000182Cull);
+}
+
+#define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001830ull);
+}
+
+#define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001834ull);
+}
+
+#define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000183Cull);
+}
+
+#define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001840ull);
+}
+
+#define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001844ull);
+}
+
+#define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001848ull);
+}
+
+#define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000184Cull);
+}
+
+#define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001850ull);
+}
+
+#define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001854ull);
+}
+
+#define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001858ull);
+}
+
+#define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018E0ull);
+}
+
+#define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018E4ull);
+}
+
+#define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018E8ull);
+}
+
+#define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018ECull);
+}
+
+#define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018F0ull);
+}
+
+#define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018F4ull);
+}
+
+#define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018F8ull);
+}
+
+#define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000018FCull);
+}
+
+#define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000011B8ull);
+}
+
+#define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000118Cull);
+}
+
+#define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000130ull);
+}
+
+#define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000011A0ull);
+}
+
+#define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001198ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000048ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001180ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001184ull);
+}
+
+#define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC()
+static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000001188ull);
+}
+
+#define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000011A8ull);
+}
+
+#define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC()
+static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000011B0ull);
+}
+
+#define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000001F8ull);
+}
+
+#define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000200ull);
+}
+
+#define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000208ull);
+}
+
+#define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC()
+static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000210ull);
+}
+
+#define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC()
+static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000001F0ull);
+}
+
+static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + (offset&3)*8;
+}
+
+static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + (offset&3)*8;
+}
+
+#define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000000ull);
+}
+
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + (offset&3)*16;
+}
+
+#define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC()
+static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000001E0ull);
+}
+
+#define CVMX_PCIEEP_CFG000 CVMX_PCIEEP_CFG000_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG000_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG000 not supported on this chip\n");
+#endif
+    return 0x0000000000000000ull;
+}
+
+#define CVMX_PCIEEP_CFG001 CVMX_PCIEEP_CFG001_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG001_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG001 not supported on this chip\n");
+#endif
+    return 0x0000000000000004ull;
+}
+
+#define CVMX_PCIEEP_CFG002 CVMX_PCIEEP_CFG002_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG002_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG002 not supported on this chip\n");
+#endif
+    return 0x0000000000000008ull;
+}
+
+#define CVMX_PCIEEP_CFG003 CVMX_PCIEEP_CFG003_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG003_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG003 not supported on this chip\n");
+#endif
+    return 0x000000000000000Cull;
+}
+
+#define CVMX_PCIEEP_CFG004 CVMX_PCIEEP_CFG004_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG004_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG004 not supported on this chip\n");
+#endif
+    return 0x0000000000000010ull;
+}
+
+#define CVMX_PCIEEP_CFG004_MASK CVMX_PCIEEP_CFG004_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG004_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG004_MASK not supported on this chip\n");
+#endif
+    return 0x0000000080000010ull;
+}
+
+#define CVMX_PCIEEP_CFG005 CVMX_PCIEEP_CFG005_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG005_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG005 not supported on this chip\n");
+#endif
+    return 0x0000000000000014ull;
+}
+
+#define CVMX_PCIEEP_CFG005_MASK CVMX_PCIEEP_CFG005_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG005_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG005_MASK not supported on this chip\n");
+#endif
+    return 0x0000000080000014ull;
+}
+
+#define CVMX_PCIEEP_CFG006 CVMX_PCIEEP_CFG006_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG006_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG006 not supported on this chip\n");
+#endif
+    return 0x0000000000000018ull;
+}
+
+#define CVMX_PCIEEP_CFG006_MASK CVMX_PCIEEP_CFG006_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG006_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG006_MASK not supported on this chip\n");
+#endif
+    return 0x0000000080000018ull;
+}
+
+#define CVMX_PCIEEP_CFG007 CVMX_PCIEEP_CFG007_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG007_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG007 not supported on this chip\n");
+#endif
+    return 0x000000000000001Cull;
+}
+
+#define CVMX_PCIEEP_CFG007_MASK CVMX_PCIEEP_CFG007_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG007_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG007_MASK not supported on this chip\n");
+#endif
+    return 0x000000008000001Cull;
+}
+
+#define CVMX_PCIEEP_CFG008 CVMX_PCIEEP_CFG008_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG008_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG008 not supported on this chip\n");
+#endif
+    return 0x0000000000000020ull;
+}
+
+#define CVMX_PCIEEP_CFG008_MASK CVMX_PCIEEP_CFG008_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG008_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG008_MASK not supported on this chip\n");
+#endif
+    return 0x0000000080000020ull;
+}
+
+#define CVMX_PCIEEP_CFG009 CVMX_PCIEEP_CFG009_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG009_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG009 not supported on this chip\n");
+#endif
+    return 0x0000000000000024ull;
+}
+
+#define CVMX_PCIEEP_CFG009_MASK CVMX_PCIEEP_CFG009_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG009_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG009_MASK not supported on this chip\n");
+#endif
+    return 0x0000000080000024ull;
+}
+
+#define CVMX_PCIEEP_CFG010 CVMX_PCIEEP_CFG010_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG010_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG010 not supported on this chip\n");
+#endif
+    return 0x0000000000000028ull;
+}
+
+#define CVMX_PCIEEP_CFG011 CVMX_PCIEEP_CFG011_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG011_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG011 not supported on this chip\n");
+#endif
+    return 0x000000000000002Cull;
+}
+
+#define CVMX_PCIEEP_CFG012 CVMX_PCIEEP_CFG012_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG012_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG012 not supported on this chip\n");
+#endif
+    return 0x0000000000000030ull;
+}
+
+#define CVMX_PCIEEP_CFG012_MASK CVMX_PCIEEP_CFG012_MASK_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG012_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG012_MASK not supported on this chip\n");
+#endif
+    return 0x0000000080000030ull;
+}
+
+#define CVMX_PCIEEP_CFG013 CVMX_PCIEEP_CFG013_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG013_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG013 not supported on this chip\n");
+#endif
+    return 0x0000000000000034ull;
+}
+
+#define CVMX_PCIEEP_CFG015 CVMX_PCIEEP_CFG015_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG015_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG015 not supported on this chip\n");
+#endif
+    return 0x000000000000003Cull;
+}
+
+#define CVMX_PCIEEP_CFG016 CVMX_PCIEEP_CFG016_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG016_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG016 not supported on this chip\n");
+#endif
+    return 0x0000000000000040ull;
+}
+
+#define CVMX_PCIEEP_CFG017 CVMX_PCIEEP_CFG017_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG017_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG017 not supported on this chip\n");
+#endif
+    return 0x0000000000000044ull;
+}
+
+#define CVMX_PCIEEP_CFG020 CVMX_PCIEEP_CFG020_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG020_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG020 not supported on this chip\n");
+#endif
+    return 0x0000000000000050ull;
+}
+
+#define CVMX_PCIEEP_CFG021 CVMX_PCIEEP_CFG021_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG021_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG021 not supported on this chip\n");
+#endif
+    return 0x0000000000000054ull;
+}
+
+#define CVMX_PCIEEP_CFG022 CVMX_PCIEEP_CFG022_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG022_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG022 not supported on this chip\n");
+#endif
+    return 0x0000000000000058ull;
+}
+
+#define CVMX_PCIEEP_CFG023 CVMX_PCIEEP_CFG023_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG023_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG023 not supported on this chip\n");
+#endif
+    return 0x000000000000005Cull;
+}
+
+#define CVMX_PCIEEP_CFG028 CVMX_PCIEEP_CFG028_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG028_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG028 not supported on this chip\n");
+#endif
+    return 0x0000000000000070ull;
+}
+
+#define CVMX_PCIEEP_CFG029 CVMX_PCIEEP_CFG029_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG029_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG029 not supported on this chip\n");
+#endif
+    return 0x0000000000000074ull;
+}
+
+#define CVMX_PCIEEP_CFG030 CVMX_PCIEEP_CFG030_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG030_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG030 not supported on this chip\n");
+#endif
+    return 0x0000000000000078ull;
+}
+
+#define CVMX_PCIEEP_CFG031 CVMX_PCIEEP_CFG031_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG031_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG031 not supported on this chip\n");
+#endif
+    return 0x000000000000007Cull;
+}
+
+#define CVMX_PCIEEP_CFG032 CVMX_PCIEEP_CFG032_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG032_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG032 not supported on this chip\n");
+#endif
+    return 0x0000000000000080ull;
+}
+
+#define CVMX_PCIEEP_CFG033 CVMX_PCIEEP_CFG033_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG033_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG033 not supported on this chip\n");
+#endif
+    return 0x0000000000000084ull;
+}
+
+#define CVMX_PCIEEP_CFG034 CVMX_PCIEEP_CFG034_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG034_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG034 not supported on this chip\n");
+#endif
+    return 0x0000000000000088ull;
+}
+
+#define CVMX_PCIEEP_CFG037 CVMX_PCIEEP_CFG037_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG037_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG037 not supported on this chip\n");
+#endif
+    return 0x0000000000000094ull;
+}
+
+#define CVMX_PCIEEP_CFG038 CVMX_PCIEEP_CFG038_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG038_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG038 not supported on this chip\n");
+#endif
+    return 0x0000000000000098ull;
+}
+
+#define CVMX_PCIEEP_CFG039 CVMX_PCIEEP_CFG039_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG039_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG039 not supported on this chip\n");
+#endif
+    return 0x000000000000009Cull;
+}
+
+#define CVMX_PCIEEP_CFG040 CVMX_PCIEEP_CFG040_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG040_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG040 not supported on this chip\n");
+#endif
+    return 0x00000000000000A0ull;
+}
+
+#define CVMX_PCIEEP_CFG041 CVMX_PCIEEP_CFG041_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG041_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG041 not supported on this chip\n");
+#endif
+    return 0x00000000000000A4ull;
+}
+
+#define CVMX_PCIEEP_CFG042 CVMX_PCIEEP_CFG042_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG042_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG042 not supported on this chip\n");
+#endif
+    return 0x00000000000000A8ull;
+}
+
+#define CVMX_PCIEEP_CFG064 CVMX_PCIEEP_CFG064_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG064_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG064 not supported on this chip\n");
+#endif
+    return 0x0000000000000100ull;
+}
+
+#define CVMX_PCIEEP_CFG065 CVMX_PCIEEP_CFG065_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG065_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG065 not supported on this chip\n");
+#endif
+    return 0x0000000000000104ull;
+}
+
+#define CVMX_PCIEEP_CFG066 CVMX_PCIEEP_CFG066_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG066_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG066 not supported on this chip\n");
+#endif
+    return 0x0000000000000108ull;
+}
+
+#define CVMX_PCIEEP_CFG067 CVMX_PCIEEP_CFG067_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG067_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG067 not supported on this chip\n");
+#endif
+    return 0x000000000000010Cull;
+}
+
+#define CVMX_PCIEEP_CFG068 CVMX_PCIEEP_CFG068_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG068_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG068 not supported on this chip\n");
+#endif
+    return 0x0000000000000110ull;
+}
+
+#define CVMX_PCIEEP_CFG069 CVMX_PCIEEP_CFG069_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG069_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG069 not supported on this chip\n");
+#endif
+    return 0x0000000000000114ull;
+}
+
+#define CVMX_PCIEEP_CFG070 CVMX_PCIEEP_CFG070_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG070_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG070 not supported on this chip\n");
+#endif
+    return 0x0000000000000118ull;
+}
+
+#define CVMX_PCIEEP_CFG071 CVMX_PCIEEP_CFG071_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG071_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG071 not supported on this chip\n");
+#endif
+    return 0x000000000000011Cull;
+}
+
+#define CVMX_PCIEEP_CFG072 CVMX_PCIEEP_CFG072_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG072_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG072 not supported on this chip\n");
+#endif
+    return 0x0000000000000120ull;
+}
+
+#define CVMX_PCIEEP_CFG073 CVMX_PCIEEP_CFG073_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG073_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG073 not supported on this chip\n");
+#endif
+    return 0x0000000000000124ull;
+}
+
+#define CVMX_PCIEEP_CFG074 CVMX_PCIEEP_CFG074_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG074_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG074 not supported on this chip\n");
+#endif
+    return 0x0000000000000128ull;
+}
+
+#define CVMX_PCIEEP_CFG448 CVMX_PCIEEP_CFG448_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG448_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG448 not supported on this chip\n");
+#endif
+    return 0x0000000000000700ull;
+}
+
+#define CVMX_PCIEEP_CFG449 CVMX_PCIEEP_CFG449_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG449_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG449 not supported on this chip\n");
+#endif
+    return 0x0000000000000704ull;
+}
+
+#define CVMX_PCIEEP_CFG450 CVMX_PCIEEP_CFG450_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG450_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG450 not supported on this chip\n");
+#endif
+    return 0x0000000000000708ull;
+}
+
+#define CVMX_PCIEEP_CFG451 CVMX_PCIEEP_CFG451_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG451_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG451 not supported on this chip\n");
+#endif
+    return 0x000000000000070Cull;
+}
+
+#define CVMX_PCIEEP_CFG452 CVMX_PCIEEP_CFG452_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG452_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG452 not supported on this chip\n");
+#endif
+    return 0x0000000000000710ull;
+}
+
+#define CVMX_PCIEEP_CFG453 CVMX_PCIEEP_CFG453_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG453_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG453 not supported on this chip\n");
+#endif
+    return 0x0000000000000714ull;
+}
+
+#define CVMX_PCIEEP_CFG454 CVMX_PCIEEP_CFG454_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG454_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG454 not supported on this chip\n");
+#endif
+    return 0x0000000000000718ull;
+}
+
+#define CVMX_PCIEEP_CFG455 CVMX_PCIEEP_CFG455_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG455_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG455 not supported on this chip\n");
+#endif
+    return 0x000000000000071Cull;
+}
+
+#define CVMX_PCIEEP_CFG456 CVMX_PCIEEP_CFG456_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG456_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG456 not supported on this chip\n");
+#endif
+    return 0x0000000000000720ull;
+}
+
+#define CVMX_PCIEEP_CFG458 CVMX_PCIEEP_CFG458_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG458_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG458 not supported on this chip\n");
+#endif
+    return 0x0000000000000728ull;
+}
+
+#define CVMX_PCIEEP_CFG459 CVMX_PCIEEP_CFG459_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG459_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG459 not supported on this chip\n");
+#endif
+    return 0x000000000000072Cull;
+}
+
+#define CVMX_PCIEEP_CFG460 CVMX_PCIEEP_CFG460_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG460_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG460 not supported on this chip\n");
+#endif
+    return 0x0000000000000730ull;
+}
+
+#define CVMX_PCIEEP_CFG461 CVMX_PCIEEP_CFG461_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG461_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG461 not supported on this chip\n");
+#endif
+    return 0x0000000000000734ull;
+}
+
+#define CVMX_PCIEEP_CFG462 CVMX_PCIEEP_CFG462_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG462_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG462 not supported on this chip\n");
+#endif
+    return 0x0000000000000738ull;
+}
+
+#define CVMX_PCIEEP_CFG463 CVMX_PCIEEP_CFG463_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG463_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG463 not supported on this chip\n");
+#endif
+    return 0x000000000000073Cull;
+}
+
+#define CVMX_PCIEEP_CFG464 CVMX_PCIEEP_CFG464_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG464_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG464 not supported on this chip\n");
+#endif
+    return 0x0000000000000740ull;
+}
+
+#define CVMX_PCIEEP_CFG465 CVMX_PCIEEP_CFG465_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG465_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG465 not supported on this chip\n");
+#endif
+    return 0x0000000000000744ull;
+}
+
+#define CVMX_PCIEEP_CFG466 CVMX_PCIEEP_CFG466_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG466_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG466 not supported on this chip\n");
+#endif
+    return 0x0000000000000748ull;
+}
+
+#define CVMX_PCIEEP_CFG467 CVMX_PCIEEP_CFG467_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG467_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG467 not supported on this chip\n");
+#endif
+    return 0x000000000000074Cull;
+}
+
+#define CVMX_PCIEEP_CFG468 CVMX_PCIEEP_CFG468_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG468_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG468 not supported on this chip\n");
+#endif
+    return 0x0000000000000750ull;
+}
+
+#define CVMX_PCIEEP_CFG490 CVMX_PCIEEP_CFG490_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG490_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG490 not supported on this chip\n");
+#endif
+    return 0x00000000000007A8ull;
+}
+
+#define CVMX_PCIEEP_CFG491 CVMX_PCIEEP_CFG491_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG491_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG491 not supported on this chip\n");
+#endif
+    return 0x00000000000007ACull;
+}
+
+#define CVMX_PCIEEP_CFG492 CVMX_PCIEEP_CFG492_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG492_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG492 not supported on this chip\n");
+#endif
+    return 0x00000000000007B0ull;
+}
+
+#define CVMX_PCIEEP_CFG516 CVMX_PCIEEP_CFG516_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG516_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG516 not supported on this chip\n");
+#endif
+    return 0x0000000000000810ull;
+}
+
+#define CVMX_PCIEEP_CFG517 CVMX_PCIEEP_CFG517_FUNC()
+static inline uint64_t CVMX_PCIEEP_CFG517_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PCIEEP_CFG517 not supported on this chip\n");
+#endif
+    return 0x0000000000000814ull;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000000ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG001(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000004ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG002(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000008ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG003(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000000Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG004(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000010ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG005(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000014ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG006(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000018ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG007(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000001Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG008(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000020ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG009(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000024ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG010(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000028ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG011(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000002Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG012(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000030ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG013(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000034ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG014(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000038ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG015(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000003Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG016(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000040ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG017(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000044ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG020(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000050ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG021(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000054ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG022(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000058ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG023(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000005Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG028(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000070ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG029(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000074ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG030(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000078ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG031(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000007Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG032(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000080ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG033(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000084ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG034(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000088ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG035(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000008Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG036(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000090ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG037(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000094ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG038(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000098ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG039(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000009Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG040(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000000A0ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG041(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000000A4ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG042(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000000A8ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG064(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000100ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG065(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000104ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG066(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000108ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG067(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000010Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG068(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000110ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG069(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000114ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG070(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000118ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG071(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000011Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG072(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000120ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG073(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000124ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG074(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000128ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG075(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000012Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG076(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000130ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG077(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000134ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG448(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000700ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG449(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000704ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG450(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000708ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG451(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000070Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG452(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000710ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG453(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000714ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG454(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000718ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG455(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000071Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG456(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000720ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG458(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000728ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG459(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000072Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG460(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000730ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG461(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000734ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG462(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000738ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG463(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000073Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG464(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000740ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG465(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000744ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG466(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000748ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG467(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000074Cull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG468(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000750ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG490(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000007A8ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG491(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000007ACull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG492(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000007B0ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG516(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000810ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCIERCX_CFG517(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000814ull + (offset&1)*0;
+}
+
+static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000100ull + (offset&31)*4;
+}
+
+#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC()
+static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n");
+#endif
+    return 0x00000000000001C0ull;
+}
+
+#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC()
+static inline uint64_t CVMX_PCI_CFG00_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n");
+#endif
+    return 0x0000000000000000ull;
+}
+
+#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC()
+static inline uint64_t CVMX_PCI_CFG01_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n");
+#endif
+    return 0x0000000000000004ull;
+}
+
+#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC()
+static inline uint64_t CVMX_PCI_CFG02_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n");
+#endif
+    return 0x0000000000000008ull;
+}
+
+#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC()
+static inline uint64_t CVMX_PCI_CFG03_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n");
+#endif
+    return 0x000000000000000Cull;
+}
+
+#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC()
+static inline uint64_t CVMX_PCI_CFG04_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n");
+#endif
+    return 0x0000000000000010ull;
+}
+
+#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC()
+static inline uint64_t CVMX_PCI_CFG05_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n");
+#endif
+    return 0x0000000000000014ull;
+}
+
+#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC()
+static inline uint64_t CVMX_PCI_CFG06_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n");
+#endif
+    return 0x0000000000000018ull;
+}
+
+#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC()
+static inline uint64_t CVMX_PCI_CFG07_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n");
+#endif
+    return 0x000000000000001Cull;
+}
+
+#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC()
+static inline uint64_t CVMX_PCI_CFG08_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n");
+#endif
+    return 0x0000000000000020ull;
+}
+
+#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC()
+static inline uint64_t CVMX_PCI_CFG09_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n");
+#endif
+    return 0x0000000000000024ull;
+}
+
+#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC()
+static inline uint64_t CVMX_PCI_CFG10_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n");
+#endif
+    return 0x0000000000000028ull;
+}
+
+#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC()
+static inline uint64_t CVMX_PCI_CFG11_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n");
+#endif
+    return 0x000000000000002Cull;
+}
+
+#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC()
+static inline uint64_t CVMX_PCI_CFG12_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n");
+#endif
+    return 0x0000000000000030ull;
+}
+
+#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC()
+static inline uint64_t CVMX_PCI_CFG13_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n");
+#endif
+    return 0x0000000000000034ull;
+}
+
+#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC()
+static inline uint64_t CVMX_PCI_CFG15_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n");
+#endif
+    return 0x000000000000003Cull;
+}
+
+#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC()
+static inline uint64_t CVMX_PCI_CFG16_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n");
+#endif
+    return 0x0000000000000040ull;
+}
+
+#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC()
+static inline uint64_t CVMX_PCI_CFG17_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n");
+#endif
+    return 0x0000000000000044ull;
+}
+
+#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC()
+static inline uint64_t CVMX_PCI_CFG18_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n");
+#endif
+    return 0x0000000000000048ull;
+}
+
+#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC()
+static inline uint64_t CVMX_PCI_CFG19_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n");
+#endif
+    return 0x000000000000004Cull;
+}
+
+#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC()
+static inline uint64_t CVMX_PCI_CFG20_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n");
+#endif
+    return 0x0000000000000050ull;
+}
+
+#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC()
+static inline uint64_t CVMX_PCI_CFG21_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n");
+#endif
+    return 0x0000000000000054ull;
+}
+
+#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC()
+static inline uint64_t CVMX_PCI_CFG22_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n");
+#endif
+    return 0x0000000000000058ull;
+}
+
+#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC()
+static inline uint64_t CVMX_PCI_CFG56_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n");
+#endif
+    return 0x00000000000000E0ull;
+}
+
+#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC()
+static inline uint64_t CVMX_PCI_CFG57_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n");
+#endif
+    return 0x00000000000000E4ull;
+}
+
+#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC()
+static inline uint64_t CVMX_PCI_CFG58_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n");
+#endif
+    return 0x00000000000000E8ull;
+}
+
+#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC()
+static inline uint64_t CVMX_PCI_CFG59_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n");
+#endif
+    return 0x00000000000000ECull;
+}
+
+#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC()
+static inline uint64_t CVMX_PCI_CFG60_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n");
+#endif
+    return 0x00000000000000F0ull;
+}
+
+#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC()
+static inline uint64_t CVMX_PCI_CFG61_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n");
+#endif
+    return 0x00000000000000F4ull;
+}
+
+#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC()
+static inline uint64_t CVMX_PCI_CFG62_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n");
+#endif
+    return 0x00000000000000F8ull;
+}
+
+#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC()
+static inline uint64_t CVMX_PCI_CFG63_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n");
+#endif
+    return 0x00000000000000FCull;
+}
+
+#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC()
+static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n");
+#endif
+    return 0x00000000000001B8ull;
+}
+
+#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC()
+static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n");
+#endif
+    return 0x000000000000018Cull;
+}
+
+static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000080ull + (offset&3)*8;
+}
+
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000000A0ull + (offset&1)*8;
+}
+
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000000A4ull + (offset&1)*8;
+}
+
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x00000000000000B0ull + (offset&1)*4;
+}
+
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000084ull + (offset&3)*8;
+}
+
+#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC()
+static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n");
+#endif
+    return 0x0000000000000038ull;
+}
+
+#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n");
+#endif
+    return 0x00000000000001A0ull;
+}
+
+#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n");
+#endif
+    return 0x0000000000000030ull;
+}
+
+#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n");
+#endif
+    return 0x0000000000000198ull;
+}
+
+#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n");
+#endif
+    return 0x00000000000000F0ull;
+}
+
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000040ull + (offset&3)*16;
+}
+
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000048ull + (offset&3)*16;
+}
+
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x000000000000004Cull + (offset&3)*16;
+}
+
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset);
+#endif
+    return 0x0000000000000044ull + (offset&3)*16;
+}
+
+#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n");
+#endif
+    return 0x0000000000000180ull;
+}
+
+#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n");
+#endif
+    return 0x0000000000000184ull;
+}
+
+#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC()
+static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n");
+#endif
+    return 0x0000000000000188ull;
+}
+
+#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC()
+static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000000B0ull);
+}
+
+#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC()
+static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n");
+#endif
+    return 0x00000000000001A8ull;
+}
+
+#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC()
+static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n");
+#endif
+    return 0x00000000000001B0ull;
+}
+
+#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC()
+static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n");
+#endif
+    return 0x0000000000000008ull;
+}
+
+#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC()
+static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n");
+#endif
+    return 0x0000000000000020ull;
+}
+
+#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n");
+#endif
+    return 0x0000000000000000ull;
+}
+
+#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n");
+#endif
+    return 0x0000000000000010ull;
+}
+
+#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC()
+static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n");
+#endif
+    return 0x0000000000000018ull;
+}
+
+static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010018ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010020ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010028ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010068ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010060ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010058ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010010ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010030ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010050ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010048ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010080ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010088ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010090ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010098ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010040ull) + (offset&3)*16384;
+}
+
+static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010000ull) + (offset&1)*16384;
+}
+
+static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010038ull) + (offset&1)*16384;
+}
+
+static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001070000010008ull) + (offset&1)*16384;
+}
+
+static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_ANX_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_INTX_EN_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_INTX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_LOG_ANLX_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_MISCX_CTL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_MRX_STATUS_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_RXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_RXX_SYNC_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_TXX_STATES_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id == 0))))))
+        cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset&3) + (block_id&1)*0x20000ull)*1024;
+}
+
+static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + ((offset&3) + (block_id&1)*0x800000ull)*16;
+}
+
+static inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + ((offset&3) + (block_id&1)*0x800000ull)*16;
+}
+
+static inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + (offset&31)*16;
+}
+
+#define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
+}
+
+#define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
+}
+
+#define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
+}
+
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
+}
+
+#define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
+}
+
+#define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + (offset&7)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + (offset&7)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + (offset&7)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4)))))
+        cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + (offset&7)*16;
+}
+
+#define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 CVMX_PEXP_NPEI_DMA_STATE1_P1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_P1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 CVMX_PEXP_NPEI_DMA_STATE2_P1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_P1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 CVMX_PEXP_NPEI_DMA_STATE3_P1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE3_P1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 CVMX_PEXP_NPEI_DMA_STATE4_P1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE4_P1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
+}
+
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 CVMX_PEXP_NPEI_DMA_STATE5_P1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE5_P1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
+}
+
+#define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
+}
+
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
+}
+
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
+}
+
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27))))))
+        cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + (offset&31)*16 - 16*12;
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
+}
+
+#define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
+}
+
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + (offset&31)*16;
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + (offset&31)*16;
+}
+
+#define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
+}
+
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31)))))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + (offset&31)*16;
+}
+
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
+}
+
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
+}
+
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
+}
+
+#define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
+}
+
+#define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
+}
+
+#define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
+}
+
+#define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
+}
+
+#define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
+static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
+}
+
+#define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC()
+static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000038ull);
+}
+
+#define CVMX_PIP_BIST_STATUS CVMX_PIP_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_PIP_BIST_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000000ull);
+}
+
+static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + (offset&1)*8;
+}
+
+static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + (offset&1)*8;
+}
+
+static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + (offset&3)*8;
+}
+
+#define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC()
+static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000190ull);
+}
+
+#define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC()
+static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000198ull);
+}
+
+static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + (offset&1)*8;
+}
+
+#define CVMX_PIP_GBL_CFG CVMX_PIP_GBL_CFG_FUNC()
+static inline uint64_t CVMX_PIP_GBL_CFG_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000028ull);
+}
+
+#define CVMX_PIP_GBL_CTL CVMX_PIP_GBL_CTL_FUNC()
+static inline uint64_t CVMX_PIP_GBL_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000020ull);
+}
+
+#define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC()
+static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A00001A0ull);
+}
+
+#define CVMX_PIP_INT_EN CVMX_PIP_INT_EN_FUNC()
+static inline uint64_t CVMX_PIP_INT_EN_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000010ull);
+}
+
+#define CVMX_PIP_INT_REG CVMX_PIP_INT_REG_FUNC()
+static inline uint64_t CVMX_PIP_INT_REG_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000008ull);
+}
+
+#define CVMX_PIP_IP_OFFSET CVMX_PIP_IP_OFFSET_FUNC()
+static inline uint64_t CVMX_PIP_IP_OFFSET_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000060ull);
+}
+
+static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + (offset&63)*8;
+}
+
+static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + (offset&63)*8;
+}
+
+static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
+        cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + (offset&63)*8;
+}
+
+static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + (offset&7)*8;
+}
+
+#define CVMX_PIP_RAW_WORD CVMX_PIP_RAW_WORD_FUNC()
+static inline uint64_t CVMX_PIP_RAW_WORD_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A00000B0ull);
+}
+
+#define CVMX_PIP_SFT_RST CVMX_PIP_SFT_RST_FUNC()
+static inline uint64_t CVMX_PIP_SFT_RST_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000030ull);
+}
+
+static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + (offset&63)*80;
+}
+
+static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + (offset&63)*80;
+}
+
+#define CVMX_PIP_STAT_CTL CVMX_PIP_STAT_CTL_FUNC()
+static inline uint64_t CVMX_PIP_STAT_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000018ull);
+}
+
+static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + (offset&63)*32;
+}
+
+static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + (offset&63)*32;
+}
+
+static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39))))))
+        cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + (offset&63)*32;
+}
+
+static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63)))))
+        cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + (offset&63)*8;
+}
+
+#define CVMX_PIP_TAG_MASK CVMX_PIP_TAG_MASK_FUNC()
+static inline uint64_t CVMX_PIP_TAG_MASK_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000070ull);
+}
+
+#define CVMX_PIP_TAG_SECRET CVMX_PIP_TAG_SECRET_FUNC()
+static inline uint64_t CVMX_PIP_TAG_SECRET_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000068ull);
+}
+
+#define CVMX_PIP_TODO_ENTRY CVMX_PIP_TODO_ENTRY_FUNC()
+static inline uint64_t CVMX_PIP_TODO_ENTRY_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00011800A0000078ull);
+}
+
+#define CVMX_PKO_MEM_COUNT0 CVMX_PKO_MEM_COUNT0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_COUNT0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001080ull);
+}
+
+#define CVMX_PKO_MEM_COUNT1 CVMX_PKO_MEM_COUNT1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_COUNT1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001088ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG0 CVMX_PKO_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001100ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG1 CVMX_PKO_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001108ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG10 CVMX_PKO_MEM_DEBUG10_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG10_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001150ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG11 CVMX_PKO_MEM_DEBUG11_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG11_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001158ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG12 CVMX_PKO_MEM_DEBUG12_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG12_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001160ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG13 CVMX_PKO_MEM_DEBUG13_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG13_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001168ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG14 CVMX_PKO_MEM_DEBUG14_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG14_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_MEM_DEBUG14 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050001170ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG2 CVMX_PKO_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001110ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG3 CVMX_PKO_MEM_DEBUG3_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG3_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001118ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG4 CVMX_PKO_MEM_DEBUG4_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG4_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001120ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG5 CVMX_PKO_MEM_DEBUG5_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG5_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001128ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG6 CVMX_PKO_MEM_DEBUG6_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG6_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001130ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG7 CVMX_PKO_MEM_DEBUG7_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG7_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001138ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG8 CVMX_PKO_MEM_DEBUG8_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG8_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001140ull);
+}
+
+#define CVMX_PKO_MEM_DEBUG9 CVMX_PKO_MEM_DEBUG9_FUNC()
+static inline uint64_t CVMX_PKO_MEM_DEBUG9_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001148ull);
+}
+
+#define CVMX_PKO_MEM_PORT_PTRS CVMX_PKO_MEM_PORT_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_PTRS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_MEM_PORT_PTRS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050001010ull);
+}
+
+#define CVMX_PKO_MEM_PORT_QOS CVMX_PKO_MEM_PORT_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_QOS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_MEM_PORT_QOS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050001018ull);
+}
+
+#define CVMX_PKO_MEM_PORT_RATE0 CVMX_PKO_MEM_PORT_RATE0_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_RATE0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_MEM_PORT_RATE0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050001020ull);
+}
+
+#define CVMX_PKO_MEM_PORT_RATE1 CVMX_PKO_MEM_PORT_RATE1_FUNC()
+static inline uint64_t CVMX_PKO_MEM_PORT_RATE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_MEM_PORT_RATE1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050001028ull);
+}
+
+#define CVMX_PKO_MEM_QUEUE_PTRS CVMX_PKO_MEM_QUEUE_PTRS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_QUEUE_PTRS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001000ull);
+}
+
+#define CVMX_PKO_MEM_QUEUE_QOS CVMX_PKO_MEM_QUEUE_QOS_FUNC()
+static inline uint64_t CVMX_PKO_MEM_QUEUE_QOS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050001008ull);
+}
+
+#define CVMX_PKO_REG_BIST_RESULT CVMX_PKO_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_PKO_REG_BIST_RESULT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000080ull);
+}
+
+#define CVMX_PKO_REG_CMD_BUF CVMX_PKO_REG_CMD_BUF_FUNC()
+static inline uint64_t CVMX_PKO_REG_CMD_BUF_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000010ull);
+}
+
+static inline uint64_t CVMX_PKO_REG_CRC_CTLX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PKO_REG_CRC_CTLX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050000028ull) + (offset&1)*8;
+}
+
+#define CVMX_PKO_REG_CRC_ENABLE CVMX_PKO_REG_CRC_ENABLE_FUNC()
+static inline uint64_t CVMX_PKO_REG_CRC_ENABLE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_PKO_REG_CRC_ENABLE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050000020ull);
+}
+
+static inline uint64_t CVMX_PKO_REG_CRC_IVX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_PKO_REG_CRC_IVX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050000038ull) + (offset&1)*8;
+}
+
+#define CVMX_PKO_REG_DEBUG0 CVMX_PKO_REG_DEBUG0_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000098ull);
+}
+
+#define CVMX_PKO_REG_DEBUG1 CVMX_PKO_REG_DEBUG1_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_PKO_REG_DEBUG1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800500000A0ull);
+}
+
+#define CVMX_PKO_REG_DEBUG2 CVMX_PKO_REG_DEBUG2_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_PKO_REG_DEBUG2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800500000A8ull);
+}
+
+#define CVMX_PKO_REG_DEBUG3 CVMX_PKO_REG_DEBUG3_FUNC()
+static inline uint64_t CVMX_PKO_REG_DEBUG3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_PKO_REG_DEBUG3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800500000B0ull);
+}
+
+#define CVMX_PKO_REG_ENGINE_INFLIGHT CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_INFLIGHT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_REG_ENGINE_INFLIGHT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050000050ull);
+}
+
+#define CVMX_PKO_REG_ENGINE_THRESH CVMX_PKO_REG_ENGINE_THRESH_FUNC()
+static inline uint64_t CVMX_PKO_REG_ENGINE_THRESH_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_PKO_REG_ENGINE_THRESH not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050000058ull);
+}
+
+#define CVMX_PKO_REG_ERROR CVMX_PKO_REG_ERROR_FUNC()
+static inline uint64_t CVMX_PKO_REG_ERROR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000088ull);
+}
+
+#define CVMX_PKO_REG_FLAGS CVMX_PKO_REG_FLAGS_FUNC()
+static inline uint64_t CVMX_PKO_REG_FLAGS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000000ull);
+}
+
+#define CVMX_PKO_REG_GMX_PORT_MODE CVMX_PKO_REG_GMX_PORT_MODE_FUNC()
+static inline uint64_t CVMX_PKO_REG_GMX_PORT_MODE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000018ull);
+}
+
+#define CVMX_PKO_REG_INT_MASK CVMX_PKO_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_PKO_REG_INT_MASK_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000090ull);
+}
+
+#define CVMX_PKO_REG_QUEUE_MODE CVMX_PKO_REG_QUEUE_MODE_FUNC()
+static inline uint64_t CVMX_PKO_REG_QUEUE_MODE_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000048ull);
+}
+
+#define CVMX_PKO_REG_QUEUE_PTRS1 CVMX_PKO_REG_QUEUE_PTRS1_FUNC()
+static inline uint64_t CVMX_PKO_REG_QUEUE_PTRS1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_PKO_REG_QUEUE_PTRS1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180050000100ull);
+}
+
+#define CVMX_PKO_REG_READ_IDX CVMX_PKO_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_PKO_REG_READ_IDX_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180050000008ull);
+}
+
+#define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC()
+static inline uint64_t CVMX_POW_BIST_STAT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
+}
+
+#define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC()
+static inline uint64_t CVMX_POW_DS_PC_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000398ull);
+}
+
+#define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC()
+static inline uint64_t CVMX_POW_ECC_ERR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000218ull);
+}
+
+#define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC()
+static inline uint64_t CVMX_POW_INT_CTL_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000220ull);
+}
+
+static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000340ull) + (offset&7)*8;
+}
+
+#define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC()
+static inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000388ull);
+}
+
+#define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
+static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000238ull);
+}
+
+#define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
+static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000240ull);
+}
+
+static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + (offset&7)*8;
+}
+
+#define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC()
+static inline uint64_t CVMX_POW_NOS_CNT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000228ull);
+}
+
+#define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC()
+static inline uint64_t CVMX_POW_NW_TIM_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000210ull);
+}
+
+#define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
+static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(!OCTEON_IS_MODEL(OCTEON_CN3XXX)))
+        cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000230ull);
+}
+
+static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3)))))
+        cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000000ull) + (offset&15)*8;
+}
+
+static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + (offset&7)*8;
+}
+
+static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000180ull) + (offset&7)*8;
+}
+
+#define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC()
+static inline uint64_t CVMX_POW_TS_PC_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000390ull);
+}
+
+#define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC()
+static inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000380ull);
+}
+
+static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7)))))
+        cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000300ull) + (offset&7)*8;
+}
+
+#define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC()
+static inline uint64_t CVMX_POW_WQ_INT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000200ull);
+}
+
+static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000100ull) + (offset&15)*8;
+}
+
+#define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC()
+static inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001670000000208ull);
+}
+
+static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000080ull) + (offset&15)*8;
+}
+
+static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15)))))
+        cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001670000000280ull) + (offset&15)*8;
+}
+
+#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070001000ull);
+}
+
+#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070001008ull);
+}
+
+#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070001010ull);
+}
+
+#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000080ull);
+}
+
+#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC()
+static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000008ull);
+}
+
+#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC()
+static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000000ull);
+}
+
+#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000100ull);
+}
+
+#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000108ull);
+}
+
+#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000150ull);
+}
+
+#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000158ull);
+}
+
+#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000160ull);
+}
+
+#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000110ull);
+}
+
+#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000118ull);
+}
+
+#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000120ull);
+}
+
+#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000128ull);
+}
+
+#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000130ull);
+}
+
+#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000138ull);
+}
+
+#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000140ull);
+}
+
+#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC()
+static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000148ull);
+}
+
+#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC()
+static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000088ull);
+}
+
+#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000090ull);
+}
+
+#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC()
+static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000010ull);
+}
+
+#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
+        cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180070000018ull);
+}
+
+#define CVMX_RNM_BIST_STATUS CVMX_RNM_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_RNM_BIST_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180040000008ull);
+}
+
+#define CVMX_RNM_CTL_STATUS CVMX_RNM_CTL_STATUS_FUNC()
+static inline uint64_t CVMX_RNM_CTL_STATUS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180040000000ull);
+}
+
+static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_SMIX_CLK(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset&1)*256;
+}
+
+static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_SMIX_CMD(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset&1)*256;
+}
+
+static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_SMIX_EN(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset&1)*256;
+}
+
+static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_SMIX_RD_DAT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset&1)*256;
+}
+
+static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1)))))
+        cvmx_warn("CVMX_SMIX_WR_DAT(%lu) is invalid on this chip\n", offset);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset&1)*256;
+}
+
+#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
+static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
+        cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000388ull);
+}
+
+#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
+static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
+        cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000380ull);
+}
+
+static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000340ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800900007F8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_CLK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000348ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_CLK_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_CLK_STAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000350ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_DBG_DESKEW_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_DBG_DESKEW_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000368ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_DBG_DESKEW_STATE(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_DBG_DESKEW_STATE(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000370ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_DRV_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_DRV_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000358ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_ERR_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_ERR_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000320ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_DAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_INT_DAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000318ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_MSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000308ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000300ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_INT_SYNC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000310ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TPA_ACC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_TPA_ACC(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000338ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TPA_MAX(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_TPA_MAX(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000330ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TPA_SEL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_TPA_SEL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000328ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SPXX_TRN4_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SPXX_TRN4_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000360ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000200ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000218ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000000ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000208ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000220ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000228ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000608ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000688ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000600ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000690ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000610ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000698ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000618ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000400ull) + ((offset&31) + (block_id&1)*0x1000000ull)*8;
+}
+
+static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000628ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000630ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000648ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000680ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000638ull) + (block_id&1)*0x8000000ull;
+}
+
+static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180090000640ull) + (block_id&1)*0x8000000ull;
+}
+
+#define CVMX_TIM_MEM_DEBUG0 CVMX_TIM_MEM_DEBUG0_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058001100ull);
+}
+
+#define CVMX_TIM_MEM_DEBUG1 CVMX_TIM_MEM_DEBUG1_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058001108ull);
+}
+
+#define CVMX_TIM_MEM_DEBUG2 CVMX_TIM_MEM_DEBUG2_FUNC()
+static inline uint64_t CVMX_TIM_MEM_DEBUG2_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058001110ull);
+}
+
+#define CVMX_TIM_MEM_RING0 CVMX_TIM_MEM_RING0_FUNC()
+static inline uint64_t CVMX_TIM_MEM_RING0_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058001000ull);
+}
+
+#define CVMX_TIM_MEM_RING1 CVMX_TIM_MEM_RING1_FUNC()
+static inline uint64_t CVMX_TIM_MEM_RING1_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058001008ull);
+}
+
+#define CVMX_TIM_REG_BIST_RESULT CVMX_TIM_REG_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_TIM_REG_BIST_RESULT_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058000080ull);
+}
+
+#define CVMX_TIM_REG_ERROR CVMX_TIM_REG_ERROR_FUNC()
+static inline uint64_t CVMX_TIM_REG_ERROR_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058000088ull);
+}
+
+#define CVMX_TIM_REG_FLAGS CVMX_TIM_REG_FLAGS_FUNC()
+static inline uint64_t CVMX_TIM_REG_FLAGS_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058000000ull);
+}
+
+#define CVMX_TIM_REG_INT_MASK CVMX_TIM_REG_INT_MASK_FUNC()
+static inline uint64_t CVMX_TIM_REG_INT_MASK_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058000090ull);
+}
+
+#define CVMX_TIM_REG_READ_IDX CVMX_TIM_REG_READ_IDX_FUNC()
+static inline uint64_t CVMX_TIM_REG_READ_IDX_FUNC(void)
+{
+    return CVMX_ADD_IO_SEG(0x0001180058000008ull);
+}
+
+#define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC()
+static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000010ull);
+}
+
+#define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC()
+static inline uint64_t CVMX_TRA_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000000ull);
+}
+
+#define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC()
+static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000018ull);
+}
+
+#define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC()
+static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000028ull);
+}
+
+#define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000058ull);
+}
+
+#define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000060ull);
+}
+
+#define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC()
+static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000040ull);
+}
+
+#define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC()
+static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000050ull);
+}
+
+#define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC()
+static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000048ull);
+}
+
+#define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC()
+static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000008ull);
+}
+
+#define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC()
+static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000020ull);
+}
+
+#define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000098ull);
+}
+
+#define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A80000A0ull);
+}
+
+#define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000080ull);
+}
+
+#define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000090ull);
+}
+
+#define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A8000088ull);
+}
+
+#define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A80000D8ull);
+}
+
+#define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A80000E0ull);
+}
+
+#define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A80000C0ull);
+}
+
+#define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A80000D0ull);
+}
+
+#define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC()
+static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800A80000C8ull);
+}
+
+static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((offset&7) + (block_id&1)*0x40000000000ull)*4;
+}
+
+static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + ((offset&7) + (block_id&1)*0x8000000000ull)*32;
+}
+
+static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1))))))
+        cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + ((offset&7) + (block_id&1)*0x100000000ull)*4096;
+}
+
+static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + (block_id&1)*0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180068000010ull) + (block_id&1)*0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + (block_id&1)*0x100000000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180068000008ull) + (block_id&1)*0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180068000000ull) + (block_id&1)*0x10000000ull;
+}
+
+static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(
+        (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) ||
+        (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1)))))
+        cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180068000018ull) + (block_id&1)*0x10000000ull;
+}
+
+#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180038000080ull);
+}
+
+#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180038000008ull);
+}
+
+#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC()
+static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180038000000ull);
+}
+
+#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC()
+static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x00011800380000A0ull);
+}
+
+#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC()
+static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180038000098ull);
+}
+
+#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC()
+static inline uint64_t CVMX_ZIP_ERROR_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180038000088ull);
+}
+
+#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC()
+static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void)
+{
+#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n");
+#endif
+    return CVMX_ADD_IO_SEG(0x0001180038000090ull);
+}
+
+
+#endif /* __CVMX_CSR_ADDRESSES_H__ */
diff --git a/cvmx-csr-db-support.c b/cvmx-csr-db-support.c
new file mode 100644
index 0000000000000..a5af6a1370da5
--- /dev/null
+++ b/cvmx-csr-db-support.c
@@ -0,0 +1,216 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Utility functions for working with the CSR database
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-csr-db.h"
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    #define PRINTF printk
+#else
+    #define PRINTF printf
+#endif
+
+/**
+ * Figure out which database to use for this chip. The passed
+ * identifier can be a processor ID or a PCI ID.
+ *
+ * @param identifier processor ID or a PCI ID
+ *
+ * @return index into the csr db
+ */
+int cvmx_db_get_chipindex(int identifier)
+{
+    /* First try and see if the identifier is a Processor ID */
+    switch (identifier & 0xffff00)
+    {
+        case 0x000d0600: /* CN50XX */
+            return 8;
+        case 0x000d0400: /* CN56XX */
+            return 7;
+        case 0x000d0300: /* CN58XX */
+            return 5;
+        case 0x000d0000: /* CN38XX */
+            return 3;
+        case 0x000d0100: /* CN31XX */
+            return 1;
+        case 0x000d0200: /* CN3010 */
+            return 2;
+        case 0x000d0700: /* CN52XX */
+            return 10;
+    }
+
+    /* Next try PCI device IDs */
+    switch (identifier)
+    {
+        case 0x0003177d: /* CN38XX Pass 1 */
+            return 0;
+        case 0x0004177d: /* CN38XX Pass 2 */
+            return 0;
+        case 0x0005177d: /* CN38XX Pass 3 */
+            return 3;
+        case 0x1001177d: /* Thunder */
+            return 3;
+        case 0x0020177d: /* CN31XX Pass 1 */
+            return 1;
+        case 0x0030177d: /* CN30XX Pass 1 */
+            return 2;
+        case 0x0040177d: /* CN58XX Pass 2 */
+            return 5;
+        case 0x0050177d: /* CN56XX Pass 2 */
+            return 7;
+        case 0x0070177d: /* CN50XX Pass 1 */
+            return 8;
+        case 0x0080177d: /* CN52XX Pass 2 */
+            return 10;
+    }
+
+    /* Default to Pass 3 if we don't know */
+    return 3;
+}
+
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+/**
+ * Get the CSR DB entry for the passed Octeon model and CSR name. The
+ * model can either be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param name       CSR name to lookup
+ *
+ * @return CSR DB entry or NULL on failure
+ */
+const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const char *name)
+{
+    int chip = cvmx_db_get_chipindex(identifier);
+    int i=0;
+    if (strncasecmp(name, "CVMX_", 5) == 0)
+        name += 5;
+    while (cvmx_csr_db_addresses[chip][i].name)
+    {
+        if (strcasecmp(name, cvmx_csr_db_addresses[chip][i].name) == 0)
+            return &(cvmx_csr_db_addresses[chip][i]);
+        i++;
+    }
+    return NULL;
+}
+#endif
+
+
+/**
+ * Decode a CSR value into named bitfields. The model can either
+ * be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param address    CSR address being decoded
+ * @param value      Value to decode
+ */
+void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value)
+{
+    int chip = cvmx_db_get_chipindex(identifier);
+    int index=0;
+    /* Strip off the upper 8 bits since they are normally mips addressing
+        modes */
+    address &= (1ull<<56)-1;
+    while (cvmx_csr_db_addresses[chip][index].name)
+    {
+        if (cvmx_csr_db_addresses[chip][index].address == address)
+        {
+            int field;
+            int csr = cvmx_csr_db_addresses[chip][index].csroff;
+            PRINTF("%s(0x%016llx) = 0x%016llx\n", cvmx_csr_db_addresses[chip][index].name, (unsigned long long)address, (unsigned long long)value);
+            for (field=cvmx_csr_db[chip][csr].fieldoff+cvmx_csr_db[chip][csr].numfields-1; field>=cvmx_csr_db[chip][csr].fieldoff; field--)
+            {
+                uint64_t v = (value >> cvmx_csr_db_fields[chip][field].startbit);
+                if(cvmx_csr_db_fields[chip][field].sizebits < 64)
+                    v = v & ~((~0x0ull) << cvmx_csr_db_fields[chip][field].sizebits);
+		if (cvmx_csr_db_fields[chip][field].sizebits == 1)
+                    PRINTF("  [   %2d] %-20s = %10llu (0x%llx)\n",
+                        cvmx_csr_db_fields[chip][field].startbit, cvmx_csr_db_fields[chip][field].name,
+                        (unsigned long long)v, (unsigned long long)v);
+                else
+                    PRINTF("  [%2d:%2d] %-20s = %10llu (0x%llx)\n",
+                        cvmx_csr_db_fields[chip][field].startbit + cvmx_csr_db_fields[chip][field].sizebits - 1,
+                        cvmx_csr_db_fields[chip][field].startbit,
+                        cvmx_csr_db_fields[chip][field].name,
+                        (unsigned long long)v, (unsigned long long)v);
+            }
+        }
+        index++;
+    }
+}
+
+
+#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
+/**
+ * Print a list of csrs begimning with a prefix. The
+ * model can either be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param prefix     Beginning prefix to look for
+ */
+void cvmx_csr_db_display_list(int identifier, const char *prefix)
+{
+    int i, len;
+    int chip = cvmx_db_get_chipindex(identifier);
+    if (prefix == NULL)
+        prefix = "";
+    if (strncasecmp(prefix, "CVMX_", 5) == 0)
+        prefix += 5;
+    len = strlen(prefix);
+
+    i=0;
+    while (cvmx_csr_db_addresses[chip][i].name)
+    {
+        if (strncasecmp(prefix, cvmx_csr_db_addresses[chip][i].name, len) == 0)
+            PRINTF("%s\n", cvmx_csr_db_addresses[chip][i].name);
+        i++;
+    }
+}
+#endif
diff --git a/cvmx-csr-db.c b/cvmx-csr-db.c
new file mode 100644
index 0000000000000..ef44facac5d48
--- /dev/null
+++ b/cvmx-csr-db.c
@@ -0,0 +1,74292 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and type definitions for
+ * Octeon.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-csr-db.h"
+
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	4,	0},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	4,	4},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	3,	8},
+	{"cvmx_asx#_rld_bypass"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	2,	11},
+	{"cvmx_asx#_rld_bypass_setting",	CVMX_CSR_DB_TYPE_RSL,	64,	8,	2,	13},
+	{"cvmx_asx#_rld_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	3,	15},
+	{"cvmx_asx#_rld_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	3,	18},
+	{"cvmx_asx#_rld_fcram_mode"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	21},
+	{"cvmx_asx#_rld_nctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	23},
+	{"cvmx_asx#_rld_nctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	25},
+	{"cvmx_asx#_rld_pctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	27},
+	{"cvmx_asx#_rld_pctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	29},
+	{"cvmx_asx#_rld_setting"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	31},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	33},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	35},
+	{"cvmx_asx#_rx_wol"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	3,	37},
+	{"cvmx_asx#_rx_wol_msk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	1,	40},
+	{"cvmx_asx#_rx_wol_powok"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	2,	41},
+	{"cvmx_asx#_rx_wol_sig"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	43},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	45},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	3,	47},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	50},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	2,	52},
+	{"cvmx_asx0_dbg_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	3,	54},
+	{"cvmx_asx0_dbg_data_enable"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	2,	57},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	66,	2,	59},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	67,	2,	61},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	68,	2,	63},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	69,	2,	65},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	70,	15,	67},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	103,	2,	82},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	136,	15,	84},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	169,	2,	99},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	170,	2,	101},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	186,	2,	103},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	202,	2,	105},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	203,	2,	107},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	204,	2,	109},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	205,	1,	111},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	221,	3,	112},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	222,	2,	115},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	223,	4,	117},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	2,	121},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	225,	3,	123},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	229,	7,	126},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	245,	7,	133},
+	{"cvmx_dfa_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	246,	3,	140},
+	{"cvmx_dfa_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	247,	10,	143},
+	{"cvmx_dfa_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	248,	2,	153},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	249,	2,	155},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	250,	4,	157},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	251,	3,	161},
+	{"cvmx_dfa_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	21,	164},
+	{"cvmx_dfa_memcfg0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	253,	16,	185},
+	{"cvmx_dfa_memcfg1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	254,	11,	201},
+	{"cvmx_dfa_memcfg2"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	255,	8,	212},
+	{"cvmx_dfa_memfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	256,	6,	220},
+	{"cvmx_dfa_memfcr"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	257,	6,	226},
+	{"cvmx_dfa_memrld"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	258,	2,	232},
+	{"cvmx_dfa_ncbctl"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	259,	8,	234},
+	{"cvmx_dfa_sbd_dbg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	260,	1,	242},
+	{"cvmx_dfa_sbd_dbg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	261,	1,	243},
+	{"cvmx_dfa_sbd_dbg2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	262,	1,	244},
+	{"cvmx_dfa_sbd_dbg3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	263,	1,	245},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	264,	6,	246},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	265,	7,	252},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	266,	3,	259},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	273,	2,	262},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	280,	3,	264},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	281,	2,	267},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	282,	29,	269},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	283,	29,	298},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	284,	2,	327},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	292,	2,	329},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	300,	3,	331},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	301,	3,	334},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	302,	2,	337},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	303,	2,	339},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	304,	8,	341},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	306,	2,	349},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	308,	3,	351},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	310,	2,	354},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	312,	5,	356},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	320,	1,	361},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	328,	1,	362},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	336,	1,	363},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	344,	1,	364},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	352,	1,	365},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	360,	1,	366},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	368,	2,	367},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	376,	4,	369},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	384,	2,	373},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	392,	11,	375},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	400,	9,	386},
+	{"cvmx_gmx#_rx#_frm_max"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	2,	395},
+	{"cvmx_gmx#_rx#_frm_min"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	2,	397},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	424,	2,	399},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	432,	20,	401},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	440,	20,	421},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	448,	2,	441},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	456,	4,	443},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	2,	447},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	2,	449},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	480,	2,	451},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	488,	2,	453},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	496,	2,	455},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	504,	2,	457},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	512,	2,	459},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	520,	2,	461},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	528,	2,	463},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	536,	2,	465},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	544,	4,	467},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	552,	2,	471},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	560,	2,	473},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	568,	2,	475},
+	{"cvmx_gmx#_rx_pass_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	576,	2,	477},
+	{"cvmx_gmx#_rx_pass_map#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	578,	2,	479},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	610,	2,	481},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	612,	2,	483},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	620,	3,	485},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	622,	5,	488},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	630,	2,	493},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	638,	2,	495},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	646,	3,	497},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	654,	2,	500},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	662,	2,	502},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	670,	2,	504},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	678,	2,	506},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	686,	2,	508},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	694,	2,	510},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	702,	2,	512},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	710,	2,	514},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	718,	2,	516},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	726,	2,	518},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	734,	2,	520},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	742,	2,	522},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	750,	2,	524},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	758,	2,	526},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	766,	2,	528},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	774,	2,	530},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	782,	2,	532},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	790,	2,	534},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	798,	2,	536},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	806,	2,	538},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	808,	2,	540},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	2,	542},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	3,	544},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	814,	7,	547},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	816,	7,	554},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	818,	2,	561},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	820,	2,	563},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	822,	4,	565},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	824,	2,	569},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	826,	2,	571},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	828,	2,	573},
+	{"cvmx_gmx#_tx_spi_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	830,	3,	575},
+	{"cvmx_gmx#_tx_spi_max"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	832,	3,	578},
+	{"cvmx_gmx#_tx_spi_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	834,	2,	581},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	836,	7,	583},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	852,	2,	590},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	853,	2,	592},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	854,	2,	594},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	855,	2,	596},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	856,	19,	598},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	857,	6,	617},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	858,	3,	623},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	859,	3,	626},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	860,	3,	629},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	861,	5,	632},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	862,	5,	637},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	863,	1,	642},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	864,	1,	643},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	865,	5,	644},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	866,	5,	649},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	867,	3,	654},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	868,	3,	657},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	869,	3,	660},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	870,	5,	663},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	871,	5,	668},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	872,	1,	673},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	873,	1,	674},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	874,	3,	675},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	875,	3,	678},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	876,	3,	681},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	877,	2,	684},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	878,	2,	686},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	879,	2,	688},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	880,	2,	690},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	881,	17,	692},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	882,	2,	709},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	883,	1,	711},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	884,	9,	712},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	885,	6,	721},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	886,	6,	727},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	887,	2,	733},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	888,	2,	735},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	889,	3,	737},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	925,	2,	740},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	961,	6,	742},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	962,	2,	748},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	970,	2,	750},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	971,	3,	752},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	972,	5,	755},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	980,	3,	760},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	981,	2,	763},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	982,	2,	765},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	983,	4,	767},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	984,	3,	771},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	985,	5,	774},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	986,	5,	779},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	987,	5,	784},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	988,	5,	789},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	989,	8,	794},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	990,	9,	802},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	991,	8,	811},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	992,	5,	819},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	993,	4,	824},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	994,	2,	828},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	995,	14,	830},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	996,	19,	844},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	997,	3,	863},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	3,	866},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	999,	2,	869},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	17,	871},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1004,	5,	888},
+	{"cvmx_l2c_spar1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1005,	5,	893},
+	{"cvmx_l2c_spar2"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	5,	898},
+	{"cvmx_l2c_spar3"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1007,	5,	903},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1008,	2,	908},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1009,	3,	910},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1010,	2,	913},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1011,	2,	915},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1012,	2,	917},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1013,	7,	919},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1014,	4,	926},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1015,	3,	930},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1016,	3,	933},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1017,	2,	936},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1018,	2,	938},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	2,	940},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1020,	4,	942},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1021,	13,	946},
+	{"cvmx_led_blink"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1022,	2,	959},
+	{"cvmx_led_clk_phase"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1023,	2,	961},
+	{"cvmx_led_cylon"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1024,	2,	963},
+	{"cvmx_led_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1025,	2,	965},
+	{"cvmx_led_en"                 ,	CVMX_CSR_DB_TYPE_RSL,	64,	1026,	2,	967},
+	{"cvmx_led_polarity"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	2,	969},
+	{"cvmx_led_prt"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1028,	2,	971},
+	{"cvmx_led_prt_fmt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1029,	2,	973},
+	{"cvmx_led_prt_status#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1030,	2,	975},
+	{"cvmx_led_udd_cnt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1038,	2,	977},
+	{"cvmx_led_udd_dat#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1040,	2,	979},
+	{"cvmx_led_udd_dat_clr#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1042,	2,	981},
+	{"cvmx_led_udd_dat_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1044,	2,	983},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1046,	9,	985},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1047,	19,	994},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1048,	2,	1013},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1049,	2,	1015},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1050,	18,	1017},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1051,	5,	1035},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1052,	6,	1040},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1053,	2,	1046},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1054,	2,	1048},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1055,	14,	1050},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1056,	9,	1064},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1057,	2,	1073},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1058,	2,	1075},
+	{"cvmx_lmc#_pll_bwctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	3,	1077},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1060,	9,	1080},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1061,	9,	1089},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1062,	4,	1098},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1063,	3,	1102},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1064,	3,	1105},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1065,	3,	1108},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1066,	5,	1111},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1068,	1,	1116},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1069,	6,	1117},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1077,	13,	1123},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1085,	4,	1136},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1086,	2,	1140},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1087,	2,	1142},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1088,	8,	1144},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1089,	7,	1152},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1090,	2,	1159},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1091,	8,	1161},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1092,	2,	1169},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1093,	8,	1171},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1094,	12,	1179},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1095,	3,	1191},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1096,	3,	1194},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1097,	2,	1197},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1099,	2,	1199},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1101,	2,	1201},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1103,	7,	1203},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1105,	2,	1210},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1107,	7,	1212},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1109,	4,	1219},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1111,	8,	1223},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1113,	9,	1231},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1115,	7,	1240},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1117,	9,	1247},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1119,	2,	1256},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1121,	2,	1258},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1123,	4,	1260},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1125,	2,	1264},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1127,	2,	1266},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1129,	2,	1268},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1131,	4,	1270},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1133,	2,	1274},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1135,	2,	1276},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1137,	2,	1278},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1139,	2,	1280},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1141,	2,	1282},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1143,	2,	1284},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1145,	6,	1286},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1147,	2,	1292},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1151,	2,	1294},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1155,	21,	1296},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1156,	3,	1317},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1160,	21,	1320},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1161,	2,	1341},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1162,	13,	1343},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1163,	3,	1356},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1164,	3,	1359},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1165,	3,	1362},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1166,	3,	1365},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1167,	2,	1368},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1168,	2,	1370},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1169,	9,	1372},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1170,	43,	1381},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1171,	43,	1424},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1172,	2,	1467},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1173,	2,	1469},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1174,	8,	1471},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1178,	1,	1479},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1179,	2,	1480},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1183,	38,	1482},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1184,	3,	1520},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1188,	2,	1523},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1192,	3,	1525},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1196,	3,	1528},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1200,	3,	1531},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1201,	4,	1534},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1202,	2,	1538},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1203,	13,	1540},
+	{"cvmx_npi_port33_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1204,	13,	1553},
+	{"cvmx_npi_port34_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1205,	13,	1566},
+	{"cvmx_npi_port35_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1206,	13,	1579},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1207,	3,	1592},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1208,	33,	1595},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1209,	2,	1628},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1213,	2,	1630},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1214,	5,	1632},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1246,	2,	1637},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1247,	24,	1639},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1248,	2,	1663},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1249,	7,	1665},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1250,	5,	1672},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1251,	1,	1677},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1252,	5,	1678},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1253,	1,	1683},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1254,	4,	1684},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1255,	2,	1688},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1256,	1,	1690},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1257,	2,	1691},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1258,	4,	1693},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1259,	2,	1697},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1260,	4,	1699},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1261,	16,	1703},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1262,	1,	1719},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1263,	1,	1720},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1264,	18,	1721},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1265,	1,	1739},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1266,	1,	1740},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1267,	7,	1741},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1268,	7,	1748},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1269,	13,	1755},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1270,	10,	1768},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1271,	10,	1778},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1272,	7,	1788},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1273,	2,	1795},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1274,	1,	1797},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1275,	2,	1798},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1276,	16,	1800},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	1277,	2,	1816},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	1281,	1,	1818},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1283,	1,	1819},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	1285,	1,	1820},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1287,	1,	1821},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1291,	35,	1822},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1292,	35,	1857},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1293,	35,	1892},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1294,	35,	1927},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	1295,	2,	1962},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1296,	2,	1964},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	1300,	1,	1966},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	1304,	1,	1967},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	1308,	1,	1968},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1312,	3,	1969},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1313,	3,	1972},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1314,	3,	1975},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1315,	3,	1978},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1316,	2,	1981},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1317,	2,	1983},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1318,	4,	1985},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1319,	1,	1989},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1320,	4,	1990},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1321,	1,	1994},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1322,	2,	1995},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1323,	5,	1997},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1324,	2,	2002},
+	{"cvmx_pip_crc_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	3,	2004},
+	{"cvmx_pip_crc_iv#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1327,	2,	2007},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1329,	4,	2009},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1333,	8,	2013},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1334,	16,	2021},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1335,	10,	2037},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1336,	10,	2047},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1337,	2,	2057},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1338,	18,	2059},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	25,	2077},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1410,	2,	2102},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1474,	2,	2104},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1482,	9,	2106},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1486,	2,	2115},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1487,	2,	2117},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1523,	2,	2119},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1559,	2,	2121},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1595,	2,	2123},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1631,	2,	2125},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1667,	2,	2127},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1703,	2,	2129},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1739,	2,	2131},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1775,	2,	2133},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1811,	2,	2135},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1847,	2,	2137},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1848,	2,	2139},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1884,	2,	2141},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1920,	2,	2143},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1956,	2,	2145},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2020,	2,	2147},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2021,	3,	2149},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2022,	3,	2152},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2023,	2,	2155},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2024,	2,	2157},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2025,	4,	2159},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2026,	5,	2163},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2027,	4,	2168},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2028,	5,	2172},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2029,	1,	2177},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2030,	4,	2178},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2031,	2,	2182},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2032,	5,	2184},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2033,	5,	2189},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2034,	1,	2194},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2035,	19,	2195},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2036,	7,	2214},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2037,	4,	2221},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2038,	6,	2225},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2039,	7,	2231},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2040,	9,	2238},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2041,	5,	2247},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2042,	13,	2252},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2043,	4,	2265},
+	{"cvmx_pko_reg_crc_ctl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2044,	3,	2269},
+	{"cvmx_pko_reg_crc_enable"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2046,	2,	2272},
+	{"cvmx_pko_reg_crc_iv#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2047,	2,	2274},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2049,	2,	2276},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2050,	3,	2278},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2051,	5,	2281},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2052,	3,	2286},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2053,	3,	2289},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2054,	2,	2292},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2055,	3,	2294},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2056,	13,	2297},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2057,	2,	2310},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2058,	9,	2312},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2059,	3,	2321},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2060,	2,	2324},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2068,	2,	2326},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2069,	2,	2328},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2070,	2,	2330},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2071,	2,	2332},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2087,	5,	2334},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2095,	8,	2339},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2103,	2,	2347},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2104,	2,	2349},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2105,	2,	2351},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2113,	3,	2353},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2114,	4,	2356},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2130,	5,	2360},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2131,	7,	2365},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2147,	2,	2372},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2163,	3,	2374},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2164,	5,	2377},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2165,	8,	2382},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2166,	6,	2390},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2167,	2,	2396},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2168,	4,	2398},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2169,	4,	2402},
+	{"cvmx_spx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2170,	2,	2406},
+	{"cvmx_spx#_bist_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2172,	4,	2408},
+	{"cvmx_spx#_clk_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2174,	11,	2412},
+	{"cvmx_spx#_clk_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	9,	2423},
+	{"cvmx_spx#_dbg_deskew_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	16,	2432},
+	{"cvmx_spx#_dbg_deskew_state"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	5,	2448},
+	{"cvmx_spx#_drv_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	4,	2453},
+	{"cvmx_spx#_err_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2184,	6,	2457},
+	{"cvmx_spx#_int_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2186,	6,	2463},
+	{"cvmx_spx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2188,	12,	2469},
+	{"cvmx_spx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2190,	14,	2481},
+	{"cvmx_spx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2192,	12,	2495},
+	{"cvmx_spx#_tpa_acc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2194,	2,	2507},
+	{"cvmx_spx#_tpa_max"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2196,	2,	2509},
+	{"cvmx_spx#_tpa_sel"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2198,	2,	2511},
+	{"cvmx_spx#_trn4_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2200,	8,	2513},
+	{"cvmx_spx0_pll_bw_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2202,	2,	2521},
+	{"cvmx_spx0_pll_setting"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2203,	2,	2523},
+	{"cvmx_srx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2204,	5,	2525},
+	{"cvmx_srx#_ign_rx_full"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2206,	2,	2530},
+	{"cvmx_srx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2208,	6,	2532},
+	{"cvmx_srx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2272,	4,	2538},
+	{"cvmx_stx#_arb_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2274,	5,	2542},
+	{"cvmx_stx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2276,	2,	2547},
+	{"cvmx_stx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2278,	4,	2549},
+	{"cvmx_stx#_dip_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2280,	3,	2553},
+	{"cvmx_stx#_ign_cal"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2282,	2,	2556},
+	{"cvmx_stx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2284,	9,	2558},
+	{"cvmx_stx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2286,	10,	2567},
+	{"cvmx_stx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2288,	9,	2577},
+	{"cvmx_stx#_min_bst"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2290,	2,	2586},
+	{"cvmx_stx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2292,	6,	2588},
+	{"cvmx_stx#_spi4_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	3,	2594},
+	{"cvmx_stx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	4,	2597},
+	{"cvmx_stx#_stat_bytes_hi"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	2,	2601},
+	{"cvmx_stx#_stat_bytes_lo"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	2,	2603},
+	{"cvmx_stx#_stat_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	3,	2605},
+	{"cvmx_stx#_stat_pkt_xmt"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	2,	2608},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2368,	6,	2610},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2369,	3,	2616},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2370,	5,	2619},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2371,	4,	2624},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2372,	6,	2628},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2373,	4,	2634},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2374,	2,	2638},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	4,	2640},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2376,	2,	2644},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	3,	2646},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	4,	2649},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	12,	2653},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	3,	2665},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	2,	2668},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2382,	2,	2670},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2383,	17,	2672},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2384,	12,	2689},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2385,	6,	2701},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2386,	5,	2707},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2387,	1,	2712},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2388,	2,	2713},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2389,	2,	2715},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2390,	17,	2717},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2391,	12,	2734},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2392,	6,	2746},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2393,	2,	2752},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2394,	2,	2754},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2395,	17,	2756},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2396,	12,	2773},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2397,	6,	2785},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2398,	3,	2791},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2399,	5,	2794},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2400,	3,	2799},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2401,	6,	2802},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	2402,	2,	2808},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	2403,	2,	2810},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2404,	2,	2812},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_FCRAM_MODE"         ,	   0x11800B0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_FCRAM_MODE"         ,	   0x11800B8000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_RX_WOL"                 ,	   0x11800B0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_RX_WOL"                 ,	   0x11800B8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_RX_WOL_MSK"             ,	   0x11800B0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_RX_WOL_MSK"             ,	   0x11800B8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_RX_WOL_POWOK"           ,	   0x11800B0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_RX_WOL_POWOK"           ,	   0x11800B8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_RX_WOL_SIG"             ,	   0x11800B0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX1_RX_WOL_SIG"             ,	   0x11800B8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT20_EN0"               ,	   0x1070000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT21_EN0"               ,	   0x1070000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT22_EN0"               ,	   0x1070000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT20_EN1"               ,	   0x1070000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT21_EN1"               ,	   0x1070000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET10"              ,	   0x1070000000650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET11"              ,	   0x1070000000658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET12"              ,	   0x1070000000660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET13"              ,	   0x1070000000668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET14"              ,	   0x1070000000670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET15"              ,	   0x1070000000678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG12"                  ,	   0x1070000000560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"DFA_ERR"                     ,	   0x1180030000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"DFA_MEMCFG0"                 ,	   0x1180030000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"DFA_MEMCFG1"                 ,	   0x1180030000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"DFA_MEMCFG2"                 ,	   0x1180030000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"DFA_MEMFADR"                 ,	   0x1180030000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"DFA_MEMFCR"                  ,	   0x1180030000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"DFA_MEMRLD"                  ,	   0x1180030000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"DFA_NCBCTL"                  ,	   0x1180030000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"DFA_SBD_DBG0"                ,	   0x1180030000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX000_FRM_MAX"          ,	   0x1180008000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX001_FRM_MAX"          ,	   0x1180008000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX002_FRM_MAX"          ,	   0x1180008001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX003_FRM_MAX"          ,	   0x1180008001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX000_FRM_MAX"          ,	   0x1180010000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX001_FRM_MAX"          ,	   0x1180010000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX002_FRM_MAX"          ,	   0x1180010001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX003_FRM_MAX"          ,	   0x1180010001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX000_FRM_MIN"          ,	   0x1180008000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_FRM_MIN"          ,	   0x1180008000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_FRM_MIN"          ,	   0x1180008001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX003_FRM_MIN"          ,	   0x1180008001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX000_FRM_MIN"          ,	   0x1180010000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX001_FRM_MIN"          ,	   0x1180010000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX002_FRM_MIN"          ,	   0x1180010001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX003_FRM_MIN"          ,	   0x1180010001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX003_RX_INBND"         ,	   0x1180008001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX000_RX_INBND"         ,	   0x1180010000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX001_RX_INBND"         ,	   0x1180010000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX002_RX_INBND"         ,	   0x1180010001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX003_RX_INBND"         ,	   0x1180010001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP003"         ,	   0x1180008000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP004"         ,	   0x1180008000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP005"         ,	   0x1180008000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP006"         ,	   0x1180008000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP007"         ,	   0x1180008000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP008"         ,	   0x1180008000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP009"         ,	   0x1180008000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP010"         ,	   0x1180008000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP011"         ,	   0x1180008000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP012"         ,	   0x1180008000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP013"         ,	   0x1180008000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP014"         ,	   0x1180008000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP015"         ,	   0x1180008000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP000"         ,	   0x1180010000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP001"         ,	   0x1180010000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP002"         ,	   0x1180010000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP003"         ,	   0x1180010000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP004"         ,	   0x1180010000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP005"         ,	   0x1180010000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP006"         ,	   0x1180010000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP007"         ,	   0x1180010000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP008"         ,	   0x1180010000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP009"         ,	   0x1180010000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP010"         ,	   0x1180010000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP011"         ,	   0x1180010000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP012"         ,	   0x1180010000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"L2C_SPAR3"                   ,	   0x1180080000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LMC0_PLL_BWCTL"              ,	   0x1180088000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	324},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	325},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	335},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	354},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	355},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	356},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	357},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	358},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	359},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	360},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	361},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	362},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	363},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	364},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	365},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	366},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	367},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	368},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	369},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	370},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	371},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	372},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	373},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	384},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
+	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
+	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
+	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	385},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	386},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	386},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	387},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	387},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	388},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	388},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
+	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
+	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
+	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	389},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	390},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	391},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	392},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	393},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	394},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_PKT_CREDITS3"            ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_PKTS_SENT2"              ,	              0x60ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_PKTS_SENT3"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	399},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	400},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	401},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	403},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	404},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	405},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	406},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	407},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	408},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	409},
+	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PKO_REG_CRC_CTL0"            ,	   0x1180050000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PKO_REG_CRC_CTL1"            ,	   0x1180050000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PKO_REG_CRC_ENABLE"          ,	   0x1180050000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PKO_REG_CRC_IV0"             ,	   0x1180050000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PKO_REG_CRC_IV1"             ,	   0x1180050000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	476},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	477},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	482},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK12"            ,	   0x1670000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	491},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"SPX1_CLK_STAT"               ,	   0x1180098000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"SPX0_DBG_DESKEW_CTL"         ,	   0x1180090000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"SPX1_DBG_DESKEW_CTL"         ,	   0x1180098000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"SPX0_DBG_DESKEW_STATE"       ,	   0x1180090000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"SPX1_DBG_DESKEW_STATE"       ,	   0x1180098000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"SPX0_DRV_CTL"                ,	   0x1180090000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"SPX1_DRV_CTL"                ,	   0x1180098000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"SPX0_ERR_CTL"                ,	   0x1180090000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"SPX1_ERR_CTL"                ,	   0x1180098000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"SPX0_INT_DAT"                ,	   0x1180090000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"SPX1_INT_DAT"                ,	   0x1180098000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"SPX0_INT_MSK"                ,	   0x1180090000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"SPX1_INT_MSK"                ,	   0x1180098000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"SPX0_INT_REG"                ,	   0x1180090000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"SPX1_INT_REG"                ,	   0x1180098000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"SPX0_INT_SYNC"               ,	   0x1180090000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"SPX1_INT_SYNC"               ,	   0x1180098000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"SPX0_TPA_ACC"                ,	   0x1180090000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"SPX1_TPA_ACC"                ,	   0x1180098000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"SPX0_TPA_MAX"                ,	   0x1180090000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"SPX1_TPA_MAX"                ,	   0x1180098000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"SPX0_TPA_SEL"                ,	   0x1180090000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"SPX1_TPA_SEL"                ,	   0x1180098000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"SPX0_TRN4_CTL"               ,	   0x1180090000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"SPX1_TRN4_CTL"               ,	   0x1180098000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"SPX0_PLL_BW_CTL"             ,	   0x1180090000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"SPX0_PLL_SETTING"            ,	   0x1180090000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"SRX0_COM_CTL"                ,	   0x1180090000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"SRX1_COM_CTL"                ,	   0x1180098000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"SRX0_IGN_RX_FULL"            ,	   0x1180090000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"SRX1_IGN_RX_FULL"            ,	   0x1180098000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"SRX0_SPI4_CAL000"            ,	   0x1180090000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL001"            ,	   0x1180090000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL002"            ,	   0x1180090000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL003"            ,	   0x1180090000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL004"            ,	   0x1180090000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL005"            ,	   0x1180090000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL006"            ,	   0x1180090000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL007"            ,	   0x1180090000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL008"            ,	   0x1180090000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL009"            ,	   0x1180090000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL010"            ,	   0x1180090000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL011"            ,	   0x1180090000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL012"            ,	   0x1180090000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL013"            ,	   0x1180090000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL014"            ,	   0x1180090000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL015"            ,	   0x1180090000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL016"            ,	   0x1180090000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL003"            ,	   0x1180098000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL004"            ,	   0x1180098000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL005"            ,	   0x1180098000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL006"            ,	   0x1180098000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL007"            ,	   0x1180098000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL008"            ,	   0x1180098000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL009"            ,	   0x1180098000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL010"            ,	   0x1180098000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL011"            ,	   0x1180098000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL012"            ,	   0x1180098000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL013"            ,	   0x1180098000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL014"            ,	   0x1180098000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL015"            ,	   0x1180098000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL016"            ,	   0x1180098000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"STX0_ARB_CTL"                ,	   0x1180090000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"STX1_ARB_CTL"                ,	   0x1180098000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"STX0_BCKPRS_CNT"             ,	   0x1180090000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"STX1_BCKPRS_CNT"             ,	   0x1180098000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"STX0_COM_CTL"                ,	   0x1180090000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"STX1_COM_CTL"                ,	   0x1180098000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"STX0_DIP_CNT"                ,	   0x1180090000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL001"            ,	   0x1180090000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL002"            ,	   0x1180090000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL003"            ,	   0x1180090000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL004"            ,	   0x1180090000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL005"            ,	   0x1180090000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL006"            ,	   0x1180090000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL007"            ,	   0x1180090000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL008"            ,	   0x1180090000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL009"            ,	   0x1180090000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL010"            ,	   0x1180090000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL011"            ,	   0x1180090000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL012"            ,	   0x1180090000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL013"            ,	   0x1180090000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL014"            ,	   0x1180090000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL015"            ,	   0x1180090000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL016"            ,	   0x1180090000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL003"            ,	   0x1180098000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL004"            ,	   0x1180098000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL005"            ,	   0x1180098000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL006"            ,	   0x1180098000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL007"            ,	   0x1180098000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL008"            ,	   0x1180098000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL009"            ,	   0x1180098000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL010"            ,	   0x1180098000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL011"            ,	   0x1180098000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL012"            ,	   0x1180098000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL013"            ,	   0x1180098000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL014"            ,	   0x1180098000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL015"            ,	   0x1180098000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL016"            ,	   0x1180098000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"STX1_SPI4_STAT"              ,	   0x1180098000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"STX0_STAT_BYTES_HI"          ,	   0x1180090000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"STX1_STAT_BYTES_HI"          ,	   0x1180098000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"STX0_STAT_BYTES_LO"          ,	   0x1180090000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"STX1_STAT_BYTES_LO"          ,	   0x1180098000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"STX0_STAT_CTL"               ,	   0x1180090000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"STX1_STAT_CTL"               ,	   0x1180098000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"STX0_STAT_PKT_XMT"           ,	   0x1180090000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"STX1_STAT_PKT_XMT"           ,	   0x1180098000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"OVRFLW"                      ,	0,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPOP"                       ,	4,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPSH"                       ,	8,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	4,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	8,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	1,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_LOOP"                    ,	4,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	1,	3,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	3,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	4,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	5,	"RO",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	4,	5,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	5,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	6,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	7,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	7,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	8,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	8,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	9,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	10,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	11,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	12,	"RO",	1,	1,	0,	0},
+	{"RESERVED_5_63"               ,	5,	59,	12,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	13,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	13,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	14,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	14,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	15,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	1,	1,	15,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	15,	"RAZ",	1,	1,	0,	0},
+	{"MSK"                         ,	0,	64,	16,	"R/W",	0,	1,	0ull,	0},
+	{"POWEROK"                     ,	0,	1,	17,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	17,	"RAZ",	1,	1,	0,	0},
+	{"SIG"                         ,	0,	32,	18,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	18,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	19,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	19,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	20,	"R/W",	0,	0,	8ull,	8ull},
+	{"PCTL"                        ,	4,	4,	20,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_8_63"               ,	8,	56,	20,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	4,	21,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	22,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	22,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	23,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	4,	4,	23,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	23,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	24,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	24,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	25,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	25,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	16,	26,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	26,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	16,	27,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	27,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	28,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	28,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	29,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	29,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	30,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	31,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	32,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	32,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	33,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	33,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	34,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	34,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	16,	35,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	35,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	36,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	36,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	16,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	37,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	38,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	39,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	15,	39,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	39,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	40,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	40,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	41,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	41,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	41,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	42,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	42,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	43,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	44,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	45,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	45,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	45,	"RO",	1,	1,	0,	0},
+	{"CCLK_DIV2"                   ,	23,	1,	45,	"RO",	1,	1,	0,	0},
+	{"DCLK_MUL2"                   ,	24,	1,	45,	"RO",	1,	1,	0,	0},
+	{"D_MUL"                       ,	25,	4,	45,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	45,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	16,	46,	"RO",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	16,	16,	46,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	46,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P1_BRF"                      ,	0,	8,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BRF"                      ,	8,	8,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"P1_BWB"                      ,	16,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BWB"                      ,	17,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"CRF"                         ,	18,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"DRF"                         ,	19,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	20,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"IFU"                         ,	21,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	22,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	47,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SARB"                        ,	0,	1,	48,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	48,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	49,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	49,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	50,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	50,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	50,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	50,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	51,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	31,	51,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	51,	"RAZ",	1,	1,	0,	0},
+	{"CP2ECCENA"                   ,	0,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SBE"                      ,	1,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2DBE"                      ,	2,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2SBINA"                    ,	3,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2DBINA"                    ,	4,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SYN"                      ,	5,	8,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEECCENA"                   ,	13,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESBE"                      ,	14,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEDBE"                      ,	15,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTESBINA"                    ,	16,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEDBINA"                    ,	17,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESYN"                      ,	18,	7,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEPARENA"                   ,	25,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEPERR"                     ,	26,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEPINA"                     ,	27,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PARENA"                   ,	28,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PERR"                     ,	29,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2PINA"                     ,	30,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBLOVF"                      ,	31,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBLINA"                      ,	32,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	52,	"RAZ",	1,	1,	0,	0},
+	{"ENA_P1"                      ,	0,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENA_P0"                      ,	1,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	53,	"RAZ",	1,	1,	0,	0},
+	{"MTYPE"                       ,	3,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_LAT"                     ,	4,	2,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"RW_DLY"                      ,	6,	4,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_DLY"                      ,	10,	4,	53,	"R/W",	0,	0,	2ull,	2ull},
+	{"FPRCH"                       ,	14,	2,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	16,	2,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLEN"                        ,	18,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBUNK"                       ,	19,	3,	53,	"R/W",	0,	0,	2ull,	2ull},
+	{"R2R_PBUNK"                   ,	22,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_P1"                     ,	23,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"INIT_P0"                     ,	24,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUNK_INIT"                   ,	25,	2,	53,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_27_63"              ,	27,	37,	53,	"RAZ",	1,	1,	0,	0},
+	{"REF_INT"                     ,	0,	4,	54,	"R/W",	0,	0,	3ull,	3ull},
+	{"TSKW"                        ,	4,	2,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	54,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TRL"                         ,	8,	4,	54,	"R/W",	0,	0,	6ull,	6ull},
+	{"TWL"                         ,	12,	4,	54,	"R/W",	0,	0,	7ull,	7ull},
+	{"TRC"                         ,	16,	4,	54,	"R/W",	0,	0,	6ull,	6ull},
+	{"TMRSC"                       ,	20,	3,	54,	"R/W",	0,	0,	6ull,	6ull},
+	{"MRS_ENA"                     ,	23,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"AREF_ENA"                    ,	24,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"REF_INTLO"                   ,	25,	9,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	54,	"RAZ",	1,	1,	0,	0},
+	{"FCRAM2P"                     ,	0,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXBNK"                      ,	1,	1,	55,	"R/W",	0,	0,	1ull,	1ull},
+	{"UA_START"                    ,	2,	2,	55,	"R/W",	0,	0,	1ull,	1ull},
+	{"REFSHORT"                    ,	4,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRFC"                        ,	5,	5,	55,	"R/W",	0,	0,	9ull,	9ull},
+	{"SILRST"                      ,	10,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	11,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	55,	"RAZ",	1,	1,	0,	0},
+	{"MADDR"                       ,	0,	24,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"BNUM"                        ,	24,	3,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"PNUM"                        ,	27,	1,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	28,	2,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"FDST"                        ,	30,	9,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	56,	"RAZ",	1,	1,	0,	0},
+	{"MRS"                         ,	0,	15,	57,	"R/W",	0,	0,	66ull,	66ull},
+	{"RESERVED_15_15"              ,	15,	1,	57,	"RAZ",	1,	1,	0,	0},
+	{"EMRS"                        ,	16,	15,	57,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_31_31"              ,	31,	1,	57,	"RAZ",	1,	1,	0,	0},
+	{"EMRS2"                       ,	32,	15,	57,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	57,	"RAZ",	1,	1,	0,	0},
+	{"MRSDAT"                      ,	0,	23,	58,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_23_63"              ,	23,	41,	58,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"DTMODE"                      ,	3,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"DCMODE"                      ,	4,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDLCK"                      ,	5,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	4,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	59,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	60,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	61,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	62,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	63,	"RO",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	64,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	65,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	66,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	66,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	66,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	67,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	67,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	68,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	68,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	68,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	69,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	69,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	70,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	71,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	72,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	73,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	73,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	74,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	74,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	74,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	75,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	75,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	75,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	76,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	76,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	77,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	77,	"RAZ",	1,	1,	0,	0},
+	{"OUT_COL"                     ,	0,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_OVR"                     ,	1,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	16,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_21"              ,	18,	4,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	78,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	79,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	80,	"RO",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	80,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	80,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	81,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	81,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	82,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	82,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	82,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	82,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	82,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	83,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	84,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	85,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	86,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	87,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	88,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	89,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	89,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	90,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	90,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	90,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	91,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	91,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	92,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_FREE"                    ,	6,	1,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLAN_LEN"                    ,	7,	1,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	93,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	94,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	94,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	95,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	95,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	96,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	96,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	97,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	98,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	99,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	99,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	100,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	100,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	100,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	100,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	101,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	101,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	102,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	103,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	104,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	105,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	106,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	106,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	107,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	107,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	108,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	108,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	109,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	109,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	110,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	110,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	111,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	111,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	112,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	112,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	113,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	113,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	114,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	114,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	16,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	115,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	4,	116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	116,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	117,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	117,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	118,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	118,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	119,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	119,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	119,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	120,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	120,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	120,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	120,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	120,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	121,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	121,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	122,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	122,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	123,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	123,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	123,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	124,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	124,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	125,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	125,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	126,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	126,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	127,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	127,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	128,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	128,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	129,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	129,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	130,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	130,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	131,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	131,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	133,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	133,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	134,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	134,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	135,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	135,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	141,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	142,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	142,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	143,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	143,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	144,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	144,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	145,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	145,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	146,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	146,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	146,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	147,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	147,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	148,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	148,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	148,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	149,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	149,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	150,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	150,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	151,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	152,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	152,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	153,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	153,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	154,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	154,	"RAZ",	1,	1,	0,	0},
+	{"CONT_PKT"                    ,	0,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"TPA_CLR"                     ,	1,	1,	155,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	155,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX1"                        ,	0,	8,	156,	"R/W",	0,	1,	8ull,	0},
+	{"MAX2"                        ,	8,	8,	156,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	156,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	6,	157,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	157,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	158,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	159,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	159,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	160,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	160,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	161,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	161,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	162,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	162,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	163,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	164,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	164,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	165,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	166,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	166,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	166,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	167,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	168,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	168,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	168,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	168,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	168,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	169,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	169,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	169,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	169,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	169,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	170,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	171,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	172,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	173,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	173,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	174,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	175,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	176,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	177,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	177,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	177,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	177,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	177,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	178,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	178,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	178,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	178,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	178,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	179,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	180,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	181,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	182,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	183,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	184,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	184,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	185,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	186,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	187,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	188,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	189,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	191,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	192,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	193,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	194,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	195,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	195,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	196,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	197,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	197,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	198,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	199,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	199,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	200,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	200,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	201,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	202,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	202,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	202,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	202,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	203,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	203,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	203,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	204,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	204,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	205,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	205,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	206,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	207,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	208,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	209,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	13,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	210,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	211,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"PICBST"                      ,	2,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RHDF"                        ,	4,	4,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	212,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	213,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	213,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	213,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	213,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	213,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	213,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	4,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	4,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	214,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	215,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	215,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	216,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	216,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	218,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	219,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	10,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	10,	17,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	220,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"STPARTDIS"                   ,	4,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	221,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	222,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	224,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK4"                       ,	0,	8,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK5"                       ,	8,	8,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK6"                       ,	16,	8,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK7"                       ,	24,	8,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	225,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK8"                       ,	0,	8,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK9"                       ,	8,	8,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK10"                      ,	16,	8,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK11"                      ,	24,	8,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	226,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK12"                      ,	0,	8,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK13"                      ,	8,	8,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK14"                      ,	16,	8,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK15"                      ,	24,	8,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	227,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	228,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	229,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	230,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	231,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	233,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	233,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	233,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	233,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	233,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	233,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	11,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	235,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	237,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	238,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	239,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_512K"                   ,	34,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_256K"                   ,	35,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	240,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	241,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	241,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	10,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	241,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	241,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	241,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RATE"                        ,	0,	8,	242,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_63"               ,	8,	56,	242,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	7,	243,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_7_63"               ,	7,	57,	243,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	0,	16,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	244,	"RAZ",	1,	1,	0,	0},
+	{"DBG_EN"                      ,	0,	1,	245,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	245,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	246,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	246,	"RAZ",	1,	1,	0,	0},
+	{"POLARITY"                    ,	0,	1,	247,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	247,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	8,	248,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	248,	"RAZ",	1,	1,	0,	0},
+	{"FORMAT"                      ,	0,	4,	249,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	249,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	250,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	250,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	251,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	251,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	32,	252,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	252,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	32,	253,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	253,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	32,	254,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	254,	"RAZ",	1,	1,	0,	0},
+	{"PCTL_DAT"                    ,	0,	4,	255,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CMD"                    ,	4,	4,	255,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CLK"                    ,	8,	4,	255,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	255,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	255,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CMD"                    ,	20,	4,	255,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CLK"                    ,	24,	4,	255,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	255,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	255,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	256,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	256,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	256,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE128B"                    ,	10,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"SET_ZERO"                    ,	11,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	256,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	256,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	256,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	256,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	256,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	257,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	258,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	259,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	259,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	259,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	259,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	259,	"R/W",	0,	0,	2ull,	2ull},
+	{"SILO_HC"                     ,	21,	1,	259,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	259,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	259,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	259,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	259,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRDSYN0"                     ,	0,	8,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	260,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	260,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	261,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	262,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	262,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	263,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	263,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	264,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	264,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	264,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	264,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	264,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	264,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	264,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	264,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	264,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	264,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	265,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	265,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	265,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	265,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	265,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	265,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	265,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	265,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	265,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	266,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	267,	"RAZ",	1,	1,	0,	0},
+	{"BWCTL"                       ,	0,	4,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWUPD"                       ,	4,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	268,	"RAZ",	1,	1,	0,	0},
+	{"RODT_LO0"                    ,	0,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	269,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	269,	"RAZ",	1,	1,	0,	0},
+	{"WODT_LO0"                    ,	0,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO1"                    ,	4,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO2"                    ,	8,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO3"                    ,	12,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI0"                    ,	16,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI1"                    ,	20,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI2"                    ,	24,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI3"                    ,	28,	4,	270,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"NCBI"                        ,	0,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	271,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	272,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	272,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	272,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	273,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	273,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	273,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	274,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	274,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	274,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	275,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	275,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	275,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	275,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	276,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	277,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	277,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_29"              ,	28,	2,	277,	"RAZ",	1,	1,	0,	0},
+	{"ORBIT"                       ,	30,	1,	277,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	277,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	277,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	278,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_54_59"              ,	54,	6,	278,	"RAZ",	1,	1,	0,	0},
+	{"PAGES"                       ,	60,	2,	278,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	278,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	278,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	279,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	279,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	279,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	279,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	280,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	280,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	281,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	281,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	16,	282,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	282,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	282,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	282,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	282,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	282,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	282,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	282,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	283,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	283,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	283,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	283,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	283,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	283,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	283,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	284,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	284,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	285,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	285,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	285,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	285,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	285,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	10,	286,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	286,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	287,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	287,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	287,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	287,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	287,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	287,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	287,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	287,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	288,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	288,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	288,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	288,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	288,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	288,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	288,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	288,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	289,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	289,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	289,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	290,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	290,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	290,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	291,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	291,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	292,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	293,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	293,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	294,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	294,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	294,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	294,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	294,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	294,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	294,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	295,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	295,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	296,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	296,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	296,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	296,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	296,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	296,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	296,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	297,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	297,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	297,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	297,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	298,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	298,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	298,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	299,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	299,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	299,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	299,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	299,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	299,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	299,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	299,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	299,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	300,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	301,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	301,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	301,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	301,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	301,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	301,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	301,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	301,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	301,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	302,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	302,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	303,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	303,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	304,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	304,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	304,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	304,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	305,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	306,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	307,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	308,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	308,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	308,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	308,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	309,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	309,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	310,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	311,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	312,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	312,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	313,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	313,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	314,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	314,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	315,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	315,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	315,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	315,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	315,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	315,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	316,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	317,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	317,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"POF3_BS"                     ,	5,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"POF2_BS"                     ,	6,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"POF1_BS"                     ,	7,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"POF0_BS"                     ,	8,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	318,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	319,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	319,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	320,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	320,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	320,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	320,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"INS1_64B"                    ,	43,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"INS2_64B"                    ,	44,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"INS3_64B"                    ,	45,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"INS0_ENB"                    ,	46,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS1_ENB"                    ,	47,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS2_ENB"                    ,	48,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS3_ENB"                    ,	49,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT0_ENB"                    ,	50,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT1_ENB"                    ,	51,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT2_ENB"                    ,	52,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT3_ENB"                    ,	53,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIS_PNIW"                    ,	54,	1,	320,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	320,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	320,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	321,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	322,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	322,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	322,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	322,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	322,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	322,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	323,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	324,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	324,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	325,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	325,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	325,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	326,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	326,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	327,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	328,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	328,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	329,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	329,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	329,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	329,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO1_2SML"                    ,	4,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO2_2SML"                    ,	5,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO3_2SML"                    ,	6,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_RTOUT"                    ,	8,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_RTOUT"                    ,	9,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_RTOUT"                    ,	10,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_OVERF"                    ,	12,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_OVERF"                    ,	13,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_OVERF"                    ,	14,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RTOUT"                    ,	16,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_RTOUT"                    ,	17,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_RTOUT"                    ,	18,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PERR"                     ,	20,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PERR"                     ,	21,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PERR"                     ,	22,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"G1_RTOUT"                    ,	24,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"G2_RTOUT"                    ,	25,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"G3_RTOUT"                    ,	26,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PPERR"                    ,	28,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PPERR"                    ,	29,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PPERR"                    ,	30,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PTOUT"                    ,	32,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PTOUT"                    ,	33,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PTOUT"                    ,	34,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_PPERR"                    ,	36,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_PPERR"                    ,	37,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_PPERR"                    ,	38,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_42_63"              ,	42,	22,	330,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO1_2SML"                    ,	4,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO2_2SML"                    ,	5,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO3_2SML"                    ,	6,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_RTOUT"                    ,	8,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_RTOUT"                    ,	9,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_RTOUT"                    ,	10,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_OVERF"                    ,	12,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_OVERF"                    ,	13,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_OVERF"                    ,	14,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RTOUT"                    ,	16,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_RTOUT"                    ,	17,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_RTOUT"                    ,	18,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PERR"                     ,	20,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PERR"                     ,	21,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PERR"                     ,	22,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G1_RTOUT"                    ,	24,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G2_RTOUT"                    ,	25,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G3_RTOUT"                    ,	26,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PPERR"                    ,	28,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PPERR"                    ,	29,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PPERR"                    ,	30,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PTOUT"                    ,	32,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PTOUT"                    ,	33,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PTOUT"                    ,	34,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_PPERR"                    ,	36,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_PPERR"                    ,	37,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_PPERR"                    ,	38,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	331,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	332,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	332,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	333,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	333,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	334,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	334,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	334,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	334,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	334,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	334,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	334,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	334,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	335,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	336,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	336,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL1"                     ,	4,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL1"                     ,	5,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL1"                     ,	6,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL2"                     ,	8,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL2"                     ,	9,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL2"                     ,	10,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL3"                     ,	12,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL3"                     ,	13,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL3"                     ,	14,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"IPTR_O0"                     ,	16,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O1"                     ,	17,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O2"                     ,	18,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O3"                     ,	19,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_23"              ,	20,	4,	337,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"O1_CSRM"                     ,	25,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"O2_CSRM"                     ,	26,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"O3_CSRM"                     ,	27,	1,	337,	"R/W",	0,	0,	0ull,	1ull},
+	{"O0_RO"                       ,	28,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O1_RO"                       ,	32,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O1_NS"                       ,	33,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O1_ES"                       ,	34,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O2_RO"                       ,	36,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O2_NS"                       ,	37,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O2_ES"                       ,	38,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O3_RO"                       ,	40,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O3_NS"                       ,	41,	1,	337,	"R/W",	0,	1,	0ull,	0},
+	{"O3_ES"                       ,	42,	2,	337,	"R/W",	0,	1,	0ull,	0},
+	{"P0_BMODE"                    ,	44,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"P1_BMODE"                    ,	45,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"P2_BMODE"                    ,	46,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"P3_BMODE"                    ,	47,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	337,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	338,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	338,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	338,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	339,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	339,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	340,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	340,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	340,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	341,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	342,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	342,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	342,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	343,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	343,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	344,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	344,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	345,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	345,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	345,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	345,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	345,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	346,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	346,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	346,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	346,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	346,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	347,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	347,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	347,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	347,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	347,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	348,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	348,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	348,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	348,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	348,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	348,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	349,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	349,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_8"                      ,	8,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_13"                     ,	13,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_14"                     ,	14,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_15"                     ,	15,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_21"                     ,	21,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_24"                     ,	24,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_25"                     ,	25,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_26"                     ,	26,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_27"                     ,	27,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_28"                     ,	28,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_29"                     ,	29,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_31"                     ,	31,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	350,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	32,	351,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	351,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	352,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	352,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	353,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	353,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	353,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	353,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	353,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	354,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	354,	"RO",	0,	0,	4ull,	4ull},
+	{"ISAE"                        ,	0,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	355,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	355,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	355,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	355,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	355,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	355,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	356,	"RO",	0,	0,	1ull,	1ull},
+	{"CC"                          ,	8,	24,	356,	"RO",	0,	0,	1048576ull,	1048576ull},
+	{"CLS"                         ,	0,	8,	357,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	357,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	357,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	358,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	358,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	358,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	358,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	358,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	359,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	360,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	360,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	360,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	361,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	362,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	362,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	363,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	363,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	364,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	365,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	365,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	366,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	366,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	366,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	366,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	367,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	367,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	368,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	368,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	368,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	368,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	369,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	369,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	369,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	369,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	369,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	370,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	371,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	372,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	372,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	372,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	372,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	372,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	372,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	372,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	373,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	374,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	375,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	375,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	375,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	375,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	375,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	376,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	376,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	376,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	376,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	376,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	377,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	377,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	377,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	377,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	377,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	377,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	377,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	377,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	377,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	377,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	377,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	378,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	378,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	378,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	378,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	379,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	379,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	379,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	379,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	379,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	379,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	379,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	380,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	380,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	380,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	381,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	381,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	382,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	383,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	383,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	384,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	384,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	384,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	384,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	384,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	384,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	384,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	384,	"RO",	1,	1,	0,	0},
+	{"AP_PCIX"                     ,	13,	1,	384,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_14"              ,	14,	1,	384,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	384,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	384,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	384,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	384,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	384,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	384,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	385,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	385,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	387,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	388,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	389,	"RO",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT1"                      ,	18,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT2"                      ,	19,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT3"                      ,	20,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME1"                     ,	22,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME2"                     ,	23,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME3"                     ,	24,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	390,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	390,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT1"                      ,	18,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT2"                      ,	19,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT3"                      ,	20,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME1"                     ,	22,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME2"                     ,	23,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME3"                     ,	24,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	391,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	392,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	393,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	393,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	393,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	394,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	394,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	395,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	395,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	396,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	397,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	398,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	399,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	399,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	399,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	400,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	400,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	400,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	401,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	401,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	401,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	402,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	402,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	402,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	403,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	403,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	404,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	404,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	405,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	3,	45,	405,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	405,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	405,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	406,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	407,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	407,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	407,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	407,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	408,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	409,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	410,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	410,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	410,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	410,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	410,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	411,	"RAZ",	1,	1,	0,	0},
+	{"REFLECT"                     ,	0,	1,	412,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	412,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	412,	"RAZ",	1,	1,	0,	0},
+	{"IV"                          ,	0,	32,	413,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	413,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	414,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	415,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	415,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	415,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	415,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	416,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	416,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	416,	"RAZ",	0,	1,	0ull,	0},
+	{"PKTDRP"                      ,	0,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	417,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	418,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	418,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	419,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	420,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	420,	"RAZ",	1,	1,	0,	0},
+	{"CRC_EN"                      ,	12,	1,	420,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	420,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	420,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	420,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	420,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	421,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	421,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	422,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	423,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	423,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	2,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	424,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	424,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	424,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	424,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	425,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	426,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	426,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	427,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	427,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	430,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	430,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	431,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	431,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	432,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	432,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	433,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	433,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	434,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	434,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	435,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	435,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	436,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	436,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	437,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	437,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	438,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	439,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	439,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	440,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	441,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	442,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	443,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	443,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	443,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	444,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	444,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	445,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	445,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	446,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	446,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	446,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	446,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	447,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	447,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	447,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	447,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	447,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	448,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	448,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	448,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	448,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	449,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	449,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	449,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	449,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	449,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	450,	"RO",	1,	0,	0,	0ull},
+	{"WIDX2"                       ,	0,	17,	451,	"RO",	1,	0,	0,	0ull},
+	{"RIDX2"                       ,	17,	17,	451,	"RO",	1,	0,	0,	0ull},
+	{"WIDX"                        ,	34,	17,	451,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	451,	"RAZ",	1,	0,	0,	0ull},
+	{"RIDX"                        ,	0,	17,	452,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	452,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	453,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	453,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	453,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	453,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	453,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	454,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	454,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	454,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	454,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	454,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	455,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	4,	456,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	4,	2,	456,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	6,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	7,	7,	456,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	17,	5,	456,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	22,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	26,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	456,	"RAZ",	1,	0,	0,	0ull},
+	{"CBUF_FRE"                    ,	28,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"XFER_DWR"                    ,	29,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"XFER_WOR"                    ,	30,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	31,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	32,	16,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CNT"                    ,	48,	13,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_LEN"                    ,	61,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_SOP"                    ,	62,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	63,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	0,	2,	457,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_UID"                    ,	2,	1,	457,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CHK"                    ,	3,	1,	457,	"RO",	1,	0,	0,	0ull},
+	{"WORK_MIN"                    ,	4,	3,	457,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	7,	1,	457,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFM"                    ,	8,	3,	457,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	457,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	458,	"RO",	1,	0,	0,	0ull},
+	{"START"                       ,	16,	33,	458,	"RO",	1,	0,	0,	0ull},
+	{"DWB"                         ,	49,	9,	458,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	458,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	459,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	459,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	459,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	459,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	459,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	459,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	460,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	460,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	460,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	460,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	460,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	460,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	460,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	461,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	461,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	461,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	461,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	461,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	461,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	461,	"WR0",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	461,	"WR0",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	461,	"WR0",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	462,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	462,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	462,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"PSB"                         ,	0,	7,	463,	"RO",	1,	0,	0,	0ull},
+	{"PDB"                         ,	7,	4,	463,	"RO",	1,	0,	0,	0ull},
+	{"QCB"                         ,	11,	2,	463,	"RO",	1,	0,	0,	0ull},
+	{"QSB"                         ,	13,	2,	463,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	15,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"CRC"                         ,	16,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"OUT"                         ,	17,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	18,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"WIF"                         ,	19,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"RIF"                         ,	20,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	21,	1,	463,	"RO",	1,	0,	0,	0ull},
+	{"PSB2"                        ,	22,	5,	463,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	464,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	464,	"RAZ",	1,	0,	0,	0ull},
+	{"REFIN"                       ,	0,	1,	465,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	465,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	465,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	32,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	466,	"RAZ",	1,	0,	0,	0ull},
+	{"IV"                          ,	0,	32,	467,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	467,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	17,	468,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	469,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	469,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	469,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	470,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	472,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	473,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	474,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR0"                        ,	0,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR1"                        ,	1,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND0"                       ,	2,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND1"                       ,	3,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	4,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	5,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	6,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	7,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	8,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	9,	1,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	475,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	16,	475,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	475,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	476,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	476,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	477,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	477,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	477,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	477,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	477,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	477,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	478,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	478,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	478,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	479,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	479,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	480,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	480,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	481,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	481,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	482,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	482,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	483,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"RESERVED_16_63"              ,	16,	48,	483,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	484,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	484,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	484,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	484,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	484,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	11,	485,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	485,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	11,	485,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	485,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	12,	485,	"RO",	0,	1,	2027ull,	0},
+	{"BUF_CNT"                     ,	36,	12,	485,	"RO",	0,	1,	0ull,	0},
+	{"DES_CNT"                     ,	48,	12,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	485,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	486,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	486,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	487,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	487,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	488,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	489,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	489,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	489,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	12,	490,	"RO",	0,	1,	0ull,	0},
+	{"DS_CNT"                      ,	12,	12,	490,	"RO",	0,	1,	0ull,	0},
+	{"TC_CNT"                      ,	24,	4,	490,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	490,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	491,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	491,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	491,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	491,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	11,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	492,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	11,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	492,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	492,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	492,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	493,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	493,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	494,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	494,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	494,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	495,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	496,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	496,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	496,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	496,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	496,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	496,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	497,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	497,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	1,	497,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	497,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	498,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	498,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	499,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	499,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	499,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	499,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	500,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	500,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	500,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	500,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	501,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	501,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STAT0"                       ,	0,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT1"                       ,	1,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT2"                       ,	2,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	502,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRXDLCK"                     ,	0,	1,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"RCVTRN"                      ,	1,	1,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"DRPTRN"                      ,	2,	1,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"SNDTRN"                      ,	3,	1,	503,	"R/W",	0,	0,	0ull,	1ull},
+	{"STATRCV"                     ,	4,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATDRV"                     ,	5,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUNBIST"                     ,	6,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDLY"                      ,	7,	5,	503,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_12_15"              ,	12,	4,	503,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SEETRN"                      ,	16,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	503,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	504,	"RAZ",	0,	1,	0ull,	0},
+	{"D4CLK0"                      ,	4,	1,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"D4CLK1"                      ,	5,	1,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK0"                      ,	6,	1,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK1"                      ,	7,	1,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"SRXTRN"                      ,	8,	1,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_9"                ,	9,	1,	504,	"RAZ",	0,	1,	0ull,	0},
+	{"STXCAL"                      ,	10,	1,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	504,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLLDIS"                      ,	0,	1,	505,	"R/W",	1,	0,	0,	0ull},
+	{"DLLFRC"                      ,	1,	1,	505,	"WR0",	1,	0,	0,	0ull},
+	{"OFFDLY"                      ,	2,	6,	505,	"R/W",	1,	0,	0,	0ull},
+	{"BITSEL"                      ,	8,	5,	505,	"R/W",	1,	1,	0,	0},
+	{"OFFSET"                      ,	13,	5,	505,	"R/W",	1,	1,	0,	0},
+	{"MUX"                         ,	18,	1,	505,	"WR0",	1,	1,	0,	0},
+	{"INC"                         ,	19,	1,	505,	"WR0",	1,	1,	0,	0},
+	{"DEC"                         ,	20,	1,	505,	"WR0",	1,	1,	0,	0},
+	{"CLRDLY"                      ,	21,	1,	505,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_22_23"              ,	22,	2,	505,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SSTEP"                       ,	24,	1,	505,	"R/W",	1,	0,	0,	0ull},
+	{"SSTEP_GO"                    ,	25,	1,	505,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_26_27"              ,	26,	2,	505,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FALL8"                       ,	28,	1,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALLNOP"                     ,	29,	1,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	505,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	5,	506,	"RO",	0,	1,	0ull,	0},
+	{"MUXSEL"                      ,	5,	2,	506,	"RO",	0,	1,	0ull,	0},
+	{"UNXTERM"                     ,	7,	1,	506,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TESTRES"                     ,	8,	1,	506,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	506,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRX4CMP"                     ,	0,	8,	507,	"R/W",	0,	1,	0ull,	0},
+	{"STX4PCMP"                    ,	8,	4,	507,	"R/W",	0,	1,	0ull,	0},
+	{"STX4NCMP"                    ,	12,	4,	507,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	507,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ERRCNT"                      ,	0,	4,	508,	"R/W",	0,	0,	0ull,	3ull},
+	{"RESERVED_4_5"                ,	4,	2,	508,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPPAY"                      ,	6,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPCLS"                      ,	7,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	8,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	508,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT"                         ,	0,	8,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"RSVOP"                       ,	8,	4,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"CALBNK"                      ,	12,	2,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_30"              ,	14,	17,	509,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUL"                         ,	31,	1,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	509,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	510,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	510,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	511,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_30"              ,	12,	19,	511,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPF"                         ,	31,	1,	511,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	511,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	512,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	512,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	513,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	513,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX"                         ,	0,	32,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	514,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTSEL"                      ,	0,	4,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUX_EN"                      ,	0,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"MACRO_EN"                    ,	1,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXDIST"                     ,	2,	5,	516,	"R/W",	0,	0,	0ull,	8ull},
+	{"SET_BOOT"                    ,	7,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR_BOOT"                    ,	8,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"JITTER"                      ,	9,	3,	516,	"R/W",	0,	0,	0ull,	1ull},
+	{"TRNTEST"                     ,	12,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	516,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BW_CTL"                      ,	0,	5,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	517,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SETTING"                     ,	0,	17,	518,	"RO",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	518,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	519,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRTS"                        ,	4,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	519,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNORE"                      ,	0,	16,	520,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	520,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	521,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	521,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	521,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	521,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	521,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	521,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_2"                ,	0,	3,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	3,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINTRN"                      ,	5,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	523,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	524,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	524,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	525,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	525,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPMAX"                      ,	0,	4,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMMAX"                      ,	4,	4,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	526,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	0,	16,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	527,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	528,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	8,	1,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	529,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MINB"                        ,	0,	9,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	531,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	532,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	532,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_T"                       ,	0,	16,	533,	"R/W",	0,	1,	0ull,	0},
+	{"ALPHA"                       ,	16,	16,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	533,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	534,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	534,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	534,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	534,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	535,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	536,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	536,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	0,	4,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	4,	1,	537,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	538,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	0,	22,	539,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	539,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	539,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	539,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	539,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	539,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	540,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	540,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	540,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	541,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	541,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	541,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	541,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	541,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	542,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	543,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	544,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	544,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	544,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	544,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	545,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	545,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	546,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	546,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	547,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	548,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	549,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	550,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	552,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	552,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	553,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	554,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	554,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	555,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	555,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	555,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	555,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	555,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	556,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	557,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	557,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	557,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	557,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	557,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	559,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	559,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	560,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	561,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	562,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	562,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	562,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	562,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	562,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	563,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	564,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	564,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	565,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	566,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	566,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	567,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	567,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	567,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	567,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	568,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP_CTL"                     ,	0,	4,	569,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	569,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	569,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	570,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	571,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	571,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	572,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	572,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	572,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	572,	"RO",	0,	0,	15360ull,	15360ull},
+	{"RESERVED_48_63"              ,	48,	16,	572,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	573,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	574,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	575,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_gmii_rx_clk_set"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	2,	0},
+	{"cvmx_asx#_gmii_rx_dat_set"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	2},
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	6,	4},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	6,	10},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	4,	16},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	2,	20},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	2,	22},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	2,	24},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	4,	26},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	2,	30},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	32},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	17,	2,	34},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	18,	2,	36},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	19,	2,	38},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	20,	2,	40},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	21,	19,	42},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	26,	2,	61},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	31,	19,	63},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	36,	2,	82},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	37,	2,	84},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	39,	2,	86},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	41,	2,	88},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	42,	2,	90},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	43,	2,	92},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	44,	1,	94},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	46,	3,	95},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	47,	2,	98},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	48,	4,	100},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	49,	2,	104},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	50,	3,	106},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	54,	7,	109},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	56,	6,	116},
+	{"cvmx_dfa_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	57,	3,	122},
+	{"cvmx_dfa_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	58,	7,	125},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	59,	2,	132},
+	{"cvmx_dfa_ddr2_addr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	60,	6,	134},
+	{"cvmx_dfa_ddr2_bus"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	61,	2,	140},
+	{"cvmx_dfa_ddr2_cfg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	16,	142},
+	{"cvmx_dfa_ddr2_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	63,	6,	158},
+	{"cvmx_dfa_ddr2_emrs"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	4,	164},
+	{"cvmx_dfa_ddr2_fcnt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	2,	168},
+	{"cvmx_dfa_ddr2_mrs"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	4,	170},
+	{"cvmx_dfa_ddr2_opt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	67,	3,	174},
+	{"cvmx_dfa_ddr2_pll"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	14,	177},
+	{"cvmx_dfa_ddr2_tmg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	69,	21,	191},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	70,	4,	212},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	71,	3,	216},
+	{"cvmx_dfa_eclkcfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	14,	219},
+	{"cvmx_dfa_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	73,	21,	233},
+	{"cvmx_dfa_memfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	6,	254},
+	{"cvmx_dfa_sbd_dbg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	1,	260},
+	{"cvmx_dfa_sbd_dbg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	76,	1,	261},
+	{"cvmx_dfa_sbd_dbg2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	1,	262},
+	{"cvmx_dfa_sbd_dbg3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	78,	1,	263},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	6,	264},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	80,	7,	270},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	81,	29,	277},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	82,	29,	306},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	335},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	337},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	3,	339},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	100,	3,	342},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	345},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	102,	2,	347},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	8,	349},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	104,	2,	357},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	3,	359},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	106,	2,	362},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	5,	364},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	110,	1,	369},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	1,	370},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	116,	1,	371},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	1,	372},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	1,	373},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	125,	1,	374},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	128,	2,	375},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	131,	4,	377},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	134,	2,	381},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	137,	11,	383},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	140,	9,	394},
+	{"cvmx_gmx#_rx#_frm_max"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	143,	2,	403},
+	{"cvmx_gmx#_rx#_frm_min"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	146,	2,	405},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	149,	2,	407},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	152,	20,	409},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	155,	20,	429},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	158,	2,	449},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	161,	4,	451},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	164,	2,	455},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	167,	2,	457},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	170,	2,	459},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	173,	2,	461},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	176,	2,	463},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	179,	2,	465},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	182,	2,	467},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	185,	2,	469},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	188,	2,	471},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	191,	2,	473},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	194,	4,	475},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	197,	2,	479},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	200,	2,	481},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	203,	2,	483},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	206,	4,	485},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	207,	2,	489},
+	{"cvmx_gmx#_rx_tx_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	208,	4,	491},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	209,	2,	495},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	212,	3,	497},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	213,	5,	500},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	216,	2,	505},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	219,	2,	507},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	222,	3,	509},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	225,	2,	512},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	228,	2,	514},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	231,	2,	516},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	234,	2,	518},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	237,	2,	520},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	240,	2,	522},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	243,	2,	524},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	246,	2,	526},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	249,	2,	528},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	2,	530},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	255,	2,	532},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	258,	2,	534},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	261,	2,	536},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	264,	2,	538},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	267,	2,	540},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	270,	2,	542},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	273,	2,	544},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	276,	2,	546},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	279,	2,	548},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	282,	2,	550},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	283,	2,	552},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	284,	2,	554},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	285,	3,	556},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	286,	8,	559},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	287,	8,	567},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	288,	2,	575},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	289,	2,	577},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	290,	6,	579},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	291,	2,	585},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	292,	2,	587},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	293,	2,	589},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	294,	7,	591},
+	{"cvmx_gpio_boot_ena"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	310,	3,	598},
+	{"cvmx_gpio_dbg_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	311,	2,	601},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	312,	2,	603},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	313,	2,	605},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	314,	2,	607},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	315,	2,	609},
+	{"cvmx_gpio_xbit_cfg#"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	316,	6,	611},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	324,	19,	617},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	325,	6,	636},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	326,	3,	642},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	327,	5,	645},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	328,	5,	650},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	329,	1,	655},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	330,	1,	656},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	331,	5,	657},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	332,	5,	662},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	333,	5,	667},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	334,	5,	672},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	335,	1,	677},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	336,	1,	678},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	337,	2,	679},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	338,	2,	681},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	339,	2,	683},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	340,	2,	685},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	341,	17,	687},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	342,	2,	704},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	343,	1,	706},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	344,	10,	707},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	345,	6,	717},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	346,	6,	723},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	347,	2,	729},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	348,	2,	731},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	349,	2,	733},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	350,	3,	735},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	355,	2,	738},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	360,	6,	740},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	361,	5,	746},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	362,	6,	751},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	363,	7,	757},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	364,	2,	764},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	372,	2,	766},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	373,	3,	768},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	374,	5,	771},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	382,	3,	776},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	383,	2,	779},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	384,	2,	781},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	385,	2,	783},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	386,	7,	785},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	387,	6,	792},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	388,	8,	798},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	389,	9,	806},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	390,	10,	815},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	391,	5,	825},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	392,	4,	830},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	393,	2,	834},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	394,	17,	836},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	395,	19,	853},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	396,	3,	872},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	397,	4,	875},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	398,	2,	879},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	402,	17,	881},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	403,	4,	898},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	404,	2,	902},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	405,	3,	904},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	406,	2,	907},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	407,	2,	909},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	2,	911},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	409,	7,	913},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	410,	6,	920},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	411,	3,	926},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	412,	3,	929},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	413,	2,	932},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	414,	2,	934},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	415,	2,	936},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	3,	938},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	417,	15,	941},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	418,	9,	956},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	419,	20,	965},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	420,	2,	985},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	421,	2,	987},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	422,	18,	989},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	423,	5,	1007},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	424,	6,	1012},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	425,	2,	1018},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	426,	2,	1020},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	427,	14,	1022},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	428,	10,	1036},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	429,	2,	1046},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	430,	2,	1048},
+	{"cvmx_lmc#_pll_bwctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	431,	3,	1050},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	432,	9,	1053},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	433,	5,	1062},
+	{"cvmx_lmc#_wodt_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	434,	5,	1067},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	435,	5,	1072},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	436,	3,	1077},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	437,	3,	1080},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	438,	3,	1083},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	439,	5,	1086},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	441,	1,	1091},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	442,	10,	1092},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	450,	13,	1102},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	458,	4,	1115},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	459,	2,	1119},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	460,	2,	1121},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	461,	10,	1123},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	462,	9,	1133},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	463,	2,	1142},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	8,	1144},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	465,	4,	1152},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	466,	2,	1156},
+	{"cvmx_mio_fus_unlock"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	467,	2,	1158},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	468,	2,	1160},
+	{"cvmx_mio_pll_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	469,	2,	1162},
+	{"cvmx_mio_pll_setting"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	470,	2,	1164},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	13,	1166},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	12,	1179},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	473,	3,	1191},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	474,	3,	1194},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	475,	2,	1197},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	477,	2,	1199},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	479,	2,	1201},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	481,	7,	1203},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	483,	2,	1210},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	485,	7,	1212},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	487,	4,	1219},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	489,	8,	1223},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	491,	9,	1231},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	493,	7,	1240},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	495,	9,	1247},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	497,	2,	1256},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	499,	2,	1258},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	501,	4,	1260},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	503,	2,	1264},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	505,	2,	1266},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	507,	2,	1268},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	509,	4,	1270},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	511,	2,	1274},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	513,	2,	1276},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	515,	2,	1278},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	517,	2,	1280},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	519,	2,	1282},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	521,	2,	1284},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	523,	6,	1286},
+	{"cvmx_mpi_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	525,	13,	1292},
+	{"cvmx_mpi_dat#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	526,	2,	1305},
+	{"cvmx_mpi_sts"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	535,	4,	1307},
+	{"cvmx_mpi_tx"                 ,	CVMX_CSR_DB_TYPE_NCB,	64,	536,	6,	1311},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	537,	2,	1317},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	539,	2,	1319},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	541,	21,	1321},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	542,	3,	1342},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	544,	18,	1345},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	545,	2,	1363},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	546,	13,	1365},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	547,	3,	1378},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	548,	3,	1381},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	549,	3,	1384},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	550,	3,	1387},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	551,	2,	1390},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	552,	2,	1392},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	553,	9,	1394},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	554,	54,	1403},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	555,	54,	1457},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	556,	2,	1511},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	557,	2,	1513},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	558,	8,	1515},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	562,	1,	1523},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	563,	2,	1524},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	565,	23,	1526},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	566,	3,	1549},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	568,	2,	1552},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	570,	3,	1554},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	572,	3,	1557},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	574,	3,	1560},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	575,	4,	1563},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	576,	2,	1567},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	577,	13,	1569},
+	{"cvmx_npi_port33_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	578,	13,	1582},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	579,	3,	1595},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	580,	33,	1598},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	581,	2,	1631},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	583,	2,	1633},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	584,	5,	1635},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	616,	2,	1640},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	617,	24,	1642},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	618,	2,	1666},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	619,	7,	1668},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	620,	5,	1675},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	621,	1,	1680},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	622,	5,	1681},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	623,	1,	1686},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	624,	4,	1687},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	625,	2,	1691},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	626,	1,	1693},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	627,	2,	1694},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	628,	4,	1696},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	629,	2,	1700},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	630,	4,	1702},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	631,	16,	1706},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	632,	1,	1722},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	633,	1,	1723},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	634,	18,	1724},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	635,	1,	1742},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	636,	1,	1743},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	637,	7,	1744},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	638,	7,	1751},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	639,	13,	1758},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	640,	10,	1771},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	641,	10,	1781},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	642,	7,	1791},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	643,	2,	1798},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	644,	1,	1800},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	645,	2,	1801},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	646,	16,	1803},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	647,	2,	1819},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	649,	1,	1821},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	651,	1,	1822},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	653,	1,	1823},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	655,	1,	1824},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	657,	33,	1825},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	658,	33,	1858},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	659,	33,	1891},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	660,	33,	1924},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	661,	2,	1957},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	662,	2,	1959},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	664,	1,	1961},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	666,	1,	1962},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	668,	1,	1963},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	670,	3,	1964},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	671,	3,	1967},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	672,	3,	1970},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	673,	3,	1973},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	674,	2,	1976},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	675,	2,	1978},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	676,	4,	1980},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	677,	1,	1984},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	678,	4,	1985},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	679,	1,	1989},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	680,	2,	1990},
+	{"cvmx_pcm#_dma_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	681,	12,	1992},
+	{"cvmx_pcm#_int_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	685,	9,	2004},
+	{"cvmx_pcm#_int_sum"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	689,	9,	2013},
+	{"cvmx_pcm#_rxaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	693,	2,	2022},
+	{"cvmx_pcm#_rxcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	697,	2,	2024},
+	{"cvmx_pcm#_rxmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	701,	1,	2026},
+	{"cvmx_pcm#_rxmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	705,	1,	2027},
+	{"cvmx_pcm#_rxmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	709,	1,	2028},
+	{"cvmx_pcm#_rxmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	713,	1,	2029},
+	{"cvmx_pcm#_rxmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	717,	1,	2030},
+	{"cvmx_pcm#_rxmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	721,	1,	2031},
+	{"cvmx_pcm#_rxmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	725,	1,	2032},
+	{"cvmx_pcm#_rxmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	729,	1,	2033},
+	{"cvmx_pcm#_rxstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	733,	3,	2034},
+	{"cvmx_pcm#_tdm_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	737,	6,	2037},
+	{"cvmx_pcm#_tdm_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	741,	1,	2043},
+	{"cvmx_pcm#_txaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	745,	3,	2044},
+	{"cvmx_pcm#_txcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	749,	2,	2047},
+	{"cvmx_pcm#_txmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	753,	1,	2049},
+	{"cvmx_pcm#_txmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	757,	1,	2050},
+	{"cvmx_pcm#_txmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	761,	1,	2051},
+	{"cvmx_pcm#_txmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	765,	1,	2052},
+	{"cvmx_pcm#_txmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	769,	1,	2053},
+	{"cvmx_pcm#_txmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	773,	1,	2054},
+	{"cvmx_pcm#_txmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	777,	1,	2055},
+	{"cvmx_pcm#_txmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	781,	1,	2056},
+	{"cvmx_pcm#_txstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	785,	3,	2057},
+	{"cvmx_pcm_clk#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	789,	12,	2060},
+	{"cvmx_pcm_clk#_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	791,	1,	2072},
+	{"cvmx_pcm_clk#_gen"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	793,	3,	2073},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	795,	2,	2076},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	796,	4,	2078},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	800,	8,	2082},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	801,	16,	2090},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	10,	2106},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	10,	2116},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	2,	2126},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	805,	16,	2128},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	25,	2144},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	815,	2,	2169},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	879,	2,	2171},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	887,	9,	2173},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	891,	2,	2182},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	892,	2,	2184},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	893,	2,	2186},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	898,	2,	2188},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	903,	2,	2190},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	908,	2,	2192},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	913,	2,	2194},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	918,	2,	2196},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	923,	2,	2198},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	928,	2,	2200},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	933,	2,	2202},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	938,	2,	2204},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	943,	2,	2206},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	944,	2,	2208},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	949,	2,	2210},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	954,	2,	2212},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	959,	2,	2214},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1023,	2,	2216},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1024,	3,	2218},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1025,	3,	2221},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1026,	2,	2224},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	2,	2226},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1028,	4,	2228},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1029,	5,	2232},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1030,	4,	2237},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1031,	5,	2241},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1032,	1,	2246},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1033,	4,	2247},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1034,	2,	2251},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1035,	5,	2253},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1036,	5,	2258},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1037,	1,	2263},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1038,	19,	2264},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1039,	7,	2283},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1040,	4,	2290},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1041,	6,	2294},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1042,	6,	2300},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1043,	9,	2306},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1044,	5,	2315},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1045,	13,	2320},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1046,	4,	2333},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1047,	2,	2337},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1048,	3,	2339},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1049,	5,	2342},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1050,	3,	2347},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1051,	3,	2350},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1052,	2,	2353},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1053,	3,	2355},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1054,	12,	2358},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1055,	2,	2370},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1056,	9,	2372},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1057,	3,	2381},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1058,	2,	2384},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1066,	2,	2386},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1067,	2,	2388},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1068,	2,	2390},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1069,	2,	2392},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1071,	5,	2394},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1079,	10,	2399},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1087,	2,	2409},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1088,	2,	2411},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1089,	2,	2413},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1097,	3,	2415},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1098,	6,	2418},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1114,	5,	2424},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1115,	7,	2429},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1131,	2,	2436},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1147,	3,	2438},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1148,	5,	2441},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1149,	8,	2446},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1150,	6,	2454},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1151,	2,	2460},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1152,	4,	2462},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1153,	4,	2466},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1154,	6,	2470},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1155,	3,	2476},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1156,	5,	2479},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1157,	4,	2484},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1158,	6,	2488},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1159,	4,	2494},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1160,	2,	2498},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1161,	4,	2500},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1162,	2,	2504},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1163,	3,	2506},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1164,	4,	2509},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1165,	12,	2513},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1166,	3,	2525},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	2,	2528},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	2,	2530},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	17,	2532},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	12,	2549},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	6,	2561},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	5,	2567},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1173,	1,	2572},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1174,	2,	2573},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	2,	2575},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1176,	17,	2577},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1177,	12,	2594},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1178,	6,	2606},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1179,	2,	2612},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1180,	2,	2614},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1181,	17,	2616},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1182,	12,	2633},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	6,	2645},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1184,	2,	2651},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1185,	2,	2653},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1186,	8,	2655},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1187,	11,	2663},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1188,	15,	2674},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1193,	8,	2689},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1198,	8,	2697},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1199,	4,	2705},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1204,	15,	2709},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1209,	6,	2724},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1214,	6,	2730},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1215,	4,	2736},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1220,	2,	2740},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1224,	6,	2742},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1225,	4,	2748},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1226,	1,	2752},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1227,	1,	2753},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1228,	1,	2754},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1229,	7,	2755},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1230,	1,	2762},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1231,	14,	2763},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1232,	10,	2777},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1233,	12,	2787},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1234,	32,	2799},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1235,	32,	2831},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1236,	2,	2863},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1237,	4,	2865},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1238,	13,	2869},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1239,	10,	2882},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1240,	10,	2892},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1241,	2,	2902},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1242,	6,	2904},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1243,	5,	2910},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1244,	6,	2915},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1245,	5,	2921},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1246,	1,	2926},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1247,	13,	2927},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1248,	2,	2940},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1249,	2,	2942},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1250,	11,	2944},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1258,	3,	2955},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	1259,	12,	2958},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1267,	12,	2970},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1275,	6,	2982},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1283,	4,	2988},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1291,	2,	2992},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1292,	2,	2994},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1293,	15,	2996},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1294,	2,	3011},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1295,	3,	3013},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	1296,	1,	3016},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1304,	6,	3017},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1305,	4,	3023},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1306,	15,	3027},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1307,	6,	3042},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1308,	2,	3048},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1309,	2,	3050},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1310,	2,	3052},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1311,	2,	3054},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1312,	2,	3056},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1313,	2,	3058},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1314,	2,	3060},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1315,	2,	3062},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1316,	2,	3064},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1317,	2,	3066},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1318,	2,	3068},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1319,	2,	3070},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1320,	2,	3072},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1321,	2,	3074},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1322,	2,	3076},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1323,	2,	3078},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1324,	7,	3080},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	39,	3087},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1326,	39,	3126},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1327,	22,	3165},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1328,	3,	3187},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1329,	5,	3190},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1330,	3,	3195},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1331,	6,	3198},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1332,	2,	3204},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1333,	2,	3206},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1334,	2,	3208},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800B0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800B0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	11},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"DFA_DDR2_ADDR"               ,	   0x1180030000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"DFA_DDR2_BUS"                ,	   0x1180030000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"DFA_DDR2_CFG"                ,	   0x1180030000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"DFA_DDR2_COMP"               ,	   0x1180030000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"DFA_DDR2_EMRS"               ,	   0x1180030000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"DFA_DDR2_FCNT"               ,	   0x1180030000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"DFA_DDR2_MRS"                ,	   0x1180030000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"DFA_DDR2_OPT"                ,	   0x1180030000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"DFA_DDR2_PLL"                ,	   0x1180030000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"DFA_DDR2_TMG"                ,	   0x1180030000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	46},
+	{"DFA_ECLKCFG"                 ,	   0x1180030000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"DFA_ERR"                     ,	   0x1180030000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"DFA_MEMFADR"                 ,	   0x1180030000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"DFA_SBD_DBG0"                ,	   0x1180030000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX000_FRM_MAX"          ,	   0x1180008000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX001_FRM_MAX"          ,	   0x1180008000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX002_FRM_MAX"          ,	   0x1180008001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX000_FRM_MIN"          ,	   0x1180008000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX001_FRM_MIN"          ,	   0x1180008000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX002_FRM_MIN"          ,	   0x1180008001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	141},
+	{"GPIO_BOOT_ENA"               ,	   0x10700000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	142},
+	{"GPIO_DBG_ENA"                ,	   0x10700000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"GPIO_XBIT_CFG16"             ,	   0x1070000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG17"             ,	   0x1070000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG18"             ,	   0x1070000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG19"             ,	   0x1070000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG20"             ,	   0x1070000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG21"             ,	   0x1070000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG22"             ,	   0x1070000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"GPIO_XBIT_CFG23"             ,	   0x1070000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	174},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	175},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	176},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	177},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	178},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	179},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	180},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	181},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	182},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	183},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	184},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	185},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	186},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"LMC0_PLL_BWCTL"              ,	   0x1180088000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_FUS_UNLOCK"              ,	   0x1180000001578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_PLL_CTL"                 ,	   0x1180000001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_PLL_SETTING"             ,	   0x1180000001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT4"                    ,	   0x10700000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT5"                    ,	   0x10700000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT6"                    ,	   0x10700000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT7"                    ,	   0x10700000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_DAT8"                    ,	   0x10700000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	308},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	310},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	316},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	317},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	318},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	319},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	320},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	321},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	322},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	323},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	324},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	336},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	337},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	338},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	339},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	340},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	341},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	342},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	343},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	344},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	345},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	346},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	347},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	348},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	349},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	350},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	351},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	352},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	353},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	354},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	355},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	356},
+	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	356},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	357},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	357},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	358},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	358},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
+	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	361},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	362},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	363},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	364},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	365},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	366},
+	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	366},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	367},
+	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	367},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	368},
+	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	368},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	369},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	369},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	370},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	371},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	372},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	374},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	375},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	376},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	377},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	378},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	379},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	380},
+	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM3_DMA_CFG"                ,	   0x107000001C018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM3_INT_ENA"                ,	   0x107000001C020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM3_INT_SUM"                ,	   0x107000001C028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM3_RXADDR"                 ,	   0x107000001C068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM3_RXCNT"                  ,	   0x107000001C060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM3_RXMSK0"                 ,	   0x107000001C0C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_RXMSK1"                 ,	   0x107000001C0C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM3_RXMSK2"                 ,	   0x107000001C0D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM3_RXMSK3"                 ,	   0x107000001C0D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM3_RXMSK4"                 ,	   0x107000001C0E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM3_RXMSK5"                 ,	   0x107000001C0E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM3_RXMSK6"                 ,	   0x107000001C0F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM3_RXMSK7"                 ,	   0x107000001C0F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM3_RXSTART"                ,	   0x107000001C058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM3_TDM_CFG"                ,	   0x107000001C010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM3_TDM_DBG"                ,	   0x107000001C030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM3_TXADDR"                 ,	   0x107000001C050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM3_TXCNT"                  ,	   0x107000001C048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM3_TXMSK0"                 ,	   0x107000001C080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM3_TXMSK1"                 ,	   0x107000001C088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM3_TXMSK2"                 ,	   0x107000001C090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM3_TXMSK3"                 ,	   0x107000001C098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM3_TXMSK4"                 ,	   0x107000001C0A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM3_TXMSK5"                 ,	   0x107000001C0A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM3_TXMSK6"                 ,	   0x107000001C0B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM3_TXMSK7"                 ,	   0x107000001C0B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"PCM3_TXSTART"                ,	   0x107000001C040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
+	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
+	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
+	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
+	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	471},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	472},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	474},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	476},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	477},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	482},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	540},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	541},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	542},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	543},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	544},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	546},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	551},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	552},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	553},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	554},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	555},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	557},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	558},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	559},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	560},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	561},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	562},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	563},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	564},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	565},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	566},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	567},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	568},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	569},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	570},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	571},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	572},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	573},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	574},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	575},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	576},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	577},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	578},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	581},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	582},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	583},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	584},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	585},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	586},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	587},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	588},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	589},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	590},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	591},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	592},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	593},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	594},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	595},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	596},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	597},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	598},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"SETTING"                     ,	0,	5,	0,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	0,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	1,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_3"                ,	3,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"TXPOP"                       ,	4,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"TXPSH"                       ,	8,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_11_63"              ,	11,	53,	2,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"TXPOP"                       ,	4,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"TXPSH"                       ,	8,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	3,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	3,	4,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	4,	"RAZ",	1,	1,	0,	0},
+	{"EXT_LOOP"                    ,	4,	3,	4,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	4,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	5,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	5,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	3,	6,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	6,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	7,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	7,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	8,	"R/W",	0,	0,	8ull,	8ull},
+	{"PCTL"                        ,	4,	4,	8,	"R/W",	0,	0,	8ull,	8ull},
+	{"BYPASS"                      ,	8,	1,	8,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	8,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	3,	9,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	9,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	3,	10,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	10,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	11,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	11,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	2,	12,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	12,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	2,	13,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	13,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	14,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	14,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	15,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	2,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	16,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	17,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	17,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	17,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	17,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	17,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	17,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	17,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	17,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	2,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	18,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	19,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	19,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	20,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	20,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	2,	21,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	21,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	22,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	22,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	2,	23,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	23,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	24,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	25,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	1,	25,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	25,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	26,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	27,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	27,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	27,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	27,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	28,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	28,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	29,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	30,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	31,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	31,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	31,	"RO",	1,	1,	0,	0},
+	{"RESERVED_23_27"              ,	23,	5,	31,	"RAZ",	1,	1,	0,	0},
+	{"PLL_MUL"                     ,	28,	3,	31,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	31,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	16,	32,	"RO",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	16,	16,	32,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	32,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_17"               ,	0,	18,	33,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CRF"                         ,	18,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"DRF"                         ,	19,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	20,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"IFU"                         ,	21,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	22,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	33,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DBELL"                       ,	0,	20,	34,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	34,	"RAZ",	1,	1,	0,	0},
+	{"NUM_COLS"                    ,	0,	2,	35,	"R/W",	0,	0,	1ull,	1ull},
+	{"NUM_COLROWS"                 ,	2,	3,	35,	"R/W",	0,	0,	1ull,	1ull},
+	{"RNK_LO"                      ,	5,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_RNKS"                    ,	6,	2,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	8,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	35,	"RAZ",	1,	1,	0,	0},
+	{"BUS_CNT"                     ,	0,	47,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	36,	"RAZ",	1,	1,	0,	0},
+	{"PRTENA"                      ,	0,	1,	37,	"R/W",	0,	0,	0ull,	1ull},
+	{"INIT"                        ,	1,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPRCH"                       ,	2,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	3,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_LAT"                     ,	4,	2,	37,	"R/W",	0,	0,	1ull,	1ull},
+	{"SILO_HC"                     ,	6,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_QC"                     ,	7,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNK_MSK"                     ,	8,	4,	37,	"R/W",	0,	0,	0ull,	15ull},
+	{"TSKW"                        ,	12,	2,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	37,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REF_INT"                     ,	16,	13,	37,	"R/W",	0,	0,	780ull,	780ull},
+	{"RESERVED_29_31"              ,	29,	3,	37,	"RAZ",	1,	1,	0,	0},
+	{"FPIP"                        ,	32,	3,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRS_PGM"                     ,	35,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRFC"                        ,	36,	5,	37,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_41_63"              ,	41,	23,	37,	"RAZ",	1,	1,	0,	0},
+	{"COMP_BYPASS"                 ,	0,	1,	38,	"R/W",	0,	0,	0ull,	1ull},
+	{"NCTL_CSR"                    ,	1,	4,	38,	"R/W",	0,	1,	13ull,	0},
+	{"PCTL_CSR"                    ,	5,	4,	38,	"R/W",	0,	1,	13ull,	0},
+	{"RESERVED_9_55"               ,	9,	47,	38,	"RAZ",	1,	1,	0,	0},
+	{"DFA__NCTL"                   ,	56,	4,	38,	"RO",	1,	1,	0,	0},
+	{"DFA__PCTL"                   ,	60,	4,	38,	"RO",	1,	1,	0,	0},
+	{"EMRS1"                       ,	0,	15,	39,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	39,	"RAZ",	1,	1,	0,	0},
+	{"EMRS1_OCD"                   ,	16,	15,	39,	"R/W",	0,	0,	896ull,	896ull},
+	{"RESERVED_31_63"              ,	31,	33,	39,	"RAZ",	1,	1,	0,	0},
+	{"FCYC_CNT"                    ,	0,	47,	40,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	40,	"RAZ",	1,	1,	0,	0},
+	{"MRS_DLL"                     ,	0,	15,	41,	"R/W",	0,	0,	1858ull,	1858ull},
+	{"RESERVED_15_15"              ,	15,	1,	41,	"RAZ",	1,	1,	0,	0},
+	{"MRS"                         ,	16,	15,	41,	"R/W",	0,	0,	1602ull,	1602ull},
+	{"RESERVED_31_63"              ,	31,	33,	41,	"RAZ",	1,	1,	0,	0},
+	{"MAX_WRITE_BATCH"             ,	0,	5,	42,	"R/W",	0,	0,	31ull,	31ull},
+	{"MAX_READ_BATCH"              ,	5,	5,	42,	"R/W",	0,	0,	31ull,	31ull},
+	{"RESERVED_10_63"              ,	10,	54,	42,	"RAZ",	1,	1,	0,	0},
+	{"PLL_INIT"                    ,	0,	1,	43,	"R/W",	0,	0,	0ull,	1ull},
+	{"PLL_BYPASS"                  ,	1,	1,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLL_RATIO"                   ,	2,	5,	43,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	43,	"RAZ",	1,	1,	0,	0},
+	{"PLL_DIV2"                    ,	8,	1,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"BW_UPD"                      ,	9,	1,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"BW_CTL"                      ,	10,	4,	43,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	14,	1,	43,	"R/W",	0,	0,	0ull,	1ull},
+	{"DLL_BYP"                     ,	15,	1,	43,	"R/W",	0,	1,	0ull,	0},
+	{"DLL_SETTING"                 ,	16,	5,	43,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_26"              ,	21,	6,	43,	"RAZ",	1,	1,	0,	0},
+	{"SETTING90"                   ,	27,	5,	43,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_46"              ,	32,	15,	43,	"RAZ",	1,	1,	0,	0},
+	{"PLL_SETTING"                 ,	47,	17,	43,	"RO",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	0,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMRD"                        ,	1,	2,	44,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	3,	3,	44,	"R/W",	0,	0,	4ull,	4ull},
+	{"POCAS"                       ,	6,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	7,	3,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRCD"                        ,	10,	4,	44,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRRD"                        ,	14,	3,	44,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRAS"                        ,	17,	5,	44,	"R/W",	0,	0,	10ull,	10ull},
+	{"TRP"                         ,	22,	4,	44,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWR"                         ,	26,	3,	44,	"R/W",	0,	0,	3ull,	3ull},
+	{"TWTR"                        ,	29,	4,	44,	"R/W",	0,	0,	2ull,	2ull},
+	{"TFAW"                        ,	33,	5,	44,	"R/W",	0,	0,	9ull,	9ull},
+	{"R2R_SLOT"                    ,	38,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	39,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"DQSN_ENA"                    ,	40,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_RTT"                     ,	41,	2,	44,	"R/W",	0,	0,	2ull,	2ull},
+	{"CTR_RST"                     ,	43,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAVMIPO"                     ,	44,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_CLR"                     ,	45,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCNT_MODE"                   ,	46,	1,	44,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	44,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	9,	45,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	45,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	45,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	45,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	46,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	31,	46,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	46,	"RAZ",	1,	1,	0,	0},
+	{"DFA_FRSTN"                   ,	0,	1,	47,	"R/W",	0,	0,	0ull,	1ull},
+	{"MAXBNK"                      ,	1,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"DTECLKDIS"                   ,	2,	1,	47,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	47,	"RAZ",	0,	0,	0ull,	9ull},
+	{"SARB"                        ,	8,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"IMODE"                       ,	9,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	10,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	11,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"DTMODE"                      ,	12,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"DCMODE"                      ,	13,	1,	47,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDLCK"                      ,	14,	1,	47,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	47,	"RAZ",	1,	1,	0,	0},
+	{"SBDNUM"                      ,	16,	3,	47,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	47,	"RAZ",	1,	1,	0,	0},
+	{"CP2ECCENA"                   ,	0,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SBE"                      ,	1,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2DBE"                      ,	2,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2SBINA"                    ,	3,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2DBINA"                    ,	4,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SYN"                      ,	5,	8,	48,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEECCENA"                   ,	13,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESBE"                      ,	14,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEDBE"                      ,	15,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTESBINA"                    ,	16,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEDBINA"                    ,	17,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESYN"                      ,	18,	7,	48,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEPARENA"                   ,	25,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEPERR"                     ,	26,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEPINA"                     ,	27,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PARENA"                   ,	28,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PERR"                     ,	29,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2PINA"                     ,	30,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBLOVF"                      ,	31,	1,	48,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBLINA"                      ,	32,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	48,	"RAZ",	1,	1,	0,	0},
+	{"MADDR"                       ,	0,	25,	49,	"RO",	0,	0,	0ull,	0ull},
+	{"BNUM"                        ,	25,	3,	49,	"RO",	0,	0,	0ull,	0ull},
+	{"PNUM"                        ,	28,	1,	49,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	29,	2,	49,	"RO",	0,	0,	0ull,	0ull},
+	{"FDST"                        ,	31,	9,	49,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	49,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	50,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	51,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	52,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	53,	"RO",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	54,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	55,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	56,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	56,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	57,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	57,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	58,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	58,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	59,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	59,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	60,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	60,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	60,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	61,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	61,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	61,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	62,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	62,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	63,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	3,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_21"               ,	5,	17,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	3,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_25"              ,	25,	1,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	64,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	65,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	65,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	66,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	66,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	66,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	67,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	67,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	68,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	68,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	68,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	68,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	68,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	69,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	70,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	71,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	72,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	73,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	74,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	75,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	75,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	76,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	76,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	76,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	76,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	77,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	77,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	78,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	78,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	79,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	79,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	79,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	79,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	79,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	79,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_FREE"                    ,	6,	1,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLAN_LEN"                    ,	7,	1,	79,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	79,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	80,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	80,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	81,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	81,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	82,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	82,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	83,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	83,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	84,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	85,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	85,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	86,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	86,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	86,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	86,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	87,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	87,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	88,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	88,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	89,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	89,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	90,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	90,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	91,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	91,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	92,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	92,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	93,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	93,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	94,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	94,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	95,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	95,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	96,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	96,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	97,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	97,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	98,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	98,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	99,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	99,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	100,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	100,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	3,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_15"               ,	3,	13,	101,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	3,	101,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	101,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	102,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_3_63"               ,	3,	61,	102,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	3,	103,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	103,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	3,	103,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	103,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	104,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	104,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	105,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	106,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	106,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	106,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	106,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	106,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	107,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	107,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	108,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	108,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	109,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	109,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	109,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	110,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	110,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	111,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	111,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	112,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	112,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	113,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	113,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	114,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	114,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	115,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	115,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	116,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	116,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	117,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	117,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	118,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	118,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	119,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	119,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	120,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	120,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	121,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	121,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	122,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	122,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	123,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	123,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	124,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	124,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	125,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	125,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	126,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	126,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	127,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	7,	128,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_7_63"               ,	7,	57,	128,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	3,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	129,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	130,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	130,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	3,	131,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_3_63"               ,	3,	61,	131,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	132,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	132,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	132,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	3,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	3,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	3,	133,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	133,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKO_NXA"                     ,	0,	1,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	3,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	3,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	3,	134,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	134,	"RAZ",	0,	0,	0ull,	0ull},
+	{"JAM"                         ,	0,	8,	135,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	135,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	136,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	136,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	3,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	137,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	3,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	137,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	3,	137,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	137,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DMAC"                        ,	0,	48,	138,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	138,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	139,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	139,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	140,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	140,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	141,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	142,	"RAZ",	1,	1,	0,	0},
+	{"BOOT_ENA"                    ,	8,	4,	142,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	142,	"RAZ",	1,	1,	0,	0},
+	{"DBG_ENA"                     ,	0,	21,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	143,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	144,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	144,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	24,	145,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	145,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	24,	146,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	146,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	24,	147,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	147,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	148,	"RAZ",	1,	1,	0,	0},
+	{"FIL_CNT"                     ,	4,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	148,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	149,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	150,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	150,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	150,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	150,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	151,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	151,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	151,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	152,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	152,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	152,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	152,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	152,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	153,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	153,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	153,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	153,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	153,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	154,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	155,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	156,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	157,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	158,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	158,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	158,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	158,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	158,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	159,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	159,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	159,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	159,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	159,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	160,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	161,	"R/W",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	6,	162,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	162,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	163,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	164,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	165,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	166,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	167,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	168,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	169,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	169,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	170,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	171,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	171,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	172,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	173,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	173,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	174,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	174,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	175,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	176,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	176,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	177,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	177,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	177,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	177,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	177,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	178,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	178,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	178,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_44_63"              ,	44,	20,	178,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	179,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	180,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	180,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	180,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	180,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	180,	"RO",	0,	0,	8ull,	8ull},
+	{"RESERVED_61_63"              ,	61,	3,	180,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	181,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	181,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	182,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	182,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	183,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	184,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	184,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	184,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	184,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	185,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	185,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	185,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	3,	186,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_63"               ,	3,	61,	186,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	187,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	187,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	188,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	188,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	10,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	189,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	189,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	5,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_8"                ,	5,	4,	190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	191,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	191,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	191,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	192,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	192,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	192,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	192,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	192,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	192,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	2,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_9"                ,	7,	3,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	3,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	194,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	194,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	195,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	195,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	3,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	2,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	3,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	198,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	10,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	10,	17,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	3,	200,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_3"                ,	3,	1,	200,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STPARTDIS"                   ,	4,	1,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	200,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	201,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	202,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	4,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	203,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	4,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	203,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	4,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	204,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	205,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	206,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	207,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	208,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	209,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	209,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	209,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	209,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	10,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	210,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	2,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_13"              ,	13,	1,	210,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	210,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	211,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	212,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	213,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	214,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	215,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	216,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_128K"                   ,	34,	1,	216,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	216,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	9,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	2,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	217,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCTL_DAT"                    ,	0,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CMD"                    ,	4,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CLK"                    ,	8,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	218,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CMD"                    ,	20,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CLK"                    ,	24,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	218,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	218,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	219,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	219,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	219,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	219,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	219,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	11,	1,	219,	"R/W",	0,	0,	1ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	219,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	219,	"R/W",	0,	1,	0ull,	0},
+	{"PLL_BYPASS"                  ,	16,	1,	219,	"R/W",	0,	0,	1ull,	1ull},
+	{"PLL_DIV2"                    ,	17,	1,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	219,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	219,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	219,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	219,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	219,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	220,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	221,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	221,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	222,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	222,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	222,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	222,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	222,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	222,	"R/W",	0,	0,	2ull,	2ull},
+	{"SILO_HC"                     ,	21,	1,	222,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	222,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	222,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	222,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	222,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRDSYN0"                     ,	0,	8,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	223,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	224,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	225,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	226,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	227,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	227,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	227,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	227,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	227,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	227,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	227,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	227,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	227,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	227,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	227,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	228,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	228,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	228,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	228,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	228,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	228,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	228,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	228,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMP_BYPASS"                 ,	31,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	228,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	229,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	230,	"RAZ",	1,	1,	0,	0},
+	{"BWCTL"                       ,	0,	4,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWUPD"                       ,	4,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	231,	"RAZ",	1,	1,	0,	0},
+	{"RODT_LO0"                    ,	0,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	232,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	232,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	233,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	233,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	233,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	233,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	233,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WODT_D2_R0"                  ,	0,	8,	234,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	8,	8,	234,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	16,	8,	234,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	24,	8,	234,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NCBI"                        ,	0,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_1"                      ,	3,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	235,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	236,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	236,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	236,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	237,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	237,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	237,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	238,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	238,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	238,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	239,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	239,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	239,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	239,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	239,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	240,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	241,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	241,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	241,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	241,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	241,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	241,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	241,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	241,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	241,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_63"              ,	37,	27,	241,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	242,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	242,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	242,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	242,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	243,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	243,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	243,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	243,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	244,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	244,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	245,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	245,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	2,	246,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_11"               ,	2,	10,	246,	"RAZ",	1,	1,	0,	0},
+	{"PLL_OFF"                     ,	12,	4,	246,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	246,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	246,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	246,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	246,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	246,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	246,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	246,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	247,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	247,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	247,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	247,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	247,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	247,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	247,	"RO",	1,	1,	0,	0},
+	{"PLL_DIV4"                    ,	31,	1,	247,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	247,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	248,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	248,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	249,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	249,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	249,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	249,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	249,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	249,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	249,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	250,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	251,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	251,	"RAZ",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	24,	252,	"R/W",	0,	0,	0ull,	5071723ull},
+	{"RESERVED_24_63"              ,	24,	40,	252,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	10,	253,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	253,	"RAZ",	1,	1,	0,	0},
+	{"BW_CTL"                      ,	0,	5,	254,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SETTING"                     ,	0,	17,	255,	"RO",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	255,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_INT"                      ,	0,	1,	256,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	256,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	256,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	256,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	256,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	256,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	256,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	256,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	257,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	257,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	257,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	257,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	257,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	257,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	257,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	257,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	257,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	257,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	257,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	257,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	258,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	258,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	258,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	259,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	259,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	259,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	260,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	260,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	261,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	261,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	262,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	262,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	263,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	263,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	263,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	263,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	263,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	263,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	263,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	264,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	264,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	265,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	265,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	265,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	265,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	265,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	265,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	265,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	266,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	266,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	266,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	266,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	267,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	267,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	267,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	267,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	267,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	267,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	267,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	267,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	268,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	268,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	268,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	268,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	268,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	268,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	268,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	268,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	268,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	269,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	269,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	269,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	269,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	269,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	270,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	270,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	270,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	270,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	270,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	270,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	270,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	270,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	270,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	271,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	271,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	272,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	272,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	273,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	273,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	273,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	273,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	274,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	274,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	275,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	275,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	276,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	276,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	277,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	277,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	277,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	277,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	278,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	279,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	280,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	281,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	281,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	282,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	282,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	283,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	283,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	284,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	284,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	284,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	284,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	284,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	284,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLELO"                      ,	1,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_CONT"                    ,	2,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIREOR"                      ,	3,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	4,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_ENA"                     ,	5,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA"                       ,	6,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"CSHI"                        ,	7,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLECLKS"                    ,	8,	2,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRITX"                       ,	10,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	285,	"RAZ",	1,	1,	0,	0},
+	{"CLKDIV"                      ,	16,	13,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	285,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	8,	286,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	286,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	287,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	287,	"RAZ",	1,	1,	0,	0},
+	{"RXNUM"                       ,	8,	5,	287,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	287,	"RAZ",	1,	1,	0,	0},
+	{"TOTNUM"                      ,	0,	5,	288,	"WO",	1,	0,	0,	2ull},
+	{"RESERVED_5_7"                ,	5,	3,	288,	"RAZ",	1,	1,	0,	0},
+	{"TXNUM"                       ,	8,	5,	288,	"WO",	1,	0,	0,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	288,	"RAZ",	1,	1,	0,	0},
+	{"LEAVECS"                     ,	16,	1,	288,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	288,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	289,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	289,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	290,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	290,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"POF3_BS"                     ,	5,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"POF2_BS"                     ,	6,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"POF1_BS"                     ,	7,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"POF0_BS"                     ,	8,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	291,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	292,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	292,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	293,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	293,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	293,	"R/W",	0,	1,	0ull,	0},
+	{"INS1_64B"                    ,	43,	1,	293,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_45"              ,	44,	2,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INS0_ENB"                    ,	46,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS1_ENB"                    ,	47,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_48_49"              ,	48,	2,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT0_ENB"                    ,	50,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT1_ENB"                    ,	51,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_52_53"              ,	52,	2,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIS_PNIW"                    ,	54,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	293,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	293,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	294,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	294,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	295,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	295,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	295,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	295,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	295,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	295,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	295,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	296,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	297,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	297,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	298,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	298,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	298,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	299,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	299,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	299,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	300,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	301,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	301,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	302,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	302,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	302,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	302,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO1_2SML"                    ,	4,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_RTOUT"                    ,	8,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_10"               ,	9,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_OVERF"                    ,	12,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RTOUT"                    ,	16,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_18"              ,	17,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PERR"                     ,	20,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_22"              ,	21,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"G1_RTOUT"                    ,	24,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_25_26"              ,	25,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PPERR"                    ,	28,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_30"              ,	29,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PTOUT"                    ,	32,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_33_34"              ,	33,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_PPERR"                    ,	36,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_37_38"              ,	37,	2,	303,	"RAZ",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_S_E"                     ,	42,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_A_F"                     ,	43,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_S_E"                     ,	44,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_A_F"                     ,	45,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_S_E"                      ,	46,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_A_F"                      ,	47,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_S_E"                      ,	48,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_A_F"                      ,	49,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_S_E"                     ,	50,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_A_F"                     ,	51,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_S_E"                     ,	52,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_A_F"                     ,	53,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RWX_S_E"                     ,	54,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDX_S_E"                     ,	55,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_E"                     ,	56,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_F"                     ,	57,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_E"                     ,	58,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_F"                     ,	59,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_S_E"                      ,	60,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_A_F"                      ,	61,	1,	303,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	303,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	304,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO1_2SML"                    ,	4,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_RTOUT"                    ,	8,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_OVERF"                    ,	12,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_14"              ,	13,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RTOUT"                    ,	16,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_18"              ,	17,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PERR"                     ,	20,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_22"              ,	21,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G1_RTOUT"                    ,	24,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_26"              ,	25,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PPERR"                    ,	28,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_30"              ,	29,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PTOUT"                    ,	32,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_34"              ,	33,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_PPERR"                    ,	36,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_38"              ,	37,	2,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_S_E"                     ,	42,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_A_F"                     ,	43,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_S_E"                     ,	44,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_A_F"                     ,	45,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_S_E"                      ,	46,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_A_F"                      ,	47,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_S_E"                      ,	48,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_A_F"                      ,	49,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_S_E"                     ,	50,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_A_F"                     ,	51,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_S_E"                     ,	52,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_A_F"                     ,	53,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RWX_S_E"                     ,	54,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDX_S_E"                     ,	55,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_E"                     ,	56,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_F"                     ,	57,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_E"                     ,	58,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_F"                     ,	59,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_S_E"                      ,	60,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_A_F"                      ,	61,	1,	304,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	304,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	305,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	305,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	306,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	307,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	307,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	307,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	307,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	308,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	309,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	309,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	310,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL1"                     ,	4,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL1"                     ,	5,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL1"                     ,	6,	2,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPTR_O0"                     ,	16,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O1"                     ,	17,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_18_23"              ,	18,	6,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"O1_CSRM"                     ,	25,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_26_27"              ,	26,	2,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_RO"                       ,	28,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	310,	"R/W",	0,	1,	0ull,	0},
+	{"O1_RO"                       ,	32,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"O1_NS"                       ,	33,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"O1_ES"                       ,	34,	2,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_43"              ,	36,	8,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_BMODE"                    ,	44,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"P1_BMODE"                    ,	45,	1,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NADDR"                       ,	0,	61,	311,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	311,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	311,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	312,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	312,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	313,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	314,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	315,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	315,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	315,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	316,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	316,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	317,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	317,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	318,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	318,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	318,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	318,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	318,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	318,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	319,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	319,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	319,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	319,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	319,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	320,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	320,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	320,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_8"                      ,	8,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_14"                     ,	14,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_15"                     ,	15,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_21"                     ,	21,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_24"                     ,	24,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_25"                     ,	25,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_26"                     ,	26,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_27"                     ,	27,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_28"                     ,	28,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_29"                     ,	29,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_31"                     ,	31,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	321,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	32,	322,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	322,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	323,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	323,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	324,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	324,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	324,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	324,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	325,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	325,	"RO",	0,	0,	32ull,	32ull},
+	{"ISAE"                        ,	0,	1,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	326,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	326,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	326,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	326,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	326,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	326,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	326,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	326,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	326,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	326,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	326,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	326,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	326,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	326,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	326,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	326,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	326,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	326,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	8,	24,	327,	"RO",	0,	0,	1048576ull,	1048576ull},
+	{"CLS"                         ,	0,	8,	328,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	328,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	328,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	329,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	329,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	329,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	329,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	329,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	330,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	331,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	331,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	331,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	332,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	333,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	333,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	333,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	333,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	334,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	334,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	335,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	336,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	336,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	337,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	337,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	337,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	338,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	338,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	339,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	339,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	339,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	339,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	340,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	340,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	340,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	341,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	342,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	343,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	343,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	343,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	343,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	343,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	343,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	343,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	343,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	343,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	344,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	345,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	346,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	346,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	346,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	346,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	346,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	347,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	347,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	347,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	347,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	347,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	348,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	348,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	348,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	348,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	348,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	348,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	348,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	348,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	348,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	348,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	348,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	349,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	349,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	349,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	349,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	350,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	350,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	350,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	350,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	350,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	350,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	351,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	351,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	351,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	352,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	352,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	353,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	354,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	354,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	355,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	355,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	355,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	355,	"RO",	0,	1,	0ull,	0},
+	{"AP_PCIX"                     ,	13,	1,	355,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_14"              ,	14,	1,	355,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	355,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	355,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	355,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	355,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	355,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_31"              ,	20,	12,	355,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	356,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	358,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	359,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT1"                      ,	18,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_20"              ,	19,	2,	361,	"RAZ",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME1"                     ,	22,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_24"              ,	23,	2,	361,	"RAZ",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	361,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT1"                      ,	18,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_20"              ,	19,	2,	362,	"RAZ",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME1"                     ,	22,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_24"              ,	23,	2,	362,	"RAZ",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	362,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	363,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	363,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	363,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	363,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	363,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	364,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	364,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	364,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	364,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	365,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	365,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	366,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	366,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	368,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	369,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	370,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	370,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	370,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	371,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	371,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	371,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	372,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	372,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	372,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	373,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	373,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	373,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	374,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	374,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	375,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	375,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	376,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	2,	46,	376,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	376,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	376,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	377,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	378,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	378,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	378,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	378,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	379,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	380,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	380,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	381,	"R/W",	0,	0,	0ull,	8ull},
+	{"FETCHSIZ"                    ,	4,	4,	381,	"R/W",	0,	0,	0ull,	7ull},
+	{"TXRD"                        ,	8,	10,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"USELDT"                      ,	18,	1,	381,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	381,	"RAZ",	1,	1,	0,	0},
+	{"RXST"                        ,	20,	10,	381,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_30_31"              ,	30,	2,	381,	"RAZ",	1,	1,	0,	0},
+	{"TXSLOTS"                     ,	32,	10,	381,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_43"              ,	42,	2,	381,	"RAZ",	1,	1,	0,	0},
+	{"RXSLOTS"                     ,	44,	10,	381,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_62"              ,	54,	9,	381,	"RAZ",	1,	1,	0,	0},
+	{"RDPEND"                      ,	63,	1,	381,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYNCMISSED"                 ,	0,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXWRAP"                      ,	2,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXST"                        ,	3,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXWRAP"                      ,	4,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRD"                        ,	5,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXEMPTY"                     ,	6,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXOVF"                       ,	7,	1,	382,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	382,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCMISSED"                 ,	0,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXWRAP"                      ,	2,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXST"                        ,	3,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXWRAP"                      ,	4,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXRD"                        ,	5,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXEMPTY"                     ,	6,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXOVF"                       ,	7,	1,	383,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	383,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	384,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	384,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	385,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	385,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	386,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	387,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	388,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	389,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	390,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	391,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	392,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	393,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	394,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	394,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	394,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"USECLK1"                     ,	1,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	2,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	395,	"RAZ",	1,	1,	0,	0},
+	{"SAMPPT"                      ,	32,	16,	395,	"R/W",	0,	1,	0ull,	0},
+	{"DRVTIM"                      ,	48,	16,	395,	"R/W",	0,	1,	0ull,	0},
+	{"DEBUGINFO"                   ,	0,	64,	396,	"RO",	1,	1,	0,	0},
+	{"FRAM"                        ,	0,	3,	397,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	397,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	397,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	398,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	398,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	399,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	400,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	401,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	402,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	403,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	404,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	405,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	406,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	407,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	407,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	407,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCPOL"                    ,	1,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCLKPOL"                     ,	2,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITLEN"                      ,	3,	2,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRABIT"                    ,	5,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUMSLOTS"                    ,	6,	10,	408,	"R/W",	0,	1,	0ull,	0},
+	{"FSYNCLOC"                    ,	16,	5,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCLEN"                    ,	21,	5,	408,	"R/W",	0,	0,	0ull,	2ull},
+	{"RESERVED_26_31"              ,	26,	6,	408,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCSAMP"                   ,	32,	16,	408,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_62"              ,	48,	15,	408,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCGOOD"                   ,	63,	1,	408,	"RO",	0,	0,	0ull,	1ull},
+	{"DEBUGINFO"                   ,	0,	64,	409,	"RO",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	410,	"R/W",	0,	1,	0ull,	0},
+	{"NUMSAMP"                     ,	32,	16,	410,	"R/W",	0,	1,	0ull,	0},
+	{"DELTASAMP"                   ,	48,	16,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	411,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	411,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	412,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	413,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	413,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	413,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	414,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	414,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	414,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	414,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKTDRP"                      ,	0,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	415,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	416,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	416,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	417,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	418,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	418,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	418,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	418,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	418,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	419,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	419,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	420,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	421,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	2,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	422,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	422,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	422,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	422,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	423,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	423,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	424,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	425,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	425,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	426,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	426,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	427,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	427,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	430,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	430,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	431,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	431,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	432,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	432,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	433,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	433,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	434,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	434,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	435,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	435,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	436,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	436,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	437,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	437,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	438,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	439,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	439,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	440,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	441,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	442,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	442,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	442,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	443,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	443,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	444,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	444,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	445,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	445,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	445,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	445,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	446,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	446,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	446,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	446,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	446,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	447,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	447,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	447,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	447,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	448,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	448,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	448,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	448,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	449,	"RO",	1,	0,	0,	0ull},
+	{"WIDX2"                       ,	0,	17,	450,	"RO",	1,	0,	0,	0ull},
+	{"RIDX2"                       ,	17,	17,	450,	"RO",	1,	0,	0,	0ull},
+	{"WIDX"                        ,	34,	17,	450,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	450,	"RAZ",	1,	0,	0,	0ull},
+	{"RIDX"                        ,	0,	17,	451,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	451,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	452,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	452,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	452,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	452,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	452,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	453,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	453,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	453,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	453,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	453,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	454,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	4,	455,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	4,	2,	455,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	6,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	7,	7,	455,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	3,	455,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	17,	5,	455,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	22,	3,	455,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	26,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	455,	"RAZ",	1,	0,	0,	0ull},
+	{"CBUF_FRE"                    ,	28,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"XFER_DWR"                    ,	29,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"XFER_WOR"                    ,	30,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	31,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	32,	16,	455,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CNT"                    ,	48,	13,	455,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_LEN"                    ,	61,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_SOP"                    ,	62,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	63,	1,	455,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	0,	2,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_UID"                    ,	2,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CHK"                    ,	3,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"WORK_MIN"                    ,	4,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	7,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFM"                    ,	8,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	456,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	457,	"RO",	1,	0,	0,	0ull},
+	{"START"                       ,	16,	33,	457,	"RO",	1,	0,	0,	0ull},
+	{"DWB"                         ,	49,	9,	457,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	457,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	458,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	458,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	458,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	458,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	458,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	458,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	459,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	459,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	459,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	459,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	459,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	459,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	460,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	460,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	460,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	460,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	460,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	460,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	460,	"WR0",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	460,	"WR0",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	460,	"WR0",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	461,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	461,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	461,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	461,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	461,	"RAZ",	1,	0,	0,	0ull},
+	{"PSB"                         ,	0,	7,	462,	"RO",	1,	0,	0,	0ull},
+	{"PDB"                         ,	7,	4,	462,	"RO",	1,	0,	0,	0ull},
+	{"QCB"                         ,	11,	2,	462,	"RO",	1,	0,	0,	0ull},
+	{"QSB"                         ,	13,	2,	462,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	15,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"CRC"                         ,	16,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"OUT"                         ,	17,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	18,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"WIF"                         ,	19,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"RIF"                         ,	20,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	21,	1,	462,	"RO",	1,	0,	0,	0ull},
+	{"PSB2"                        ,	22,	5,	462,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	463,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	17,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	464,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	465,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	466,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	466,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	467,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	468,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	468,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	469,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR"                         ,	0,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	2,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	3,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	4,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	5,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT0"                        ,	6,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT1"                        ,	7,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	8,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	471,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	2,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	471,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	472,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	472,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	473,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	473,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	473,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	473,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	473,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	473,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	474,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	474,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	475,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	476,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	476,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	9,	477,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	477,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	478,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	478,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	479,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"RESERVED_16_63"              ,	16,	48,	479,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	480,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	480,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	480,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	480,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	480,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	8,	481,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_11"               ,	8,	4,	481,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	8,	481,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_20_23"              ,	20,	4,	481,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	9,	481,	"RO",	0,	1,	249ull,	0},
+	{"RESERVED_33_35"              ,	33,	3,	481,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	9,	481,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	481,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	9,	481,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	481,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	482,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	482,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	483,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	484,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	484,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	485,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	485,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	485,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	9,	486,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	486,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	9,	486,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	486,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	486,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	486,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	487,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	487,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	487,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	487,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	8,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_11"               ,	8,	4,	488,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	8,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_23"              ,	20,	4,	488,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	488,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	488,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	489,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	489,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	490,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	490,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	490,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	491,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	492,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	492,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	492,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	492,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	492,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	492,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	493,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	493,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	1,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	493,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	494,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	494,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	495,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	495,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	495,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	496,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	496,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	496,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	497,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	497,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	497,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	498,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	498,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	498,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	499,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	499,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	499,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	500,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	501,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	502,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	502,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	502,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	502,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	503,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	503,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	504,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	504,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	505,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	506,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	507,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	507,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	507,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	507,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	508,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	510,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	511,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	512,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	512,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	513,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	513,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	513,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	513,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	514,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	516,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	517,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	518,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	518,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	519,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	519,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	520,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	520,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	520,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	520,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	520,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	521,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	522,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	523,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	524,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	525,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	525,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	525,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	525,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	525,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	526,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INEPINT"                     ,	0,	16,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	529,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	529,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	529,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	529,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	530,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	530,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	530,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	530,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	530,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	531,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	531,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	531,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	531,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	531,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	531,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	532,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	533,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	534,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	535,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	535,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	535,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	535,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	535,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	535,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	535,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	536,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	536,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	536,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	536,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	536,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	536,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	537,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	537,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	538,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	539,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	540,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	540,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	541,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	543,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	545,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	545,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	545,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	545,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	545,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	546,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	547,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	547,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	547,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	547,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	547,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	547,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	547,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	547,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	547,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	547,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	547,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	547,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	548,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	548,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	548,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	548,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	548,	"RO",	0,	0,	1ull,	1ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	548,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	548,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	549,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	549,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	549,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	549,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	549,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"AVALIDFLTR"                  ,	22,	1,	549,	"RO",	0,	0,	1ull,	1ull},
+	{"BVALIDFLTR"                  ,	23,	1,	549,	"RO",	0,	0,	1ull,	1ull},
+	{"SESSENDFLTR"                 ,	24,	1,	549,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_25_31"              ,	25,	7,	549,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	550,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	550,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	550,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	550,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	551,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	551,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	551,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	551,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	552,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	552,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	553,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	554,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	554,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	554,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	554,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	554,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	554,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	555,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	555,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	555,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	555,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	556,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	556,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	556,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	557,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	557,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	558,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	559,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	559,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	560,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	561,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	561,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	561,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	561,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	561,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	562,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	563,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	563,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	563,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	563,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	563,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	563,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	564,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	565,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	566,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	567,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	568,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	569,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	570,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	572,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	572,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	573,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	574,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	574,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	574,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	575,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	575,	"R/W",	0,	0,	1824ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	578,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	579,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	580,	"R/W",	0,	0,	4ull,	4ull},
+	{"HRST"                        ,	3,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	580,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	580,	"R/W",	0,	0,	2ull,	2ull},
+	{"P_COM_ON"                    ,	13,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_XENBN"                     ,	14,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_RCLK"                      ,	15,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_X_ON"                      ,	16,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"HCLK_RST"                    ,	17,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_18_63"              ,	18,	46,	580,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	581,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	581,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	582,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	582,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	583,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	583,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	584,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	584,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	585,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	585,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	586,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	586,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	587,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	587,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	588,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	588,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	589,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	589,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	590,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	590,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	591,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	591,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	592,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	592,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	593,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	593,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	594,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	594,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	595,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	595,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	596,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	596,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	597,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	597,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	598,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	598,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	598,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"N2U_PF"                      ,	26,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"N2U_PE"                      ,	27,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_D_PE"                    ,	28,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_D_PF"                    ,	29,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_C_PF"                    ,	30,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_C_PE"                    ,	31,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	599,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"N2U_PF"                      ,	26,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"N2U_PE"                      ,	27,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_D_PE"                    ,	28,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_D_PF"                    ,	29,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_C_PF"                    ,	30,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_C_PE"                    ,	31,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	600,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	600,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	600,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"TUNING"                      ,	19,	4,	601,	"R/W",	0,	0,	9ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	601,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	601,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	601,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	601,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	601,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	601,	"RAZ",	1,	1,	0,	0},
+	{"ZIP_CTL"                     ,	0,	4,	602,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	602,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	602,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	603,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	604,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	604,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	605,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	605,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	605,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	605,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	605,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	606,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	607,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	607,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	608,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn30xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_gmii_rx_clk_set"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	2,	0},
+	{"cvmx_asx#_gmii_rx_dat_set"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	2},
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	6,	4},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	6,	10},
+	{"cvmx_asx#_mii_rx_dat_set"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	2,	16},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	4,	18},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	2,	22},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	2,	24},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	2,	26},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	4,	28},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	32},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	17,	2,	34},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	18,	2,	36},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	19,	2,	38},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	20,	2,	40},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	21,	2,	42},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	22,	19,	44},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	25,	2,	63},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	28,	19,	65},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	31,	2,	84},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	32,	2,	86},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	33,	2,	88},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	34,	2,	90},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	35,	2,	92},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	36,	2,	94},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	37,	1,	96},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	38,	2,	97},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	39,	2,	99},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	40,	4,	101},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	41,	2,	105},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	42,	3,	107},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	46,	7,	110},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	47,	6,	117},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	48,	6,	123},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	49,	7,	129},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	50,	29,	136},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	51,	29,	165},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	194},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	196},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	3,	198},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	69,	3,	201},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	2,	204},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	2,	206},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	8,	208},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	73,	2,	216},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	4,	218},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	2,	222},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	76,	5,	224},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	1,	229},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	82,	1,	230},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	85,	1,	231},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	88,	1,	232},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	1,	233},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	94,	1,	234},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	235},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	100,	4,	237},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	241},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	106,	11,	243},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	10,	254},
+	{"cvmx_gmx#_rx#_frm_max"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	112,	2,	264},
+	{"cvmx_gmx#_rx#_frm_min"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	266},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	2,	268},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	20,	270},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	124,	20,	290},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	127,	2,	310},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	130,	4,	312},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	133,	2,	316},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	136,	2,	318},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	139,	2,	320},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	142,	2,	322},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	145,	2,	324},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	148,	2,	326},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	151,	2,	328},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	154,	2,	330},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	157,	2,	332},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	160,	2,	334},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	163,	4,	336},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	166,	2,	340},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	169,	2,	342},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	172,	2,	344},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	175,	4,	346},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	176,	2,	350},
+	{"cvmx_gmx#_rx_tx_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	177,	4,	352},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	178,	2,	356},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	181,	3,	358},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	182,	5,	361},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	185,	2,	366},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	188,	2,	368},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	191,	3,	370},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	194,	2,	373},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	197,	2,	375},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	200,	2,	377},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	203,	2,	379},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	206,	2,	381},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	209,	2,	383},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	212,	2,	385},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	215,	2,	387},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	218,	2,	389},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	221,	2,	391},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	224,	2,	393},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	227,	2,	395},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	230,	2,	397},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	233,	2,	399},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	236,	2,	401},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	239,	2,	403},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	242,	2,	405},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	245,	2,	407},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	248,	2,	409},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	251,	2,	411},
+	{"cvmx_gmx#_tx_clk_msk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	2,	413},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	254,	2,	415},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	255,	2,	417},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	256,	3,	419},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	257,	10,	422},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	258,	10,	432},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	259,	2,	442},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	260,	2,	444},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	261,	6,	446},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	262,	2,	452},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	263,	2,	454},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	264,	2,	456},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	265,	7,	458},
+	{"cvmx_gpio_boot_ena"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	281,	3,	465},
+	{"cvmx_gpio_dbg_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	282,	2,	468},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	283,	2,	470},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	284,	2,	472},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	285,	2,	474},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	286,	2,	476},
+	{"cvmx_gpio_xbit_cfg#"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	287,	6,	478},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	295,	19,	484},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	296,	6,	503},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	297,	3,	509},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	298,	5,	512},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	299,	5,	517},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	300,	1,	522},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	301,	1,	523},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	302,	5,	524},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	303,	5,	529},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	304,	5,	534},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	305,	5,	539},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	306,	1,	544},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	307,	1,	545},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	308,	2,	546},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	309,	2,	548},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	310,	2,	550},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	311,	2,	552},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	312,	17,	554},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	313,	2,	571},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	314,	1,	573},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	315,	10,	574},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	316,	6,	584},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	317,	6,	590},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	318,	2,	596},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	319,	2,	598},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	320,	2,	600},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	321,	3,	602},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	325,	2,	605},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	329,	6,	607},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	330,	5,	613},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	331,	6,	618},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	332,	7,	624},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	333,	2,	631},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	341,	2,	633},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	342,	3,	635},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	343,	5,	638},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	351,	3,	643},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	352,	2,	646},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	353,	2,	648},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	354,	2,	650},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	355,	7,	652},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	356,	6,	659},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	357,	8,	665},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	358,	9,	673},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	359,	10,	682},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	360,	5,	692},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	361,	4,	697},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	362,	2,	701},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	363,	17,	703},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	364,	19,	720},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	365,	3,	739},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	366,	4,	742},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	367,	2,	746},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	371,	17,	748},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	372,	2,	765},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	373,	2,	767},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	374,	3,	769},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	375,	2,	772},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	376,	2,	774},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	377,	2,	776},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	378,	7,	778},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	379,	6,	785},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	380,	3,	791},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	381,	3,	794},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	382,	2,	797},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	383,	2,	799},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	384,	2,	801},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	385,	3,	803},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	386,	15,	806},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	387,	9,	821},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	388,	20,	830},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	389,	2,	850},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	390,	2,	852},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	391,	2,	854},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	392,	18,	856},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	393,	4,	874},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	394,	5,	878},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	395,	6,	883},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	396,	2,	889},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	397,	2,	891},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	398,	14,	893},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	399,	10,	907},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	400,	2,	917},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	401,	2,	919},
+	{"cvmx_lmc#_pll_bwctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	402,	3,	921},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	403,	9,	924},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	404,	5,	933},
+	{"cvmx_lmc#_wodt_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	405,	5,	938},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	406,	5,	943},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	407,	3,	948},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	3,	951},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	409,	3,	954},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	410,	5,	957},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	412,	1,	962},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	413,	10,	963},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	421,	13,	973},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	429,	4,	986},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	430,	2,	990},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	431,	2,	992},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	432,	10,	994},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	433,	9,	1004},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	434,	2,	1013},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	435,	8,	1015},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	436,	4,	1023},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	437,	2,	1027},
+	{"cvmx_mio_fus_unlock"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	438,	2,	1029},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	439,	2,	1031},
+	{"cvmx_mio_pll_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	440,	2,	1033},
+	{"cvmx_mio_pll_setting"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	441,	2,	1035},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	442,	13,	1037},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	443,	12,	1050},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	444,	3,	1062},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	445,	3,	1065},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	446,	2,	1068},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	448,	2,	1070},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	450,	2,	1072},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	452,	7,	1074},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	454,	2,	1081},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	456,	7,	1083},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	458,	4,	1090},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	460,	8,	1094},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	462,	9,	1102},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	7,	1111},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	466,	9,	1118},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	468,	2,	1127},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	470,	2,	1129},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	4,	1131},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	474,	2,	1135},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	476,	2,	1137},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	478,	2,	1139},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	480,	4,	1141},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	482,	2,	1145},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	484,	2,	1147},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	486,	2,	1149},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	488,	2,	1151},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	490,	2,	1153},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	492,	2,	1155},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	494,	6,	1157},
+	{"cvmx_mpi_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	496,	14,	1163},
+	{"cvmx_mpi_dat#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	497,	2,	1177},
+	{"cvmx_mpi_sts"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	506,	4,	1179},
+	{"cvmx_mpi_tx"                 ,	CVMX_CSR_DB_TYPE_NCB,	64,	507,	6,	1183},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	508,	2,	1189},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	509,	2,	1191},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	510,	19,	1193},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	511,	3,	1212},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	512,	15,	1215},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	513,	2,	1230},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	514,	13,	1232},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	515,	3,	1245},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	516,	3,	1248},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	517,	3,	1251},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	518,	3,	1254},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	519,	2,	1257},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	520,	2,	1259},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	521,	9,	1261},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	522,	45,	1270},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	523,	45,	1315},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	524,	2,	1360},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	525,	2,	1362},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	526,	10,	1364},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	530,	1,	1374},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	531,	2,	1375},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	532,	14,	1377},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	533,	3,	1391},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	534,	2,	1394},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	535,	3,	1396},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	536,	3,	1399},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	537,	3,	1402},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	538,	4,	1405},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	539,	2,	1409},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	540,	13,	1411},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	541,	3,	1424},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	542,	33,	1427},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	543,	2,	1460},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	544,	2,	1462},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	545,	5,	1464},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	577,	2,	1469},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	578,	24,	1471},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	579,	2,	1495},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	580,	7,	1497},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	581,	5,	1504},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	582,	1,	1509},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	583,	5,	1510},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	584,	1,	1515},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	585,	4,	1516},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	586,	2,	1520},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	587,	1,	1522},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	588,	2,	1523},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	589,	4,	1525},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	590,	2,	1529},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	591,	4,	1531},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	592,	16,	1535},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	593,	1,	1551},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	594,	1,	1552},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	595,	18,	1553},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	596,	1,	1571},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	597,	1,	1572},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	598,	7,	1573},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	599,	7,	1580},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	600,	13,	1587},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	601,	10,	1600},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	602,	10,	1610},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	603,	7,	1620},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	604,	2,	1627},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	605,	1,	1629},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	606,	2,	1630},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	607,	22,	1632},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	608,	2,	1654},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	609,	1,	1656},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	611,	1,	1657},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	613,	1,	1658},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	615,	1,	1659},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	616,	31,	1660},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	617,	31,	1691},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	618,	31,	1722},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	619,	31,	1753},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	620,	2,	1784},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	621,	2,	1786},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	622,	1,	1788},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	623,	1,	1789},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	624,	1,	1790},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	625,	3,	1791},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	626,	3,	1794},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	627,	3,	1797},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	628,	3,	1800},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	629,	2,	1803},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	630,	2,	1805},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	631,	4,	1807},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	632,	1,	1811},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	633,	4,	1812},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	634,	1,	1816},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	635,	2,	1817},
+	{"cvmx_pcm#_dma_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	636,	12,	1819},
+	{"cvmx_pcm#_int_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	640,	9,	1831},
+	{"cvmx_pcm#_int_sum"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	644,	9,	1840},
+	{"cvmx_pcm#_rxaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	648,	2,	1849},
+	{"cvmx_pcm#_rxcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	652,	2,	1851},
+	{"cvmx_pcm#_rxmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	656,	1,	1853},
+	{"cvmx_pcm#_rxmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	660,	1,	1854},
+	{"cvmx_pcm#_rxmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	664,	1,	1855},
+	{"cvmx_pcm#_rxmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	668,	1,	1856},
+	{"cvmx_pcm#_rxmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	672,	1,	1857},
+	{"cvmx_pcm#_rxmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	676,	1,	1858},
+	{"cvmx_pcm#_rxmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	680,	1,	1859},
+	{"cvmx_pcm#_rxmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	684,	1,	1860},
+	{"cvmx_pcm#_rxstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	688,	3,	1861},
+	{"cvmx_pcm#_tdm_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	692,	6,	1864},
+	{"cvmx_pcm#_tdm_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	696,	1,	1870},
+	{"cvmx_pcm#_txaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	700,	3,	1871},
+	{"cvmx_pcm#_txcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	704,	2,	1874},
+	{"cvmx_pcm#_txmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	708,	1,	1876},
+	{"cvmx_pcm#_txmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	712,	1,	1877},
+	{"cvmx_pcm#_txmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	716,	1,	1878},
+	{"cvmx_pcm#_txmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	720,	1,	1879},
+	{"cvmx_pcm#_txmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	724,	1,	1880},
+	{"cvmx_pcm#_txmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	728,	1,	1881},
+	{"cvmx_pcm#_txmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	732,	1,	1882},
+	{"cvmx_pcm#_txmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	736,	1,	1883},
+	{"cvmx_pcm#_txstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	740,	3,	1884},
+	{"cvmx_pcm_clk#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	744,	12,	1887},
+	{"cvmx_pcm_clk#_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	746,	1,	1899},
+	{"cvmx_pcm_clk#_gen"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	748,	3,	1900},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	750,	2,	1903},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	751,	4,	1905},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	755,	8,	1909},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	756,	16,	1917},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	757,	10,	1933},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	758,	10,	1943},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	759,	2,	1953},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	760,	16,	1955},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	765,	25,	1971},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	770,	2,	1996},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	834,	2,	1998},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	842,	9,	2000},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	846,	2,	2009},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	847,	2,	2011},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	848,	2,	2013},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	853,	2,	2015},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	858,	2,	2017},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	863,	2,	2019},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	868,	2,	2021},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	873,	2,	2023},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	878,	2,	2025},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	883,	2,	2027},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	888,	2,	2029},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	893,	2,	2031},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	898,	2,	2033},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	899,	2,	2035},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	904,	2,	2037},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	909,	2,	2039},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	914,	2,	2041},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	978,	2,	2043},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	979,	3,	2045},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	980,	3,	2048},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	981,	2,	2051},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	982,	2,	2053},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	983,	4,	2055},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	984,	5,	2059},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	985,	4,	2064},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	986,	5,	2068},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	987,	1,	2073},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	988,	4,	2074},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	989,	2,	2078},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	990,	5,	2080},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	991,	5,	2085},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	992,	1,	2090},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	993,	19,	2091},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	994,	7,	2110},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	995,	4,	2117},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	996,	6,	2121},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	997,	6,	2127},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	9,	2133},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	999,	5,	2142},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1000,	13,	2147},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1001,	4,	2160},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1002,	2,	2164},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	3,	2166},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1004,	5,	2169},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1005,	3,	2174},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	3,	2177},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1007,	2,	2180},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1008,	3,	2182},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1009,	12,	2185},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1010,	2,	2197},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1011,	13,	2199},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1012,	3,	2212},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1013,	2,	2215},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1021,	2,	2217},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1022,	2,	2219},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1023,	2,	2221},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1024,	2,	2223},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1025,	5,	2225},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1033,	10,	2230},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1041,	2,	2240},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1042,	2,	2242},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1043,	2,	2244},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1051,	3,	2246},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1052,	6,	2249},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1068,	5,	2255},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1069,	7,	2260},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1085,	2,	2267},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1101,	3,	2269},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1102,	5,	2272},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1103,	8,	2277},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1104,	6,	2285},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1105,	2,	2291},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1106,	4,	2293},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1107,	4,	2297},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1108,	6,	2301},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1109,	3,	2307},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1110,	5,	2310},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1111,	4,	2315},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1112,	6,	2319},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1113,	4,	2325},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1114,	2,	2329},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1115,	4,	2331},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1116,	2,	2335},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1117,	3,	2337},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1118,	2,	2340},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1119,	2,	2342},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1120,	8,	2344},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1121,	11,	2352},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1122,	15,	2363},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1127,	8,	2378},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1132,	8,	2386},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1133,	4,	2394},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1138,	15,	2398},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1143,	6,	2413},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1148,	6,	2419},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1149,	4,	2425},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1154,	2,	2429},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1158,	6,	2431},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1159,	4,	2437},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1160,	1,	2441},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1161,	1,	2442},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1162,	1,	2443},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1163,	7,	2444},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1164,	1,	2451},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1165,	14,	2452},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1166,	10,	2466},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1167,	12,	2476},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1168,	32,	2488},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1169,	32,	2520},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1170,	2,	2552},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1171,	4,	2554},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1172,	13,	2558},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1173,	10,	2571},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1174,	10,	2581},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1175,	2,	2591},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1176,	6,	2593},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1177,	5,	2599},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1178,	6,	2604},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1179,	5,	2610},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1180,	1,	2615},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1181,	13,	2616},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1182,	2,	2629},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1183,	2,	2631},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1184,	11,	2633},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1192,	3,	2644},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	1193,	12,	2647},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1201,	12,	2659},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1209,	6,	2671},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1217,	4,	2677},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1225,	2,	2681},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1226,	2,	2683},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1227,	15,	2685},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1228,	2,	2700},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1229,	3,	2702},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	1230,	1,	2705},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1238,	6,	2706},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1239,	4,	2712},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1240,	15,	2716},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1241,	6,	2731},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1242,	2,	2737},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1243,	2,	2739},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1244,	2,	2741},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1245,	2,	2743},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1246,	2,	2745},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1247,	2,	2747},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1248,	2,	2749},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1249,	2,	2751},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1250,	2,	2753},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1251,	2,	2755},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1252,	2,	2757},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1253,	2,	2759},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1254,	2,	2761},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1255,	2,	2763},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1256,	2,	2765},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1257,	2,	2767},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1258,	7,	2769},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1259,	39,	2776},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1260,	39,	2815},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1261,	22,	2854},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800B0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800B0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_MII_RX_DAT_SET"         ,	   0x11800B0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"GMX0_RX000_FRM_MAX"          ,	   0x1180008000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"GMX0_RX001_FRM_MAX"          ,	   0x1180008000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"GMX0_RX002_FRM_MAX"          ,	   0x1180008001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"GMX0_RX000_FRM_MIN"          ,	   0x1180008000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"GMX0_RX001_FRM_MIN"          ,	   0x1180008000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"GMX0_RX002_FRM_MIN"          ,	   0x1180008001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX_CLK_MSK000"          ,	   0x1180008000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX_CLK_MSK001"          ,	   0x1180008000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	121},
+	{"GPIO_BOOT_ENA"               ,	   0x10700000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	122},
+	{"GPIO_DBG_ENA"                ,	   0x10700000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"GPIO_XBIT_CFG16"             ,	   0x1070000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG17"             ,	   0x1070000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG18"             ,	   0x1070000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG19"             ,	   0x1070000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG20"             ,	   0x1070000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG21"             ,	   0x1070000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG22"             ,	   0x1070000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_XBIT_CFG23"             ,	   0x1070000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	143},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	144},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"LMC0_PLL_BWCTL"              ,	   0x1180088000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"MIO_FUS_UNLOCK"              ,	   0x1180000001578ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"MIO_PLL_CTL"                 ,	   0x1180000001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"MIO_PLL_SETTING"             ,	   0x1180000001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	267},
+	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT4"                    ,	   0x10700000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT5"                    ,	   0x10700000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT6"                    ,	   0x10700000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT7"                    ,	   0x10700000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_DAT8"                    ,	   0x10700000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	268},
+	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	269},
+	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	270},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	271},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	272},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	273},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	274},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	275},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	290},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	300},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	305},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	306},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	307},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	308},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	309},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	310},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	311},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	312},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	313},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	314},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	315},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	316},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	317},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	318},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	319},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	320},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	321},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	322},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	323},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	324},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	336},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	337},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	338},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	338},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	339},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	339},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	340},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	340},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	341},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	342},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	343},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	344},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	345},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	346},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	347},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	348},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	349},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	351},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	352},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	353},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	355},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	356},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	357},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	358},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	359},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	360},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	361},
+	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCM3_DMA_CFG"                ,	   0x107000001C018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"PCM3_INT_ENA"                ,	   0x107000001C020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"PCM3_INT_SUM"                ,	   0x107000001C028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"PCM3_RXADDR"                 ,	   0x107000001C068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"PCM3_RXCNT"                  ,	   0x107000001C060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM3_RXMSK0"                 ,	   0x107000001C0C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM3_RXMSK1"                 ,	   0x107000001C0C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM3_RXMSK2"                 ,	   0x107000001C0D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM3_RXMSK3"                 ,	   0x107000001C0D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM3_RXMSK4"                 ,	   0x107000001C0E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM3_RXMSK5"                 ,	   0x107000001C0E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM3_RXMSK6"                 ,	   0x107000001C0F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM3_RXMSK7"                 ,	   0x107000001C0F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM3_RXSTART"                ,	   0x107000001C058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM3_TDM_CFG"                ,	   0x107000001C010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM3_TDM_DBG"                ,	   0x107000001C030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM3_TXADDR"                 ,	   0x107000001C050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM3_TXCNT"                  ,	   0x107000001C048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM3_TXMSK0"                 ,	   0x107000001C080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM3_TXMSK1"                 ,	   0x107000001C088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM3_TXMSK2"                 ,	   0x107000001C090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM3_TXMSK3"                 ,	   0x107000001C098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM3_TXMSK4"                 ,	   0x107000001C0A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM3_TXMSK5"                 ,	   0x107000001C0A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM3_TXMSK6"                 ,	   0x107000001C0B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_TXMSK7"                 ,	   0x107000001C0B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM3_TXSTART"                ,	   0x107000001C040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	452},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	453},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	454},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	455},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	456},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	457},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	458},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	459},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	460},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	461},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	462},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	463},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	464},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	465},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	466},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	467},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	468},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	488},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	489},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	490},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	491},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	492},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	493},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	494},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	495},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	496},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	497},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	498},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	499},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	500},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	501},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	502},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	503},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	504},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	505},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	506},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	507},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	508},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	509},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	512},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	516},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	519},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	520},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	521},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	522},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	523},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	524},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	525},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	526},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	542},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	543},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	544},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	545},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	546},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	547},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	548},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	549},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	550},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	551},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	552},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	553},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	554},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	555},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	556},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	557},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	558},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	559},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"SETTING"                     ,	0,	5,	0,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	0,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	1,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_3"                ,	3,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"TXPOP"                       ,	4,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"TXPSH"                       ,	8,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_11_63"              ,	11,	53,	2,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"TXPOP"                       ,	4,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"TXPSH"                       ,	8,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	3,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	4,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	4,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	3,	5,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	5,	"RAZ",	1,	1,	0,	0},
+	{"EXT_LOOP"                    ,	4,	3,	5,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	5,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	6,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	6,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	3,	7,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	7,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	8,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	8,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	9,	"R/W",	0,	0,	8ull,	8ull},
+	{"PCTL"                        ,	4,	4,	9,	"R/W",	0,	0,	8ull,	8ull},
+	{"BYPASS"                      ,	8,	1,	9,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	9,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	3,	10,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	10,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	3,	11,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	11,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	12,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	12,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	1,	13,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	13,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	1,	14,	"RO",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	14,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	15,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_47"              ,	47,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	16,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	1,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	17,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_47"              ,	47,	1,	18,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	18,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	18,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	18,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	1,	19,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	19,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	20,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	21,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	21,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	1,	22,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	22,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	23,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	1,	24,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	24,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	25,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	26,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	26,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	27,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	27,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	28,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	28,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	28,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	29,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	29,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	30,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	31,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	31,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	31,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	31,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	31,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	32,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	32,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	32,	"RO",	1,	1,	0,	0},
+	{"RESERVED_23_27"              ,	23,	5,	32,	"RAZ",	1,	1,	0,	0},
+	{"PLL_MUL"                     ,	28,	3,	32,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	32,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	33,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	33,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	34,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	35,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	35,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	36,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	37,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	38,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	38,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	39,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	39,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	39,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	40,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	40,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	40,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	41,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	41,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	42,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	42,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	43,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	3,	43,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_21"               ,	5,	17,	43,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	3,	43,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_25"              ,	25,	1,	43,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	43,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	43,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	43,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	44,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	45,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	45,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0MII"                       ,	2,	1,	45,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	45,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	46,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	46,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	47,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	47,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	47,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	47,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	47,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	48,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	49,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	50,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	51,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	52,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	53,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	54,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	54,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	55,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	55,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	55,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	55,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	56,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	56,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	57,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	58,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	58,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	58,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	58,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	58,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	58,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_FREE"                    ,	6,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLAN_LEN"                    ,	7,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	58,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	59,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	59,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	60,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	60,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	61,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	61,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	62,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	62,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	63,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	63,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	64,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	64,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	65,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	65,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	65,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	65,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	66,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	66,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	67,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	67,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	68,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	68,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	69,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	70,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	70,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	71,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	71,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	72,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	72,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	73,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	73,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	74,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	74,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	75,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	75,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	76,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	76,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	77,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	77,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	78,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	78,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	79,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	79,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	3,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_15"               ,	3,	13,	80,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	3,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	80,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	81,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_3_63"               ,	3,	61,	81,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	3,	82,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	82,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	3,	82,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	82,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	83,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	83,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	84,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	84,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	84,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	85,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	85,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	85,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	85,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	85,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	86,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	86,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	87,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	87,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	88,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	88,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	88,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	89,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	89,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	90,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	90,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	91,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	91,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	92,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	92,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	93,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	94,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	94,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	95,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	95,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	96,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	96,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	97,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	97,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	98,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	98,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	99,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	99,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	100,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	100,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	101,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	101,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	106,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	106,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	7,	107,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_7_63"               ,	7,	57,	107,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	3,	108,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	108,	"RAZ",	1,	1,	0,	0},
+	{"MSK"                         ,	0,	1,	109,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	109,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	110,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	110,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	3,	111,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_3_63"               ,	3,	61,	111,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	112,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	112,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	112,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	3,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	3,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	3,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	3,	113,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	113,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKO_NXA"                     ,	0,	1,	114,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	3,	114,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	3,	114,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	3,	114,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	3,	114,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	114,	"RAZ",	0,	0,	0ull,	0ull},
+	{"JAM"                         ,	0,	8,	115,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	115,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	116,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	116,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	3,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	117,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	3,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	117,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	3,	117,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	117,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DMAC"                        ,	0,	48,	118,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	118,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	119,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	119,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	120,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	120,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	121,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	121,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	122,	"RAZ",	1,	1,	0,	0},
+	{"BOOT_ENA"                    ,	8,	4,	122,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	122,	"RAZ",	1,	1,	0,	0},
+	{"DBG_ENA"                     ,	0,	21,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	123,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	124,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	124,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	24,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	125,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	24,	126,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	126,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	24,	127,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	127,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	128,	"RAZ",	1,	1,	0,	0},
+	{"FIL_CNT"                     ,	4,	4,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	128,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	129,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	129,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	130,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	130,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	130,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	130,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	131,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	131,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	131,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	132,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	132,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	132,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	132,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	132,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	133,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	133,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	133,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	133,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	133,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	134,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	135,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	136,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	137,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	138,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	138,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	138,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	138,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	138,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	139,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	139,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	139,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	139,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	139,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	140,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	141,	"R/W",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	6,	142,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	142,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	143,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	143,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	144,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	145,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	146,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	147,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	149,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	149,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	150,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	151,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	152,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	153,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	153,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	154,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	154,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	155,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	155,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	156,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	156,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	157,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	157,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	157,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	157,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	157,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	158,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	158,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	158,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	158,	"RO",	0,	0,	4ull,	4ull},
+	{"RESERVED_44_63"              ,	44,	20,	158,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	159,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	160,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	160,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	160,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	160,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	160,	"RO",	0,	0,	8ull,	8ull},
+	{"RESERVED_61_63"              ,	61,	3,	160,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	161,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	161,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	162,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	162,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	163,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	163,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	164,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	164,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	164,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	164,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	164,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	165,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	165,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	165,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	3,	166,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_63"               ,	3,	61,	166,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	167,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	167,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	168,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	168,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	169,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	9,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_18"              ,	15,	4,	169,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	169,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	169,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	5,	170,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_8"                ,	5,	4,	170,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	170,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	170,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	170,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	170,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	171,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	171,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	171,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	172,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	172,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	172,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	172,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	172,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	172,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	172,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	2,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_5"                ,	5,	1,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	1,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_9"                ,	7,	3,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	2,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	174,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	174,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	175,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	175,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	176,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	2,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_17"              ,	16,	2,	177,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	2,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	177,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	2,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_26"              ,	25,	2,	177,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	177,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	178,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	178,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	8,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	8,	19,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	2,	180,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_2_3"                ,	2,	2,	180,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STPARTDIS"                   ,	4,	1,	180,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	180,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	181,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	181,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	4,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	183,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	4,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	184,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	185,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	185,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	185,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	186,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	187,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	188,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	189,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	189,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	189,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	189,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	189,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	189,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	9,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	2,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_13"              ,	13,	1,	190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	191,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	194,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	195,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	195,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_64K"                    ,	34,	1,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	8,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	2,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	197,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PCTL_DAT"                    ,	0,	4,	198,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CMD"                    ,	4,	4,	198,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CLK"                    ,	8,	4,	198,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	198,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	198,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CMD"                    ,	20,	4,	198,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CLK"                    ,	24,	4,	198,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	198,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	198,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	199,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	199,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	199,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	11,	1,	199,	"R/W",	0,	0,	1ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	199,	"R/W",	0,	1,	0ull,	0},
+	{"PLL_BYPASS"                  ,	16,	1,	199,	"R/W",	0,	0,	1ull,	1ull},
+	{"PLL_DIV2"                    ,	17,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	199,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	199,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	199,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	199,	"RAZ",	1,	1,	0,	0},
+	{"DATA_LAYOUT"                 ,	0,	2,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	200,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	201,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	202,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	202,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	203,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	203,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	203,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	203,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	203,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	203,	"R/W",	0,	0,	2ull,	2ull},
+	{"SILO_HC"                     ,	21,	1,	203,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	203,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	203,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	203,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	203,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	5,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	5,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	5,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	204,	"RAZ",	1,	1,	0,	0},
+	{"MRDSYN0"                     ,	0,	8,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	205,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	206,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	208,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	209,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	209,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	209,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	209,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	209,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	209,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	209,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	209,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	209,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	209,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	209,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	210,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	210,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	210,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	210,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	210,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	210,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	210,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	210,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMP_BYPASS"                 ,	31,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	210,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	211,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	212,	"RAZ",	1,	1,	0,	0},
+	{"BWCTL"                       ,	0,	4,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWUPD"                       ,	4,	1,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	213,	"RAZ",	1,	1,	0,	0},
+	{"RODT_LO0"                    ,	0,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	214,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	214,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	215,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	215,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	215,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	215,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	215,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WODT_D2_R0"                  ,	0,	8,	216,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	8,	8,	216,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	16,	8,	216,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	24,	8,	216,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	216,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NCBI"                        ,	0,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_1"                      ,	3,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	217,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	218,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	219,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	219,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	219,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	220,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	220,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	220,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	221,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	221,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	221,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	221,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	221,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	222,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	223,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	223,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	223,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	223,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_63"              ,	37,	27,	223,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	224,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	224,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	224,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	224,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	225,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	225,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	225,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	225,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	226,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	226,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	227,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	227,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	1,	228,	"RO",	1,	1,	0,	0},
+	{"RESERVED_1_11"               ,	1,	11,	228,	"RAZ",	1,	1,	0,	0},
+	{"PLL_OFF"                     ,	12,	4,	228,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	228,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	228,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	228,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	228,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	228,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	228,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	228,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	229,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	229,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	229,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	229,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	229,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	229,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_30"              ,	29,	2,	229,	"RAZ",	1,	1,	0,	0},
+	{"PLL_DIV4"                    ,	31,	1,	229,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	229,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	230,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	230,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	231,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	231,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	231,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	231,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	232,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	232,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	233,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	233,	"RAZ",	1,	1,	0,	0},
+	{"KEY"                         ,	0,	24,	234,	"R/W",	0,	0,	0ull,	5071723ull},
+	{"RESERVED_24_63"              ,	24,	40,	234,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	10,	235,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	235,	"RAZ",	1,	1,	0,	0},
+	{"BW_CTL"                      ,	0,	5,	236,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SETTING"                     ,	0,	17,	237,	"RO",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	237,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_INT"                      ,	0,	1,	238,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	238,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	238,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	238,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	238,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	238,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	238,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	238,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	238,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	238,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	238,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	238,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	238,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	239,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	239,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	239,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	239,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	239,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	239,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	239,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	239,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	239,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	239,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	239,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	239,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	240,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	240,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	240,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	241,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	241,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	241,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	242,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	242,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	243,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	243,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	244,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	244,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	245,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	245,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	245,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	245,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	245,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	245,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	245,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	246,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	246,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	247,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	247,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	248,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	248,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	248,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	248,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	249,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	249,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	249,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	249,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	249,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	249,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	249,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	249,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	250,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	250,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	250,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	250,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	250,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	250,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	250,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	250,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	250,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	251,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	251,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	251,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	251,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	251,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	251,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	251,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	252,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	252,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	252,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	252,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	252,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	252,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	252,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	252,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	252,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	253,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	253,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	254,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	254,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	255,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	255,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	255,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	255,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	256,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	257,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	257,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	258,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	258,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	259,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	259,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	259,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	259,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	260,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	260,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	261,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	261,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	262,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	262,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	263,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	263,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	264,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	264,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	265,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	265,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	266,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	266,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	266,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	266,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	266,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	266,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLELO"                      ,	1,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_CONT"                    ,	2,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIREOR"                      ,	3,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	4,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_ENA"                     ,	5,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA"                       ,	6,	1,	267,	"R/W",	0,	0,	0ull,	1ull},
+	{"CSHI"                        ,	7,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLECLKS"                    ,	8,	2,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRITX"                       ,	10,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSLATE"                      ,	11,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	267,	"RAZ",	1,	1,	0,	0},
+	{"CLKDIV"                      ,	16,	13,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	267,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	8,	268,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	268,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	269,	"RAZ",	1,	1,	0,	0},
+	{"RXNUM"                       ,	8,	5,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	269,	"RAZ",	1,	1,	0,	0},
+	{"TOTNUM"                      ,	0,	5,	270,	"WO",	1,	0,	0,	2ull},
+	{"RESERVED_5_7"                ,	5,	3,	270,	"RAZ",	1,	1,	0,	0},
+	{"TXNUM"                       ,	8,	5,	270,	"WO",	1,	0,	0,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	270,	"RAZ",	1,	1,	0,	0},
+	{"LEAVECS"                     ,	16,	1,	270,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	270,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	271,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	271,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	272,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	272,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	273,	"RAZ",	1,	1,	0,	0},
+	{"POF0_BS"                     ,	8,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	273,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	274,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	274,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	274,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	275,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	275,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	275,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_43_45"              ,	43,	3,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INS0_ENB"                    ,	46,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_47_49"              ,	47,	3,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT0_ENB"                    ,	50,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_51_53"              ,	51,	3,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIS_PNIW"                    ,	54,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	275,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	275,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	276,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	276,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	277,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	277,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	277,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	277,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	277,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	277,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	277,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	277,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	277,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	277,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	277,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	277,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	278,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	279,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	279,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	280,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	281,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	281,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	281,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	282,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	283,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	284,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	284,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	284,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	284,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	284,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	284,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_6"                ,	4,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_10"               ,	8,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_14"              ,	12,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_18"              ,	16,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_22"              ,	20,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_24_26"              ,	24,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_30"              ,	28,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_34"              ,	32,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_36_38"              ,	36,	3,	285,	"RAZ",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_S_E"                     ,	42,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_A_F"                     ,	43,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_S_E"                     ,	44,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_A_F"                     ,	45,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_S_E"                      ,	46,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_A_F"                      ,	47,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_S_E"                      ,	48,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_A_F"                      ,	49,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_S_E"                     ,	50,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_A_F"                     ,	51,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_S_E"                     ,	52,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_A_F"                     ,	53,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RWX_S_E"                     ,	54,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDX_S_E"                     ,	55,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_E"                     ,	56,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_F"                     ,	57,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_E"                     ,	58,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_F"                     ,	59,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_S_E"                      ,	60,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_A_F"                      ,	61,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	285,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	286,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_6"                ,	4,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_10"               ,	8,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_22"              ,	20,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_26"              ,	24,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_30"              ,	28,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_34"              ,	32,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_38"              ,	36,	3,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_S_E"                     ,	42,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_A_F"                     ,	43,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_S_E"                     ,	44,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_A_F"                     ,	45,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_S_E"                      ,	46,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_A_F"                      ,	47,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_S_E"                      ,	48,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_A_F"                      ,	49,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_S_E"                     ,	50,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_A_F"                     ,	51,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_S_E"                     ,	52,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_A_F"                     ,	53,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RWX_S_E"                     ,	54,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDX_S_E"                     ,	55,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_E"                     ,	56,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_F"                     ,	57,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_E"                     ,	58,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_F"                     ,	59,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_S_E"                      ,	60,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_A_F"                      ,	61,	1,	286,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	286,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	287,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	287,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	288,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	288,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	289,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	289,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	289,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	289,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	289,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	289,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	289,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	36,	1,	289,	"R/W",	0,	1,	0ull,	0},
+	{"SHORTL"                      ,	37,	1,	289,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	289,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	290,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	291,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	291,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	292,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	292,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_15"               ,	4,	12,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPTR_O0"                     ,	16,	1,	292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_23"              ,	17,	7,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	292,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_25_27"              ,	25,	3,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_RO"                       ,	28,	1,	292,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	292,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_43"              ,	32,	12,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_BMODE"                    ,	44,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_45_63"              ,	45,	19,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NADDR"                       ,	0,	61,	293,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	293,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	293,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	294,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	295,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	296,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	297,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	297,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	297,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	298,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	298,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	299,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	299,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	300,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	300,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	300,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	300,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	300,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	301,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	301,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_8"                      ,	8,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_14"                     ,	14,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_15"                     ,	15,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_21"                     ,	21,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_24"                     ,	24,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_25"                     ,	25,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_26"                     ,	26,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_27"                     ,	27,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_28"                     ,	28,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_29"                     ,	29,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_31"                     ,	31,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	302,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	32,	303,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	303,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	304,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	304,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	305,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	305,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	305,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	306,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	306,	"RO",	0,	0,	48ull,	48ull},
+	{"ISAE"                        ,	0,	1,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	307,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	307,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	307,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	307,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	307,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	307,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	307,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	307,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	307,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	307,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	307,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	307,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	307,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	307,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	308,	"RO",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	8,	24,	308,	"RO",	0,	0,	733184ull,	733184ull},
+	{"CLS"                         ,	0,	8,	309,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	309,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	309,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	310,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	310,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	310,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	310,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	310,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	311,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	312,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	312,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	312,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	312,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	312,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	313,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	314,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	314,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	315,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	315,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	316,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	317,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	317,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	318,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	318,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	318,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	319,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	319,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	320,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	320,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	320,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	320,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	321,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	321,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	321,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	321,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	322,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	323,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	324,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	324,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	324,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	324,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	324,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	325,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	326,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	327,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	327,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	327,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	327,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	327,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	328,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	328,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	328,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	328,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	328,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	329,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	329,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	329,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	329,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	329,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	329,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	329,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	329,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	329,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	329,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	329,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	329,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	329,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	330,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	330,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	330,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	330,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	331,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	331,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	331,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	332,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	332,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	332,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	332,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	332,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	333,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	333,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	334,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	335,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	335,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	336,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	336,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	336,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	336,	"RO",	0,	1,	0ull,	0},
+	{"AP_PCIX"                     ,	13,	1,	336,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_14"              ,	14,	1,	336,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	336,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	336,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	336,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	336,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	336,	"RO",	0,	0,	1ull,	1ull},
+	{"BB0"                         ,	20,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1"                         ,	21,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_ES"                       ,	22,	2,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_CA"                       ,	24,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_SIZ"                     ,	25,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_HOLE"                    ,	26,	3,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	336,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	337,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	337,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	338,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	339,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	340,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_20"              ,	18,	3,	342,	"RAZ",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_24"              ,	22,	3,	342,	"RAZ",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	342,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_20"              ,	18,	3,	343,	"RAZ",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_24"              ,	22,	3,	343,	"RAZ",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	343,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	344,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_20"              ,	18,	3,	344,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_24"              ,	22,	3,	344,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	344,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_20"              ,	18,	3,	345,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_24"              ,	22,	3,	345,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	345,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	346,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	346,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	347,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	347,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	349,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	350,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	351,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	351,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	351,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	352,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	352,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	352,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	353,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	353,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	353,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	354,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	354,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	354,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	355,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	355,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	356,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	356,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	357,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	2,	46,	357,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	357,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	357,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	358,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	359,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	359,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	359,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	359,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	360,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	361,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	361,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	362,	"R/W",	0,	0,	0ull,	8ull},
+	{"FETCHSIZ"                    ,	4,	4,	362,	"R/W",	0,	0,	0ull,	7ull},
+	{"TXRD"                        ,	8,	10,	362,	"R/W",	0,	0,	0ull,	1ull},
+	{"USELDT"                      ,	18,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	362,	"RAZ",	1,	1,	0,	0},
+	{"RXST"                        ,	20,	10,	362,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_30_31"              ,	30,	2,	362,	"RAZ",	1,	1,	0,	0},
+	{"TXSLOTS"                     ,	32,	10,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_43"              ,	42,	2,	362,	"RAZ",	1,	1,	0,	0},
+	{"RXSLOTS"                     ,	44,	10,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_62"              ,	54,	9,	362,	"RAZ",	1,	1,	0,	0},
+	{"RDPEND"                      ,	63,	1,	362,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYNCMISSED"                 ,	0,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXWRAP"                      ,	2,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXST"                        ,	3,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXWRAP"                      ,	4,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRD"                        ,	5,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXEMPTY"                     ,	6,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXOVF"                       ,	7,	1,	363,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	363,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCMISSED"                 ,	0,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXWRAP"                      ,	2,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXST"                        ,	3,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXWRAP"                      ,	4,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXRD"                        ,	5,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXEMPTY"                     ,	6,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXOVF"                       ,	7,	1,	364,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	364,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	365,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	365,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	366,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	366,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	367,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	368,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	369,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	370,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	371,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	372,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	373,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	374,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	375,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	375,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	375,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"USECLK1"                     ,	1,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	2,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	376,	"RAZ",	1,	1,	0,	0},
+	{"SAMPPT"                      ,	32,	16,	376,	"R/W",	0,	1,	0ull,	0},
+	{"DRVTIM"                      ,	48,	16,	376,	"R/W",	0,	1,	0ull,	0},
+	{"DEBUGINFO"                   ,	0,	64,	377,	"RO",	1,	1,	0,	0},
+	{"FRAM"                        ,	0,	3,	378,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	378,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	378,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	379,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	379,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	380,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	381,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	382,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	383,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	384,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	385,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	386,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	387,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	388,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	388,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	388,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCPOL"                    ,	1,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCLKPOL"                     ,	2,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITLEN"                      ,	3,	2,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRABIT"                    ,	5,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUMSLOTS"                    ,	6,	10,	389,	"R/W",	0,	1,	0ull,	0},
+	{"FSYNCLOC"                    ,	16,	5,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCLEN"                    ,	21,	5,	389,	"R/W",	0,	0,	0ull,	2ull},
+	{"RESERVED_26_31"              ,	26,	6,	389,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCSAMP"                   ,	32,	16,	389,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_62"              ,	48,	15,	389,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCGOOD"                   ,	63,	1,	389,	"RO",	0,	0,	0ull,	1ull},
+	{"DEBUGINFO"                   ,	0,	64,	390,	"RO",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	391,	"R/W",	0,	1,	0ull,	0},
+	{"NUMSAMP"                     ,	32,	16,	391,	"R/W",	0,	1,	0ull,	0},
+	{"DELTASAMP"                   ,	48,	16,	391,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	392,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	393,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	393,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	393,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	393,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	394,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	394,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	394,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	394,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	395,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	395,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	395,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKTDRP"                      ,	0,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	396,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	397,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	397,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	398,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	398,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	399,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	399,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	399,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	399,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	399,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	400,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	400,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	401,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	402,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	2,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	403,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	403,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	403,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	403,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	404,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	405,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	406,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	406,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	407,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	407,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	408,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	408,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	409,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	409,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	410,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	410,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	411,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	411,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	412,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	412,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	413,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	413,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	414,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	414,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	415,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	416,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	417,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	417,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	418,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	418,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	419,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	419,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	420,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	421,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	422,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	422,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	423,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	423,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	423,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	424,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	424,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	425,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	425,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	426,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	426,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	426,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	426,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	427,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	427,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	427,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	427,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	427,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	428,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	428,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	428,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	428,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	429,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	429,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	429,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	429,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	429,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	430,	"RO",	1,	0,	0,	0ull},
+	{"WIDX2"                       ,	0,	17,	431,	"RO",	1,	0,	0,	0ull},
+	{"RIDX2"                       ,	17,	17,	431,	"RO",	1,	0,	0,	0ull},
+	{"WIDX"                        ,	34,	17,	431,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	431,	"RAZ",	1,	0,	0,	0ull},
+	{"RIDX"                        ,	0,	17,	432,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	432,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	433,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	433,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	433,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	433,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	433,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	434,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	434,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	434,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	434,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	434,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	435,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	4,	436,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	4,	2,	436,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	6,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	7,	7,	436,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	3,	436,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	17,	5,	436,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	22,	3,	436,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	26,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	436,	"RAZ",	1,	0,	0,	0ull},
+	{"CBUF_FRE"                    ,	28,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"XFER_DWR"                    ,	29,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"XFER_WOR"                    ,	30,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	31,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	32,	16,	436,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CNT"                    ,	48,	13,	436,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_LEN"                    ,	61,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_SOP"                    ,	62,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	63,	1,	436,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	0,	2,	437,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_UID"                    ,	2,	1,	437,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CHK"                    ,	3,	1,	437,	"RO",	1,	0,	0,	0ull},
+	{"WORK_MIN"                    ,	4,	3,	437,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	7,	1,	437,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFM"                    ,	8,	3,	437,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	437,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	438,	"RO",	1,	0,	0,	0ull},
+	{"START"                       ,	16,	33,	438,	"RO",	1,	0,	0,	0ull},
+	{"DWB"                         ,	49,	9,	438,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	438,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	439,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	439,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	439,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	439,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	439,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	439,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	440,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	440,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	440,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	440,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	440,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	440,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	441,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	441,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	441,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	441,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	441,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	441,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	441,	"WR0",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	441,	"WR0",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	441,	"WR0",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	442,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	442,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	442,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"PSB"                         ,	0,	7,	443,	"RO",	1,	0,	0,	0ull},
+	{"PDB"                         ,	7,	4,	443,	"RO",	1,	0,	0,	0ull},
+	{"QCB"                         ,	11,	2,	443,	"RO",	1,	0,	0,	0ull},
+	{"QSB"                         ,	13,	2,	443,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	15,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"CRC"                         ,	16,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"OUT"                         ,	17,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	18,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"WIF"                         ,	19,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"RIF"                         ,	20,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	21,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"PSB2"                        ,	22,	5,	443,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	443,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	444,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	444,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	17,	445,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	445,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	446,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	447,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	447,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	448,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	449,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	449,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	449,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	450,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	451,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR"                         ,	0,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	2,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	3,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	4,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	5,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT0"                        ,	6,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT1"                        ,	7,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	8,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	452,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	452,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	453,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	453,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	454,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	454,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	454,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	454,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	454,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	454,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	454,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	454,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	454,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	454,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	454,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	455,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	455,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	456,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	456,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	457,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	457,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	7,	458,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	458,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	459,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	459,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	460,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"RESERVED_16_63"              ,	16,	48,	460,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	461,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	461,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	461,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	461,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	461,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	6,	462,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_11"               ,	6,	6,	462,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	6,	462,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_18_23"              ,	18,	6,	462,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	7,	462,	"RO",	0,	1,	58ull,	0},
+	{"RESERVED_31_35"              ,	31,	5,	462,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	7,	462,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_43_47"              ,	43,	5,	462,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	7,	462,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_55_63"              ,	55,	9,	462,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	463,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	463,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	464,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	464,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	465,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	465,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	466,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	466,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	466,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	7,	467,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_11"               ,	7,	5,	467,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	7,	467,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_19_23"              ,	19,	5,	467,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	467,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	467,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	468,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	468,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	468,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	468,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	468,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	6,	469,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_11"               ,	6,	6,	469,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	6,	469,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_23"              ,	18,	6,	469,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	469,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	469,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	469,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	470,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	470,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	471,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	472,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	473,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	473,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	473,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	473,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	473,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	473,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	474,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	474,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	1,	474,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	474,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	475,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	475,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	476,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	476,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	476,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	476,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	477,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	477,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	477,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	477,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	478,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	478,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	478,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	479,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	479,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	479,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	480,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	480,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	480,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	482,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	483,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	483,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	483,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	484,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	484,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	485,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	485,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	486,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	487,	"RAZ",	1,	0,	0,	0ull},
+	{"INEPINT"                     ,	0,	16,	488,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	488,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	489,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	489,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	490,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	490,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	490,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	490,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	491,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	491,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	491,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	491,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	491,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	491,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	491,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	492,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	492,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	492,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	492,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	492,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	492,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	492,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	492,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	492,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	493,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	494,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	495,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	496,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	496,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	496,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	496,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	496,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	496,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	496,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	496,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	496,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	497,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	498,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	499,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	500,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	501,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	501,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	502,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	503,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	505,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	506,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	506,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	506,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	506,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	506,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	507,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	508,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	508,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	508,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	508,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	508,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	508,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	508,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	508,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	508,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	508,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	508,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	508,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	508,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	508,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	509,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	509,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	509,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	509,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	509,	"RO",	0,	0,	1ull,	1ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	509,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	509,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	510,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	510,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	510,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"AVALIDFLTR"                  ,	22,	1,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"BVALIDFLTR"                  ,	23,	1,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"SESSENDFLTR"                 ,	24,	1,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_25_31"              ,	25,	7,	510,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	511,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	512,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	512,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	512,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	513,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	513,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	514,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	514,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	514,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	514,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	515,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	515,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	515,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	515,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	515,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	515,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	515,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	516,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	516,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	516,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	516,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	516,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	516,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	516,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	516,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	516,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	516,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	517,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	517,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	517,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	518,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	518,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	519,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	520,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	521,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	522,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	522,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	522,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	522,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	522,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	523,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	524,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	524,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	524,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	524,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	524,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	524,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	524,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	524,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	524,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	524,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	525,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	525,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	526,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	527,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	528,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	529,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	529,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	530,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	531,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	533,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	533,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	534,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	535,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	535,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	535,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	536,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	536,	"R/W",	0,	0,	1824ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	539,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	540,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	541,	"R/W",	0,	0,	4ull,	4ull},
+	{"HRST"                        ,	3,	1,	541,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	541,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	541,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	541,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	541,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	541,	"R/W",	0,	0,	2ull,	2ull},
+	{"P_COM_ON"                    ,	13,	1,	541,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_XENBN"                     ,	14,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_RCLK"                      ,	15,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_X_ON"                      ,	16,	1,	541,	"R/W",	0,	0,	1ull,	1ull},
+	{"HCLK_RST"                    ,	17,	1,	541,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_18_63"              ,	18,	46,	541,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	542,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	542,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	543,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	544,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	544,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	545,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	545,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	546,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	546,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	547,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	547,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	548,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	548,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	549,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	549,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	550,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	550,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	551,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	551,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	552,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	552,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	553,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	553,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	554,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	554,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	555,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	555,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	556,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	556,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	557,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	557,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	558,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	558,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	559,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	559,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	559,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"N2U_PF"                      ,	26,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"N2U_PE"                      ,	27,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_D_PE"                    ,	28,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_D_PF"                    ,	29,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_C_PF"                    ,	30,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"U2N_C_PE"                    ,	31,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	560,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"N2U_PF"                      ,	26,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"N2U_PE"                      ,	27,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_D_PE"                    ,	28,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_D_PF"                    ,	29,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_C_PF"                    ,	30,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"U2N_C_PE"                    ,	31,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	561,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	561,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	561,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"TUNING"                      ,	19,	4,	562,	"R/W",	0,	0,	9ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	562,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	562,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	562,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	562,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	562,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	562,	"RAZ",	1,	1,	0,	0},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	4,	0},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	4,	4},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	3,	8},
+	{"cvmx_asx#_rld_bypass"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	2,	11},
+	{"cvmx_asx#_rld_bypass_setting",	CVMX_CSR_DB_TYPE_RSL,	64,	8,	2,	13},
+	{"cvmx_asx#_rld_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	3,	15},
+	{"cvmx_asx#_rld_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	3,	18},
+	{"cvmx_asx#_rld_fcram_mode"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	21},
+	{"cvmx_asx#_rld_nctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	23},
+	{"cvmx_asx#_rld_nctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	25},
+	{"cvmx_asx#_rld_pctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	27},
+	{"cvmx_asx#_rld_pctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	29},
+	{"cvmx_asx#_rld_setting"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	31},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	33},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	35},
+	{"cvmx_asx#_rx_wol"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	3,	37},
+	{"cvmx_asx#_rx_wol_msk"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	1,	40},
+	{"cvmx_asx#_rx_wol_powok"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	2,	41},
+	{"cvmx_asx#_rx_wol_sig"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	43},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	45},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	3,	47},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	50},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	2,	52},
+	{"cvmx_asx0_dbg_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	3,	54},
+	{"cvmx_asx0_dbg_data_enable"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	2,	57},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	66,	2,	59},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	67,	2,	61},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	68,	2,	63},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	69,	2,	65},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	70,	15,	67},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	103,	2,	82},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	136,	15,	84},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	169,	2,	99},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	170,	2,	101},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	186,	2,	103},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	202,	2,	105},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	203,	2,	107},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	204,	2,	109},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	205,	1,	111},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	221,	3,	112},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	222,	2,	115},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	223,	4,	117},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	2,	121},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	225,	3,	123},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	229,	7,	126},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	245,	7,	133},
+	{"cvmx_dfa_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	246,	3,	140},
+	{"cvmx_dfa_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	247,	10,	143},
+	{"cvmx_dfa_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	248,	5,	153},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	249,	2,	158},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	250,	4,	160},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	251,	3,	164},
+	{"cvmx_dfa_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	21,	167},
+	{"cvmx_dfa_memcfg0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	253,	17,	188},
+	{"cvmx_dfa_memcfg1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	254,	11,	205},
+	{"cvmx_dfa_memcfg2"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	255,	8,	216},
+	{"cvmx_dfa_memfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	256,	6,	224},
+	{"cvmx_dfa_memfcr"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	257,	6,	230},
+	{"cvmx_dfa_memrld"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	258,	2,	236},
+	{"cvmx_dfa_ncbctl"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	259,	8,	238},
+	{"cvmx_dfa_sbd_dbg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	260,	1,	246},
+	{"cvmx_dfa_sbd_dbg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	261,	1,	247},
+	{"cvmx_dfa_sbd_dbg2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	262,	1,	248},
+	{"cvmx_dfa_sbd_dbg3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	263,	1,	249},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	264,	6,	250},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	265,	7,	256},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	266,	3,	263},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	273,	2,	266},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	280,	3,	268},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	281,	2,	271},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	282,	29,	273},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	283,	29,	302},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	284,	2,	331},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	292,	2,	333},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	300,	3,	335},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	301,	3,	338},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	302,	2,	341},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	303,	2,	343},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	304,	8,	345},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	306,	2,	353},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	308,	3,	355},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	310,	2,	358},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	312,	5,	360},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	320,	1,	365},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	328,	1,	366},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	336,	1,	367},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	344,	1,	368},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	352,	1,	369},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	360,	1,	370},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	368,	2,	371},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	376,	4,	373},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	384,	2,	377},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	392,	11,	379},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	400,	10,	390},
+	{"cvmx_gmx#_rx#_frm_max"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	2,	400},
+	{"cvmx_gmx#_rx#_frm_min"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	2,	402},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	424,	2,	404},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	432,	20,	406},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	440,	20,	426},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	448,	2,	446},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	456,	4,	448},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	2,	452},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	472,	2,	454},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	480,	2,	456},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	488,	2,	458},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	496,	2,	460},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	504,	2,	462},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	512,	2,	464},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	520,	2,	466},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	528,	2,	468},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	536,	2,	470},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	544,	4,	472},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	552,	2,	476},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	560,	2,	478},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	568,	2,	480},
+	{"cvmx_gmx#_rx_pass_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	576,	2,	482},
+	{"cvmx_gmx#_rx_pass_map#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	578,	2,	484},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	610,	3,	486},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	612,	2,	489},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	614,	2,	491},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	622,	3,	493},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	624,	5,	496},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	632,	2,	501},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	640,	2,	503},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	648,	3,	505},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	656,	2,	508},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	664,	2,	510},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	672,	2,	512},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	680,	2,	514},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	688,	2,	516},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	696,	2,	518},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	704,	2,	520},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	712,	2,	522},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	720,	2,	524},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	728,	2,	526},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	736,	2,	528},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	744,	2,	530},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	752,	2,	532},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	760,	2,	534},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	768,	2,	536},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	776,	2,	538},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	784,	2,	540},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	792,	2,	542},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	800,	2,	544},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	808,	2,	546},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	2,	548},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	2,	550},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	814,	3,	552},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	816,	8,	555},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	818,	8,	563},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	820,	2,	571},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	822,	2,	573},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	824,	4,	575},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	826,	2,	579},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	828,	2,	581},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	830,	2,	583},
+	{"cvmx_gmx#_tx_spi_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	832,	3,	585},
+	{"cvmx_gmx#_tx_spi_drain"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	834,	2,	588},
+	{"cvmx_gmx#_tx_spi_max"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	836,	3,	590},
+	{"cvmx_gmx#_tx_spi_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	838,	2,	593},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	840,	7,	595},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	856,	2,	602},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	857,	2,	604},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	858,	2,	606},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	859,	2,	608},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	860,	19,	610},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	861,	6,	629},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	862,	3,	635},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	863,	3,	638},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	864,	3,	641},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	865,	5,	644},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	866,	5,	649},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	867,	1,	654},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	868,	1,	655},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	869,	5,	656},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	870,	5,	661},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	871,	3,	666},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	872,	3,	669},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	873,	3,	672},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	874,	5,	675},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	875,	5,	680},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	876,	1,	685},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	877,	1,	686},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	878,	3,	687},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	879,	3,	690},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	880,	3,	693},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	881,	2,	696},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	882,	2,	698},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	883,	2,	700},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	884,	2,	702},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	885,	17,	704},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	886,	2,	721},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	887,	1,	723},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	888,	10,	724},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	889,	11,	734},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	890,	11,	745},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	891,	2,	756},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	892,	2,	758},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	893,	2,	760},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	894,	3,	762},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	930,	2,	765},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	966,	6,	767},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	967,	5,	773},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	968,	6,	778},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	969,	7,	784},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	970,	2,	791},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	978,	2,	793},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	979,	3,	795},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	980,	5,	798},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	988,	3,	803},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	989,	2,	806},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	990,	2,	808},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	991,	2,	810},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	992,	4,	812},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	993,	3,	816},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	994,	5,	819},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	995,	5,	824},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	996,	5,	829},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	997,	5,	834},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	8,	839},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	999,	9,	847},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1000,	8,	856},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1001,	5,	864},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1002,	4,	869},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	2,	873},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1004,	14,	875},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1005,	19,	889},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	3,	908},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1007,	3,	911},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1008,	2,	914},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1012,	17,	916},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1013,	5,	933},
+	{"cvmx_l2c_spar1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1014,	5,	938},
+	{"cvmx_l2c_spar2"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1015,	5,	943},
+	{"cvmx_l2c_spar3"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1016,	5,	948},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1017,	2,	953},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1018,	3,	955},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	2,	958},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1020,	2,	960},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1021,	2,	962},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1022,	7,	964},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1023,	4,	971},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1024,	3,	975},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1025,	3,	978},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1026,	2,	981},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	2,	983},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1028,	2,	985},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1029,	4,	987},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1030,	13,	991},
+	{"cvmx_led_blink"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1031,	2,	1004},
+	{"cvmx_led_clk_phase"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1032,	2,	1006},
+	{"cvmx_led_cylon"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1033,	2,	1008},
+	{"cvmx_led_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1034,	2,	1010},
+	{"cvmx_led_en"                 ,	CVMX_CSR_DB_TYPE_RSL,	64,	1035,	2,	1012},
+	{"cvmx_led_polarity"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1036,	2,	1014},
+	{"cvmx_led_prt"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1037,	2,	1016},
+	{"cvmx_led_prt_fmt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1038,	2,	1018},
+	{"cvmx_led_prt_status#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1039,	2,	1020},
+	{"cvmx_led_udd_cnt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1047,	2,	1022},
+	{"cvmx_led_udd_dat#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1049,	2,	1024},
+	{"cvmx_led_udd_dat_clr#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1051,	2,	1026},
+	{"cvmx_led_udd_dat_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1053,	2,	1028},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1055,	9,	1030},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1056,	19,	1039},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1057,	2,	1058},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1058,	2,	1060},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	18,	1062},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1060,	6,	1080},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1061,	5,	1086},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1062,	6,	1091},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1063,	2,	1097},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1064,	2,	1099},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1065,	14,	1101},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1066,	9,	1115},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1067,	2,	1124},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1068,	2,	1126},
+	{"cvmx_lmc#_pll_bwctl"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1069,	3,	1128},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1070,	9,	1131},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1071,	9,	1140},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1072,	4,	1149},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1073,	3,	1153},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1074,	3,	1156},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1075,	3,	1159},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1076,	5,	1162},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1078,	1,	1167},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1079,	6,	1168},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1087,	13,	1174},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1095,	4,	1187},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1096,	2,	1191},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1097,	2,	1193},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1098,	8,	1195},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1099,	8,	1203},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1100,	2,	1211},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1101,	8,	1213},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1102,	4,	1221},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1103,	2,	1225},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1104,	2,	1227},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1105,	13,	1229},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1106,	12,	1242},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1107,	3,	1254},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1108,	3,	1257},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1109,	2,	1260},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1111,	2,	1262},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1113,	2,	1264},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1115,	7,	1266},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1117,	2,	1273},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1119,	7,	1275},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1121,	4,	1282},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1123,	8,	1286},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1125,	9,	1294},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1127,	7,	1303},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1129,	9,	1310},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1131,	2,	1319},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1133,	2,	1321},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1135,	4,	1323},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1137,	2,	1327},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1139,	2,	1329},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1141,	2,	1331},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1143,	4,	1333},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1145,	2,	1337},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1147,	2,	1339},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1149,	2,	1341},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1151,	2,	1343},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1153,	2,	1345},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1155,	2,	1347},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1157,	6,	1349},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1159,	2,	1355},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1163,	2,	1357},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1167,	21,	1359},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1168,	3,	1380},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1172,	21,	1383},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1173,	2,	1404},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1174,	13,	1406},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1175,	3,	1419},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1176,	3,	1422},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1177,	3,	1425},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1178,	3,	1428},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1179,	2,	1431},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1180,	2,	1433},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1181,	10,	1435},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1182,	63,	1445},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1183,	63,	1508},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1184,	2,	1571},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1185,	2,	1573},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1186,	10,	1575},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1190,	1,	1585},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1191,	2,	1586},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1195,	39,	1588},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1196,	3,	1627},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1200,	2,	1630},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1204,	3,	1632},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1208,	3,	1635},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1212,	3,	1638},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1213,	4,	1641},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1214,	2,	1645},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1215,	13,	1647},
+	{"cvmx_npi_port33_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1216,	13,	1660},
+	{"cvmx_npi_port34_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1217,	13,	1673},
+	{"cvmx_npi_port35_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1218,	13,	1686},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1219,	3,	1699},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1220,	33,	1702},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1221,	2,	1735},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1225,	2,	1737},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1226,	5,	1739},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1258,	2,	1744},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1259,	24,	1746},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1260,	2,	1770},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1261,	7,	1772},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1262,	5,	1779},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1263,	1,	1784},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1264,	5,	1785},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1265,	1,	1790},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1266,	4,	1791},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1267,	2,	1795},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1268,	1,	1797},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1269,	2,	1798},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1270,	4,	1800},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1271,	2,	1804},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1272,	4,	1806},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1273,	16,	1810},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1274,	1,	1826},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1275,	1,	1827},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1276,	18,	1828},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1277,	1,	1846},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1278,	1,	1847},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1279,	7,	1848},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1280,	7,	1855},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1281,	13,	1862},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1282,	10,	1875},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1283,	10,	1885},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1284,	7,	1895},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1285,	2,	1902},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1286,	1,	1904},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1287,	2,	1905},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1288,	22,	1907},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	1289,	2,	1929},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	1293,	1,	1931},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1295,	1,	1932},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	1297,	1,	1933},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1299,	1,	1934},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1303,	35,	1935},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1304,	35,	1970},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1305,	35,	2005},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1306,	35,	2040},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	1307,	2,	2075},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1308,	2,	2077},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	1312,	1,	2079},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	1316,	1,	2080},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	1320,	1,	2081},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1324,	3,	2082},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1325,	3,	2085},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1326,	3,	2088},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1327,	3,	2091},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1328,	2,	2094},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1329,	2,	2096},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1330,	4,	2098},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1331,	1,	2102},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1332,	4,	2103},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1333,	1,	2107},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1334,	2,	2108},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1335,	5,	2110},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1336,	2,	2115},
+	{"cvmx_pip_crc_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1337,	3,	2117},
+	{"cvmx_pip_crc_iv#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1339,	2,	2120},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1341,	4,	2122},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1345,	8,	2126},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1346,	16,	2134},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1347,	10,	2150},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1348,	10,	2160},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1349,	2,	2170},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1350,	18,	2172},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1386,	25,	2190},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1422,	2,	2215},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1486,	2,	2217},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1494,	9,	2219},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1498,	2,	2228},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1499,	2,	2230},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1500,	2,	2232},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1536,	2,	2234},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1572,	2,	2236},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1608,	2,	2238},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1644,	2,	2240},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1680,	2,	2242},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1716,	2,	2244},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1752,	2,	2246},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	2,	2248},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	2,	2250},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1860,	2,	2252},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1861,	2,	2254},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1897,	2,	2256},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1933,	2,	2258},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1969,	2,	2260},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2033,	2,	2262},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2034,	3,	2264},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2035,	3,	2267},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2036,	2,	2270},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2037,	2,	2272},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2038,	4,	2274},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2039,	5,	2278},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2040,	4,	2283},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2041,	5,	2287},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2042,	1,	2292},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2043,	4,	2293},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2044,	2,	2297},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2045,	5,	2299},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2046,	5,	2304},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2047,	1,	2309},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2048,	19,	2310},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2049,	7,	2329},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2050,	4,	2336},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2051,	6,	2340},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2052,	7,	2346},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2053,	9,	2353},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2054,	5,	2362},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2055,	13,	2367},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2056,	4,	2380},
+	{"cvmx_pko_reg_crc_ctl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2057,	3,	2384},
+	{"cvmx_pko_reg_crc_enable"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2059,	2,	2387},
+	{"cvmx_pko_reg_crc_iv#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2060,	2,	2389},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2062,	2,	2391},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2063,	3,	2393},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2064,	5,	2396},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2065,	3,	2401},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2066,	3,	2404},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2067,	2,	2407},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2068,	3,	2409},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2069,	13,	2412},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2070,	2,	2425},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2071,	13,	2427},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2072,	3,	2440},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2073,	2,	2443},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2081,	2,	2445},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2082,	2,	2447},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2083,	2,	2449},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2084,	2,	2451},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2100,	5,	2453},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2108,	8,	2458},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2116,	2,	2466},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2117,	2,	2468},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2118,	2,	2470},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2126,	3,	2472},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2127,	4,	2475},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2143,	5,	2479},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2144,	7,	2484},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2160,	2,	2491},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	3,	2493},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2177,	5,	2496},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	8,	2501},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2179,	6,	2509},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	2,	2515},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2181,	4,	2517},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	4,	2521},
+	{"cvmx_spx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	2,	2525},
+	{"cvmx_spx#_bist_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2185,	4,	2527},
+	{"cvmx_spx#_clk_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2187,	11,	2531},
+	{"cvmx_spx#_clk_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2189,	9,	2542},
+	{"cvmx_spx#_dbg_deskew_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2191,	16,	2551},
+	{"cvmx_spx#_dbg_deskew_state"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2193,	5,	2567},
+	{"cvmx_spx#_drv_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2195,	4,	2572},
+	{"cvmx_spx#_err_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2197,	6,	2576},
+	{"cvmx_spx#_int_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2199,	6,	2582},
+	{"cvmx_spx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2201,	12,	2588},
+	{"cvmx_spx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2203,	14,	2600},
+	{"cvmx_spx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2205,	12,	2614},
+	{"cvmx_spx#_tpa_acc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2207,	2,	2626},
+	{"cvmx_spx#_tpa_max"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2209,	2,	2628},
+	{"cvmx_spx#_tpa_sel"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2211,	2,	2630},
+	{"cvmx_spx#_trn4_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2213,	8,	2632},
+	{"cvmx_spx0_pll_bw_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2215,	2,	2640},
+	{"cvmx_spx0_pll_setting"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2216,	2,	2642},
+	{"cvmx_srx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2217,	5,	2644},
+	{"cvmx_srx#_ign_rx_full"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2219,	2,	2649},
+	{"cvmx_srx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2221,	6,	2651},
+	{"cvmx_srx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2285,	4,	2657},
+	{"cvmx_srx#_sw_tick_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2287,	6,	2661},
+	{"cvmx_srx#_sw_tick_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2289,	1,	2667},
+	{"cvmx_stx#_arb_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2291,	5,	2668},
+	{"cvmx_stx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2293,	2,	2673},
+	{"cvmx_stx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2295,	4,	2675},
+	{"cvmx_stx#_dip_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2297,	3,	2679},
+	{"cvmx_stx#_ign_cal"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2299,	2,	2682},
+	{"cvmx_stx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2301,	9,	2684},
+	{"cvmx_stx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2303,	10,	2693},
+	{"cvmx_stx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2305,	9,	2703},
+	{"cvmx_stx#_min_bst"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2307,	2,	2712},
+	{"cvmx_stx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2309,	6,	2714},
+	{"cvmx_stx#_spi4_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2373,	3,	2720},
+	{"cvmx_stx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	4,	2723},
+	{"cvmx_stx#_stat_bytes_hi"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	2,	2727},
+	{"cvmx_stx#_stat_bytes_lo"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	2,	2729},
+	{"cvmx_stx#_stat_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	3,	2731},
+	{"cvmx_stx#_stat_pkt_xmt"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2383,	2,	2734},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2385,	6,	2736},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2386,	3,	2742},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2387,	5,	2745},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2388,	4,	2750},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2389,	6,	2754},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2390,	4,	2760},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2391,	2,	2764},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2392,	4,	2766},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2393,	2,	2770},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2394,	3,	2772},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2395,	4,	2775},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2396,	12,	2779},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2397,	3,	2791},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2398,	2,	2794},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2399,	2,	2796},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2400,	17,	2798},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2401,	12,	2815},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2402,	6,	2827},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2403,	5,	2833},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2404,	1,	2838},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2405,	2,	2839},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2406,	2,	2841},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2407,	17,	2843},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2408,	12,	2860},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2409,	6,	2872},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2410,	2,	2878},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2411,	2,	2880},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2412,	17,	2882},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2413,	12,	2899},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2414,	6,	2911},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2415,	3,	2917},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2416,	5,	2920},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2417,	3,	2925},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2418,	6,	2928},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	2419,	2,	2934},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	2420,	2,	2936},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2421,	2,	2938},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_FCRAM_MODE"         ,	   0x11800B0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_FCRAM_MODE"         ,	   0x11800B8000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_RX_WOL"                 ,	   0x11800B0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_RX_WOL"                 ,	   0x11800B8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_RX_WOL_MSK"             ,	   0x11800B0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_RX_WOL_MSK"             ,	   0x11800B8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_RX_WOL_POWOK"           ,	   0x11800B0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_RX_WOL_POWOK"           ,	   0x11800B8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_RX_WOL_SIG"             ,	   0x11800B0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX1_RX_WOL_SIG"             ,	   0x11800B8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT20_EN0"               ,	   0x1070000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT21_EN0"               ,	   0x1070000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT22_EN0"               ,	   0x1070000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT20_EN1"               ,	   0x1070000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT21_EN1"               ,	   0x1070000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET10"              ,	   0x1070000000650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET11"              ,	   0x1070000000658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET12"              ,	   0x1070000000660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET13"              ,	   0x1070000000668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET14"              ,	   0x1070000000670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_MBOX_SET15"              ,	   0x1070000000678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG12"                  ,	   0x1070000000560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"DFA_ERR"                     ,	   0x1180030000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"DFA_MEMCFG0"                 ,	   0x1180030000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"DFA_MEMCFG1"                 ,	   0x1180030000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"DFA_MEMCFG2"                 ,	   0x1180030000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"DFA_MEMFADR"                 ,	   0x1180030000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"DFA_MEMFCR"                  ,	   0x1180030000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"DFA_MEMRLD"                  ,	   0x1180030000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"DFA_NCBCTL"                  ,	   0x1180030000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"DFA_SBD_DBG0"                ,	   0x1180030000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX000_FRM_MAX"          ,	   0x1180008000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX001_FRM_MAX"          ,	   0x1180008000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX002_FRM_MAX"          ,	   0x1180008001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX003_FRM_MAX"          ,	   0x1180008001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX000_FRM_MAX"          ,	   0x1180010000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX001_FRM_MAX"          ,	   0x1180010000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX002_FRM_MAX"          ,	   0x1180010001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX003_FRM_MAX"          ,	   0x1180010001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX000_FRM_MIN"          ,	   0x1180008000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_FRM_MIN"          ,	   0x1180008000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_FRM_MIN"          ,	   0x1180008001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX003_FRM_MIN"          ,	   0x1180008001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX000_FRM_MIN"          ,	   0x1180010000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX001_FRM_MIN"          ,	   0x1180010000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX002_FRM_MIN"          ,	   0x1180010001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX003_FRM_MIN"          ,	   0x1180010001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX003_RX_INBND"         ,	   0x1180008001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX000_RX_INBND"         ,	   0x1180010000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX001_RX_INBND"         ,	   0x1180010000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX002_RX_INBND"         ,	   0x1180010001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX003_RX_INBND"         ,	   0x1180010001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP003"         ,	   0x1180008000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP004"         ,	   0x1180008000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP005"         ,	   0x1180008000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP006"         ,	   0x1180008000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP007"         ,	   0x1180008000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP008"         ,	   0x1180008000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP009"         ,	   0x1180008000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP010"         ,	   0x1180008000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP011"         ,	   0x1180008000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP012"         ,	   0x1180008000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP013"         ,	   0x1180008000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP014"         ,	   0x1180008000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP015"         ,	   0x1180008000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP000"         ,	   0x1180010000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP001"         ,	   0x1180010000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP002"         ,	   0x1180010000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP003"         ,	   0x1180010000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP004"         ,	   0x1180010000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP005"         ,	   0x1180010000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP006"         ,	   0x1180010000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP007"         ,	   0x1180010000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP008"         ,	   0x1180010000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP009"         ,	   0x1180010000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP010"         ,	   0x1180010000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP011"         ,	   0x1180010000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP012"         ,	   0x1180010000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	187},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"L2C_SPAR3"                   ,	   0x1180080000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"LMC0_PLL_BWCTL"              ,	   0x1180088000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	326},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	327},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	328},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	329},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	330},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	331},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	332},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	333},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	334},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	345},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	363},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	364},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	365},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	366},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	367},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	368},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	369},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	370},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	371},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	372},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	373},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	394},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	395},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	396},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	397},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	398},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
+	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
+	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
+	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	399},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	400},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	401},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	402},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	403},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	404},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
+	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
+	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
+	{"PCI_PKT_CREDITS3"            ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCI,	32,	405},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_PKTS_SENT2"              ,	              0x60ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_PKTS_SENT3"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	409},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	410},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	411},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	413},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	415},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	416},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	417},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	418},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	419},
+	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"PKO_REG_CRC_CTL0"            ,	   0x1180050000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"PKO_REG_CRC_CTL1"            ,	   0x1180050000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"PKO_REG_CRC_ENABLE"          ,	   0x1180050000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"PKO_REG_CRC_IV0"             ,	   0x1180050000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"PKO_REG_CRC_IV1"             ,	   0x1180050000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	489},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	490},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	491},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	492},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	493},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK12"            ,	   0x1670000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	494},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	495},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	496},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	497},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	498},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	499},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	500},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	502},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	510},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	511},
+	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	512},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	513},
+	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	514},
+	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"SPX1_CLK_STAT"               ,	   0x1180098000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	515},
+	{"SPX0_DBG_DESKEW_CTL"         ,	   0x1180090000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"SPX1_DBG_DESKEW_CTL"         ,	   0x1180098000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	516},
+	{"SPX0_DBG_DESKEW_STATE"       ,	   0x1180090000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"SPX1_DBG_DESKEW_STATE"       ,	   0x1180098000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	517},
+	{"SPX0_DRV_CTL"                ,	   0x1180090000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"SPX1_DRV_CTL"                ,	   0x1180098000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	518},
+	{"SPX0_ERR_CTL"                ,	   0x1180090000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"SPX1_ERR_CTL"                ,	   0x1180098000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	519},
+	{"SPX0_INT_DAT"                ,	   0x1180090000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"SPX1_INT_DAT"                ,	   0x1180098000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"SPX0_INT_MSK"                ,	   0x1180090000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SPX1_INT_MSK"                ,	   0x1180098000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SPX0_INT_REG"                ,	   0x1180090000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"SPX1_INT_REG"                ,	   0x1180098000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"SPX0_INT_SYNC"               ,	   0x1180090000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"SPX1_INT_SYNC"               ,	   0x1180098000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"SPX0_TPA_ACC"                ,	   0x1180090000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"SPX1_TPA_ACC"                ,	   0x1180098000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"SPX0_TPA_MAX"                ,	   0x1180090000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"SPX1_TPA_MAX"                ,	   0x1180098000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"SPX0_TPA_SEL"                ,	   0x1180090000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"SPX1_TPA_SEL"                ,	   0x1180098000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"SPX0_TRN4_CTL"               ,	   0x1180090000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"SPX1_TRN4_CTL"               ,	   0x1180098000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"SPX0_PLL_BW_CTL"             ,	   0x1180090000388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"SPX0_PLL_SETTING"            ,	   0x1180090000380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"SRX0_COM_CTL"                ,	   0x1180090000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"SRX1_COM_CTL"                ,	   0x1180098000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"SRX0_IGN_RX_FULL"            ,	   0x1180090000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"SRX1_IGN_RX_FULL"            ,	   0x1180098000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"SRX0_SPI4_CAL000"            ,	   0x1180090000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL001"            ,	   0x1180090000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL002"            ,	   0x1180090000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL003"            ,	   0x1180090000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL004"            ,	   0x1180090000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL005"            ,	   0x1180090000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL006"            ,	   0x1180090000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL007"            ,	   0x1180090000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL008"            ,	   0x1180090000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL009"            ,	   0x1180090000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL010"            ,	   0x1180090000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL011"            ,	   0x1180090000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL012"            ,	   0x1180090000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL013"            ,	   0x1180090000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL014"            ,	   0x1180090000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL015"            ,	   0x1180090000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL016"            ,	   0x1180090000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL003"            ,	   0x1180098000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL004"            ,	   0x1180098000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL005"            ,	   0x1180098000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL006"            ,	   0x1180098000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL007"            ,	   0x1180098000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL008"            ,	   0x1180098000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL009"            ,	   0x1180098000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL010"            ,	   0x1180098000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL011"            ,	   0x1180098000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL012"            ,	   0x1180098000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL013"            ,	   0x1180098000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL014"            ,	   0x1180098000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL015"            ,	   0x1180098000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL016"            ,	   0x1180098000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"SRX0_SW_TICK_CTL"            ,	   0x1180090000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"SRX1_SW_TICK_CTL"            ,	   0x1180098000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"SRX0_SW_TICK_DAT"            ,	   0x1180090000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"SRX1_SW_TICK_DAT"            ,	   0x1180098000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"STX0_ARB_CTL"                ,	   0x1180090000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"STX1_ARB_CTL"                ,	   0x1180098000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"STX0_BCKPRS_CNT"             ,	   0x1180090000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"STX1_BCKPRS_CNT"             ,	   0x1180098000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"STX0_COM_CTL"                ,	   0x1180090000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"STX1_COM_CTL"                ,	   0x1180098000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"STX0_DIP_CNT"                ,	   0x1180090000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL001"            ,	   0x1180090000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL002"            ,	   0x1180090000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL003"            ,	   0x1180090000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL004"            ,	   0x1180090000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL005"            ,	   0x1180090000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL006"            ,	   0x1180090000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL007"            ,	   0x1180090000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL008"            ,	   0x1180090000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL009"            ,	   0x1180090000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL010"            ,	   0x1180090000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL011"            ,	   0x1180090000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL012"            ,	   0x1180090000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL013"            ,	   0x1180090000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL014"            ,	   0x1180090000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL015"            ,	   0x1180090000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL016"            ,	   0x1180090000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL003"            ,	   0x1180098000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL004"            ,	   0x1180098000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL005"            ,	   0x1180098000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL006"            ,	   0x1180098000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL007"            ,	   0x1180098000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL008"            ,	   0x1180098000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL009"            ,	   0x1180098000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL010"            ,	   0x1180098000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL011"            ,	   0x1180098000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL012"            ,	   0x1180098000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL013"            ,	   0x1180098000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL014"            ,	   0x1180098000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL015"            ,	   0x1180098000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL016"            ,	   0x1180098000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"STX1_SPI4_STAT"              ,	   0x1180098000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"STX0_STAT_BYTES_HI"          ,	   0x1180090000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"STX1_STAT_BYTES_HI"          ,	   0x1180098000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"STX0_STAT_BYTES_LO"          ,	   0x1180090000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"STX1_STAT_BYTES_LO"          ,	   0x1180098000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"STX0_STAT_CTL"               ,	   0x1180090000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"STX1_STAT_CTL"               ,	   0x1180098000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"STX0_STAT_PKT_XMT"           ,	   0x1180090000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"STX1_STAT_PKT_XMT"           ,	   0x1180098000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"OVRFLW"                      ,	0,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPOP"                       ,	4,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPSH"                       ,	8,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	4,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	8,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	1,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_LOOP"                    ,	4,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	1,	3,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	3,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	4,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	5,	"RO",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	4,	5,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	5,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	6,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	1,	7,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	7,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	8,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	8,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	9,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	10,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	11,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	11,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	12,	"RO",	1,	1,	0,	0},
+	{"RESERVED_5_63"               ,	5,	59,	12,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	13,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	13,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	14,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	14,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	15,	"RO",	1,	1,	0,	0},
+	{"STATUS"                      ,	1,	1,	15,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	15,	"RAZ",	1,	1,	0,	0},
+	{"MSK"                         ,	0,	64,	16,	"R/W",	0,	1,	0ull,	0},
+	{"POWEROK"                     ,	0,	1,	17,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	17,	"RAZ",	1,	1,	0,	0},
+	{"SIG"                         ,	0,	32,	18,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	18,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	19,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	19,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	20,	"R/W",	0,	0,	8ull,	8ull},
+	{"PCTL"                        ,	4,	4,	20,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_8_63"               ,	8,	56,	20,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	4,	21,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	21,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	22,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	22,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	23,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	4,	4,	23,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	23,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	24,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	24,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	25,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	25,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	16,	26,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	26,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	16,	27,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	27,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	28,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	28,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	29,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	29,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	29,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	30,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	31,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	32,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	32,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	33,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	33,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	34,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	34,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	16,	35,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	35,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	36,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	36,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	16,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	37,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	38,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	39,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	15,	39,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	39,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	40,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	40,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	41,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	41,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	41,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	42,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	42,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	43,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	43,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	44,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	44,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	45,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	45,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	45,	"RO",	1,	1,	0,	0},
+	{"CCLK_DIV2"                   ,	23,	1,	45,	"RO",	1,	1,	0,	0},
+	{"DCLK_MUL2"                   ,	24,	1,	45,	"RO",	1,	1,	0,	0},
+	{"D_MUL"                       ,	25,	4,	45,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	45,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	16,	46,	"RO",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	16,	16,	46,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	46,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P1_BRF"                      ,	0,	8,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BRF"                      ,	8,	8,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"P1_BWB"                      ,	16,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BWB"                      ,	17,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"CRF"                         ,	18,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"DRF"                         ,	19,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	20,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"IFU"                         ,	21,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	22,	1,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	47,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SARB"                        ,	0,	1,	48,	"R/W",	0,	0,	1ull,	1ull},
+	{"GXOR_ENA"                    ,	1,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXOR_ENA"                    ,	2,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"NRPL_ENA"                    ,	3,	1,	48,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	48,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	49,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	49,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	50,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	50,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	50,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	50,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	51,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	31,	51,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	51,	"RAZ",	1,	1,	0,	0},
+	{"CP2ECCENA"                   ,	0,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SBE"                      ,	1,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2DBE"                      ,	2,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2SBINA"                    ,	3,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2DBINA"                    ,	4,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SYN"                      ,	5,	8,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEECCENA"                   ,	13,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESBE"                      ,	14,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEDBE"                      ,	15,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTESBINA"                    ,	16,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEDBINA"                    ,	17,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESYN"                      ,	18,	7,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEPARENA"                   ,	25,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEPERR"                     ,	26,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEPINA"                     ,	27,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PARENA"                   ,	28,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PERR"                     ,	29,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2PINA"                     ,	30,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBLOVF"                      ,	31,	1,	52,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBLINA"                      ,	32,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	52,	"RAZ",	1,	1,	0,	0},
+	{"ENA_P1"                      ,	0,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENA_P0"                      ,	1,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	53,	"RAZ",	1,	1,	0,	0},
+	{"MTYPE"                       ,	3,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_LAT"                     ,	4,	2,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"RW_DLY"                      ,	6,	4,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_DLY"                      ,	10,	4,	53,	"R/W",	0,	0,	2ull,	2ull},
+	{"FPRCH"                       ,	14,	2,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	16,	2,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLEN"                        ,	18,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBUNK"                       ,	19,	3,	53,	"R/W",	0,	0,	2ull,	2ull},
+	{"R2R_PBUNK"                   ,	22,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_P1"                     ,	23,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"INIT_P0"                     ,	24,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUNK_INIT"                   ,	25,	2,	53,	"R/W",	0,	0,	3ull,	3ull},
+	{"LPP_ENA"                     ,	27,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	53,	"RAZ",	1,	1,	0,	0},
+	{"REF_INT"                     ,	0,	4,	54,	"R/W",	0,	0,	3ull,	3ull},
+	{"TSKW"                        ,	4,	2,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	54,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TRL"                         ,	8,	4,	54,	"R/W",	0,	0,	6ull,	6ull},
+	{"TWL"                         ,	12,	4,	54,	"R/W",	0,	0,	7ull,	7ull},
+	{"TRC"                         ,	16,	4,	54,	"R/W",	0,	0,	6ull,	6ull},
+	{"TMRSC"                       ,	20,	3,	54,	"R/W",	0,	0,	6ull,	6ull},
+	{"MRS_ENA"                     ,	23,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"AREF_ENA"                    ,	24,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"REF_INTLO"                   ,	25,	9,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	54,	"RAZ",	1,	1,	0,	0},
+	{"FCRAM2P"                     ,	0,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXBNK"                      ,	1,	1,	55,	"R/W",	0,	0,	1ull,	1ull},
+	{"UA_START"                    ,	2,	2,	55,	"R/W",	0,	0,	1ull,	1ull},
+	{"REFSHORT"                    ,	4,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRFC"                        ,	5,	5,	55,	"R/W",	0,	0,	9ull,	9ull},
+	{"SILRST"                      ,	10,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	11,	1,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	55,	"RAZ",	1,	1,	0,	0},
+	{"MADDR"                       ,	0,	24,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"BNUM"                        ,	24,	3,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"PNUM"                        ,	27,	1,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	28,	2,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"FDST"                        ,	30,	9,	56,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	56,	"RAZ",	1,	1,	0,	0},
+	{"MRS"                         ,	0,	15,	57,	"R/W",	0,	0,	66ull,	66ull},
+	{"RESERVED_15_15"              ,	15,	1,	57,	"RAZ",	1,	1,	0,	0},
+	{"EMRS"                        ,	16,	15,	57,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_31_31"              ,	31,	1,	57,	"RAZ",	1,	1,	0,	0},
+	{"EMRS2"                       ,	32,	15,	57,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	57,	"RAZ",	1,	1,	0,	0},
+	{"MRSDAT"                      ,	0,	23,	58,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_23_63"              ,	23,	41,	58,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"DTMODE"                      ,	3,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"DCMODE"                      ,	4,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDLCK"                      ,	5,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	4,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	59,	"RAZ",	1,	1,	0,	0},
+	{"SBD0"                        ,	0,	64,	60,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	61,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	62,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	63,	"RO",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	64,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	64,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	65,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	66,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	66,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	66,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	67,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	67,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	68,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	68,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	68,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	69,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	69,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	70,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	70,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	71,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	71,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	72,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	72,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	73,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	73,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	74,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	74,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	74,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	75,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	75,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	75,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	76,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	76,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	77,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	77,	"RAZ",	1,	1,	0,	0},
+	{"OUT_COL"                     ,	0,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_OVR"                     ,	1,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	16,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_21"              ,	18,	4,	78,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	78,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	79,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	80,	"RO",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	80,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	80,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	81,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	81,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	82,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	82,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	82,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	82,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	82,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	83,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	84,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	85,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	86,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	87,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	88,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	89,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	89,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	90,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	90,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	90,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	91,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	91,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	92,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	93,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_FREE"                    ,	6,	1,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLAN_LEN"                    ,	7,	1,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	93,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	94,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	94,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	95,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	95,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	96,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	96,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	97,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	98,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	98,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	99,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	99,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	100,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	100,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	100,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	100,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	101,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	101,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	102,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	103,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	104,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	105,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	106,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	106,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	107,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	107,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	108,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	108,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	109,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	109,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	110,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	110,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	111,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	111,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	112,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	112,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	113,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	113,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	114,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	114,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	16,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	115,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	4,	116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	116,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	16,	117,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP"                        ,	16,	16,	117,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	117,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	118,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	118,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	119,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	119,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	120,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	120,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	120,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	121,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	122,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	122,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	123,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	123,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	124,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	125,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	125,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	126,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	126,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	127,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	127,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	128,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	128,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	129,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	129,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	130,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	130,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	131,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	131,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	133,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	133,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	134,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	134,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	135,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	135,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	142,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	143,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	143,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	144,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	144,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	145,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	145,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	146,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	146,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	147,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	147,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	147,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	148,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	148,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	149,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	149,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	150,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	150,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	151,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	151,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	152,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	153,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	153,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	154,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	154,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	155,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	155,	"RAZ",	1,	1,	0,	0},
+	{"CONT_PKT"                    ,	0,	1,	156,	"R/W",	0,	1,	0ull,	0},
+	{"TPA_CLR"                     ,	1,	1,	156,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	156,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DRAIN"                       ,	0,	16,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	157,	"RAZ",	1,	1,	0,	0},
+	{"MAX1"                        ,	0,	8,	158,	"R/W",	0,	1,	8ull,	0},
+	{"MAX2"                        ,	8,	8,	158,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	158,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	6,	159,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	159,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	160,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	161,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	161,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	162,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	162,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	163,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	163,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	164,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	164,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	165,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	165,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	166,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	166,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	166,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	167,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	168,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	168,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	168,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	169,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	170,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	170,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	170,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	170,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	170,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	171,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	171,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	171,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	171,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	171,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	172,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	173,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	174,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	175,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	176,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	177,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	178,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	179,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	179,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	179,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	179,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	179,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	180,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	180,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	180,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	180,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	180,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	181,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	182,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	183,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	184,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	185,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	186,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	186,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	187,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	188,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	189,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	190,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	191,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	193,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	193,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	194,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	195,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	195,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	196,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	197,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	197,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	198,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	198,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	199,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	200,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	200,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	201,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	201,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	201,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	201,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	201,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	202,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	202,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	202,	"RO",	0,	0,	36ull,	36ull},
+	{"RESERVED_44_63"              ,	44,	20,	202,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	203,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	203,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	204,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	204,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	204,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	204,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	204,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	204,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	205,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	205,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	206,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	207,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	208,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	208,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	208,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	208,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	209,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	209,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	209,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	210,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	210,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	211,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	211,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	212,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	212,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	213,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	214,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	215,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	216,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	216,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	216,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	216,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	216,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	13,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	217,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	218,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"PICBST"                      ,	2,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RHDF"                        ,	4,	4,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	219,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	220,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	220,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	220,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	4,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	4,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	221,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	222,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	222,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	224,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	4,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	4,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	225,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	225,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	226,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	10,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	10,	17,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	227,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	4,	228,	"R/W",	0,	0,	15ull,	15ull},
+	{"STPARTDIS"                   ,	4,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	228,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	229,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	230,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	231,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK4"                       ,	0,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK5"                       ,	8,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK6"                       ,	16,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK7"                       ,	24,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK8"                       ,	0,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK9"                       ,	8,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK10"                      ,	16,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK11"                      ,	24,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	233,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK12"                      ,	0,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK13"                      ,	8,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK14"                      ,	16,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK15"                      ,	24,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	235,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	237,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	238,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	239,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	240,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	240,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	240,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	240,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	240,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	240,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	11,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	241,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	241,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	242,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	243,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	244,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	245,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	246,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_512K"                   ,	34,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_256K"                   ,	35,	1,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	247,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	248,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	248,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	10,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	248,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	248,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	248,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	248,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RATE"                        ,	0,	8,	249,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_63"               ,	8,	56,	249,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	7,	250,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_7_63"               ,	7,	57,	250,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	0,	16,	251,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	251,	"RAZ",	1,	1,	0,	0},
+	{"DBG_EN"                      ,	0,	1,	252,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	252,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	253,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	253,	"RAZ",	1,	1,	0,	0},
+	{"POLARITY"                    ,	0,	1,	254,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	254,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	8,	255,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	255,	"RAZ",	1,	1,	0,	0},
+	{"FORMAT"                      ,	0,	4,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	256,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	257,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	258,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	258,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	32,	259,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	259,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	32,	260,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	260,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	32,	261,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	261,	"RAZ",	1,	1,	0,	0},
+	{"PCTL_DAT"                    ,	0,	4,	262,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CMD"                    ,	4,	4,	262,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CLK"                    ,	8,	4,	262,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	262,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	262,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CMD"                    ,	20,	4,	262,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CLK"                    ,	24,	4,	262,	"R/W",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	262,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	262,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	263,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	263,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	263,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	263,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	263,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE128B"                    ,	10,	1,	263,	"R/W",	0,	0,	1ull,	1ull},
+	{"SET_ZERO"                    ,	11,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	263,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	263,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	263,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	263,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	263,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	263,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	263,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	264,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	265,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	266,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	266,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	266,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	266,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	266,	"R/W",	0,	0,	2ull,	2ull},
+	{"SILO_HC"                     ,	21,	1,	266,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	266,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	266,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	266,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRDSYN0"                     ,	0,	8,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	268,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	269,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	270,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	271,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	272,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	272,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	272,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	272,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	272,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	272,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	272,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	272,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	272,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	272,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	273,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	273,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	273,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	273,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	273,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	273,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	273,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	273,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	273,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	274,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	1,	1,	0,	0},
+	{"BWCTL"                       ,	0,	4,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"BWUPD"                       ,	4,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	276,	"RAZ",	1,	1,	0,	0},
+	{"RODT_LO0"                    ,	0,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	277,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	277,	"RAZ",	1,	1,	0,	0},
+	{"WODT_LO0"                    ,	0,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO1"                    ,	4,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO2"                    ,	8,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO3"                    ,	12,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI0"                    ,	16,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI1"                    ,	20,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI2"                    ,	24,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI3"                    ,	28,	4,	278,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	278,	"RAZ",	1,	1,	0,	0},
+	{"NCBI"                        ,	0,	1,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	279,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	280,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	281,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	282,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	282,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	282,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	283,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	283,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	283,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	284,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	285,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	285,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_29"              ,	28,	2,	285,	"RAZ",	1,	1,	0,	0},
+	{"ORBIT"                       ,	30,	1,	285,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	285,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	285,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	286,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_54_59"              ,	54,	6,	286,	"RAZ",	1,	1,	0,	0},
+	{"PAGES"                       ,	60,	2,	286,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	286,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	286,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	287,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	287,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	287,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	287,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	288,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	288,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	289,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	289,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	16,	290,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	290,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	290,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	290,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	290,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	290,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	290,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	290,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	291,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	291,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	291,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	291,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	291,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	291,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	291,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	291,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	292,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	292,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	293,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	293,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	293,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	293,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	293,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	294,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	295,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	10,	296,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	296,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	297,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	297,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	297,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	297,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	297,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	297,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	297,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	297,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	298,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	298,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	298,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	298,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	298,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	298,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	298,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	298,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	298,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	299,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	299,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	299,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	300,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	300,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	300,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	301,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	301,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	302,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	302,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	303,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	303,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	304,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	304,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	304,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	304,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	304,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	304,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	304,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	305,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	306,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	306,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	307,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	307,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	307,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	307,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	308,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	308,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	308,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	309,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	309,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	309,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	309,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	309,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	309,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	309,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	309,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	309,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	310,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	311,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	311,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	311,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	311,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	311,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	311,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	311,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	311,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	311,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	312,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	312,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	313,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	313,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	314,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	314,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	314,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	314,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	315,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	316,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	317,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	318,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	318,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	318,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	318,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	319,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	320,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	321,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	322,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	322,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	323,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	323,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	324,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	324,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	325,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	325,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	325,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	325,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	325,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	325,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	326,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	326,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	327,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	327,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"POF3_BS"                     ,	5,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"POF2_BS"                     ,	6,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"POF1_BS"                     ,	7,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"POF0_BS"                     ,	8,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	328,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	329,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	329,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	330,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	330,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	330,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	330,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"INS1_64B"                    ,	43,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"INS2_64B"                    ,	44,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"INS3_64B"                    ,	45,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"INS0_ENB"                    ,	46,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS1_ENB"                    ,	47,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS2_ENB"                    ,	48,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS3_ENB"                    ,	49,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT0_ENB"                    ,	50,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT1_ENB"                    ,	51,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT2_ENB"                    ,	52,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT3_ENB"                    ,	53,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIS_PNIW"                    ,	54,	1,	330,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	330,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	330,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	331,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	331,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	332,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	332,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	332,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	332,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	332,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	332,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	332,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	332,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	332,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	332,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	332,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	332,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	333,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	333,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	333,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	334,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	334,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	334,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	335,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	335,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	335,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	336,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	336,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	337,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	337,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	338,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	338,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	339,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	339,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	339,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	339,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	339,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	339,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	339,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	339,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_RR"                      ,	22,	1,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	339,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO1_2SML"                    ,	4,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO2_2SML"                    ,	5,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO3_2SML"                    ,	6,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_RTOUT"                    ,	8,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_RTOUT"                    ,	9,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_RTOUT"                    ,	10,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_OVERF"                    ,	12,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_OVERF"                    ,	13,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_OVERF"                    ,	14,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RTOUT"                    ,	16,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_RTOUT"                    ,	17,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_RTOUT"                    ,	18,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PERR"                     ,	20,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PERR"                     ,	21,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PERR"                     ,	22,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"G1_RTOUT"                    ,	24,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"G2_RTOUT"                    ,	25,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"G3_RTOUT"                    ,	26,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PPERR"                    ,	28,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PPERR"                    ,	29,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PPERR"                    ,	30,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PTOUT"                    ,	32,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PTOUT"                    ,	33,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PTOUT"                    ,	34,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_PPERR"                    ,	36,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_PPERR"                    ,	37,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_PPERR"                    ,	38,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_S_E"                     ,	42,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_A_F"                     ,	43,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_S_E"                     ,	44,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_A_F"                     ,	45,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_S_E"                      ,	46,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_A_F"                      ,	47,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_S_E"                      ,	48,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_A_F"                      ,	49,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_S_E"                     ,	50,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_A_F"                     ,	51,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_S_E"                     ,	52,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_A_F"                     ,	53,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"RWX_S_E"                     ,	54,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDX_S_E"                     ,	55,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_E"                     ,	56,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_F"                     ,	57,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_E"                     ,	58,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_F"                     ,	59,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_S_E"                      ,	60,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_A_F"                      ,	61,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	340,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO1_2SML"                    ,	4,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO2_2SML"                    ,	5,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO3_2SML"                    ,	6,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_RTOUT"                    ,	8,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_RTOUT"                    ,	9,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_RTOUT"                    ,	10,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_OVERF"                    ,	12,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_OVERF"                    ,	13,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_OVERF"                    ,	14,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RTOUT"                    ,	16,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_RTOUT"                    ,	17,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_RTOUT"                    ,	18,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PERR"                     ,	20,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PERR"                     ,	21,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PERR"                     ,	22,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G1_RTOUT"                    ,	24,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G2_RTOUT"                    ,	25,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G3_RTOUT"                    ,	26,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PPERR"                    ,	28,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PPERR"                    ,	29,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PPERR"                    ,	30,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PTOUT"                    ,	32,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PTOUT"                    ,	33,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PTOUT"                    ,	34,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_PPERR"                    ,	36,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_PPERR"                    ,	37,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_PPERR"                    ,	38,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_S_E"                     ,	42,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_A_F"                     ,	43,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_S_E"                     ,	44,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_A_F"                     ,	45,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_S_E"                      ,	46,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_A_F"                      ,	47,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_S_E"                      ,	48,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_A_F"                      ,	49,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_S_E"                     ,	50,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_A_F"                     ,	51,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_S_E"                     ,	52,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_A_F"                     ,	53,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RWX_S_E"                     ,	54,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDX_S_E"                     ,	55,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_E"                     ,	56,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_F"                     ,	57,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_E"                     ,	58,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_F"                     ,	59,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_S_E"                      ,	60,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_A_F"                      ,	61,	1,	341,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	341,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	342,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	343,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	344,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	344,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	344,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	36,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"SHORTL"                      ,	37,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	344,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	345,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	346,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL1"                     ,	4,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL1"                     ,	5,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL1"                     ,	6,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL2"                     ,	8,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL2"                     ,	9,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL2"                     ,	10,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL3"                     ,	12,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL3"                     ,	13,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL3"                     ,	14,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"IPTR_O0"                     ,	16,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O1"                     ,	17,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O2"                     ,	18,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O3"                     ,	19,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_23"              ,	20,	4,	347,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"O1_CSRM"                     ,	25,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"O2_CSRM"                     ,	26,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"O3_CSRM"                     ,	27,	1,	347,	"R/W",	0,	0,	0ull,	1ull},
+	{"O0_RO"                       ,	28,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O1_RO"                       ,	32,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O1_NS"                       ,	33,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O1_ES"                       ,	34,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O2_RO"                       ,	36,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O2_NS"                       ,	37,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O2_ES"                       ,	38,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O3_RO"                       ,	40,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O3_NS"                       ,	41,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"O3_ES"                       ,	42,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"P0_BMODE"                    ,	44,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"P1_BMODE"                    ,	45,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"P2_BMODE"                    ,	46,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"P3_BMODE"                    ,	47,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	48,	1,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	347,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	348,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	348,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	349,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	350,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	350,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	351,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	352,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	352,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	352,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	353,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	353,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	353,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	353,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	354,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	354,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	355,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	355,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	355,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	355,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	355,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	356,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	356,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	356,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	356,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	356,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	357,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	357,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	357,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	357,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	357,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	358,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	358,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	358,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	358,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	358,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	358,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	359,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	359,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	359,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_8"                      ,	8,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_13"                     ,	13,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_14"                     ,	14,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_15"                     ,	15,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_21"                     ,	21,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_24"                     ,	24,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_25"                     ,	25,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_26"                     ,	26,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_27"                     ,	27,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_28"                     ,	28,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_29"                     ,	29,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_31"                     ,	31,	1,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	360,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	32,	361,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	361,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	362,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	362,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	363,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	363,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	363,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	363,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	364,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	364,	"RO",	0,	0,	5ull,	5ull},
+	{"ISAE"                        ,	0,	1,	365,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	365,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	365,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	365,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	365,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	365,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	365,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	365,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	365,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	365,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	365,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	365,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	365,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	365,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	365,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	365,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	365,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	366,	"RO",	0,	0,	3ull,	3ull},
+	{"CC"                          ,	8,	24,	366,	"RO",	0,	0,	733184ull,	733184ull},
+	{"CLS"                         ,	0,	8,	367,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	367,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	367,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	367,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	368,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	368,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	368,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	369,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	370,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	370,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	370,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	371,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	372,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	372,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	372,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	373,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	373,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	374,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	375,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	375,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	376,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	376,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	376,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	376,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	377,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	377,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	378,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	378,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	378,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	378,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	379,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	379,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	379,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	379,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	380,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	381,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	382,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	382,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	382,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	382,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	382,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	382,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	382,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	382,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	382,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	382,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	382,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	382,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	382,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	383,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	384,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	385,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	385,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	385,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	385,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	385,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	386,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	386,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	386,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	386,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	386,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	387,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	387,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	387,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	387,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	387,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	387,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	387,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	387,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	387,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	387,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	387,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	387,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	387,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	388,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	388,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	388,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	388,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	389,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	389,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	389,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	389,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	389,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	389,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	390,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	390,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	390,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	390,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	390,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	390,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	390,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	391,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	391,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	392,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	393,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	393,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	394,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	394,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	394,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	394,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	394,	"RO",	1,	1,	0,	0},
+	{"AP_PCIX"                     ,	13,	1,	394,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_14"              ,	14,	1,	394,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	394,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	394,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	394,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	394,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	394,	"RO",	0,	0,	1ull,	1ull},
+	{"BB0"                         ,	20,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1"                         ,	21,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_ES"                       ,	22,	2,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_CA"                       ,	24,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_SIZ"                     ,	25,	1,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_HOLE"                    ,	26,	3,	394,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	394,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	395,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	395,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	397,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	398,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	399,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT1"                      ,	18,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT2"                      ,	19,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT3"                      ,	20,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME1"                     ,	22,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME2"                     ,	23,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME3"                     ,	24,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	400,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	400,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT1"                      ,	18,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT2"                      ,	19,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT3"                      ,	20,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME1"                     ,	22,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME2"                     ,	23,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME3"                     ,	24,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	401,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	402,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	402,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	403,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	403,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	403,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	404,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	404,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	405,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	405,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	406,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	407,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	408,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	409,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	409,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	409,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	410,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	410,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	410,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	411,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	411,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	411,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	412,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	412,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	412,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	413,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	413,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	414,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	414,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	415,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	3,	45,	415,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	415,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	415,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	416,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	417,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	417,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	417,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	417,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	418,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	419,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	420,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	420,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	420,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	420,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	420,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	421,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	421,	"RAZ",	1,	1,	0,	0},
+	{"REFLECT"                     ,	0,	1,	422,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	422,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	422,	"RAZ",	1,	1,	0,	0},
+	{"IV"                          ,	0,	32,	423,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	423,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	424,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	425,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	425,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	425,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	425,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	426,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	426,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	426,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	426,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKTDRP"                      ,	0,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	427,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	427,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	428,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	428,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	429,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	430,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	430,	"RAZ",	1,	1,	0,	0},
+	{"CRC_EN"                      ,	12,	1,	430,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	430,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	430,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	430,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	430,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	431,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	431,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	432,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	432,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	433,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	433,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	2,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	434,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	434,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	434,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	434,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	435,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	436,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	437,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	437,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	438,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	439,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	439,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	440,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	440,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	441,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	441,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	442,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	442,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	443,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	443,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	444,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	444,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	445,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	445,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	446,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	446,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	447,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	448,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	448,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	449,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	449,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	450,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	450,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	451,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	452,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	453,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	453,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	453,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	454,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	454,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	454,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	455,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	455,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	456,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	456,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	457,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	457,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	457,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	457,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	458,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	458,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	458,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	458,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	458,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	459,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	459,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	459,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	459,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	460,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	460,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	460,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	460,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	460,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	461,	"RO",	1,	0,	0,	0ull},
+	{"WIDX2"                       ,	0,	17,	462,	"RO",	1,	0,	0,	0ull},
+	{"RIDX2"                       ,	17,	17,	462,	"RO",	1,	0,	0,	0ull},
+	{"WIDX"                        ,	34,	17,	462,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"RIDX"                        ,	0,	17,	463,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	464,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	464,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	464,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	464,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	464,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	465,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	465,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	465,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	465,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	465,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	466,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	4,	467,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	4,	2,	467,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	6,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	7,	7,	467,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	3,	467,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	17,	5,	467,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	22,	3,	467,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	26,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	467,	"RAZ",	1,	0,	0,	0ull},
+	{"CBUF_FRE"                    ,	28,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"XFER_DWR"                    ,	29,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"XFER_WOR"                    ,	30,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	31,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	32,	16,	467,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CNT"                    ,	48,	13,	467,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_LEN"                    ,	61,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_SOP"                    ,	62,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	63,	1,	467,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_MOD"                    ,	0,	2,	468,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_UID"                    ,	2,	1,	468,	"RO",	1,	0,	0,	0ull},
+	{"DWRI_CHK"                    ,	3,	1,	468,	"RO",	1,	0,	0,	0ull},
+	{"WORK_MIN"                    ,	4,	3,	468,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	7,	1,	468,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFM"                    ,	8,	3,	468,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	469,	"RO",	1,	0,	0,	0ull},
+	{"START"                       ,	16,	33,	469,	"RO",	1,	0,	0,	0ull},
+	{"DWB"                         ,	49,	9,	469,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	469,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	470,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	470,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	470,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	470,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	470,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	470,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	471,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	471,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	472,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	472,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	472,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	472,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	472,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	472,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	472,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	472,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	472,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	473,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	473,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	473,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	473,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	473,	"RAZ",	1,	0,	0,	0ull},
+	{"PSB"                         ,	0,	7,	474,	"RO",	1,	0,	0,	0ull},
+	{"PDB"                         ,	7,	4,	474,	"RO",	1,	0,	0,	0ull},
+	{"QCB"                         ,	11,	2,	474,	"RO",	1,	0,	0,	0ull},
+	{"QSB"                         ,	13,	2,	474,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	15,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"CRC"                         ,	16,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"OUT"                         ,	17,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	18,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"WIF"                         ,	19,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"RIF"                         ,	20,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	21,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"PSB2"                        ,	22,	5,	474,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	474,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	475,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	475,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	475,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	475,	"RAZ",	1,	0,	0,	0ull},
+	{"REFIN"                       ,	0,	1,	476,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	476,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	476,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	32,	477,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	477,	"RAZ",	1,	0,	0,	0ull},
+	{"IV"                          ,	0,	32,	478,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	478,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	17,	479,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	479,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	480,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	480,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	481,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	482,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	483,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	483,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	484,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	484,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	485,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR0"                        ,	0,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR1"                        ,	1,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND0"                       ,	2,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND1"                       ,	3,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	4,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	5,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	6,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	7,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	8,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	9,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	486,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	16,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	486,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	487,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	487,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	488,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	488,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	488,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	488,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	488,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	488,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	488,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	488,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	488,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	488,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	488,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	489,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	489,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	489,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	490,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	490,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	491,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	491,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	492,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	492,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	493,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	493,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	494,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"RESERVED_16_63"              ,	16,	48,	494,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	495,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	495,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	495,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	495,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	495,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	11,	496,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	496,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	11,	496,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	496,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	12,	496,	"RO",	0,	1,	2027ull,	0},
+	{"BUF_CNT"                     ,	36,	12,	496,	"RO",	0,	1,	0ull,	0},
+	{"DES_CNT"                     ,	48,	12,	496,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	496,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	497,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	497,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	498,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	498,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	499,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	499,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	500,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	500,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	500,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	12,	501,	"RO",	0,	1,	0ull,	0},
+	{"DS_CNT"                      ,	12,	12,	501,	"RO",	0,	1,	0ull,	0},
+	{"TC_CNT"                      ,	24,	4,	501,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	501,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	502,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	502,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	502,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	502,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	11,	503,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	503,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	11,	503,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	503,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	503,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	503,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	503,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	504,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	504,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	505,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	505,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	505,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	506,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	507,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	507,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	507,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	507,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	507,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	507,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	508,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	508,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	508,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	508,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	1,	508,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	508,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	509,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	509,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	510,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	510,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	510,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	510,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	511,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	511,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	511,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	511,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	512,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STAT0"                       ,	0,	1,	513,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT1"                       ,	1,	1,	513,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT2"                       ,	2,	1,	513,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	513,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRXDLCK"                     ,	0,	1,	514,	"R/W",	0,	0,	0ull,	1ull},
+	{"RCVTRN"                      ,	1,	1,	514,	"R/W",	0,	0,	0ull,	1ull},
+	{"DRPTRN"                      ,	2,	1,	514,	"R/W",	0,	0,	0ull,	1ull},
+	{"SNDTRN"                      ,	3,	1,	514,	"R/W",	0,	0,	0ull,	1ull},
+	{"STATRCV"                     ,	4,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATDRV"                     ,	5,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUNBIST"                     ,	6,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDLY"                      ,	7,	5,	514,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_12_15"              ,	12,	4,	514,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SEETRN"                      ,	16,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	514,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	515,	"RAZ",	0,	1,	0ull,	0},
+	{"D4CLK0"                      ,	4,	1,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"D4CLK1"                      ,	5,	1,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK0"                      ,	6,	1,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK1"                      ,	7,	1,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"SRXTRN"                      ,	8,	1,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_9"                ,	9,	1,	515,	"RAZ",	0,	1,	0ull,	0},
+	{"STXCAL"                      ,	10,	1,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLLDIS"                      ,	0,	1,	516,	"R/W",	1,	0,	0,	0ull},
+	{"DLLFRC"                      ,	1,	1,	516,	"WR0",	1,	0,	0,	0ull},
+	{"OFFDLY"                      ,	2,	6,	516,	"R/W",	1,	0,	0,	0ull},
+	{"BITSEL"                      ,	8,	5,	516,	"R/W",	1,	1,	0,	0},
+	{"OFFSET"                      ,	13,	5,	516,	"R/W",	1,	1,	0,	0},
+	{"MUX"                         ,	18,	1,	516,	"WR0",	1,	1,	0,	0},
+	{"INC"                         ,	19,	1,	516,	"WR0",	1,	1,	0,	0},
+	{"DEC"                         ,	20,	1,	516,	"WR0",	1,	1,	0,	0},
+	{"CLRDLY"                      ,	21,	1,	516,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_22_23"              ,	22,	2,	516,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SSTEP"                       ,	24,	1,	516,	"R/W",	1,	0,	0,	0ull},
+	{"SSTEP_GO"                    ,	25,	1,	516,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_26_27"              ,	26,	2,	516,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FALL8"                       ,	28,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALLNOP"                     ,	29,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	516,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	5,	517,	"RO",	0,	1,	0ull,	0},
+	{"MUXSEL"                      ,	5,	2,	517,	"RO",	0,	1,	0ull,	0},
+	{"UNXTERM"                     ,	7,	1,	517,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TESTRES"                     ,	8,	1,	517,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	517,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRX4CMP"                     ,	0,	8,	518,	"R/W",	0,	1,	0ull,	0},
+	{"STX4PCMP"                    ,	8,	4,	518,	"R/W",	0,	1,	0ull,	0},
+	{"STX4NCMP"                    ,	12,	4,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	518,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ERRCNT"                      ,	0,	4,	519,	"R/W",	0,	0,	0ull,	3ull},
+	{"RESERVED_4_5"                ,	4,	2,	519,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPPAY"                      ,	6,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPCLS"                      ,	7,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	8,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	519,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT"                         ,	0,	8,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RSVOP"                       ,	8,	4,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"CALBNK"                      ,	12,	2,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_30"              ,	14,	17,	520,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUL"                         ,	31,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	520,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	521,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	521,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	522,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_30"              ,	12,	19,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPF"                         ,	31,	1,	522,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	523,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	523,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	524,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	524,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX"                         ,	0,	32,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	525,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTSEL"                      ,	0,	4,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	526,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUX_EN"                      ,	0,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"MACRO_EN"                    ,	1,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXDIST"                     ,	2,	5,	527,	"R/W",	0,	0,	0ull,	8ull},
+	{"SET_BOOT"                    ,	7,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR_BOOT"                    ,	8,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"JITTER"                      ,	9,	3,	527,	"R/W",	0,	0,	0ull,	1ull},
+	{"TRNTEST"                     ,	12,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	527,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BW_CTL"                      ,	0,	5,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	528,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SETTING"                     ,	0,	17,	529,	"RO",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	529,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	530,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	530,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRTS"                        ,	4,	4,	530,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNORE"                      ,	0,	16,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	531,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	532,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	532,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	532,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	533,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	533,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	4,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC"                         ,	4,	4,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOD"                         ,	8,	4,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	534,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_2"                ,	0,	3,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	3,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINTRN"                      ,	5,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	536,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	538,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	538,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	538,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	538,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPMAX"                      ,	0,	4,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMMAX"                      ,	4,	4,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	539,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	0,	16,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	540,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	541,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	8,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	542,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	543,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MINB"                        ,	0,	9,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	544,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	545,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	545,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_T"                       ,	0,	16,	546,	"R/W",	0,	1,	0ull,	0},
+	{"ALPHA"                       ,	16,	16,	546,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	546,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	547,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	547,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	548,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	549,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	0,	4,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	4,	1,	550,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	550,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	551,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	551,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	0,	22,	552,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	552,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	552,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	552,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	552,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	552,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	553,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	553,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	553,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	554,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	554,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	554,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	554,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	554,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	555,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	556,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	557,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	557,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	557,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	557,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	558,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	558,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	559,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	559,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	560,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	561,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	562,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	563,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	565,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	565,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	566,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	567,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	567,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	568,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	568,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	568,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	568,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	568,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	569,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	570,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	570,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	570,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	570,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	570,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	572,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	572,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	573,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	574,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	574,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	575,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	575,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	575,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	575,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	575,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	576,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	577,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	577,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	579,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	579,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	580,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	580,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	580,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	580,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	580,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	581,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP_CTL"                     ,	0,	4,	582,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	582,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	582,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	583,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	584,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	584,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	585,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	585,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	585,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	585,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	585,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	586,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	586,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	587,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	587,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	588,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	4,	0},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	4,	4},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	3,	8},
+	{"cvmx_asx#_rld_bypass"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	2,	11},
+	{"cvmx_asx#_rld_bypass_setting",	CVMX_CSR_DB_TYPE_RSL,	64,	8,	2,	13},
+	{"cvmx_asx#_rld_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	3,	15},
+	{"cvmx_asx#_rld_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	3,	18},
+	{"cvmx_asx#_rld_nctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	21},
+	{"cvmx_asx#_rld_nctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	23},
+	{"cvmx_asx#_rld_pctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	25},
+	{"cvmx_asx#_rld_pctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	27},
+	{"cvmx_asx#_rld_setting"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	6,	29},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	35},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	2,	37},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	39},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	4,	41},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	45},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	47},
+	{"cvmx_asx0_dbg_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	3,	49},
+	{"cvmx_asx0_dbg_data_enable"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	55,	2,	52},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	56,	2,	54},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	57,	2,	56},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	58,	2,	58},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	59,	2,	60},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	60,	15,	62},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	93,	2,	77},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	126,	15,	79},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	142,	2,	94},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	158,	15,	96},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	191,	15,	111},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	207,	2,	126},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	208,	2,	128},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	224,	2,	130},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	240,	2,	132},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	241,	2,	134},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	242,	2,	136},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	243,	1,	138},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	259,	3,	139},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	260,	2,	142},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	261,	4,	144},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	262,	2,	148},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	263,	3,	150},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	267,	7,	153},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	283,	5,	160},
+	{"cvmx_dfa_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	284,	4,	165},
+	{"cvmx_dfa_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	285,	10,	169},
+	{"cvmx_dfa_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	286,	5,	179},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	287,	2,	184},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	288,	4,	186},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	289,	3,	190},
+	{"cvmx_dfa_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	290,	21,	193},
+	{"cvmx_dfa_memcfg0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	291,	20,	214},
+	{"cvmx_dfa_memcfg1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	292,	11,	234},
+	{"cvmx_dfa_memcfg2"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	293,	8,	245},
+	{"cvmx_dfa_memfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	294,	6,	253},
+	{"cvmx_dfa_memfcr"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	295,	6,	259},
+	{"cvmx_dfa_memrld"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	296,	2,	265},
+	{"cvmx_dfa_ncbctl"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	297,	8,	267},
+	{"cvmx_dfa_rodt_comp_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	298,	6,	275},
+	{"cvmx_dfa_sbd_dbg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	299,	1,	281},
+	{"cvmx_dfa_sbd_dbg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	300,	1,	282},
+	{"cvmx_dfa_sbd_dbg2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	301,	1,	283},
+	{"cvmx_dfa_sbd_dbg3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	302,	1,	284},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	303,	6,	285},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	304,	7,	291},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	305,	3,	298},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	312,	2,	301},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	319,	3,	303},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	320,	2,	306},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	321,	29,	308},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	322,	29,	337},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	323,	2,	366},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	331,	2,	368},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	339,	3,	370},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	340,	3,	373},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	341,	2,	376},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	342,	2,	378},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	343,	8,	380},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	345,	2,	388},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	347,	3,	390},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	349,	2,	393},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	351,	5,	395},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	359,	1,	400},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	367,	1,	401},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	375,	1,	402},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	383,	1,	403},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	391,	1,	404},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	399,	1,	405},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	407,	2,	406},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	415,	4,	408},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	423,	2,	412},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	431,	11,	414},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	439,	10,	425},
+	{"cvmx_gmx#_rx#_frm_max"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	447,	2,	435},
+	{"cvmx_gmx#_rx#_frm_min"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	455,	2,	437},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	463,	2,	439},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	21,	441},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	479,	21,	462},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	487,	2,	483},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	495,	2,	485},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	503,	4,	487},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	511,	2,	491},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	519,	2,	493},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	527,	2,	495},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	535,	2,	497},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	543,	2,	499},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	551,	2,	501},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	559,	2,	503},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	567,	2,	505},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	575,	2,	507},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	583,	2,	509},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	591,	4,	511},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	599,	2,	515},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	607,	2,	517},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	615,	2,	519},
+	{"cvmx_gmx#_rx_pass_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	623,	2,	521},
+	{"cvmx_gmx#_rx_pass_map#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	625,	2,	523},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	657,	3,	525},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	659,	2,	528},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	661,	2,	530},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	669,	3,	532},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	671,	5,	535},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	679,	2,	540},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	687,	2,	542},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	695,	3,	544},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	703,	2,	547},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	711,	2,	549},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	719,	2,	551},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	727,	2,	553},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	735,	2,	555},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	743,	2,	557},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	751,	2,	559},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	759,	2,	561},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	767,	2,	563},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	775,	2,	565},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	783,	2,	567},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	791,	2,	569},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	799,	2,	571},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	807,	2,	573},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	815,	2,	575},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	823,	2,	577},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	831,	2,	579},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	839,	2,	581},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	847,	2,	583},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	855,	2,	585},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	857,	2,	587},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	859,	2,	589},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	861,	3,	591},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	863,	8,	594},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	865,	8,	602},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	867,	2,	610},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	869,	2,	612},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	871,	4,	614},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	873,	2,	618},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	875,	2,	620},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	877,	2,	622},
+	{"cvmx_gmx#_tx_spi_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	879,	3,	624},
+	{"cvmx_gmx#_tx_spi_drain"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	881,	2,	627},
+	{"cvmx_gmx#_tx_spi_max"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	883,	4,	629},
+	{"cvmx_gmx#_tx_spi_round#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	885,	2,	633},
+	{"cvmx_gmx#_tx_spi_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	949,	2,	635},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	951,	7,	637},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	967,	2,	644},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	968,	2,	646},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	969,	2,	648},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	970,	2,	650},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	971,	19,	652},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	972,	6,	671},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	973,	3,	677},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	974,	3,	680},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	975,	3,	683},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	976,	5,	686},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	977,	5,	691},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	978,	1,	696},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	979,	1,	697},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	980,	7,	698},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	981,	7,	705},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	982,	3,	712},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	983,	3,	715},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	984,	3,	718},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	985,	5,	721},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	986,	5,	726},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	987,	1,	731},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	988,	1,	732},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	989,	3,	733},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	990,	3,	736},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	991,	3,	739},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	992,	2,	742},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	993,	2,	744},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	994,	2,	746},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	995,	2,	748},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	996,	17,	750},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	997,	2,	767},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	998,	1,	769},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	999,	12,	770},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1000,	11,	782},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1001,	11,	793},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1002,	2,	804},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1003,	2,	806},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1004,	2,	808},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1005,	3,	810},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1041,	2,	813},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1077,	6,	815},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1078,	5,	821},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1079,	6,	826},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1080,	7,	832},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1081,	2,	839},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1089,	2,	841},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1090,	3,	843},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1091,	5,	846},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1099,	3,	851},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1100,	2,	854},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1101,	2,	856},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1102,	2,	858},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1103,	4,	860},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1104,	3,	864},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1105,	5,	867},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1106,	5,	872},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1107,	7,	877},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1108,	5,	884},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1109,	8,	889},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1110,	10,	897},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1111,	8,	907},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1112,	5,	915},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1113,	4,	920},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1114,	2,	924},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1115,	14,	926},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1116,	19,	940},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1117,	3,	959},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1118,	3,	962},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1119,	2,	965},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1123,	17,	967},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1124,	5,	984},
+	{"cvmx_l2c_spar1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1125,	5,	989},
+	{"cvmx_l2c_spar2"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1126,	5,	994},
+	{"cvmx_l2c_spar3"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1127,	5,	999},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1128,	2,	1004},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1129,	3,	1006},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1130,	2,	1009},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1131,	2,	1011},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1132,	2,	1013},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1133,	7,	1015},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1134,	5,	1022},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1135,	3,	1027},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1136,	3,	1030},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1137,	2,	1033},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1138,	2,	1035},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1139,	2,	1037},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1140,	6,	1039},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1141,	14,	1045},
+	{"cvmx_led_blink"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1142,	2,	1059},
+	{"cvmx_led_clk_phase"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1143,	2,	1061},
+	{"cvmx_led_cylon"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1144,	2,	1063},
+	{"cvmx_led_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1145,	2,	1065},
+	{"cvmx_led_en"                 ,	CVMX_CSR_DB_TYPE_RSL,	64,	1146,	2,	1067},
+	{"cvmx_led_polarity"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1147,	2,	1069},
+	{"cvmx_led_prt"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1148,	2,	1071},
+	{"cvmx_led_prt_fmt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1149,	2,	1073},
+	{"cvmx_led_prt_status#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1150,	2,	1075},
+	{"cvmx_led_udd_cnt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1158,	2,	1077},
+	{"cvmx_led_udd_dat#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1160,	2,	1079},
+	{"cvmx_led_udd_dat_clr#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1162,	2,	1081},
+	{"cvmx_led_udd_dat_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1164,	2,	1083},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1166,	7,	1085},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	19,	1092},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	4,	1111},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	2,	1115},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	2,	1117},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	18,	1119},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	6,	1137},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1173,	5,	1143},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1174,	5,	1148},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	6,	1153},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1176,	2,	1159},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1177,	2,	1161},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1178,	14,	1163},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1179,	9,	1177},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1180,	2,	1186},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1181,	2,	1188},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1182,	12,	1190},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	3,	1202},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1184,	6,	1205},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1185,	9,	1211},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1186,	9,	1220},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1187,	4,	1229},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1188,	3,	1233},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1189,	3,	1236},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1190,	3,	1239},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1191,	5,	1242},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1193,	1,	1247},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1194,	10,	1248},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1202,	13,	1258},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1210,	4,	1271},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1211,	1,	1275},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1215,	2,	1276},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1216,	2,	1278},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1217,	9,	1280},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1218,	8,	1289},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1219,	2,	1297},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1220,	3,	1299},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1221,	2,	1302},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1222,	6,	1304},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1223,	8,	1310},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1224,	4,	1318},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1225,	2,	1322},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1226,	2,	1324},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1227,	13,	1326},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1228,	12,	1339},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1229,	3,	1351},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1230,	3,	1354},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1231,	2,	1357},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1233,	2,	1359},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1235,	2,	1361},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1237,	7,	1363},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1239,	2,	1370},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1241,	7,	1372},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1243,	4,	1379},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1245,	8,	1383},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1247,	9,	1391},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1249,	7,	1400},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1251,	9,	1407},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1253,	2,	1416},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1255,	2,	1418},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1257,	4,	1420},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1259,	2,	1424},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1261,	2,	1426},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1263,	2,	1428},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1265,	4,	1430},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1267,	2,	1434},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1269,	2,	1436},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1271,	2,	1438},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1273,	2,	1440},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1275,	2,	1442},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1277,	2,	1444},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1279,	6,	1446},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1281,	2,	1452},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1285,	2,	1454},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1289,	21,	1456},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1290,	3,	1477},
+	{"cvmx_npi_comp_ctl"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1294,	3,	1480},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1295,	21,	1483},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1296,	2,	1504},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1297,	13,	1506},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1298,	3,	1519},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1299,	3,	1522},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1300,	3,	1525},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1301,	3,	1528},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1302,	2,	1531},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1303,	2,	1533},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1304,	10,	1535},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1305,	63,	1545},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1306,	63,	1608},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1307,	2,	1671},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1308,	2,	1673},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1309,	10,	1675},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1313,	1,	1685},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1314,	2,	1686},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1318,	39,	1688},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1319,	3,	1727},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1323,	2,	1730},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1327,	3,	1732},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1331,	3,	1735},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1335,	3,	1738},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1336,	7,	1741},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1337,	2,	1748},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1338,	13,	1750},
+	{"cvmx_npi_port33_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1339,	13,	1763},
+	{"cvmx_npi_port34_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1340,	13,	1776},
+	{"cvmx_npi_port35_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1341,	13,	1789},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1342,	3,	1802},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1343,	33,	1805},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1344,	2,	1838},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1348,	2,	1840},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1349,	5,	1842},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1381,	2,	1847},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1382,	24,	1849},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1383,	2,	1873},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1384,	7,	1875},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1385,	5,	1882},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1386,	1,	1887},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1387,	5,	1888},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1388,	1,	1893},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1389,	4,	1894},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1390,	2,	1898},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1391,	1,	1900},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1392,	2,	1901},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1393,	4,	1903},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1394,	2,	1907},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1395,	4,	1909},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1396,	16,	1913},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1397,	1,	1929},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1398,	1,	1930},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1399,	18,	1931},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1400,	1,	1949},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1401,	1,	1950},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1402,	7,	1951},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1403,	7,	1958},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1404,	13,	1965},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1405,	10,	1978},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1406,	10,	1988},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1407,	7,	1998},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1408,	2,	2005},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1409,	1,	2007},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1410,	2,	2008},
+	{"cvmx_pci_cnt_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1411,	6,	2010},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1412,	22,	2016},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	1413,	2,	2038},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	1417,	1,	2040},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1419,	1,	2041},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	1421,	1,	2042},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1423,	1,	2043},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1427,	35,	2044},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1428,	35,	2079},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1429,	35,	2114},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1430,	35,	2149},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	1431,	2,	2184},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1432,	2,	2186},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	1436,	1,	2188},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	1440,	1,	2189},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	1444,	1,	2190},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1448,	3,	2191},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1449,	3,	2194},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1450,	3,	2197},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1451,	3,	2200},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1452,	2,	2203},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1453,	2,	2205},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1454,	4,	2207},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1455,	1,	2211},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1456,	4,	2212},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1457,	1,	2216},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1458,	2,	2217},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1459,	5,	2219},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1460,	2,	2224},
+	{"cvmx_pip_crc_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1461,	3,	2226},
+	{"cvmx_pip_crc_iv#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1463,	2,	2229},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1465,	4,	2231},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1469,	8,	2235},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1470,	16,	2243},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1471,	10,	2259},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1472,	10,	2269},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1473,	2,	2279},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1474,	19,	2281},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1510,	25,	2300},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1546,	2,	2325},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1610,	2,	2327},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1618,	9,	2329},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1622,	2,	2338},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1623,	2,	2340},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1624,	2,	2342},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1660,	2,	2344},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1696,	2,	2346},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1732,	2,	2348},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1768,	2,	2350},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	2,	2352},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1840,	2,	2354},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1876,	2,	2356},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1912,	2,	2358},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1948,	2,	2360},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1984,	2,	2362},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1985,	2,	2364},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2021,	2,	2366},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2057,	2,	2368},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2093,	2,	2370},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2157,	2,	2372},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2158,	3,	2374},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2159,	3,	2377},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2160,	2,	2380},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2161,	2,	2382},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2162,	4,	2384},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2163,	5,	2388},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2164,	4,	2393},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2165,	8,	2397},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2166,	4,	2405},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2167,	5,	2409},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2168,	5,	2414},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2169,	1,	2419},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2170,	18,	2420},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2171,	4,	2438},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2172,	2,	2442},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2173,	6,	2444},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2174,	7,	2450},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2175,	4,	2457},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	9,	2461},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2177,	5,	2470},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	15,	2475},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2179,	4,	2490},
+	{"cvmx_pko_reg_crc_ctl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	3,	2494},
+	{"cvmx_pko_reg_crc_enable"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	2,	2497},
+	{"cvmx_pko_reg_crc_iv#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	2,	2499},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2185,	1,	2501},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2186,	1,	2502},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2187,	1,	2503},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2188,	1,	2504},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2189,	4,	2505},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2190,	5,	2509},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2191,	3,	2514},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2192,	4,	2517},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2193,	2,	2521},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2194,	3,	2523},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2195,	3,	2526},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2196,	13,	2529},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2197,	2,	2542},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2198,	13,	2544},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2199,	3,	2557},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2200,	2,	2560},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2208,	2,	2562},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2209,	2,	2564},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2210,	2,	2566},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2211,	2,	2568},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2212,	10,	2570},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2228,	5,	2580},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2236,	8,	2585},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2244,	2,	2593},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2245,	2,	2595},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2246,	2,	2597},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2254,	3,	2599},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2255,	4,	2602},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2271,	5,	2606},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2272,	7,	2611},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2288,	2,	2618},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2304,	3,	2620},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2305,	7,	2623},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2306,	8,	2630},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2307,	6,	2638},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2308,	2,	2644},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2309,	4,	2646},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2310,	4,	2650},
+	{"cvmx_spx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2311,	2,	2654},
+	{"cvmx_spx#_bist_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2313,	4,	2656},
+	{"cvmx_spx#_clk_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2315,	11,	2660},
+	{"cvmx_spx#_clk_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2317,	9,	2671},
+	{"cvmx_spx#_dbg_deskew_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2319,	16,	2680},
+	{"cvmx_spx#_dbg_deskew_state"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2321,	5,	2696},
+	{"cvmx_spx#_drv_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2323,	5,	2701},
+	{"cvmx_spx#_err_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2325,	6,	2706},
+	{"cvmx_spx#_int_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2327,	6,	2712},
+	{"cvmx_spx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2329,	12,	2718},
+	{"cvmx_spx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2331,	14,	2730},
+	{"cvmx_spx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2333,	12,	2744},
+	{"cvmx_spx#_tpa_acc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2335,	2,	2756},
+	{"cvmx_spx#_tpa_max"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2337,	2,	2758},
+	{"cvmx_spx#_tpa_sel"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2339,	2,	2760},
+	{"cvmx_spx#_trn4_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2341,	8,	2762},
+	{"cvmx_srx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2343,	5,	2770},
+	{"cvmx_srx#_ign_rx_full"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2345,	2,	2775},
+	{"cvmx_srx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	6,	2777},
+	{"cvmx_srx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2411,	4,	2783},
+	{"cvmx_srx#_sw_tick_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2413,	6,	2787},
+	{"cvmx_srx#_sw_tick_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2415,	1,	2793},
+	{"cvmx_stx#_arb_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2417,	5,	2794},
+	{"cvmx_stx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2419,	2,	2799},
+	{"cvmx_stx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2421,	4,	2801},
+	{"cvmx_stx#_dip_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2423,	3,	2805},
+	{"cvmx_stx#_ign_cal"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2425,	2,	2808},
+	{"cvmx_stx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2427,	9,	2810},
+	{"cvmx_stx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2429,	10,	2819},
+	{"cvmx_stx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2431,	9,	2829},
+	{"cvmx_stx#_min_bst"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2433,	2,	2838},
+	{"cvmx_stx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2435,	6,	2840},
+	{"cvmx_stx#_spi4_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2499,	3,	2846},
+	{"cvmx_stx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2501,	4,	2849},
+	{"cvmx_stx#_stat_bytes_hi"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2503,	2,	2853},
+	{"cvmx_stx#_stat_bytes_lo"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2505,	2,	2855},
+	{"cvmx_stx#_stat_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2507,	3,	2857},
+	{"cvmx_stx#_stat_pkt_xmt"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2509,	2,	2860},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2511,	6,	2862},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2512,	3,	2868},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2513,	5,	2871},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2514,	4,	2876},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2515,	6,	2880},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2516,	4,	2886},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2517,	2,	2890},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2518,	4,	2892},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2519,	2,	2896},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2520,	3,	2898},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2521,	4,	2901},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2522,	12,	2905},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2523,	3,	2917},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2524,	5,	2920},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2525,	2,	2925},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2526,	2,	2927},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2527,	18,	2929},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2528,	12,	2947},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2529,	6,	2959},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2530,	5,	2965},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2531,	1,	2970},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2532,	2,	2971},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2533,	2,	2973},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2534,	18,	2975},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2535,	12,	2993},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2536,	6,	3005},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2537,	2,	3011},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2538,	2,	3013},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2539,	18,	3015},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2540,	12,	3033},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2541,	6,	3045},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2542,	3,	3051},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2543,	5,	3054},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2544,	3,	3059},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2545,	6,	3062},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	2546,	2,	3068},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	2547,	2,	3070},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2548,	2,	3072},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT20_EN0"               ,	   0x1070000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT21_EN0"               ,	   0x1070000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT22_EN0"               ,	   0x1070000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT20_EN1"               ,	   0x1070000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT21_EN1"               ,	   0x1070000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT12_EN4_0"             ,	   0x1070000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT13_EN4_0"             ,	   0x1070000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT14_EN4_0"             ,	   0x1070000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT15_EN4_0"             ,	   0x1070000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT12_EN4_1"             ,	   0x1070000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT13_EN4_1"             ,	   0x1070000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT14_EN4_1"             ,	   0x1070000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT15_EN4_1"             ,	   0x1070000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_SUM4"              ,	   0x1070000000C60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_SUM4"              ,	   0x1070000000C68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_SUM4"              ,	   0x1070000000C70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_SUM4"              ,	   0x1070000000C78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET10"              ,	   0x1070000000650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET11"              ,	   0x1070000000658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET12"              ,	   0x1070000000660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET13"              ,	   0x1070000000668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET14"              ,	   0x1070000000670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_MBOX_SET15"              ,	   0x1070000000678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG12"                  ,	   0x1070000000560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	47},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	48},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"DFA_ERR"                     ,	   0x1180030000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"DFA_MEMCFG0"                 ,	   0x1180030000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"DFA_MEMCFG1"                 ,	   0x1180030000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"DFA_MEMCFG2"                 ,	   0x1180030000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"DFA_MEMFADR"                 ,	   0x1180030000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"DFA_MEMFCR"                  ,	   0x1180030000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"DFA_MEMRLD"                  ,	   0x1180030000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"DFA_NCBCTL"                  ,	   0x1180030000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"DFA_RODT_COMP_CTL"           ,	   0x1180030000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"DFA_SBD_DBG0"                ,	   0x1180030000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX000_FRM_MAX"          ,	   0x1180008000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX001_FRM_MAX"          ,	   0x1180008000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX002_FRM_MAX"          ,	   0x1180008001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX003_FRM_MAX"          ,	   0x1180008001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX000_FRM_MAX"          ,	   0x1180010000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX001_FRM_MAX"          ,	   0x1180010000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX002_FRM_MAX"          ,	   0x1180010001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX003_FRM_MAX"          ,	   0x1180010001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX000_FRM_MIN"          ,	   0x1180008000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX001_FRM_MIN"          ,	   0x1180008000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX002_FRM_MIN"          ,	   0x1180008001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX003_FRM_MIN"          ,	   0x1180008001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX000_FRM_MIN"          ,	   0x1180010000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX001_FRM_MIN"          ,	   0x1180010000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX002_FRM_MIN"          ,	   0x1180010001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX003_FRM_MIN"          ,	   0x1180010001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180010000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180010000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180010001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180010001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX003_RX_INBND"         ,	   0x1180008001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX000_RX_INBND"         ,	   0x1180010000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX001_RX_INBND"         ,	   0x1180010000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX002_RX_INBND"         ,	   0x1180010001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX003_RX_INBND"         ,	   0x1180010001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP003"         ,	   0x1180008000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP004"         ,	   0x1180008000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP005"         ,	   0x1180008000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP006"         ,	   0x1180008000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP007"         ,	   0x1180008000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP008"         ,	   0x1180008000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP009"         ,	   0x1180008000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP010"         ,	   0x1180008000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP011"         ,	   0x1180008000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP012"         ,	   0x1180008000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP013"         ,	   0x1180008000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP014"         ,	   0x1180008000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PASS_MAP015"         ,	   0x1180008000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP000"         ,	   0x1180010000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP001"         ,	   0x1180010000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP002"         ,	   0x1180010000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP003"         ,	   0x1180010000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP004"         ,	   0x1180010000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP005"         ,	   0x1180010000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP006"         ,	   0x1180010000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP007"         ,	   0x1180010000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP008"         ,	   0x1180010000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP009"         ,	   0x1180010000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP010"         ,	   0x1180010000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP011"         ,	   0x1180010000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP012"         ,	   0x1180010000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX_SPI_ROUND000"        ,	   0x1180008000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND001"        ,	   0x1180008000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND002"        ,	   0x1180008000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND003"        ,	   0x1180008000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND004"        ,	   0x11800080006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND005"        ,	   0x11800080006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND006"        ,	   0x11800080006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND007"        ,	   0x11800080006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND008"        ,	   0x11800080006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND009"        ,	   0x11800080006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND010"        ,	   0x11800080006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND011"        ,	   0x11800080006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND012"        ,	   0x11800080006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND013"        ,	   0x11800080006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND014"        ,	   0x11800080006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND015"        ,	   0x11800080006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND016"        ,	   0x1180008000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND017"        ,	   0x1180008000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND018"        ,	   0x1180008000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND019"        ,	   0x1180008000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND020"        ,	   0x1180008000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND021"        ,	   0x1180008000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND022"        ,	   0x1180008000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND023"        ,	   0x1180008000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND024"        ,	   0x1180008000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND025"        ,	   0x1180008000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND026"        ,	   0x1180008000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND027"        ,	   0x1180008000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND028"        ,	   0x1180008000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND029"        ,	   0x1180008000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND030"        ,	   0x1180008000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_ROUND031"        ,	   0x1180008000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND000"        ,	   0x1180010000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND001"        ,	   0x1180010000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND002"        ,	   0x1180010000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND003"        ,	   0x1180010000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND004"        ,	   0x11800100006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND005"        ,	   0x11800100006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND006"        ,	   0x11800100006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND007"        ,	   0x11800100006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND008"        ,	   0x11800100006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND009"        ,	   0x11800100006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND010"        ,	   0x11800100006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND011"        ,	   0x11800100006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND012"        ,	   0x11800100006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND013"        ,	   0x11800100006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND014"        ,	   0x11800100006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND015"        ,	   0x11800100006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND016"        ,	   0x1180010000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND017"        ,	   0x1180010000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND018"        ,	   0x1180010000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND019"        ,	   0x1180010000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND020"        ,	   0x1180010000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND021"        ,	   0x1180010000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND022"        ,	   0x1180010000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND023"        ,	   0x1180010000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND024"        ,	   0x1180010000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND025"        ,	   0x1180010000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND026"        ,	   0x1180010000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND027"        ,	   0x1180010000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND028"        ,	   0x1180010000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND029"        ,	   0x1180010000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND030"        ,	   0x1180010000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_SPI_ROUND031"        ,	   0x1180010000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	188},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	189},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	190},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"L2C_SPAR3"                   ,	   0x1180080000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	335},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	336},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	337},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	338},
+	{"NPI_COMP_CTL"                ,	   0x11F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	339},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	340},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	341},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	342},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	343},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	344},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	355},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	365},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	373},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	374},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	375},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	376},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	377},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	378},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	379},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	380},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	381},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	382},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	383},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	394},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	395},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	396},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	397},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	398},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	399},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	400},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	401},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	402},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	403},
+	{"PCI_CNT_REG"                 ,	   0x11F00000011B8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	404},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	405},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	406},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	407},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	408},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	409},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	409},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
+	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
+	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
+	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	410},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	411},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	412},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	413},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	415},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_PKT_CREDITS3"            ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_PKTS_SENT2"              ,	              0x60ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_PKTS_SENT3"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	420},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	421},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	422},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	424},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	425},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	426},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	427},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	428},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	429},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	430},
+	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"PKO_REG_CRC_CTL0"            ,	   0x1180050000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"PKO_REG_CRC_CTL1"            ,	   0x1180050000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"PKO_REG_CRC_ENABLE"          ,	   0x1180050000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"PKO_REG_CRC_IV0"             ,	   0x1180050000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"PKO_REG_CRC_IV1"             ,	   0x1180050000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	500},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	501},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	502},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	503},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	504},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	505},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	506},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	507},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	508},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK12"            ,	   0x1670000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	509},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	512},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	513},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	515},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	517},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	520},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	521},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	522},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	523},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	524},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	525},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	526},
+	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	527},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	528},
+	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	529},
+	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"SPX1_CLK_STAT"               ,	   0x1180098000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"SPX0_DBG_DESKEW_CTL"         ,	   0x1180090000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"SPX1_DBG_DESKEW_CTL"         ,	   0x1180098000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"SPX0_DBG_DESKEW_STATE"       ,	   0x1180090000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SPX1_DBG_DESKEW_STATE"       ,	   0x1180098000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SPX0_DRV_CTL"                ,	   0x1180090000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"SPX1_DRV_CTL"                ,	   0x1180098000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"SPX0_ERR_CTL"                ,	   0x1180090000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"SPX1_ERR_CTL"                ,	   0x1180098000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"SPX0_INT_DAT"                ,	   0x1180090000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"SPX1_INT_DAT"                ,	   0x1180098000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"SPX0_INT_MSK"                ,	   0x1180090000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"SPX1_INT_MSK"                ,	   0x1180098000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"SPX0_INT_REG"                ,	   0x1180090000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"SPX1_INT_REG"                ,	   0x1180098000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"SPX0_INT_SYNC"               ,	   0x1180090000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"SPX1_INT_SYNC"               ,	   0x1180098000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"SPX0_TPA_ACC"                ,	   0x1180090000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"SPX1_TPA_ACC"                ,	   0x1180098000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"SPX0_TPA_MAX"                ,	   0x1180090000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"SPX1_TPA_MAX"                ,	   0x1180098000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"SPX0_TPA_SEL"                ,	   0x1180090000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"SPX1_TPA_SEL"                ,	   0x1180098000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"SPX0_TRN4_CTL"               ,	   0x1180090000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"SPX1_TRN4_CTL"               ,	   0x1180098000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"SRX0_COM_CTL"                ,	   0x1180090000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"SRX1_COM_CTL"                ,	   0x1180098000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"SRX0_IGN_RX_FULL"            ,	   0x1180090000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"SRX1_IGN_RX_FULL"            ,	   0x1180098000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"SRX0_SPI4_CAL000"            ,	   0x1180090000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL001"            ,	   0x1180090000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL002"            ,	   0x1180090000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL003"            ,	   0x1180090000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL004"            ,	   0x1180090000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL005"            ,	   0x1180090000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL006"            ,	   0x1180090000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL007"            ,	   0x1180090000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL008"            ,	   0x1180090000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL009"            ,	   0x1180090000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL010"            ,	   0x1180090000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL011"            ,	   0x1180090000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL012"            ,	   0x1180090000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL013"            ,	   0x1180090000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL014"            ,	   0x1180090000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL015"            ,	   0x1180090000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL016"            ,	   0x1180090000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL003"            ,	   0x1180098000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL004"            ,	   0x1180098000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL005"            ,	   0x1180098000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL006"            ,	   0x1180098000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL007"            ,	   0x1180098000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL008"            ,	   0x1180098000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL009"            ,	   0x1180098000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL010"            ,	   0x1180098000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL011"            ,	   0x1180098000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL012"            ,	   0x1180098000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL013"            ,	   0x1180098000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL014"            ,	   0x1180098000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL015"            ,	   0x1180098000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL016"            ,	   0x1180098000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"SRX0_SW_TICK_CTL"            ,	   0x1180090000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"SRX1_SW_TICK_CTL"            ,	   0x1180098000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"SRX0_SW_TICK_DAT"            ,	   0x1180090000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"SRX1_SW_TICK_DAT"            ,	   0x1180098000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"STX0_ARB_CTL"                ,	   0x1180090000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"STX1_ARB_CTL"                ,	   0x1180098000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"STX0_BCKPRS_CNT"             ,	   0x1180090000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"STX1_BCKPRS_CNT"             ,	   0x1180098000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"STX0_COM_CTL"                ,	   0x1180090000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"STX1_COM_CTL"                ,	   0x1180098000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"STX0_DIP_CNT"                ,	   0x1180090000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL001"            ,	   0x1180090000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL002"            ,	   0x1180090000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL003"            ,	   0x1180090000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL004"            ,	   0x1180090000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL005"            ,	   0x1180090000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL006"            ,	   0x1180090000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL007"            ,	   0x1180090000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL008"            ,	   0x1180090000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL009"            ,	   0x1180090000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL010"            ,	   0x1180090000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL011"            ,	   0x1180090000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL012"            ,	   0x1180090000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL013"            ,	   0x1180090000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL014"            ,	   0x1180090000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL015"            ,	   0x1180090000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL016"            ,	   0x1180090000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL003"            ,	   0x1180098000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL004"            ,	   0x1180098000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL005"            ,	   0x1180098000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL006"            ,	   0x1180098000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL007"            ,	   0x1180098000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL008"            ,	   0x1180098000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL009"            ,	   0x1180098000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL010"            ,	   0x1180098000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL011"            ,	   0x1180098000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL012"            ,	   0x1180098000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL013"            ,	   0x1180098000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL014"            ,	   0x1180098000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL015"            ,	   0x1180098000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL016"            ,	   0x1180098000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"STX1_SPI4_STAT"              ,	   0x1180098000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"STX0_STAT_BYTES_HI"          ,	   0x1180090000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"STX1_STAT_BYTES_HI"          ,	   0x1180098000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"STX0_STAT_BYTES_LO"          ,	   0x1180090000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"STX1_STAT_BYTES_LO"          ,	   0x1180098000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"STX0_STAT_CTL"               ,	   0x1180090000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"STX1_STAT_CTL"               ,	   0x1180098000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"STX0_STAT_PKT_XMT"           ,	   0x1180090000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"STX1_STAT_PKT_XMT"           ,	   0x1180098000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"OVRFLW"                      ,	0,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPOP"                       ,	4,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPSH"                       ,	8,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	4,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	8,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	1,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_LOOP"                    ,	4,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	1,	3,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	3,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	4,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	5,	"RO",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	5,	5,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	5,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	6,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	7,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	7,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	8,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	8,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	9,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	10,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	11,	"RO",	1,	1,	0,	0},
+	{"DFALOCK"                     ,	5,	1,	11,	"RO",	1,	1,	0,	0},
+	{"DFALEAD"                     ,	6,	1,	11,	"RO",	1,	1,	0,	0},
+	{"DFALAG"                      ,	7,	1,	11,	"RO",	1,	1,	0,	0},
+	{"DFASET"                      ,	8,	5,	11,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	11,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	12,	"R/W",	0,	0,	24ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	13,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	13,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	14,	"R/W",	0,	0,	24ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	14,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	15,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_5_7"                ,	5,	3,	15,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	15,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_13_63"              ,	13,	51,	15,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	17,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	17,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	18,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	4,	5,	18,	"R/W",	0,	1,	31ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	18,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	19,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	19,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	20,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	16,	21,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	21,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	16,	22,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	22,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	23,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	24,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	24,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	25,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	25,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	26,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	26,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	27,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	27,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	28,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	28,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	28,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	28,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	28,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	28,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	29,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	29,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	29,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	30,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	30,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	32,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	16,	33,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	33,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	34,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	16,	35,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	35,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	36,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	37,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	15,	37,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	37,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	38,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	39,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	39,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	39,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	39,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	40,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	40,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	41,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	41,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	41,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	42,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	42,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	42,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	42,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	42,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	42,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	42,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	43,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	43,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	43,	"RO",	1,	1,	0,	0},
+	{"REM"                         ,	23,	6,	43,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	43,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	4,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	44,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	16,	4,	44,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	44,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P1_BRF"                      ,	0,	8,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BRF"                      ,	8,	8,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"P1_BWB"                      ,	16,	1,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BWB"                      ,	17,	1,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"CRF"                         ,	18,	1,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	45,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	20,	1,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"IFU"                         ,	21,	1,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	22,	1,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	45,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SARB"                        ,	0,	1,	46,	"R/W",	0,	0,	1ull,	1ull},
+	{"GXOR_ENA"                    ,	1,	1,	46,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXOR_ENA"                    ,	2,	1,	46,	"R/W",	0,	0,	0ull,	0ull},
+	{"NRPL_ENA"                    ,	3,	1,	46,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	46,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	47,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	47,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	48,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	48,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	48,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	48,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	49,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	31,	49,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	49,	"RAZ",	1,	1,	0,	0},
+	{"CP2ECCENA"                   ,	0,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SBE"                      ,	1,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2DBE"                      ,	2,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2SBINA"                    ,	3,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2DBINA"                    ,	4,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SYN"                      ,	5,	8,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEECCENA"                   ,	13,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESBE"                      ,	14,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEDBE"                      ,	15,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTESBINA"                    ,	16,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEDBINA"                    ,	17,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESYN"                      ,	18,	7,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEPARENA"                   ,	25,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEPERR"                     ,	26,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEPINA"                     ,	27,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PARENA"                   ,	28,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PERR"                     ,	29,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2PINA"                     ,	30,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBLOVF"                      ,	31,	1,	50,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBLINA"                      ,	32,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	50,	"RAZ",	1,	1,	0,	0},
+	{"ENA_P1"                      ,	0,	1,	51,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENA_P0"                      ,	1,	1,	51,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	51,	"RAZ",	1,	1,	0,	0},
+	{"MTYPE"                       ,	3,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_LAT"                     ,	4,	2,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"RW_DLY"                      ,	6,	4,	51,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_DLY"                      ,	10,	4,	51,	"R/W",	0,	0,	2ull,	2ull},
+	{"FPRCH"                       ,	14,	2,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	16,	2,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLEN"                        ,	18,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBUNK"                       ,	19,	3,	51,	"R/W",	0,	0,	2ull,	2ull},
+	{"R2R_PBUNK"                   ,	22,	1,	51,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_P1"                     ,	23,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"INIT_P0"                     ,	24,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUNK_INIT"                   ,	25,	2,	51,	"R/W",	0,	0,	3ull,	3ull},
+	{"LPP_ENA"                     ,	27,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDIV"                      ,	28,	2,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"RLDCK_RST"                   ,	30,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"RLDQCK90_RST"                ,	31,	1,	51,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	51,	"RAZ",	1,	1,	0,	0},
+	{"REF_INT"                     ,	0,	4,	52,	"R/W",	0,	0,	3ull,	3ull},
+	{"TSKW"                        ,	4,	2,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	52,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TRL"                         ,	8,	4,	52,	"R/W",	0,	0,	6ull,	6ull},
+	{"TWL"                         ,	12,	4,	52,	"R/W",	0,	0,	7ull,	7ull},
+	{"TRC"                         ,	16,	4,	52,	"R/W",	0,	0,	6ull,	6ull},
+	{"TMRSC"                       ,	20,	3,	52,	"R/W",	0,	0,	6ull,	6ull},
+	{"MRS_ENA"                     ,	23,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"AREF_ENA"                    ,	24,	1,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"REF_INTLO"                   ,	25,	9,	52,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	52,	"RAZ",	1,	1,	0,	0},
+	{"FCRAM2P"                     ,	0,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXBNK"                      ,	1,	1,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"UA_START"                    ,	2,	2,	53,	"R/W",	0,	0,	1ull,	1ull},
+	{"REFSHORT"                    ,	4,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRFC"                        ,	5,	5,	53,	"R/W",	0,	0,	9ull,	9ull},
+	{"SILRST"                      ,	10,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	11,	1,	53,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	53,	"RAZ",	1,	1,	0,	0},
+	{"MADDR"                       ,	0,	24,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"BNUM"                        ,	24,	3,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"PNUM"                        ,	27,	1,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	28,	2,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"FDST"                        ,	30,	9,	54,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	54,	"RAZ",	1,	1,	0,	0},
+	{"MRS"                         ,	0,	15,	55,	"R/W",	0,	0,	66ull,	66ull},
+	{"RESERVED_15_15"              ,	15,	1,	55,	"RAZ",	1,	1,	0,	0},
+	{"EMRS"                        ,	16,	15,	55,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_31_31"              ,	31,	1,	55,	"RAZ",	1,	1,	0,	0},
+	{"EMRS2"                       ,	32,	15,	55,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	55,	"RAZ",	1,	1,	0,	0},
+	{"MRSDAT"                      ,	0,	23,	56,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_23_63"              ,	23,	41,	56,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"DTMODE"                      ,	3,	1,	57,	"R/W",	0,	0,	1ull,	1ull},
+	{"DCMODE"                      ,	4,	1,	57,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDLCK"                      ,	5,	1,	57,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	5,	57,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	57,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	58,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	58,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	58,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	58,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	58,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	58,	"RAZ",	0,	1,	0ull,	0},
+	{"SBD0"                        ,	0,	64,	59,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	60,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	61,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	62,	"RO",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	63,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	63,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	64,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	65,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	65,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	65,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	66,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	66,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	67,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	67,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	67,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	68,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	68,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	69,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	69,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	70,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	70,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	71,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	72,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	72,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	73,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	73,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	73,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	74,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	74,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	74,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	75,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	75,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	76,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	76,	"RAZ",	1,	1,	0,	0},
+	{"OUT_COL"                     ,	0,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_OVR"                     ,	1,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	16,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_21"              ,	18,	4,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	4,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	77,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	77,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	17,	78,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	78,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	79,	"RO",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	79,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	79,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	80,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	80,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	81,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	81,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	81,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	81,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	81,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	82,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	83,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	84,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	85,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	86,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	87,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	88,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	88,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	89,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	89,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	89,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	89,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	90,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	90,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	91,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	91,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	92,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_FREE"                    ,	6,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLAN_LEN"                    ,	7,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	92,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	93,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	93,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	94,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	94,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	95,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	95,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	96,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	97,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	97,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	98,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	98,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	99,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	99,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	100,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	100,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	100,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	100,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	101,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	101,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	102,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	103,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	104,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	105,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	106,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	106,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	107,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	107,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	108,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	108,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	109,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	109,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	110,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	110,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	111,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	111,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	112,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	112,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	113,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	113,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	114,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	114,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	16,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	115,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	4,	116,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	116,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	16,	117,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP"                        ,	16,	16,	117,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	117,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	118,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	118,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	119,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	119,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	120,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	120,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	120,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	121,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	121,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	122,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	122,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	123,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	123,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	124,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	125,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	125,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	126,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	126,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	127,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	127,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	128,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	128,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	129,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	129,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	130,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	130,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	131,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	131,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	133,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	133,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	134,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	134,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	135,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	135,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	142,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	142,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	143,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	143,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	144,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	144,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	145,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	145,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	146,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	146,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	147,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	147,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	147,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	148,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	148,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	148,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	149,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	149,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	149,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	150,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	150,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	151,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	151,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	152,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	153,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	153,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	154,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	154,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	155,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	155,	"RAZ",	1,	1,	0,	0},
+	{"CONT_PKT"                    ,	0,	1,	156,	"R/W",	0,	1,	0ull,	0},
+	{"TPA_CLR"                     ,	1,	1,	156,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	156,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DRAIN"                       ,	0,	16,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	157,	"RAZ",	1,	1,	0,	0},
+	{"MAX1"                        ,	0,	8,	158,	"R/W",	0,	1,	8ull,	0},
+	{"MAX2"                        ,	8,	8,	158,	"R/W",	0,	1,	4ull,	0},
+	{"SLICE"                       ,	16,	7,	158,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	158,	"RAZ",	1,	1,	0,	0},
+	{"ROUND"                       ,	0,	16,	159,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	159,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	6,	160,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	160,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	161,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	161,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	162,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	162,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	163,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	163,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	164,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	164,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	165,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	165,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	166,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	166,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	167,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	167,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	167,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	167,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	167,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	168,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	168,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	168,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	169,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	169,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	169,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	170,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	170,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	171,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	171,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	171,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	171,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	171,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	172,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	172,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	172,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	172,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	172,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	173,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	174,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	175,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	176,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	176,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	177,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	178,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	179,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	179,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	180,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	180,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	180,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	180,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	180,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	181,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	181,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	181,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	181,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	181,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	182,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	183,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	184,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	185,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	186,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	187,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	187,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	188,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	189,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	190,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	191,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	191,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	192,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	194,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	194,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	195,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	195,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	196,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	196,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	197,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	198,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	198,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	199,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	199,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	200,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	201,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	201,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	202,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	202,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	202,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	202,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	202,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	203,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	203,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	203,	"RO",	0,	0,	36ull,	36ull},
+	{"RESERVED_44_63"              ,	44,	20,	203,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	204,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	204,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	205,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	205,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	205,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	205,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	205,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	205,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	205,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	206,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	206,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	207,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	208,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	209,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	209,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	209,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	209,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	210,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	210,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	210,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	211,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	211,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	212,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	212,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	213,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	213,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	214,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	214,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	215,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	216,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	217,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	217,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	13,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	218,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	218,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	219,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	219,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"PICBST"                      ,	2,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RHDB"                        ,	4,	4,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RMDB"                        ,	8,	4,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	220,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	220,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	221,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	221,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	221,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFILL_DIS"                   ,	14,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	221,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	4,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	4,	222,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	222,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	223,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	224,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	224,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	225,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	226,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	227,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	11,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	11,	16,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	228,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	4,	229,	"R/W",	0,	0,	15ull,	15ull},
+	{"STPARTDIS"                   ,	4,	1,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	229,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	230,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	230,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	231,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK4"                       ,	0,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK5"                       ,	8,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK6"                       ,	16,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK7"                       ,	24,	8,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	233,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK8"                       ,	0,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK9"                       ,	8,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK10"                      ,	16,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK11"                      ,	24,	8,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK12"                      ,	0,	8,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK13"                      ,	8,	8,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK14"                      ,	16,	8,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK15"                      ,	24,	8,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	235,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	236,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	237,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	238,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	239,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	240,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	241,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	241,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	241,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	241,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	11,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"FADRU"                       ,	18,	1,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	242,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	243,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	244,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	245,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	246,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	247,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_1024K"                  ,	34,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_512K"                   ,	35,	1,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	248,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	2,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	248,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	10,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"FADRU"                       ,	28,	1,	249,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	249,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RATE"                        ,	0,	8,	250,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_63"               ,	8,	56,	250,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	7,	251,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_7_63"               ,	7,	57,	251,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	0,	16,	252,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	252,	"RAZ",	1,	1,	0,	0},
+	{"DBG_EN"                      ,	0,	1,	253,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	253,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	254,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	254,	"RAZ",	1,	1,	0,	0},
+	{"POLARITY"                    ,	0,	1,	255,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	255,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	8,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	256,	"RAZ",	1,	1,	0,	0},
+	{"FORMAT"                      ,	0,	4,	257,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	257,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	258,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	258,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	259,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	32,	260,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	260,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	32,	261,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	261,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	32,	262,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	262,	"RAZ",	1,	1,	0,	0},
+	{"PCTL_DAT"                    ,	0,	4,	263,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_11"               ,	4,	8,	263,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	263,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	263,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	263,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	263,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	263,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	264,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	264,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	264,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE128B"                    ,	10,	1,	264,	"R/W",	0,	0,	1ull,	1ull},
+	{"DRESET"                      ,	11,	1,	264,	"R/W",	0,	0,	1ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	264,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	264,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	264,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	264,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	264,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	264,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	265,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	265,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	265,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	265,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	266,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	267,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	268,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	268,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	268,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	268,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	268,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	268,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	268,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	268,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	268,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CS_MASK"                     ,	0,	8,	270,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	270,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	270,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	270,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	270,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	271,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	272,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	273,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	274,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	275,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	275,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	275,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	275,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	275,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	275,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	275,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	275,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	275,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	275,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	276,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	276,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	276,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	276,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	276,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	276,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	276,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	276,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	276,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	277,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	278,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	279,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	279,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	279,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	279,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	279,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	279,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	279,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	280,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	280,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	280,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	281,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	281,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	281,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	281,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO1"                    ,	4,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO2"                    ,	8,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO3"                    ,	12,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI0"                    ,	16,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI1"                    ,	20,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI2"                    ,	24,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI3"                    ,	28,	4,	282,	"R/W",	0,	0,	15ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	282,	"RAZ",	1,	1,	0,	0},
+	{"WODT_LO0"                    ,	0,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO1"                    ,	4,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO2"                    ,	8,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO3"                    ,	12,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI0"                    ,	16,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI1"                    ,	20,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI2"                    ,	24,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI3"                    ,	28,	4,	283,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	283,	"RAZ",	1,	1,	0,	0},
+	{"NCBI"                        ,	0,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	284,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	285,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	285,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	285,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	286,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	286,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	286,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	287,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	287,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	287,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	288,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	288,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	288,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	288,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	289,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	290,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	290,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	290,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	290,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_63"              ,	37,	27,	290,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	291,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	291,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	291,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	291,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	292,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	292,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	292,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	292,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	293,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	294,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	294,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	295,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	295,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	16,	296,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	296,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	296,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	296,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	296,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	296,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	296,	"RO",	1,	1,	0,	0},
+	{"NOKASU"                      ,	29,	1,	296,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_63"              ,	30,	34,	296,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	297,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	297,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	297,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	297,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	297,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	297,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	297,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	297,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	2,	298,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	298,	"RAZ",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	299,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	299,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	299,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	300,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	300,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	301,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	301,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	301,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	301,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	301,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	302,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	302,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	302,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	302,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	302,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	303,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	304,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	304,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	2,	305,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	305,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	306,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	306,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	306,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	306,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	306,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	306,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	306,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	306,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	306,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	307,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	307,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	307,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	307,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	307,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	307,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	307,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	307,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	307,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	308,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	308,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	308,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	309,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	309,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	309,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	310,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	311,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	312,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	312,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	313,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	313,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	313,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	313,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	313,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	313,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	313,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	314,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	314,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	315,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	315,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	315,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	316,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	316,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	316,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	316,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	317,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	317,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	317,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	318,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	318,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	318,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	318,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	318,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	318,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	318,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	318,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	318,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	319,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	320,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	320,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	320,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	320,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	320,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	320,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	320,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	320,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	320,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	321,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	321,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	322,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	322,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	323,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	323,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	323,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	323,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	324,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	324,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	325,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	326,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	326,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	327,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	327,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	327,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	327,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	328,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	328,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	329,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	330,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	330,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	331,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	331,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	332,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	332,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	333,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	333,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	334,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	334,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	334,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	334,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	334,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	334,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	335,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	335,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	336,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	336,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"POF3_BS"                     ,	5,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"POF2_BS"                     ,	6,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"POF1_BS"                     ,	7,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"POF0_BS"                     ,	8,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	337,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	338,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	338,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	338,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	339,	"R/W",	0,	1,	16ull,	0},
+	{"PCTL"                        ,	5,	5,	339,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	339,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	340,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	340,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	340,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	340,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"INS1_64B"                    ,	43,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"INS2_64B"                    ,	44,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"INS3_64B"                    ,	45,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"INS0_ENB"                    ,	46,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS1_ENB"                    ,	47,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS2_ENB"                    ,	48,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS3_ENB"                    ,	49,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT0_ENB"                    ,	50,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT1_ENB"                    ,	51,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT2_ENB"                    ,	52,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT3_ENB"                    ,	53,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIS_PNIW"                    ,	54,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	340,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	340,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	341,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	341,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	342,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	342,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	342,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	342,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	342,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	342,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	342,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	342,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	342,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	342,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	342,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	343,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	344,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	344,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	344,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	345,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	345,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	346,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	346,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	346,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	347,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	348,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	349,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	349,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_RR"                      ,	22,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	349,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO1_2SML"                    ,	4,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO2_2SML"                    ,	5,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO3_2SML"                    ,	6,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_RTOUT"                    ,	8,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_RTOUT"                    ,	9,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_RTOUT"                    ,	10,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_OVERF"                    ,	12,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_OVERF"                    ,	13,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_OVERF"                    ,	14,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RTOUT"                    ,	16,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_RTOUT"                    ,	17,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_RTOUT"                    ,	18,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PERR"                     ,	20,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PERR"                     ,	21,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PERR"                     ,	22,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"G1_RTOUT"                    ,	24,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"G2_RTOUT"                    ,	25,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"G3_RTOUT"                    ,	26,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PPERR"                    ,	28,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PPERR"                    ,	29,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PPERR"                    ,	30,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PTOUT"                    ,	32,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PTOUT"                    ,	33,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PTOUT"                    ,	34,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_PPERR"                    ,	36,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_PPERR"                    ,	37,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_PPERR"                    ,	38,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_S_E"                     ,	42,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_A_F"                     ,	43,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_S_E"                     ,	44,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_A_F"                     ,	45,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_S_E"                      ,	46,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_A_F"                      ,	47,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_S_E"                      ,	48,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_A_F"                      ,	49,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_S_E"                     ,	50,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_A_F"                     ,	51,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_S_E"                     ,	52,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_A_F"                     ,	53,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"RWX_S_E"                     ,	54,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDX_S_E"                     ,	55,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_E"                     ,	56,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_F"                     ,	57,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_E"                     ,	58,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_F"                     ,	59,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_S_E"                      ,	60,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_A_F"                      ,	61,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	350,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	351,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO1_2SML"                    ,	4,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO2_2SML"                    ,	5,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO3_2SML"                    ,	6,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_RTOUT"                    ,	8,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_RTOUT"                    ,	9,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_RTOUT"                    ,	10,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_OVERF"                    ,	12,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_OVERF"                    ,	13,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_OVERF"                    ,	14,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RTOUT"                    ,	16,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_RTOUT"                    ,	17,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_RTOUT"                    ,	18,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PERR"                     ,	20,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PERR"                     ,	21,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PERR"                     ,	22,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G1_RTOUT"                    ,	24,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G2_RTOUT"                    ,	25,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G3_RTOUT"                    ,	26,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PPERR"                    ,	28,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PPERR"                    ,	29,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PPERR"                    ,	30,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PTOUT"                    ,	32,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PTOUT"                    ,	33,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PTOUT"                    ,	34,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_PPERR"                    ,	36,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_PPERR"                    ,	37,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_PPERR"                    ,	38,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_S_E"                     ,	42,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_A_F"                     ,	43,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_S_E"                     ,	44,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_A_F"                     ,	45,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_S_E"                      ,	46,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_A_F"                      ,	47,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_S_E"                      ,	48,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_A_F"                      ,	49,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_S_E"                     ,	50,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_A_F"                     ,	51,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_S_E"                     ,	52,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_A_F"                     ,	53,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RWX_S_E"                     ,	54,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDX_S_E"                     ,	55,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_E"                     ,	56,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_F"                     ,	57,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_E"                     ,	58,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_F"                     ,	59,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_S_E"                      ,	60,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_A_F"                      ,	61,	1,	351,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	351,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	352,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	352,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	353,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	353,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	354,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	354,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	354,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	36,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"SHORTL"                      ,	37,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	354,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	355,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	356,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL1"                     ,	4,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL1"                     ,	5,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL1"                     ,	6,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL2"                     ,	8,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL2"                     ,	9,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL2"                     ,	10,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL3"                     ,	12,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL3"                     ,	13,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL3"                     ,	14,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"IPTR_O0"                     ,	16,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O1"                     ,	17,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O2"                     ,	18,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O3"                     ,	19,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_23"              ,	20,	4,	357,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"O1_CSRM"                     ,	25,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"O2_CSRM"                     ,	26,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"O3_CSRM"                     ,	27,	1,	357,	"R/W",	0,	0,	0ull,	1ull},
+	{"O0_RO"                       ,	28,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O1_RO"                       ,	32,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O1_NS"                       ,	33,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O1_ES"                       ,	34,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O2_RO"                       ,	36,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O2_NS"                       ,	37,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O2_ES"                       ,	38,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O3_RO"                       ,	40,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O3_NS"                       ,	41,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"O3_ES"                       ,	42,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"P0_BMODE"                    ,	44,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"P1_BMODE"                    ,	45,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"P2_BMODE"                    ,	46,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"P3_BMODE"                    ,	47,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	48,	1,	357,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	357,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	358,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	358,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	358,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	359,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	359,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	360,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	360,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	361,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	361,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	361,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	362,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	362,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	362,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	363,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	363,	"RAZ",	1,	1,	0,	0},
+	{"PCI_OVR"                     ,	8,	4,	363,	"R/W",	0,	1,	0ull,	0},
+	{"HOSTMODE"                    ,	12,	1,	363,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	363,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	364,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	364,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	365,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	365,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	365,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	365,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	365,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	365,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	366,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	366,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	366,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	366,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	366,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	367,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	367,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	367,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	367,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	367,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	368,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	368,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	368,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	368,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	368,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	368,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	369,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	369,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	369,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_8"                      ,	8,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_13"                     ,	13,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_14"                     ,	14,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_15"                     ,	15,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_21"                     ,	21,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_24"                     ,	24,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_25"                     ,	25,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_26"                     ,	26,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_27"                     ,	27,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_28"                     ,	28,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_29"                     ,	29,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_31"                     ,	31,	1,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	370,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	32,	371,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	371,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	372,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	372,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	373,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	373,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	373,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	373,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	373,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	374,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	374,	"RO",	0,	0,	64ull,	64ull},
+	{"ISAE"                        ,	0,	1,	375,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	375,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	375,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	375,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	375,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	375,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	375,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	375,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	375,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	375,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	375,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	375,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	375,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	375,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	376,	"RO",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	8,	24,	376,	"RO",	0,	0,	733184ull,	733184ull},
+	{"CLS"                         ,	0,	8,	377,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	377,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	377,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	377,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	377,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	378,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	378,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	378,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	379,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	380,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	380,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	380,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	381,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	382,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	382,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	382,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	382,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	383,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	383,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	384,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	385,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	385,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	386,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	386,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	386,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	386,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	387,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	387,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	388,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	388,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	388,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	388,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	389,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	389,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	389,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	390,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	391,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	392,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	392,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	392,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	392,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	392,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	392,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	392,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	393,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	394,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	395,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	395,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	395,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	395,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	395,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	395,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	396,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	396,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	396,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	396,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	396,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	397,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	397,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	397,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	397,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	397,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	397,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	397,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	397,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	397,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	397,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	397,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	397,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	397,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	398,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	398,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	398,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	398,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	398,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	399,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	399,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	399,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	399,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	399,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	399,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	399,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	400,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	400,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	400,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	400,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	400,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	400,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	401,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	401,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	402,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	403,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	403,	"RAZ",	1,	1,	0,	0},
+	{"PCICNT"                      ,	0,	32,	404,	"R/W",	0,	1,	0ull,	0},
+	{"AP_SPEED"                    ,	32,	2,	404,	"RO",	1,	1,	0,	0},
+	{"AP_PCIX"                     ,	34,	1,	404,	"RO",	1,	1,	0,	0},
+	{"HM_SPEED"                    ,	35,	2,	404,	"RO",	0,	1,	0ull,	0},
+	{"HM_PCIX"                     ,	37,	1,	404,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	404,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	405,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	405,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	405,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	405,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	405,	"RO",	0,	1,	0ull,	0},
+	{"AP_PCIX"                     ,	13,	1,	405,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_14"              ,	14,	1,	405,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	405,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	405,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	405,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	405,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	405,	"RO",	0,	0,	1ull,	1ull},
+	{"BB0"                         ,	20,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1"                         ,	21,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_ES"                       ,	22,	2,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_CA"                       ,	24,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_SIZ"                     ,	25,	1,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_HOLE"                    ,	26,	3,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	405,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	406,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	406,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	407,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	408,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	409,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	410,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT1"                      ,	18,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT2"                      ,	19,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT3"                      ,	20,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME1"                     ,	22,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME2"                     ,	23,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME3"                     ,	24,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	411,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT1"                      ,	18,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT2"                      ,	19,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT3"                      ,	20,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME1"                     ,	22,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME2"                     ,	23,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME3"                     ,	24,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	412,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	413,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	413,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	413,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	414,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	414,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	415,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	415,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	416,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	416,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	418,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	419,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	420,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	420,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	420,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	421,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	421,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	421,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	422,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	422,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	422,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	423,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	423,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	423,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	424,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	424,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	425,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	425,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	426,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	3,	45,	426,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	426,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	426,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	427,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	428,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	428,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	428,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	428,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	429,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	430,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	431,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	431,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	431,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	431,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	431,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	432,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	432,	"RAZ",	1,	1,	0,	0},
+	{"REFLECT"                     ,	0,	1,	433,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	433,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	433,	"RAZ",	1,	1,	0,	0},
+	{"IV"                          ,	0,	32,	434,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	434,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	435,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	436,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	436,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	436,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	436,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	437,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	437,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	437,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	437,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKTDRP"                      ,	0,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	438,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	439,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	440,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	441,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	441,	"RAZ",	1,	1,	0,	0},
+	{"CRC_EN"                      ,	12,	1,	441,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	441,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	441,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT"                     ,	20,	4,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	441,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	441,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	442,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	442,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	443,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	443,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	444,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	2,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	445,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	445,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	445,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	445,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	446,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	447,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	448,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	448,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	449,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	449,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	450,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	450,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	451,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	451,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	452,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	452,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	453,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	453,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	454,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	454,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	455,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	455,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	456,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	456,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	457,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	457,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	458,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	458,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	459,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	459,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	460,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	460,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	461,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	461,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	462,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	462,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	463,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	464,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	465,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	465,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	465,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	466,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	466,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	467,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	467,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	468,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	468,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	468,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	468,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	469,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	469,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	469,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	469,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	469,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	470,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	470,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	470,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	471,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	471,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	471,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	471,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	471,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	472,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	472,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	472,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	472,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	473,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	473,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	473,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	473,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	473,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	474,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	474,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	474,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	474,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	474,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	475,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	476,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	476,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	6,	8,	476,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	4,	476,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF_MAX"                 ,	18,	4,	476,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	22,	5,	476,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	27,	3,	476,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	30,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	31,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	32,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	33,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	34,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	35,	1,	476,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	36,	3,	476,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	39,	6,	476,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	45,	16,	476,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	61,	3,	476,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	0,	3,	477,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	3,	16,	477,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	19,	16,	477,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	35,	29,	477,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	0,	11,	478,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	478,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	479,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	479,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	479,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	479,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	479,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	479,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	480,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	480,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	480,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	480,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	480,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	481,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	481,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	482,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	482,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	482,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	482,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	482,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	482,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	482,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	482,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	482,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	483,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	483,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	483,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	483,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	484,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	4,	484,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	484,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	484,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	484,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	6,	484,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	21,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	22,	3,	484,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	25,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	26,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	27,	3,	484,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CRC"                     ,	30,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	31,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	32,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	484,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	485,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	485,	"RAZ",	1,	0,	0,	0ull},
+	{"REFIN"                       ,	0,	1,	486,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	486,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	486,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	32,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	487,	"RAZ",	1,	0,	0,	0ull},
+	{"IV"                          ,	0,	32,	488,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	489,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	490,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	491,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	492,	"RO",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	0,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	493,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	494,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	494,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	495,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	498,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR0"                        ,	0,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR1"                        ,	1,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND0"                       ,	2,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND1"                       ,	3,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	4,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	5,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	6,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	7,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	8,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	9,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	500,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	16,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	500,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	501,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	501,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	502,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	502,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	502,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	502,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	502,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	502,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	502,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	502,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	502,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	503,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	503,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	504,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	504,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	505,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	505,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	506,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	506,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	507,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	507,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	508,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	508,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	509,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	509,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	509,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	510,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	510,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	510,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	510,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	510,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	11,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	11,	511,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	511,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	12,	511,	"RO",	0,	1,	2027ull,	0},
+	{"BUF_CNT"                     ,	36,	12,	511,	"RO",	0,	1,	0ull,	0},
+	{"DES_CNT"                     ,	48,	12,	511,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	511,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	512,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	512,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	513,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	513,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	514,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	514,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	515,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	515,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	515,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	12,	516,	"RO",	0,	1,	0ull,	0},
+	{"DS_CNT"                      ,	12,	12,	516,	"RO",	0,	1,	0ull,	0},
+	{"TC_CNT"                      ,	24,	4,	516,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	516,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	517,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	517,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	517,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	517,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	11,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	518,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	11,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	518,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	518,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	518,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	519,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	519,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	520,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	521,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	522,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	522,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	522,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	522,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	522,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	523,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	523,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	1,	523,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	523,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	524,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	525,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	525,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	525,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	525,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	526,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	526,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	526,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	526,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	527,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STAT0"                       ,	0,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT1"                       ,	1,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT2"                       ,	2,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	528,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRXDLCK"                     ,	0,	1,	529,	"R/W",	0,	0,	0ull,	1ull},
+	{"RCVTRN"                      ,	1,	1,	529,	"R/W",	0,	0,	0ull,	1ull},
+	{"DRPTRN"                      ,	2,	1,	529,	"R/W",	0,	0,	0ull,	1ull},
+	{"SNDTRN"                      ,	3,	1,	529,	"R/W",	0,	0,	0ull,	1ull},
+	{"STATRCV"                     ,	4,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATDRV"                     ,	5,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUNBIST"                     ,	6,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDLY"                      ,	7,	5,	529,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_12_15"              ,	12,	4,	529,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SEETRN"                      ,	16,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	529,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	530,	"RAZ",	0,	1,	0ull,	0},
+	{"D4CLK0"                      ,	4,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"D4CLK1"                      ,	5,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK0"                      ,	6,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK1"                      ,	7,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"SRXTRN"                      ,	8,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_9"                ,	9,	1,	530,	"RAZ",	0,	1,	0ull,	0},
+	{"STXCAL"                      ,	10,	1,	530,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLLDIS"                      ,	0,	1,	531,	"R/W",	1,	0,	0,	0ull},
+	{"DLLFRC"                      ,	1,	1,	531,	"WR0",	1,	0,	0,	0ull},
+	{"OFFDLY"                      ,	2,	6,	531,	"R/W",	1,	0,	0,	0ull},
+	{"BITSEL"                      ,	8,	5,	531,	"R/W",	1,	1,	0,	0},
+	{"OFFSET"                      ,	13,	5,	531,	"R/W",	1,	1,	0,	0},
+	{"MUX"                         ,	18,	1,	531,	"WR0",	1,	1,	0,	0},
+	{"INC"                         ,	19,	1,	531,	"WR0",	1,	1,	0,	0},
+	{"DEC"                         ,	20,	1,	531,	"WR0",	1,	1,	0,	0},
+	{"CLRDLY"                      ,	21,	1,	531,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_22_23"              ,	22,	2,	531,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SSTEP"                       ,	24,	1,	531,	"R/W",	1,	0,	0,	0ull},
+	{"SSTEP_GO"                    ,	25,	1,	531,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_26_27"              ,	26,	2,	531,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FALL8"                       ,	28,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALLNOP"                     ,	29,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	531,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	5,	532,	"RO",	0,	1,	0ull,	0},
+	{"MUXSEL"                      ,	5,	2,	532,	"RO",	0,	1,	0ull,	0},
+	{"UNXTERM"                     ,	7,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TESTRES"                     ,	8,	1,	532,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	532,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRX4CMP"                     ,	0,	10,	533,	"R/W",	0,	0,	239ull,	239ull},
+	{"RESERVED_10_15"              ,	10,	6,	533,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX4PCMP"                    ,	16,	4,	533,	"R/W",	0,	0,	3ull,	3ull},
+	{"STX4NCMP"                    ,	20,	4,	533,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_24_63"              ,	24,	40,	533,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ERRCNT"                      ,	0,	4,	534,	"R/W",	0,	0,	0ull,	3ull},
+	{"RESERVED_4_5"                ,	4,	2,	534,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPPAY"                      ,	6,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPCLS"                      ,	7,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	8,	1,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	534,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT"                         ,	0,	8,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RSVOP"                       ,	8,	4,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"CALBNK"                      ,	12,	2,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_30"              ,	14,	17,	535,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUL"                         ,	31,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	535,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	536,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	536,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_30"              ,	12,	19,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPF"                         ,	31,	1,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	538,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	538,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	538,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	539,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	539,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX"                         ,	0,	32,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	540,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTSEL"                      ,	0,	4,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	541,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUX_EN"                      ,	0,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"MACRO_EN"                    ,	1,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXDIST"                     ,	2,	5,	542,	"R/W",	0,	0,	0ull,	8ull},
+	{"SET_BOOT"                    ,	7,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR_BOOT"                    ,	8,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"JITTER"                      ,	9,	3,	542,	"R/W",	0,	0,	0ull,	1ull},
+	{"TRNTEST"                     ,	12,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	542,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	543,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	543,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	543,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRTS"                        ,	4,	4,	543,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	543,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNORE"                      ,	0,	16,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	544,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	545,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	545,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	545,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	546,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	546,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	546,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	546,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	4,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC"                         ,	4,	4,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOD"                         ,	8,	4,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_2"                ,	0,	3,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	3,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINTRN"                      ,	5,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	549,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	550,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	550,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	551,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	551,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	551,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	551,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPMAX"                      ,	0,	4,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMMAX"                      ,	4,	4,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	552,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	0,	16,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	553,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	554,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	555,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	8,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	555,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALPAR1"                     ,	1,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRBST"                      ,	2,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATOVR"                      ,	3,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	4,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"NOSYNC"                      ,	5,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNXFRM"                      ,	6,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMERR"                      ,	7,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	556,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MINB"                        ,	0,	9,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	557,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	558,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	558,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	558,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	558,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	558,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	558,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_T"                       ,	0,	16,	559,	"R/W",	0,	1,	0ull,	0},
+	{"ALPHA"                       ,	16,	16,	559,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	559,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	560,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	560,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	560,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	560,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	561,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	561,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	562,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	0,	4,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	4,	1,	563,	"WR0",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	563,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	564,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	0,	22,	565,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	565,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	565,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	565,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	565,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	565,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	566,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	566,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	566,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	567,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	567,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	567,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	567,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	567,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	568,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	569,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	570,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	570,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	570,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	570,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	571,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	572,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	572,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	573,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	574,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	575,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	576,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	12,	10,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	24,	40,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	579,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	579,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	580,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	581,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	581,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	582,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	582,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	582,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	582,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	582,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	583,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	584,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	584,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	584,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	584,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	584,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	586,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	586,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	587,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	588,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	588,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	589,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	589,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	589,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	589,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	589,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	590,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	591,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	591,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	592,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	592,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	593,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	593,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	594,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	594,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	594,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	594,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	594,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	595,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP_CTL"                     ,	0,	4,	596,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	596,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	596,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	597,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	598,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	598,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	599,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	599,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	599,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	599,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	599,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	599,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	600,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	600,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	601,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	601,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	602,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	4,	0},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	4,	4},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	3,	8},
+	{"cvmx_asx#_rld_bypass"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	2,	11},
+	{"cvmx_asx#_rld_bypass_setting",	CVMX_CSR_DB_TYPE_RSL,	64,	8,	2,	13},
+	{"cvmx_asx#_rld_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	3,	15},
+	{"cvmx_asx#_rld_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	3,	18},
+	{"cvmx_asx#_rld_nctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	21},
+	{"cvmx_asx#_rld_nctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	23},
+	{"cvmx_asx#_rld_pctl_strong"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	25},
+	{"cvmx_asx#_rld_pctl_weak"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	2,	27},
+	{"cvmx_asx#_rld_setting"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	6,	29},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	35},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	2,	37},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	39},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	4,	41},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	45},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	47},
+	{"cvmx_asx0_dbg_data_drv"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	3,	49},
+	{"cvmx_asx0_dbg_data_enable"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	55,	2,	52},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	56,	2,	54},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	57,	2,	56},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	58,	2,	58},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	59,	2,	60},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	60,	15,	62},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	93,	15,	77},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	126,	15,	92},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	159,	2,	107},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	192,	2,	109},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	225,	2,	111},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	258,	15,	113},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	274,	15,	128},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	290,	15,	143},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	306,	2,	158},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	322,	2,	160},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	338,	2,	162},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	354,	15,	164},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	387,	15,	179},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	403,	2,	194},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	404,	2,	196},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	420,	2,	198},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	436,	2,	200},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	437,	2,	202},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	438,	2,	204},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	439,	1,	206},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	455,	3,	207},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	456,	2,	210},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	457,	4,	212},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	458,	2,	216},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	459,	3,	218},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	463,	7,	221},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	479,	5,	228},
+	{"cvmx_dfa_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	480,	4,	233},
+	{"cvmx_dfa_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	481,	10,	237},
+	{"cvmx_dfa_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	482,	5,	247},
+	{"cvmx_dfa_dbell"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	483,	2,	252},
+	{"cvmx_dfa_difctl"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	484,	4,	254},
+	{"cvmx_dfa_difrdptr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	485,	3,	258},
+	{"cvmx_dfa_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	486,	21,	261},
+	{"cvmx_dfa_memcfg0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	487,	20,	282},
+	{"cvmx_dfa_memcfg1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	488,	11,	302},
+	{"cvmx_dfa_memcfg2"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	489,	8,	313},
+	{"cvmx_dfa_memfadr"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	490,	6,	321},
+	{"cvmx_dfa_memfcr"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	491,	6,	327},
+	{"cvmx_dfa_memrld"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	492,	2,	333},
+	{"cvmx_dfa_ncbctl"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	493,	8,	335},
+	{"cvmx_dfa_rodt_comp_ctl"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	494,	6,	343},
+	{"cvmx_dfa_sbd_dbg0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	495,	1,	349},
+	{"cvmx_dfa_sbd_dbg1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	496,	1,	350},
+	{"cvmx_dfa_sbd_dbg2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	497,	1,	351},
+	{"cvmx_dfa_sbd_dbg3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	498,	1,	352},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	499,	6,	353},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	500,	7,	359},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	501,	3,	366},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	508,	2,	369},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	515,	3,	371},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	516,	2,	374},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	517,	29,	376},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	518,	29,	405},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	519,	2,	434},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	527,	2,	436},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	535,	3,	438},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	536,	3,	441},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	537,	2,	444},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	538,	2,	446},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	539,	8,	448},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	541,	2,	456},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	543,	3,	458},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	545,	2,	461},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	547,	5,	463},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	555,	1,	468},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	563,	1,	469},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	571,	1,	470},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	579,	1,	471},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	587,	1,	472},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	595,	1,	473},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	603,	2,	474},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	611,	4,	476},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	619,	2,	480},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	627,	11,	482},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	635,	12,	493},
+	{"cvmx_gmx#_rx#_frm_max"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	643,	2,	505},
+	{"cvmx_gmx#_rx#_frm_min"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	651,	2,	507},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	659,	2,	509},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	667,	21,	511},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	675,	21,	532},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	683,	2,	553},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	691,	2,	555},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	699,	4,	557},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	707,	2,	561},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	715,	2,	563},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	723,	2,	565},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	731,	2,	567},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	739,	2,	569},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	747,	2,	571},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	755,	2,	573},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	763,	2,	575},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	771,	2,	577},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	779,	2,	579},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	787,	4,	581},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	795,	2,	585},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	2,	587},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	811,	2,	589},
+	{"cvmx_gmx#_rx_pass_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	819,	2,	591},
+	{"cvmx_gmx#_rx_pass_map#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	821,	2,	593},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	853,	3,	595},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	855,	2,	598},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	857,	2,	600},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	865,	3,	602},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	867,	5,	605},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	875,	2,	610},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	883,	2,	612},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	891,	3,	614},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	899,	2,	617},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	907,	2,	619},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	915,	2,	621},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	923,	2,	623},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	931,	2,	625},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	939,	2,	627},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	947,	2,	629},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	955,	2,	631},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	963,	2,	633},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	971,	2,	635},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	979,	2,	637},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	987,	2,	639},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	995,	2,	641},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	2,	643},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1011,	2,	645},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	2,	647},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	2,	649},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1035,	2,	651},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1043,	2,	653},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1051,	2,	655},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1053,	2,	657},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1055,	2,	659},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1057,	3,	661},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	8,	664},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1061,	8,	672},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1063,	2,	680},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1065,	2,	682},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1067,	4,	684},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1069,	2,	688},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1071,	2,	690},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1073,	2,	692},
+	{"cvmx_gmx#_tx_spi_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1075,	3,	694},
+	{"cvmx_gmx#_tx_spi_drain"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1077,	2,	697},
+	{"cvmx_gmx#_tx_spi_max"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1079,	4,	699},
+	{"cvmx_gmx#_tx_spi_round#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1081,	2,	703},
+	{"cvmx_gmx#_tx_spi_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1145,	2,	705},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1147,	7,	707},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1163,	2,	714},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1164,	2,	716},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1165,	2,	718},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1166,	2,	720},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	19,	722},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	6,	741},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	3,	747},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	3,	750},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	3,	753},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	5,	756},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1173,	5,	761},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1174,	1,	766},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	1,	767},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1176,	7,	768},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1177,	7,	775},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1178,	3,	782},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1179,	3,	785},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1180,	3,	788},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1181,	5,	791},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1182,	5,	796},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	1,	801},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	1184,	1,	802},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1185,	3,	803},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1186,	3,	806},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1187,	3,	809},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1188,	2,	812},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1189,	2,	814},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1190,	2,	816},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1191,	2,	818},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1192,	17,	820},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1193,	2,	837},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1194,	1,	839},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1195,	12,	840},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1196,	11,	852},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1197,	11,	863},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1198,	2,	874},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1199,	2,	876},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1200,	2,	878},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1201,	3,	880},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1237,	2,	883},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1273,	6,	885},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1274,	5,	891},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1275,	6,	896},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1276,	7,	902},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1277,	2,	909},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1285,	2,	911},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1286,	3,	913},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1287,	5,	916},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1295,	3,	921},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1296,	2,	924},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1297,	2,	926},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1298,	2,	928},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1299,	4,	930},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1300,	3,	934},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1301,	5,	937},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1302,	5,	942},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1303,	7,	947},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1304,	5,	954},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1305,	8,	959},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1306,	13,	967},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1307,	8,	980},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1308,	5,	988},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1309,	4,	993},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1310,	2,	997},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1311,	14,	999},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1312,	19,	1013},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1313,	3,	1032},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1314,	3,	1035},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1315,	2,	1038},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1319,	17,	1040},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1320,	5,	1057},
+	{"cvmx_l2c_spar1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1321,	5,	1062},
+	{"cvmx_l2c_spar2"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1322,	5,	1067},
+	{"cvmx_l2c_spar3"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1323,	5,	1072},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1324,	2,	1077},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	3,	1079},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1326,	2,	1082},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1327,	2,	1084},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1328,	2,	1086},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1329,	7,	1088},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1330,	5,	1095},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1331,	3,	1100},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1332,	3,	1103},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1333,	2,	1106},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1334,	2,	1108},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1335,	2,	1110},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1336,	6,	1112},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1337,	14,	1118},
+	{"cvmx_led_blink"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1338,	2,	1132},
+	{"cvmx_led_clk_phase"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1339,	2,	1134},
+	{"cvmx_led_cylon"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1340,	2,	1136},
+	{"cvmx_led_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1341,	2,	1138},
+	{"cvmx_led_en"                 ,	CVMX_CSR_DB_TYPE_RSL,	64,	1342,	2,	1140},
+	{"cvmx_led_polarity"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1343,	2,	1142},
+	{"cvmx_led_prt"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1344,	2,	1144},
+	{"cvmx_led_prt_fmt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1345,	2,	1146},
+	{"cvmx_led_prt_status#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1346,	2,	1148},
+	{"cvmx_led_udd_cnt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1354,	2,	1150},
+	{"cvmx_led_udd_dat#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1356,	2,	1152},
+	{"cvmx_led_udd_dat_clr#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1358,	2,	1154},
+	{"cvmx_led_udd_dat_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1360,	2,	1156},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1362,	7,	1158},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1363,	19,	1165},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1364,	4,	1184},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1365,	2,	1188},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1366,	2,	1190},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1367,	18,	1192},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1368,	6,	1210},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1369,	5,	1216},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1370,	5,	1221},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1371,	6,	1226},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1372,	2,	1232},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1373,	2,	1234},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	14,	1236},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1375,	9,	1250},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1376,	2,	1259},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1377,	2,	1261},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1378,	2,	1263},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1379,	12,	1265},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1380,	6,	1277},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1381,	6,	1283},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1382,	9,	1289},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1383,	9,	1298},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1384,	4,	1307},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1385,	3,	1311},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1386,	3,	1314},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1387,	3,	1317},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1388,	5,	1320},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1390,	1,	1325},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1391,	10,	1326},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1399,	13,	1336},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1407,	4,	1349},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1408,	1,	1353},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1412,	2,	1354},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1413,	2,	1356},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1414,	9,	1358},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1415,	8,	1367},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1416,	2,	1375},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1417,	1,	1377},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1418,	3,	1378},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1419,	2,	1381},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1420,	6,	1383},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1421,	8,	1389},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1422,	4,	1397},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1423,	2,	1401},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1424,	2,	1403},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1425,	13,	1405},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1426,	12,	1418},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1427,	3,	1430},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1428,	3,	1433},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1429,	2,	1436},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1431,	2,	1438},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1433,	2,	1440},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1435,	7,	1442},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1437,	2,	1449},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1439,	7,	1451},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1441,	4,	1458},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1443,	8,	1462},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1445,	9,	1470},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1447,	7,	1479},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1449,	9,	1486},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1451,	2,	1495},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1453,	2,	1497},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1455,	4,	1499},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1457,	2,	1503},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1459,	2,	1505},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1461,	2,	1507},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1463,	4,	1509},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1465,	2,	1513},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1467,	2,	1515},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1469,	2,	1517},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1471,	2,	1519},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1473,	2,	1521},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1475,	2,	1523},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1477,	6,	1525},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1479,	2,	1531},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1483,	2,	1533},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1487,	21,	1535},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1488,	3,	1556},
+	{"cvmx_npi_comp_ctl"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1492,	3,	1559},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1493,	21,	1562},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1494,	2,	1583},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1495,	13,	1585},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1496,	3,	1598},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1497,	3,	1601},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1498,	3,	1604},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1499,	3,	1607},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1500,	2,	1610},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1501,	2,	1612},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1502,	10,	1614},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1503,	63,	1624},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1504,	63,	1687},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1505,	2,	1750},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1506,	2,	1752},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1507,	10,	1754},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1511,	1,	1764},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1512,	2,	1765},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1516,	39,	1767},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1517,	3,	1806},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1521,	2,	1809},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1525,	3,	1811},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1529,	3,	1814},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1533,	3,	1817},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1534,	7,	1820},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1535,	2,	1827},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1536,	13,	1829},
+	{"cvmx_npi_port33_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1537,	13,	1842},
+	{"cvmx_npi_port34_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1538,	13,	1855},
+	{"cvmx_npi_port35_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1539,	13,	1868},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1540,	3,	1881},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1541,	33,	1884},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1542,	2,	1917},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1546,	2,	1919},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1547,	5,	1921},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1579,	2,	1926},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1580,	24,	1928},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1581,	2,	1952},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1582,	7,	1954},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1583,	5,	1961},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1584,	1,	1966},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1585,	5,	1967},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1586,	1,	1972},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1587,	4,	1973},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1588,	2,	1977},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1589,	1,	1979},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1590,	2,	1980},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1591,	4,	1982},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1592,	2,	1986},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1593,	4,	1988},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1594,	16,	1992},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1595,	1,	2008},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1596,	1,	2009},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1597,	18,	2010},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1598,	1,	2028},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1599,	1,	2029},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1600,	7,	2030},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1601,	7,	2037},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1602,	13,	2044},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1603,	10,	2057},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1604,	10,	2067},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1605,	7,	2077},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1606,	2,	2084},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1607,	1,	2086},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	1608,	2,	2087},
+	{"cvmx_pci_cnt_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1609,	6,	2089},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1610,	22,	2095},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	1611,	2,	2117},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	1615,	1,	2119},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1617,	1,	2120},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	1619,	1,	2121},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1621,	1,	2122},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1625,	35,	2123},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1626,	35,	2158},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	1627,	35,	2193},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1628,	35,	2228},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	1629,	2,	2263},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	1630,	2,	2265},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	1634,	1,	2267},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	1638,	1,	2268},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	1642,	1,	2269},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1646,	3,	2270},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1647,	3,	2273},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	1648,	3,	2276},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1649,	3,	2279},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1650,	2,	2282},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	1651,	2,	2284},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1652,	4,	2286},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1653,	1,	2290},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1654,	4,	2291},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1655,	1,	2295},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	1656,	2,	2296},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1657,	5,	2298},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1658,	2,	2303},
+	{"cvmx_pip_crc_ctl#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1659,	3,	2305},
+	{"cvmx_pip_crc_iv#"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1661,	2,	2308},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1663,	4,	2310},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1667,	8,	2314},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1668,	16,	2322},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1669,	12,	2338},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1670,	12,	2350},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1671,	2,	2362},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1672,	19,	2364},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1708,	25,	2383},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1744,	2,	2408},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	2,	2410},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1816,	9,	2412},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1820,	2,	2421},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1821,	2,	2423},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1822,	2,	2425},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1858,	2,	2427},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1894,	2,	2429},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1930,	2,	2431},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1966,	2,	2433},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2002,	2,	2435},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2038,	2,	2437},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2074,	2,	2439},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2110,	2,	2441},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2146,	2,	2443},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	2,	2445},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	2,	2447},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2219,	2,	2449},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2255,	2,	2451},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2291,	2,	2453},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	2,	2455},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	3,	2457},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	3,	2460},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	2463},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	2,	2465},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	4,	2467},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	5,	2471},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	4,	2476},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	8,	2480},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	4,	2488},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	5,	2492},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	5,	2497},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	1,	2502},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2368,	18,	2503},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2369,	4,	2521},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2370,	2,	2525},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2371,	6,	2527},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2372,	7,	2533},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2373,	4,	2540},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2374,	9,	2544},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	5,	2553},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2376,	15,	2558},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	4,	2573},
+	{"cvmx_pko_reg_crc_ctl#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	3,	2577},
+	{"cvmx_pko_reg_crc_enable"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	2,	2580},
+	{"cvmx_pko_reg_crc_iv#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	2,	2582},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2383,	1,	2584},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2384,	1,	2585},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2385,	1,	2586},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2386,	1,	2587},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2387,	4,	2588},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2388,	5,	2592},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2389,	3,	2597},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2390,	4,	2600},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2391,	2,	2604},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2392,	3,	2606},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2393,	3,	2609},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2394,	13,	2612},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2395,	2,	2625},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2396,	13,	2627},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2397,	3,	2640},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2398,	2,	2643},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2406,	2,	2645},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2407,	2,	2647},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2408,	2,	2649},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2409,	2,	2651},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2410,	10,	2653},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2426,	5,	2663},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2434,	8,	2668},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2442,	2,	2676},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2443,	2,	2678},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2444,	2,	2680},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2452,	3,	2682},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2453,	4,	2685},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2469,	5,	2689},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2470,	7,	2694},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2486,	2,	2701},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2502,	3,	2703},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2503,	7,	2706},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2504,	8,	2713},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2505,	6,	2721},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2506,	2,	2727},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2507,	4,	2729},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2508,	4,	2733},
+	{"cvmx_spx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2509,	2,	2737},
+	{"cvmx_spx#_bist_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2511,	4,	2739},
+	{"cvmx_spx#_clk_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2513,	11,	2743},
+	{"cvmx_spx#_clk_stat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2515,	9,	2754},
+	{"cvmx_spx#_dbg_deskew_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2517,	16,	2763},
+	{"cvmx_spx#_dbg_deskew_state"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2519,	5,	2779},
+	{"cvmx_spx#_drv_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2521,	5,	2784},
+	{"cvmx_spx#_err_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2523,	6,	2789},
+	{"cvmx_spx#_int_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2525,	6,	2795},
+	{"cvmx_spx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2527,	12,	2801},
+	{"cvmx_spx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2529,	14,	2813},
+	{"cvmx_spx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2531,	12,	2827},
+	{"cvmx_spx#_tpa_acc"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2533,	2,	2839},
+	{"cvmx_spx#_tpa_max"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2535,	2,	2841},
+	{"cvmx_spx#_tpa_sel"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2537,	2,	2843},
+	{"cvmx_spx#_trn4_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2539,	8,	2845},
+	{"cvmx_srx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2541,	5,	2853},
+	{"cvmx_srx#_ign_rx_full"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2543,	2,	2858},
+	{"cvmx_srx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2545,	6,	2860},
+	{"cvmx_srx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2609,	4,	2866},
+	{"cvmx_srx#_sw_tick_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2611,	6,	2870},
+	{"cvmx_srx#_sw_tick_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2613,	1,	2876},
+	{"cvmx_stx#_arb_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2615,	5,	2877},
+	{"cvmx_stx#_bckprs_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2617,	2,	2882},
+	{"cvmx_stx#_com_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2619,	4,	2884},
+	{"cvmx_stx#_dip_cnt"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2621,	3,	2888},
+	{"cvmx_stx#_ign_cal"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2623,	2,	2891},
+	{"cvmx_stx#_int_msk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2625,	9,	2893},
+	{"cvmx_stx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2627,	10,	2902},
+	{"cvmx_stx#_int_sync"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2629,	9,	2912},
+	{"cvmx_stx#_min_bst"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2631,	2,	2921},
+	{"cvmx_stx#_spi4_cal#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2633,	6,	2923},
+	{"cvmx_stx#_spi4_dat"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2697,	3,	2929},
+	{"cvmx_stx#_spi4_stat"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2699,	4,	2932},
+	{"cvmx_stx#_stat_bytes_hi"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2701,	2,	2936},
+	{"cvmx_stx#_stat_bytes_lo"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2703,	2,	2938},
+	{"cvmx_stx#_stat_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2705,	3,	2940},
+	{"cvmx_stx#_stat_pkt_xmt"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2707,	2,	2943},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2709,	6,	2945},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2710,	3,	2951},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2711,	5,	2954},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2712,	4,	2959},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2713,	6,	2963},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2714,	4,	2969},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2715,	2,	2973},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2716,	4,	2975},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2717,	2,	2979},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2718,	3,	2981},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2719,	4,	2984},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2720,	12,	2988},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2721,	3,	3000},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2722,	5,	3003},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2723,	2,	3008},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2724,	2,	3010},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2725,	18,	3012},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2726,	12,	3030},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2727,	6,	3042},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2728,	5,	3048},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2729,	1,	3053},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2730,	2,	3054},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2731,	2,	3056},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2732,	18,	3058},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2733,	12,	3076},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2734,	6,	3088},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2735,	2,	3094},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2736,	2,	3096},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2737,	18,	3098},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2738,	12,	3116},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2739,	6,	3128},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2740,	3,	3134},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2741,	5,	3137},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2742,	3,	3142},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2743,	6,	3145},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	2744,	2,	3151},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	2745,	2,	3153},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2746,	2,	3155},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX1_INT_EN"                 ,	   0x11800B8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX1_INT_REG"                ,	   0x11800B8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX1_PRT_LOOP"               ,	   0x11800B8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_RLD_BYPASS"             ,	   0x11800B0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX1_RLD_BYPASS"             ,	   0x11800B8000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_RLD_BYPASS_SETTING"     ,	   0x11800B0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX1_RLD_BYPASS_SETTING"     ,	   0x11800B8000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_RLD_COMP"               ,	   0x11800B0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX1_RLD_COMP"               ,	   0x11800B8000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RLD_DATA_DRV"           ,	   0x11800B0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX1_RLD_DATA_DRV"           ,	   0x11800B8000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RLD_NCTL_STRONG"        ,	   0x11800B0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX1_RLD_NCTL_STRONG"        ,	   0x11800B8000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_RLD_NCTL_WEAK"          ,	   0x11800B0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX1_RLD_NCTL_WEAK"          ,	   0x11800B8000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_RLD_PCTL_STRONG"        ,	   0x11800B0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX1_RLD_PCTL_STRONG"        ,	   0x11800B8000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_RLD_PCTL_WEAK"          ,	   0x11800B0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX1_RLD_PCTL_WEAK"          ,	   0x11800B8000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_RLD_SETTING"            ,	   0x11800B0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX1_RLD_SETTING"            ,	   0x11800B8000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_CLK_SET003"          ,	   0x11800B0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET000"          ,	   0x11800B8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET001"          ,	   0x11800B8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET002"          ,	   0x11800B8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX1_RX_CLK_SET003"          ,	   0x11800B8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX1_RX_PRT_EN"              ,	   0x11800B8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_CLK_SET003"          ,	   0x11800B0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET000"          ,	   0x11800B8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET001"          ,	   0x11800B8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET002"          ,	   0x11800B8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX1_TX_CLK_SET003"          ,	   0x11800B8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX1_TX_COMP_BYP"            ,	   0x11800B8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_HI_WATER003"         ,	   0x11800B0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER000"         ,	   0x11800B8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER001"         ,	   0x11800B8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER002"         ,	   0x11800B8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX1_TX_HI_WATER003"         ,	   0x11800B8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX1_TX_PRT_EN"              ,	   0x11800B8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"ASX0_DBG_DATA_DRV"           ,	   0x11800B0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"ASX0_DBG_DATA_ENABLE"        ,	   0x11800B0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT20_EN0"               ,	   0x1070000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT21_EN0"               ,	   0x1070000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT22_EN0"               ,	   0x1070000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT24_EN0"               ,	   0x1070000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT25_EN0"               ,	   0x1070000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT26_EN0"               ,	   0x10700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT27_EN0"               ,	   0x10700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT28_EN0"               ,	   0x10700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT29_EN0"               ,	   0x10700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT30_EN0"               ,	   0x10700000003E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT31_EN0"               ,	   0x10700000003F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT16_EN0_W1C"           ,	   0x1070000002300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT17_EN0_W1C"           ,	   0x1070000002310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT18_EN0_W1C"           ,	   0x1070000002320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT19_EN0_W1C"           ,	   0x1070000002330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT20_EN0_W1C"           ,	   0x1070000002340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT21_EN0_W1C"           ,	   0x1070000002350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT22_EN0_W1C"           ,	   0x1070000002360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT23_EN0_W1C"           ,	   0x1070000002370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT24_EN0_W1C"           ,	   0x1070000002380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT25_EN0_W1C"           ,	   0x1070000002390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT26_EN0_W1C"           ,	   0x10700000023A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT27_EN0_W1C"           ,	   0x10700000023B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT28_EN0_W1C"           ,	   0x10700000023C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT29_EN0_W1C"           ,	   0x10700000023D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT30_EN0_W1C"           ,	   0x10700000023E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT31_EN0_W1C"           ,	   0x10700000023F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT16_EN0_W1S"           ,	   0x1070000006300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT17_EN0_W1S"           ,	   0x1070000006310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT18_EN0_W1S"           ,	   0x1070000006320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT19_EN0_W1S"           ,	   0x1070000006330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT20_EN0_W1S"           ,	   0x1070000006340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT21_EN0_W1S"           ,	   0x1070000006350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT22_EN0_W1S"           ,	   0x1070000006360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT23_EN0_W1S"           ,	   0x1070000006370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT24_EN0_W1S"           ,	   0x1070000006380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT25_EN0_W1S"           ,	   0x1070000006390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT26_EN0_W1S"           ,	   0x10700000063A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT27_EN0_W1S"           ,	   0x10700000063B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT28_EN0_W1S"           ,	   0x10700000063C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT29_EN0_W1S"           ,	   0x10700000063D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT30_EN0_W1S"           ,	   0x10700000063E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT31_EN0_W1S"           ,	   0x10700000063F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT20_EN1"               ,	   0x1070000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT21_EN1"               ,	   0x1070000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT24_EN1"               ,	   0x1070000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT25_EN1"               ,	   0x1070000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT26_EN1"               ,	   0x10700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT27_EN1"               ,	   0x10700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT28_EN1"               ,	   0x10700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT29_EN1"               ,	   0x10700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT30_EN1"               ,	   0x10700000003E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT31_EN1"               ,	   0x10700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT16_EN1_W1C"           ,	   0x1070000002308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT17_EN1_W1C"           ,	   0x1070000002318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT18_EN1_W1C"           ,	   0x1070000002328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT19_EN1_W1C"           ,	   0x1070000002338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT20_EN1_W1C"           ,	   0x1070000002348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT21_EN1_W1C"           ,	   0x1070000002358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT22_EN1_W1C"           ,	   0x1070000002368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT23_EN1_W1C"           ,	   0x1070000002378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT24_EN1_W1C"           ,	   0x1070000002388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT25_EN1_W1C"           ,	   0x1070000002398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT26_EN1_W1C"           ,	   0x10700000023A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT27_EN1_W1C"           ,	   0x10700000023B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT28_EN1_W1C"           ,	   0x10700000023C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT29_EN1_W1C"           ,	   0x10700000023D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT30_EN1_W1C"           ,	   0x10700000023E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT31_EN1_W1C"           ,	   0x10700000023F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT16_EN1_W1S"           ,	   0x1070000006308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT17_EN1_W1S"           ,	   0x1070000006318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT18_EN1_W1S"           ,	   0x1070000006328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT19_EN1_W1S"           ,	   0x1070000006338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT20_EN1_W1S"           ,	   0x1070000006348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT21_EN1_W1S"           ,	   0x1070000006358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT22_EN1_W1S"           ,	   0x1070000006368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT23_EN1_W1S"           ,	   0x1070000006378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT24_EN1_W1S"           ,	   0x1070000006388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT25_EN1_W1S"           ,	   0x1070000006398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT26_EN1_W1S"           ,	   0x10700000063A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT27_EN1_W1S"           ,	   0x10700000063B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT28_EN1_W1S"           ,	   0x10700000063C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT29_EN1_W1S"           ,	   0x10700000063D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT30_EN1_W1S"           ,	   0x10700000063E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT31_EN1_W1S"           ,	   0x10700000063F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT12_EN4_0"             ,	   0x1070000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT13_EN4_0"             ,	   0x1070000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT14_EN4_0"             ,	   0x1070000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT15_EN4_0"             ,	   0x1070000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT10_EN4_0_W1C"         ,	   0x1070000002D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT11_EN4_0_W1C"         ,	   0x1070000002D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT12_EN4_0_W1C"         ,	   0x1070000002D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT13_EN4_0_W1C"         ,	   0x1070000002D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT14_EN4_0_W1C"         ,	   0x1070000002D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT15_EN4_0_W1C"         ,	   0x1070000002D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT10_EN4_0_W1S"         ,	   0x1070000006D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT11_EN4_0_W1S"         ,	   0x1070000006D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT12_EN4_0_W1S"         ,	   0x1070000006D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT13_EN4_0_W1S"         ,	   0x1070000006D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT14_EN4_0_W1S"         ,	   0x1070000006D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT15_EN4_0_W1S"         ,	   0x1070000006D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT12_EN4_1"             ,	   0x1070000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT13_EN4_1"             ,	   0x1070000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT14_EN4_1"             ,	   0x1070000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT15_EN4_1"             ,	   0x1070000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT10_EN4_1_W1C"         ,	   0x1070000002D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT11_EN4_1_W1C"         ,	   0x1070000002D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT12_EN4_1_W1C"         ,	   0x1070000002D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT13_EN4_1_W1C"         ,	   0x1070000002D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT14_EN4_1_W1C"         ,	   0x1070000002D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT15_EN4_1_W1C"         ,	   0x1070000002D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT10_EN4_1_W1S"         ,	   0x1070000006D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT11_EN4_1_W1S"         ,	   0x1070000006D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT12_EN4_1_W1S"         ,	   0x1070000006D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT13_EN4_1_W1S"         ,	   0x1070000006D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT14_EN4_1_W1S"         ,	   0x1070000006D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT15_EN4_1_W1S"         ,	   0x1070000006D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT24_SUM0"              ,	   0x10700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT25_SUM0"              ,	   0x10700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT26_SUM0"              ,	   0x10700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT27_SUM0"              ,	   0x10700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT28_SUM0"              ,	   0x10700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT29_SUM0"              ,	   0x10700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT30_SUM0"              ,	   0x10700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT31_SUM0"              ,	   0x10700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	36},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT12_SUM4"              ,	   0x1070000000C60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT13_SUM4"              ,	   0x1070000000C68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT14_SUM4"              ,	   0x1070000000C70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT15_SUM4"              ,	   0x1070000000C78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	37},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	38},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR12"              ,	   0x10700000006E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR13"              ,	   0x10700000006E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR14"              ,	   0x10700000006F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_CLR15"              ,	   0x10700000006F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	39},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET10"              ,	   0x1070000000650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET11"              ,	   0x1070000000658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET12"              ,	   0x1070000000660ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET13"              ,	   0x1070000000668ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET14"              ,	   0x1070000000670ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_MBOX_SET15"              ,	   0x1070000000678ull,	CVMX_CSR_DB_TYPE_NCB,	64,	40},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	41},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	42},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	43},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE12"               ,	   0x10700000005E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE13"               ,	   0x10700000005E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE14"               ,	   0x10700000005F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_POKE15"               ,	   0x10700000005F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	44},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	45},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	46},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	47},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	48},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	49},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG12"                  ,	   0x1070000000560ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG13"                  ,	   0x1070000000568ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG14"                  ,	   0x1070000000570ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"CIU_WDOG15"                  ,	   0x1070000000578ull,	CVMX_CSR_DB_TYPE_NCB,	64,	50},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	51},
+	{"DFA_BST0"                    ,	   0x11800300007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"DFA_BST1"                    ,	   0x11800300007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"DFA_CFG"                     ,	   0x1180030000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"DFA_DBELL"                   ,	   0x1370000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	55},
+	{"DFA_DIFCTL"                  ,	   0x1370600000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	56},
+	{"DFA_DIFRDPTR"                ,	   0x1370200000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	57},
+	{"DFA_ERR"                     ,	   0x1180030000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"DFA_MEMCFG0"                 ,	   0x1180030000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"DFA_MEMCFG1"                 ,	   0x1180030000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"DFA_MEMCFG2"                 ,	   0x1180030000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"DFA_MEMFADR"                 ,	   0x1180030000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"DFA_MEMFCR"                  ,	   0x1180030000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"DFA_MEMRLD"                  ,	   0x1180030000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"DFA_NCBCTL"                  ,	   0x1180030000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"DFA_RODT_COMP_CTL"           ,	   0x1180030000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"DFA_SBD_DBG0"                ,	   0x1180030000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"DFA_SBD_DBG1"                ,	   0x1180030000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"DFA_SBD_DBG2"                ,	   0x1180030000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"DFA_SBD_DBG3"                ,	   0x1180030000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_RX000_FRM_MAX"          ,	   0x1180008000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX001_FRM_MAX"          ,	   0x1180008000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX002_FRM_MAX"          ,	   0x1180008001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX003_FRM_MAX"          ,	   0x1180008001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX000_FRM_MAX"          ,	   0x1180010000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX001_FRM_MAX"          ,	   0x1180010000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX002_FRM_MAX"          ,	   0x1180010001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX1_RX003_FRM_MAX"          ,	   0x1180010001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_RX000_FRM_MIN"          ,	   0x1180008000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX001_FRM_MIN"          ,	   0x1180008000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX002_FRM_MIN"          ,	   0x1180008001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX003_FRM_MIN"          ,	   0x1180008001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX000_FRM_MIN"          ,	   0x1180010000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX001_FRM_MIN"          ,	   0x1180010000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX002_FRM_MIN"          ,	   0x1180010001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX1_RX003_FRM_MIN"          ,	   0x1180010001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180010000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180010000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180010001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180010001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX003_RX_INBND"         ,	   0x1180008001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX000_RX_INBND"         ,	   0x1180010000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX001_RX_INBND"         ,	   0x1180010000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX002_RX_INBND"         ,	   0x1180010001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX1_RX003_RX_INBND"         ,	   0x1180010001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX_PASS_EN"             ,	   0x11800080005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX_PASS_EN"             ,	   0x11800100005F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX_PASS_MAP000"         ,	   0x1180008000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP001"         ,	   0x1180008000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP002"         ,	   0x1180008000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP003"         ,	   0x1180008000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP004"         ,	   0x1180008000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP005"         ,	   0x1180008000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP006"         ,	   0x1180008000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP007"         ,	   0x1180008000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP008"         ,	   0x1180008000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP009"         ,	   0x1180008000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP010"         ,	   0x1180008000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP011"         ,	   0x1180008000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP012"         ,	   0x1180008000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP013"         ,	   0x1180008000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP014"         ,	   0x1180008000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PASS_MAP015"         ,	   0x1180008000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP000"         ,	   0x1180010000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP001"         ,	   0x1180010000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP002"         ,	   0x1180010000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP003"         ,	   0x1180010000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP004"         ,	   0x1180010000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP005"         ,	   0x1180010000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP006"         ,	   0x1180010000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP007"         ,	   0x1180010000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP008"         ,	   0x1180010000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP009"         ,	   0x1180010000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP010"         ,	   0x1180010000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP011"         ,	   0x1180010000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP012"         ,	   0x1180010000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP013"         ,	   0x1180010000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP014"         ,	   0x1180010000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX_PASS_MAP015"         ,	   0x1180010000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX003_CLK"              ,	   0x1180008001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX000_CLK"              ,	   0x1180010000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX001_CLK"              ,	   0x1180010000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX002_CLK"              ,	   0x1180010001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_TX003_CLK"              ,	   0x1180010001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX_SPI_CTL"             ,	   0x11800080004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX_SPI_CTL"             ,	   0x11800100004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX_SPI_DRAIN"           ,	   0x11800080004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX_SPI_DRAIN"           ,	   0x11800100004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX_SPI_MAX"             ,	   0x11800080004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX_SPI_MAX"             ,	   0x11800100004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX_SPI_ROUND000"        ,	   0x1180008000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND001"        ,	   0x1180008000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND002"        ,	   0x1180008000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND003"        ,	   0x1180008000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND004"        ,	   0x11800080006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND005"        ,	   0x11800080006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND006"        ,	   0x11800080006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND007"        ,	   0x11800080006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND008"        ,	   0x11800080006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND009"        ,	   0x11800080006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND010"        ,	   0x11800080006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND011"        ,	   0x11800080006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND012"        ,	   0x11800080006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND013"        ,	   0x11800080006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND014"        ,	   0x11800080006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND015"        ,	   0x11800080006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND016"        ,	   0x1180008000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND017"        ,	   0x1180008000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND018"        ,	   0x1180008000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND019"        ,	   0x1180008000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND020"        ,	   0x1180008000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND021"        ,	   0x1180008000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND022"        ,	   0x1180008000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND023"        ,	   0x1180008000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND024"        ,	   0x1180008000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND025"        ,	   0x1180008000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND026"        ,	   0x1180008000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND027"        ,	   0x1180008000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND028"        ,	   0x1180008000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND029"        ,	   0x1180008000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND030"        ,	   0x1180008000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_ROUND031"        ,	   0x1180008000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND000"        ,	   0x1180010000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND001"        ,	   0x1180010000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND002"        ,	   0x1180010000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND003"        ,	   0x1180010000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND004"        ,	   0x11800100006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND005"        ,	   0x11800100006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND006"        ,	   0x11800100006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND007"        ,	   0x11800100006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND008"        ,	   0x11800100006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND009"        ,	   0x11800100006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND010"        ,	   0x11800100006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND011"        ,	   0x11800100006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND012"        ,	   0x11800100006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND013"        ,	   0x11800100006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND014"        ,	   0x11800100006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND015"        ,	   0x11800100006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND016"        ,	   0x1180010000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND017"        ,	   0x1180010000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND018"        ,	   0x1180010000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND019"        ,	   0x1180010000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND020"        ,	   0x1180010000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND021"        ,	   0x1180010000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND022"        ,	   0x1180010000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND023"        ,	   0x1180010000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND024"        ,	   0x1180010000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND025"        ,	   0x1180010000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND026"        ,	   0x1180010000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND027"        ,	   0x1180010000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND028"        ,	   0x1180010000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND029"        ,	   0x1180010000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND030"        ,	   0x1180010000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX_SPI_ROUND031"        ,	   0x1180010000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX_SPI_THRESH"          ,	   0x11800080004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX_SPI_THRESH"          ,	   0x11800100004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	171},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	172},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	173},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	197},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	198},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	199},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	200},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	201},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT4_BP_PAGE_CNT"       ,	   0x14F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT5_BP_PAGE_CNT"       ,	   0x14F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT6_BP_PAGE_CNT"       ,	   0x14F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT7_BP_PAGE_CNT"       ,	   0x14F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT8_BP_PAGE_CNT"       ,	   0x14F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT9_BP_PAGE_CNT"       ,	   0x14F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT10_BP_PAGE_CNT"      ,	   0x14F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT11_BP_PAGE_CNT"      ,	   0x14F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT12_BP_PAGE_CNT"      ,	   0x14F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT13_BP_PAGE_CNT"      ,	   0x14F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT14_BP_PAGE_CNT"      ,	   0x14F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT15_BP_PAGE_CNT"      ,	   0x14F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT20_BP_PAGE_CNT"      ,	   0x14F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT21_BP_PAGE_CNT"      ,	   0x14F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT22_BP_PAGE_CNT"      ,	   0x14F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT23_BP_PAGE_CNT"      ,	   0x14F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT24_BP_PAGE_CNT"      ,	   0x14F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT25_BP_PAGE_CNT"      ,	   0x14F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT26_BP_PAGE_CNT"      ,	   0x14F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT27_BP_PAGE_CNT"      ,	   0x14F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT28_BP_PAGE_CNT"      ,	   0x14F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT29_BP_PAGE_CNT"      ,	   0x14F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT30_BP_PAGE_CNT"      ,	   0x14F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT31_BP_PAGE_CNT"      ,	   0x14F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR4"  ,	   0x14F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR5"  ,	   0x14F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR6"  ,	   0x14F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR7"  ,	   0x14F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR8"  ,	   0x14F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR9"  ,	   0x14F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR10" ,	   0x14F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR11" ,	   0x14F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR12" ,	   0x14F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR13" ,	   0x14F0000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR14" ,	   0x14F0000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR15" ,	   0x14F0000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR20" ,	   0x14F0000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR21" ,	   0x14F0000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR22" ,	   0x14F0000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR23" ,	   0x14F0000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR24" ,	   0x14F0000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR25" ,	   0x14F0000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR26" ,	   0x14F0000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR27" ,	   0x14F0000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR28" ,	   0x14F0000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR29" ,	   0x14F00000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR30" ,	   0x14F00000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR31" ,	   0x14F00000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	212},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	213},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	214},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	215},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	216},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	217},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	218},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"L2C_SPAR3"                   ,	   0x1180080000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"LMC0_NXM"                    ,	   0x11800880000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_INPUT2"        ,	   0x11F0000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_INPUT3"        ,	   0x11F00000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	345},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BASE_ADDR_OUTPUT2"       ,	   0x11F00000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BASE_ADDR_OUTPUT3"       ,	   0x11F00000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	346},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	347},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_BUFF_SIZE_OUTPUT2"       ,	   0x11F00000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_BUFF_SIZE_OUTPUT3"       ,	   0x11F00000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	348},
+	{"NPI_COMP_CTL"                ,	   0x11F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	349},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	350},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	351},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	352},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	353},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	354},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	355},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	356},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	357},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	358},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	359},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	360},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	361},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	362},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	363},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	364},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	365},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_NUM_DESC_OUTPUT2"        ,	   0x11F0000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_NUM_DESC_OUTPUT3"        ,	   0x11F0000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	366},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P2_DBPAIR_ADDR"          ,	   0x11F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P3_DBPAIR_ADDR"          ,	   0x11F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	368},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P2_INSTR_ADDR"           ,	   0x11F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P3_INSTR_ADDR"           ,	   0x11F00000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	369},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P2_INSTR_CNTS"           ,	   0x11F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P3_INSTR_CNTS"           ,	   0x11F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	370},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_P2_PAIR_CNTS"            ,	   0x11F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_P3_PAIR_CNTS"            ,	   0x11F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	371},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	372},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	373},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	374},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"NPI_PORT34_INSTR_HDR"        ,	   0x11F0000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"NPI_PORT35_INSTR_HDR"        ,	   0x11F0000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_SIZE_INPUT2"             ,	   0x11F0000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_SIZE_INPUT3"             ,	   0x11F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	383},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	384},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	385},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	386},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	387},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	388},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	389},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	390},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	391},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	392},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	393},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	394},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	395},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	396},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	397},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	398},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	399},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	400},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	401},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	402},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	403},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	404},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	405},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	406},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	407},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	408},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	409},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	410},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	411},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	412},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	413},
+	{"PCI_CNT_REG"                 ,	   0x11F00000011B8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	414},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	415},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_DBELL2"                  ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_DBELL3"                  ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCI,	32,	416},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	417},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	418},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	419},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
+	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
+	{"PCI_INSTR_COUNT2"            ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
+	{"PCI_INSTR_COUNT3"            ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	420},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	421},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	422},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	423},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	424},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	425},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
+	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
+	{"PCI_PKT_CREDITS2"            ,	              0x64ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
+	{"PCI_PKT_CREDITS3"            ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCI,	32,	426},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	427},
+	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	427},
+	{"PCI_PKTS_SENT2"              ,	              0x60ull,	CVMX_CSR_DB_TYPE_PCI,	32,	427},
+	{"PCI_PKTS_SENT3"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCI,	32,	427},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
+	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
+	{"PCI_PKTS_SENT_INT_LEV2"      ,	              0x68ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
+	{"PCI_PKTS_SENT_INT_LEV3"      ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCI,	32,	428},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_PKTS_SENT_TIME2"         ,	              0x6Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_PKTS_SENT_TIME3"         ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	429},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	430},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	431},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	432},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	433},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	434},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	435},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	436},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	437},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	438},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	439},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	440},
+	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PIP_CRC_CTL0"                ,	   0x11800A0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_CRC_CTL1"                ,	   0x11800A0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PIP_CRC_IV0"                 ,	   0x11800A0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_CRC_IV1"                 ,	   0x11800A0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG4"                ,	   0x11800A0000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG5"                ,	   0x11800A0000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG6"                ,	   0x11800A0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG7"                ,	   0x11800A0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG8"                ,	   0x11800A0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG9"                ,	   0x11800A0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG10"               ,	   0x11800A0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG11"               ,	   0x11800A0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG12"               ,	   0x11800A0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG13"               ,	   0x11800A0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG14"               ,	   0x11800A0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG15"               ,	   0x11800A0000278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG20"               ,	   0x11800A00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG21"               ,	   0x11800A00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG22"               ,	   0x11800A00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG23"               ,	   0x11800A00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG24"               ,	   0x11800A00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG25"               ,	   0x11800A00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG26"               ,	   0x11800A00002D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG27"               ,	   0x11800A00002D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG28"               ,	   0x11800A00002E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG29"               ,	   0x11800A00002E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG30"               ,	   0x11800A00002F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG31"               ,	   0x11800A00002F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG4"                ,	   0x11800A0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG5"                ,	   0x11800A0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG6"                ,	   0x11800A0000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG7"                ,	   0x11800A0000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG8"                ,	   0x11800A0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG9"                ,	   0x11800A0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG10"               ,	   0x11800A0000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG11"               ,	   0x11800A0000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG12"               ,	   0x11800A0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG13"               ,	   0x11800A0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG14"               ,	   0x11800A0000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG15"               ,	   0x11800A0000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG20"               ,	   0x11800A00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG21"               ,	   0x11800A00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG22"               ,	   0x11800A00004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG23"               ,	   0x11800A00004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG24"               ,	   0x11800A00004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG25"               ,	   0x11800A00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG26"               ,	   0x11800A00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG27"               ,	   0x11800A00004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG28"               ,	   0x11800A00004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG29"               ,	   0x11800A00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG30"               ,	   0x11800A00004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG31"               ,	   0x11800A00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT4"              ,	   0x11800A0000940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT5"              ,	   0x11800A0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT6"              ,	   0x11800A00009E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT7"              ,	   0x11800A0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT8"              ,	   0x11800A0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT9"              ,	   0x11800A0000AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT10"             ,	   0x11800A0000B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT11"             ,	   0x11800A0000B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT12"             ,	   0x11800A0000BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT13"             ,	   0x11800A0000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT14"             ,	   0x11800A0000C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT15"             ,	   0x11800A0000CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT20"             ,	   0x11800A0000E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT21"             ,	   0x11800A0000E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT22"             ,	   0x11800A0000EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT23"             ,	   0x11800A0000F30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT24"             ,	   0x11800A0000F80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT25"             ,	   0x11800A0000FD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT26"             ,	   0x11800A0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT27"             ,	   0x11800A0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT28"             ,	   0x11800A00010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT29"             ,	   0x11800A0001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT30"             ,	   0x11800A0001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT31"             ,	   0x11800A00011B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT4"              ,	   0x11800A0000948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT5"              ,	   0x11800A0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT6"              ,	   0x11800A00009E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT7"              ,	   0x11800A0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT8"              ,	   0x11800A0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT9"              ,	   0x11800A0000AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT10"             ,	   0x11800A0000B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT11"             ,	   0x11800A0000B78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT12"             ,	   0x11800A0000BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT13"             ,	   0x11800A0000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT14"             ,	   0x11800A0000C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT15"             ,	   0x11800A0000CB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT20"             ,	   0x11800A0000E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT21"             ,	   0x11800A0000E98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT22"             ,	   0x11800A0000EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT23"             ,	   0x11800A0000F38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT24"             ,	   0x11800A0000F88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT25"             ,	   0x11800A0000FD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT26"             ,	   0x11800A0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT27"             ,	   0x11800A0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT28"             ,	   0x11800A00010C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT29"             ,	   0x11800A0001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT30"             ,	   0x11800A0001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT31"             ,	   0x11800A00011B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT4"              ,	   0x11800A0000950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT5"              ,	   0x11800A00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT6"              ,	   0x11800A00009F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT7"              ,	   0x11800A0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT8"              ,	   0x11800A0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT9"              ,	   0x11800A0000AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT10"             ,	   0x11800A0000B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT11"             ,	   0x11800A0000B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT12"             ,	   0x11800A0000BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT13"             ,	   0x11800A0000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT14"             ,	   0x11800A0000C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT15"             ,	   0x11800A0000CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT20"             ,	   0x11800A0000E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT21"             ,	   0x11800A0000EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT22"             ,	   0x11800A0000EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT23"             ,	   0x11800A0000F40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT24"             ,	   0x11800A0000F90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT25"             ,	   0x11800A0000FE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT26"             ,	   0x11800A0001030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT27"             ,	   0x11800A0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT28"             ,	   0x11800A00010D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT29"             ,	   0x11800A0001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT30"             ,	   0x11800A0001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT31"             ,	   0x11800A00011C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT4"              ,	   0x11800A0000958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT5"              ,	   0x11800A00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT6"              ,	   0x11800A00009F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT7"              ,	   0x11800A0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT8"              ,	   0x11800A0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT9"              ,	   0x11800A0000AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT10"             ,	   0x11800A0000B38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT11"             ,	   0x11800A0000B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT12"             ,	   0x11800A0000BD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT13"             ,	   0x11800A0000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT14"             ,	   0x11800A0000C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT15"             ,	   0x11800A0000CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT20"             ,	   0x11800A0000E58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT21"             ,	   0x11800A0000EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT22"             ,	   0x11800A0000EF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT23"             ,	   0x11800A0000F48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT24"             ,	   0x11800A0000F98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT25"             ,	   0x11800A0000FE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT26"             ,	   0x11800A0001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT27"             ,	   0x11800A0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT28"             ,	   0x11800A00010D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT29"             ,	   0x11800A0001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT30"             ,	   0x11800A0001178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT31"             ,	   0x11800A00011C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT4"              ,	   0x11800A0000960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT5"              ,	   0x11800A00009B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT6"              ,	   0x11800A0000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT7"              ,	   0x11800A0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT8"              ,	   0x11800A0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT9"              ,	   0x11800A0000AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT10"             ,	   0x11800A0000B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT11"             ,	   0x11800A0000B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT12"             ,	   0x11800A0000BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT13"             ,	   0x11800A0000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT14"             ,	   0x11800A0000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT15"             ,	   0x11800A0000CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT20"             ,	   0x11800A0000E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT21"             ,	   0x11800A0000EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT22"             ,	   0x11800A0000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT23"             ,	   0x11800A0000F50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT24"             ,	   0x11800A0000FA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT25"             ,	   0x11800A0000FF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT26"             ,	   0x11800A0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT27"             ,	   0x11800A0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT28"             ,	   0x11800A00010E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT29"             ,	   0x11800A0001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT30"             ,	   0x11800A0001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT31"             ,	   0x11800A00011D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT4"              ,	   0x11800A0000968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT5"              ,	   0x11800A00009B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT6"              ,	   0x11800A0000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT7"              ,	   0x11800A0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT8"              ,	   0x11800A0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT9"              ,	   0x11800A0000AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT10"             ,	   0x11800A0000B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT11"             ,	   0x11800A0000B98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT12"             ,	   0x11800A0000BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT13"             ,	   0x11800A0000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT14"             ,	   0x11800A0000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT15"             ,	   0x11800A0000CD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT20"             ,	   0x11800A0000E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT21"             ,	   0x11800A0000EB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT22"             ,	   0x11800A0000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT23"             ,	   0x11800A0000F58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT24"             ,	   0x11800A0000FA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT25"             ,	   0x11800A0000FF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT26"             ,	   0x11800A0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT27"             ,	   0x11800A0001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT28"             ,	   0x11800A00010E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT29"             ,	   0x11800A0001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT30"             ,	   0x11800A0001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT31"             ,	   0x11800A00011D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT4"              ,	   0x11800A0000970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT5"              ,	   0x11800A00009C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT6"              ,	   0x11800A0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT7"              ,	   0x11800A0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT8"              ,	   0x11800A0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT9"              ,	   0x11800A0000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT10"             ,	   0x11800A0000B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT11"             ,	   0x11800A0000BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT12"             ,	   0x11800A0000BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT13"             ,	   0x11800A0000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT14"             ,	   0x11800A0000C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT15"             ,	   0x11800A0000CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT20"             ,	   0x11800A0000E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT21"             ,	   0x11800A0000EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT22"             ,	   0x11800A0000F10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT23"             ,	   0x11800A0000F60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT24"             ,	   0x11800A0000FB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT25"             ,	   0x11800A0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT26"             ,	   0x11800A0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT27"             ,	   0x11800A00010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT28"             ,	   0x11800A00010F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT29"             ,	   0x11800A0001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT30"             ,	   0x11800A0001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT31"             ,	   0x11800A00011E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT4"              ,	   0x11800A0000978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT5"              ,	   0x11800A00009C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT6"              ,	   0x11800A0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT7"              ,	   0x11800A0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT8"              ,	   0x11800A0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT9"              ,	   0x11800A0000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT10"             ,	   0x11800A0000B58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT11"             ,	   0x11800A0000BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT12"             ,	   0x11800A0000BF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT13"             ,	   0x11800A0000C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT14"             ,	   0x11800A0000C98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT15"             ,	   0x11800A0000CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT20"             ,	   0x11800A0000E78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT21"             ,	   0x11800A0000EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT22"             ,	   0x11800A0000F18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT23"             ,	   0x11800A0000F68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT24"             ,	   0x11800A0000FB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT25"             ,	   0x11800A0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT26"             ,	   0x11800A0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT27"             ,	   0x11800A00010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT28"             ,	   0x11800A00010F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT29"             ,	   0x11800A0001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT30"             ,	   0x11800A0001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT31"             ,	   0x11800A00011E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT4"              ,	   0x11800A0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT5"              ,	   0x11800A00009D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT6"              ,	   0x11800A0000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT7"              ,	   0x11800A0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT8"              ,	   0x11800A0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT9"              ,	   0x11800A0000B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT10"             ,	   0x11800A0000B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT11"             ,	   0x11800A0000BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT12"             ,	   0x11800A0000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT13"             ,	   0x11800A0000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT14"             ,	   0x11800A0000CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT15"             ,	   0x11800A0000CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT20"             ,	   0x11800A0000E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT21"             ,	   0x11800A0000ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT22"             ,	   0x11800A0000F20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT23"             ,	   0x11800A0000F70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT24"             ,	   0x11800A0000FC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT25"             ,	   0x11800A0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT26"             ,	   0x11800A0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT27"             ,	   0x11800A00010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT28"             ,	   0x11800A0001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT29"             ,	   0x11800A0001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT30"             ,	   0x11800A00011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT31"             ,	   0x11800A00011F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT4"              ,	   0x11800A0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT5"              ,	   0x11800A00009D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT6"              ,	   0x11800A0000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT7"              ,	   0x11800A0000A78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT8"              ,	   0x11800A0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT9"              ,	   0x11800A0000B18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT10"             ,	   0x11800A0000B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT11"             ,	   0x11800A0000BB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT12"             ,	   0x11800A0000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT13"             ,	   0x11800A0000C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT14"             ,	   0x11800A0000CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT15"             ,	   0x11800A0000CF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT20"             ,	   0x11800A0000E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT21"             ,	   0x11800A0000ED8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT22"             ,	   0x11800A0000F28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT23"             ,	   0x11800A0000F78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT24"             ,	   0x11800A0000FC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT25"             ,	   0x11800A0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT26"             ,	   0x11800A0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT27"             ,	   0x11800A00010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT28"             ,	   0x11800A0001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT29"             ,	   0x11800A0001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT30"             ,	   0x11800A00011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT31"             ,	   0x11800A00011F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS4"          ,	   0x11800A0001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS5"          ,	   0x11800A0001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS6"          ,	   0x11800A0001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS7"          ,	   0x11800A0001AF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS8"          ,	   0x11800A0001B10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS9"          ,	   0x11800A0001B30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS10"         ,	   0x11800A0001B50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS11"         ,	   0x11800A0001B70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS12"         ,	   0x11800A0001B90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS13"         ,	   0x11800A0001BB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS14"         ,	   0x11800A0001BD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS15"         ,	   0x11800A0001BF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS20"         ,	   0x11800A0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS21"         ,	   0x11800A0001CB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS22"         ,	   0x11800A0001CD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS23"         ,	   0x11800A0001CF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS24"         ,	   0x11800A0001D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS25"         ,	   0x11800A0001D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS26"         ,	   0x11800A0001D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS27"         ,	   0x11800A0001D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS28"         ,	   0x11800A0001D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS29"         ,	   0x11800A0001DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS30"         ,	   0x11800A0001DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS31"         ,	   0x11800A0001DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	469},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS4"          ,	   0x11800A0001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS5"          ,	   0x11800A0001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS6"          ,	   0x11800A0001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS7"          ,	   0x11800A0001AE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS8"          ,	   0x11800A0001B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS9"          ,	   0x11800A0001B28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS10"         ,	   0x11800A0001B48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS11"         ,	   0x11800A0001B68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS12"         ,	   0x11800A0001B88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS13"         ,	   0x11800A0001BA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS14"         ,	   0x11800A0001BC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS15"         ,	   0x11800A0001BE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS20"         ,	   0x11800A0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS21"         ,	   0x11800A0001CA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS22"         ,	   0x11800A0001CC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS23"         ,	   0x11800A0001CE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS24"         ,	   0x11800A0001D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS25"         ,	   0x11800A0001D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS26"         ,	   0x11800A0001D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS27"         ,	   0x11800A0001D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS28"         ,	   0x11800A0001D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS29"         ,	   0x11800A0001DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS30"         ,	   0x11800A0001DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS31"         ,	   0x11800A0001DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	470},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS4"          ,	   0x11800A0001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS5"          ,	   0x11800A0001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS6"          ,	   0x11800A0001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS7"          ,	   0x11800A0001AE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS8"          ,	   0x11800A0001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS9"          ,	   0x11800A0001B20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS10"         ,	   0x11800A0001B40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS11"         ,	   0x11800A0001B60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS12"         ,	   0x11800A0001B80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS13"         ,	   0x11800A0001BA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS14"         ,	   0x11800A0001BC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS15"         ,	   0x11800A0001BE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS20"         ,	   0x11800A0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS21"         ,	   0x11800A0001CA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS22"         ,	   0x11800A0001CC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS23"         ,	   0x11800A0001CE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS24"         ,	   0x11800A0001D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS25"         ,	   0x11800A0001D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS26"         ,	   0x11800A0001D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS27"         ,	   0x11800A0001D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS28"         ,	   0x11800A0001D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS29"         ,	   0x11800A0001DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS30"         ,	   0x11800A0001DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS31"         ,	   0x11800A0001DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	471},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	472},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	473},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	474},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	475},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	476},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	477},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	478},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	479},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	480},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	481},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	482},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	483},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	484},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	485},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	486},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	487},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	488},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"PKO_REG_CRC_CTL0"            ,	   0x1180050000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"PKO_REG_CRC_CTL1"            ,	   0x1180050000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"PKO_REG_CRC_ENABLE"          ,	   0x1180050000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"PKO_REG_CRC_IV0"             ,	   0x1180050000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"PKO_REG_CRC_IV1"             ,	   0x1180050000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	506},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	507},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	508},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	509},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	510},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	511},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	512},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	513},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	514},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	515},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	516},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	517},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	518},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK12"            ,	   0x1670000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK13"            ,	   0x1670000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK14"            ,	   0x1670000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_PP_GRP_MSK15"            ,	   0x1670000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	519},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	520},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	521},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	522},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	523},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	524},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	525},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	526},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	527},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	528},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	529},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	530},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	531},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	532},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	533},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	534},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	535},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	536},
+	{"SPX0_BCKPRS_CNT"             ,	   0x1180090000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"SPX1_BCKPRS_CNT"             ,	   0x1180098000340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	537},
+	{"SPX0_BIST_STAT"              ,	   0x11800900007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"SPX1_BIST_STAT"              ,	   0x11800980007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	538},
+	{"SPX0_CLK_CTL"                ,	   0x1180090000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"SPX1_CLK_CTL"                ,	   0x1180098000348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	539},
+	{"SPX0_CLK_STAT"               ,	   0x1180090000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"SPX1_CLK_STAT"               ,	   0x1180098000350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	540},
+	{"SPX0_DBG_DESKEW_CTL"         ,	   0x1180090000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"SPX1_DBG_DESKEW_CTL"         ,	   0x1180098000368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	541},
+	{"SPX0_DBG_DESKEW_STATE"       ,	   0x1180090000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"SPX1_DBG_DESKEW_STATE"       ,	   0x1180098000370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	542},
+	{"SPX0_DRV_CTL"                ,	   0x1180090000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"SPX1_DRV_CTL"                ,	   0x1180098000358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	543},
+	{"SPX0_ERR_CTL"                ,	   0x1180090000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"SPX1_ERR_CTL"                ,	   0x1180098000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	544},
+	{"SPX0_INT_DAT"                ,	   0x1180090000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SPX1_INT_DAT"                ,	   0x1180098000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	545},
+	{"SPX0_INT_MSK"                ,	   0x1180090000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"SPX1_INT_MSK"                ,	   0x1180098000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	546},
+	{"SPX0_INT_REG"                ,	   0x1180090000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"SPX1_INT_REG"                ,	   0x1180098000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	547},
+	{"SPX0_INT_SYNC"               ,	   0x1180090000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"SPX1_INT_SYNC"               ,	   0x1180098000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	548},
+	{"SPX0_TPA_ACC"                ,	   0x1180090000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"SPX1_TPA_ACC"                ,	   0x1180098000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	549},
+	{"SPX0_TPA_MAX"                ,	   0x1180090000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"SPX1_TPA_MAX"                ,	   0x1180098000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	550},
+	{"SPX0_TPA_SEL"                ,	   0x1180090000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"SPX1_TPA_SEL"                ,	   0x1180098000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	551},
+	{"SPX0_TRN4_CTL"               ,	   0x1180090000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"SPX1_TRN4_CTL"               ,	   0x1180098000360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	552},
+	{"SRX0_COM_CTL"                ,	   0x1180090000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"SRX1_COM_CTL"                ,	   0x1180098000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	553},
+	{"SRX0_IGN_RX_FULL"            ,	   0x1180090000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"SRX1_IGN_RX_FULL"            ,	   0x1180098000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	554},
+	{"SRX0_SPI4_CAL000"            ,	   0x1180090000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL001"            ,	   0x1180090000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL002"            ,	   0x1180090000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL003"            ,	   0x1180090000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL004"            ,	   0x1180090000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL005"            ,	   0x1180090000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL006"            ,	   0x1180090000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL007"            ,	   0x1180090000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL008"            ,	   0x1180090000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL009"            ,	   0x1180090000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL010"            ,	   0x1180090000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL011"            ,	   0x1180090000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL012"            ,	   0x1180090000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL013"            ,	   0x1180090000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL014"            ,	   0x1180090000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL015"            ,	   0x1180090000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL016"            ,	   0x1180090000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL017"            ,	   0x1180090000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL018"            ,	   0x1180090000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL019"            ,	   0x1180090000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL020"            ,	   0x11800900000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL021"            ,	   0x11800900000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL022"            ,	   0x11800900000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL023"            ,	   0x11800900000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL024"            ,	   0x11800900000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL025"            ,	   0x11800900000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL026"            ,	   0x11800900000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL027"            ,	   0x11800900000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL028"            ,	   0x11800900000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL029"            ,	   0x11800900000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL030"            ,	   0x11800900000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_CAL031"            ,	   0x11800900000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL000"            ,	   0x1180098000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL001"            ,	   0x1180098000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL002"            ,	   0x1180098000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL003"            ,	   0x1180098000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL004"            ,	   0x1180098000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL005"            ,	   0x1180098000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL006"            ,	   0x1180098000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL007"            ,	   0x1180098000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL008"            ,	   0x1180098000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL009"            ,	   0x1180098000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL010"            ,	   0x1180098000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL011"            ,	   0x1180098000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL012"            ,	   0x1180098000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL013"            ,	   0x1180098000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL014"            ,	   0x1180098000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL015"            ,	   0x1180098000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL016"            ,	   0x1180098000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL017"            ,	   0x1180098000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL018"            ,	   0x1180098000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL019"            ,	   0x1180098000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL020"            ,	   0x11800980000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL021"            ,	   0x11800980000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL022"            ,	   0x11800980000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL023"            ,	   0x11800980000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL024"            ,	   0x11800980000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL025"            ,	   0x11800980000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL026"            ,	   0x11800980000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL027"            ,	   0x11800980000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL028"            ,	   0x11800980000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL029"            ,	   0x11800980000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL030"            ,	   0x11800980000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX1_SPI4_CAL031"            ,	   0x11800980000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	555},
+	{"SRX0_SPI4_STAT"              ,	   0x1180090000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"SRX1_SPI4_STAT"              ,	   0x1180098000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	556},
+	{"SRX0_SW_TICK_CTL"            ,	   0x1180090000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"SRX1_SW_TICK_CTL"            ,	   0x1180098000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	557},
+	{"SRX0_SW_TICK_DAT"            ,	   0x1180090000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"SRX1_SW_TICK_DAT"            ,	   0x1180098000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"STX0_ARB_CTL"                ,	   0x1180090000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"STX1_ARB_CTL"                ,	   0x1180098000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"STX0_BCKPRS_CNT"             ,	   0x1180090000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"STX1_BCKPRS_CNT"             ,	   0x1180098000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	560},
+	{"STX0_COM_CTL"                ,	   0x1180090000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"STX1_COM_CTL"                ,	   0x1180098000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	561},
+	{"STX0_DIP_CNT"                ,	   0x1180090000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"STX1_DIP_CNT"                ,	   0x1180098000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	562},
+	{"STX0_IGN_CAL"                ,	   0x1180090000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"STX1_IGN_CAL"                ,	   0x1180098000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	563},
+	{"STX0_INT_MSK"                ,	   0x11800900006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"STX1_INT_MSK"                ,	   0x11800980006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	564},
+	{"STX0_INT_REG"                ,	   0x1180090000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"STX1_INT_REG"                ,	   0x1180098000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	565},
+	{"STX0_INT_SYNC"               ,	   0x11800900006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"STX1_INT_SYNC"               ,	   0x11800980006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	566},
+	{"STX0_MIN_BST"                ,	   0x1180090000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"STX1_MIN_BST"                ,	   0x1180098000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	567},
+	{"STX0_SPI4_CAL000"            ,	   0x1180090000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL001"            ,	   0x1180090000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL002"            ,	   0x1180090000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL003"            ,	   0x1180090000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL004"            ,	   0x1180090000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL005"            ,	   0x1180090000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL006"            ,	   0x1180090000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL007"            ,	   0x1180090000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL008"            ,	   0x1180090000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL009"            ,	   0x1180090000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL010"            ,	   0x1180090000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL011"            ,	   0x1180090000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL012"            ,	   0x1180090000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL013"            ,	   0x1180090000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL014"            ,	   0x1180090000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL015"            ,	   0x1180090000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL016"            ,	   0x1180090000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL017"            ,	   0x1180090000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL018"            ,	   0x1180090000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL019"            ,	   0x1180090000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL020"            ,	   0x11800900004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL021"            ,	   0x11800900004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL022"            ,	   0x11800900004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL023"            ,	   0x11800900004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL024"            ,	   0x11800900004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL025"            ,	   0x11800900004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL026"            ,	   0x11800900004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL027"            ,	   0x11800900004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL028"            ,	   0x11800900004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL029"            ,	   0x11800900004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL030"            ,	   0x11800900004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_CAL031"            ,	   0x11800900004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL000"            ,	   0x1180098000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL001"            ,	   0x1180098000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL002"            ,	   0x1180098000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL003"            ,	   0x1180098000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL004"            ,	   0x1180098000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL005"            ,	   0x1180098000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL006"            ,	   0x1180098000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL007"            ,	   0x1180098000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL008"            ,	   0x1180098000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL009"            ,	   0x1180098000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL010"            ,	   0x1180098000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL011"            ,	   0x1180098000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL012"            ,	   0x1180098000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL013"            ,	   0x1180098000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL014"            ,	   0x1180098000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL015"            ,	   0x1180098000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL016"            ,	   0x1180098000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL017"            ,	   0x1180098000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL018"            ,	   0x1180098000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL019"            ,	   0x1180098000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL020"            ,	   0x11800980004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL021"            ,	   0x11800980004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL022"            ,	   0x11800980004B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL023"            ,	   0x11800980004B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL024"            ,	   0x11800980004C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL025"            ,	   0x11800980004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL026"            ,	   0x11800980004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL027"            ,	   0x11800980004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL028"            ,	   0x11800980004E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL029"            ,	   0x11800980004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL030"            ,	   0x11800980004F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX1_SPI4_CAL031"            ,	   0x11800980004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	568},
+	{"STX0_SPI4_DAT"               ,	   0x1180090000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"STX1_SPI4_DAT"               ,	   0x1180098000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	569},
+	{"STX0_SPI4_STAT"              ,	   0x1180090000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"STX1_SPI4_STAT"              ,	   0x1180098000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	570},
+	{"STX0_STAT_BYTES_HI"          ,	   0x1180090000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"STX1_STAT_BYTES_HI"          ,	   0x1180098000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	571},
+	{"STX0_STAT_BYTES_LO"          ,	   0x1180090000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"STX1_STAT_BYTES_LO"          ,	   0x1180098000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	572},
+	{"STX0_STAT_CTL"               ,	   0x1180090000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"STX1_STAT_CTL"               ,	   0x1180098000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	573},
+	{"STX0_STAT_PKT_XMT"           ,	   0x1180090000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"STX1_STAT_PKT_XMT"           ,	   0x1180098000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	574},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	575},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	576},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	577},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	581},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	582},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	583},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	584},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	585},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	586},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	587},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	588},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	589},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	590},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	591},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	592},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	593},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	594},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	595},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	596},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	597},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	598},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	599},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	600},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	601},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	602},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	603},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	604},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	605},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	606},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	607},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	608},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	609},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	610},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	611},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	612},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"OVRFLW"                      ,	0,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPOP"                       ,	4,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXPSH"                       ,	8,	4,	0,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	4,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	8,	4,	1,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	1,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXT_LOOP"                    ,	4,	4,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	1,	3,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	3,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	4,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	5,	"RO",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	5,	5,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	5,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"PCTL"                        ,	4,	4,	6,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	6,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	7,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	7,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	8,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	8,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	9,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	9,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	10,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	10,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	11,	"RO",	1,	1,	0,	0},
+	{"DFALOCK"                     ,	5,	1,	11,	"RO",	1,	1,	0,	0},
+	{"DFALEAD"                     ,	6,	1,	11,	"RO",	1,	1,	0,	0},
+	{"DFALAG"                      ,	7,	1,	11,	"RO",	1,	1,	0,	0},
+	{"DFASET"                      ,	8,	5,	11,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	11,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	12,	"R/W",	0,	0,	24ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	12,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	13,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	13,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	14,	"R/W",	0,	0,	24ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	14,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	15,	"R/W",	0,	0,	6ull,	6ull},
+	{"RESERVED_5_7"                ,	5,	3,	15,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	15,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_13_63"              ,	13,	51,	15,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	16,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	4,	17,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	17,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	4,	18,	"R/W",	0,	1,	15ull,	0},
+	{"PCTL"                        ,	4,	5,	18,	"R/W",	0,	1,	31ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	18,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	19,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	19,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	20,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	16,	21,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	21,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	16,	22,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	22,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	23,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	24,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	24,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	24,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	25,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	25,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	25,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	26,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	26,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	26,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	27,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	27,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	28,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	28,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	29,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	29,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	30,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	30,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	31,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	31,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	31,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	32,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	32,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	32,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	33,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	34,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	34,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	35,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	35,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	36,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	36,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	37,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	37,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	37,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	37,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	37,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	16,	38,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	38,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	39,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	40,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	40,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	16,	41,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	41,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	42,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	16,	43,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	43,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	44,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	45,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	15,	45,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	46,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	46,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	47,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	47,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	47,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	48,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	48,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	49,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	49,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	49,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	50,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	50,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	50,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	51,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	51,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	51,	"RO",	1,	1,	0,	0},
+	{"REM"                         ,	23,	6,	51,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	51,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	4,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	52,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RDF"                         ,	16,	4,	52,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	52,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P1_BRF"                      ,	0,	8,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BRF"                      ,	8,	8,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"P1_BWB"                      ,	16,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"P0_BWB"                      ,	17,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"CRF"                         ,	18,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	53,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GFU"                         ,	20,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"IFU"                         ,	21,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"CRQ"                         ,	22,	1,	53,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	53,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SARB"                        ,	0,	1,	54,	"R/W",	0,	0,	1ull,	1ull},
+	{"GXOR_ENA"                    ,	1,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"NXOR_ENA"                    ,	2,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"NRPL_ENA"                    ,	3,	1,	54,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	54,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	20,	55,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	55,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	9,	56,	"R/W",	0,	1,	3ull,	0},
+	{"POOL"                        ,	9,	3,	56,	"R/W",	0,	1,	0ull,	0},
+	{"DWBCNT"                      ,	12,	8,	56,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	56,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	57,	"RAZ",	1,	1,	0,	0},
+	{"RDPTR"                       ,	5,	31,	57,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	57,	"RAZ",	1,	1,	0,	0},
+	{"CP2ECCENA"                   ,	0,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SBE"                      ,	1,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2DBE"                      ,	2,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2SBINA"                    ,	3,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2DBINA"                    ,	4,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2SYN"                      ,	5,	8,	58,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEECCENA"                   ,	13,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESBE"                      ,	14,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEDBE"                      ,	15,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTESBINA"                    ,	16,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEDBINA"                    ,	17,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTESYN"                      ,	18,	7,	58,	"RO",	0,	0,	0ull,	0ull},
+	{"DTEPARENA"                   ,	25,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTEPERR"                     ,	26,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTEPINA"                     ,	27,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PARENA"                   ,	28,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP2PERR"                     ,	29,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CP2PINA"                     ,	30,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"DBLOVF"                      ,	31,	1,	58,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBLINA"                      ,	32,	1,	58,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	58,	"RAZ",	1,	1,	0,	0},
+	{"ENA_P1"                      ,	0,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"ENA_P0"                      ,	1,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	59,	"RAZ",	1,	1,	0,	0},
+	{"MTYPE"                       ,	3,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_LAT"                     ,	4,	2,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RW_DLY"                      ,	6,	4,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"WR_DLY"                      ,	10,	4,	59,	"R/W",	0,	0,	2ull,	2ull},
+	{"FPRCH"                       ,	14,	2,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"BPRCH"                       ,	16,	2,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"BLEN"                        ,	18,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBUNK"                       ,	19,	3,	59,	"R/W",	0,	0,	2ull,	2ull},
+	{"R2R_PBUNK"                   ,	22,	1,	59,	"R/W",	0,	0,	1ull,	1ull},
+	{"INIT_P1"                     ,	23,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"INIT_P0"                     ,	24,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUNK_INIT"                   ,	25,	2,	59,	"R/W",	0,	0,	3ull,	3ull},
+	{"LPP_ENA"                     ,	27,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDIV"                      ,	28,	2,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RLDCK_RST"                   ,	30,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RLDQCK90_RST"                ,	31,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	59,	"RAZ",	1,	1,	0,	0},
+	{"REF_INT"                     ,	0,	4,	60,	"R/W",	0,	0,	3ull,	3ull},
+	{"TSKW"                        ,	4,	2,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	60,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TRL"                         ,	8,	4,	60,	"R/W",	0,	0,	6ull,	6ull},
+	{"TWL"                         ,	12,	4,	60,	"R/W",	0,	0,	7ull,	7ull},
+	{"TRC"                         ,	16,	4,	60,	"R/W",	0,	0,	6ull,	6ull},
+	{"TMRSC"                       ,	20,	3,	60,	"R/W",	0,	0,	6ull,	6ull},
+	{"MRS_ENA"                     ,	23,	1,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"AREF_ENA"                    ,	24,	1,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"REF_INTLO"                   ,	25,	9,	60,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	60,	"RAZ",	1,	1,	0,	0},
+	{"FCRAM2P"                     ,	0,	1,	61,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXBNK"                      ,	1,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"UA_START"                    ,	2,	2,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"REFSHORT"                    ,	4,	1,	61,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRFC"                        ,	5,	5,	61,	"R/W",	0,	0,	9ull,	9ull},
+	{"SILRST"                      ,	10,	1,	61,	"R/W",	0,	0,	0ull,	0ull},
+	{"DTECLKDIS"                   ,	11,	1,	61,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	61,	"RAZ",	1,	1,	0,	0},
+	{"MADDR"                       ,	0,	24,	62,	"RO",	0,	0,	0ull,	0ull},
+	{"BNUM"                        ,	24,	3,	62,	"RO",	0,	0,	0ull,	0ull},
+	{"PNUM"                        ,	27,	1,	62,	"RO",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	28,	2,	62,	"RO",	0,	0,	0ull,	0ull},
+	{"FDST"                        ,	30,	9,	62,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	62,	"RAZ",	1,	1,	0,	0},
+	{"MRS"                         ,	0,	15,	63,	"R/W",	0,	0,	66ull,	66ull},
+	{"RESERVED_15_15"              ,	15,	1,	63,	"RAZ",	1,	1,	0,	0},
+	{"EMRS"                        ,	16,	15,	63,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_31_31"              ,	31,	1,	63,	"RAZ",	1,	1,	0,	0},
+	{"EMRS2"                       ,	32,	15,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_63"              ,	47,	17,	63,	"RAZ",	1,	1,	0,	0},
+	{"MRSDAT"                      ,	0,	23,	64,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_23_63"              ,	23,	41,	64,	"RAZ",	1,	1,	0,	0},
+	{"IMODE"                       ,	0,	1,	65,	"R/W",	0,	0,	1ull,	1ull},
+	{"QMODE"                       ,	1,	1,	65,	"R/W",	0,	0,	1ull,	1ull},
+	{"PMODE"                       ,	2,	1,	65,	"R/W",	0,	0,	1ull,	1ull},
+	{"DTMODE"                      ,	3,	1,	65,	"R/W",	0,	0,	1ull,	1ull},
+	{"DCMODE"                      ,	4,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDLCK"                      ,	5,	1,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBDNUM"                      ,	6,	5,	65,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	65,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	66,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	66,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	66,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	66,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	66,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	66,	"RAZ",	0,	1,	0ull,	0},
+	{"SBD0"                        ,	0,	64,	67,	"RO",	1,	1,	0,	0},
+	{"SBD1"                        ,	0,	64,	68,	"RO",	1,	1,	0,	0},
+	{"SBD2"                        ,	0,	64,	69,	"RO",	1,	1,	0,	0},
+	{"SBD3"                        ,	0,	64,	70,	"RO",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	71,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	72,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	72,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	72,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	72,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	72,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	72,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	72,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	73,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	73,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	73,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	74,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	74,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	75,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	75,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	75,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	76,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	76,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	77,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	78,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	78,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	79,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	80,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	80,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	81,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	81,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	81,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	82,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	82,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	82,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	83,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	83,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	84,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	84,	"RAZ",	1,	1,	0,	0},
+	{"OUT_COL"                     ,	0,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_OVR"                     ,	1,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	16,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_21"              ,	18,	4,	85,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	4,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	85,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	17,	86,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	86,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	87,	"RO",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	87,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	87,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	88,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	88,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	89,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	89,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	89,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	89,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	89,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	90,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	91,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	92,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	93,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	94,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	95,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	96,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	96,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	97,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	97,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	97,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	97,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	98,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	98,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"CAREXT"                      ,	1,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR"                      ,	2,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	99,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	99,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	100,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	100,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	100,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	100,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	100,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	100,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_FREE"                    ,	6,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"VLAN_LEN"                    ,	7,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	100,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	101,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	101,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	102,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	102,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	103,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	103,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	104,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAREXT"                      ,	1,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	105,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	106,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	106,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	107,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	107,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	108,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	108,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	108,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	108,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	109,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	109,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	110,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	110,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	111,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	111,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	112,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	112,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	113,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	113,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	114,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	114,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	115,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	115,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	116,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	116,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	117,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	117,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	118,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	118,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	119,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	119,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	120,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	120,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	121,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	121,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	122,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	122,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	16,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	123,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	4,	124,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	124,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	16,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"DROP"                        ,	16,	16,	125,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	125,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	126,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	126,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	127,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	127,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	128,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	128,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	129,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	129,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	129,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	129,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	129,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	130,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	130,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	131,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	131,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	132,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	132,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	132,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	133,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	133,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	134,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	134,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	135,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	135,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	136,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	136,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	137,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	137,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	138,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	138,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	139,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	139,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	142,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	142,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	143,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	143,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	144,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	144,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	145,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	145,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	146,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	146,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	147,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	147,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	148,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	148,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	149,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	149,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	150,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	151,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	151,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	152,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	152,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	153,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	153,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	154,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	154,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	155,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	155,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	155,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	156,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	156,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	156,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NCB_NXA"                     ,	1,	1,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	157,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	157,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	157,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	158,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	158,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	159,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	159,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	160,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	161,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	161,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	162,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	162,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	163,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	163,	"RAZ",	1,	1,	0,	0},
+	{"CONT_PKT"                    ,	0,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"TPA_CLR"                     ,	1,	1,	164,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	164,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DRAIN"                       ,	0,	16,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	165,	"RAZ",	1,	1,	0,	0},
+	{"MAX1"                        ,	0,	8,	166,	"R/W",	0,	1,	8ull,	0},
+	{"MAX2"                        ,	8,	8,	166,	"R/W",	0,	1,	4ull,	0},
+	{"SLICE"                       ,	16,	7,	166,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	166,	"RAZ",	1,	1,	0,	0},
+	{"ROUND"                       ,	0,	16,	167,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	167,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	6,	168,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	168,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	169,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	169,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	170,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	170,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	171,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	172,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	172,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	173,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	173,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	174,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	175,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	175,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	175,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	176,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	177,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	177,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	177,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	178,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	179,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	179,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	179,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	179,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	179,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	180,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	180,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	180,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	180,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	180,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	181,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	182,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	183,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	183,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	184,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	184,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	185,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	186,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	187,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	187,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	187,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	188,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	188,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	188,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	188,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	188,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	189,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	189,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	189,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	189,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	189,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	190,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	191,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	192,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	193,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	193,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	194,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	194,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	195,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	195,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	196,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	197,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	197,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	198,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	198,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	199,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	200,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	201,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	202,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	202,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	203,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	204,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	205,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	205,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	206,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	206,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	207,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	207,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	208,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	209,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	209,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	210,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	210,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	210,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	210,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	210,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	211,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	211,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	211,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	211,	"RO",	0,	0,	36ull,	36ull},
+	{"RESERVED_44_63"              ,	44,	20,	211,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	212,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	213,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	213,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	213,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	213,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	213,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	213,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	214,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	214,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	215,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	215,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	216,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	217,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	217,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	217,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	217,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	218,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	218,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	218,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	219,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	219,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	220,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	220,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	221,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	221,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	222,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	223,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	224,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	225,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	225,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	225,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	225,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	225,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	13,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	226,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	226,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	227,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	227,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"PICBST"                      ,	2,	1,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"RHDB"                        ,	4,	4,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"RMDB"                        ,	8,	4,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	228,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	228,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	229,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	229,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	229,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	229,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	229,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFILL_DIS"                   ,	14,	1,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_17"              ,	15,	3,	229,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LBIST"                       ,	18,	1,	229,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSTRUN"                      ,	19,	1,	229,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	229,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	4,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	4,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	230,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	231,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	231,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	231,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	232,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	233,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	4,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	4,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	235,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	235,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	11,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	11,	16,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	236,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	4,	237,	"R/W",	0,	0,	15ull,	15ull},
+	{"STPARTDIS"                   ,	4,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	237,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	238,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	238,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	239,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	240,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK4"                       ,	0,	8,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK5"                       ,	8,	8,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK6"                       ,	16,	8,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK7"                       ,	24,	8,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	241,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK8"                       ,	0,	8,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK9"                       ,	8,	8,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK10"                      ,	16,	8,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK11"                      ,	24,	8,	242,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	242,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK12"                      ,	0,	8,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK13"                      ,	8,	8,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK14"                      ,	16,	8,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK15"                      ,	24,	8,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	243,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	244,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	245,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	246,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	246,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	247,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	247,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	248,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	248,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	249,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	249,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	249,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	11,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"FADRU"                       ,	18,	1,	250,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	250,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	251,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	251,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	251,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	252,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	253,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	255,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_1024K"                  ,	34,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_512K"                   ,	35,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	2,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	257,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	257,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	257,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	257,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	257,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	10,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	257,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	257,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	257,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	257,	"R/W",	0,	0,	0ull,	1ull},
+	{"FADRU"                       ,	28,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	257,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RATE"                        ,	0,	8,	258,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_63"               ,	8,	56,	258,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	7,	259,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_7_63"               ,	7,	57,	259,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	0,	16,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	260,	"RAZ",	1,	1,	0,	0},
+	{"DBG_EN"                      ,	0,	1,	261,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	261,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	262,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	262,	"RAZ",	1,	1,	0,	0},
+	{"POLARITY"                    ,	0,	1,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	263,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	8,	264,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	264,	"RAZ",	1,	1,	0,	0},
+	{"FORMAT"                      ,	0,	4,	265,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	265,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	266,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	267,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	32,	268,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	268,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	32,	269,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	269,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	32,	270,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	270,	"RAZ",	1,	1,	0,	0},
+	{"PCTL_DAT"                    ,	0,	5,	271,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_11"               ,	5,	7,	271,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	271,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	271,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	271,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	271,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	271,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	272,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	272,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	272,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE128B"                    ,	10,	1,	272,	"R/W",	0,	0,	1ull,	1ull},
+	{"DRESET"                      ,	11,	1,	272,	"R/W",	0,	0,	1ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	272,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	272,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	272,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	272,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	272,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	273,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	273,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	273,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	274,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	276,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	276,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	276,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	276,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	276,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	276,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	276,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	276,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CS_MASK"                     ,	0,	8,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	278,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	278,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	278,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	278,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	279,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	280,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	281,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	281,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	282,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	283,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	283,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	283,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	283,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	283,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	283,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	283,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	283,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	283,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	283,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	283,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	284,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	284,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	284,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	284,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	284,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	284,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	284,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	284,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	284,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	285,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	285,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	286,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	286,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	287,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	287,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	288,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	288,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	288,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	288,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	288,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	288,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	288,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	288,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	289,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	289,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_21"               ,	2,	20,	289,	"RAZ",	1,	1,	0,	0},
+	{"DDR__PCTL"                   ,	22,	5,	289,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	27,	5,	289,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	289,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	290,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	290,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	290,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	290,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	290,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	290,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	291,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	291,	"RAZ",	1,	1,	0,	0},
+	{"WODT_LO0"                    ,	0,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO1"                    ,	4,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO2"                    ,	8,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO3"                    ,	12,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI0"                    ,	16,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI1"                    ,	20,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI2"                    ,	24,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI3"                    ,	28,	4,	292,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	292,	"RAZ",	1,	1,	0,	0},
+	{"NCBI"                        ,	0,	1,	293,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	293,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	293,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	293,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	294,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	294,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	294,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	295,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	295,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	295,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	296,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	296,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	296,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	297,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	297,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	297,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	297,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	298,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	299,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	299,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	299,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	299,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_63"              ,	37,	27,	299,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	300,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	300,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	301,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	301,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	301,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	301,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	302,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	303,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	303,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	304,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	304,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	16,	305,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	305,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	305,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	305,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	305,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	305,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	305,	"RO",	1,	1,	0,	0},
+	{"NOKASU"                      ,	29,	1,	305,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_63"              ,	30,	34,	305,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	306,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	306,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	306,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	306,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	306,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	306,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	306,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	306,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	2,	307,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	307,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	308,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	309,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	309,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	309,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	310,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	310,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	311,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	311,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	311,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	311,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	311,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	311,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	312,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	312,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	312,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	312,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	312,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	313,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	314,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	2,	315,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	315,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	316,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	316,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	316,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	316,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	316,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	316,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	316,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	316,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	317,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	317,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	317,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	317,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	317,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	317,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	317,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	317,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	318,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	318,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	319,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	319,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	319,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	320,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	320,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	321,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	322,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	323,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	323,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	323,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	323,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	323,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	323,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	323,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	324,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	324,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	325,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	325,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	326,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	326,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	326,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	326,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	327,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	327,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	327,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	328,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	328,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	328,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	328,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	328,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	328,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	328,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	328,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	328,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	329,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	330,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	330,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	330,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	330,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	330,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	330,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	330,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	330,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	330,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	331,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	331,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	332,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	332,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	333,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	333,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	333,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	333,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	334,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	334,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	335,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	335,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	336,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	336,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	337,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	337,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	337,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	337,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	338,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	338,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	339,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	339,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	340,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	340,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	341,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	341,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	342,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	342,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	343,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	343,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	344,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	344,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	344,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	344,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	344,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	344,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	345,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	346,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	346,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"POF3_BS"                     ,	5,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"POF2_BS"                     ,	6,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"POF1_BS"                     ,	7,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"POF0_BS"                     ,	8,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	347,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	347,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	348,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	348,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	349,	"R/W",	0,	1,	16ull,	0},
+	{"PCTL"                        ,	5,	5,	349,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	349,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	350,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	350,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	350,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	350,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	350,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"INS1_64B"                    ,	43,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"INS2_64B"                    ,	44,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"INS3_64B"                    ,	45,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"INS0_ENB"                    ,	46,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS1_ENB"                    ,	47,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS2_ENB"                    ,	48,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS3_ENB"                    ,	49,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT0_ENB"                    ,	50,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT1_ENB"                    ,	51,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT2_ENB"                    ,	52,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT3_ENB"                    ,	53,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIS_PNIW"                    ,	54,	1,	350,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	350,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	350,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	351,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	351,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	352,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	352,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	352,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	352,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	352,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	352,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	352,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	352,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	352,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	352,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	352,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	352,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	352,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	353,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	353,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	353,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	354,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	354,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	355,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	356,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	356,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	356,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	357,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	358,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	359,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	359,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	359,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	359,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_RR"                      ,	22,	1,	359,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	359,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO1_2SML"                    ,	4,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO2_2SML"                    ,	5,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO3_2SML"                    ,	6,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_RTOUT"                    ,	8,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_RTOUT"                    ,	9,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_RTOUT"                    ,	10,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_OVERF"                    ,	12,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_OVERF"                    ,	13,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_OVERF"                    ,	14,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RTOUT"                    ,	16,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_RTOUT"                    ,	17,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_RTOUT"                    ,	18,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PERR"                     ,	20,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PERR"                     ,	21,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PERR"                     ,	22,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"G1_RTOUT"                    ,	24,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"G2_RTOUT"                    ,	25,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"G3_RTOUT"                    ,	26,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PPERR"                    ,	28,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PPERR"                    ,	29,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PPERR"                    ,	30,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PTOUT"                    ,	32,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P2_PTOUT"                    ,	33,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P3_PTOUT"                    ,	34,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_PPERR"                    ,	36,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I2_PPERR"                    ,	37,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"I3_PPERR"                    ,	38,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_S_E"                     ,	42,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_A_F"                     ,	43,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_S_E"                     ,	44,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_A_F"                     ,	45,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_S_E"                      ,	46,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_A_F"                      ,	47,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_S_E"                      ,	48,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_A_F"                      ,	49,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_S_E"                     ,	50,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_A_F"                     ,	51,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_S_E"                     ,	52,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_A_F"                     ,	53,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"RWX_S_E"                     ,	54,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDX_S_E"                     ,	55,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_E"                     ,	56,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_F"                     ,	57,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_E"                     ,	58,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_F"                     ,	59,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_S_E"                      ,	60,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_A_F"                      ,	61,	1,	360,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	360,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	361,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO1_2SML"                    ,	4,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO2_2SML"                    ,	5,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO3_2SML"                    ,	6,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_RTOUT"                    ,	8,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_RTOUT"                    ,	9,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_RTOUT"                    ,	10,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_OVERF"                    ,	12,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_OVERF"                    ,	13,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_OVERF"                    ,	14,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RTOUT"                    ,	16,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_RTOUT"                    ,	17,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_RTOUT"                    ,	18,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PERR"                     ,	20,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PERR"                     ,	21,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PERR"                     ,	22,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G1_RTOUT"                    ,	24,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G2_RTOUT"                    ,	25,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G3_RTOUT"                    ,	26,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PPERR"                    ,	28,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PPERR"                    ,	29,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PPERR"                    ,	30,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PTOUT"                    ,	32,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P2_PTOUT"                    ,	33,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P3_PTOUT"                    ,	34,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_PPERR"                    ,	36,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2_PPERR"                    ,	37,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I3_PPERR"                    ,	38,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_S_E"                     ,	42,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_A_F"                     ,	43,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_S_E"                     ,	44,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_A_F"                     ,	45,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_S_E"                      ,	46,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_A_F"                      ,	47,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_S_E"                      ,	48,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_A_F"                      ,	49,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_S_E"                     ,	50,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_A_F"                     ,	51,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_S_E"                     ,	52,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_A_F"                     ,	53,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RWX_S_E"                     ,	54,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDX_S_E"                     ,	55,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_E"                     ,	56,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_F"                     ,	57,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_E"                     ,	58,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_F"                     ,	59,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_S_E"                      ,	60,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_A_F"                      ,	61,	1,	361,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	361,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	362,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	363,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	363,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	364,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	364,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	364,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	36,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"SHORTL"                      ,	37,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	364,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	365,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	366,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL1"                     ,	4,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL1"                     ,	5,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL1"                     ,	6,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL2"                     ,	8,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL2"                     ,	9,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL2"                     ,	10,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL3"                     ,	12,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL3"                     ,	13,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL3"                     ,	14,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"IPTR_O0"                     ,	16,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O1"                     ,	17,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O2"                     ,	18,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O3"                     ,	19,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_23"              ,	20,	4,	367,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"O1_CSRM"                     ,	25,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"O2_CSRM"                     ,	26,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"O3_CSRM"                     ,	27,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"O0_RO"                       ,	28,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O1_RO"                       ,	32,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O1_NS"                       ,	33,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O1_ES"                       ,	34,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O2_RO"                       ,	36,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O2_NS"                       ,	37,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O2_ES"                       ,	38,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O3_RO"                       ,	40,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O3_NS"                       ,	41,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"O3_ES"                       ,	42,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"P0_BMODE"                    ,	44,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"P1_BMODE"                    ,	45,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"P2_BMODE"                    ,	46,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"P3_BMODE"                    ,	47,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	48,	1,	367,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	367,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	368,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	368,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	368,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	369,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	369,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	370,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	370,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	371,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	371,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	371,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	372,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	372,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	372,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	373,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	373,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	373,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	373,	"RAZ",	1,	1,	0,	0},
+	{"PCI_OVR"                     ,	8,	4,	373,	"R/W",	0,	1,	0ull,	0},
+	{"HOSTMODE"                    ,	12,	1,	373,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	373,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	374,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	374,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	375,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	375,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	375,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	375,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	375,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	376,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	376,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	376,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	376,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	376,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	377,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	377,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	377,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	377,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	377,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	378,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	378,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	378,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	378,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	378,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	378,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	378,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	379,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	379,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	379,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_8"                      ,	8,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_13"                     ,	13,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_14"                     ,	14,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_15"                     ,	15,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_21"                     ,	21,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_24"                     ,	24,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_25"                     ,	25,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_26"                     ,	26,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_27"                     ,	27,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_28"                     ,	28,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_29"                     ,	29,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RINT_31"                     ,	31,	1,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	380,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	32,	381,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	381,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	382,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	382,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	383,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	383,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	383,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	383,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	384,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	384,	"RO",	0,	0,	64ull,	64ull},
+	{"ISAE"                        ,	0,	1,	385,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	385,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	385,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	385,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	385,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	385,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	385,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	385,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	385,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	385,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	385,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	385,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	385,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	385,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	385,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	385,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	385,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	385,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	385,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	386,	"RO",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	8,	24,	386,	"RO",	0,	0,	733184ull,	733184ull},
+	{"CLS"                         ,	0,	8,	387,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	387,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	387,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	387,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	387,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	387,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	387,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	388,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	388,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	388,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	388,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	389,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	390,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	390,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	390,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	390,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	390,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	391,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	392,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	392,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	392,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	393,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	393,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	394,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	395,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	395,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	396,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	396,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	396,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	397,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	397,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	398,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	398,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	398,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	398,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	399,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	399,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	399,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	399,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	400,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	401,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	402,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	402,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	402,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	402,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	402,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	402,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	402,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	402,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	403,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	404,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	405,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	405,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	405,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	405,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	405,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	405,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	406,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	406,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	406,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	406,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	406,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	407,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	407,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	407,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	407,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	407,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	407,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	407,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	407,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	407,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	407,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	407,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	408,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	408,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	408,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	408,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	408,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	409,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	409,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	409,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	410,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	410,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	410,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	410,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	410,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	411,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	411,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	412,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	413,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	413,	"RAZ",	1,	1,	0,	0},
+	{"PCICNT"                      ,	0,	32,	414,	"R/W",	0,	1,	0ull,	0},
+	{"AP_SPEED"                    ,	32,	2,	414,	"RO",	1,	1,	0,	0},
+	{"AP_PCIX"                     ,	34,	1,	414,	"RO",	1,	1,	0,	0},
+	{"HM_SPEED"                    ,	35,	2,	414,	"RO",	0,	1,	0ull,	0},
+	{"HM_PCIX"                     ,	37,	1,	414,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	414,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	415,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	415,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	415,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	415,	"RO",	0,	1,	0ull,	0},
+	{"AP_PCIX"                     ,	13,	1,	415,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_14"              ,	14,	1,	415,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	415,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	415,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	415,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	415,	"RO",	0,	0,	1ull,	1ull},
+	{"BB0"                         ,	20,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1"                         ,	21,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_ES"                       ,	22,	2,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_CA"                       ,	24,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_SIZ"                     ,	25,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_HOLE"                    ,	26,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	415,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	416,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	416,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	418,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	419,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	420,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT1"                      ,	18,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT2"                      ,	19,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT3"                      ,	20,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME1"                     ,	22,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME2"                     ,	23,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME3"                     ,	24,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	421,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	421,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT1"                      ,	18,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT2"                      ,	19,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT3"                      ,	20,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME1"                     ,	22,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME2"                     ,	23,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME3"                     ,	24,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	422,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	423,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	423,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	423,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT2"                       ,	19,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT3"                       ,	20,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME2"                      ,	23,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME3"                      ,	24,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	424,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	425,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	425,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	426,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	426,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	430,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	430,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	430,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	431,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	431,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	431,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	432,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	432,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	432,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	433,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	433,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	433,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	434,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	434,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	435,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	435,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	436,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	3,	45,	436,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	436,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	436,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	437,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	438,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	438,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	438,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	438,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	439,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	440,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	440,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	441,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	441,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	441,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	441,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	441,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	442,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	442,	"RAZ",	1,	1,	0,	0},
+	{"REFLECT"                     ,	0,	1,	443,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	443,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	443,	"RAZ",	1,	1,	0,	0},
+	{"IV"                          ,	0,	32,	444,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	444,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	445,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	445,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	446,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	446,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	446,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	446,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	446,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	447,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	447,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	447,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	447,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	447,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKTDRP"                      ,	0,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	448,	"RAZ",	1,	1,	0,	0},
+	{"PUNYERR"                     ,	12,	1,	448,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	448,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	449,	"RAZ",	1,	1,	0,	0},
+	{"PUNYERR"                     ,	12,	1,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	449,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	450,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	450,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	451,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	451,	"RAZ",	1,	1,	0,	0},
+	{"CRC_EN"                      ,	12,	1,	451,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	451,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	451,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT"                     ,	20,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	451,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	451,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	451,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	452,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	452,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	453,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	453,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	454,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	2,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_19"              ,	18,	2,	455,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	455,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	455,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	455,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	456,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	456,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	457,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	458,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	458,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	459,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	459,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	460,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	460,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	461,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	461,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	462,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	462,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	463,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	463,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	464,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	464,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	465,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	465,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	466,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	466,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	467,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	467,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	468,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	468,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	469,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	469,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	470,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	470,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	471,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	472,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	473,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	474,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	475,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	475,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	475,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	476,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	476,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	477,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	477,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	478,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	478,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	478,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	478,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	479,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	479,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	479,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	479,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	479,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	480,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	480,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	480,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	481,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	481,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	481,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	481,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	481,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	481,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	481,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	481,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	482,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	482,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	482,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	482,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	483,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	483,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	483,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	483,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	483,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	484,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	484,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	484,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	484,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	484,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	485,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	486,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	486,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	6,	8,	486,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	4,	486,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF_MAX"                 ,	18,	4,	486,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	22,	5,	486,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	27,	3,	486,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	30,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	31,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	32,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	33,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	34,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	35,	1,	486,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	36,	3,	486,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	39,	6,	486,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	45,	16,	486,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	61,	3,	486,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	0,	3,	487,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	3,	16,	487,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	19,	16,	487,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	35,	29,	487,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	0,	11,	488,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	488,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	489,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	489,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	489,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	489,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	489,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	489,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	490,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	490,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	490,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	490,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	490,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	490,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	490,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	491,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	491,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	491,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	491,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	492,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	492,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	492,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	492,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	492,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	492,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	492,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	492,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	492,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	493,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	493,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	493,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	493,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	493,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	494,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	4,	494,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	494,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	494,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	494,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	6,	494,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	21,	1,	494,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	22,	3,	494,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	25,	1,	494,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	26,	1,	494,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	27,	3,	494,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CRC"                     ,	30,	1,	494,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	31,	1,	494,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	32,	1,	494,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	494,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	495,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	495,	"RAZ",	1,	0,	0,	0ull},
+	{"REFIN"                       ,	0,	1,	496,	"R/W",	0,	0,	1ull,	1ull},
+	{"INVRES"                      ,	1,	1,	496,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	496,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	32,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	497,	"RAZ",	1,	0,	0,	0ull},
+	{"IV"                          ,	0,	32,	498,	"R/W",	0,	0,	1185899593ull,	1185899593ull},
+	{"RESERVED_32_63"              ,	32,	32,	498,	"RAZ",	1,	1,	0,	0},
+	{"ASSERTS"                     ,	0,	64,	499,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	0,	1,	503,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	503,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	503,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	503,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	504,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	504,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	505,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	506,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	507,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	508,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	509,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR0"                        ,	0,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR1"                        ,	1,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND0"                       ,	2,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND1"                       ,	3,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	4,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	5,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	6,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	7,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	8,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	9,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	510,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	16,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	510,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	511,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	511,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	512,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	512,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	512,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	512,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	512,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	513,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	513,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	514,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	514,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	515,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	515,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	516,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	516,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	517,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	517,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	518,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	519,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	519,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	520,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	520,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	520,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	520,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	520,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	11,	521,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	521,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	11,	521,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	521,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	12,	521,	"RO",	0,	1,	2027ull,	0},
+	{"BUF_CNT"                     ,	36,	12,	521,	"RO",	0,	1,	0ull,	0},
+	{"DES_CNT"                     ,	48,	12,	521,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	521,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	522,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	522,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	523,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	523,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	524,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	524,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	525,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	525,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	525,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	12,	526,	"RO",	0,	1,	0ull,	0},
+	{"DS_CNT"                      ,	12,	12,	526,	"RO",	0,	1,	0ull,	0},
+	{"TC_CNT"                      ,	24,	4,	526,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	526,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	527,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	527,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	527,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	527,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	527,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	11,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	528,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	11,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	528,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	528,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	528,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	528,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	529,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	529,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	530,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	531,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	531,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	532,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	532,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	532,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	532,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	532,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	532,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	533,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	533,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	1,	533,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	533,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	534,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	534,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	535,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	535,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	535,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	535,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	536,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	536,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	536,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	536,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	537,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STAT0"                       ,	0,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT1"                       ,	1,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"STAT2"                       ,	2,	1,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	538,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRXDLCK"                     ,	0,	1,	539,	"R/W",	0,	0,	0ull,	1ull},
+	{"RCVTRN"                      ,	1,	1,	539,	"R/W",	0,	0,	0ull,	1ull},
+	{"DRPTRN"                      ,	2,	1,	539,	"R/W",	0,	0,	0ull,	1ull},
+	{"SNDTRN"                      ,	3,	1,	539,	"R/W",	0,	0,	0ull,	1ull},
+	{"STATRCV"                     ,	4,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATDRV"                     ,	5,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUNBIST"                     ,	6,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLKDLY"                      ,	7,	5,	539,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_12_15"              ,	12,	4,	539,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SEETRN"                      ,	16,	1,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	539,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	540,	"RAZ",	0,	1,	0ull,	0},
+	{"D4CLK0"                      ,	4,	1,	540,	"R/W1C",	0,	1,	0ull,	0},
+	{"D4CLK1"                      ,	5,	1,	540,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK0"                      ,	6,	1,	540,	"R/W1C",	0,	1,	0ull,	0},
+	{"S4CLK1"                      ,	7,	1,	540,	"R/W1C",	0,	1,	0ull,	0},
+	{"SRXTRN"                      ,	8,	1,	540,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_9_9"                ,	9,	1,	540,	"RAZ",	0,	1,	0ull,	0},
+	{"STXCAL"                      ,	10,	1,	540,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	540,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLLDIS"                      ,	0,	1,	541,	"R/W",	1,	0,	0,	0ull},
+	{"DLLFRC"                      ,	1,	1,	541,	"WR0",	1,	0,	0,	0ull},
+	{"OFFDLY"                      ,	2,	6,	541,	"R/W",	1,	0,	0,	0ull},
+	{"BITSEL"                      ,	8,	5,	541,	"R/W",	1,	1,	0,	0},
+	{"OFFSET"                      ,	13,	5,	541,	"R/W",	1,	1,	0,	0},
+	{"MUX"                         ,	18,	1,	541,	"WR0",	1,	1,	0,	0},
+	{"INC"                         ,	19,	1,	541,	"WR0",	1,	1,	0,	0},
+	{"DEC"                         ,	20,	1,	541,	"WR0",	1,	1,	0,	0},
+	{"CLRDLY"                      ,	21,	1,	541,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_22_23"              ,	22,	2,	541,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SSTEP"                       ,	24,	1,	541,	"R/W",	1,	0,	0,	0ull},
+	{"SSTEP_GO"                    ,	25,	1,	541,	"WR0",	1,	1,	0,	0},
+	{"RESERVED_26_27"              ,	26,	2,	541,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FALL8"                       ,	28,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALLNOP"                     ,	29,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	541,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OFFSET"                      ,	0,	5,	542,	"RO",	0,	1,	0ull,	0},
+	{"MUXSEL"                      ,	5,	2,	542,	"RO",	0,	1,	0ull,	0},
+	{"UNXTERM"                     ,	7,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TESTRES"                     ,	8,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	542,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SRX4CMP"                     ,	0,	10,	543,	"R/W",	0,	0,	239ull,	239ull},
+	{"RESERVED_10_15"              ,	10,	6,	543,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STX4PCMP"                    ,	16,	4,	543,	"R/W",	0,	0,	3ull,	3ull},
+	{"STX4NCMP"                    ,	20,	4,	543,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_24_63"              ,	24,	40,	543,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ERRCNT"                      ,	0,	4,	544,	"R/W",	0,	0,	0ull,	3ull},
+	{"RESERVED_4_5"                ,	4,	2,	544,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPPAY"                      ,	6,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPCLS"                      ,	7,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	8,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	544,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT"                         ,	0,	8,	545,	"RO",	0,	0,	0ull,	0ull},
+	{"RSVOP"                       ,	8,	4,	545,	"RO",	0,	0,	0ull,	0ull},
+	{"CALBNK"                      ,	12,	2,	545,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_30"              ,	14,	17,	545,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUL"                         ,	31,	1,	545,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	545,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	546,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	546,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_30"              ,	12,	19,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPF"                         ,	31,	1,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	0,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABNORM"                      ,	1,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	548,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPIOVR"                      ,	4,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLSERR"                      ,	5,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRWNNG"                      ,	6,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	7,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"TPAOVR"                      ,	8,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"DIPERR"                      ,	9,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	10,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"CALERR"                      ,	11,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	548,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	549,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	549,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX"                         ,	0,	32,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	550,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRTSEL"                      ,	0,	4,	551,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	551,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MUX_EN"                      ,	0,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"MACRO_EN"                    ,	1,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXDIST"                     ,	2,	5,	552,	"R/W",	0,	0,	0ull,	8ull},
+	{"SET_BOOT"                    ,	7,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR_BOOT"                    ,	8,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"JITTER"                      ,	9,	3,	552,	"R/W",	0,	0,	0ull,	1ull},
+	{"TRNTEST"                     ,	12,	1,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	552,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	553,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	553,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	553,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRTS"                        ,	4,	4,	553,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	553,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNORE"                      ,	0,	16,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	554,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PRT0"                        ,	0,	4,	555,	"R/W",	1,	1,	0,	0},
+	{"PRT1"                        ,	4,	4,	555,	"R/W",	1,	1,	0,	0},
+	{"PRT2"                        ,	8,	4,	555,	"R/W",	1,	1,	0,	0},
+	{"PRT3"                        ,	12,	4,	555,	"R/W",	1,	1,	0,	0},
+	{"ODDPAR"                      ,	16,	1,	555,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_17_63"              ,	17,	47,	555,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	0,	7,	556,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	556,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	556,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	556,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	4,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC"                         ,	4,	4,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOD"                         ,	8,	4,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOP"                         ,	12,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOP"                         ,	13,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	557,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DAT"                         ,	0,	64,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_2"                ,	0,	3,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	3,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINTRN"                      ,	5,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	559,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	560,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	560,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INF_EN"                      ,	0,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_2"                ,	1,	2,	561,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ST_EN"                       ,	3,	1,	561,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	561,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIPMAX"                      ,	0,	4,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMMAX"                      ,	4,	4,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	562,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IGNTPA"                      ,	0,	16,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	563,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CALPAR0"                     ,	0,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RESERVED_8_63"               ,	8,	56,	564,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"FRMERR"                      ,	7,	1,	565,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNCERR"                     ,	8,	1,	565,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	565,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"FRMERR"                      ,	7,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	566,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MINB"                        ,	0,	9,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	567,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_7_7"                ,	7,	1,	570,	"RAZ",	0,	0,	0ull,	0ull},
+	{"M"                           ,	8,	8,	570,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	570,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	571,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	0,	32,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	572,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"CLR"                         ,	4,	1,	573,	"WR0",	0,	0,	0ull,	0ull},
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+	{"CNT"                         ,	0,	32,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	574,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_46_46"              ,	46,	1,	575,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	575,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	575,	"RAZ",	1,	0,	0,	0ull},
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+	{"BASE"                        ,	20,	31,	576,	"RO",	1,	0,	0,	0ull},
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+	{"CSIZE"                       ,	8,	13,	577,	"RO",	1,	0,	0,	0ull},
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+	{"NUM_BUCKETS"                 ,	4,	20,	578,	"R/W",	0,	0,	0ull,	0ull},
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+	{"POOL"                        ,	39,	3,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	579,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	580,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	580,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	580,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	580,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	581,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
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+	{"MASK"                        ,	0,	16,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	583,	"RAZ",	1,	0,	0,	0ull},
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+	{"INC"                         ,	8,	8,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	584,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	585,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
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+	{"MCD0_ENA"                    ,	13,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	586,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RPTR"                        ,	8,	8,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	588,	"RO",	0,	0,	0ull,	0ull},
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+	{"RPTR"                        ,	12,	10,	588,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	588,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	24,	40,	588,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	589,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	589,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_36_63"              ,	36,	28,	590,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"PL2"                         ,	1,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBLD8"                      ,	10,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBLD32"                     ,	12,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	591,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	591,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	592,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	592,	"R/W",	0,	0,	0ull,	3ull},
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+	{"RNG"                         ,	8,	1,	592,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	592,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	592,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	592,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	592,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_20_63"              ,	20,	44,	593,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"CIU_THR"                     ,	1,	1,	594,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	594,	"R/W1C",	0,	0,	0ull,	0ull},
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+	{"RESERVED_36_63"              ,	36,	28,	596,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_36_63"              ,	36,	28,	597,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"PL2"                         ,	1,	1,	598,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	598,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBLD8"                      ,	10,	1,	598,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBST"                       ,	14,	1,	598,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	598,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	598,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	598,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	599,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	599,	"R/W",	0,	0,	0ull,	3ull},
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+	{"RNG"                         ,	8,	1,	599,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	599,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	599,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	599,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	599,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RESERVED_20_63"              ,	20,	44,	600,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	601,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	601,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	602,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	603,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	603,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	604,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	604,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	604,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	604,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	604,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	605,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP_CTL"                     ,	0,	4,	606,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	606,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	606,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	607,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	607,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	608,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	608,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	609,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	609,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	609,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	609,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	609,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	610,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	611,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	611,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	612,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	11,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	11},
+	{"cvmx_agl_gmx_drv_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	6,	13},
+	{"cvmx_agl_gmx_inf_mode"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	3,	19},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	7,	22},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	11,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	10,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	15,	11,	53},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	64},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	17,	2,	66},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	68},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	19,	19,	70},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	19,	89},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	21,	2,	108},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	110},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	23,	2,	112},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	114},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	25,	2,	116},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	118},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	27,	2,	120},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	122},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	29,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	31,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	32,	2,	130},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	33,	4,	132},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	136},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	35,	2,	138},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	2,	140},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	37,	4,	142},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	4,	146},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	39,	2,	150},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	3,	152},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	41,	5,	155},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	3,	160},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	43,	2,	163},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	165},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	45,	2,	167},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	169},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	47,	2,	171},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	173},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	49,	2,	175},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	177},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	51,	2,	179},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	181},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	53,	2,	183},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	185},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	55,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	57,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	193},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	59,	2,	195},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	197},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	61,	2,	199},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	2,	201},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	63,	3,	203},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	10,	206},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	10,	216},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	226},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	67,	2,	228},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	6,	230},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	69,	2,	236},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	70,	2,	238},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	71,	2,	240},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	72,	2,	242},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	73,	2,	244},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	74,	2,	246},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	75,	21,	248},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	100,	2,	269},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	125,	21,	271},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	137,	2,	292},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	149,	21,	294},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	174,	21,	315},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	186,	2,	336},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	187,	2,	338},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	199,	2,	340},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	211,	2,	342},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	212,	2,	344},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	213,	2,	346},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	214,	1,	348},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	226,	3,	349},
+	{"cvmx_ciu_qlm_dcok"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	227,	2,	352},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	228,	5,	354},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	229,	6,	359},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	230,	2,	365},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	231,	2,	367},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	232,	2,	369},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	233,	2,	371},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	234,	3,	373},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	238,	7,	376},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	250,	6,	383},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	251,	7,	389},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	3,	396},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	259,	2,	399},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	266,	3,	401},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	267,	2,	404},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	268,	29,	406},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	269,	29,	435},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	270,	2,	464},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	278,	2,	466},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	286,	3,	468},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	287,	3,	471},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	288,	2,	474},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	289,	2,	476},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	290,	7,	478},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	292,	2,	485},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	294,	2,	487},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	296,	7,	489},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	298,	2,	496},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	300,	10,	498},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	308,	1,	508},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	316,	1,	509},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	324,	1,	510},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	332,	1,	511},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	340,	1,	512},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	348,	1,	513},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	356,	2,	514},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	364,	4,	516},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	372,	2,	520},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	380,	9,	522},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	388,	10,	531},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	396,	2,	541},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	404,	25,	543},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	412,	25,	568},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	420,	2,	593},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	428,	2,	595},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	436,	2,	597},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	444,	2,	599},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	452,	2,	601},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	460,	2,	603},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	468,	2,	605},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	476,	2,	607},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	484,	2,	609},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	492,	2,	611},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	500,	2,	613},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	508,	2,	615},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	516,	4,	617},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	524,	2,	621},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	532,	2,	623},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	540,	2,	625},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	548,	4,	627},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	550,	2,	631},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	552,	5,	633},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	554,	2,	638},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	556,	2,	640},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	564,	3,	642},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	566,	5,	645},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	574,	2,	650},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	582,	3,	652},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	590,	2,	655},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	598,	2,	657},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	606,	2,	659},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	614,	2,	661},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	622,	2,	663},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	630,	2,	665},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	638,	2,	667},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	646,	2,	669},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	654,	2,	671},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	662,	2,	673},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	670,	2,	675},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	678,	2,	677},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	686,	2,	679},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	694,	2,	681},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	702,	2,	683},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	710,	2,	685},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	718,	2,	687},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	726,	2,	689},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	734,	2,	691},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	742,	2,	693},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	750,	2,	695},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	752,	2,	697},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	754,	2,	699},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	756,	3,	701},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	758,	8,	704},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	760,	8,	712},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	762,	2,	720},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	764,	2,	722},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	766,	6,	724},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	768,	2,	730},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	770,	2,	732},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	772,	2,	734},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	774,	9,	736},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	776,	3,	745},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	778,	9,	748},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	794,	2,	757},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	798,	2,	759},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	799,	2,	761},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	800,	2,	763},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	801,	2,	765},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	19,	767},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	6,	786},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	3,	792},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	805,	3,	795},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	806,	3,	798},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	807,	5,	801},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	808,	5,	806},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	809,	1,	811},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	1,	812},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	811,	7,	813},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	7,	820},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	813,	3,	827},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	814,	3,	830},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	815,	3,	833},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	816,	5,	836},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	817,	5,	841},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	818,	1,	846},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	819,	1,	847},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	820,	3,	848},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	821,	3,	851},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	822,	3,	854},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	823,	2,	857},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	824,	2,	859},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	825,	2,	861},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	826,	2,	863},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	827,	19,	865},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	828,	2,	884},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	829,	1,	886},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	830,	15,	887},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	831,	13,	902},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	832,	13,	915},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	833,	2,	928},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	834,	2,	930},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	835,	2,	932},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	836,	3,	934},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	844,	3,	937},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	848,	2,	940},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	852,	2,	942},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	860,	2,	944},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	956,	1,	946},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	959,	1,	947},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	962,	6,	948},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	963,	5,	954},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	964,	6,	959},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	965,	7,	965},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	966,	2,	972},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	974,	2,	974},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	975,	3,	976},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	976,	2,	979},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	977,	5,	981},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	985,	3,	986},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	986,	4,	989},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	987,	3,	993},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	988,	2,	996},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	989,	2,	998},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	990,	4,	1000},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	991,	3,	1004},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	992,	5,	1007},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	993,	5,	1012},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	994,	7,	1017},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	995,	11,	1024},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	996,	8,	1035},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	997,	15,	1043},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	998,	8,	1058},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	999,	5,	1066},
+	{"cvmx_l2c_grpwrr0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1000,	2,	1071},
+	{"cvmx_l2c_grpwrr1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1001,	2,	1073},
+	{"cvmx_l2c_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1002,	10,	1075},
+	{"cvmx_l2c_int_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1003,	10,	1085},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1004,	4,	1095},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1005,	2,	1099},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1006,	14,	1101},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1007,	19,	1115},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1008,	3,	1134},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1009,	3,	1137},
+	{"cvmx_l2c_oob"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1010,	3,	1140},
+	{"cvmx_l2c_oob1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1011,	6,	1143},
+	{"cvmx_l2c_oob2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1012,	6,	1149},
+	{"cvmx_l2c_oob3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1013,	6,	1155},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1014,	2,	1161},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1018,	17,	1163},
+	{"cvmx_l2c_ppgrp"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1019,	13,	1180},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1020,	5,	1193},
+	{"cvmx_l2c_spar1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1021,	5,	1198},
+	{"cvmx_l2c_spar2"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1022,	5,	1203},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1023,	2,	1208},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1024,	3,	1210},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1025,	2,	1213},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1026,	2,	1215},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1027,	2,	1217},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1028,	7,	1219},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1029,	5,	1226},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1030,	3,	1231},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1031,	3,	1234},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1032,	2,	1237},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1033,	2,	1239},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1034,	2,	1241},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1035,	6,	1243},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1036,	14,	1249},
+	{"cvmx_led_blink"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1037,	2,	1263},
+	{"cvmx_led_clk_phase"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1038,	2,	1265},
+	{"cvmx_led_cylon"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1039,	2,	1267},
+	{"cvmx_led_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1040,	2,	1269},
+	{"cvmx_led_en"                 ,	CVMX_CSR_DB_TYPE_RSL,	64,	1041,	2,	1271},
+	{"cvmx_led_polarity"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1042,	2,	1273},
+	{"cvmx_led_prt"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1043,	2,	1275},
+	{"cvmx_led_prt_fmt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1044,	2,	1277},
+	{"cvmx_led_prt_status#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1045,	2,	1279},
+	{"cvmx_led_udd_cnt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1053,	2,	1281},
+	{"cvmx_led_udd_dat#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1055,	2,	1283},
+	{"cvmx_led_udd_dat_clr#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1057,	2,	1285},
+	{"cvmx_led_udd_dat_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	2,	1287},
+	{"cvmx_lmc#_bist_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1061,	2,	1289},
+	{"cvmx_lmc#_bist_result"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1063,	8,	1291},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1065,	7,	1299},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1067,	19,	1306},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1069,	8,	1325},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1071,	2,	1333},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1073,	2,	1335},
+	{"cvmx_lmc#_dclk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1075,	5,	1337},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1077,	18,	1342},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1079,	6,	1360},
+	{"cvmx_lmc#_dll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1081,	5,	1366},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1083,	5,	1371},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1085,	5,	1376},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1087,	6,	1381},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1089,	2,	1387},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1091,	2,	1389},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1093,	14,	1391},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1095,	9,	1405},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1097,	2,	1414},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1099,	2,	1416},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1101,	12,	1418},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1103,	6,	1430},
+	{"cvmx_lmc#_read_level_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1105,	7,	1436},
+	{"cvmx_lmc#_read_level_dbg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1107,	4,	1443},
+	{"cvmx_lmc#_read_level_rank#"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1109,	11,	1447},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1117,	6,	1458},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1119,	9,	1464},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1121,	5,	1473},
+	{"cvmx_lmc#_wodt_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1123,	5,	1478},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1125,	5,	1483},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1126,	3,	1488},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1127,	10,	1491},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1130,	3,	1501},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1133,	3,	1504},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1136,	15,	1507},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1139,	3,	1522},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1140,	3,	1525},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1141,	3,	1528},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1142,	5,	1531},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1144,	1,	1536},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1145,	13,	1537},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1153,	13,	1550},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1161,	6,	1563},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1162,	1,	1569},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1166,	2,	1570},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	2,	1572},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	13,	1574},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	8,	1587},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	4,	1595},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	1,	1599},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	3,	1600},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1173,	2,	1603},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1174,	6,	1605},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1175,	7,	1611},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1176,	4,	1618},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1177,	2,	1622},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1178,	2,	1624},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1179,	13,	1626},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1181,	12,	1639},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1183,	3,	1651},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1185,	3,	1654},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1187,	2,	1657},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1189,	2,	1659},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1191,	2,	1661},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1193,	7,	1663},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1195,	2,	1670},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1197,	7,	1672},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1199,	4,	1679},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1201,	8,	1683},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1203,	9,	1691},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1205,	7,	1700},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1207,	9,	1707},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1209,	2,	1716},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1211,	2,	1718},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1213,	4,	1720},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1215,	2,	1724},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1217,	2,	1726},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1219,	2,	1728},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1221,	4,	1730},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1223,	2,	1734},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1225,	2,	1736},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1227,	2,	1738},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1229,	2,	1740},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1231,	2,	1742},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1233,	2,	1744},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1235,	6,	1746},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1237,	5,	1752},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	1238,	8,	1757},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1239,	8,	1765},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1240,	2,	1773},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1241,	3,	1775},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1242,	5,	1778},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1243,	4,	1783},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	1244,	8,	1787},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1245,	2,	1795},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1246,	2,	1797},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1247,	5,	1799},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1248,	4,	1804},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1249,	4,	1808},
+	{"cvmx_npei_bar1_index#"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	1250,	5,	1812},
+	{"cvmx_npei_bist_status"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1282,	59,	1817},
+	{"cvmx_npei_ctl_port0"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1283,	17,	1876},
+	{"cvmx_npei_ctl_port1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1284,	17,	1893},
+	{"cvmx_npei_ctl_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1285,	6,	1910},
+	{"cvmx_npei_ctl_status2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1286,	11,	1916},
+	{"cvmx_npei_data_out_cnt"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1287,	5,	1927},
+	{"cvmx_npei_dbg_data"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1288,	8,	1932},
+	{"cvmx_npei_dbg_select"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1289,	2,	1940},
+	{"cvmx_npei_dma#_counts"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1290,	3,	1942},
+	{"cvmx_npei_dma#_dbell"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	1295,	2,	1945},
+	{"cvmx_npei_dma#_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1300,	3,	1947},
+	{"cvmx_npei_dma#_naddr"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1305,	2,	1950},
+	{"cvmx_npei_dma0_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1310,	2,	1952},
+	{"cvmx_npei_dma1_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1311,	2,	1954},
+	{"cvmx_npei_dma_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1312,	2,	1956},
+	{"cvmx_npei_dma_control"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1313,	16,	1958},
+	{"cvmx_npei_dma_state1_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1314,	11,	1974},
+	{"cvmx_npei_dma_state2_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1315,	6,	1985},
+	{"cvmx_npei_dma_state3_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1316,	5,	1991},
+	{"cvmx_npei_dma_state4_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1317,	5,	1996},
+	{"cvmx_npei_dma_state5_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1318,	3,	2001},
+	{"cvmx_npei_int_enb"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1319,	63,	2004},
+	{"cvmx_npei_int_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1320,	62,	2067},
+	{"cvmx_npei_int_info"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1321,	3,	2129},
+	{"cvmx_npei_int_sum"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1322,	60,	2132},
+	{"cvmx_npei_last_win_rdata0"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1323,	1,	2192},
+	{"cvmx_npei_last_win_rdata1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1324,	1,	2193},
+	{"cvmx_npei_mem_access_ctl"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1325,	3,	2194},
+	{"cvmx_npei_mem_access_subid#" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1326,	11,	2197},
+	{"cvmx_npei_msi_enb0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1342,	1,	2208},
+	{"cvmx_npei_msi_enb1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1343,	1,	2209},
+	{"cvmx_npei_msi_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1344,	1,	2210},
+	{"cvmx_npei_msi_enb3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1345,	1,	2211},
+	{"cvmx_npei_msi_rcv0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1346,	1,	2212},
+	{"cvmx_npei_msi_rcv1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1347,	1,	2213},
+	{"cvmx_npei_msi_rcv2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1348,	1,	2214},
+	{"cvmx_npei_msi_rcv3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1349,	1,	2215},
+	{"cvmx_npei_msi_rd_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1350,	3,	2216},
+	{"cvmx_npei_msi_wr_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1351,	3,	2219},
+	{"cvmx_npei_pcie_msi_rcv"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1352,	2,	2222},
+	{"cvmx_npei_pcie_msi_rcv_b1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1353,	3,	2224},
+	{"cvmx_npei_pcie_msi_rcv_b2"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1354,	3,	2227},
+	{"cvmx_npei_pcie_msi_rcv_b3"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1355,	3,	2230},
+	{"cvmx_npei_rsl_int_blocks"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1356,	29,	2233},
+	{"cvmx_npei_scratch_1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1357,	1,	2262},
+	{"cvmx_npei_state1"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1358,	4,	2263},
+	{"cvmx_npei_state2"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1359,	7,	2267},
+	{"cvmx_npei_state3"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1360,	5,	2274},
+	{"cvmx_npei_win_rd_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1361,	4,	2279},
+	{"cvmx_npei_win_rd_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1362,	1,	2283},
+	{"cvmx_npei_win_wr_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1363,	4,	2284},
+	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1364,	1,	2288},
+	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1365,	2,	2289},
+	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1366,	2,	2291},
+	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1367,	2,	2293},
+	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1368,	24,	2295},
+	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1369,	4,	2319},
+	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1370,	5,	2323},
+	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1371,	5,	2328},
+	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1372,	2,	2333},
+	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1373,	1,	2335},
+	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1374,	1,	2336},
+	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1375,	5,	2337},
+	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1376,	2,	2342},
+	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1377,	1,	2344},
+	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1378,	1,	2345},
+	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1379,	4,	2346},
+	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1380,	2,	2350},
+	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1381,	2,	2352},
+	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1382,	1,	2354},
+	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1383,	1,	2355},
+	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1384,	2,	2356},
+	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1385,	3,	2358},
+	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1386,	2,	2361},
+	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1387,	2,	2363},
+	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1388,	4,	2365},
+	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1389,	10,	2369},
+	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1390,	12,	2379},
+	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1391,	7,	2391},
+	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1392,	2,	2398},
+	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1393,	1,	2400},
+	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1394,	2,	2401},
+	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1395,	7,	2403},
+	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1396,	11,	2410},
+	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1397,	19,	2421},
+	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1398,	11,	2440},
+	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1399,	17,	2451},
+	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1400,	12,	2468},
+	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1401,	22,	2480},
+	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1402,	3,	2502},
+	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1403,	3,	2505},
+	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1404,	1,	2508},
+	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1405,	1,	2509},
+	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1406,	1,	2510},
+	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1407,	1,	2511},
+	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1408,	3,	2512},
+	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1409,	14,	2515},
+	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1410,	14,	2529},
+	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1411,	14,	2543},
+	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1412,	9,	2557},
+	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1413,	9,	2566},
+	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1414,	6,	2575},
+	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1415,	1,	2581},
+	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1416,	1,	2582},
+	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1417,	1,	2583},
+	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1418,	1,	2584},
+	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1419,	2,	2585},
+	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1420,	1,	2587},
+	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1421,	6,	2588},
+	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1422,	6,	2594},
+	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1423,	13,	2600},
+	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1424,	5,	2613},
+	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1425,	8,	2618},
+	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1426,	19,	2626},
+	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1427,	3,	2645},
+	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1428,	1,	2648},
+	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1429,	1,	2649},
+	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1430,	3,	2650},
+	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1431,	3,	2653},
+	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1432,	3,	2656},
+	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1433,	4,	2659},
+	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1434,	4,	2663},
+	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1435,	4,	2667},
+	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1436,	7,	2671},
+	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1437,	5,	2678},
+	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1438,	5,	2683},
+	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1439,	4,	2688},
+	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1440,	4,	2692},
+	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1441,	4,	2696},
+	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1442,	1,	2700},
+	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1443,	1,	2701},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1444,	2,	2702},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1446,	24,	2704},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1448,	4,	2728},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1450,	5,	2732},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1452,	1,	2737},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1454,	1,	2738},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1456,	4,	2739},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1458,	17,	2743},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1460,	4,	2760},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1462,	6,	2764},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1464,	1,	2770},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1466,	1,	2771},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1468,	2,	2772},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1470,	2,	2774},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1472,	1,	2776},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1474,	15,	2777},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1476,	10,	2792},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1478,	12,	2802},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1480,	7,	2814},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1482,	2,	2821},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1484,	1,	2823},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1486,	2,	2824},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1488,	7,	2826},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1490,	11,	2833},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1492,	19,	2844},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1494,	11,	2863},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1496,	20,	2874},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1498,	12,	2894},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1500,	22,	2906},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1502,	8,	2928},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1504,	4,	2936},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1506,	3,	2940},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1508,	3,	2943},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1510,	1,	2946},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1512,	1,	2947},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1514,	1,	2948},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1516,	1,	2949},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1518,	3,	2950},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1520,	14,	2953},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1522,	14,	2967},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1524,	14,	2981},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1526,	9,	2995},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1528,	9,	3004},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1530,	6,	3013},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1532,	1,	3019},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1534,	1,	3020},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1536,	1,	3021},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1538,	1,	3022},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1540,	4,	3023},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1542,	9,	3027},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1544,	2,	3036},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1546,	2,	3038},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1548,	1,	3040},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1550,	6,	3041},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1552,	6,	3047},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1554,	13,	3053},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1556,	5,	3066},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1558,	8,	3071},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1560,	19,	3079},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1562,	3,	3098},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1564,	1,	3101},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1566,	1,	3102},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1568,	3,	3103},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1570,	3,	3106},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1572,	3,	3109},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1574,	4,	3112},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1576,	4,	3116},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1578,	4,	3120},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1580,	7,	3124},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1582,	5,	3131},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1584,	5,	3136},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1586,	4,	3141},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1588,	4,	3145},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1590,	4,	3149},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1592,	1,	3153},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1594,	1,	3154},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1596,	9,	3155},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1604,	6,	3164},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1612,	9,	3170},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1620,	6,	3179},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1628,	13,	3185},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1636,	13,	3198},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1644,	2,	3211},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1652,	4,	3213},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1660,	8,	3217},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1668,	13,	3225},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1676,	17,	3238},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1684,	7,	3255},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1692,	3,	3262},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1700,	8,	3265},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1708,	7,	3273},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1716,	4,	3280},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1724,	5,	3284},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1732,	8,	3289},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1734,	2,	3297},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1736,	5,	3299},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1738,	10,	3304},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1740,	2,	3314},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1742,	7,	3316},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1744,	7,	3323},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1746,	6,	3330},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1748,	5,	3336},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1750,	5,	3341},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1752,	3,	3346},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1754,	6,	3349},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1756,	9,	3355},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1758,	3,	3364},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1760,	9,	3367},
+	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1762,	13,	3376},
+	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1764,	15,	3389},
+	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1766,	2,	3404},
+	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1768,	2,	3406},
+	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1770,	2,	3408},
+	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1772,	16,	3410},
+	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1774,	2,	3426},
+	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1776,	32,	3428},
+	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1778,	32,	3460},
+	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1780,	5,	3492},
+	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1782,	2,	3497},
+	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1784,	2,	3499},
+	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1786,	2,	3501},
+	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	2,	3503},
+	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1796,	2,	3505},
+	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	8,	3507},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1806,	5,	3515},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1807,	2,	3520},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	4,	3522},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1812,	3,	3526},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1814,	8,	3529},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1815,	18,	3537},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1816,	13,	3555},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1817,	13,	3568},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	2,	3581},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	27,	3583},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1831,	25,	3610},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1843,	2,	3635},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1907,	2,	3637},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1915,	9,	3639},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1923,	2,	3648},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1924,	2,	3650},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1925,	2,	3652},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1937,	2,	3654},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1949,	2,	3656},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1961,	2,	3658},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1973,	2,	3660},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1985,	2,	3662},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1997,	2,	3664},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2009,	2,	3666},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2021,	2,	3668},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2033,	2,	3670},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2045,	2,	3672},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2046,	2,	3674},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2058,	2,	3676},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2070,	2,	3678},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2082,	2,	3680},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2146,	2,	3682},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2147,	3,	3684},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2148,	3,	3687},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2149,	2,	3690},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2150,	2,	3692},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2151,	4,	3694},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2152,	5,	3698},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2153,	4,	3703},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2154,	8,	3707},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2155,	4,	3715},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2156,	5,	3719},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2157,	1,	3724},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2158,	5,	3725},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2159,	1,	3730},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2160,	13,	3731},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2161,	4,	3744},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2162,	13,	3748},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2163,	6,	3761},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2164,	9,	3767},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2165,	4,	3776},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2166,	7,	3780},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2167,	5,	3787},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2168,	5,	3792},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2169,	4,	3797},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2170,	9,	3801},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2171,	5,	3810},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2172,	16,	3815},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2173,	4,	3831},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2174,	1,	3835},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2175,	1,	3836},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	1,	3837},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2177,	1,	3838},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	11,	3839},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2179,	2,	3850},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	4,	3852},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2181,	5,	3856},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	3,	3861},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	4,	3864},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2184,	2,	3868},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2185,	3,	3870},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2186,	3,	3873},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2187,	13,	3876},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2188,	2,	3889},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2189,	13,	3891},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2190,	3,	3904},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2191,	2,	3907},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2199,	2,	3909},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2200,	2,	3911},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2201,	2,	3913},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2202,	2,	3915},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2210,	2,	3917},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2211,	2,	3919},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2212,	2,	3921},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2213,	10,	3923},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2225,	5,	3933},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2233,	8,	3938},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2241,	2,	3946},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2242,	2,	3948},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2243,	2,	3950},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2251,	3,	3952},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2252,	4,	3955},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2268,	5,	3959},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2269,	7,	3964},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2285,	2,	3971},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2301,	1,	3973},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2302,	1,	3974},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2303,	1,	3975},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2304,	5,	3976},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2305,	5,	3981},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2306,	4,	3986},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2307,	10,	3990},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2308,	1,	4000},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2309,	3,	4001},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2310,	7,	4004},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2311,	2,	4011},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2312,	1,	4013},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2313,	1,	4014},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2314,	1,	4015},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2315,	18,	4016},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2316,	3,	4034},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2317,	2,	4037},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2318,	3,	4039},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2319,	7,	4042},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2320,	2,	4049},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2321,	2,	4051},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2322,	2,	4053},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2323,	3,	4055},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2324,	3,	4058},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2325,	7,	4061},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2326,	10,	4068},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2328,	6,	4078},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2330,	2,	4084},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2332,	4,	4086},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2334,	4,	4090},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2336,	6,	4094},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2337,	3,	4100},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2338,	5,	4103},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2339,	4,	4108},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2340,	6,	4112},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2341,	4,	4118},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2342,	2,	4122},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2343,	4,	4124},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2344,	2,	4128},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2345,	3,	4130},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	4,	4133},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	12,	4137},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	3,	4149},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	5,	4152},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	2,	4157},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2351,	2,	4159},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	18,	4161},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	12,	4179},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	6,	4191},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	5,	4197},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	1,	4202},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	2,	4203},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4205},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	18,	4207},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	12,	4225},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	6,	4237},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	2,	4243},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	2,	4245},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	18,	4247},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	12,	4265},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	6,	4277},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2367,	2,	4283},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2368,	2,	4285},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2369,	8,	4287},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2370,	11,	4295},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2371,	15,	4306},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2376,	8,	4321},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2381,	8,	4329},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2382,	4,	4337},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2387,	15,	4341},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2392,	6,	4356},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2397,	6,	4362},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2398,	4,	4368},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2403,	2,	4372},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2407,	6,	4374},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2408,	4,	4380},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2409,	1,	4384},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2410,	1,	4385},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2411,	1,	4386},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2412,	7,	4387},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2413,	1,	4394},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2414,	14,	4395},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2415,	10,	4409},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2416,	14,	4419},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2417,	32,	4433},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2418,	32,	4465},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2419,	2,	4497},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2420,	4,	4499},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2421,	13,	4503},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2422,	10,	4516},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2423,	10,	4526},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2424,	2,	4536},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2425,	6,	4538},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2426,	5,	4544},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2427,	6,	4549},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2428,	5,	4555},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2429,	1,	4560},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2430,	13,	4561},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2431,	2,	4574},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2432,	2,	4576},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2433,	11,	4578},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2441,	3,	4589},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	2442,	12,	4592},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2450,	12,	4604},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2458,	6,	4616},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2466,	4,	4622},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2474,	2,	4626},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2475,	2,	4628},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2476,	15,	4630},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2477,	2,	4645},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2478,	3,	4647},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2479,	1,	4650},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2487,	6,	4651},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2488,	8,	4657},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2489,	15,	4665},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2490,	6,	4680},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2491,	2,	4686},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2492,	2,	4688},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2493,	2,	4690},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2494,	2,	4692},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2495,	2,	4694},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2496,	2,	4696},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2497,	2,	4698},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2498,	2,	4700},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2499,	2,	4702},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2500,	2,	4704},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2501,	2,	4706},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2502,	2,	4708},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2503,	2,	4710},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2504,	2,	4712},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2505,	2,	4714},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2506,	2,	4716},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2507,	7,	4718},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2508,	34,	4725},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2509,	34,	4759},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2510,	35,	4793},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2511,	3,	4828},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2512,	5,	4831},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2513,	3,	4836},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2514,	6,	4839},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	2515,	2,	4845},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	2516,	2,	4847},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2517,	2,	4849},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT20_EN0"               ,	   0x1070000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT21_EN0"               ,	   0x1070000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT22_EN0"               ,	   0x1070000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT20_EN1"               ,	   0x1070000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT21_EN1"               ,	   0x1070000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET10"              ,	   0x1070000000650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET11"              ,	   0x1070000000658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_QLM_DCOK"                ,	   0x1070000000760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX1_CLK_EN"                 ,	   0x11800100007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180010000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180010000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180010001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180010001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX_XAUI_BAD_COL"        ,	   0x1180010000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_RX_XAUI_CTL"            ,	   0x1180010000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180010000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180010001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX1_TX_XAUI_CTL"            ,	   0x1180010000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GMX1_XAUI_EXT_LOOPBACK"      ,	   0x1180010000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14F0000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14F0000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14F0000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14F0000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14F0000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14F0000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14F0000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14F0000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14F0000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14F0000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14F0000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14F0000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14F0000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14F0000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14F0000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14F0000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14F0000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14F0000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14F0000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14F0000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14F0000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14F0000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14F0000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14F0000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14F0000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14F0000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14F0000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14F0000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14F0000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14F0000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14F0000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14F0000000D80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC1_BIST_CTL"               ,	   0x11800E80000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LMC1_BIST_RESULT"            ,	   0x11800E80000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LMC1_COMP_CTL"               ,	   0x11800E8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LMC1_CTL"                    ,	   0x11800E8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC1_CTL1"                   ,	   0x11800E8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LMC1_DCLK_CNT_HI"            ,	   0x11800E8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LMC1_DCLK_CNT_LO"            ,	   0x11800E8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LMC0_DCLK_CTL"               ,	   0x11800880000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LMC1_DCLK_CTL"               ,	   0x11800E80000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"LMC1_DDR2_CTL"               ,	   0x11800E8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"LMC1_DELAY_CFG"              ,	   0x11800E8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LMC1_DLL_CTL"                ,	   0x11800E80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LMC1_DUAL_MEMCFG"            ,	   0x11800E8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LMC1_ECC_SYND"               ,	   0x11800E8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LMC1_FADR"                   ,	   0x11800E8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC1_IFB_CNT_HI"             ,	   0x11800E8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC1_IFB_CNT_LO"             ,	   0x11800E8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC1_MEM_CFG0"               ,	   0x11800E8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC1_MEM_CFG1"               ,	   0x11800E8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC1_OPS_CNT_HI"             ,	   0x11800E8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC1_OPS_CNT_LO"             ,	   0x11800E8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC1_PLL_CTL"                ,	   0x11800E80000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC1_PLL_STATUS"             ,	   0x11800E80000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC1_READ_LEVEL_CTL"         ,	   0x11800E8000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"LMC1_READ_LEVEL_DBG"         ,	   0x11800E8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK000"     ,	   0x11800E8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK001"     ,	   0x11800E8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK002"     ,	   0x11800E8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_READ_LEVEL_RANK003"     ,	   0x11800E8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC1_RODT_COMP_CTL"          ,	   0x11800E80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"LMC1_RODT_CTL"               ,	   0x11800E8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"LMC1_WODT_CTL0"              ,	   0x11800E8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"LMC1_WODT_CTL1"              ,	   0x11800E8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_BOOT_DMA_CFG2"           ,	   0x1180000000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_BOOT_DMA_INT2"           ,	   0x1180000000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_BOOT_DMA_INT_EN2"        ,	   0x1180000000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_DMA_TIM2"           ,	   0x1180000000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	408},
+	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	409},
+	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	410},
+	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	411},
+	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	412},
+	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	413},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	414},
+	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	415},
+	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	416},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA4_COUNTS"            ,	   0x11F0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA4_DBELL"             ,	   0x11F00000083F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	418},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11F0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA4_NADDR"             ,	   0x11F00000084E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	421},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	423},
+	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA_STATE1_P1"          ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA_STATE2_P1"          ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
+	{"NPEI_DMA_STATE3_P1"          ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
+	{"NPEI_DMA_STATE4_P1"          ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
+	{"NPEI_DMA_STATE5_P1"          ,	   0x11F00000086C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
+	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
+	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
+	{"NPEI_INT_INFO"               ,	   0x11F0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
+	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	436},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	457},
+	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	458},
+	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	459},
+	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	460},
+	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	461},
+	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	463},
+	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	464},
+	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	465},
+	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	466},
+	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	467},
+	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	468},
+	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	469},
+	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	470},
+	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	471},
+	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	472},
+	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	473},
+	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	474},
+	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	475},
+	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	476},
+	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	477},
+	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	478},
+	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	479},
+	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	480},
+	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	481},
+	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	482},
+	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	483},
+	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	484},
+	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	485},
+	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	486},
+	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	487},
+	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	488},
+	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	489},
+	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	490},
+	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	491},
+	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	492},
+	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	493},
+	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	494},
+	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	495},
+	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	496},
+	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	497},
+	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	498},
+	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	499},
+	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	500},
+	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	501},
+	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	502},
+	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	503},
+	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	504},
+	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	505},
+	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	506},
+	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	507},
+	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	508},
+	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	509},
+	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	510},
+	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	511},
+	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	512},
+	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	513},
+	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	514},
+	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	515},
+	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	516},
+	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	517},
+	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	518},
+	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	519},
+	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	520},
+	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	521},
+	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	522},
+	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	523},
+	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	524},
+	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	525},
+	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
+	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
+	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
+	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
+	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
+	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
+	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
+	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
+	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
+	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
+	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
+	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
+	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
+	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	540},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	540},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	541},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	541},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	542},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	542},
+	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	543},
+	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	543},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	544},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	544},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	545},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	545},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	546},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	546},
+	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
+	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
+	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
+	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
+	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
+	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
+	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
+	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
+	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
+	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
+	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
+	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
+	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
+	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
+	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
+	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
+	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
+	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
+	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
+	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
+	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
+	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
+	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
+	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
+	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
+	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
+	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
+	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
+	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
+	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800B8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800B8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800B8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800B8001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	616},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800B8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800B8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800B8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800B8001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	617},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800B8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800B8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800B8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800B8001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	618},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800B8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800B8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800B8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800B8001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	619},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800B8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800B8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800B8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800B8001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	620},
+	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT000_REG"             ,	   0x11800B8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT001_REG"             ,	   0x11800B8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT002_REG"             ,	   0x11800B8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS1_INT003_REG"             ,	   0x11800B8001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	621},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800B8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800B8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800B8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800B8001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	622},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800B8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800B8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800B8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800B8001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800B8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800B8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800B8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800B8001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800B8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800B8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800B8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800B8001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800B8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800B8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800B8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800B8001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800B8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800B8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800B8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800B8001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800B8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800B8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800B8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800B8001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800B8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800B8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800B8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800B8001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800B8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800B8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800B8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800B8001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800B8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800B8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800B8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800B8001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800B8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800B8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800B8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800B8001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	736},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	737},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	738},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	739},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	740},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	741},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	742},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	743},
+	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	744},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	756},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	820},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	821},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	822},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	823},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	824},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	825},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	826},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	827},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	828},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	874},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	875},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	876},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	877},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	878},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	879},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	880},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	881},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	882},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	900},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_21"               ,	3,	19,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_25"              ,	23,	3,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYP_EN"                      ,	16,	1,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	2,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	3,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"DUPLEX"                      ,	2,	1,	4,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_EN"                       ,	4,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	4,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	9,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	10,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	11,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	11,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	12,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	12,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	12,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	12,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	13,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	13,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	14,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	14,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	15,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	16,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	16,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	17,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	17,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	18,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	18,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"MAXERR"                      ,	2,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	19,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	19,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	20,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	21,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	21,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	22,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	22,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	32,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	32,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	33,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	35,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	35,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	36,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	36,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	37,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	37,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	1,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	38,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	1,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	38,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	39,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	39,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	40,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	40,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	40,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	1,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	68,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	68,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	68,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	71,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	12,	72,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	72,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	12,	73,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	73,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	74,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	74,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	75,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	12,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	76,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	12,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	78,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	80,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	12,	81,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	81,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	82,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	83,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	12,	84,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	84,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	85,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	85,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	12,	86,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	86,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	87,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	88,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	11,	88,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	88,	"RAZ",	1,	1,	0,	0},
+	{"QLM_DCOK"                    ,	0,	4,	89,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	89,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	4,	90,	"R/W",	0,	1,	0ull,	0},
+	{"MUX_SEL"                     ,	4,	2,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	90,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	90,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	91,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	91,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_60"              ,	37,	24,	91,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	91,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	91,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	91,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	92,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	93,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	93,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	94,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	94,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	95,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	95,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	96,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	97,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	97,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	97,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	98,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	99,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	100,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	100,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	100,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	101,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	101,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	102,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	102,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	102,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	103,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	103,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	104,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	105,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	105,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	106,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	107,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	107,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	108,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	108,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	108,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	109,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	109,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	109,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	110,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	110,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	111,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	111,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	112,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	112,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	112,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	112,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	112,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	112,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	112,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	113,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	113,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	114,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	114,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	115,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	115,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	2,	115,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	115,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	2,	115,	"RO",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	115,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	116,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	116,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	117,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	117,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	117,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	117,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	117,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	117,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	117,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	117,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	117,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	118,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	119,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	120,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	121,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	122,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	123,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	124,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	124,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	125,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	125,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	125,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	125,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	126,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	126,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	127,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	127,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	127,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	127,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	127,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	127,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	127,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	128,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	128,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	128,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	128,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	128,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	128,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	128,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	128,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	128,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	129,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	129,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	130,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	130,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	130,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	130,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	130,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	130,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	131,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	131,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	131,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	131,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	131,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	131,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	131,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	132,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	132,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	133,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	133,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	134,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	135,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	135,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	136,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	137,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	138,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	139,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	140,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	141,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	142,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	142,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	143,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	143,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	144,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	144,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	145,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	145,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	146,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	146,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	147,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	147,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	148,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	148,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	149,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	149,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	150,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	150,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	150,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	150,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	150,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	151,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	151,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	152,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	152,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	153,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	153,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	154,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	154,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	154,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	154,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	154,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	155,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	155,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	156,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	156,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	156,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	157,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	157,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	158,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	158,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	159,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	159,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	160,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	160,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	161,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	161,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	162,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	162,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	163,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	163,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	164,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	164,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	165,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	165,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	166,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	166,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	167,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	167,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	168,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	168,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	169,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	169,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	170,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	170,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	171,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	171,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	172,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	172,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	173,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	173,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	174,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	174,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	175,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	176,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	176,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	177,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	177,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	178,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	178,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	179,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	179,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	180,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	180,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	180,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	181,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	181,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	181,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	182,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	183,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	183,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	184,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	184,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	185,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	185,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	186,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	186,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	187,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	187,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	188,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	188,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	189,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	189,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	189,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	189,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	189,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	190,	"R/W",	0,	0,	8ull,	8ull},
+	{"EN"                          ,	4,	1,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	190,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	191,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	192,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	192,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	193,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	193,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	194,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	195,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	195,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	196,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	196,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	197,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	198,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	198,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	198,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	198,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	199,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	200,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	200,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	200,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	201,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	202,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	202,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	202,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	202,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	202,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	203,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	203,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	203,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	203,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	203,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	204,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	205,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	206,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	207,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	208,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	209,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	210,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	211,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	211,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	211,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	211,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	211,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	212,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	212,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	212,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	212,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	212,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	213,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	214,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	215,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	216,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	217,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	218,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	218,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	219,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	220,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	221,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	222,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	40,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	223,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	225,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	225,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	226,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	227,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	228,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	229,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	229,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	230,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	230,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	231,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	232,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	233,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	233,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	234,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	234,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	235,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	235,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	236,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	237,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	238,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	238,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	238,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	238,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	238,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	239,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	239,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	239,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_44_63"              ,	44,	20,	239,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	240,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	241,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	241,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	241,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	241,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	241,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	241,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	242,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	242,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	243,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	244,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	4,	245,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	245,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	246,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	246,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	246,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	246,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	246,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	247,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	247,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	247,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	248,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	248,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	248,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	248,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	249,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	249,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	249,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	250,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	250,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	251,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	251,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	252,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	253,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	253,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	253,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	254,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	254,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	254,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	254,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	254,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	255,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	255,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	255,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	255,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	255,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	13,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	256,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF0"                   ,	9,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	257,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF1"                   ,	11,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF0"                       ,	12,	4,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF1"                       ,	16,	4,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"ILC"                         ,	20,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC0"                        ,	21,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC1"                        ,	22,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC2"                        ,	23,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	257,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"PICBST"                      ,	2,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RHDB"                        ,	4,	4,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RMDB"                        ,	8,	4,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	258,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	259,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	259,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	259,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	259,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	259,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFILL_DIS"                   ,	14,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPRES0"                      ,	15,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPRES1"                      ,	16,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_BANK"                    ,	17,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBIST"                       ,	18,	1,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSTRUN"                      ,	19,	1,	259,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	259,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	4,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	4,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	260,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	261,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	261,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	261,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	261,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PLC0RMSK"                    ,	0,	32,	262,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC1RMSK"                    ,	32,	32,	262,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC2RMSK"                    ,	0,	32,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILCRMSK"                     ,	32,	32,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"OOB1EN"                      ,	0,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB2EN"                      ,	1,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB3EN"                      ,	2,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TSECEN"                    ,	3,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TDEDEN"                    ,	4,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DSECEN"                    ,	5,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDEDEN"                    ,	6,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKENA"                      ,	7,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCK2ENA"                     ,	8,	1,	264,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OOB1"                        ,	0,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB2"                        ,	1,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB3"                        ,	2,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TSEC"                      ,	3,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TDED"                      ,	4,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DSEC"                      ,	5,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DDED"                      ,	6,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK"                         ,	7,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK2"                        ,	8,	1,	265,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	265,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	266,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	4,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	4,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	268,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	268,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	11,	270,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	11,	16,	270,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	270,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	4,	271,	"R/W",	0,	0,	15ull,	15ull},
+	{"STPARTDIS"                   ,	4,	1,	271,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	271,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STENA"                       ,	0,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWBENA"                      ,	1,	1,	272,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	273,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	273,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	274,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	274,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	275,	"RO",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP0GRP"                      ,	0,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP1GRP"                      ,	2,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP2GRP"                      ,	4,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP3GRP"                      ,	6,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP4GRP"                      ,	8,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP5GRP"                      ,	10,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP6GRP"                      ,	12,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP7GRP"                      ,	14,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP8GRP"                      ,	16,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP9GRP"                      ,	18,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP10GRP"                     ,	20,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP11GRP"                     ,	22,	2,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	278,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	279,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	279,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	279,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	279,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	279,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK4"                       ,	0,	8,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK5"                       ,	8,	8,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK6"                       ,	16,	8,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK7"                       ,	24,	8,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK8"                       ,	0,	8,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK9"                       ,	8,	8,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK10"                      ,	16,	8,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK11"                      ,	24,	8,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	284,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	285,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	286,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	287,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	287,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	287,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	11,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"FADRU"                       ,	18,	1,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	289,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	290,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	293,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_1024K"                  ,	34,	1,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_512K"                   ,	35,	1,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	294,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	3,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	294,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	10,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	295,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"FADRU"                       ,	28,	1,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	295,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RATE"                        ,	0,	8,	296,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_63"               ,	8,	56,	296,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	7,	297,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_7_63"               ,	7,	57,	297,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	0,	16,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	298,	"RAZ",	1,	1,	0,	0},
+	{"DBG_EN"                      ,	0,	1,	299,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	299,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	300,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	300,	"RAZ",	1,	1,	0,	0},
+	{"POLARITY"                    ,	0,	1,	301,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	301,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	8,	302,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	302,	"RAZ",	1,	1,	0,	0},
+	{"FORMAT"                      ,	0,	4,	303,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	303,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	304,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	304,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	305,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	32,	306,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	306,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	32,	307,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	307,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	32,	308,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	308,	"RAZ",	1,	1,	0,	0},
+	{"START"                       ,	0,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	309,	"RAZ",	1,	0,	0,	0ull},
+	{"MRD"                         ,	0,	3,	310,	"RO",	1,	0,	0,	0ull},
+	{"MRF"                         ,	3,	1,	310,	"RO",	1,	0,	0,	0ull},
+	{"MWC"                         ,	4,	1,	310,	"RO",	1,	0,	0,	0ull},
+	{"MWD"                         ,	5,	3,	310,	"RO",	1,	0,	0,	0ull},
+	{"MWF"                         ,	8,	1,	310,	"RO",	1,	0,	0,	0ull},
+	{"CSRE2D"                      ,	9,	1,	310,	"RO",	1,	0,	0,	0ull},
+	{"CSRD2E"                      ,	10,	1,	310,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	310,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL_DAT"                    ,	0,	5,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_11"               ,	5,	7,	311,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	311,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	311,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	311,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	311,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	312,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	312,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	312,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	312,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	312,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	11,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	312,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	312,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	312,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	312,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	312,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	312,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	312,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	312,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	313,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	313,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEQUENCE"                    ,	10,	3,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLEPOWER"                   ,	13,	3,	313,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	16,	4,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	20,	1,	313,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_63"              ,	21,	43,	313,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	314,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	315,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	315,	"RAZ",	1,	1,	0,	0},
+	{"DCLK90_VLU"                  ,	0,	5,	316,	"R/W",	0,	1,	0ull,	0},
+	{"DCLK90_LD"                   ,	5,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"DCLK90_BYP"                  ,	6,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"OFF90_ENA"                   ,	7,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	316,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	317,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	317,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	317,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	317,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	317,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	317,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	317,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	317,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	318,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	318,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	318,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	318,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	318,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	318,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	0,	5,	319,	"R/W",	0,	1,	0ull,	0},
+	{"DLL90_ENA"                   ,	5,	1,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	6,	1,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	7,	1,	319,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	319,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	320,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	320,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	320,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	320,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	321,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	322,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	323,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	323,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	324,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	325,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	325,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	325,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	325,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	325,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	325,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	325,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	325,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	325,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	325,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	326,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	326,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	326,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	326,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	326,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	326,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	326,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	326,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	326,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	327,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	328,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	329,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	329,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	329,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	329,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	329,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	329,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	329,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	330,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	330,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_21"               ,	2,	20,	330,	"RAZ",	1,	1,	0,	0},
+	{"DDR__PCTL"                   ,	22,	5,	330,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	27,	5,	330,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	330,	"RAZ",	1,	1,	0,	0},
+	{"BNK"                         ,	0,	3,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	331,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COL"                         ,	4,	12,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW"                         ,	16,	16,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"PATTERN"                     ,	32,	8,	331,	"R/W",	0,	0,	170ull,	170ull},
+	{"RANKMASK"                    ,	40,	4,	331,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	331,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE"                        ,	0,	4,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	332,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	16,	16,	332,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	332,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	4,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	8,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	12,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	16,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	20,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	24,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	28,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	32,	4,	333,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	36,	2,	333,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	333,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL"                        ,	0,	5,	334,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	334,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	334,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	334,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	334,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	334,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO1"                    ,	4,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO2"                    ,	8,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO3"                    ,	12,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI0"                    ,	16,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI1"                    ,	20,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI2"                    ,	24,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI3"                    ,	28,	4,	335,	"R/W",	0,	0,	15ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	335,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	336,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	336,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	336,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	336,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	336,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WODT_D2_R0"                  ,	0,	8,	337,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	8,	8,	337,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	16,	8,	337,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	24,	8,	337,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	337,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NCBI"                        ,	0,	1,	338,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	338,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA"                         ,	2,	1,	338,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	3,	1,	338,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	338,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	339,	"R/W",	0,	1,	31ull,	0},
+	{"PCTL"                        ,	5,	5,	339,	"R/W",	0,	1,	31ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	339,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	340,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	340,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	340,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	341,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	341,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	341,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	342,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	343,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	343,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	343,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	344,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	344,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	345,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	346,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	346,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	347,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	347,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	347,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	348,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	349,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	349,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	349,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	349,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	349,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	350,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	350,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	351,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	351,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	351,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	351,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	351,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	351,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	352,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	353,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	353,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	354,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	354,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	12,	355,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_15"              ,	12,	4,	355,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	355,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	355,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	355,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	355,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	355,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	355,	"RO",	1,	1,	0,	0},
+	{"NOKASU"                      ,	29,	1,	355,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_31"              ,	30,	2,	355,	"RAZ",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	355,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	355,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	355,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	356,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	356,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	356,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	356,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	356,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	356,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	356,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	356,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	357,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	357,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	357,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	357,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	358,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	359,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	359,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	359,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	360,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	360,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	361,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	361,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	361,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	361,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	361,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	361,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	362,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	362,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	362,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	362,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	362,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	363,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	363,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	363,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	363,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	364,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	364,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	3,	365,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_3_63"               ,	3,	61,	365,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	366,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	366,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	366,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	366,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	366,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	366,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	366,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	366,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	367,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	367,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	367,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	367,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	367,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	367,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	367,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	368,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	368,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	369,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	369,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	369,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	370,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	370,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	371,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	371,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	372,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	372,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	373,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	373,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	373,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	373,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	373,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	373,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	373,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	374,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	374,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	375,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	375,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	376,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	376,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	376,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	376,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	377,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	377,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	377,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	378,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	378,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	378,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	378,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	378,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	378,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	378,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	378,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	378,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	379,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	380,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	380,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	380,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	380,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	380,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	380,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	380,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	380,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	380,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	381,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	381,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	382,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	382,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	383,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	383,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	383,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	383,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	384,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	385,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	385,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	386,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	386,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	387,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	387,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	387,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	387,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	388,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	388,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	389,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	389,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	390,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	390,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	391,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	391,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	392,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	392,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	393,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	393,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	394,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	394,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	394,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	394,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	394,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	394,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	395,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	395,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	396,	"R/W",	0,	0,	1ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	396,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	5,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	396,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	396,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	396,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	397,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	397,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	398,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	398,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	399,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	399,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	400,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	33,	400,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	400,	"RAZ",	1,	1,	0,	0},
+	{"ISIZE"                       ,	40,	20,	400,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	400,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	401,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	401,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	401,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	402,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	402,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	402,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	402,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	403,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	404,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	405,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	33,	405,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	405,	"RAZ",	1,	1,	0,	0},
+	{"OSIZE"                       ,	40,	20,	405,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	405,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	406,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	406,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	406,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	406,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	407,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	407,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	408,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	408,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	408,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	408,	"RAZ",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF4"                        ,	2,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF3"                        ,	3,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF2"                        ,	4,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF1"                        ,	5,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF0"                        ,	6,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM1"                        ,	7,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM0"                        ,	8,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P1"                     ,	9,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_CO"                     ,	19,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_NO"                     ,	20,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_PO"                     ,	21,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_CO"                     ,	22,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_NO"                     ,	23,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_PO"                     ,	24,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P1"                      ,	25,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D4_PST"                      ,	31,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_PST"                      ,	32,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_PST"                      ,	33,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_PST"                      ,	34,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_PST"                      ,	35,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D4_MEM"                      ,	36,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_MEM"                      ,	37,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_MEM"                      ,	38,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_MEM"                      ,	39,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_MEM"                      ,	40,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_S1"                      ,	41,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_S0"                      ,	42,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_I1"                      ,	43,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_I0"                      ,	44,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_OUT"                     ,	45,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_OIF"                     ,	46,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_ODF"                     ,	47,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_SLM"                     ,	48,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_IND"                     ,	49,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNTM"                    ,	50,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_IMEM"                    ,	51,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_POUT"                    ,	52,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_SL"                     ,	53,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_ID"                     ,	54,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_CNT"                    ,	55,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_IM"                     ,	56,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_INT"                    ,	57,	1,	409,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	409,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	410,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	410,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	410,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	410,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	410,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	410,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	410,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	410,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	410,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	410,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	410,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	410,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	411,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	411,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	411,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	411,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	411,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	411,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	411,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	411,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	411,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	411,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	411,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	411,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	412,	"RO",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	8,	1,	412,	"RO",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	9,	4,	412,	"R/W",	0,	0,	15ull,	15ull},
+	{"ARB"                         ,	13,	1,	412,	"R/W",	0,	0,	0ull,	1ull},
+	{"LNK_RST"                     ,	14,	1,	412,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	412,	"RAZ",	1,	1,	0,	0},
+	{"C0_B0_D"                     ,	0,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_WI_D"                     ,	1,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_B0_D"                     ,	2,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_WI_D"                     ,	3,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_B1_S"                     ,	4,	3,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"C1_B1_S"                     ,	7,	3,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"C0_W_FLT"                    ,	10,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_W_FLT"                    ,	11,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRRS"                        ,	12,	3,	413,	"R/W",	0,	0,	2ull,	2ull},
+	{"MPS"                         ,	15,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	413,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	414,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	414,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	414,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	414,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	414,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	415,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	415,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	415,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	23,	2,	415,	"RO",	1,	1,	0,	0},
+	{"QLM3_SPD"                    ,	25,	2,	415,	"RO",	1,	1,	0,	0},
+	{"QLM0_REV_LANES"              ,	27,	1,	415,	"RO",	1,	1,	0,	0},
+	{"QLM2_REV_LANES"              ,	28,	1,	415,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	415,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	416,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	416,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	417,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	418,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	418,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	419,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	419,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	419,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	420,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	420,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	421,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	421,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	32,	422,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	422,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0"                        ,	0,	32,	423,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1"                        ,	32,	32,	423,	"R/W",	0,	1,	0ull,	0},
+	{"CSIZE"                       ,	0,	14,	424,	"R/W",	0,	1,	0ull,	0},
+	{"O_MODE"                      ,	14,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	424,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	424,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	424,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	424,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	424,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	424,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA0_ENB"                    ,	34,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_ENB"                    ,	35,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2_ENB"                    ,	36,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3_ENB"                    ,	37,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4_ENB"                    ,	38,	1,	424,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_39_63"              ,	39,	25,	424,	"RAZ",	1,	1,	0,	0},
+	{"D4_REQST"                    ,	0,	5,	425,	"RO",	0,	1,	0ull,	0},
+	{"D3_REQST"                    ,	5,	5,	425,	"RO",	0,	1,	0ull,	0},
+	{"D2_REQST"                    ,	10,	5,	425,	"RO",	0,	1,	0ull,	0},
+	{"D1_REQST"                    ,	15,	5,	425,	"RO",	0,	1,	0ull,	0},
+	{"D0_REQST"                    ,	20,	5,	425,	"RO",	0,	1,	0ull,	0},
+	{"D4_DIFST"                    ,	25,	7,	425,	"RO",	0,	1,	0ull,	0},
+	{"D3_DIFST"                    ,	32,	7,	425,	"RO",	0,	1,	0ull,	0},
+	{"D2_DIFST"                    ,	39,	7,	425,	"RO",	0,	1,	0ull,	0},
+	{"D1_DIFST"                    ,	46,	7,	425,	"RO",	0,	1,	0ull,	0},
+	{"D0_DIFST"                    ,	53,	7,	425,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	425,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D4_DFFST"                    ,	0,	9,	426,	"RO",	0,	1,	0ull,	0},
+	{"D3_DFFST"                    ,	9,	9,	426,	"RO",	0,	1,	0ull,	0},
+	{"D2_DFFST"                    ,	18,	9,	426,	"RO",	0,	1,	0ull,	0},
+	{"D1_DFFST"                    ,	27,	9,	426,	"RO",	0,	1,	0ull,	0},
+	{"D0_DFFST"                    ,	36,	9,	426,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	426,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_DREST"                    ,	0,	15,	427,	"RO",	0,	1,	0ull,	0},
+	{"D2_DREST"                    ,	15,	15,	427,	"RO",	0,	1,	0ull,	0},
+	{"D1_DREST"                    ,	30,	15,	427,	"RO",	0,	1,	0ull,	0},
+	{"D0_DREST"                    ,	45,	15,	427,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	427,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_DWEST"                    ,	0,	13,	428,	"RO",	0,	1,	0ull,	0},
+	{"D2_DWEST"                    ,	13,	13,	428,	"RO",	0,	1,	0ull,	0},
+	{"D1_DWEST"                    ,	26,	13,	428,	"RO",	0,	1,	0ull,	0},
+	{"D0_DWEST"                    ,	39,	13,	428,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	428,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D4_DWEST"                    ,	0,	13,	429,	"RO",	0,	1,	0ull,	0},
+	{"D4_DREST"                    ,	13,	15,	429,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	429,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4DBO"                     ,	8,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0FI"                      ,	9,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_20"              ,	20,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_29"              ,	29,	1,	430,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_61_62"              ,	61,	2,	430,	"RAZ",	0,	1,	0ull,	0},
+	{"MIO_INTA"                    ,	63,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_RTO"                     ,	0,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4DBO"                     ,	8,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0FI"                      ,	9,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_20"              ,	20,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_27_27"              ,	27,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_29"              ,	29,	1,	431,	"RAZ",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	431,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_61_63"              ,	61,	3,	431,	"RAZ",	0,	1,	0ull,	0},
+	{"PSLDBOF"                     ,	0,	6,	432,	"RO",	0,	1,	0ull,	0},
+	{"PIDBOF"                      ,	6,	6,	432,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	432,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA4DBO"                     ,	8,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0FI"                      ,	9,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_18"              ,	15,	4,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_29"              ,	29,	1,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	433,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_61_62"              ,	61,	2,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	433,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	434,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	435,	"RO",	0,	1,	0ull,	0},
+	{"TIMER"                       ,	0,	10,	436,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	436,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	437,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	30,	1,	437,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	31,	1,	437,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	32,	1,	437,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	33,	1,	437,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	437,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	437,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	2,	437,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	41,	1,	437,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	437,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	438,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	439,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	440,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	441,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	442,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	443,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	444,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	445,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	446,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	446,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	446,	"RAZ",	1,	1,	0,	0},
+	{"MSI_INT"                     ,	0,	8,	447,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	447,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	447,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	448,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	448,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	449,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	449,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	449,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	450,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	450,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	450,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	451,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	451,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	451,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"NPEI"                        ,	3,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	15,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASXPCS0"                     ,	22,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"ASXPCS1"                     ,	23,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_27"              ,	24,	4,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	28,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC1"                        ,	29,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	452,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	452,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	453,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	454,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	454,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	454,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	454,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	455,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	455,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	455,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	455,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	455,	"RO",	0,	1,	1ull,	0},
+	{"NPEI"                        ,	47,	1,	455,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	455,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	456,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	456,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	456,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	456,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	456,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	457,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	457,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	457,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	457,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	458,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_1"                ,	0,	2,	459,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	2,	46,	459,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	459,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	460,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	461,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	461,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	462,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	462,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	463,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	463,	"RO/WRSL",	0,	0,	80ull,	80ull},
+	{"ISAE"                        ,	0,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	464,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	464,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	464,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	464,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	464,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	465,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	465,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	465,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	465,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	466,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	467,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	467,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	467,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	467,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	468,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	468,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	470,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	471,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	471,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	471,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	471,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	472,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	472,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	474,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	475,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	475,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	475,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	475,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	476,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	476,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_6"                ,	0,	7,	477,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	7,	25,	477,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	478,	"WORSL",	0,	0,	127ull,	127ull},
+	{"CISP"                        ,	0,	32,	479,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	480,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	480,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	481,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	482,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	482,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"CP"                          ,	0,	8,	483,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	483,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	484,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	484,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	484,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	484,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	485,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	485,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	485,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	485,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	485,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	485,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	485,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	485,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	485,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	485,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	486,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	486,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	486,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	486,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	486,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	486,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	487,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	487,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	487,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	487,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	487,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	488,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	488,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	489,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	490,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	491,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	491,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	491,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	491,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	491,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	491,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	491,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	492,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	492,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	492,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	492,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	492,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	492,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	492,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	492,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	492,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	493,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	493,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	493,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	493,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	493,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	494,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	494,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	494,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	494,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	494,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	494,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	494,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	494,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	494,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	494,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	494,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	495,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	495,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	495,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	495,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	495,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	495,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	495,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	495,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	495,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	495,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	495,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	495,	"RAZ",	1,	1,	0,	0},
+	{"ABP"                         ,	0,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	496,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIC"                         ,	8,	2,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCC"                         ,	10,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	497,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	497,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"EMIS"                        ,	23,	1,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	497,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	497,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	498,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	498,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	498,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	499,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	499,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	500,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	501,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	502,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	503,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	504,	"RO",	0,	0,	1ull,	0ull},
+	{"CV"                          ,	16,	4,	504,	"RO",	0,	0,	1ull,	0ull},
+	{"NCO"                         ,	20,	12,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	505,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	505,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	505,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	505,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	505,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	506,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	506,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	506,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	506,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	507,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	507,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	507,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	507,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	507,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	507,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	507,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	507,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	508,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	508,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	508,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	508,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	509,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	509,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	509,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	509,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	510,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	510,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	511,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	513,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	514,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	515,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	515,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	516,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	517,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	517,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	517,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	517,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	518,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	518,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	518,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	518,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	518,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	518,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	519,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	519,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	519,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	519,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	519,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_24"              ,	22,	3,	519,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	519,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	519,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	520,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	520,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	520,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	520,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	520,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	521,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	521,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	521,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	521,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	521,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	521,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	521,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	522,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	522,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	522,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	523,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	523,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	524,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	525,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	526,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	526,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	526,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	527,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	528,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	529,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	530,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	532,	"RO/WRSL",	0,	0,	72ull,	72ull},
+	{"HEADER_CREDITS"              ,	12,	8,	532,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	532,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	532,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	532,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	532,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	532,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	533,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	533,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	533,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	533,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	533,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	534,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	534,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	534,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	534,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	534,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	535,	"RO/WRSL",	0,	0,	216ull,	216ull},
+	{"RESERVED_14_15"              ,	14,	2,	535,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	535,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	535,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	536,	"RO/WRSL",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	536,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	536,	"RO/WRSL",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	536,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	537,	"RO/WRSL",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	537,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	537,	"RO/WRSL",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	537,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	540,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	540,	"R/W",	0,	0,	80ull,	80ull},
+	{"ISAE"                        ,	0,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	541,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	541,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	541,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	541,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	541,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	541,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	542,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	542,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	543,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	543,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	543,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	543,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	544,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	545,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	546,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	547,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	547,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	547,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	547,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	547,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	548,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	548,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	549,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	549,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	549,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	549,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	551,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	553,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	553,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	554,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	555,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	555,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	555,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	556,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	556,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	556,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	556,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	556,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	557,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	557,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	557,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	557,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	558,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	558,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	558,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	558,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	559,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	561,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	561,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	562,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	562,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	562,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	562,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	563,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	563,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	563,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	563,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	563,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	564,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	564,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	564,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	564,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	564,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	564,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	564,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	564,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	564,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	565,	"R/W",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	565,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	565,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	565,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	565,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	565,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	565,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	565,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	565,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	566,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	566,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	566,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	566,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	566,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	566,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	566,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	566,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	566,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	568,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	568,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	568,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	568,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	568,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	568,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	568,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	569,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	569,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	570,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	570,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	570,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	570,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	571,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	571,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	572,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	573,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	574,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	575,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	576,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	577,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	577,	"RO",	0,	0,	1ull,	1ull},
+	{"NCO"                         ,	20,	12,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	578,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	578,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	578,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	578,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	579,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	579,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	579,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	580,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	580,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	580,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	580,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	581,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	581,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	581,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	581,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	582,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	582,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	582,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	582,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	583,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	583,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	583,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	584,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	586,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	588,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	589,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	589,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	591,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	591,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	592,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	593,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	593,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	593,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	593,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	593,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	594,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	594,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	594,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	594,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	594,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	594,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	595,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	595,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	595,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	595,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	595,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_24"              ,	22,	3,	595,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	595,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	596,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	597,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	597,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	597,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	597,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	597,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	597,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	598,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	598,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	599,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	600,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	602,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	603,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	603,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	603,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	604,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	605,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	606,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	608,	"R/W",	0,	0,	72ull,	72ull},
+	{"HEADER_CREDITS"              ,	12,	8,	608,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	608,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	608,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	608,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	608,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	608,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	609,	"R/W",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	609,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	609,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	609,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	609,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	610,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	610,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_20_20"              ,	20,	1,	610,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	610,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	610,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	611,	"R/W",	0,	0,	216ull,	216ull},
+	{"RESERVED_14_15"              ,	14,	2,	611,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	611,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	611,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	612,	"R/W",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	612,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	612,	"R/W",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	612,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	613,	"R/W",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	613,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	613,	"R/W",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	613,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	615,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	616,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	616,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	616,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	616,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	616,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	616,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	616,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	616,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	617,	"RAZ",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	617,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	617,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	617,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	617,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	618,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	618,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	618,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	618,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	619,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	619,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	620,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	620,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	621,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	621,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	622,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	622,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	623,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	623,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	624,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	624,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	624,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	625,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	625,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	625,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	625,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	625,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	625,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	626,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	626,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	626,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	626,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	626,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	626,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	626,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	627,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	628,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	629,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	629,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	629,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	629,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	629,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	629,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	629,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	629,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	630,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	630,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	630,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	630,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	630,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	630,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	630,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	631,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	631,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	631,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	631,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	632,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	632,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	633,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	633,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	633,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	633,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	633,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	633,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	633,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	634,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	635,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	635,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	635,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	635,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	635,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	636,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	636,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	636,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	636,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	636,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	636,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	636,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	637,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	637,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	638,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	638,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	638,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	638,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	638,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	638,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	638,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	639,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	639,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	640,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	640,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	641,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	641,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	641,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	642,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	642,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	642,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	642,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	642,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	643,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	643,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	643,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	644,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	644,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	644,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	644,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	644,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	645,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	645,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	645,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	645,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	645,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	645,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	645,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	645,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	645,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	646,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	647,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	647,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	647,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	647,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA4"                     ,	3,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	4,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	5,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	6,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	7,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	8,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"PTLP_OR"                     ,	9,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"NTLP_OR"                     ,	10,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"CTLP_OR"                     ,	11,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	648,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"RSL_P2E"                     ,	6,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	7,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_P2E"                     ,	8,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_RSL"                     ,	9,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	10,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	11,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	12,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"CTO_P2E"                     ,	13,	1,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	649,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	650,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	650,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	651,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	651,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	652,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	653,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	653,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	653,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	13,	2,	653,	"RO",	1,	1,	0,	0},
+	{"PBUS"                        ,	15,	8,	653,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	23,	5,	653,	"RO",	1,	1,	0,	0},
+	{"RESERVED_28_63"              ,	28,	36,	653,	"RAZ",	1,	1,	0,	0},
+	{"PCIERST"                     ,	0,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	654,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	655,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	655,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	656,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	657,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	658,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	659,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_38"               ,	0,	39,	660,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	39,	25,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	661,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	661,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	662,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	662,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"NPEI_P"                      ,	0,	5,	663,	"R/W",	0,	0,	2ull,	2ull},
+	{"NPEI_NP"                     ,	5,	5,	663,	"R/W",	0,	0,	2ull,	2ull},
+	{"NPEI_CPL"                    ,	10,	5,	663,	"R/W",	0,	0,	2ull,	2ull},
+	{"PESC_P"                      ,	15,	5,	663,	"R/W",	0,	0,	2ull,	2ull},
+	{"PESC_NP"                     ,	20,	5,	663,	"R/W",	0,	0,	2ull,	2ull},
+	{"PESC_CPL"                    ,	25,	5,	663,	"R/W",	0,	0,	2ull,	2ull},
+	{"PEAI_PPF"                    ,	30,	8,	663,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_38_63"              ,	38,	26,	663,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	664,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	664,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	664,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	664,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	665,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	666,	"RAZ",	1,	1,	0,	0},
+	{"MINLEN"                      ,	0,	16,	667,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	667,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	667,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	668,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	668,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	668,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	668,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	668,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	669,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	669,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	669,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	669,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	669,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	669,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_63"              ,	21,	43,	669,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	670,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	670,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	671,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	671,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	672,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	673,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	673,	"RAZ",	1,	1,	0,	0},
+	{"CRC_EN"                      ,	12,	1,	673,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	673,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	673,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT"                     ,	20,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	673,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	673,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	673,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	673,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	673,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	673,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	674,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	675,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	676,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	677,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	677,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	677,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	677,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	678,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	679,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	680,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	680,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	681,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	681,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	682,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	682,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	683,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	683,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	684,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	684,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	685,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	685,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	686,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	686,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	687,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	687,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	688,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	688,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	689,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	689,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	690,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	690,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	691,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	691,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	692,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	692,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	693,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	693,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	694,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	695,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	696,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	696,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	696,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	697,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	697,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	697,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	698,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	698,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	699,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	699,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	700,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	700,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	700,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	700,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	701,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	701,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	701,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	701,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	701,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	702,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	702,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	702,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	702,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	703,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	703,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	703,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	703,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	703,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	703,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	703,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	703,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	704,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	704,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	704,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	704,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	705,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	705,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	705,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	705,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	705,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	706,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	707,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	707,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	707,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	707,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	707,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	708,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	709,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	709,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	709,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	709,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	709,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	709,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	709,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	709,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	709,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	709,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	709,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	709,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	709,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	710,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	710,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	710,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	710,	"RAZ",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	0,	8,	711,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	711,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	711,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	711,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	711,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	711,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	711,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	711,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	711,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	711,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	711,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	711,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	711,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	712,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	712,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	712,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	712,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	712,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	712,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	713,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	713,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	713,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	713,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	713,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	713,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	713,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	713,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	713,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	714,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	714,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	714,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	714,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	715,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	715,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	715,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	715,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	715,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	715,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	715,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	716,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	716,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	716,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	716,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	716,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	717,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	717,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_PKT"                    ,	8,	24,	717,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	717,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	717,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	718,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	718,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_LIM"                    ,	8,	24,	718,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	718,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	719,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	719,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	719,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	719,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	719,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	719,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	719,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	719,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	719,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	720,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	720,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	720,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	720,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	720,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	721,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	721,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	721,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	721,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	721,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	721,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	721,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	721,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	721,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	721,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	722,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	722,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	64,	723,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	724,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE5"                     ,	20,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE6"                     ,	24,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE7"                     ,	28,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE8"                     ,	32,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_40_63"              ,	40,	24,	727,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	10,	728,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	728,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	729,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	729,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	730,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	730,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	731,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	731,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	731,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	732,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	732,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	733,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	734,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	735,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	735,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR0"                        ,	0,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR1"                        ,	1,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND0"                       ,	2,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND1"                       ,	3,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	4,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	5,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	6,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	7,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	8,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	9,	1,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	736,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	12,	736,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	736,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	737,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	737,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	738,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	738,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	738,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	738,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	738,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	738,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	738,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	738,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	738,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	739,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	739,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	740,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	740,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	741,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	741,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	742,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	742,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	743,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	743,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	744,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	744,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	745,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	745,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	746,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	746,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	747,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	748,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	748,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	748,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	749,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	749,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	749,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	749,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	749,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	11,	750,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	750,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	11,	750,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	750,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	12,	750,	"RO",	0,	1,	2027ull,	0},
+	{"BUF_CNT"                     ,	36,	12,	750,	"RO",	0,	1,	0ull,	0},
+	{"DES_CNT"                     ,	48,	12,	750,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	750,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	751,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	751,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	752,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	752,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	753,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	753,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	754,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	754,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	754,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	12,	755,	"RO",	0,	1,	0ull,	0},
+	{"DS_CNT"                      ,	12,	12,	755,	"RO",	0,	1,	0ull,	0},
+	{"TC_CNT"                      ,	24,	4,	755,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	755,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	756,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	756,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	756,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	756,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	756,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	11,	757,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	757,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	11,	757,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	757,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	757,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	757,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	758,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	758,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	759,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	760,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	761,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	762,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	762,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	762,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	762,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	762,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	33,	763,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	763,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	763,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	763,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	763,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	764,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	764,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	764,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	764,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	765,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	765,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	765,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	765,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	765,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	765,	"RAZ",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	765,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	765,	"RAZ",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	765,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	765,	"RAZ",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	766,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	767,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	767,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	767,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	768,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	768,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	768,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	768,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	768,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	768,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	768,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	15,	769,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	769,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OWORDP"                      ,	0,	64,	770,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	771,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	772,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	773,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	773,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	773,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	773,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FPACREDS"                    ,	12,	2,	773,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	773,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	773,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	773,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	773,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	773,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	773,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	773,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	773,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	773,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	773,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	773,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	773,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	773,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	40,	774,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	774,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	774,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	775,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	775,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	40,	776,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	776,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	776,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	777,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	777,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	777,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	777,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	777,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	777,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	777,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	0,	1,	778,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	778,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	0,	1,	779,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	779,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COEFFS"                      ,	0,	8,	780,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	780,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	781,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	781,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	0,	1,	782,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	782,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	782,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	783,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	783,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	784,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	784,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	784,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	784,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	784,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	784,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	784,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	784,	"RAZ",	1,	1,	0,	0},
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+	{"TRIG_CTL"                    ,	2,	2,	800,	"R/W",	0,	0,	0ull,	0ull},
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+	{"ILLEGAL"                     ,	13,	19,	813,	"R/W",	0,	0,	0ull,	524287ull},
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+	{"PKO"                         ,	17,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	819,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INEPINT"                     ,	0,	16,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	820,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	821,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	822,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	822,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	822,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	822,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	822,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	823,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	823,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	823,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	823,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	823,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	823,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	823,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	824,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	824,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	824,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	824,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	824,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	824,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	824,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	824,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	825,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	825,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	825,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	825,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	825,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	825,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	825,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	825,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	826,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	826,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	827,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	827,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	828,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	828,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	828,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	828,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	828,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	828,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	828,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	828,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	828,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	829,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	829,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	830,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	831,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	832,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	833,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	833,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	834,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	835,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	836,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	838,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	838,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	838,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	838,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	838,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	838,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	839,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	840,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	840,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	840,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	840,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	840,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	840,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	840,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	840,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	840,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	840,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	840,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	840,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	840,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	840,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	841,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	841,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	841,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	841,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	841,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	841,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	841,	"RO",	0,	0,	1ull,	1ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	841,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	841,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	841,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	842,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	842,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	842,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	842,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	842,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	842,	"RO",	0,	0,	1ull,	1ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	842,	"RO",	0,	0,	1ull,	1ull},
+	{"AVALIDFLTR"                  ,	22,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"BVALIDFLTR"                  ,	23,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"SESSENDFLTR"                 ,	24,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDEDTRFIFO"                 ,	25,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVMODINEND"              ,	26,	4,	842,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_30_31"              ,	30,	2,	842,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	843,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	843,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	843,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	843,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	843,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	844,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	844,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	844,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	844,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	845,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	845,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	846,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	846,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	846,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	846,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	847,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	847,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	847,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	847,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	847,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	847,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	847,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	848,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	848,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	848,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	848,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	848,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	848,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	848,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	848,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	848,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	848,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	849,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	849,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	849,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	849,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	850,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	850,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	851,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	852,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	852,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	853,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	854,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	854,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	854,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	854,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	854,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	855,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	856,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	856,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	856,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	856,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	856,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	856,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	857,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	857,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	858,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	859,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	860,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	860,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	860,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	861,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	862,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	863,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	865,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	865,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	866,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	867,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	867,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	867,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	867,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	867,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	867,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	867,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	867,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	867,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	867,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	867,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	868,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	868,	"R/W",	0,	0,	256ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	869,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	869,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	869,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	870,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	871,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	871,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"N2UF_BIS"                    ,	3,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"E2HC_BIS"                    ,	4,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NF_BIS"                    ,	5,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NC_BIS"                    ,	6,	1,	872,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	872,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	873,	"R/W",	0,	0,	4ull,	0ull},
+	{"HRST"                        ,	3,	1,	873,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	873,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	873,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	873,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	873,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	873,	"R/W",	0,	0,	2ull,	0ull},
+	{"P_COM_ON"                    ,	13,	1,	873,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_RTYPE"                     ,	14,	2,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	873,	"RAZ",	1,	1,	0,	0},
+	{"HCLK_RST"                    ,	17,	1,	873,	"R/W",	0,	0,	1ull,	1ull},
+	{"DIVIDE2"                     ,	18,	2,	873,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_63"              ,	20,	44,	873,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	874,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	874,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	874,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	875,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	875,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	876,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	876,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	877,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	877,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	878,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	878,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	879,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	879,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	880,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	880,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	881,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	881,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	882,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	882,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	883,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	883,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	884,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	884,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	885,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	885,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	886,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	886,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	887,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	887,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	888,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	888,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	889,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	889,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	890,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	890,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	891,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	892,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	892,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	893,	"RAZ",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	893,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	893,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	893,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_22"              ,	19,	4,	894,	"RAZ",	0,	0,	0ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	894,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	894,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	894,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXPREEMPHASISTUNE"           ,	30,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	894,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	894,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	38,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	39,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	40,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRVVBUS"                     ,	41,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	42,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGDISABLE"                  ,	43,	1,	894,	"R/W",	0,	0,	1ull,	1ull},
+	{"OTGTUNE"                     ,	44,	3,	894,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMPDISTUNE"                 ,	47,	3,	894,	"R/W",	0,	0,	2ull,	2ull},
+	{"SQRXTUNE"                    ,	50,	3,	894,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXHSXVTUNE"                  ,	53,	2,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFSLSTUNE"                  ,	55,	4,	894,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXVREFTUNE"                  ,	59,	4,	894,	"R/W",	0,	0,	7ull,	7ull},
+	{"TXRISETUNE"                  ,	63,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP_CTL"                     ,	0,	4,	895,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	895,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	895,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	896,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	897,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	897,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	898,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	898,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	898,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	898,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	898,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	899,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	899,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	900,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	901,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	11,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	11},
+	{"cvmx_agl_gmx_drv_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	6,	13},
+	{"cvmx_agl_gmx_inf_mode"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	3,	19},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	7,	22},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	1,	29},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	30},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	7,	1,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	32},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	1,	33},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	34},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	11,	2,	35},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	4,	37},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	2,	41},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	10,	43},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	15,	11,	53},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	2,	64},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	17,	2,	66},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	68},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	19,	19,	70},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	19,	89},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	21,	2,	108},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	110},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	23,	2,	112},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	2,	114},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	25,	2,	116},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	26,	2,	118},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	27,	2,	120},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	122},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	29,	2,	124},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	126},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	31,	2,	128},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	32,	2,	130},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	33,	4,	132},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	2,	136},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	35,	2,	138},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	2,	140},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	37,	4,	142},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	4,	146},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	39,	2,	150},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	40,	3,	152},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	41,	5,	155},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	3,	160},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	43,	2,	163},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	165},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	45,	2,	167},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	169},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	47,	2,	171},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	173},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	49,	2,	175},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	177},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	51,	2,	179},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	181},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	53,	2,	183},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	185},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	55,	2,	187},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	189},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	57,	2,	191},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	193},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	59,	2,	195},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	197},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	61,	2,	199},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	2,	201},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	63,	3,	203},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	10,	206},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	10,	216},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	226},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	67,	2,	228},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	6,	230},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	69,	2,	236},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	70,	2,	238},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	71,	2,	240},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	72,	2,	242},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	73,	2,	244},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	74,	2,	246},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	75,	21,	248},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	100,	21,	269},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	125,	21,	290},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	150,	2,	311},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	175,	2,	313},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	200,	2,	315},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	225,	21,	317},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	237,	21,	338},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	249,	21,	359},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	261,	2,	380},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	273,	2,	382},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	285,	2,	384},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	297,	21,	386},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	322,	21,	407},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	334,	2,	428},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	335,	2,	430},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	347,	2,	432},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	359,	2,	434},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	360,	2,	436},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	361,	2,	438},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	362,	1,	440},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	374,	3,	441},
+	{"cvmx_ciu_qlm_dcok"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	375,	2,	444},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	376,	5,	446},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	377,	8,	451},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	378,	2,	459},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	379,	2,	461},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	380,	2,	463},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	381,	2,	465},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	382,	3,	467},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	386,	7,	470},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	398,	6,	477},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	399,	7,	483},
+	{"cvmx_fpa_fpf#_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	400,	3,	490},
+	{"cvmx_fpa_fpf#_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	407,	2,	493},
+	{"cvmx_fpa_fpf0_marks"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	414,	3,	495},
+	{"cvmx_fpa_fpf0_size"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	415,	2,	498},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	29,	500},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	417,	29,	529},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	418,	2,	558},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	426,	2,	560},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	434,	3,	562},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	435,	3,	565},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	436,	2,	568},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	437,	2,	570},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	438,	7,	572},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	440,	2,	579},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	442,	2,	581},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	444,	5,	583},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	446,	7,	588},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	448,	2,	595},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	450,	8,	597},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	452,	10,	605},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	460,	1,	615},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	468,	1,	616},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	476,	1,	617},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	484,	1,	618},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	492,	1,	619},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	500,	1,	620},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	508,	2,	621},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	516,	4,	623},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	524,	2,	627},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	532,	9,	629},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	540,	11,	638},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	548,	2,	649},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	556,	27,	651},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	564,	27,	678},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	572,	2,	705},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	580,	2,	707},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	588,	2,	709},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	596,	2,	711},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	604,	2,	713},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	612,	2,	715},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	620,	2,	717},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	628,	2,	719},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	636,	2,	721},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	644,	2,	723},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	652,	2,	725},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	660,	2,	727},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	668,	4,	729},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	676,	2,	733},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	684,	2,	735},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	692,	2,	737},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	700,	4,	739},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	702,	4,	743},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	704,	2,	747},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	706,	5,	749},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	708,	2,	754},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	710,	2,	756},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	718,	3,	758},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	720,	5,	761},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	728,	2,	766},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	736,	2,	768},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	738,	2,	770},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	740,	3,	772},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	748,	2,	775},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	756,	2,	777},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	764,	2,	779},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	772,	3,	781},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	780,	2,	784},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	788,	2,	786},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	796,	2,	788},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	2,	790},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	2,	792},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	820,	2,	794},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	828,	2,	796},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	836,	2,	798},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	844,	2,	800},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	852,	2,	802},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	860,	2,	804},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	868,	2,	806},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	876,	2,	808},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	884,	2,	810},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	892,	2,	812},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	900,	2,	814},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	908,	2,	816},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	910,	2,	818},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	912,	2,	820},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	914,	2,	822},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	916,	2,	824},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	918,	3,	826},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	920,	8,	829},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	922,	8,	837},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	924,	2,	845},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	926,	2,	847},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	928,	6,	849},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	930,	2,	855},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	932,	2,	857},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	934,	2,	859},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	936,	9,	861},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	938,	3,	870},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	940,	9,	873},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	956,	2,	882},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	960,	2,	884},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	961,	2,	886},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	962,	2,	888},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	963,	2,	890},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	964,	19,	892},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	965,	6,	911},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	966,	3,	917},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	967,	3,	920},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	968,	3,	923},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	969,	5,	926},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	970,	5,	931},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	971,	1,	936},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	972,	1,	937},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	973,	7,	938},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	974,	7,	945},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	975,	3,	952},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	976,	3,	955},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	977,	3,	958},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	978,	5,	961},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	979,	5,	966},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	980,	1,	971},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	981,	1,	972},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	982,	3,	973},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	983,	3,	976},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	984,	3,	979},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	985,	2,	982},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	986,	2,	984},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	987,	2,	986},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	988,	2,	988},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	989,	19,	990},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	990,	2,	1009},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	991,	1,	1011},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	992,	15,	1012},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	993,	13,	1027},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	994,	13,	1040},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	995,	2,	1053},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	996,	2,	1055},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	997,	2,	1057},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	998,	3,	1059},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1010,	3,	1062},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1014,	2,	1065},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	1018,	2,	1067},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1030,	2,	1069},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1158,	1,	1071},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	1161,	1,	1072},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1164,	6,	1073},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	1165,	5,	1079},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1166,	6,	1084},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1167,	7,	1090},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1168,	2,	1097},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	1176,	2,	1099},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1177,	3,	1101},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1178,	2,	1104},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	1179,	5,	1106},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	1187,	3,	1111},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1188,	4,	1114},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1189,	3,	1118},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1190,	2,	1121},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	1191,	2,	1123},
+	{"cvmx_key_bist_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1192,	4,	1125},
+	{"cvmx_key_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1193,	3,	1129},
+	{"cvmx_key_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1194,	5,	1132},
+	{"cvmx_key_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1195,	5,	1137},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1196,	7,	1142},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1197,	11,	1149},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1198,	8,	1160},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1199,	15,	1168},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1200,	8,	1183},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1201,	5,	1191},
+	{"cvmx_l2c_grpwrr0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1202,	2,	1196},
+	{"cvmx_l2c_grpwrr1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1203,	2,	1198},
+	{"cvmx_l2c_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1204,	10,	1200},
+	{"cvmx_l2c_int_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1205,	10,	1210},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1206,	4,	1220},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1207,	2,	1224},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1208,	14,	1226},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1209,	19,	1240},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1210,	3,	1259},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1211,	3,	1262},
+	{"cvmx_l2c_oob"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1212,	3,	1265},
+	{"cvmx_l2c_oob1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1213,	6,	1268},
+	{"cvmx_l2c_oob2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1214,	6,	1274},
+	{"cvmx_l2c_oob3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1215,	6,	1280},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1216,	2,	1286},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1220,	17,	1288},
+	{"cvmx_l2c_ppgrp"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1221,	13,	1305},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1222,	5,	1318},
+	{"cvmx_l2c_spar1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1223,	5,	1323},
+	{"cvmx_l2c_spar2"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1224,	5,	1328},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1225,	2,	1333},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1226,	3,	1335},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1227,	2,	1338},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1228,	2,	1340},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1229,	2,	1342},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1230,	7,	1344},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1231,	5,	1351},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1232,	3,	1356},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1233,	3,	1359},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1234,	2,	1362},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1235,	2,	1364},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1236,	2,	1366},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1237,	6,	1368},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1238,	14,	1374},
+	{"cvmx_led_blink"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1239,	2,	1388},
+	{"cvmx_led_clk_phase"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1240,	2,	1390},
+	{"cvmx_led_cylon"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1241,	2,	1392},
+	{"cvmx_led_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1242,	2,	1394},
+	{"cvmx_led_en"                 ,	CVMX_CSR_DB_TYPE_RSL,	64,	1243,	2,	1396},
+	{"cvmx_led_polarity"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1244,	2,	1398},
+	{"cvmx_led_prt"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1245,	2,	1400},
+	{"cvmx_led_prt_fmt"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1246,	2,	1402},
+	{"cvmx_led_prt_status#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1247,	2,	1404},
+	{"cvmx_led_udd_cnt#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1255,	2,	1406},
+	{"cvmx_led_udd_dat#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1257,	2,	1408},
+	{"cvmx_led_udd_dat_clr#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1259,	2,	1410},
+	{"cvmx_led_udd_dat_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1261,	2,	1412},
+	{"cvmx_lmc#_bist_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1263,	2,	1414},
+	{"cvmx_lmc#_bist_result"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1265,	8,	1416},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1267,	7,	1424},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1269,	19,	1431},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1271,	8,	1450},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1273,	2,	1458},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1275,	2,	1460},
+	{"cvmx_lmc#_dclk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1277,	5,	1462},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1279,	18,	1467},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1281,	6,	1485},
+	{"cvmx_lmc#_dll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1283,	5,	1491},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1285,	5,	1496},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1287,	5,	1501},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	1289,	6,	1506},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1291,	2,	1512},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1293,	2,	1514},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1295,	14,	1516},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1297,	9,	1530},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1299,	2,	1539},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1301,	2,	1541},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1303,	2,	1543},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1305,	13,	1545},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1307,	6,	1558},
+	{"cvmx_lmc#_read_level_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1309,	7,	1564},
+	{"cvmx_lmc#_read_level_dbg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1311,	4,	1571},
+	{"cvmx_lmc#_read_level_rank#"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1313,	11,	1575},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1321,	6,	1586},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1323,	9,	1592},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	5,	1601},
+	{"cvmx_lmc#_wodt_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1327,	5,	1606},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1329,	5,	1611},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1330,	3,	1616},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1331,	10,	1619},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1334,	3,	1629},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1337,	3,	1632},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1340,	15,	1635},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1343,	3,	1650},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1344,	3,	1653},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1345,	3,	1656},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1346,	5,	1659},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1348,	1,	1664},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1349,	8,	1665},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1350,	13,	1673},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1358,	13,	1686},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1366,	6,	1699},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1367,	1,	1705},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1371,	2,	1706},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1372,	2,	1708},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1373,	13,	1710},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	8,	1723},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1375,	4,	1731},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1376,	1,	1735},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1377,	3,	1736},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1378,	2,	1739},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1379,	6,	1741},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1380,	7,	1747},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1381,	4,	1754},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1382,	2,	1758},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1383,	2,	1760},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1384,	13,	1762},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1386,	12,	1775},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1388,	3,	1787},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1390,	3,	1790},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1392,	2,	1793},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1394,	2,	1795},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1396,	2,	1797},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1398,	7,	1799},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1400,	2,	1806},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1402,	7,	1808},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1404,	4,	1815},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1406,	8,	1819},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1408,	9,	1827},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1410,	7,	1836},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1412,	9,	1843},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1414,	2,	1852},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1416,	2,	1854},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1418,	4,	1856},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1420,	2,	1860},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1422,	2,	1862},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1424,	2,	1864},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1426,	4,	1866},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1428,	2,	1870},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1430,	2,	1872},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1432,	2,	1874},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1434,	2,	1876},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1436,	2,	1878},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1438,	2,	1880},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1440,	6,	1882},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1442,	5,	1888},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	1443,	8,	1893},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1444,	8,	1901},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1445,	2,	1909},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1446,	3,	1911},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1447,	5,	1914},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1448,	4,	1919},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	1449,	8,	1923},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1450,	2,	1931},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1451,	2,	1933},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1452,	5,	1935},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1453,	4,	1940},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1454,	4,	1944},
+	{"cvmx_npei_bar1_index#"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	1455,	5,	1948},
+	{"cvmx_npei_bist_status"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1487,	58,	1953},
+	{"cvmx_npei_bist_status2"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1488,	15,	2011},
+	{"cvmx_npei_ctl_port0"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1489,	17,	2026},
+	{"cvmx_npei_ctl_port1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1490,	17,	2043},
+	{"cvmx_npei_ctl_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1491,	10,	2060},
+	{"cvmx_npei_ctl_status2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1492,	11,	2070},
+	{"cvmx_npei_data_out_cnt"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1493,	5,	2081},
+	{"cvmx_npei_dbg_data"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1494,	8,	2086},
+	{"cvmx_npei_dbg_select"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1495,	2,	2094},
+	{"cvmx_npei_dma#_counts"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1496,	3,	2096},
+	{"cvmx_npei_dma#_dbell"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	1501,	2,	2099},
+	{"cvmx_npei_dma#_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1506,	4,	2101},
+	{"cvmx_npei_dma#_naddr"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1511,	2,	2105},
+	{"cvmx_npei_dma0_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1516,	2,	2107},
+	{"cvmx_npei_dma1_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1517,	2,	2109},
+	{"cvmx_npei_dma_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1518,	2,	2111},
+	{"cvmx_npei_dma_control"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1519,	17,	2113},
+	{"cvmx_npei_dma_pcie_req_num"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1520,	15,	2130},
+	{"cvmx_npei_int_a_enb"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1521,	11,	2145},
+	{"cvmx_npei_int_a_enb2"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1522,	11,	2156},
+	{"cvmx_npei_int_a_sum"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1523,	11,	2167},
+	{"cvmx_npei_int_enb"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1524,	64,	2178},
+	{"cvmx_npei_int_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1525,	63,	2242},
+	{"cvmx_npei_int_info"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1526,	3,	2305},
+	{"cvmx_npei_int_sum"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1527,	64,	2308},
+	{"cvmx_npei_int_sum2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1528,	61,	2372},
+	{"cvmx_npei_last_win_rdata0"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1529,	1,	2433},
+	{"cvmx_npei_last_win_rdata1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1530,	1,	2434},
+	{"cvmx_npei_mem_access_ctl"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1531,	3,	2435},
+	{"cvmx_npei_mem_access_subid#" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1532,	11,	2438},
+	{"cvmx_npei_msi_enb0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1548,	1,	2449},
+	{"cvmx_npei_msi_enb1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1549,	1,	2450},
+	{"cvmx_npei_msi_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1550,	1,	2451},
+	{"cvmx_npei_msi_enb3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1551,	1,	2452},
+	{"cvmx_npei_msi_rcv0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1552,	1,	2453},
+	{"cvmx_npei_msi_rcv1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1553,	1,	2454},
+	{"cvmx_npei_msi_rcv2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1554,	1,	2455},
+	{"cvmx_npei_msi_rcv3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1555,	1,	2456},
+	{"cvmx_npei_msi_rd_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1556,	3,	2457},
+	{"cvmx_npei_msi_w1c_enb0"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1557,	1,	2460},
+	{"cvmx_npei_msi_w1c_enb1"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1558,	1,	2461},
+	{"cvmx_npei_msi_w1c_enb2"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1559,	1,	2462},
+	{"cvmx_npei_msi_w1c_enb3"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1560,	1,	2463},
+	{"cvmx_npei_msi_w1s_enb0"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1561,	1,	2464},
+	{"cvmx_npei_msi_w1s_enb1"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1562,	1,	2465},
+	{"cvmx_npei_msi_w1s_enb2"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1563,	1,	2466},
+	{"cvmx_npei_msi_w1s_enb3"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1564,	1,	2467},
+	{"cvmx_npei_msi_wr_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1565,	3,	2468},
+	{"cvmx_npei_pcie_credit_cnt"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1566,	7,	2471},
+	{"cvmx_npei_pcie_msi_rcv"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1567,	2,	2478},
+	{"cvmx_npei_pcie_msi_rcv_b1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1568,	3,	2480},
+	{"cvmx_npei_pcie_msi_rcv_b2"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1569,	3,	2483},
+	{"cvmx_npei_pcie_msi_rcv_b3"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1570,	3,	2486},
+	{"cvmx_npei_pkt#_cnts"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1571,	3,	2489},
+	{"cvmx_npei_pkt#_in_bp"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1603,	2,	2492},
+	{"cvmx_npei_pkt#_instr_baddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1635,	2,	2494},
+	{"cvmx_npei_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1667,	2,	2496},
+	{"cvmx_npei_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1699,	5,	2498},
+	{"cvmx_npei_pkt#_instr_header" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1731,	13,	2503},
+	{"cvmx_npei_pkt#_slist_baddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1763,	2,	2516},
+	{"cvmx_npei_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1795,	2,	2518},
+	{"cvmx_npei_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1827,	2,	2520},
+	{"cvmx_npei_pkt_cnt_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1859,	2,	2522},
+	{"cvmx_npei_pkt_cnt_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1860,	2,	2524},
+	{"cvmx_npei_pkt_data_out_es"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1861,	1,	2526},
+	{"cvmx_npei_pkt_data_out_ns"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1862,	2,	2527},
+	{"cvmx_npei_pkt_data_out_ror"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1863,	2,	2529},
+	{"cvmx_npei_pkt_dpaddr"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1864,	2,	2531},
+	{"cvmx_npei_pkt_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1865,	2,	2533},
+	{"cvmx_npei_pkt_in_done#_cnts" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1866,	2,	2535},
+	{"cvmx_npei_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1898,	2,	2537},
+	{"cvmx_npei_pkt_in_pcie_port"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1899,	1,	2539},
+	{"cvmx_npei_pkt_input_control" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1900,	10,	2540},
+	{"cvmx_npei_pkt_instr_enb"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1901,	2,	2550},
+	{"cvmx_npei_pkt_instr_rd_size" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1902,	1,	2552},
+	{"cvmx_npei_pkt_instr_size"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1903,	2,	2553},
+	{"cvmx_npei_pkt_int_levels"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1904,	3,	2555},
+	{"cvmx_npei_pkt_iptr"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1905,	2,	2558},
+	{"cvmx_npei_pkt_out_bmode"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1906,	2,	2560},
+	{"cvmx_npei_pkt_out_enb"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1907,	2,	2562},
+	{"cvmx_npei_pkt_output_wmark"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1908,	2,	2564},
+	{"cvmx_npei_pkt_pcie_port"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1909,	1,	2566},
+	{"cvmx_npei_pkt_port_in_rst"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1910,	2,	2567},
+	{"cvmx_npei_pkt_slist_es"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1911,	1,	2569},
+	{"cvmx_npei_pkt_slist_id_size" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1912,	3,	2570},
+	{"cvmx_npei_pkt_slist_ns"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1913,	2,	2573},
+	{"cvmx_npei_pkt_slist_ror"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1914,	2,	2575},
+	{"cvmx_npei_pkt_time_int"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1915,	2,	2577},
+	{"cvmx_npei_pkt_time_int_enb"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1916,	2,	2579},
+	{"cvmx_npei_rsl_int_blocks"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1917,	29,	2581},
+	{"cvmx_npei_scratch_1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1918,	1,	2610},
+	{"cvmx_npei_state1"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1919,	4,	2611},
+	{"cvmx_npei_state2"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1920,	7,	2615},
+	{"cvmx_npei_state3"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1921,	5,	2622},
+	{"cvmx_npei_win_rd_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1922,	4,	2627},
+	{"cvmx_npei_win_rd_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1923,	1,	2631},
+	{"cvmx_npei_win_wr_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1924,	4,	2632},
+	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1925,	1,	2636},
+	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1926,	2,	2637},
+	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1927,	2,	2639},
+	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1928,	2,	2641},
+	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1929,	24,	2643},
+	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1930,	4,	2667},
+	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1931,	5,	2671},
+	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1932,	5,	2676},
+	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1933,	2,	2681},
+	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1934,	1,	2683},
+	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1935,	1,	2684},
+	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1936,	5,	2685},
+	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1937,	2,	2690},
+	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1938,	1,	2692},
+	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1939,	1,	2693},
+	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1940,	4,	2694},
+	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1941,	2,	2698},
+	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1942,	2,	2700},
+	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1943,	1,	2702},
+	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1944,	1,	2703},
+	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1945,	2,	2704},
+	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1946,	3,	2706},
+	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1947,	2,	2709},
+	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1948,	2,	2711},
+	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1949,	4,	2713},
+	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1950,	10,	2717},
+	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1951,	12,	2727},
+	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1952,	7,	2739},
+	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1953,	2,	2746},
+	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1954,	1,	2748},
+	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1955,	2,	2749},
+	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1956,	7,	2751},
+	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1957,	11,	2758},
+	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1958,	19,	2769},
+	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1959,	11,	2788},
+	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1960,	17,	2799},
+	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1961,	12,	2816},
+	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1962,	22,	2828},
+	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1963,	3,	2850},
+	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1964,	3,	2853},
+	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1965,	1,	2856},
+	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1966,	1,	2857},
+	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1967,	1,	2858},
+	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1968,	1,	2859},
+	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1969,	3,	2860},
+	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1970,	14,	2863},
+	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1971,	14,	2877},
+	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1972,	14,	2891},
+	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1973,	9,	2905},
+	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1974,	9,	2914},
+	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1975,	6,	2923},
+	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1976,	1,	2929},
+	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1977,	1,	2930},
+	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1978,	1,	2931},
+	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1979,	1,	2932},
+	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1980,	2,	2933},
+	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1981,	1,	2935},
+	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1982,	6,	2936},
+	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1983,	6,	2942},
+	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1984,	13,	2948},
+	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1985,	5,	2961},
+	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1986,	8,	2966},
+	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1987,	19,	2974},
+	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1988,	3,	2993},
+	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1989,	1,	2996},
+	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1990,	1,	2997},
+	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1991,	3,	2998},
+	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1992,	3,	3001},
+	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1993,	3,	3004},
+	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1994,	4,	3007},
+	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1995,	4,	3011},
+	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1996,	4,	3015},
+	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1997,	7,	3019},
+	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1998,	5,	3026},
+	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1999,	5,	3031},
+	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2000,	4,	3036},
+	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2001,	4,	3040},
+	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2002,	4,	3044},
+	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2003,	1,	3048},
+	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	2004,	1,	3049},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2005,	2,	3050},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2007,	24,	3052},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2009,	4,	3076},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2011,	5,	3080},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2013,	1,	3085},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2015,	1,	3086},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2017,	4,	3087},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2019,	17,	3091},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2021,	4,	3108},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2023,	6,	3112},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2025,	1,	3118},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2027,	1,	3119},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2029,	2,	3120},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2031,	2,	3122},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2033,	1,	3124},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2035,	15,	3125},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2037,	10,	3140},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2039,	12,	3150},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2041,	7,	3162},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2043,	2,	3169},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2045,	1,	3171},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2047,	2,	3172},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2049,	7,	3174},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2051,	11,	3181},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2053,	19,	3192},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2055,	11,	3211},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2057,	20,	3222},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2059,	12,	3242},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2061,	22,	3254},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2063,	8,	3276},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2065,	4,	3284},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2067,	3,	3288},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2069,	3,	3291},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2071,	1,	3294},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2073,	1,	3295},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2075,	1,	3296},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2077,	1,	3297},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2079,	3,	3298},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2081,	14,	3301},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2083,	14,	3315},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2085,	14,	3329},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2087,	9,	3343},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2089,	9,	3352},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2091,	6,	3361},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2093,	1,	3367},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2095,	1,	3368},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2097,	1,	3369},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2099,	1,	3370},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2101,	4,	3371},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2103,	9,	3375},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2105,	2,	3384},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2107,	2,	3386},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2109,	1,	3388},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2111,	6,	3389},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2113,	6,	3395},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2115,	13,	3401},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2117,	5,	3414},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2119,	8,	3419},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2121,	19,	3427},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2123,	3,	3446},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2125,	1,	3449},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2127,	1,	3450},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2129,	3,	3451},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2131,	3,	3454},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2133,	3,	3457},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2135,	4,	3460},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2137,	4,	3464},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2139,	4,	3468},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2141,	7,	3472},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2143,	5,	3479},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2145,	5,	3484},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2147,	4,	3489},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2149,	4,	3493},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2151,	4,	3497},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2153,	1,	3501},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	2155,	1,	3502},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2157,	9,	3503},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2165,	6,	3512},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2173,	9,	3518},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2181,	6,	3527},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2189,	13,	3533},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2197,	13,	3546},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	2205,	2,	3559},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2213,	4,	3561},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2221,	8,	3565},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2229,	13,	3573},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2237,	17,	3586},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2245,	7,	3603},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2253,	3,	3610},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2261,	8,	3613},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2269,	7,	3621},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2277,	4,	3628},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	2285,	5,	3632},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	2293,	8,	3637},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2295,	2,	3645},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	2297,	5,	3647},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2299,	10,	3652},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2301,	2,	3662},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2303,	7,	3664},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2305,	7,	3671},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2307,	6,	3678},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2309,	5,	3684},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	2311,	5,	3689},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2313,	3,	3694},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2315,	6,	3697},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2317,	9,	3703},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	2319,	5,	3712},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	2321,	10,	3717},
+	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2323,	14,	3727},
+	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2325,	15,	3741},
+	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2327,	2,	3756},
+	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2329,	2,	3758},
+	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2331,	2,	3760},
+	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2333,	16,	3762},
+	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2335,	3,	3778},
+	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2337,	32,	3781},
+	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2339,	32,	3813},
+	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2341,	5,	3845},
+	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2343,	2,	3850},
+	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2345,	2,	3852},
+	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2347,	2,	3854},
+	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2349,	2,	3856},
+	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	2,	3858},
+	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	8,	3860},
+	{"cvmx_pip_bck_prs"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	5,	3868},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2368,	2,	3873},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2369,	4,	3875},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2373,	16,	3879},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2374,	16,	3895},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	3,	3911},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	8,	3914},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	22,	3922},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	6,	3944},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	14,	3950},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	14,	3964},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2382,	2,	3978},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2383,	28,	3980},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2399,	25,	4008},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2415,	2,	4033},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2479,	4,	4035},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2487,	9,	4039},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2495,	2,	4048},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2496,	2,	4050},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2497,	2,	4052},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2513,	2,	4054},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2529,	2,	4056},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2545,	2,	4058},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2561,	2,	4060},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2577,	2,	4062},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2593,	2,	4064},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2609,	2,	4066},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2625,	2,	4068},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2641,	2,	4070},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2657,	2,	4072},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2658,	2,	4074},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2674,	2,	4076},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2690,	2,	4078},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2706,	2,	4080},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2770,	2,	4082},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2771,	3,	4084},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2772,	3,	4087},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2773,	2,	4090},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2774,	2,	4092},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2775,	4,	4094},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2776,	5,	4098},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2777,	4,	4103},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2778,	8,	4107},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2779,	4,	4115},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2780,	5,	4119},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2781,	1,	4124},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2782,	5,	4125},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2783,	1,	4130},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2784,	13,	4131},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2785,	4,	4144},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2786,	13,	4148},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2787,	6,	4161},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2788,	9,	4167},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2789,	4,	4176},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2790,	7,	4180},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2791,	5,	4187},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2792,	5,	4192},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2793,	4,	4197},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2794,	9,	4201},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2795,	5,	4210},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2796,	16,	4215},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2797,	4,	4231},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2798,	1,	4235},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2799,	1,	4236},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2800,	1,	4237},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2801,	1,	4238},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	2802,	11,	4239},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2803,	2,	4250},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2804,	4,	4252},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2805,	5,	4256},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2806,	3,	4261},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2807,	4,	4264},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2808,	2,	4268},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2809,	3,	4270},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2810,	3,	4273},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2811,	13,	4276},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2812,	2,	4289},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2813,	13,	4291},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2814,	3,	4304},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2815,	2,	4307},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2823,	2,	4309},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2824,	2,	4311},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2825,	2,	4313},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2826,	2,	4315},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2834,	2,	4317},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2835,	2,	4319},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2836,	2,	4321},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2837,	10,	4323},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2849,	5,	4333},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2857,	8,	4338},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2865,	2,	4346},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2866,	2,	4348},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2867,	2,	4350},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2875,	3,	4352},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2876,	4,	4355},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2892,	5,	4359},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2893,	7,	4364},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2909,	2,	4371},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2925,	1,	4373},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2926,	1,	4374},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2927,	1,	4375},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2928,	5,	4376},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2929,	5,	4381},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2930,	4,	4386},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2931,	10,	4390},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2932,	1,	4400},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2933,	3,	4401},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2934,	7,	4404},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2935,	2,	4411},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2936,	1,	4413},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2937,	1,	4414},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2938,	1,	4415},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2939,	18,	4416},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2940,	3,	4434},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2941,	2,	4437},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2942,	3,	4439},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2943,	7,	4442},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2944,	2,	4449},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2945,	2,	4451},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2946,	2,	4453},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2947,	3,	4455},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2948,	3,	4458},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2949,	7,	4461},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2950,	10,	4468},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2952,	6,	4478},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2954,	2,	4484},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2956,	4,	4486},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2958,	4,	4490},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2960,	6,	4494},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2961,	3,	4500},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2962,	5,	4503},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2963,	4,	4508},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2964,	6,	4512},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2965,	4,	4518},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2966,	2,	4522},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2967,	4,	4524},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2968,	2,	4528},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2969,	3,	4530},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2970,	4,	4533},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2971,	12,	4537},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2972,	3,	4549},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2973,	5,	4552},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2974,	2,	4557},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2975,	2,	4559},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2976,	18,	4561},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2977,	12,	4579},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2978,	6,	4591},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2979,	5,	4597},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2980,	1,	4602},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2981,	2,	4603},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2982,	2,	4605},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2983,	18,	4607},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2984,	12,	4625},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2985,	6,	4637},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2986,	2,	4643},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2987,	2,	4645},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2988,	18,	4647},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2989,	12,	4665},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2990,	6,	4677},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2991,	2,	4683},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2992,	2,	4685},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2993,	8,	4687},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2994,	11,	4695},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2995,	15,	4706},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3000,	8,	4721},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3005,	8,	4729},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	3006,	4,	4737},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3011,	15,	4741},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3016,	6,	4756},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3021,	6,	4762},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	3022,	4,	4768},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	3027,	2,	4772},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	3031,	6,	4774},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3032,	4,	4780},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3033,	1,	4784},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3034,	1,	4785},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3035,	1,	4786},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3036,	7,	4787},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3037,	1,	4794},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3038,	14,	4795},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3039,	10,	4809},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3040,	14,	4819},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3041,	32,	4833},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3042,	32,	4865},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	3043,	2,	4897},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3044,	4,	4899},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3045,	13,	4903},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3046,	10,	4916},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3047,	10,	4926},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3048,	2,	4936},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3049,	6,	4938},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3050,	5,	4944},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3051,	6,	4949},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3052,	5,	4955},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3053,	1,	4960},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3054,	13,	4961},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	3055,	2,	4974},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3056,	2,	4976},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3057,	11,	4978},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	3065,	3,	4989},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	3066,	12,	4992},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	3074,	12,	5004},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3082,	6,	5016},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3090,	4,	5022},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	3098,	2,	5026},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	3099,	2,	5028},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	3100,	15,	5030},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	3101,	2,	5045},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3102,	3,	5047},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	3103,	1,	5050},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	3111,	6,	5051},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	3112,	8,	5057},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3113,	15,	5065},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	3114,	6,	5080},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3115,	2,	5086},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3116,	2,	5088},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3117,	2,	5090},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3118,	2,	5092},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3119,	2,	5094},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3120,	2,	5096},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3121,	2,	5098},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	3122,	2,	5100},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3123,	2,	5102},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3124,	2,	5104},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3125,	2,	5106},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3126,	2,	5108},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3127,	2,	5110},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3128,	2,	5112},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3129,	2,	5114},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	3130,	2,	5116},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	3131,	7,	5118},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3132,	34,	5125},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3133,	34,	5159},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	3134,	35,	5193},
+	{"cvmx_zip_cmd_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	3135,	3,	5228},
+	{"cvmx_zip_cmd_buf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3136,	5,	5231},
+	{"cvmx_zip_cmd_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	3137,	3,	5236},
+	{"cvmx_zip_constants"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	3138,	6,	5239},
+	{"cvmx_zip_debug0"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	3139,	2,	5245},
+	{"cvmx_zip_error"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	3140,	2,	5247},
+	{"cvmx_zip_int_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3141,	2,	5249},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT8_EN0"                ,	   0x1070000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT9_EN0"                ,	   0x1070000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT10_EN0"               ,	   0x10700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT11_EN0"               ,	   0x10700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT12_EN0"               ,	   0x10700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT13_EN0"               ,	   0x10700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT14_EN0"               ,	   0x10700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT15_EN0"               ,	   0x10700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT16_EN0"               ,	   0x1070000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT17_EN0"               ,	   0x1070000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT18_EN0"               ,	   0x1070000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT19_EN0"               ,	   0x1070000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT20_EN0"               ,	   0x1070000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT21_EN0"               ,	   0x1070000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT22_EN0"               ,	   0x1070000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT23_EN0"               ,	   0x1070000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT8_EN0_W1C"            ,	   0x1070000002280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT9_EN0_W1C"            ,	   0x1070000002290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT10_EN0_W1C"           ,	   0x10700000022A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT11_EN0_W1C"           ,	   0x10700000022B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT12_EN0_W1C"           ,	   0x10700000022C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT13_EN0_W1C"           ,	   0x10700000022D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT14_EN0_W1C"           ,	   0x10700000022E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT15_EN0_W1C"           ,	   0x10700000022F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT16_EN0_W1C"           ,	   0x1070000002300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT17_EN0_W1C"           ,	   0x1070000002310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT18_EN0_W1C"           ,	   0x1070000002320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT19_EN0_W1C"           ,	   0x1070000002330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT20_EN0_W1C"           ,	   0x1070000002340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT21_EN0_W1C"           ,	   0x1070000002350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT22_EN0_W1C"           ,	   0x1070000002360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT23_EN0_W1C"           ,	   0x1070000002370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT8_EN0_W1S"            ,	   0x1070000006280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT9_EN0_W1S"            ,	   0x1070000006290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT10_EN0_W1S"           ,	   0x10700000062A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT11_EN0_W1S"           ,	   0x10700000062B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT12_EN0_W1S"           ,	   0x10700000062C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT13_EN0_W1S"           ,	   0x10700000062D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT14_EN0_W1S"           ,	   0x10700000062E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT15_EN0_W1S"           ,	   0x10700000062F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT16_EN0_W1S"           ,	   0x1070000006300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT17_EN0_W1S"           ,	   0x1070000006310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT18_EN0_W1S"           ,	   0x1070000006320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT19_EN0_W1S"           ,	   0x1070000006330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT20_EN0_W1S"           ,	   0x1070000006340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT21_EN0_W1S"           ,	   0x1070000006350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT22_EN0_W1S"           ,	   0x1070000006360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT23_EN0_W1S"           ,	   0x1070000006370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT8_EN1"                ,	   0x1070000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT9_EN1"                ,	   0x1070000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT10_EN1"               ,	   0x10700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT11_EN1"               ,	   0x10700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT12_EN1"               ,	   0x10700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT13_EN1"               ,	   0x10700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT14_EN1"               ,	   0x10700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT15_EN1"               ,	   0x10700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT16_EN1"               ,	   0x1070000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT17_EN1"               ,	   0x1070000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT18_EN1"               ,	   0x1070000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT19_EN1"               ,	   0x1070000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT20_EN1"               ,	   0x1070000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT21_EN1"               ,	   0x1070000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT22_EN1"               ,	   0x1070000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT23_EN1"               ,	   0x1070000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT8_EN1_W1C"            ,	   0x1070000002288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT9_EN1_W1C"            ,	   0x1070000002298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT10_EN1_W1C"           ,	   0x10700000022A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT11_EN1_W1C"           ,	   0x10700000022B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT12_EN1_W1C"           ,	   0x10700000022C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT13_EN1_W1C"           ,	   0x10700000022D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT14_EN1_W1C"           ,	   0x10700000022E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT15_EN1_W1C"           ,	   0x10700000022F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT16_EN1_W1C"           ,	   0x1070000002308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT17_EN1_W1C"           ,	   0x1070000002318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT18_EN1_W1C"           ,	   0x1070000002328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT19_EN1_W1C"           ,	   0x1070000002338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT20_EN1_W1C"           ,	   0x1070000002348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT21_EN1_W1C"           ,	   0x1070000002358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT22_EN1_W1C"           ,	   0x1070000002368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT23_EN1_W1C"           ,	   0x1070000002378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT8_EN1_W1S"            ,	   0x1070000006288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT9_EN1_W1S"            ,	   0x1070000006298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT10_EN1_W1S"           ,	   0x10700000062A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT11_EN1_W1S"           ,	   0x10700000062B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT12_EN1_W1S"           ,	   0x10700000062C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT13_EN1_W1S"           ,	   0x10700000062D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT14_EN1_W1S"           ,	   0x10700000062E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT15_EN1_W1S"           ,	   0x10700000062F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT16_EN1_W1S"           ,	   0x1070000006308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT17_EN1_W1S"           ,	   0x1070000006318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT18_EN1_W1S"           ,	   0x1070000006328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT19_EN1_W1S"           ,	   0x1070000006338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT20_EN1_W1S"           ,	   0x1070000006348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT21_EN1_W1S"           ,	   0x1070000006358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT22_EN1_W1S"           ,	   0x1070000006368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT23_EN1_W1S"           ,	   0x1070000006378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT4_EN4_0"              ,	   0x1070000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT5_EN4_0"              ,	   0x1070000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT6_EN4_0"              ,	   0x1070000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT7_EN4_0"              ,	   0x1070000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT8_EN4_0"              ,	   0x1070000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT9_EN4_0"              ,	   0x1070000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT10_EN4_0"             ,	   0x1070000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT11_EN4_0"             ,	   0x1070000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT4_EN4_0_W1C"          ,	   0x1070000002CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT5_EN4_0_W1C"          ,	   0x1070000002CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT6_EN4_0_W1C"          ,	   0x1070000002CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT7_EN4_0_W1C"          ,	   0x1070000002CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT8_EN4_0_W1C"          ,	   0x1070000002D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT9_EN4_0_W1C"          ,	   0x1070000002D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT10_EN4_0_W1C"         ,	   0x1070000002D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT11_EN4_0_W1C"         ,	   0x1070000002D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT4_EN4_0_W1S"          ,	   0x1070000006CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT5_EN4_0_W1S"          ,	   0x1070000006CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT6_EN4_0_W1S"          ,	   0x1070000006CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT7_EN4_0_W1S"          ,	   0x1070000006CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT8_EN4_0_W1S"          ,	   0x1070000006D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT9_EN4_0_W1S"          ,	   0x1070000006D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT10_EN4_0_W1S"         ,	   0x1070000006D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT11_EN4_0_W1S"         ,	   0x1070000006D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT4_EN4_1"              ,	   0x1070000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT5_EN4_1"              ,	   0x1070000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT6_EN4_1"              ,	   0x1070000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT7_EN4_1"              ,	   0x1070000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT8_EN4_1"              ,	   0x1070000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT9_EN4_1"              ,	   0x1070000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT10_EN4_1"             ,	   0x1070000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT11_EN4_1"             ,	   0x1070000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT4_EN4_1_W1C"          ,	   0x1070000002CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT5_EN4_1_W1C"          ,	   0x1070000002CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT6_EN4_1_W1C"          ,	   0x1070000002CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT7_EN4_1_W1C"          ,	   0x1070000002CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT8_EN4_1_W1C"          ,	   0x1070000002D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT9_EN4_1_W1C"          ,	   0x1070000002D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT10_EN4_1_W1C"         ,	   0x1070000002D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT11_EN4_1_W1C"         ,	   0x1070000002D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT4_EN4_1_W1S"          ,	   0x1070000006CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT5_EN4_1_W1S"          ,	   0x1070000006CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT6_EN4_1_W1S"          ,	   0x1070000006CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT7_EN4_1_W1S"          ,	   0x1070000006CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT8_EN4_1_W1S"          ,	   0x1070000006D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT9_EN4_1_W1S"          ,	   0x1070000006D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT10_EN4_1_W1S"         ,	   0x1070000006D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT11_EN4_1_W1S"         ,	   0x1070000006D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT8_SUM0"               ,	   0x1070000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT9_SUM0"               ,	   0x1070000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT10_SUM0"              ,	   0x1070000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT11_SUM0"              ,	   0x1070000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT12_SUM0"              ,	   0x1070000000060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT13_SUM0"              ,	   0x1070000000068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT14_SUM0"              ,	   0x1070000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT15_SUM0"              ,	   0x1070000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT16_SUM0"              ,	   0x1070000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT17_SUM0"              ,	   0x1070000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT18_SUM0"              ,	   0x1070000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT19_SUM0"              ,	   0x1070000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT20_SUM0"              ,	   0x10700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT21_SUM0"              ,	   0x10700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT22_SUM0"              ,	   0x10700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT23_SUM0"              ,	   0x10700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT4_SUM4"               ,	   0x1070000000C20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT5_SUM4"               ,	   0x1070000000C28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT6_SUM4"               ,	   0x1070000000C30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT7_SUM4"               ,	   0x1070000000C38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT8_SUM4"               ,	   0x1070000000C40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT9_SUM4"               ,	   0x1070000000C48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT10_SUM4"              ,	   0x1070000000C50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT11_SUM4"              ,	   0x1070000000C58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR4"               ,	   0x10700000006A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR5"               ,	   0x10700000006A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR6"               ,	   0x10700000006B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR7"               ,	   0x10700000006B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR8"               ,	   0x10700000006C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR9"               ,	   0x10700000006C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR10"              ,	   0x10700000006D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR11"              ,	   0x10700000006D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET4"               ,	   0x1070000000620ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET5"               ,	   0x1070000000628ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET6"               ,	   0x1070000000630ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET7"               ,	   0x1070000000638ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET8"               ,	   0x1070000000640ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET9"               ,	   0x1070000000648ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET10"              ,	   0x1070000000650ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET11"              ,	   0x1070000000658ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE4"                ,	   0x10700000005A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE5"                ,	   0x10700000005A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE6"                ,	   0x10700000005B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE7"                ,	   0x10700000005B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE8"                ,	   0x10700000005C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE9"                ,	   0x10700000005C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE10"               ,	   0x10700000005D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE11"               ,	   0x10700000005D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_QLM_DCOK"                ,	   0x1070000000760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG4"                   ,	   0x1070000000520ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG5"                   ,	   0x1070000000528ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG6"                   ,	   0x1070000000530ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG7"                   ,	   0x1070000000538ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG8"                   ,	   0x1070000000540ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG9"                   ,	   0x1070000000548ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG10"                  ,	   0x1070000000550ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG11"                  ,	   0x1070000000558ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_FPF1_MARKS"              ,	   0x1180028000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF2_MARKS"              ,	   0x1180028000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF3_MARKS"              ,	   0x1180028000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF4_MARKS"              ,	   0x1180028000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF5_MARKS"              ,	   0x1180028000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF6_MARKS"              ,	   0x1180028000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF7_MARKS"              ,	   0x1180028000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_FPF1_SIZE"               ,	   0x1180028000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF2_SIZE"               ,	   0x1180028000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF3_SIZE"               ,	   0x1180028000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF4_SIZE"               ,	   0x1180028000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF5_SIZE"               ,	   0x1180028000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF6_SIZE"               ,	   0x1180028000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF7_SIZE"               ,	   0x1180028000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_FPF0_MARKS"              ,	   0x1180028000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_FPF0_SIZE"               ,	   0x1180028000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX1_BAD_REG"                ,	   0x1180010000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX1_BIST"                   ,	   0x1180010000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX1_CLK_EN"                 ,	   0x11800100007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX1_HG2_CONTROL"            ,	   0x1180010000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX1_INF_MODE"               ,	   0x11800100007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX1_NXA_ADR"                ,	   0x1180010000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX1_PRT000_CBFC_CTL"        ,	   0x1180010000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_PRT000_CFG"             ,	   0x1180010000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_PRT001_CFG"             ,	   0x1180010000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_PRT002_CFG"             ,	   0x1180010001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX1_PRT003_CFG"             ,	   0x1180010001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX000_ADR_CAM0"         ,	   0x1180010000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX001_ADR_CAM0"         ,	   0x1180010000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX002_ADR_CAM0"         ,	   0x1180010001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX1_RX003_ADR_CAM0"         ,	   0x1180010001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX000_ADR_CAM1"         ,	   0x1180010000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX001_ADR_CAM1"         ,	   0x1180010000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX002_ADR_CAM1"         ,	   0x1180010001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX1_RX003_ADR_CAM1"         ,	   0x1180010001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX000_ADR_CAM2"         ,	   0x1180010000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX001_ADR_CAM2"         ,	   0x1180010000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX002_ADR_CAM2"         ,	   0x1180010001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX1_RX003_ADR_CAM2"         ,	   0x1180010001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX000_ADR_CAM3"         ,	   0x1180010000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX001_ADR_CAM3"         ,	   0x1180010000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX002_ADR_CAM3"         ,	   0x1180010001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX1_RX003_ADR_CAM3"         ,	   0x1180010001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX000_ADR_CAM4"         ,	   0x11800100001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX001_ADR_CAM4"         ,	   0x11800100009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX002_ADR_CAM4"         ,	   0x11800100011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX1_RX003_ADR_CAM4"         ,	   0x11800100019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX000_ADR_CAM5"         ,	   0x11800100001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX001_ADR_CAM5"         ,	   0x11800100009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX002_ADR_CAM5"         ,	   0x11800100011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX1_RX003_ADR_CAM5"         ,	   0x11800100019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX000_ADR_CAM_EN"       ,	   0x1180010000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX001_ADR_CAM_EN"       ,	   0x1180010000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX002_ADR_CAM_EN"       ,	   0x1180010001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX1_RX003_ADR_CAM_EN"       ,	   0x1180010001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX000_ADR_CTL"          ,	   0x1180010000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX001_ADR_CTL"          ,	   0x1180010000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX002_ADR_CTL"          ,	   0x1180010001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX1_RX003_ADR_CTL"          ,	   0x1180010001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX000_DECISION"         ,	   0x1180010000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX001_DECISION"         ,	   0x1180010000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX002_DECISION"         ,	   0x1180010001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX1_RX003_DECISION"         ,	   0x1180010001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX000_FRM_CHK"          ,	   0x1180010000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX001_FRM_CHK"          ,	   0x1180010000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX002_FRM_CHK"          ,	   0x1180010001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX1_RX003_FRM_CHK"          ,	   0x1180010001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX000_FRM_CTL"          ,	   0x1180010000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX001_FRM_CTL"          ,	   0x1180010000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX002_FRM_CTL"          ,	   0x1180010001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX1_RX003_FRM_CTL"          ,	   0x1180010001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX000_IFG"              ,	   0x1180010000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX001_IFG"              ,	   0x1180010000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX002_IFG"              ,	   0x1180010001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX1_RX003_IFG"              ,	   0x1180010001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX000_INT_EN"           ,	   0x1180010000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX001_INT_EN"           ,	   0x1180010000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX002_INT_EN"           ,	   0x1180010001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX1_RX003_INT_EN"           ,	   0x1180010001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX000_INT_REG"          ,	   0x1180010000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX001_INT_REG"          ,	   0x1180010000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX002_INT_REG"          ,	   0x1180010001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX1_RX003_INT_REG"          ,	   0x1180010001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX000_JABBER"           ,	   0x1180010000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX001_JABBER"           ,	   0x1180010000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX002_JABBER"           ,	   0x1180010001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX1_RX003_JABBER"           ,	   0x1180010001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX000_PAUSE_DROP_TIME"  ,	   0x1180010000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX001_PAUSE_DROP_TIME"  ,	   0x1180010000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX002_PAUSE_DROP_TIME"  ,	   0x1180010001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX1_RX003_PAUSE_DROP_TIME"  ,	   0x1180010001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX000_STATS_CTL"        ,	   0x1180010000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX001_STATS_CTL"        ,	   0x1180010000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX002_STATS_CTL"        ,	   0x1180010001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX1_RX003_STATS_CTL"        ,	   0x1180010001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX000_STATS_OCTS"       ,	   0x1180010000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX001_STATS_OCTS"       ,	   0x1180010000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX002_STATS_OCTS"       ,	   0x1180010001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX1_RX003_STATS_OCTS"       ,	   0x1180010001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX000_STATS_OCTS_CTL"   ,	   0x1180010000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX001_STATS_OCTS_CTL"   ,	   0x1180010000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX002_STATS_OCTS_CTL"   ,	   0x1180010001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX1_RX003_STATS_OCTS_CTL"   ,	   0x1180010001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX000_STATS_OCTS_DMAC"  ,	   0x11800100000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX001_STATS_OCTS_DMAC"  ,	   0x11800100008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX002_STATS_OCTS_DMAC"  ,	   0x11800100010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX1_RX003_STATS_OCTS_DMAC"  ,	   0x11800100018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX000_STATS_OCTS_DRP"   ,	   0x11800100000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX001_STATS_OCTS_DRP"   ,	   0x11800100008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX002_STATS_OCTS_DRP"   ,	   0x11800100010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX1_RX003_STATS_OCTS_DRP"   ,	   0x11800100018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_RX000_STATS_PKTS"       ,	   0x1180010000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_RX001_STATS_PKTS"       ,	   0x1180010000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_RX002_STATS_PKTS"       ,	   0x1180010001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX1_RX003_STATS_PKTS"       ,	   0x1180010001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX000_STATS_PKTS_BAD"   ,	   0x11800100000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX001_STATS_PKTS_BAD"   ,	   0x11800100008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX002_STATS_PKTS_BAD"   ,	   0x11800100010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX1_RX003_STATS_PKTS_BAD"   ,	   0x11800100018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_RX000_STATS_PKTS_CTL"   ,	   0x1180010000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_RX001_STATS_PKTS_CTL"   ,	   0x1180010000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_RX002_STATS_PKTS_CTL"   ,	   0x1180010001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX1_RX003_STATS_PKTS_CTL"   ,	   0x1180010001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX000_STATS_PKTS_DMAC"  ,	   0x11800100000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX001_STATS_PKTS_DMAC"  ,	   0x11800100008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX002_STATS_PKTS_DMAC"  ,	   0x11800100010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX1_RX003_STATS_PKTS_DMAC"  ,	   0x11800100018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX000_STATS_PKTS_DRP"   ,	   0x11800100000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX001_STATS_PKTS_DRP"   ,	   0x11800100008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX002_STATS_PKTS_DRP"   ,	   0x11800100010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX1_RX003_STATS_PKTS_DRP"   ,	   0x11800100018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_RX000_UDD_SKP"          ,	   0x1180010000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_RX001_UDD_SKP"          ,	   0x1180010000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_RX002_UDD_SKP"          ,	   0x1180010001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX1_RX003_UDD_SKP"          ,	   0x1180010001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_RX_BP_DROP000"          ,	   0x1180010000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_RX_BP_DROP001"          ,	   0x1180010000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_RX_BP_DROP002"          ,	   0x1180010000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX1_RX_BP_DROP003"          ,	   0x1180010000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_RX_BP_OFF000"           ,	   0x1180010000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_RX_BP_OFF001"           ,	   0x1180010000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_RX_BP_OFF002"           ,	   0x1180010000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX1_RX_BP_OFF003"           ,	   0x1180010000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_RX_BP_ON000"            ,	   0x1180010000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_RX_BP_ON001"            ,	   0x1180010000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_RX_BP_ON002"            ,	   0x1180010000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX1_RX_BP_ON003"            ,	   0x1180010000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX1_RX_HG2_STATUS"          ,	   0x1180010000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX1_RX_PRT_INFO"            ,	   0x11800100004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX1_RX_PRTS"                ,	   0x1180010000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX1_RX_XAUI_BAD_COL"        ,	   0x1180010000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX1_RX_XAUI_CTL"            ,	   0x1180010000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_SMAC000"                ,	   0x1180010000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_SMAC001"                ,	   0x1180010000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_SMAC002"                ,	   0x1180010001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX1_SMAC003"                ,	   0x1180010001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX1_STAT_BP"                ,	   0x1180010000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX000_APPEND"           ,	   0x1180010000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX001_APPEND"           ,	   0x1180010000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX002_APPEND"           ,	   0x1180010001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX1_TX003_APPEND"           ,	   0x1180010001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX000_BURST"            ,	   0x1180010000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX001_BURST"            ,	   0x1180010000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX002_BURST"            ,	   0x1180010001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX1_TX003_BURST"            ,	   0x1180010001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX1_TX000_CBFC_XOFF"        ,	   0x11800100005A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX1_TX000_CBFC_XON"         ,	   0x11800100005C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX000_CTL"              ,	   0x1180010000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX001_CTL"              ,	   0x1180010000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX002_CTL"              ,	   0x1180010001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX1_TX003_CTL"              ,	   0x1180010001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX000_MIN_PKT"          ,	   0x1180010000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX001_MIN_PKT"          ,	   0x1180010000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX002_MIN_PKT"          ,	   0x1180010001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX1_TX003_MIN_PKT"          ,	   0x1180010001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX000_PAUSE_PKT_INTERVAL",	   0x1180010000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX001_PAUSE_PKT_INTERVAL",	   0x1180010000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX002_PAUSE_PKT_INTERVAL",	   0x1180010001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX1_TX003_PAUSE_PKT_INTERVAL",	   0x1180010001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX000_PAUSE_PKT_TIME"   ,	   0x1180010000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX001_PAUSE_PKT_TIME"   ,	   0x1180010000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX002_PAUSE_PKT_TIME"   ,	   0x1180010001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX1_TX003_PAUSE_PKT_TIME"   ,	   0x1180010001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX000_PAUSE_TOGO"       ,	   0x1180010000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX001_PAUSE_TOGO"       ,	   0x1180010000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX002_PAUSE_TOGO"       ,	   0x1180010001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX1_TX003_PAUSE_TOGO"       ,	   0x1180010001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX000_PAUSE_ZERO"       ,	   0x1180010000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX001_PAUSE_ZERO"       ,	   0x1180010000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX002_PAUSE_ZERO"       ,	   0x1180010001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX1_TX003_PAUSE_ZERO"       ,	   0x1180010001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX000_SGMII_CTL"        ,	   0x1180010000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX001_SGMII_CTL"        ,	   0x1180010000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX002_SGMII_CTL"        ,	   0x1180010001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX1_TX003_SGMII_CTL"        ,	   0x1180010001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX000_SLOT"             ,	   0x1180010000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX001_SLOT"             ,	   0x1180010000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX002_SLOT"             ,	   0x1180010001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX1_TX003_SLOT"             ,	   0x1180010001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX000_SOFT_PAUSE"       ,	   0x1180010000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX001_SOFT_PAUSE"       ,	   0x1180010000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX002_SOFT_PAUSE"       ,	   0x1180010001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX1_TX003_SOFT_PAUSE"       ,	   0x1180010001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX000_STAT0"            ,	   0x1180010000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX001_STAT0"            ,	   0x1180010000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX002_STAT0"            ,	   0x1180010001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX1_TX003_STAT0"            ,	   0x1180010001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX000_STAT1"            ,	   0x1180010000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX001_STAT1"            ,	   0x1180010000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX002_STAT1"            ,	   0x1180010001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX1_TX003_STAT1"            ,	   0x1180010001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX000_STAT2"            ,	   0x1180010000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX001_STAT2"            ,	   0x1180010000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX002_STAT2"            ,	   0x1180010001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX1_TX003_STAT2"            ,	   0x1180010001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX1_TX000_STAT3"            ,	   0x1180010000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX1_TX001_STAT3"            ,	   0x1180010000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX1_TX002_STAT3"            ,	   0x1180010001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX1_TX003_STAT3"            ,	   0x1180010001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX000_STAT4"            ,	   0x11800100002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX001_STAT4"            ,	   0x1180010000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX002_STAT4"            ,	   0x11800100012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX1_TX003_STAT4"            ,	   0x1180010001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX000_STAT5"            ,	   0x11800100002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX001_STAT5"            ,	   0x1180010000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX002_STAT5"            ,	   0x11800100012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX1_TX003_STAT5"            ,	   0x1180010001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX000_STAT6"            ,	   0x11800100002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX001_STAT6"            ,	   0x1180010000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX002_STAT6"            ,	   0x11800100012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX1_TX003_STAT6"            ,	   0x1180010001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX000_STAT7"            ,	   0x11800100002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX001_STAT7"            ,	   0x1180010000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX002_STAT7"            ,	   0x11800100012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX1_TX003_STAT7"            ,	   0x1180010001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX000_STAT8"            ,	   0x11800100002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX001_STAT8"            ,	   0x1180010000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX002_STAT8"            ,	   0x11800100012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX1_TX003_STAT8"            ,	   0x1180010001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX000_STAT9"            ,	   0x11800100002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX001_STAT9"            ,	   0x1180010000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX002_STAT9"            ,	   0x11800100012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX1_TX003_STAT9"            ,	   0x1180010001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX000_STATS_CTL"        ,	   0x1180010000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX001_STATS_CTL"        ,	   0x1180010000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX002_STATS_CTL"        ,	   0x1180010001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX1_TX003_STATS_CTL"        ,	   0x1180010001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX1_TX000_THRESH"           ,	   0x1180010000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX1_TX001_THRESH"           ,	   0x1180010000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX1_TX002_THRESH"           ,	   0x1180010001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX1_TX003_THRESH"           ,	   0x1180010001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GMX1_TX_BP"                  ,	   0x11800100004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"GMX1_TX_COL_ATTEMPT"         ,	   0x1180010000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"GMX1_TX_CORRUPT"             ,	   0x11800100004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"GMX1_TX_HG2_REG1"            ,	   0x1180010000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"GMX1_TX_HG2_REG2"            ,	   0x1180010000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"GMX1_TX_IFG"                 ,	   0x1180010000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"GMX1_TX_INT_EN"              ,	   0x1180010000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"GMX1_TX_INT_REG"             ,	   0x1180010000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"GMX1_TX_JAM"                 ,	   0x1180010000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"GMX1_TX_LFSR"                ,	   0x11800100004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"GMX1_TX_OVR_BP"              ,	   0x11800100004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"GMX1_TX_PAUSE_PKT_DMAC"      ,	   0x11800100004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"GMX1_TX_PAUSE_PKT_TYPE"      ,	   0x11800100004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"GMX1_TX_PRTS"                ,	   0x1180010000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"GMX1_TX_XAUI_CTL"            ,	   0x1180010000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"GMX1_XAUI_EXT_LOOPBACK"      ,	   0x1180010000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	208},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	209},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	210},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	211},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT16_BP_PAGE_CNT"      ,	   0x14F00000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT17_BP_PAGE_CNT"      ,	   0x14F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT18_BP_PAGE_CNT"      ,	   0x14F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT19_BP_PAGE_CNT"      ,	   0x14F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR16" ,	   0x14F0000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR17" ,	   0x14F0000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR18" ,	   0x14F0000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR19" ,	   0x14F0000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_128_CNT"        ,	   0x14F0000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_129_CNT"        ,	   0x14F0000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_130_CNT"        ,	   0x14F0000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_131_CNT"        ,	   0x14F0000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_132_CNT"        ,	   0x14F0000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_133_CNT"        ,	   0x14F0000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_134_CNT"        ,	   0x14F0000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_135_CNT"        ,	   0x14F0000000CC0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_136_CNT"        ,	   0x14F0000000CC8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_137_CNT"        ,	   0x14F0000000CD0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_138_CNT"        ,	   0x14F0000000CD8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_139_CNT"        ,	   0x14F0000000CE0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_140_CNT"        ,	   0x14F0000000CE8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_141_CNT"        ,	   0x14F0000000CF0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_142_CNT"        ,	   0x14F0000000CF8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_143_CNT"        ,	   0x14F0000000D00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_144_CNT"        ,	   0x14F0000000D08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_145_CNT"        ,	   0x14F0000000D10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_146_CNT"        ,	   0x14F0000000D18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_147_CNT"        ,	   0x14F0000000D20ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_148_CNT"        ,	   0x14F0000000D28ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_149_CNT"        ,	   0x14F0000000D30ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_150_CNT"        ,	   0x14F0000000D38ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_151_CNT"        ,	   0x14F0000000D40ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_152_CNT"        ,	   0x14F0000000D48ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_153_CNT"        ,	   0x14F0000000D50ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_154_CNT"        ,	   0x14F0000000D58ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_155_CNT"        ,	   0x14F0000000D60ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_156_CNT"        ,	   0x14F0000000D68ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_157_CNT"        ,	   0x14F0000000D70ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_158_CNT"        ,	   0x14F0000000D78ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_159_CNT"        ,	   0x14F0000000D80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14F0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14F0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14F0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14F00000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14F00000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14F00000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14F00000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14F00000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14F00000010C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14F00000010D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14F00000010D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14F00000010E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14F00000010E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14F00000010F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14F00000010F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14F0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14F0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14F0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14F0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14F0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14F0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14F0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14F0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14F0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14F0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14F0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14F0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14F0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14F0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14F0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14F0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14F0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PORT_QOS_INT2"           ,	   0x14F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PORT_QOS_INT_ENB2"       ,	   0x14F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	264},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	265},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	266},
+	{"KEY_BIST_REG"                ,	   0x1180020000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"KEY_CTL_STATUS"              ,	   0x1180020000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"KEY_INT_ENB"                 ,	   0x1180020000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"KEY_INT_SUM"                 ,	   0x1180020000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"L2C_SPAR1"                   ,	   0x1180080000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"L2C_SPAR2"                   ,	   0x1180080000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LED_BLINK"                   ,	   0x1180000001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LED_CLK_PHASE"               ,	   0x1180000001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LED_CYLON"                   ,	   0x1180000001AF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LED_DBG"                     ,	   0x1180000001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LED_EN"                      ,	   0x1180000001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LED_POLARITY"                ,	   0x1180000001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LED_PRT"                     ,	   0x1180000001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"LED_PRT_FMT"                 ,	   0x1180000001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"LED_PRT_STATUS0"             ,	   0x1180000001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS1"             ,	   0x1180000001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS2"             ,	   0x1180000001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS3"             ,	   0x1180000001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS4"             ,	   0x1180000001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS5"             ,	   0x1180000001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS6"             ,	   0x1180000001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_PRT_STATUS7"             ,	   0x1180000001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LED_UDD_CNT0"                ,	   0x1180000001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LED_UDD_CNT1"                ,	   0x1180000001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LED_UDD_DAT0"                ,	   0x1180000001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LED_UDD_DAT1"                ,	   0x1180000001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LED_UDD_DAT_CLR0"            ,	   0x1180000001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LED_UDD_DAT_CLR1"            ,	   0x1180000001AD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LED_UDD_DAT_SET0"            ,	   0x1180000001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LED_UDD_DAT_SET1"            ,	   0x1180000001AD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC1_BIST_CTL"               ,	   0x11800E80000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC1_BIST_RESULT"            ,	   0x11800E80000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC1_COMP_CTL"               ,	   0x11800E8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC1_CTL"                    ,	   0x11800E8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC1_CTL1"                   ,	   0x11800E8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC1_DCLK_CNT_HI"            ,	   0x11800E8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC1_DCLK_CNT_LO"            ,	   0x11800E8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"LMC0_DCLK_CTL"               ,	   0x11800880000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC1_DCLK_CTL"               ,	   0x11800E80000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"LMC1_DDR2_CTL"               ,	   0x11800E8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC1_DELAY_CFG"              ,	   0x11800E8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC1_DLL_CTL"                ,	   0x11800E80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"LMC1_DUAL_MEMCFG"            ,	   0x11800E8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"LMC1_ECC_SYND"               ,	   0x11800E8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"LMC1_FADR"                   ,	   0x11800E8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"LMC1_IFB_CNT_HI"             ,	   0x11800E8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"LMC1_IFB_CNT_LO"             ,	   0x11800E8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"LMC1_MEM_CFG0"               ,	   0x11800E8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"LMC1_MEM_CFG1"               ,	   0x11800E8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"LMC0_NXM"                    ,	   0x11800880000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"LMC1_NXM"                    ,	   0x11800E80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"LMC1_OPS_CNT_HI"             ,	   0x11800E8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"LMC1_OPS_CNT_LO"             ,	   0x11800E8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"LMC1_PLL_CTL"                ,	   0x11800E80000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"LMC1_PLL_STATUS"             ,	   0x11800E80000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"LMC1_READ_LEVEL_CTL"         ,	   0x11800E8000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"LMC1_READ_LEVEL_DBG"         ,	   0x11800E8000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK000"     ,	   0x11800E8000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK001"     ,	   0x11800E8000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK002"     ,	   0x11800E8000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC1_READ_LEVEL_RANK003"     ,	   0x11800E8000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"LMC1_RODT_COMP_CTL"          ,	   0x11800E80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"LMC1_RODT_CTL"               ,	   0x11800E8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"LMC1_WODT_CTL0"              ,	   0x11800E8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"LMC1_WODT_CTL1"              ,	   0x11800E8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_BOOT_DMA_CFG2"           ,	   0x1180000000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_BOOT_DMA_INT2"           ,	   0x1180000000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_BOOT_DMA_INT_EN2"        ,	   0x1180000000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_BOOT_DMA_TIM2"           ,	   0x1180000000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	413},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	414},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	415},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	416},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	417},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	418},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	419},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	420},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	421},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	422},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	424},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	425},
+	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
+	{"NPEI_BIST_STATUS2"           ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
+	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
+	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
+	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
+	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
+	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
+	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA4_COUNTS"            ,	   0x11F0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA4_DBELL"             ,	   0x11F00000083F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	436},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11F0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA4_NADDR"             ,	   0x11F00000084E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_DMA_PCIE_REQ_NUM"       ,	   0x11F00000085B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_INT_A_ENB"              ,	   0x11F0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_INT_A_ENB2"             ,	   0x11F000000BCE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_INT_A_SUM"              ,	   0x11F0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_INT_INFO"               ,	   0x11F0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
+	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_INT_SUM2"               ,	   0x11F000000BCC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
+	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
+	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
+	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
+	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
+	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	464},
+	{"NPEI_MSI_W1C_ENB0"           ,	   0x11F000000BCF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	465},
+	{"NPEI_MSI_W1C_ENB1"           ,	   0x11F000000BD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	466},
+	{"NPEI_MSI_W1C_ENB2"           ,	   0x11F000000BD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	467},
+	{"NPEI_MSI_W1C_ENB3"           ,	   0x11F000000BD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	468},
+	{"NPEI_MSI_W1S_ENB0"           ,	   0x11F000000BD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
+	{"NPEI_MSI_W1S_ENB1"           ,	   0x11F000000BD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MSI_W1S_ENB2"           ,	   0x11F000000BD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	471},
+	{"NPEI_MSI_W1S_ENB3"           ,	   0x11F000000BD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	472},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	473},
+	{"NPEI_PCIE_CREDIT_CNT"        ,	   0x11F000000BD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	474},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	475},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	476},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	477},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	478},
+	{"NPEI_PKT0_CNTS"              ,	   0x11F000000A400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT1_CNTS"              ,	   0x11F000000A410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT2_CNTS"              ,	   0x11F000000A420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT3_CNTS"              ,	   0x11F000000A430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT4_CNTS"              ,	   0x11F000000A440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT5_CNTS"              ,	   0x11F000000A450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT6_CNTS"              ,	   0x11F000000A460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT7_CNTS"              ,	   0x11F000000A470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT8_CNTS"              ,	   0x11F000000A480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT9_CNTS"              ,	   0x11F000000A490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT10_CNTS"             ,	   0x11F000000A4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT11_CNTS"             ,	   0x11F000000A4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT12_CNTS"             ,	   0x11F000000A4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT13_CNTS"             ,	   0x11F000000A4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT14_CNTS"             ,	   0x11F000000A4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT15_CNTS"             ,	   0x11F000000A4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT16_CNTS"             ,	   0x11F000000A500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT17_CNTS"             ,	   0x11F000000A510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT18_CNTS"             ,	   0x11F000000A520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT19_CNTS"             ,	   0x11F000000A530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT20_CNTS"             ,	   0x11F000000A540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT21_CNTS"             ,	   0x11F000000A550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT22_CNTS"             ,	   0x11F000000A560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT23_CNTS"             ,	   0x11F000000A570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT24_CNTS"             ,	   0x11F000000A580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT25_CNTS"             ,	   0x11F000000A590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT26_CNTS"             ,	   0x11F000000A5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT27_CNTS"             ,	   0x11F000000A5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT28_CNTS"             ,	   0x11F000000A5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT29_CNTS"             ,	   0x11F000000A5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT30_CNTS"             ,	   0x11F000000A5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT31_CNTS"             ,	   0x11F000000A5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_PKT0_IN_BP"             ,	   0x11F000000B800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT1_IN_BP"             ,	   0x11F000000B810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT2_IN_BP"             ,	   0x11F000000B820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT3_IN_BP"             ,	   0x11F000000B830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT4_IN_BP"             ,	   0x11F000000B840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT5_IN_BP"             ,	   0x11F000000B850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT6_IN_BP"             ,	   0x11F000000B860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT7_IN_BP"             ,	   0x11F000000B870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT8_IN_BP"             ,	   0x11F000000B880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT9_IN_BP"             ,	   0x11F000000B890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT10_IN_BP"            ,	   0x11F000000B8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT11_IN_BP"            ,	   0x11F000000B8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT12_IN_BP"            ,	   0x11F000000B8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT13_IN_BP"            ,	   0x11F000000B8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT14_IN_BP"            ,	   0x11F000000B8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT15_IN_BP"            ,	   0x11F000000B8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT16_IN_BP"            ,	   0x11F000000B900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT17_IN_BP"            ,	   0x11F000000B910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT18_IN_BP"            ,	   0x11F000000B920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT19_IN_BP"            ,	   0x11F000000B930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT20_IN_BP"            ,	   0x11F000000B940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT21_IN_BP"            ,	   0x11F000000B950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT22_IN_BP"            ,	   0x11F000000B960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT23_IN_BP"            ,	   0x11F000000B970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT24_IN_BP"            ,	   0x11F000000B980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT25_IN_BP"            ,	   0x11F000000B990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT26_IN_BP"            ,	   0x11F000000B9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT27_IN_BP"            ,	   0x11F000000B9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT28_IN_BP"            ,	   0x11F000000B9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT29_IN_BP"            ,	   0x11F000000B9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT30_IN_BP"            ,	   0x11F000000B9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT31_IN_BP"            ,	   0x11F000000B9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_PKT0_INSTR_BADDR"       ,	   0x11F000000A800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT1_INSTR_BADDR"       ,	   0x11F000000A810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT2_INSTR_BADDR"       ,	   0x11F000000A820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT3_INSTR_BADDR"       ,	   0x11F000000A830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT4_INSTR_BADDR"       ,	   0x11F000000A840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT5_INSTR_BADDR"       ,	   0x11F000000A850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT6_INSTR_BADDR"       ,	   0x11F000000A860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT7_INSTR_BADDR"       ,	   0x11F000000A870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT8_INSTR_BADDR"       ,	   0x11F000000A880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT9_INSTR_BADDR"       ,	   0x11F000000A890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT10_INSTR_BADDR"      ,	   0x11F000000A8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT11_INSTR_BADDR"      ,	   0x11F000000A8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT12_INSTR_BADDR"      ,	   0x11F000000A8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT13_INSTR_BADDR"      ,	   0x11F000000A8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT14_INSTR_BADDR"      ,	   0x11F000000A8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT15_INSTR_BADDR"      ,	   0x11F000000A8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT16_INSTR_BADDR"      ,	   0x11F000000A900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT17_INSTR_BADDR"      ,	   0x11F000000A910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT18_INSTR_BADDR"      ,	   0x11F000000A920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT19_INSTR_BADDR"      ,	   0x11F000000A930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT20_INSTR_BADDR"      ,	   0x11F000000A940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT21_INSTR_BADDR"      ,	   0x11F000000A950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT22_INSTR_BADDR"      ,	   0x11F000000A960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT23_INSTR_BADDR"      ,	   0x11F000000A970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT24_INSTR_BADDR"      ,	   0x11F000000A980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT25_INSTR_BADDR"      ,	   0x11F000000A990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT26_INSTR_BADDR"      ,	   0x11F000000A9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT27_INSTR_BADDR"      ,	   0x11F000000A9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT28_INSTR_BADDR"      ,	   0x11F000000A9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT29_INSTR_BADDR"      ,	   0x11F000000A9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT30_INSTR_BADDR"      ,	   0x11F000000A9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT31_INSTR_BADDR"      ,	   0x11F000000A9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_PKT0_INSTR_BAOFF_DBELL" ,	   0x11F000000AC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT1_INSTR_BAOFF_DBELL" ,	   0x11F000000AC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT2_INSTR_BAOFF_DBELL" ,	   0x11F000000AC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT3_INSTR_BAOFF_DBELL" ,	   0x11F000000AC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT4_INSTR_BAOFF_DBELL" ,	   0x11F000000AC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT5_INSTR_BAOFF_DBELL" ,	   0x11F000000AC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT6_INSTR_BAOFF_DBELL" ,	   0x11F000000AC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT7_INSTR_BAOFF_DBELL" ,	   0x11F000000AC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT8_INSTR_BAOFF_DBELL" ,	   0x11F000000AC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT9_INSTR_BAOFF_DBELL" ,	   0x11F000000AC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT10_INSTR_BAOFF_DBELL",	   0x11F000000ACA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT11_INSTR_BAOFF_DBELL",	   0x11F000000ACB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT12_INSTR_BAOFF_DBELL",	   0x11F000000ACC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT13_INSTR_BAOFF_DBELL",	   0x11F000000ACD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT14_INSTR_BAOFF_DBELL",	   0x11F000000ACE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT15_INSTR_BAOFF_DBELL",	   0x11F000000ACF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT16_INSTR_BAOFF_DBELL",	   0x11F000000AD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT17_INSTR_BAOFF_DBELL",	   0x11F000000AD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT18_INSTR_BAOFF_DBELL",	   0x11F000000AD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT19_INSTR_BAOFF_DBELL",	   0x11F000000AD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT20_INSTR_BAOFF_DBELL",	   0x11F000000AD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT21_INSTR_BAOFF_DBELL",	   0x11F000000AD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT22_INSTR_BAOFF_DBELL",	   0x11F000000AD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT23_INSTR_BAOFF_DBELL",	   0x11F000000AD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT24_INSTR_BAOFF_DBELL",	   0x11F000000AD80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT25_INSTR_BAOFF_DBELL",	   0x11F000000AD90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT26_INSTR_BAOFF_DBELL",	   0x11F000000ADA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT27_INSTR_BAOFF_DBELL",	   0x11F000000ADB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT28_INSTR_BAOFF_DBELL",	   0x11F000000ADC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT29_INSTR_BAOFF_DBELL",	   0x11F000000ADD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT30_INSTR_BAOFF_DBELL",	   0x11F000000ADE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT31_INSTR_BAOFF_DBELL",	   0x11F000000ADF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,	   0x11F000000B000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,	   0x11F000000B010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,	   0x11F000000B020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,	   0x11F000000B030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,	   0x11F000000B040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,	   0x11F000000B050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,	   0x11F000000B060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,	   0x11F000000B070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,	   0x11F000000B080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,	   0x11F000000B090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT10_INSTR_FIFO_RSIZE" ,	   0x11F000000B0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT11_INSTR_FIFO_RSIZE" ,	   0x11F000000B0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT12_INSTR_FIFO_RSIZE" ,	   0x11F000000B0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT13_INSTR_FIFO_RSIZE" ,	   0x11F000000B0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT14_INSTR_FIFO_RSIZE" ,	   0x11F000000B0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT15_INSTR_FIFO_RSIZE" ,	   0x11F000000B0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT16_INSTR_FIFO_RSIZE" ,	   0x11F000000B100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT17_INSTR_FIFO_RSIZE" ,	   0x11F000000B110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT18_INSTR_FIFO_RSIZE" ,	   0x11F000000B120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT19_INSTR_FIFO_RSIZE" ,	   0x11F000000B130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT20_INSTR_FIFO_RSIZE" ,	   0x11F000000B140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT21_INSTR_FIFO_RSIZE" ,	   0x11F000000B150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT22_INSTR_FIFO_RSIZE" ,	   0x11F000000B160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT23_INSTR_FIFO_RSIZE" ,	   0x11F000000B170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT24_INSTR_FIFO_RSIZE" ,	   0x11F000000B180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT25_INSTR_FIFO_RSIZE" ,	   0x11F000000B190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT26_INSTR_FIFO_RSIZE" ,	   0x11F000000B1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT27_INSTR_FIFO_RSIZE" ,	   0x11F000000B1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT28_INSTR_FIFO_RSIZE" ,	   0x11F000000B1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT29_INSTR_FIFO_RSIZE" ,	   0x11F000000B1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT30_INSTR_FIFO_RSIZE" ,	   0x11F000000B1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT31_INSTR_FIFO_RSIZE" ,	   0x11F000000B1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_PKT0_INSTR_HEADER"      ,	   0x11F000000B400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT1_INSTR_HEADER"      ,	   0x11F000000B410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT2_INSTR_HEADER"      ,	   0x11F000000B420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT3_INSTR_HEADER"      ,	   0x11F000000B430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT4_INSTR_HEADER"      ,	   0x11F000000B440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT5_INSTR_HEADER"      ,	   0x11F000000B450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT6_INSTR_HEADER"      ,	   0x11F000000B460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT7_INSTR_HEADER"      ,	   0x11F000000B470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT8_INSTR_HEADER"      ,	   0x11F000000B480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT9_INSTR_HEADER"      ,	   0x11F000000B490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT10_INSTR_HEADER"     ,	   0x11F000000B4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT11_INSTR_HEADER"     ,	   0x11F000000B4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT12_INSTR_HEADER"     ,	   0x11F000000B4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT13_INSTR_HEADER"     ,	   0x11F000000B4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT14_INSTR_HEADER"     ,	   0x11F000000B4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT15_INSTR_HEADER"     ,	   0x11F000000B4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT16_INSTR_HEADER"     ,	   0x11F000000B500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT17_INSTR_HEADER"     ,	   0x11F000000B510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT18_INSTR_HEADER"     ,	   0x11F000000B520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT19_INSTR_HEADER"     ,	   0x11F000000B530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT20_INSTR_HEADER"     ,	   0x11F000000B540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT21_INSTR_HEADER"     ,	   0x11F000000B550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT22_INSTR_HEADER"     ,	   0x11F000000B560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT23_INSTR_HEADER"     ,	   0x11F000000B570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT24_INSTR_HEADER"     ,	   0x11F000000B580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT25_INSTR_HEADER"     ,	   0x11F000000B590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT26_INSTR_HEADER"     ,	   0x11F000000B5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT27_INSTR_HEADER"     ,	   0x11F000000B5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT28_INSTR_HEADER"     ,	   0x11F000000B5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT29_INSTR_HEADER"     ,	   0x11F000000B5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT30_INSTR_HEADER"     ,	   0x11F000000B5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT31_INSTR_HEADER"     ,	   0x11F000000B5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_PKT0_SLIST_BADDR"       ,	   0x11F0000009400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT1_SLIST_BADDR"       ,	   0x11F0000009410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT2_SLIST_BADDR"       ,	   0x11F0000009420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT3_SLIST_BADDR"       ,	   0x11F0000009430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT4_SLIST_BADDR"       ,	   0x11F0000009440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT5_SLIST_BADDR"       ,	   0x11F0000009450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT6_SLIST_BADDR"       ,	   0x11F0000009460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT7_SLIST_BADDR"       ,	   0x11F0000009470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT8_SLIST_BADDR"       ,	   0x11F0000009480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT9_SLIST_BADDR"       ,	   0x11F0000009490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT10_SLIST_BADDR"      ,	   0x11F00000094A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT11_SLIST_BADDR"      ,	   0x11F00000094B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT12_SLIST_BADDR"      ,	   0x11F00000094C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT13_SLIST_BADDR"      ,	   0x11F00000094D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT14_SLIST_BADDR"      ,	   0x11F00000094E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT15_SLIST_BADDR"      ,	   0x11F00000094F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT16_SLIST_BADDR"      ,	   0x11F0000009500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT17_SLIST_BADDR"      ,	   0x11F0000009510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT18_SLIST_BADDR"      ,	   0x11F0000009520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT19_SLIST_BADDR"      ,	   0x11F0000009530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT20_SLIST_BADDR"      ,	   0x11F0000009540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT21_SLIST_BADDR"      ,	   0x11F0000009550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT22_SLIST_BADDR"      ,	   0x11F0000009560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT23_SLIST_BADDR"      ,	   0x11F0000009570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT24_SLIST_BADDR"      ,	   0x11F0000009580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT25_SLIST_BADDR"      ,	   0x11F0000009590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT26_SLIST_BADDR"      ,	   0x11F00000095A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT27_SLIST_BADDR"      ,	   0x11F00000095B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT28_SLIST_BADDR"      ,	   0x11F00000095C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT29_SLIST_BADDR"      ,	   0x11F00000095D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT30_SLIST_BADDR"      ,	   0x11F00000095E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT31_SLIST_BADDR"      ,	   0x11F00000095F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_PKT0_SLIST_BAOFF_DBELL" ,	   0x11F0000009800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT1_SLIST_BAOFF_DBELL" ,	   0x11F0000009810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT2_SLIST_BAOFF_DBELL" ,	   0x11F0000009820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT3_SLIST_BAOFF_DBELL" ,	   0x11F0000009830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT4_SLIST_BAOFF_DBELL" ,	   0x11F0000009840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT5_SLIST_BAOFF_DBELL" ,	   0x11F0000009850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT6_SLIST_BAOFF_DBELL" ,	   0x11F0000009860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT7_SLIST_BAOFF_DBELL" ,	   0x11F0000009870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT8_SLIST_BAOFF_DBELL" ,	   0x11F0000009880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT9_SLIST_BAOFF_DBELL" ,	   0x11F0000009890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT10_SLIST_BAOFF_DBELL",	   0x11F00000098A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT11_SLIST_BAOFF_DBELL",	   0x11F00000098B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT12_SLIST_BAOFF_DBELL",	   0x11F00000098C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT13_SLIST_BAOFF_DBELL",	   0x11F00000098D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT14_SLIST_BAOFF_DBELL",	   0x11F00000098E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT15_SLIST_BAOFF_DBELL",	   0x11F00000098F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT16_SLIST_BAOFF_DBELL",	   0x11F0000009900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT17_SLIST_BAOFF_DBELL",	   0x11F0000009910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT18_SLIST_BAOFF_DBELL",	   0x11F0000009920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT19_SLIST_BAOFF_DBELL",	   0x11F0000009930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT20_SLIST_BAOFF_DBELL",	   0x11F0000009940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT21_SLIST_BAOFF_DBELL",	   0x11F0000009950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT22_SLIST_BAOFF_DBELL",	   0x11F0000009960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT23_SLIST_BAOFF_DBELL",	   0x11F0000009970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT24_SLIST_BAOFF_DBELL",	   0x11F0000009980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT25_SLIST_BAOFF_DBELL",	   0x11F0000009990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT26_SLIST_BAOFF_DBELL",	   0x11F00000099A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT27_SLIST_BAOFF_DBELL",	   0x11F00000099B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT28_SLIST_BAOFF_DBELL",	   0x11F00000099C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT29_SLIST_BAOFF_DBELL",	   0x11F00000099D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT30_SLIST_BAOFF_DBELL",	   0x11F00000099E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT31_SLIST_BAOFF_DBELL",	   0x11F00000099F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT10_SLIST_FIFO_RSIZE" ,	   0x11F0000009CA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT11_SLIST_FIFO_RSIZE" ,	   0x11F0000009CB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT12_SLIST_FIFO_RSIZE" ,	   0x11F0000009CC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT13_SLIST_FIFO_RSIZE" ,	   0x11F0000009CD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT14_SLIST_FIFO_RSIZE" ,	   0x11F0000009CE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT15_SLIST_FIFO_RSIZE" ,	   0x11F0000009CF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT16_SLIST_FIFO_RSIZE" ,	   0x11F0000009D00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT17_SLIST_FIFO_RSIZE" ,	   0x11F0000009D10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT18_SLIST_FIFO_RSIZE" ,	   0x11F0000009D20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT19_SLIST_FIFO_RSIZE" ,	   0x11F0000009D30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT20_SLIST_FIFO_RSIZE" ,	   0x11F0000009D40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT21_SLIST_FIFO_RSIZE" ,	   0x11F0000009D50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT22_SLIST_FIFO_RSIZE" ,	   0x11F0000009D60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT23_SLIST_FIFO_RSIZE" ,	   0x11F0000009D70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT24_SLIST_FIFO_RSIZE" ,	   0x11F0000009D80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT25_SLIST_FIFO_RSIZE" ,	   0x11F0000009D90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT26_SLIST_FIFO_RSIZE" ,	   0x11F0000009DA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT27_SLIST_FIFO_RSIZE" ,	   0x11F0000009DB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT28_SLIST_FIFO_RSIZE" ,	   0x11F0000009DC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT29_SLIST_FIFO_RSIZE" ,	   0x11F0000009DD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT30_SLIST_FIFO_RSIZE" ,	   0x11F0000009DE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT31_SLIST_FIFO_RSIZE" ,	   0x11F0000009DF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_PKT_CNT_INT"            ,	   0x11F0000009110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	488},
+	{"NPEI_PKT_CNT_INT_ENB"        ,	   0x11F0000009130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	489},
+	{"NPEI_PKT_DATA_OUT_ES"        ,	   0x11F00000090B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	490},
+	{"NPEI_PKT_DATA_OUT_NS"        ,	   0x11F00000090A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	491},
+	{"NPEI_PKT_DATA_OUT_ROR"       ,	   0x11F0000009090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	492},
+	{"NPEI_PKT_DPADDR"             ,	   0x11F0000009080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	493},
+	{"NPEI_PKT_IN_BP"              ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT_IN_DONE0_CNTS"      ,	   0x11F000000A000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE1_CNTS"      ,	   0x11F000000A010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE2_CNTS"      ,	   0x11F000000A020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE3_CNTS"      ,	   0x11F000000A030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE4_CNTS"      ,	   0x11F000000A040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE5_CNTS"      ,	   0x11F000000A050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE6_CNTS"      ,	   0x11F000000A060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE7_CNTS"      ,	   0x11F000000A070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE8_CNTS"      ,	   0x11F000000A080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE9_CNTS"      ,	   0x11F000000A090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE10_CNTS"     ,	   0x11F000000A0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE11_CNTS"     ,	   0x11F000000A0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE12_CNTS"     ,	   0x11F000000A0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE13_CNTS"     ,	   0x11F000000A0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE14_CNTS"     ,	   0x11F000000A0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE15_CNTS"     ,	   0x11F000000A0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE16_CNTS"     ,	   0x11F000000A100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE17_CNTS"     ,	   0x11F000000A110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE18_CNTS"     ,	   0x11F000000A120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE19_CNTS"     ,	   0x11F000000A130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE20_CNTS"     ,	   0x11F000000A140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE21_CNTS"     ,	   0x11F000000A150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE22_CNTS"     ,	   0x11F000000A160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE23_CNTS"     ,	   0x11F000000A170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE24_CNTS"     ,	   0x11F000000A180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE25_CNTS"     ,	   0x11F000000A190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE26_CNTS"     ,	   0x11F000000A1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE27_CNTS"     ,	   0x11F000000A1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE28_CNTS"     ,	   0x11F000000A1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE29_CNTS"     ,	   0x11F000000A1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE30_CNTS"     ,	   0x11F000000A1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_DONE31_CNTS"     ,	   0x11F000000A1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT_IN_INSTR_COUNTS"    ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT_IN_PCIE_PORT"       ,	   0x11F00000091A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT_INPUT_CONTROL"      ,	   0x11F0000009150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT_INSTR_ENB"          ,	   0x11F0000009000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT_INSTR_RD_SIZE"      ,	   0x11F0000009190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT_INSTR_SIZE"         ,	   0x11F0000009020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT_INT_LEVELS"         ,	   0x11F0000009100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT_IPTR"               ,	   0x11F0000009070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	503},
+	{"NPEI_PKT_OUT_BMODE"          ,	   0x11F00000090D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	504},
+	{"NPEI_PKT_OUT_ENB"            ,	   0x11F0000009010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	505},
+	{"NPEI_PKT_OUTPUT_WMARK"       ,	   0x11F0000009160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	506},
+	{"NPEI_PKT_PCIE_PORT"          ,	   0x11F00000090E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	507},
+	{"NPEI_PKT_PORT_IN_RST"        ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	508},
+	{"NPEI_PKT_SLIST_ES"           ,	   0x11F0000009050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	509},
+	{"NPEI_PKT_SLIST_ID_SIZE"      ,	   0x11F0000009180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_SLIST_NS"           ,	   0x11F0000009040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	511},
+	{"NPEI_PKT_SLIST_ROR"          ,	   0x11F0000009030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	512},
+	{"NPEI_PKT_TIME_INT"           ,	   0x11F0000009120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	513},
+	{"NPEI_PKT_TIME_INT_ENB"       ,	   0x11F0000009140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	514},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	515},
+	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	516},
+	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	517},
+	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	518},
+	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	519},
+	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	520},
+	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	521},
+	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	522},
+	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	523},
+	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	524},
+	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	525},
+	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
+	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
+	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
+	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
+	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
+	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
+	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
+	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
+	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
+	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
+	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
+	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
+	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
+	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
+	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	540},
+	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
+	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
+	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
+	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
+	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
+	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
+	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
+	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
+	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
+	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN000_ADV_REG"          ,	   0x11800B8001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN001_ADV_REG"          ,	   0x11800B8001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN002_ADV_REG"          ,	   0x11800B8001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS1_AN003_ADV_REG"          ,	   0x11800B8001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN000_EXT_ST_REG"       ,	   0x11800B8001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN001_EXT_ST_REG"       ,	   0x11800B8001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN002_EXT_ST_REG"       ,	   0x11800B8001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS1_AN003_EXT_ST_REG"       ,	   0x11800B8001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN000_LP_ABIL_REG"      ,	   0x11800B8001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN001_LP_ABIL_REG"      ,	   0x11800B8001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN002_LP_ABIL_REG"      ,	   0x11800B8001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS1_AN003_LP_ABIL_REG"      ,	   0x11800B8001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN000_RESULTS_REG"      ,	   0x11800B8001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN001_RESULTS_REG"      ,	   0x11800B8001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN002_RESULTS_REG"      ,	   0x11800B8001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS1_AN003_RESULTS_REG"      ,	   0x11800B8001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT000_EN_REG"          ,	   0x11800B8001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT001_EN_REG"          ,	   0x11800B8001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT002_EN_REG"          ,	   0x11800B8001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS1_INT003_EN_REG"          ,	   0x11800B8001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT000_REG"             ,	   0x11800B8001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT001_REG"             ,	   0x11800B8001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT002_REG"             ,	   0x11800B8001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS1_INT003_REG"             ,	   0x11800B8001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK000_TIMER_COUNT_REG",	   0x11800B8001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK001_TIMER_COUNT_REG",	   0x11800B8001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK002_TIMER_COUNT_REG",	   0x11800B8001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS1_LINK003_TIMER_COUNT_REG",	   0x11800B8001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL000_REG"         ,	   0x11800B8001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL001_REG"         ,	   0x11800B8001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL002_REG"         ,	   0x11800B8001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS1_LOG_ANL003_REG"         ,	   0x11800B8001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC000_CTL_REG"        ,	   0x11800B8001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC001_CTL_REG"        ,	   0x11800B8001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC002_CTL_REG"        ,	   0x11800B8001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS1_MISC003_CTL_REG"        ,	   0x11800B8001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR000_CONTROL_REG"      ,	   0x11800B8001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR001_CONTROL_REG"      ,	   0x11800B8001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR002_CONTROL_REG"      ,	   0x11800B8001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS1_MR003_CONTROL_REG"      ,	   0x11800B8001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR000_STATUS_REG"       ,	   0x11800B8001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR001_STATUS_REG"       ,	   0x11800B8001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR002_STATUS_REG"       ,	   0x11800B8001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS1_MR003_STATUS_REG"       ,	   0x11800B8001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX000_STATES_REG"       ,	   0x11800B8001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX001_STATES_REG"       ,	   0x11800B8001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX002_STATES_REG"       ,	   0x11800B8001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS1_RX003_STATES_REG"       ,	   0x11800B8001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX000_SYNC_REG"         ,	   0x11800B8001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX001_SYNC_REG"         ,	   0x11800B8001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX002_SYNC_REG"         ,	   0x11800B8001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS1_RX003_SYNC_REG"         ,	   0x11800B8001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM000_AN_ADV_REG"      ,	   0x11800B8001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM001_AN_ADV_REG"      ,	   0x11800B8001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM002_AN_ADV_REG"      ,	   0x11800B8001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS1_SGM003_AN_ADV_REG"      ,	   0x11800B8001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM000_LP_ADV_REG"      ,	   0x11800B8001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM001_LP_ADV_REG"      ,	   0x11800B8001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM002_LP_ADV_REG"      ,	   0x11800B8001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS1_SGM003_LP_ADV_REG"      ,	   0x11800B8001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX000_STATES_REG"       ,	   0x11800B8001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX001_STATES_REG"       ,	   0x11800B8001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX002_STATES_REG"       ,	   0x11800B8001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS1_TX003_STATES_REG"       ,	   0x11800B8001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX000_POLARITY_REG"  ,	   0x11800B8001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX001_POLARITY_REG"  ,	   0x11800B8001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX002_POLARITY_REG"  ,	   0x11800B8001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS1_TX_RX003_POLARITY_REG"  ,	   0x11800B8001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PIP_BCK_PRS"                 ,	   0x11800A0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800A0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800A0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800A00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG16"               ,	   0x11800A0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG17"               ,	   0x11800A0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG18"               ,	   0x11800A0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG19"               ,	   0x11800A0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG16"               ,	   0x11800A0000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG17"               ,	   0x11800A0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG18"               ,	   0x11800A0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG19"               ,	   0x11800A0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT16"             ,	   0x11800A0000D00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT17"             ,	   0x11800A0000D50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT18"             ,	   0x11800A0000DA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT19"             ,	   0x11800A0000DF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT16"             ,	   0x11800A0000D08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT17"             ,	   0x11800A0000D58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT18"             ,	   0x11800A0000DA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT19"             ,	   0x11800A0000DF8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT16"             ,	   0x11800A0000D10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT17"             ,	   0x11800A0000D60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT18"             ,	   0x11800A0000DB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT19"             ,	   0x11800A0000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT16"             ,	   0x11800A0000D18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT17"             ,	   0x11800A0000D68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT18"             ,	   0x11800A0000DB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT19"             ,	   0x11800A0000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT16"             ,	   0x11800A0000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT17"             ,	   0x11800A0000D70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT18"             ,	   0x11800A0000DC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT19"             ,	   0x11800A0000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT16"             ,	   0x11800A0000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT17"             ,	   0x11800A0000D78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT18"             ,	   0x11800A0000DC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT19"             ,	   0x11800A0000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT16"             ,	   0x11800A0000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT17"             ,	   0x11800A0000D80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT18"             ,	   0x11800A0000DD0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT19"             ,	   0x11800A0000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT16"             ,	   0x11800A0000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT17"             ,	   0x11800A0000D88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT18"             ,	   0x11800A0000DD8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT19"             ,	   0x11800A0000E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT16"             ,	   0x11800A0000D40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT17"             ,	   0x11800A0000D90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT18"             ,	   0x11800A0000DE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT19"             ,	   0x11800A0000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT16"             ,	   0x11800A0000D48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT17"             ,	   0x11800A0000D98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT18"             ,	   0x11800A0000DE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT19"             ,	   0x11800A0000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS16"         ,	   0x11800A0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS17"         ,	   0x11800A0001C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS18"         ,	   0x11800A0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS19"         ,	   0x11800A0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS16"         ,	   0x11800A0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS17"         ,	   0x11800A0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS18"         ,	   0x11800A0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS19"         ,	   0x11800A0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS16"         ,	   0x11800A0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS17"         ,	   0x11800A0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS18"         ,	   0x11800A0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS19"         ,	   0x11800A0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	802},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	803},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	804},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	805},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	806},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	807},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	808},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	809},
+	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	810},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	811},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	812},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	813},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK4"             ,	   0x1670000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK5"             ,	   0x1670000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK6"             ,	   0x1670000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK7"             ,	   0x1670000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK8"             ,	   0x1670000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK9"             ,	   0x1670000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK10"            ,	   0x1670000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_PP_GRP_MSK11"            ,	   0x1670000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	814},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	815},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	817},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	818},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	822},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	829},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	830},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	831},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	832},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	833},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	834},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	835},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	836},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	837},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	838},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	886},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	887},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	888},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	889},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	890},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	891},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	892},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	893},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	894},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	895},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	896},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	897},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	898},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	899},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	938},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	939},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	940},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	941},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	942},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	943},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	944},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	945},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	946},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	947},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	948},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	949},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	950},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	951},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	952},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	953},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	958},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	959},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	960},
+	{"ZIP_CMD_BIST_RESULT"         ,	   0x1180038000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	961},
+	{"ZIP_CMD_BUF"                 ,	   0x1180038000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	962},
+	{"ZIP_CMD_CTL"                 ,	   0x1180038000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	963},
+	{"ZIP_CONSTANTS"               ,	   0x11800380000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	964},
+	{"ZIP_DEBUG0"                  ,	   0x1180038000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	965},
+	{"ZIP_ERROR"                   ,	   0x1180038000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	966},
+	{"ZIP_INT_MASK"                ,	   0x1180038000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	967},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_21"               ,	3,	19,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_25"              ,	23,	3,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYP_EN"                      ,	16,	1,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	2,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	3,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"DUPLEX"                      ,	2,	1,	4,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_EN"                       ,	4,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	4,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	9,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	10,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	11,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	11,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	12,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	12,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	12,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	12,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	13,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	13,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	14,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	14,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	15,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	16,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	16,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	17,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	17,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	18,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	18,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"MAXERR"                      ,	2,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	19,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	19,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	20,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	21,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	21,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	22,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	22,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	32,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	32,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	33,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	35,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	35,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	36,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	36,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	37,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	1,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	37,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	1,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	38,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	1,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	38,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	39,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	39,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	40,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	40,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	40,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	1,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	64,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	65,	"RAZ",	0,	0,	0ull,	0ull},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	68,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	68,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	68,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	4,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	71,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	12,	72,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	72,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	12,	73,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	73,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	74,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	74,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	75,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	76,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	76,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	12,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	78,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	12,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	79,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	12,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	80,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	81,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	81,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	82,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	82,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	83,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	12,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	84,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	12,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	85,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	12,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	86,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	87,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	2,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KEY_ZERO"                    ,	51,	1,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	88,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	12,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	89,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	90,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	91,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	12,	92,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	92,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	93,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	12,	94,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	94,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	95,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	96,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	11,	96,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	96,	"RAZ",	1,	1,	0,	0},
+	{"QLM_DCOK"                    ,	0,	4,	97,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	97,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	4,	98,	"R/W",	0,	1,	0ull,	0},
+	{"MUX_SEL"                     ,	4,	2,	98,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	98,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	98,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	98,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	99,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	99,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	99,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	4,	99,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_60"              ,	44,	17,	99,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	99,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	99,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	99,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	100,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	101,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	101,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	102,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	102,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	103,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	103,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	104,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	105,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	106,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	107,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	11,	108,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	11,	11,	108,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_22_63"              ,	22,	42,	108,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	11,	109,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	109,	"RAZ",	1,	1,	0,	0},
+	{"FPF_RD"                      ,	0,	12,	110,	"R/W",	0,	0,	64ull,	0ull},
+	{"FPF_WR"                      ,	12,	12,	110,	"R/W",	0,	0,	196ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	110,	"RAZ",	1,	1,	0,	0},
+	{"FPF_SIZ"                     ,	0,	12,	111,	"R/W",	0,	0,	256ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	111,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	112,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	112,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	113,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	113,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	114,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	114,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	115,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	115,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	116,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	116,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	116,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	117,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	117,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	117,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	118,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	118,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	119,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	119,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	120,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	120,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	120,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	120,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	120,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	120,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	120,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	121,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	121,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	122,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	123,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	123,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	123,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	124,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	124,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	124,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	2,	124,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	124,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	2,	124,	"RO",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	124,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	125,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	125,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	126,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	126,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	126,	"R/W",	0,	1,	0ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	126,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	126,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	127,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	127,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	127,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	127,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	127,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	127,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	127,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	127,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	127,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	127,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	128,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	129,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	130,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	131,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	132,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	133,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	134,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	134,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	135,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	135,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	135,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	135,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	136,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	136,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	137,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	137,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	137,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	137,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	137,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	137,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	137,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	137,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	137,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	138,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	138,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	138,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	138,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	139,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	139,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	140,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	140,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	140,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	140,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	140,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	140,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	141,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	141,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	141,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	141,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	141,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	141,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	141,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	142,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	142,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	143,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	143,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	144,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	144,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	145,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	145,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	146,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	146,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	147,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	147,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	148,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	148,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	149,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	149,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	150,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	150,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	151,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	151,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	152,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	152,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	153,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	153,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	154,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	154,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	155,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	155,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	156,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	156,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	157,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	157,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	158,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	158,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	158,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	158,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	159,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	159,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	159,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	160,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	160,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	161,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	161,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	161,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	161,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	161,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	162,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	162,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	163,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	163,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	164,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	164,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	165,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	165,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	165,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	165,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	165,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	166,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	166,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	167,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	167,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	168,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	168,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	169,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	169,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	169,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	170,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	170,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	171,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	171,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	172,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	172,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	173,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	173,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	173,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	174,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	174,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	175,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	175,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	176,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	176,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	177,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	177,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	178,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	178,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	179,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	179,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	180,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	180,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	181,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	181,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	182,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	182,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	183,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	183,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	184,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	184,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	185,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	185,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	186,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	186,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	187,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	187,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	188,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	188,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	189,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	189,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	190,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	191,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	191,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	192,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	192,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	193,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	193,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	194,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	194,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	195,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	195,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	195,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	196,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	197,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	197,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	198,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	198,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	199,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	199,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	200,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	200,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	201,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	201,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	202,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	202,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	203,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	203,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	204,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	204,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	204,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	204,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	204,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	205,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	205,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	205,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	206,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	207,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	208,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	208,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	209,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	209,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	210,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	210,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	211,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	211,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	212,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	213,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	213,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	213,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	213,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	213,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	214,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	215,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	215,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	215,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	216,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	217,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	217,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	217,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	217,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	217,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	218,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	218,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	218,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	218,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	218,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	219,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	220,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	221,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	222,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	222,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	222,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	222,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	222,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	222,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	222,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	223,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	224,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	224,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	225,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	226,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	226,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	226,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	226,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	227,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	227,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	227,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	227,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	227,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	228,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	229,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	230,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	230,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	231,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	232,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	233,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	233,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	234,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	234,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	235,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	236,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	236,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	237,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	237,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	40,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	238,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	239,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	240,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	240,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	241,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	242,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	242,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	243,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	244,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	244,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	245,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	245,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	246,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	246,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	246,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	247,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	247,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	247,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	248,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	248,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	249,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	249,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	250,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	250,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	251,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	252,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	253,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	253,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	253,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	253,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	253,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	253,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	254,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	254,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	254,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	254,	"RO",	0,	0,	16ull,	16ull},
+	{"RESERVED_44_63"              ,	44,	20,	254,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	255,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	256,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	256,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	256,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	256,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	256,	"RO",	0,	0,	64ull,	64ull},
+	{"RESERVED_61_63"              ,	61,	3,	256,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	257,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	257,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	258,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	258,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	259,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	4,	260,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	260,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	261,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	261,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	261,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	261,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	261,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	262,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	262,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	262,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	263,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	263,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	263,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	263,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	264,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	264,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	264,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	265,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	265,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	266,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	266,	"RAZ",	1,	1,	0,	0},
+	{"MEM0"                        ,	0,	1,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"MEM1"                        ,	1,	1,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	2,	1,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	267,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	268,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	269,	"RAZ",	1,	1,	0,	0},
+	{"KED0_SBE"                    ,	0,	1,	270,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED0_DBE"                    ,	1,	1,	270,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_SBE"                    ,	2,	1,	270,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"KED1_DBE"                    ,	3,	1,	270,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	270,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	13,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	271,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF0"                   ,	9,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF1"                   ,	11,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF0"                       ,	12,	4,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF1"                       ,	16,	4,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"ILC"                         ,	20,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC0"                        ,	21,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC1"                        ,	22,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC2"                        ,	23,	1,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"PICBST"                      ,	2,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RHDB"                        ,	4,	4,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RMDB"                        ,	8,	4,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	273,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	273,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	274,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	274,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	274,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	274,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	274,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"DFILL_DIS"                   ,	14,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPRES0"                      ,	15,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPRES1"                      ,	16,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_BANK"                    ,	17,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBIST"                       ,	18,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSTRUN"                      ,	19,	1,	274,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	274,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	4,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	4,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PLC0RMSK"                    ,	0,	32,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC1RMSK"                    ,	32,	32,	277,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC2RMSK"                    ,	0,	32,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILCRMSK"                     ,	32,	32,	278,	"R/W",	0,	0,	0ull,	0ull},
+	{"OOB1EN"                      ,	0,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB2EN"                      ,	1,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB3EN"                      ,	2,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TSECEN"                    ,	3,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TDEDEN"                    ,	4,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DSECEN"                    ,	5,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDEDEN"                    ,	6,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKENA"                      ,	7,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCK2ENA"                     ,	8,	1,	279,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	279,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OOB1"                        ,	0,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB2"                        ,	1,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB3"                        ,	2,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TSEC"                      ,	3,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TDED"                      ,	4,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DSEC"                      ,	5,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DDED"                      ,	6,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK"                         ,	7,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK2"                        ,	8,	1,	280,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	4,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	4,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	284,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	11,	285,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	11,	16,	285,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	4,	286,	"R/W",	0,	0,	15ull,	15ull},
+	{"STPARTDIS"                   ,	4,	1,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STENA"                       ,	0,	1,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWBENA"                      ,	1,	1,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	287,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	289,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	289,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	289,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	290,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	290,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	292,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP0GRP"                      ,	0,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP1GRP"                      ,	2,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP2GRP"                      ,	4,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP3GRP"                      ,	6,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP4GRP"                      ,	8,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP5GRP"                      ,	10,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP6GRP"                      ,	12,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP7GRP"                      ,	14,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP8GRP"                      ,	16,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP9GRP"                      ,	18,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP10GRP"                     ,	20,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP11GRP"                     ,	22,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	294,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK4"                       ,	0,	8,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK5"                       ,	8,	8,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK6"                       ,	16,	8,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK7"                       ,	24,	8,	295,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	295,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK8"                       ,	0,	8,	296,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK9"                       ,	8,	8,	296,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK10"                      ,	16,	8,	296,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK11"                      ,	24,	8,	296,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	297,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	298,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	298,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	298,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	299,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	299,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	300,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	300,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	301,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	302,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	302,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	302,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	11,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"FADRU"                       ,	18,	1,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	303,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	304,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	304,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	305,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	305,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	305,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	306,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	306,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	307,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	308,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	308,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_1024K"                  ,	34,	1,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_512K"                   ,	35,	1,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	309,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	3,	309,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	309,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	310,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	310,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	310,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	10,	310,	"RO",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	310,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	310,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	310,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	310,	"R/W",	0,	0,	0ull,	1ull},
+	{"FADRU"                       ,	28,	1,	310,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RATE"                        ,	0,	8,	311,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_63"               ,	8,	56,	311,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	7,	312,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_7_63"               ,	7,	57,	312,	"RAZ",	1,	1,	0,	0},
+	{"RATE"                        ,	0,	16,	313,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	313,	"RAZ",	1,	1,	0,	0},
+	{"DBG_EN"                      ,	0,	1,	314,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	314,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	315,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	315,	"RAZ",	1,	1,	0,	0},
+	{"POLARITY"                    ,	0,	1,	316,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	316,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	8,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	317,	"RAZ",	1,	1,	0,	0},
+	{"FORMAT"                      ,	0,	4,	318,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	318,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	6,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	319,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	320,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	320,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	32,	321,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	321,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	32,	322,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	322,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	32,	323,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	323,	"RAZ",	1,	1,	0,	0},
+	{"START"                       ,	0,	1,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	324,	"RAZ",	1,	0,	0,	0ull},
+	{"MRD"                         ,	0,	3,	325,	"RO",	1,	0,	0,	0ull},
+	{"MRF"                         ,	3,	1,	325,	"RO",	1,	0,	0,	0ull},
+	{"MWC"                         ,	4,	1,	325,	"RO",	1,	0,	0,	0ull},
+	{"MWD"                         ,	5,	3,	325,	"RO",	1,	0,	0,	0ull},
+	{"MWF"                         ,	8,	1,	325,	"RO",	1,	0,	0,	0ull},
+	{"CSRE2D"                      ,	9,	1,	325,	"RO",	1,	0,	0,	0ull},
+	{"CSRD2E"                      ,	10,	1,	325,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	325,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL_DAT"                    ,	0,	5,	326,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_11"               ,	5,	7,	326,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	326,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	326,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	326,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	326,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	327,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	327,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	327,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	327,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	11,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	327,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	327,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	327,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	327,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	327,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	327,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	327,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	327,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	328,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	328,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEQUENCE"                    ,	10,	3,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLEPOWER"                   ,	13,	3,	328,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	16,	4,	328,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	20,	1,	328,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_63"              ,	21,	43,	328,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	329,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	329,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	330,	"RAZ",	1,	1,	0,	0},
+	{"DCLK90_VLU"                  ,	0,	5,	331,	"R/W",	0,	1,	0ull,	0},
+	{"DCLK90_LD"                   ,	5,	1,	331,	"R/W",	0,	1,	0ull,	0},
+	{"DCLK90_BYP"                  ,	6,	1,	331,	"R/W",	0,	1,	0ull,	0},
+	{"OFF90_ENA"                   ,	7,	1,	331,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	331,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	332,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	332,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	332,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	332,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	332,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	332,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	332,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	332,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	332,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	332,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	333,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	333,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	333,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	0,	5,	334,	"R/W",	0,	1,	0ull,	0},
+	{"DLL90_ENA"                   ,	5,	1,	334,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	6,	1,	334,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	7,	1,	334,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	334,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	335,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	335,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	335,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	335,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	335,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	336,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	337,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	337,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	338,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	338,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	339,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	339,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	340,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	340,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	340,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	340,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	340,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	340,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	340,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	340,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	340,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	340,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	341,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	341,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	341,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	341,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	341,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	341,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	341,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	341,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	341,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	342,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	342,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	343,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	344,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	344,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	345,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	345,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	345,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	345,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	345,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	345,	"R/W",	0,	0,	1ull,	0ull},
+	{"FASTEN_N"                    ,	28,	1,	345,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_63"              ,	29,	35,	345,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	346,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	346,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_21"               ,	2,	20,	346,	"RAZ",	1,	1,	0,	0},
+	{"DDR__PCTL"                   ,	22,	5,	346,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	27,	5,	346,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	346,	"RAZ",	1,	1,	0,	0},
+	{"BNK"                         ,	0,	3,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	347,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COL"                         ,	4,	12,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW"                         ,	16,	16,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"PATTERN"                     ,	32,	8,	347,	"R/W",	0,	0,	170ull,	170ull},
+	{"RANKMASK"                    ,	40,	4,	347,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	347,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE"                        ,	0,	4,	348,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	348,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	16,	16,	348,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	348,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	4,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	8,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	12,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	16,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	20,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	24,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	28,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	32,	4,	349,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	36,	2,	349,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	349,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL"                        ,	0,	5,	350,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	350,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	350,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	350,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	350,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	350,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	351,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	351,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	352,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	352,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	352,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	352,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	352,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WODT_D2_R0"                  ,	0,	8,	353,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	8,	8,	353,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	16,	8,	353,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	24,	8,	353,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	353,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NCBI"                        ,	0,	1,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA"                         ,	2,	1,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	3,	1,	354,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	354,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	355,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	5,	5,	355,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	355,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	356,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	356,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	356,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	357,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	357,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	357,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	358,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	358,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	358,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	359,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	359,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	359,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	359,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	360,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	360,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	360,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	361,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	361,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	362,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	362,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	363,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	363,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	363,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	363,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	364,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_8"                ,	0,	9,	365,	"RAZ",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	365,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	365,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	365,	"RO",	1,	1,	0,	0},
+	{"DMACK_P2"                    ,	13,	1,	365,	"RO",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	365,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	365,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	365,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	366,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	366,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	366,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	366,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	366,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	366,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	366,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	367,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	367,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	367,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	368,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	368,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	368,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	368,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	368,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	369,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	370,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	370,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	371,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	371,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	12,	372,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_15"              ,	12,	4,	372,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	372,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	372,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	372,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	372,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	372,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	372,	"RO",	1,	1,	0,	0},
+	{"NOKASU"                      ,	29,	1,	372,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_31"              ,	30,	2,	372,	"RAZ",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	372,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	372,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	372,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	373,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	373,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	373,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	373,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	373,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	373,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	373,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	373,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	374,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	374,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	374,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	374,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	375,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	376,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	376,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	376,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	377,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	377,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	378,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	378,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	378,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	378,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	378,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	378,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	379,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	379,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	379,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	379,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	379,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	380,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	380,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	381,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	381,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	3,	382,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_3_63"               ,	3,	61,	382,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	383,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	383,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	383,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	383,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	383,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	383,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	383,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	383,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	384,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	384,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	384,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	384,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	384,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	384,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	384,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	384,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	385,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	385,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	385,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	386,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	386,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	386,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	387,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	387,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	388,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	388,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	389,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	389,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	390,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	390,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	390,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	390,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	390,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	390,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	390,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	391,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	392,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	392,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	392,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	392,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	392,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	392,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	392,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	393,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	393,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	393,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	393,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	394,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	394,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	394,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	395,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	395,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	395,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	395,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	395,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	395,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	395,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	395,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	395,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	396,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	397,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	397,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	397,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	397,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	397,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	397,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	397,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	397,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	397,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	398,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	398,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	399,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	399,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	400,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	400,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	400,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	400,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	401,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	402,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	402,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	403,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	403,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	404,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	404,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	404,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	404,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	405,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	405,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	406,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	406,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	407,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	407,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	408,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	408,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	409,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	409,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	410,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	410,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	411,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	411,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	411,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	411,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	411,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	411,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	412,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	413,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	5,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	413,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	413,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	414,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	415,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	416,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	417,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	33,	417,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	417,	"RAZ",	1,	1,	0,	0},
+	{"ISIZE"                       ,	40,	20,	417,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	417,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	418,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	418,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	418,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	418,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	419,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	419,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	419,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	419,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	420,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	421,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	422,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	33,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	422,	"RAZ",	1,	1,	0,	0},
+	{"OSIZE"                       ,	40,	20,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	422,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	423,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	423,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	423,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	423,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	424,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	424,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	425,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	425,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	425,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	425,	"RAZ",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF4"                        ,	2,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF3"                        ,	3,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF2"                        ,	4,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF1"                        ,	5,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF0"                        ,	6,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM1"                        ,	7,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM0"                        ,	8,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P1"                     ,	9,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_CO"                     ,	19,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_NO"                     ,	20,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_PO"                     ,	21,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_CO"                     ,	22,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_NO"                     ,	23,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_PO"                     ,	24,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P1"                      ,	25,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D4_PST"                      ,	31,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_PST"                      ,	32,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_PST"                      ,	33,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_PST"                      ,	34,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_PST"                      ,	35,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	426,	"RAZ",	1,	1,	0,	0},
+	{"DS_MEM"                      ,	40,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D4_MEM"                      ,	41,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_MEM"                      ,	42,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_MEM"                      ,	43,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_MEM"                      ,	44,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_MEM"                      ,	45,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_POP1"                    ,	46,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_POP0"                    ,	47,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_49"              ,	48,	2,	426,	"RAZ",	1,	1,	0,	0},
+	{"PKT_POF"                     ,	50,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PFM"                     ,	51,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_IMEM"                    ,	52,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_SL"                     ,	53,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_ID"                     ,	54,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_CNT"                    ,	55,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_IM"                     ,	56,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_INT"                    ,	57,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PIF"                     ,	58,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PCR_GIM"                     ,	59,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_60_62"              ,	60,	3,	426,	"RAZ",	1,	1,	0,	0},
+	{"PKT_RDF"                     ,	63,	1,	426,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_BLK"                     ,	0,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_GL"                      ,	1,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_GD"                      ,	2,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PSC_P1"                      ,	3,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PSC_P0"                      ,	4,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_RD"                      ,	5,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"NWE_WR1"                     ,	6,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"NWE_WR0"                     ,	7,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"NWE_ST"                      ,	8,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"NRD_ST"                      ,	9,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_ERR"                     ,	10,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_ST1"                     ,	11,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_ST0"                     ,	12,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_TAG"                     ,	13,	1,	427,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	427,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	428,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	428,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	428,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	428,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	428,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	428,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	428,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	428,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	428,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	428,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	428,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	428,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	428,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	428,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	428,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	429,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	429,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	429,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	429,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	429,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	429,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	429,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	429,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	429,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	429,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	429,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	430,	"RO",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	8,	1,	430,	"RO",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	9,	4,	430,	"R/W",	0,	0,	15ull,	15ull},
+	{"ARB"                         ,	13,	1,	430,	"R/W",	0,	0,	0ull,	1ull},
+	{"LNK_RST"                     ,	14,	1,	430,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	15,	1,	430,	"R/W",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	430,	"R/W",	0,	0,	0ull,	32ull},
+	{"P0_NTAGS"                    ,	32,	6,	430,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	38,	6,	430,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_44_63"              ,	44,	20,	430,	"RAZ",	1,	1,	0,	0},
+	{"C0_B0_D"                     ,	0,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_WI_D"                     ,	1,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_B0_D"                     ,	2,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_WI_D"                     ,	3,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_B1_S"                     ,	4,	3,	431,	"R/W",	0,	0,	1ull,	1ull},
+	{"C1_B1_S"                     ,	7,	3,	431,	"R/W",	0,	0,	1ull,	1ull},
+	{"C0_W_FLT"                    ,	10,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_W_FLT"                    ,	11,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRRS"                        ,	12,	3,	431,	"R/W",	0,	0,	2ull,	2ull},
+	{"MPS"                         ,	15,	1,	431,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	431,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	432,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	432,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	432,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	432,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	432,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	433,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	433,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	433,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	23,	2,	433,	"RO",	1,	1,	0,	0},
+	{"QLM3_SPD"                    ,	25,	2,	433,	"RO",	1,	1,	0,	0},
+	{"QLM0_REV_LANES"              ,	27,	1,	433,	"RO",	1,	1,	0,	0},
+	{"QLM2_REV_LANES"              ,	28,	1,	433,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	433,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	434,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	434,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	435,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	435,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	435,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	436,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	436,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	437,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	437,	"R/W",	0,	1,	0ull,	0},
+	{"IDLE"                        ,	36,	1,	437,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_37_63"              ,	37,	27,	437,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	438,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	438,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	439,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	439,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	32,	440,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	440,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0"                        ,	0,	32,	441,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1"                        ,	32,	32,	441,	"R/W",	0,	1,	0ull,	0},
+	{"CSIZE"                       ,	0,	14,	442,	"R/W",	0,	1,	0ull,	0},
+	{"O_MODE"                      ,	14,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	442,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	442,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	442,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	442,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	442,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA0_ENB"                    ,	34,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_ENB"                    ,	35,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2_ENB"                    ,	36,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3_ENB"                    ,	37,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4_ENB"                    ,	38,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_32B_M"                     ,	39,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	442,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	443,	"RAZ",	1,	1,	0,	0},
+	{"DMA0_CNT"                    ,	8,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	443,	"RAZ",	1,	1,	0,	0},
+	{"DMA1_CNT"                    ,	16,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	443,	"RAZ",	1,	1,	0,	0},
+	{"DMA2_CNT"                    ,	24,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_29_31"              ,	29,	3,	443,	"RAZ",	1,	1,	0,	0},
+	{"DMA3_CNT"                    ,	32,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	443,	"RAZ",	1,	1,	0,	0},
+	{"DMA4_CNT"                    ,	40,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	443,	"RAZ",	1,	1,	0,	0},
+	{"PKT_CNT"                     ,	48,	5,	443,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	443,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ARB"                     ,	63,	1,	443,	"R/W",	0,	1,	1ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_CPL"                    ,	1,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"PINS_ERR"                    ,	2,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"POP_ERR"                     ,	3,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDI_ERR"                     ,	4,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"PGL_ERR"                     ,	5,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RDLK"                     ,	6,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RDLK"                     ,	7,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_BP"                      ,	8,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"POUT_ERR"                    ,	9,	1,	444,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	444,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_CPL"                    ,	1,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"PINS_ERR"                    ,	2,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"POP_ERR"                     ,	3,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDI_ERR"                     ,	4,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"PGL_ERR"                     ,	5,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RDLK"                     ,	6,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RDLK"                     ,	7,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_BP"                      ,	8,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"POUT_ERR"                    ,	9,	1,	445,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	445,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_CPL"                    ,	1,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	2,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	3,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	4,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	5,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_RDLK"                     ,	6,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RDLK"                     ,	7,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	8,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	9,	1,	446,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	446,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4DBO"                     ,	8,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0FI"                      ,	9,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_ER"                     ,	20,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_DR"                     ,	22,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_ER"                     ,	27,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_DR"                     ,	29,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_A"                       ,	61,	1,	447,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_62_62"              ,	62,	1,	447,	"RAZ",	0,	1,	0ull,	0},
+	{"MIO_INTA"                    ,	63,	1,	447,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_RTO"                     ,	0,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4DBO"                     ,	8,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0FI"                      ,	9,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_ER"                     ,	20,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_DR"                     ,	22,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_ER"                     ,	27,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_DR"                     ,	29,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	448,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_A"                       ,	61,	1,	448,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	448,	"RAZ",	0,	1,	0ull,	0},
+	{"PSLDBOF"                     ,	0,	6,	449,	"RO",	0,	1,	0ull,	0},
+	{"PIDBOF"                      ,	6,	6,	449,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	449,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA4DBO"                     ,	8,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0FI"                      ,	9,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	15,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	16,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	17,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	18,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_ER"                     ,	20,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS0_DR"                     ,	22,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_ER"                     ,	27,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS1_DR"                     ,	29,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INT_A"                       ,	61,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	450,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	450,	"RO",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	451,	"RAZ",	1,	1,	0,	0},
+	{"DMA0FI"                      ,	9,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_18"              ,	15,	4,	451,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_ER"                     ,	20,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_DR"                     ,	22,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_ER"                     ,	27,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_DR"                     ,	29,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"INT_A"                       ,	61,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	451,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	451,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	452,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	453,	"RO",	0,	1,	0ull,	0},
+	{"TIMER"                       ,	0,	10,	454,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	454,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	454,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	30,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	31,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	32,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	33,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	455,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	2,	455,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	41,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	455,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	456,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	457,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	458,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	459,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	460,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	463,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	464,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	464,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	464,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	468,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	473,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	473,	"RAZ",	1,	1,	0,	0},
+	{"P0_PCNT"                     ,	0,	8,	474,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	474,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	474,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	474,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	474,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	474,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_48_63"              ,	48,	16,	474,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	475,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	475,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	476,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	476,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	476,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	477,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	477,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	478,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	478,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	478,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	479,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	479,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	479,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	480,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	481,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	481,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	482,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	483,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	483,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	483,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	483,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	483,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_0_5"                ,	0,	6,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_27"              ,	22,	6,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	484,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	484,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	484,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	485,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	485,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	486,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	487,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	488,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	489,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	489,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	490,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	491,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	492,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	493,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	493,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	494,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	494,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	495,	"RAZ",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	496,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	496,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	497,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	498,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	498,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	498,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	498,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	498,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	498,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_23_63"              ,	23,	41,	498,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	499,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	500,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	501,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	501,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	502,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	502,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	503,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	503,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	504,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	505,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	505,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	506,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	506,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	507,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	508,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	508,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	509,	"R/W",	0,	1,	0ull,	0},
+	{"BSIZE"                       ,	0,	16,	510,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	510,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	510,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	0,	32,	511,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	511,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	512,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	512,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	513,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	513,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	514,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	514,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"NPEI"                        ,	3,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	15,	1,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASXPCS0"                     ,	22,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"ASXPCS1"                     ,	23,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_27"              ,	24,	4,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	28,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC1"                        ,	29,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	515,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	515,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	516,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	517,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	517,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	517,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	517,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	518,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	518,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	518,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	518,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	518,	"RO",	0,	1,	1ull,	0},
+	{"NPEI"                        ,	47,	1,	518,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	518,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	519,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	519,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	519,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	519,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	519,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	520,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	520,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	520,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	520,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	521,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_1"                ,	0,	2,	522,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	2,	46,	522,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	522,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	522,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	523,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	524,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	525,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	525,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	526,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	526,	"RO/WRSL",	0,	0,	80ull,	80ull},
+	{"ISAE"                        ,	0,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	527,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	527,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	527,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	527,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	528,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	528,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	528,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	528,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	529,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	529,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	530,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	530,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	530,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	530,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	531,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	531,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	532,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	533,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	534,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	534,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	534,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	534,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	534,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	535,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	535,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	536,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	537,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	538,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	538,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	538,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	538,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	539,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	539,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_6"                ,	0,	7,	540,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	7,	25,	540,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	541,	"WORSL",	0,	0,	127ull,	127ull},
+	{"CISP"                        ,	0,	32,	542,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	543,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	543,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	544,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	545,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	545,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"CP"                          ,	0,	8,	546,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	546,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	547,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	547,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	547,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	548,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	548,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	548,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	548,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	548,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	548,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	548,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	548,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	548,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	549,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	549,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	549,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	549,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	549,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	549,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	550,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	550,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	550,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	550,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	550,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	551,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	551,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	552,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	553,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	554,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	554,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	554,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	554,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	554,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	554,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	555,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	555,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	555,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	555,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	555,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	555,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	555,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	555,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	555,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	556,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	556,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	556,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	556,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	556,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	556,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	556,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	556,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	556,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	556,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	556,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	557,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	557,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	557,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	557,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	557,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	557,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	557,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	557,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	558,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	558,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	558,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	558,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	558,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	558,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	558,	"RAZ",	1,	1,	0,	0},
+	{"ABP"                         ,	0,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	559,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIC"                         ,	8,	2,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCC"                         ,	10,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	560,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	560,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	560,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	560,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	560,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	560,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"EMIS"                        ,	23,	1,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	560,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	560,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	561,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	561,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	561,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	562,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	563,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	564,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	565,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	566,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	567,	"RO",	0,	0,	1ull,	0ull},
+	{"CV"                          ,	16,	4,	567,	"RO",	0,	0,	1ull,	0ull},
+	{"NCO"                         ,	20,	12,	567,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	568,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	568,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	568,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	568,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	568,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	569,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	569,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	569,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	570,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	570,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	570,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	570,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	570,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	570,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	570,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	570,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	571,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	571,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	571,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	572,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	572,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	572,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	572,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	573,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	573,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	573,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	574,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	578,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	578,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	579,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	580,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	580,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	580,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	580,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	581,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	581,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	581,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	581,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	581,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	581,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	582,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	582,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	582,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	582,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	582,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_24"              ,	22,	3,	582,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	582,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	582,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	583,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	583,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	584,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	584,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	584,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	584,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	584,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	584,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	585,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	585,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	586,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	587,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	588,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	589,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	590,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	591,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	592,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	593,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	593,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	593,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	593,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	595,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	595,	"RO/WRSL",	0,	0,	35ull,	35ull},
+	{"RESERVED_20_20"              ,	20,	1,	595,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	595,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	595,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	595,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	595,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	596,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	596,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	596,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	596,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	596,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	597,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	597,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	597,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	597,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	597,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	598,	"RO/WRSL",	0,	0,	331ull,	331ull},
+	{"RESERVED_14_15"              ,	14,	2,	598,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	598,	"RO/WRSL",	0,	0,	41ull,	41ull},
+	{"RESERVED_26_31"              ,	26,	6,	598,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	599,	"RO/WRSL",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	599,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	599,	"RO/WRSL",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	599,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	600,	"RO/WRSL",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	600,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	600,	"RO/WRSL",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	600,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	601,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	603,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	603,	"R/W",	0,	0,	80ull,	80ull},
+	{"ISAE"                        ,	0,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	604,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	604,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	604,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	604,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	604,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	604,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	604,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	604,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	604,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	605,	"R/W",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	605,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	605,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	606,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	607,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	608,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	609,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	609,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	609,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	610,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	610,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	610,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	610,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	610,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	610,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	610,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	610,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	610,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	610,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	610,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	610,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	610,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	611,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	611,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	611,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	611,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	612,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	612,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	612,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	612,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	612,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	613,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	614,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	615,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	615,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	616,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	616,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	617,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	618,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	618,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	618,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	618,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	618,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	619,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	619,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	619,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	619,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	620,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	620,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	620,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	620,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	620,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	620,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	620,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	620,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	620,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	621,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	621,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	621,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	621,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	622,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	624,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	625,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	625,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	625,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	625,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	626,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	626,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	626,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	626,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	626,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	627,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	627,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	627,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	627,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	627,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	627,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	627,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	627,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	627,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	627,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	628,	"R/W",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	628,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	628,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	628,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	628,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	628,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	628,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	628,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	628,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	629,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	629,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	629,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	629,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	629,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	629,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	629,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	629,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	629,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	629,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	629,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	631,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	631,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	631,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	631,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	631,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	631,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	631,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	631,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	632,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	632,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	632,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	632,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	633,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	633,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	634,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	634,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	635,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	636,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	637,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	638,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	639,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	640,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	640,	"RO",	0,	0,	1ull,	1ull},
+	{"NCO"                         ,	20,	12,	640,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	641,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	641,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	641,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	641,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	642,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	642,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	642,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	643,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	643,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	643,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	643,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	643,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	643,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	643,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	643,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	644,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	644,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	644,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	645,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	645,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	645,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	645,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	646,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	646,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	646,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	651,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	651,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	652,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	652,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	652,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	653,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	654,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	654,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	655,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	656,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	656,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	656,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	656,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	656,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	657,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	657,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	657,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	657,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	657,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	658,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	658,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	658,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	658,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	658,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_24"              ,	22,	3,	658,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	658,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	659,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	659,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	660,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	660,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	660,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	660,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	660,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	660,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	661,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	661,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	662,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	662,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	662,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	663,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	665,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	666,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	666,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	667,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	667,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	668,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	669,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	669,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	670,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	670,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	670,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	670,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	671,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	671,	"R/W",	0,	0,	35ull,	35ull},
+	{"RESERVED_20_20"              ,	20,	1,	671,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	671,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	671,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	671,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	672,	"R/W",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	672,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	672,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	672,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	672,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	673,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	673,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_20_20"              ,	20,	1,	673,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	673,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	673,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	674,	"R/W",	0,	0,	331ull,	331ull},
+	{"RESERVED_14_15"              ,	14,	2,	674,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	674,	"R/W",	0,	0,	41ull,	41ull},
+	{"RESERVED_26_31"              ,	26,	6,	674,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	675,	"R/W",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	675,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	675,	"R/W",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	675,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	676,	"R/W",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	676,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	676,	"R/W",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	676,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	677,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	678,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	679,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	679,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	679,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	679,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	679,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	679,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	679,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	680,	"RAZ",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	680,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	680,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	680,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	681,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	681,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	681,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	681,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	682,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	682,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	683,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	683,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	684,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	684,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	685,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	685,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	686,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	686,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	687,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	687,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	687,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	688,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	688,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	688,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	688,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	688,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	688,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	689,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	689,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	689,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	689,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	689,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	689,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	689,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	689,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	690,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	690,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	691,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	691,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	691,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	692,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	692,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	692,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	692,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	692,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	692,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	692,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	692,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	693,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	693,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	693,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	693,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	693,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	693,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	693,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	694,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	694,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	695,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	695,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	696,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	696,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	696,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	696,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	696,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	696,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	696,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	697,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	698,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	698,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	698,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	698,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	698,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	699,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	699,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	699,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	699,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	699,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	699,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	699,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	699,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	699,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	699,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	700,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	700,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	701,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	701,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	701,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	701,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	701,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	701,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	701,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	702,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	702,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	702,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	702,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	702,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	702,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	702,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	703,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	703,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	704,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	704,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	704,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	705,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	705,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	705,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	705,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	705,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	706,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	706,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	707,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	707,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	707,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	707,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	708,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	708,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	708,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	708,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	708,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	708,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	708,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	708,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	709,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	709,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	710,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	710,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	710,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	710,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	710,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA4"                     ,	3,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	4,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	5,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	6,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	7,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	8,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"PTLP_OR"                     ,	9,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"NTLP_OR"                     ,	10,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"CTLP_OR"                     ,	11,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA5"                     ,	12,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	711,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"RSL_P2E"                     ,	6,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	7,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_P2E"                     ,	8,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_RSL"                     ,	9,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	10,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	11,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	12,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"CTO_P2E"                     ,	13,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	712,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	713,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	713,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	714,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	714,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	715,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	715,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	716,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	716,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	716,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	716,	"RAZ",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	13,	2,	716,	"RO",	1,	1,	0,	0},
+	{"PBUS"                        ,	15,	8,	716,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	23,	5,	716,	"RO",	1,	1,	0,	0},
+	{"RESERVED_28_63"              ,	28,	36,	716,	"RAZ",	1,	1,	0,	0},
+	{"PCIERST"                     ,	0,	1,	717,	"RO",	0,	0,	0ull,	0ull},
+	{"PCLK_RUN"                    ,	1,	1,	717,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	717,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	718,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	719,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	720,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	720,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	721,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	721,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	722,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	722,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_38"               ,	0,	39,	723,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	39,	25,	723,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	724,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	724,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	725,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	725,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"NPEI_P"                      ,	0,	8,	726,	"R/W",	0,	0,	128ull,	128ull},
+	{"NPEI_NP"                     ,	8,	8,	726,	"R/W",	0,	0,	16ull,	16ull},
+	{"NPEI_CPL"                    ,	16,	8,	726,	"R/W",	0,	0,	128ull,	128ull},
+	{"PESC_P"                      ,	24,	8,	726,	"R/W",	0,	0,	128ull,	128ull},
+	{"PESC_NP"                     ,	32,	8,	726,	"R/W",	0,	0,	16ull,	16ull},
+	{"PESC_CPL"                    ,	40,	8,	726,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	726,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	726,	"RAZ",	1,	1,	0,	0},
+	{"LOWATER"                     ,	0,	5,	727,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_5_7"                ,	5,	3,	727,	"RAZ",	0,	1,	0ull,	0},
+	{"HIWATER"                     ,	8,	5,	727,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_13_62"              ,	13,	50,	727,	"RAZ",	0,	1,	0ull,	0},
+	{"BCKPRS"                      ,	63,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	18,	728,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	728,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	729,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	729,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	730,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	732,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	732,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	732,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	733,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	733,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	733,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	733,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	733,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	734,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	734,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	734,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	734,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	734,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_23"              ,	21,	3,	734,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	734,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	735,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	735,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	735,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	735,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	735,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	735,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	736,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRCERR"                      ,	1,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BCKPRS"                      ,	2,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	737,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	737,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	738,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	739,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	739,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	739,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	739,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	739,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	739,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	739,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	739,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	740,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	741,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	741,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	742,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	742,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	742,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	742,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	743,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	743,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	743,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	743,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	744,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	745,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	746,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	746,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	747,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	748,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	748,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	749,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	749,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	750,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	750,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	751,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	751,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	752,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	752,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	753,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	753,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	754,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	754,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	755,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	755,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	756,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	756,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	757,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	757,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	758,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	758,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	759,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	759,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	760,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	760,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	761,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	761,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	762,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	762,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	763,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	763,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	763,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	764,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	764,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	765,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	765,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	766,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	766,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	766,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	766,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	767,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	767,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	767,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	767,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	767,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	768,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	768,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	768,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	768,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	769,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	769,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	769,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	769,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	769,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	769,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	769,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	769,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	770,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	770,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	770,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	770,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	771,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	771,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	771,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	771,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	771,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	772,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	773,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	773,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	773,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	773,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	773,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	774,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	775,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	775,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	775,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	775,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	775,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	775,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	775,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	775,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	775,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	775,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	775,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	775,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	775,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	776,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	776,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	776,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	776,	"RAZ",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	0,	8,	777,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	777,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	777,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	777,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	777,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	777,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	777,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	777,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	777,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	777,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	777,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	777,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	777,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	778,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	778,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	778,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	778,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	778,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	778,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	779,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	779,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	779,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	779,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	779,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	779,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	779,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	779,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	779,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	780,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	780,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	780,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	780,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	781,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	781,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	781,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	781,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	781,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	781,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	781,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	782,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	782,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	782,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	783,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	783,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_PKT"                    ,	8,	24,	783,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	783,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	783,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	784,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	784,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_LIM"                    ,	8,	24,	784,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	784,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	785,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	785,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	785,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	785,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	785,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	785,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	785,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	785,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	785,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	786,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	786,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	786,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	786,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	786,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	787,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	787,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	787,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	787,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	787,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	787,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	787,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	787,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	787,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	787,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	788,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	788,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	64,	789,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	790,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	792,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE5"                     ,	20,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE6"                     ,	24,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE7"                     ,	28,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE8"                     ,	32,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	793,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_40_63"              ,	40,	24,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	10,	794,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	795,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	795,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	795,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	796,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	796,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	797,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	797,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	798,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	799,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	799,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	800,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	800,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	801,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR0"                        ,	0,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR1"                        ,	1,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND0"                       ,	2,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND1"                       ,	3,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	4,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	5,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	6,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	7,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT"                         ,	8,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	9,	1,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	802,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	12,	802,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	802,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	803,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	803,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	804,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	804,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	804,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	804,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	804,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	804,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	804,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	804,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	804,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	805,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	805,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	806,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	806,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	807,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	807,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	808,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	808,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	809,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	809,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	810,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	810,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	12,	811,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	811,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	812,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	812,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	813,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	813,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	814,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	814,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	814,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	815,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	815,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	815,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	815,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	815,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	11,	816,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	816,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	11,	816,	"R/W",	0,	1,	2047ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	816,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	12,	816,	"RO",	0,	1,	2027ull,	0},
+	{"BUF_CNT"                     ,	36,	12,	816,	"RO",	0,	1,	0ull,	0},
+	{"DES_CNT"                     ,	48,	12,	816,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	816,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	817,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	817,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	818,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	818,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	819,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	819,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	820,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	820,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	820,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	12,	821,	"RO",	0,	1,	0ull,	0},
+	{"DS_CNT"                      ,	12,	12,	821,	"RO",	0,	1,	0ull,	0},
+	{"TC_CNT"                      ,	24,	4,	821,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	821,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	822,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	822,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	822,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	822,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	822,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	11,	823,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	823,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	11,	823,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_23"              ,	23,	1,	823,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	823,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	823,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	823,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	824,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	824,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	825,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	826,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	827,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	828,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	828,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	828,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	828,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	828,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	33,	829,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	829,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	829,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	829,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	829,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	830,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	830,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	830,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	831,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	831,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	831,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	831,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	831,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	831,	"RAZ",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	831,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	831,	"RAZ",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	831,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	831,	"RAZ",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	832,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	833,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	833,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	833,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	834,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	834,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	834,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	834,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	834,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	834,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	834,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	15,	835,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	835,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OWORDP"                      ,	0,	64,	836,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	837,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	838,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	839,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	839,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	839,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	839,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FPACREDS"                    ,	12,	2,	839,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	839,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	839,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	839,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	839,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	839,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	839,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	839,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	839,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	839,	"RO",	1,	1,	0,	0},
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+	{"CNT"                         ,	0,	15,	841,	"RO",	1,	1,	0,	0},
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+	{"EXP_ENT"                     ,	4,	1,	849,	"R/W",	0,	0,	0ull,	0ull},
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+	{"NUM_BUCKETS"                 ,	4,	20,	858,	"R/W",	0,	0,	0ull,	0ull},
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+	{"INTERVAL"                    ,	4,	22,	859,	"R/W",	0,	0,	0ull,	0ull},
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+	{"POOL"                        ,	39,	3,	859,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RESERVED_43_63"              ,	43,	21,	859,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	860,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	860,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	860,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	860,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	861,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	861,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	862,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	862,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"MASK"                        ,	0,	16,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	863,	"RAZ",	1,	0,	0,	0ull},
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+	{"INC"                         ,	8,	8,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	864,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	865,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
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+	{"MCD0_ENA"                    ,	13,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	866,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	866,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	867,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	867,	"RO",	0,	0,	0ull,	0ull},
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+	{"RPTR"                        ,	12,	10,	868,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	868,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	24,	40,	868,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	869,	"R/W",	0,	1,	0ull,	0},
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+	{"RESERVED_36_63"              ,	36,	28,	870,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"PL2"                         ,	1,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBLD8"                      ,	10,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBLD32"                     ,	12,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	871,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	871,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"ILLEGAL3"                    ,	1,	2,	872,	"R/W",	0,	0,	0ull,	3ull},
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+	{"RNG"                         ,	8,	1,	872,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	872,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	872,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	872,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	872,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"PKI"                         ,	16,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	873,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"CIU_THR"                     ,	1,	1,	874,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	874,	"R/W1C",	0,	0,	0ull,	0ull},
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+	{"RESERVED_4_63"               ,	4,	60,	874,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_36_63"              ,	36,	28,	876,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"RESERVED_36_63"              ,	36,	28,	877,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"PL2"                         ,	1,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
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+	{"STT"                         ,	9,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	878,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	878,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"ILLEGAL3"                    ,	1,	2,	879,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	879,	"R/W",	0,	0,	0ull,	1ull},
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+	{"FPA"                         ,	5,	1,	879,	"R/W",	0,	0,	0ull,	1ull},
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+	{"ZIP"                         ,	7,	1,	879,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	879,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	879,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	879,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	879,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	879,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	880,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	881,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	881,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	882,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	883,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	883,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	884,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	884,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	884,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	884,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	884,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	885,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	885,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INEPINT"                     ,	0,	16,	886,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	886,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	888,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	888,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	888,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	888,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	888,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	889,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	889,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	889,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	889,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	889,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	889,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	889,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	889,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	890,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	890,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	890,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	890,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	890,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	890,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	890,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	890,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	891,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	891,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	891,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	892,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	892,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	893,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	893,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	894,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	894,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	894,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	894,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	894,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	894,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	894,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	894,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	895,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	895,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	895,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	895,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	895,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	895,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	896,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	897,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	897,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	898,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	898,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	899,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	899,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	899,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	899,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	899,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	899,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	900,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	901,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	902,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	904,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	904,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	904,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	904,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	904,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	905,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	906,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	906,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	906,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	906,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	906,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	906,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	906,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	906,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	906,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	906,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	906,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	906,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	906,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	907,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	907,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	907,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	907,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	907,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	907,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	907,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	908,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	908,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	908,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	908,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	908,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	908,	"RO",	0,	0,	1ull,	1ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	908,	"RO",	0,	0,	1ull,	1ull},
+	{"AVALIDFLTR"                  ,	22,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"BVALIDFLTR"                  ,	23,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"SESSENDFLTR"                 ,	24,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDEDTRFIFO"                 ,	25,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVMODINEND"              ,	26,	4,	908,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_30_31"              ,	30,	2,	908,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	909,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	909,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	909,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	909,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	909,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	910,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	910,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	910,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	910,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	910,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	911,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	911,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	912,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	912,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	912,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	912,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	913,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	913,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	913,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	913,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	913,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	913,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	913,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	914,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	914,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	914,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	914,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	914,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	915,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	915,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	915,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	915,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	916,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	916,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	917,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	918,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	918,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	918,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	918,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	918,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	919,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	919,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	919,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	919,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	919,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	919,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	920,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	921,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	922,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	922,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	922,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	922,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	922,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	922,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	922,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	922,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	922,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	923,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	923,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	924,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	924,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	925,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	925,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	926,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	926,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	927,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	927,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	928,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	928,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	929,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	930,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	931,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	931,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	932,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	932,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	933,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	933,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	933,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	933,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	933,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	933,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	933,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	934,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	934,	"R/W",	0,	0,	256ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	935,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	935,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	935,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	937,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	937,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	937,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	937,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	937,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	937,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"N2UF_BIS"                    ,	3,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"E2HC_BIS"                    ,	4,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NF_BIS"                    ,	5,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NC_BIS"                    ,	6,	1,	938,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	938,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	939,	"R/W",	0,	0,	4ull,	0ull},
+	{"HRST"                        ,	3,	1,	939,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	939,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	939,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	939,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	939,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	939,	"R/W",	0,	0,	2ull,	0ull},
+	{"P_COM_ON"                    ,	13,	1,	939,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_RTYPE"                     ,	14,	2,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	939,	"RAZ",	1,	1,	0,	0},
+	{"HCLK_RST"                    ,	17,	1,	939,	"R/W",	0,	0,	1ull,	1ull},
+	{"DIVIDE2"                     ,	18,	2,	939,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_63"              ,	20,	44,	939,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	940,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	940,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	941,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	941,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	942,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	942,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	943,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	943,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	944,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	944,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	945,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	945,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	946,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	946,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	947,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	947,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	948,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	948,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	949,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	949,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	950,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	950,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	951,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	951,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	952,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	952,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	953,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	953,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	954,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	954,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	955,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	955,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	956,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	956,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	957,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	957,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	957,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	957,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	957,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	957,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	957,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	958,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	958,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	958,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	959,	"RAZ",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	959,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	959,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	959,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_22"              ,	19,	4,	960,	"RAZ",	0,	0,	0ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	960,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	960,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	960,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXPREEMPHASISTUNE"           ,	30,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	31,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	960,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	960,	"RO",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	38,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	39,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	40,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRVVBUS"                     ,	41,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	42,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGDISABLE"                  ,	43,	1,	960,	"R/W",	0,	0,	1ull,	1ull},
+	{"OTGTUNE"                     ,	44,	3,	960,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMPDISTUNE"                 ,	47,	3,	960,	"R/W",	0,	0,	2ull,	2ull},
+	{"SQRXTUNE"                    ,	50,	3,	960,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXHSXVTUNE"                  ,	53,	2,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFSLSTUNE"                  ,	55,	4,	960,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXVREFTUNE"                  ,	59,	4,	960,	"R/W",	0,	0,	7ull,	7ull},
+	{"TXRISETUNE"                  ,	63,	1,	960,	"R/W",	0,	0,	0ull,	0ull},
+	{"ZIP_CTL"                     ,	0,	4,	961,	"RO",	1,	0,	0,	0ull},
+	{"ZIP_CORE"                    ,	4,	27,	961,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	961,	"RAZ",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	33,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	33,	13,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	46,	3,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	49,	9,	962,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_58_63"              ,	58,	6,	962,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	963,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FORCECLK"                    ,	1,	1,	963,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	963,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DISABLED"                    ,	0,	1,	964,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	964,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTXSIZE"                     ,	8,	12,	964,	"RO",	0,	0,	1536ull,	1536ull},
+	{"ONFSIZE"                     ,	20,	12,	964,	"RO",	0,	0,	512ull,	512ull},
+	{"DEPTH"                       ,	32,	16,	964,	"RO",	0,	0,	31744ull,	31744ull},
+	{"RESERVED_48_63"              ,	48,	16,	964,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	14,	965,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	965,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	966,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	966,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	0,	1,	967,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	967,	"RAZ",	1,	0,	0,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn50xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_asx#_gmii_rx_clk_set"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	2,	0},
+	{"cvmx_asx#_gmii_rx_dat_set"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	2},
+	{"cvmx_asx#_int_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	6,	4},
+	{"cvmx_asx#_int_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	6,	10},
+	{"cvmx_asx#_mii_rx_dat_set"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	2,	16},
+	{"cvmx_asx#_prt_loop"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	5,	4,	18},
+	{"cvmx_asx#_rx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	2,	22},
+	{"cvmx_asx#_rx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	9,	2,	24},
+	{"cvmx_asx#_tx_clk_set#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	2,	26},
+	{"cvmx_asx#_tx_comp_byp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	13,	6,	28},
+	{"cvmx_asx#_tx_hi_water#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	2,	34},
+	{"cvmx_asx#_tx_prt_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	17,	2,	36},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	18,	2,	38},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	19,	2,	40},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	20,	2,	42},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	21,	2,	44},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	22,	19,	46},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	27,	2,	65},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	32,	19,	67},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	34,	2,	86},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	36,	19,	88},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	41,	19,	107},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	43,	2,	126},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	44,	2,	128},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	46,	2,	130},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	48,	2,	132},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	49,	2,	134},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	50,	2,	136},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	51,	1,	138},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	53,	3,	139},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	54,	2,	142},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	55,	4,	144},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	56,	2,	148},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	57,	3,	150},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	61,	7,	153},
+	{"cvmx_dbg_data"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	63,	6,	160},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	6,	166},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	65,	7,	172},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	29,	179},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	67,	29,	208},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	237},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	76,	2,	239},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	84,	3,	241},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	85,	3,	244},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	86,	2,	247},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	249},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	88,	8,	251},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	259},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	90,	4,	261},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	265},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	92,	5,	267},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	1,	272},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	98,	1,	273},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	1,	274},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	104,	1,	275},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	1,	276},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	110,	1,	277},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	278},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	116,	4,	280},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	2,	284},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	11,	286},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	125,	11,	297},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	128,	2,	308},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	131,	21,	310},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	134,	21,	331},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	137,	2,	352},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	140,	2,	354},
+	{"cvmx_gmx#_rx#_rx_inbnd"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	143,	4,	356},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	146,	2,	360},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	149,	2,	362},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	152,	2,	364},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	155,	2,	366},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	158,	2,	368},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	161,	2,	370},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	164,	2,	372},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	167,	2,	374},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	170,	2,	376},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	173,	2,	378},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	176,	4,	380},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	179,	2,	384},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	182,	2,	386},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	185,	2,	388},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	188,	4,	390},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	189,	2,	394},
+	{"cvmx_gmx#_rx_tx_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	190,	4,	396},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	191,	2,	400},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	194,	3,	402},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	195,	5,	405},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	198,	2,	410},
+	{"cvmx_gmx#_tx#_clk"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	201,	2,	412},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	204,	3,	414},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	207,	2,	417},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	210,	2,	419},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	213,	2,	421},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	216,	2,	423},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	219,	2,	425},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	222,	2,	427},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	225,	2,	429},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	228,	2,	431},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	231,	2,	433},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	234,	2,	435},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	237,	2,	437},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	240,	2,	439},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	243,	2,	441},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	246,	2,	443},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	249,	2,	445},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	2,	447},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	255,	2,	449},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	258,	2,	451},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	261,	2,	453},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	264,	2,	455},
+	{"cvmx_gmx#_tx_clk_msk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	265,	2,	457},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	267,	2,	459},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	268,	2,	461},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	269,	3,	463},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	270,	10,	466},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	271,	10,	476},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	272,	2,	486},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	273,	2,	488},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	274,	6,	490},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	275,	2,	496},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	276,	2,	498},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	277,	2,	500},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	278,	7,	502},
+	{"cvmx_gpio_boot_ena"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	294,	3,	509},
+	{"cvmx_gpio_dbg_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	295,	2,	512},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	296,	2,	514},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	297,	2,	516},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	298,	2,	518},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	299,	2,	520},
+	{"cvmx_gpio_xbit_cfg#"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	300,	6,	522},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	308,	19,	528},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	309,	6,	547},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	310,	3,	553},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	311,	5,	556},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	312,	5,	561},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	313,	1,	566},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	314,	1,	567},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	315,	7,	568},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	316,	7,	575},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	317,	5,	582},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	318,	5,	587},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	319,	1,	592},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	320,	1,	593},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	321,	2,	594},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	322,	2,	596},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	323,	2,	598},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	324,	2,	600},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	325,	17,	602},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	326,	2,	619},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	327,	1,	621},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	328,	15,	622},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	329,	11,	637},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	330,	11,	648},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	331,	2,	659},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	332,	2,	661},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	333,	2,	663},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	334,	3,	665},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	339,	2,	668},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	344,	6,	670},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	345,	5,	676},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	346,	6,	681},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	347,	7,	687},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	348,	2,	694},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	356,	2,	696},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	357,	3,	698},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	358,	5,	701},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	366,	3,	706},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	367,	2,	709},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	368,	2,	711},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	369,	2,	713},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	370,	8,	715},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	371,	5,	723},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	372,	8,	728},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	373,	12,	736},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	374,	9,	748},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	375,	5,	757},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	376,	4,	762},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	377,	2,	766},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	378,	16,	768},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	379,	19,	784},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	380,	3,	803},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	381,	4,	806},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	382,	2,	810},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	386,	17,	812},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	387,	3,	829},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	388,	2,	832},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	389,	3,	834},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	390,	2,	837},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	391,	2,	839},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	392,	2,	841},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	393,	7,	843},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	394,	5,	850},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	395,	3,	855},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	396,	3,	858},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	397,	2,	861},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	398,	2,	863},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	399,	2,	865},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	400,	6,	867},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	401,	14,	873},
+	{"cvmx_lmc#_bist_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	402,	2,	887},
+	{"cvmx_lmc#_bist_result"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	403,	6,	889},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	404,	7,	895},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	405,	20,	902},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	406,	5,	922},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	407,	2,	927},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	2,	929},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	409,	18,	931},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	410,	6,	949},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	411,	5,	955},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	412,	5,	960},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	413,	6,	965},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	414,	2,	971},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	415,	2,	973},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	14,	975},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	417,	10,	989},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	418,	2,	999},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	419,	2,	1001},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	420,	13,	1003},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	421,	6,	1016},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	422,	6,	1022},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	423,	9,	1028},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	424,	9,	1037},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	425,	7,	1046},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	426,	3,	1053},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	427,	3,	1056},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	428,	3,	1059},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	429,	3,	1062},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	430,	5,	1065},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	432,	1,	1070},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	433,	12,	1071},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	441,	13,	1083},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	449,	4,	1096},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	450,	1,	1100},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	454,	2,	1101},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	455,	2,	1103},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	456,	13,	1105},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	457,	8,	1118},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	458,	4,	1126},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	459,	1,	1130},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	460,	3,	1131},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	461,	2,	1134},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	462,	6,	1136},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	463,	8,	1142},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	4,	1150},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	465,	2,	1154},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	466,	2,	1156},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	467,	13,	1158},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	468,	12,	1171},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	469,	3,	1183},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	470,	3,	1186},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	2,	1189},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	473,	2,	1191},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	475,	2,	1193},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	477,	7,	1195},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	479,	2,	1202},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	481,	7,	1204},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	483,	4,	1211},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	485,	8,	1215},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	487,	9,	1223},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	489,	7,	1232},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	491,	9,	1239},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	493,	2,	1248},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	495,	2,	1250},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	497,	4,	1252},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	499,	2,	1256},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	501,	2,	1258},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	503,	2,	1260},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	505,	4,	1262},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	507,	2,	1266},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	509,	2,	1268},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	511,	2,	1270},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	513,	2,	1272},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	515,	2,	1274},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	517,	2,	1276},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	519,	6,	1278},
+	{"cvmx_mpi_cfg"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	521,	14,	1284},
+	{"cvmx_mpi_dat#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	522,	2,	1298},
+	{"cvmx_mpi_sts"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	531,	4,	1300},
+	{"cvmx_mpi_tx"                 ,	CVMX_CSR_DB_TYPE_NCB,	64,	532,	6,	1304},
+	{"cvmx_npi_base_addr_input#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	533,	2,	1310},
+	{"cvmx_npi_base_addr_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	535,	2,	1312},
+	{"cvmx_npi_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	537,	20,	1314},
+	{"cvmx_npi_buff_size_output#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	538,	3,	1334},
+	{"cvmx_npi_comp_ctl"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	540,	3,	1337},
+	{"cvmx_npi_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	541,	18,	1340},
+	{"cvmx_npi_dbg_select"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	542,	2,	1358},
+	{"cvmx_npi_dma_control"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	543,	13,	1360},
+	{"cvmx_npi_dma_highp_counts"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	544,	3,	1373},
+	{"cvmx_npi_dma_highp_naddr"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	545,	3,	1376},
+	{"cvmx_npi_dma_lowp_counts"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	546,	3,	1379},
+	{"cvmx_npi_dma_lowp_naddr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	547,	3,	1382},
+	{"cvmx_npi_highp_dbell"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	548,	2,	1385},
+	{"cvmx_npi_highp_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	549,	2,	1387},
+	{"cvmx_npi_input_control"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	550,	10,	1389},
+	{"cvmx_npi_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	551,	54,	1399},
+	{"cvmx_npi_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	552,	54,	1453},
+	{"cvmx_npi_lowp_dbell"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	553,	2,	1507},
+	{"cvmx_npi_lowp_ibuff_saddr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	554,	2,	1509},
+	{"cvmx_npi_mem_access_subid#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	555,	10,	1511},
+	{"cvmx_npi_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	559,	1,	1521},
+	{"cvmx_npi_num_desc_output#"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	560,	2,	1522},
+	{"cvmx_npi_output_control"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	562,	25,	1524},
+	{"cvmx_npi_p#_dbpair_addr"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	563,	3,	1549},
+	{"cvmx_npi_p#_instr_addr"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	565,	2,	1552},
+	{"cvmx_npi_p#_instr_cnts"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	567,	3,	1554},
+	{"cvmx_npi_p#_pair_cnts"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	569,	3,	1557},
+	{"cvmx_npi_pci_burst_size"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	571,	3,	1560},
+	{"cvmx_npi_pci_int_arb_cfg"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	572,	7,	1563},
+	{"cvmx_npi_pci_read_cmd"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	573,	2,	1570},
+	{"cvmx_npi_port32_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	574,	13,	1572},
+	{"cvmx_npi_port33_instr_hdr"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	575,	13,	1585},
+	{"cvmx_npi_port_bp_control"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	576,	3,	1598},
+	{"cvmx_npi_rsl_int_blocks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	577,	29,	1601},
+	{"cvmx_npi_size_input#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	578,	2,	1630},
+	{"cvmx_npi_win_read_to"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	580,	2,	1632},
+	{"cvmx_pci_bar1_index#"        ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	581,	5,	1634},
+	{"cvmx_pci_bist_reg"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	613,	11,	1639},
+	{"cvmx_pci_cfg00"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	614,	2,	1650},
+	{"cvmx_pci_cfg01"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	615,	24,	1652},
+	{"cvmx_pci_cfg02"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	616,	2,	1676},
+	{"cvmx_pci_cfg03"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	617,	7,	1678},
+	{"cvmx_pci_cfg04"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	618,	5,	1685},
+	{"cvmx_pci_cfg05"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	619,	1,	1690},
+	{"cvmx_pci_cfg06"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	620,	5,	1691},
+	{"cvmx_pci_cfg07"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	621,	1,	1696},
+	{"cvmx_pci_cfg08"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	622,	4,	1697},
+	{"cvmx_pci_cfg09"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	623,	2,	1701},
+	{"cvmx_pci_cfg10"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	624,	1,	1703},
+	{"cvmx_pci_cfg11"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	625,	2,	1704},
+	{"cvmx_pci_cfg12"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	626,	4,	1706},
+	{"cvmx_pci_cfg13"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	627,	2,	1710},
+	{"cvmx_pci_cfg15"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	628,	4,	1712},
+	{"cvmx_pci_cfg16"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	629,	16,	1716},
+	{"cvmx_pci_cfg17"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	630,	1,	1732},
+	{"cvmx_pci_cfg18"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	631,	1,	1733},
+	{"cvmx_pci_cfg19"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	632,	18,	1734},
+	{"cvmx_pci_cfg20"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	633,	1,	1752},
+	{"cvmx_pci_cfg21"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	634,	1,	1753},
+	{"cvmx_pci_cfg22"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	635,	7,	1754},
+	{"cvmx_pci_cfg56"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	636,	7,	1761},
+	{"cvmx_pci_cfg57"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	637,	13,	1768},
+	{"cvmx_pci_cfg58"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	638,	10,	1781},
+	{"cvmx_pci_cfg59"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	639,	10,	1791},
+	{"cvmx_pci_cfg60"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	640,	7,	1801},
+	{"cvmx_pci_cfg61"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	641,	2,	1808},
+	{"cvmx_pci_cfg62"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	642,	1,	1810},
+	{"cvmx_pci_cfg63"              ,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	643,	2,	1811},
+	{"cvmx_pci_cnt_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	644,	6,	1813},
+	{"cvmx_pci_ctl_status_2"       ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	645,	22,	1819},
+	{"cvmx_pci_dbell#"             ,	CVMX_CSR_DB_TYPE_PCI,	32,	646,	2,	1841},
+	{"cvmx_pci_dma_cnt#"           ,	CVMX_CSR_DB_TYPE_PCI,	32,	648,	1,	1843},
+	{"cvmx_pci_dma_int_lev#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	650,	1,	1844},
+	{"cvmx_pci_dma_time#"          ,	CVMX_CSR_DB_TYPE_PCI,	32,	652,	1,	1845},
+	{"cvmx_pci_instr_count#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	654,	1,	1846},
+	{"cvmx_pci_int_enb"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	656,	33,	1847},
+	{"cvmx_pci_int_enb2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	657,	33,	1880},
+	{"cvmx_pci_int_sum"            ,	CVMX_CSR_DB_TYPE_PCI,	64,	658,	33,	1913},
+	{"cvmx_pci_int_sum2"           ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	659,	33,	1946},
+	{"cvmx_pci_msi_rcv"            ,	CVMX_CSR_DB_TYPE_PCI,	32,	660,	2,	1979},
+	{"cvmx_pci_pkt_credits#"       ,	CVMX_CSR_DB_TYPE_PCI,	32,	661,	2,	1981},
+	{"cvmx_pci_pkts_sent#"         ,	CVMX_CSR_DB_TYPE_PCI,	32,	663,	1,	1983},
+	{"cvmx_pci_pkts_sent_int_lev#" ,	CVMX_CSR_DB_TYPE_PCI,	32,	665,	1,	1984},
+	{"cvmx_pci_pkts_sent_time#"    ,	CVMX_CSR_DB_TYPE_PCI,	32,	667,	1,	1985},
+	{"cvmx_pci_read_cmd_6"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	669,	3,	1986},
+	{"cvmx_pci_read_cmd_c"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	670,	3,	1989},
+	{"cvmx_pci_read_cmd_e"         ,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	671,	3,	1992},
+	{"cvmx_pci_read_timeout"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	672,	3,	1995},
+	{"cvmx_pci_scm_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	673,	2,	1998},
+	{"cvmx_pci_tsr_reg"            ,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	674,	2,	2000},
+	{"cvmx_pci_win_rd_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	675,	4,	2002},
+	{"cvmx_pci_win_rd_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	676,	1,	2006},
+	{"cvmx_pci_win_wr_addr"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	677,	4,	2007},
+	{"cvmx_pci_win_wr_data"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	678,	1,	2011},
+	{"cvmx_pci_win_wr_mask"        ,	CVMX_CSR_DB_TYPE_PCI,	64,	679,	2,	2012},
+	{"cvmx_pcm#_dma_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	680,	12,	2014},
+	{"cvmx_pcm#_int_ena"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	684,	9,	2026},
+	{"cvmx_pcm#_int_sum"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	688,	9,	2035},
+	{"cvmx_pcm#_rxaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	692,	2,	2044},
+	{"cvmx_pcm#_rxcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	696,	2,	2046},
+	{"cvmx_pcm#_rxmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	700,	1,	2048},
+	{"cvmx_pcm#_rxmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	704,	1,	2049},
+	{"cvmx_pcm#_rxmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	708,	1,	2050},
+	{"cvmx_pcm#_rxmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	712,	1,	2051},
+	{"cvmx_pcm#_rxmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	716,	1,	2052},
+	{"cvmx_pcm#_rxmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	720,	1,	2053},
+	{"cvmx_pcm#_rxmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	724,	1,	2054},
+	{"cvmx_pcm#_rxmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	728,	1,	2055},
+	{"cvmx_pcm#_rxstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	732,	3,	2056},
+	{"cvmx_pcm#_tdm_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	736,	6,	2059},
+	{"cvmx_pcm#_tdm_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	740,	1,	2065},
+	{"cvmx_pcm#_txaddr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	744,	3,	2066},
+	{"cvmx_pcm#_txcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	748,	2,	2069},
+	{"cvmx_pcm#_txmsk0"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	752,	1,	2071},
+	{"cvmx_pcm#_txmsk1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	756,	1,	2072},
+	{"cvmx_pcm#_txmsk2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	760,	1,	2073},
+	{"cvmx_pcm#_txmsk3"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	764,	1,	2074},
+	{"cvmx_pcm#_txmsk4"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	768,	1,	2075},
+	{"cvmx_pcm#_txmsk5"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	772,	1,	2076},
+	{"cvmx_pcm#_txmsk6"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	776,	1,	2077},
+	{"cvmx_pcm#_txmsk7"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	780,	1,	2078},
+	{"cvmx_pcm#_txstart"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	784,	3,	2079},
+	{"cvmx_pcm_clk#_cfg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	788,	12,	2082},
+	{"cvmx_pcm_clk#_dbg"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	790,	1,	2094},
+	{"cvmx_pcm_clk#_gen"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	792,	3,	2095},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	794,	2,	2098},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	795,	4,	2100},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	799,	3,	2104},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	801,	8,	2107},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	16,	2115},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	13,	2131},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	13,	2144},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	805,	2,	2157},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	806,	27,	2159},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	811,	25,	2186},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	816,	2,	2211},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	880,	2,	2213},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	888,	9,	2215},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	896,	2,	2224},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	897,	2,	2226},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	898,	2,	2228},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	903,	2,	2230},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	908,	2,	2232},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	913,	2,	2234},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	918,	2,	2236},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	923,	2,	2238},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	928,	2,	2240},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	933,	2,	2242},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	938,	2,	2244},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	943,	2,	2246},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	948,	2,	2248},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	949,	2,	2250},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	954,	2,	2252},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	959,	2,	2254},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	964,	2,	2256},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1028,	2,	2258},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1029,	3,	2260},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1030,	3,	2263},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1031,	2,	2266},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1032,	2,	2268},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1033,	4,	2270},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1034,	5,	2274},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1035,	4,	2279},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1036,	8,	2283},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1037,	4,	2291},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1038,	5,	2295},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1039,	5,	2300},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1040,	1,	2305},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1041,	18,	2306},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1042,	4,	2324},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1043,	2,	2328},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1044,	6,	2330},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1045,	7,	2336},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1046,	4,	2343},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1047,	9,	2347},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1048,	5,	2356},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1049,	15,	2361},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1050,	4,	2376},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1051,	1,	2380},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1052,	1,	2381},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1053,	1,	2382},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1054,	1,	2383},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1055,	4,	2384},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1056,	5,	2388},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1057,	3,	2393},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1058,	4,	2396},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1059,	2,	2400},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1060,	3,	2402},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1061,	3,	2405},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1062,	12,	2408},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1063,	2,	2420},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1064,	13,	2422},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1065,	3,	2435},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1066,	2,	2438},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1074,	2,	2440},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1075,	2,	2442},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1076,	2,	2444},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1077,	2,	2446},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1078,	10,	2448},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1080,	5,	2458},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1088,	10,	2463},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1096,	2,	2473},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1097,	2,	2475},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1098,	2,	2477},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1106,	3,	2479},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1107,	6,	2482},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1123,	5,	2488},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1124,	7,	2493},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1140,	2,	2500},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1156,	3,	2502},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1157,	7,	2505},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1158,	10,	2512},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1159,	6,	2522},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1160,	2,	2528},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1161,	4,	2530},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1162,	4,	2534},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1163,	6,	2538},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1164,	3,	2544},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1165,	5,	2547},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1166,	4,	2552},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1167,	6,	2556},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1168,	4,	2562},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1169,	2,	2566},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1170,	4,	2568},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1171,	2,	2572},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1172,	3,	2574},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1173,	2,	2577},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1174,	2,	2579},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1175,	8,	2581},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1176,	11,	2589},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1177,	15,	2600},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1182,	8,	2615},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1187,	8,	2623},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1188,	4,	2631},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1193,	15,	2635},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1198,	6,	2650},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1203,	6,	2656},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1204,	4,	2662},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1209,	2,	2666},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1213,	6,	2668},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1214,	4,	2674},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1215,	1,	2678},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1216,	1,	2679},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1217,	1,	2680},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1218,	7,	2681},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1219,	1,	2688},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1220,	14,	2689},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1221,	10,	2703},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1222,	14,	2713},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1223,	32,	2727},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1224,	32,	2759},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1225,	2,	2791},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1226,	4,	2793},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1227,	13,	2797},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1228,	10,	2810},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1229,	10,	2820},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1230,	2,	2830},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1231,	6,	2832},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1232,	5,	2838},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1233,	6,	2843},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1234,	5,	2849},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1235,	1,	2854},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1236,	13,	2855},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1237,	2,	2868},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1238,	2,	2870},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1239,	11,	2872},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1247,	3,	2883},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	1248,	12,	2886},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1256,	12,	2898},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1264,	6,	2910},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1272,	4,	2916},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1280,	2,	2920},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1281,	2,	2922},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1282,	15,	2924},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1283,	2,	2939},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1284,	3,	2941},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	1285,	1,	2944},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1293,	6,	2945},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1294,	8,	2951},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1295,	15,	2959},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	1296,	6,	2974},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1297,	2,	2980},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1298,	2,	2982},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1299,	2,	2984},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1300,	2,	2986},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1301,	2,	2988},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1302,	2,	2990},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1303,	2,	2992},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	1304,	2,	2994},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1305,	2,	2996},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1306,	2,	2998},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1307,	2,	3000},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1308,	2,	3002},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1309,	2,	3004},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1310,	2,	3006},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1311,	2,	3008},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	1312,	2,	3010},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1313,	7,	3012},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1314,	34,	3019},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1315,	34,	3053},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1316,	35,	3087},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"ASX0_GMII_RX_CLK_SET"        ,	   0x11800B0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"ASX0_GMII_RX_DAT_SET"        ,	   0x11800B0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"ASX0_INT_EN"                 ,	   0x11800B0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"ASX0_INT_REG"                ,	   0x11800B0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"ASX0_MII_RX_DAT_SET"         ,	   0x11800B0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"ASX0_PRT_LOOP"               ,	   0x11800B0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"ASX0_RX_CLK_SET000"          ,	   0x11800B0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET001"          ,	   0x11800B0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_CLK_SET002"          ,	   0x11800B0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"ASX0_RX_PRT_EN"              ,	   0x11800B0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"ASX0_TX_CLK_SET000"          ,	   0x11800B0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET001"          ,	   0x11800B0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_CLK_SET002"          ,	   0x11800B0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"ASX0_TX_COMP_BYP"            ,	   0x11800B0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"ASX0_TX_HI_WATER000"         ,	   0x11800B0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER001"         ,	   0x11800B0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_HI_WATER002"         ,	   0x11800B0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"ASX0_TX_PRT_EN"              ,	   0x11800B0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	12},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	13},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	14},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	15},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	16},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	17},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	18},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	19},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	20},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	21},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	22},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	23},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	24},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	25},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	26},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	27},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	28},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	29},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	30},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	31},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	32},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	33},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	34},
+	{"DBG_DATA"                    ,	   0x11F00000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	35},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"GMX0_RX000_RX_INBND"         ,	   0x1180008000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_RX001_RX_INBND"         ,	   0x1180008000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_RX002_RX_INBND"         ,	   0x1180008001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	71},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	72},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	73},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	74},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	75},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	76},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	77},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	78},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	79},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	80},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	81},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	82},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	83},
+	{"GMX0_RX_TX_STATUS"           ,	   0x11800080007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	84},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	85},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	86},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	87},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	88},
+	{"GMX0_TX000_CLK"              ,	   0x1180008000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX001_CLK"              ,	   0x1180008000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX002_CLK"              ,	   0x1180008001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	89},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	90},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	91},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	92},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	93},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	94},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	95},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	96},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	97},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_TX_CLK_MSK000"          ,	   0x1180008000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX_CLK_MSK001"          ,	   0x1180008000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	123},
+	{"GPIO_BOOT_ENA"               ,	   0x10700000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	124},
+	{"GPIO_DBG_ENA"                ,	   0x10700000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	125},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	126},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	127},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	128},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	129},
+	{"GPIO_XBIT_CFG16"             ,	   0x1070000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG17"             ,	   0x1070000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG18"             ,	   0x1070000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG19"             ,	   0x1070000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG20"             ,	   0x1070000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG21"             ,	   0x1070000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG22"             ,	   0x1070000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"GPIO_XBIT_CFG23"             ,	   0x1070000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	130},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	145},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	146},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	147},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	148},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	149},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	150},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	151},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	152},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	153},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	154},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	155},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	156},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	157},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	158},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	159},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	160},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	161},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	162},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	163},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	164},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	165},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	166},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	167},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	168},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	169},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	170},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	231},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	232},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	233},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	234},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	235},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	236},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	237},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	238},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	239},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	240},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	241},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	242},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	243},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	244},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	245},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	246},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	247},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	248},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	249},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	250},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	251},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"MPI_CFG"                     ,	   0x1070000001000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	276},
+	{"MPI_DAT0"                    ,	   0x1070000001080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT1"                    ,	   0x1070000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT2"                    ,	   0x1070000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT3"                    ,	   0x1070000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT4"                    ,	   0x10700000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT5"                    ,	   0x10700000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT6"                    ,	   0x10700000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT7"                    ,	   0x10700000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_DAT8"                    ,	   0x10700000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	277},
+	{"MPI_STS"                     ,	   0x1070000001008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	278},
+	{"MPI_TX"                      ,	   0x1070000001010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	279},
+	{"NPI_BASE_ADDR_INPUT0"        ,	   0x11F0000000070ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"NPI_BASE_ADDR_INPUT1"        ,	   0x11F0000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	280},
+	{"NPI_BASE_ADDR_OUTPUT0"       ,	   0x11F00000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"NPI_BASE_ADDR_OUTPUT1"       ,	   0x11F00000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	281},
+	{"NPI_BIST_STATUS"             ,	   0x11F00000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	282},
+	{"NPI_BUFF_SIZE_OUTPUT0"       ,	   0x11F00000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"NPI_BUFF_SIZE_OUTPUT1"       ,	   0x11F00000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	283},
+	{"NPI_COMP_CTL"                ,	   0x11F0000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	284},
+	{"NPI_CTL_STATUS"              ,	   0x11F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	285},
+	{"NPI_DBG_SELECT"              ,	   0x11F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	286},
+	{"NPI_DMA_CONTROL"             ,	   0x11F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	287},
+	{"NPI_DMA_HIGHP_COUNTS"        ,	   0x11F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	288},
+	{"NPI_DMA_HIGHP_NADDR"         ,	   0x11F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	289},
+	{"NPI_DMA_LOWP_COUNTS"         ,	   0x11F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	290},
+	{"NPI_DMA_LOWP_NADDR"          ,	   0x11F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	291},
+	{"NPI_HIGHP_DBELL"             ,	   0x11F0000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	292},
+	{"NPI_HIGHP_IBUFF_SADDR"       ,	   0x11F0000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	293},
+	{"NPI_INPUT_CONTROL"           ,	   0x11F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	294},
+	{"NPI_INT_ENB"                 ,	   0x11F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	295},
+	{"NPI_INT_SUM"                 ,	   0x11F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	296},
+	{"NPI_LOWP_DBELL"              ,	   0x11F0000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	297},
+	{"NPI_LOWP_IBUFF_SADDR"        ,	   0x11F0000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	298},
+	{"NPI_MEM_ACCESS_SUBID3"       ,	   0x11F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MEM_ACCESS_SUBID4"       ,	   0x11F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MEM_ACCESS_SUBID5"       ,	   0x11F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MEM_ACCESS_SUBID6"       ,	   0x11F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	299},
+	{"NPI_MSI_RCV"                 ,	   0x11F0000001190ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	300},
+	{"NPI_NUM_DESC_OUTPUT0"        ,	   0x11F0000000050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_NUM_DESC_OUTPUT1"        ,	   0x11F0000000058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	301},
+	{"NPI_OUTPUT_CONTROL"          ,	   0x11F0000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	302},
+	{"NPI_P0_DBPAIR_ADDR"          ,	   0x11F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_P1_DBPAIR_ADDR"          ,	   0x11F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	303},
+	{"NPI_P0_INSTR_ADDR"           ,	   0x11F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"NPI_P1_INSTR_ADDR"           ,	   0x11F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	304},
+	{"NPI_P0_INSTR_CNTS"           ,	   0x11F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"NPI_P1_INSTR_CNTS"           ,	   0x11F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	305},
+	{"NPI_P0_PAIR_CNTS"            ,	   0x11F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
+	{"NPI_P1_PAIR_CNTS"            ,	   0x11F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	306},
+	{"NPI_PCI_BURST_SIZE"          ,	   0x11F00000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	307},
+	{"NPI_PCI_INT_ARB_CFG"         ,	   0x11F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	308},
+	{"NPI_PCI_READ_CMD"            ,	   0x11F0000000048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	309},
+	{"NPI_PORT32_INSTR_HDR"        ,	   0x11F00000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	310},
+	{"NPI_PORT33_INSTR_HDR"        ,	   0x11F0000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	311},
+	{"NPI_PORT_BP_CONTROL"         ,	   0x11F00000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	312},
+	{"NPI_RSL_INT_BLOCKS"          ,	   0x11F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	313},
+	{"NPI_SIZE_INPUT0"             ,	   0x11F0000000078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_SIZE_INPUT1"             ,	   0x11F0000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	314},
+	{"NPI_WIN_READ_TO"             ,	   0x11F00000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	315},
+	{"PCI_BAR1_INDEX0"             ,	   0x11F0000001100ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX1"             ,	   0x11F0000001104ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX2"             ,	   0x11F0000001108ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX3"             ,	   0x11F000000110Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX4"             ,	   0x11F0000001110ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX5"             ,	   0x11F0000001114ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX6"             ,	   0x11F0000001118ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX7"             ,	   0x11F000000111Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX8"             ,	   0x11F0000001120ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX9"             ,	   0x11F0000001124ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX10"            ,	   0x11F0000001128ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX11"            ,	   0x11F000000112Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX12"            ,	   0x11F0000001130ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX13"            ,	   0x11F0000001134ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX14"            ,	   0x11F0000001138ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX15"            ,	   0x11F000000113Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX16"            ,	   0x11F0000001140ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX17"            ,	   0x11F0000001144ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX18"            ,	   0x11F0000001148ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX19"            ,	   0x11F000000114Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX20"            ,	   0x11F0000001150ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX21"            ,	   0x11F0000001154ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX22"            ,	   0x11F0000001158ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX23"            ,	   0x11F000000115Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX24"            ,	   0x11F0000001160ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX25"            ,	   0x11F0000001164ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX26"            ,	   0x11F0000001168ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX27"            ,	   0x11F000000116Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX28"            ,	   0x11F0000001170ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX29"            ,	   0x11F0000001174ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX30"            ,	   0x11F0000001178ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BAR1_INDEX31"            ,	   0x11F000000117Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	316},
+	{"PCI_BIST_REG"                ,	   0x11F00000011C0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	317},
+	{"PCI_CFG00"                   ,	   0x11F0000001800ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	318},
+	{"PCI_CFG01"                   ,	   0x11F0000001804ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	319},
+	{"PCI_CFG02"                   ,	   0x11F0000001808ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	320},
+	{"PCI_CFG03"                   ,	   0x11F000000180Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	321},
+	{"PCI_CFG04"                   ,	   0x11F0000001810ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	322},
+	{"PCI_CFG05"                   ,	   0x11F0000001814ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	323},
+	{"PCI_CFG06"                   ,	   0x11F0000001818ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	324},
+	{"PCI_CFG07"                   ,	   0x11F000000181Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	325},
+	{"PCI_CFG08"                   ,	   0x11F0000001820ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	326},
+	{"PCI_CFG09"                   ,	   0x11F0000001824ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	327},
+	{"PCI_CFG10"                   ,	   0x11F0000001828ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	328},
+	{"PCI_CFG11"                   ,	   0x11F000000182Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	329},
+	{"PCI_CFG12"                   ,	   0x11F0000001830ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	330},
+	{"PCI_CFG13"                   ,	   0x11F0000001834ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	331},
+	{"PCI_CFG15"                   ,	   0x11F000000183Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	332},
+	{"PCI_CFG16"                   ,	   0x11F0000001840ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	333},
+	{"PCI_CFG17"                   ,	   0x11F0000001844ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	334},
+	{"PCI_CFG18"                   ,	   0x11F0000001848ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	335},
+	{"PCI_CFG19"                   ,	   0x11F000000184Cull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	336},
+	{"PCI_CFG20"                   ,	   0x11F0000001850ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	337},
+	{"PCI_CFG21"                   ,	   0x11F0000001854ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	338},
+	{"PCI_CFG22"                   ,	   0x11F0000001858ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	339},
+	{"PCI_CFG56"                   ,	   0x11F00000018E0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	340},
+	{"PCI_CFG57"                   ,	   0x11F00000018E4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	341},
+	{"PCI_CFG58"                   ,	   0x11F00000018E8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	342},
+	{"PCI_CFG59"                   ,	   0x11F00000018ECull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	343},
+	{"PCI_CFG60"                   ,	   0x11F00000018F0ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	344},
+	{"PCI_CFG61"                   ,	   0x11F00000018F4ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	345},
+	{"PCI_CFG62"                   ,	   0x11F00000018F8ull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	346},
+	{"PCI_CFG63"                   ,	   0x11F00000018FCull,	CVMX_CSR_DB_TYPE_PCICONFIG,	32,	347},
+	{"PCI_CNT_REG"                 ,	   0x11F00000011B8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	348},
+	{"PCI_CTL_STATUS_2"            ,	   0x11F000000118Cull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	349},
+	{"PCI_DBELL0"                  ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
+	{"PCI_DBELL1"                  ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCI,	32,	350},
+	{"PCI_DMA_CNT0"                ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	351},
+	{"PCI_DMA_CNT1"                ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCI,	32,	351},
+	{"PCI_DMA_INT_LEV0"            ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	352},
+	{"PCI_DMA_INT_LEV1"            ,	              0xACull,	CVMX_CSR_DB_TYPE_PCI,	32,	352},
+	{"PCI_DMA_TIME0"               ,	              0xB0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	353},
+	{"PCI_DMA_TIME1"               ,	              0xB4ull,	CVMX_CSR_DB_TYPE_PCI,	32,	353},
+	{"PCI_INSTR_COUNT0"            ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCI,	32,	354},
+	{"PCI_INSTR_COUNT1"            ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	354},
+	{"PCI_INT_ENB"                 ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCI,	64,	355},
+	{"PCI_INT_ENB2"                ,	   0x11F00000011A0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	356},
+	{"PCI_INT_SUM"                 ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCI,	64,	357},
+	{"PCI_INT_SUM2"                ,	   0x11F0000001198ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	358},
+	{"PCI_MSI_RCV"                 ,	              0xF0ull,	CVMX_CSR_DB_TYPE_PCI,	32,	359},
+	{"PCI_PKT_CREDITS0"            ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
+	{"PCI_PKT_CREDITS1"            ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCI,	32,	360},
+	{"PCI_PKTS_SENT0"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCI,	32,	361},
+	{"PCI_PKTS_SENT1"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCI,	32,	361},
+	{"PCI_PKTS_SENT_INT_LEV0"      ,	              0x48ull,	CVMX_CSR_DB_TYPE_PCI,	32,	362},
+	{"PCI_PKTS_SENT_INT_LEV1"      ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCI,	32,	362},
+	{"PCI_PKTS_SENT_TIME0"         ,	              0x4Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	363},
+	{"PCI_PKTS_SENT_TIME1"         ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCI,	32,	363},
+	{"PCI_READ_CMD_6"              ,	   0x11F0000001180ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	364},
+	{"PCI_READ_CMD_C"              ,	   0x11F0000001184ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	365},
+	{"PCI_READ_CMD_E"              ,	   0x11F0000001188ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	32,	366},
+	{"PCI_READ_TIMEOUT"            ,	   0x11F00000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	367},
+	{"PCI_SCM_REG"                 ,	   0x11F00000011A8ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	368},
+	{"PCI_TSR_REG"                 ,	   0x11F00000011B0ull,	CVMX_CSR_DB_TYPE_PCI_NCB,	64,	369},
+	{"PCI_WIN_RD_ADDR"             ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCI,	64,	370},
+	{"PCI_WIN_RD_DATA"             ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCI,	64,	371},
+	{"PCI_WIN_WR_ADDR"             ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCI,	64,	372},
+	{"PCI_WIN_WR_DATA"             ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCI,	64,	373},
+	{"PCI_WIN_WR_MASK"             ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCI,	64,	374},
+	{"PCM0_DMA_CFG"                ,	   0x1070000010018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM1_DMA_CFG"                ,	   0x1070000014018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM2_DMA_CFG"                ,	   0x1070000018018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM3_DMA_CFG"                ,	   0x107000001C018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	375},
+	{"PCM0_INT_ENA"                ,	   0x1070000010020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM1_INT_ENA"                ,	   0x1070000014020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM2_INT_ENA"                ,	   0x1070000018020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM3_INT_ENA"                ,	   0x107000001C020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	376},
+	{"PCM0_INT_SUM"                ,	   0x1070000010028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM1_INT_SUM"                ,	   0x1070000014028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM2_INT_SUM"                ,	   0x1070000018028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM3_INT_SUM"                ,	   0x107000001C028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	377},
+	{"PCM0_RXADDR"                 ,	   0x1070000010068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM1_RXADDR"                 ,	   0x1070000014068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM2_RXADDR"                 ,	   0x1070000018068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM3_RXADDR"                 ,	   0x107000001C068ull,	CVMX_CSR_DB_TYPE_NCB,	64,	378},
+	{"PCM0_RXCNT"                  ,	   0x1070000010060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM1_RXCNT"                  ,	   0x1070000014060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM2_RXCNT"                  ,	   0x1070000018060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM3_RXCNT"                  ,	   0x107000001C060ull,	CVMX_CSR_DB_TYPE_NCB,	64,	379},
+	{"PCM0_RXMSK0"                 ,	   0x10700000100C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM1_RXMSK0"                 ,	   0x10700000140C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM2_RXMSK0"                 ,	   0x10700000180C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM3_RXMSK0"                 ,	   0x107000001C0C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	380},
+	{"PCM0_RXMSK1"                 ,	   0x10700000100C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM1_RXMSK1"                 ,	   0x10700000140C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM2_RXMSK1"                 ,	   0x10700000180C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM3_RXMSK1"                 ,	   0x107000001C0C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	381},
+	{"PCM0_RXMSK2"                 ,	   0x10700000100D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM1_RXMSK2"                 ,	   0x10700000140D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM2_RXMSK2"                 ,	   0x10700000180D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM3_RXMSK2"                 ,	   0x107000001C0D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	382},
+	{"PCM0_RXMSK3"                 ,	   0x10700000100D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM1_RXMSK3"                 ,	   0x10700000140D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM2_RXMSK3"                 ,	   0x10700000180D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM3_RXMSK3"                 ,	   0x107000001C0D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	383},
+	{"PCM0_RXMSK4"                 ,	   0x10700000100E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM1_RXMSK4"                 ,	   0x10700000140E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM2_RXMSK4"                 ,	   0x10700000180E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM3_RXMSK4"                 ,	   0x107000001C0E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	384},
+	{"PCM0_RXMSK5"                 ,	   0x10700000100E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM1_RXMSK5"                 ,	   0x10700000140E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM2_RXMSK5"                 ,	   0x10700000180E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM3_RXMSK5"                 ,	   0x107000001C0E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	385},
+	{"PCM0_RXMSK6"                 ,	   0x10700000100F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM1_RXMSK6"                 ,	   0x10700000140F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM2_RXMSK6"                 ,	   0x10700000180F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM3_RXMSK6"                 ,	   0x107000001C0F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	386},
+	{"PCM0_RXMSK7"                 ,	   0x10700000100F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM1_RXMSK7"                 ,	   0x10700000140F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM2_RXMSK7"                 ,	   0x10700000180F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM3_RXMSK7"                 ,	   0x107000001C0F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	387},
+	{"PCM0_RXSTART"                ,	   0x1070000010058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM1_RXSTART"                ,	   0x1070000014058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM2_RXSTART"                ,	   0x1070000018058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM3_RXSTART"                ,	   0x107000001C058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	388},
+	{"PCM0_TDM_CFG"                ,	   0x1070000010010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM1_TDM_CFG"                ,	   0x1070000014010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM2_TDM_CFG"                ,	   0x1070000018010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM3_TDM_CFG"                ,	   0x107000001C010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	389},
+	{"PCM0_TDM_DBG"                ,	   0x1070000010030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM1_TDM_DBG"                ,	   0x1070000014030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM2_TDM_DBG"                ,	   0x1070000018030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM3_TDM_DBG"                ,	   0x107000001C030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	390},
+	{"PCM0_TXADDR"                 ,	   0x1070000010050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM1_TXADDR"                 ,	   0x1070000014050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM2_TXADDR"                 ,	   0x1070000018050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM3_TXADDR"                 ,	   0x107000001C050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	391},
+	{"PCM0_TXCNT"                  ,	   0x1070000010048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM1_TXCNT"                  ,	   0x1070000014048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM2_TXCNT"                  ,	   0x1070000018048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM3_TXCNT"                  ,	   0x107000001C048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	392},
+	{"PCM0_TXMSK0"                 ,	   0x1070000010080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM1_TXMSK0"                 ,	   0x1070000014080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM2_TXMSK0"                 ,	   0x1070000018080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM3_TXMSK0"                 ,	   0x107000001C080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	393},
+	{"PCM0_TXMSK1"                 ,	   0x1070000010088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM1_TXMSK1"                 ,	   0x1070000014088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM2_TXMSK1"                 ,	   0x1070000018088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM3_TXMSK1"                 ,	   0x107000001C088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	394},
+	{"PCM0_TXMSK2"                 ,	   0x1070000010090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM1_TXMSK2"                 ,	   0x1070000014090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM2_TXMSK2"                 ,	   0x1070000018090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM3_TXMSK2"                 ,	   0x107000001C090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	395},
+	{"PCM0_TXMSK3"                 ,	   0x1070000010098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM1_TXMSK3"                 ,	   0x1070000014098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM2_TXMSK3"                 ,	   0x1070000018098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM3_TXMSK3"                 ,	   0x107000001C098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	396},
+	{"PCM0_TXMSK4"                 ,	   0x10700000100A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM1_TXMSK4"                 ,	   0x10700000140A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM2_TXMSK4"                 ,	   0x10700000180A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM3_TXMSK4"                 ,	   0x107000001C0A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	397},
+	{"PCM0_TXMSK5"                 ,	   0x10700000100A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM1_TXMSK5"                 ,	   0x10700000140A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM2_TXMSK5"                 ,	   0x10700000180A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM3_TXMSK5"                 ,	   0x107000001C0A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	398},
+	{"PCM0_TXMSK6"                 ,	   0x10700000100B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM1_TXMSK6"                 ,	   0x10700000140B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM2_TXMSK6"                 ,	   0x10700000180B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM3_TXMSK6"                 ,	   0x107000001C0B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	399},
+	{"PCM0_TXMSK7"                 ,	   0x10700000100B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM1_TXMSK7"                 ,	   0x10700000140B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM2_TXMSK7"                 ,	   0x10700000180B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM3_TXMSK7"                 ,	   0x107000001C0B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"PCM0_TXSTART"                ,	   0x1070000010040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM1_TXSTART"                ,	   0x1070000014040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM2_TXSTART"                ,	   0x1070000018040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM3_TXSTART"                ,	   0x107000001C040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"PCM_CLK0_CFG"                ,	   0x1070000010000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM_CLK1_CFG"                ,	   0x1070000014000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"PCM_CLK0_DBG"                ,	   0x1070000010038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM_CLK1_DBG"                ,	   0x1070000014038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"PCM_CLK0_GEN"                ,	   0x1070000010008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PCM_CLK1_GEN"                ,	   0x1070000014008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	417},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	418},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	419},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	420},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	421},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	422},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	423},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	424},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	425},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	426},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	427},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	428},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	429},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	430},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	431},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	432},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	433},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	434},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	435},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	436},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	437},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	438},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	439},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	440},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	441},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	442},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	443},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	444},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	445},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	446},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	447},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	448},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	449},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	450},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	451},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	452},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	453},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	454},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	455},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	456},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	457},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	458},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	459},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	460},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	461},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	462},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	463},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	464},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	465},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	466},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	467},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	468},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	469},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	470},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	471},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	472},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	473},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	474},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	475},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	476},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	477},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	478},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	479},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	480},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	481},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	482},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	483},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	484},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	485},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	486},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	487},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	488},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	489},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	490},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	491},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	492},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	493},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	494},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	495},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	496},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	497},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	498},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	499},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	500},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	501},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	502},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	503},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	504},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	505},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	506},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	507},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	508},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	509},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	510},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	511},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	512},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	513},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	514},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	515},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	516},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	517},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	518},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	519},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	520},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	521},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	522},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	523},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	524},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	525},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	526},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	527},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	528},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	529},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	530},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	531},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	532},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	533},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	534},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	535},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	536},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	537},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	538},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	539},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	540},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	541},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	542},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	543},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	544},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	545},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	546},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	547},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	548},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	549},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	550},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	551},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	552},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	553},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	554},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	555},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	556},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	557},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	558},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	559},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	560},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	561},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	562},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	563},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	564},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	565},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	566},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	567},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	568},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	569},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	570},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	571},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	572},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	573},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	574},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	575},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	576},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	577},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	578},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	579},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	580},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"SETTING"                     ,	0,	5,	0,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	0,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	1,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	1,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_3"                ,	3,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"TXPOP"                       ,	4,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	2,	"RAZ",	1,	1,	0,	0},
+	{"TXPSH"                       ,	8,	3,	2,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_11_63"              ,	11,	53,	2,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	0,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"TXPOP"                       ,	4,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"TXPSH"                       ,	8,	3,	3,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	3,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	4,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	4,	"RAZ",	1,	1,	0,	0},
+	{"INT_LOOP"                    ,	0,	3,	5,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	5,	"RAZ",	1,	1,	0,	0},
+	{"EXT_LOOP"                    ,	4,	3,	5,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	5,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	6,	"R/W",	0,	0,	24ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	6,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	3,	7,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	7,	"RAZ",	1,	1,	0,	0},
+	{"SETTING"                     ,	0,	5,	8,	"R/W",	0,	0,	24ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	8,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	9,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	9,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	9,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	9,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	16,	1,	9,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	9,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	3,	10,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	10,	"RAZ",	1,	1,	0,	0},
+	{"PRT_EN"                      ,	0,	3,	11,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	11,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	2,	12,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	12,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	2,	13,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	13,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	2,	14,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	14,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	15,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_47"              ,	47,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	16,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	16,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	2,	17,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	17,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	18,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_47"              ,	47,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	18,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	18,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	2,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	19,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_47"              ,	47,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	20,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	20,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	20,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	20,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_47_47"              ,	47,	1,	21,	"RAZ",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	21,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	21,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	52,	4,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM"                         ,	57,	1,	21,	"RO",	0,	0,	0ull,	0ull},
+	{"MPI"                         ,	58,	1,	21,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_59_63"              ,	59,	5,	21,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	2,	22,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	22,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	23,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	23,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	24,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	24,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	2,	25,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	25,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	26,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	26,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	2,	27,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	27,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	28,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	29,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	1,	29,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	29,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_BIST"                   ,	0,	1,	30,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	30,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	31,	"R/W",	0,	0,	1ull,	0ull},
+	{"NPI"                         ,	1,	1,	31,	"R/W",	0,	0,	0ull,	0ull},
+	{"HOST64"                      ,	2,	1,	31,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	31,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	32,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	32,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	33,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	34,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	34,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	34,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	34,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	35,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	35,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	35,	"RO",	1,	1,	0,	0},
+	{"RESERVED_23_27"              ,	23,	5,	35,	"RAZ",	1,	1,	0,	0},
+	{"PLL_MUL"                     ,	28,	3,	35,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	35,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	36,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	36,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	37,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	37,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	38,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	38,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	39,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	39,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	40,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	40,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	41,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	41,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	42,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	42,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	42,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	43,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	43,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	43,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	44,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	45,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	45,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	46,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	3,	46,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_21"               ,	5,	17,	46,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	3,	46,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_25"              ,	25,	1,	46,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	46,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	46,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	46,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	12,	47,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	47,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	48,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	48,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0MII"                       ,	2,	1,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	48,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	49,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	49,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	50,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	50,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	50,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	50,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	50,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	51,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	52,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	53,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	54,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	55,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	56,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	57,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	57,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	58,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	58,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	58,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	58,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	59,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	59,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	60,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	60,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	60,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"NIBERR"                      ,	9,	1,	60,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	60,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	61,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	61,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	61,	"R/W",	0,	0,	1ull,	1ull},
+	{"NULL_DIS"                    ,	10,	1,	61,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	61,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	62,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	62,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	63,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	63,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	63,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	63,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	63,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NIBERR"                      ,	9,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_LINK"                    ,	16,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_SPD"                     ,	17,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PHY_DUPX"                    ,	18,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	64,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	64,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	65,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	65,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	66,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	66,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	1,	67,	"RO",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	2,	67,	"RO",	0,	1,	0ull,	0},
+	{"DUPLEX"                      ,	3,	1,	67,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	67,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	68,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	69,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	70,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	70,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	71,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	71,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	72,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	72,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	73,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	73,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	74,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	74,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	75,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	75,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	76,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	76,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	77,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	77,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	78,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	78,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	79,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_6_63"               ,	6,	58,	79,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	80,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	80,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	81,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_9_63"               ,	9,	55,	81,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	3,	82,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_15"               ,	3,	13,	82,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	3,	82,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	82,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	83,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_3_63"               ,	3,	61,	83,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	3,	84,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	84,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	3,	84,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	84,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	85,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	85,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	86,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	86,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	86,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	87,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	87,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	87,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	87,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	87,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	88,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	88,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	6,	89,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	89,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	90,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	90,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	90,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	91,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	91,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	92,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	92,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	93,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	93,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	94,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	94,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	95,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	95,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	96,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	96,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	97,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	97,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	98,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	98,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	99,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	99,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	100,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	100,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	101,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	101,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	102,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	103,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	104,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	105,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	106,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	106,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	107,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	107,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	108,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	7,	109,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_7_63"               ,	7,	57,	109,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	3,	110,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	110,	"RAZ",	1,	1,	0,	0},
+	{"MSK"                         ,	0,	1,	111,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	111,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	112,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	112,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	3,	113,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_3_63"               ,	3,	61,	113,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	114,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	114,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	114,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	3,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	3,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	3,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	3,	115,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	115,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKO_NXA"                     ,	0,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	116,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	3,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_7"                ,	5,	3,	116,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	3,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	116,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	3,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	116,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	3,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	116,	"RAZ",	0,	0,	0ull,	0ull},
+	{"JAM"                         ,	0,	8,	117,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	117,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	118,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	118,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	3,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	119,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	3,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	119,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	3,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	119,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DMAC"                        ,	0,	48,	120,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	120,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	121,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	121,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	122,	"R/W",	0,	1,	3ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	122,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	123,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	123,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	124,	"RAZ",	1,	1,	0,	0},
+	{"BOOT_ENA"                    ,	8,	4,	124,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	124,	"RAZ",	1,	1,	0,	0},
+	{"DBG_ENA"                     ,	0,	21,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_63"              ,	21,	43,	125,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	126,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	126,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	24,	127,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	127,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	24,	128,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	128,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	24,	129,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	129,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	130,	"RAZ",	1,	1,	0,	0},
+	{"FIL_CNT"                     ,	4,	4,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	130,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	130,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	131,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	131,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	132,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	132,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	132,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	132,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	133,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	133,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	133,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	134,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	134,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	134,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	134,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	134,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	135,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	135,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	135,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	135,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	135,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	136,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	137,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	138,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	138,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	139,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	139,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	140,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	140,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	140,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	140,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	140,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	141,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	141,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	141,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	141,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	141,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	142,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	143,	"R/W",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	6,	144,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	144,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	145,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	145,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	146,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	146,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	147,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	147,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	148,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	148,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	149,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	149,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	150,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	151,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	151,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	151,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	152,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	152,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	153,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	153,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	154,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	154,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	155,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	155,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	156,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	156,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	157,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	157,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	158,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	158,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	3,	159,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	159,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	159,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	159,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	159,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	159,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	160,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	160,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	160,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	160,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_44_63"              ,	44,	20,	160,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	161,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	161,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	161,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	161,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	161,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	161,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	162,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	162,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	162,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	162,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	162,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	162,	"RO",	0,	0,	8ull,	8ull},
+	{"RESERVED_61_63"              ,	61,	3,	162,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	163,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	163,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	164,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	164,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	165,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	165,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRB_CON"                     ,	0,	32,	166,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	166,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	166,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	166,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	166,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	167,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	167,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	167,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	3,	168,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_63"               ,	3,	61,	168,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	169,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	169,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	170,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	170,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	10,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	171,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	171,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	171,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	172,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	172,	"RO",	0,	0,	0ull,	0ull},
+	{"LRF"                         ,	10,	2,	172,	"RO",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	172,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	172,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	173,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	173,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	174,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	174,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	174,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	174,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	174,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_17"              ,	14,	4,	174,	"RAZ",	1,	1,	0,	0},
+	{"LBIST"                       ,	18,	1,	174,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSTRUN"                      ,	19,	1,	174,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	174,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_9"                ,	7,	3,	175,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	3,	175,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	175,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	176,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	176,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	176,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	176,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	176,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	177,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	177,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	177,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	178,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	178,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	3,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	3,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	179,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	179,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	180,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	180,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	7,	181,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	7,	20,	181,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	181,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	3,	182,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_3"                ,	3,	1,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STPARTDIS"                   ,	4,	1,	182,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	183,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	183,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	184,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	185,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	186,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	186,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	187,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	187,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	188,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	188,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	189,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	189,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	190,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	190,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	191,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	191,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	191,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	191,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	191,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	191,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	8,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_10"               ,	8,	3,	192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	192,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	193,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	194,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	195,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	195,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	196,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	196,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	197,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_64K"                    ,	34,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_32K"                    ,	35,	1,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	198,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	3,	198,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	198,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	199,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	199,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	7,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_20"              ,	18,	3,	199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	199,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	199,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	199,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	199,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	199,	"RAZ",	0,	0,	0ull,	0ull},
+	{"START"                       ,	0,	1,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	200,	"RAZ",	1,	0,	0,	0ull},
+	{"MRD"                         ,	0,	3,	201,	"RO",	1,	0,	0,	0ull},
+	{"MRF"                         ,	3,	1,	201,	"RO",	1,	0,	0,	0ull},
+	{"MWC"                         ,	4,	1,	201,	"RO",	1,	0,	0,	0ull},
+	{"MWD"                         ,	5,	3,	201,	"RO",	1,	0,	0,	0ull},
+	{"MWF"                         ,	8,	1,	201,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	201,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL_DAT"                    ,	0,	5,	202,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_11"               ,	5,	7,	202,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	202,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	202,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	202,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	202,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	202,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	203,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	203,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	203,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	203,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	203,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	203,	"R/W",	0,	0,	1ull,	1ull},
+	{"DRESET"                      ,	11,	1,	203,	"R/W",	0,	0,	1ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	203,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	203,	"R/W",	0,	1,	0ull,	0},
+	{"PLL_BYPASS"                  ,	16,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	203,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	203,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	203,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	203,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	203,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	203,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	203,	"RAZ",	1,	1,	0,	0},
+	{"DATA_LAYOUT"                 ,	0,	2,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	204,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	204,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	204,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	204,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	205,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	206,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	206,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	207,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	207,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	207,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	207,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	207,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	207,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	207,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	207,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	207,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	207,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	208,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	208,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	208,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CS_MASK"                     ,	0,	8,	209,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	209,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	209,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	209,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	209,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	210,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	210,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	211,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	211,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	212,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	212,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	213,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	213,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	214,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	214,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	214,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	214,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	214,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	214,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	214,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	214,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	214,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	214,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	214,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	214,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	214,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	214,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	215,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	215,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	215,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	215,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	215,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	215,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	215,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	215,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMP_BYPASS"                 ,	31,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	215,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	216,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	216,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	217,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	217,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	218,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	218,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	218,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	218,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	218,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	218,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	218,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	218,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	218,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	218,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	218,	"R/W",	0,	0,	1ull,	0ull},
+	{"FASTEN_N"                    ,	28,	1,	218,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	218,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	219,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	219,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_21"               ,	2,	20,	219,	"RAZ",	1,	1,	0,	0},
+	{"DDR__PCTL"                   ,	22,	5,	219,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	27,	5,	219,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	219,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	0,	5,	220,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	220,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	220,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	220,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	220,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	220,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	221,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	221,	"RAZ",	1,	1,	0,	0},
+	{"WODT_LO0"                    ,	0,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO1"                    ,	4,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO2"                    ,	8,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_LO3"                    ,	12,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI0"                    ,	16,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI1"                    ,	20,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI2"                    ,	24,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"WODT_HI3"                    ,	28,	4,	222,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	222,	"RAZ",	1,	1,	0,	0},
+	{"NCBI"                        ,	0,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	2,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_1"                      ,	3,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM_0"                       ,	4,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"PCM_1"                       ,	5,	1,	223,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	223,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	224,	"R/W",	0,	1,	31ull,	0},
+	{"PCTL"                        ,	5,	5,	224,	"R/W",	0,	1,	31ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	224,	"RAZ",	1,	1,	0,	0},
+	{"ADR_ERR"                     ,	0,	1,	225,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	225,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	225,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	226,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	226,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	226,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	227,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	227,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	227,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	228,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	228,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	228,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	228,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	228,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	229,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	230,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	230,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	230,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	230,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	230,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	230,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	230,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	230,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	230,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	230,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	230,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_63"              ,	42,	22,	230,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	231,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	231,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	231,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	231,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	232,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	232,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	232,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	232,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	233,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	234,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	234,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	235,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	235,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	2,	236,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_15"               ,	2,	14,	236,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	236,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	236,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	236,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	236,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	236,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	236,	"RO",	0,	0,	1ull,	1ull},
+	{"NOKASU"                      ,	29,	1,	236,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_31"              ,	30,	2,	236,	"RAZ",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"FUS318"                      ,	33,	1,	236,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	236,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	237,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	237,	"RO",	0,	0,	1ull,	1ull},
+	{"NOZIP"                       ,	25,	1,	237,	"RO",	0,	0,	1ull,	1ull},
+	{"EFUS_IGN"                    ,	26,	1,	237,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	237,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	237,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	237,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	237,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	238,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	238,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	238,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	238,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	239,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	240,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	240,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	240,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	241,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	241,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	242,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	242,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	242,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	242,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	242,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	242,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	7,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	243,	"RAZ",	1,	1,	0,	0},
+	{"EFUSE"                       ,	8,	1,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	243,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	243,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	243,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	243,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	244,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	244,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	245,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	245,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	2,	246,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	246,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	247,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	247,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	247,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	247,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	247,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	247,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	247,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	247,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	247,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	248,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	248,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	248,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	248,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	248,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	248,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	248,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	248,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	248,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	248,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	248,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	248,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	249,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	249,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	249,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	250,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	250,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	250,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	251,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	251,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	252,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	252,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	253,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	253,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	254,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	254,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	254,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	254,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	254,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	254,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	254,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	255,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	255,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	256,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	256,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	256,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	257,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	257,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	257,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	257,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	258,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	258,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	258,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	258,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	258,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	258,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	258,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	258,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	259,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	259,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	259,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	259,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	259,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	259,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	259,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	259,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	259,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	260,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	260,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	260,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	260,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	260,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	260,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	260,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	261,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	261,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	261,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	261,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	261,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	261,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	261,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	261,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	261,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	262,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	262,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	263,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	263,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	264,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	264,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	264,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	264,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	265,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	265,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	266,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	266,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	267,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	267,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	268,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	268,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	268,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	268,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	269,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	269,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	270,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	270,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	271,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	271,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	272,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	272,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	273,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	273,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	274,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	274,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	275,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	275,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	275,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	275,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	275,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	275,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLELO"                      ,	1,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_CONT"                    ,	2,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"WIREOR"                      ,	3,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	4,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_ENA"                     ,	5,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSENA"                       ,	6,	1,	276,	"R/W",	0,	0,	0ull,	1ull},
+	{"CSHI"                        ,	7,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLECLKS"                    ,	8,	2,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRITX"                       ,	10,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"CSLATE"                      ,	11,	1,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	276,	"RAZ",	1,	1,	0,	0},
+	{"CLKDIV"                      ,	16,	13,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	276,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	8,	277,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_8_63"               ,	8,	56,	277,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_7"                ,	1,	7,	278,	"RAZ",	1,	1,	0,	0},
+	{"RXNUM"                       ,	8,	5,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	278,	"RAZ",	1,	1,	0,	0},
+	{"TOTNUM"                      ,	0,	5,	279,	"WO",	1,	0,	0,	2ull},
+	{"RESERVED_5_7"                ,	5,	3,	279,	"RAZ",	1,	1,	0,	0},
+	{"TXNUM"                       ,	8,	5,	279,	"WO",	1,	0,	0,	1ull},
+	{"RESERVED_13_15"              ,	13,	3,	279,	"RAZ",	1,	1,	0,	0},
+	{"LEAVECS"                     ,	16,	1,	279,	"WO",	1,	0,	0,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	279,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	280,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	280,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	281,	"RAZ",	1,	1,	0,	0},
+	{"BADDR"                       ,	3,	61,	281,	"R/W",	0,	1,	0ull,	0},
+	{"DPI_BS"                      ,	0,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PDF_BS"                      ,	1,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"DOB_BS"                      ,	2,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"NUS_BS"                      ,	3,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"POS_BS"                      ,	4,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POF1_BS"                     ,	7,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"POF0_BS"                     ,	8,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PIG_BS"                      ,	9,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PGF_BS"                      ,	10,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RDNL_BS"                     ,	11,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAD_BS"                     ,	12,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PCAC_BS"                     ,	13,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RDN_BS"                      ,	14,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PCN_BS"                      ,	15,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNC_BS"                     ,	16,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RDP_BS"                      ,	17,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF_BS"                      ,	18,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_BS"                      ,	19,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	282,	"RAZ",	1,	1,	0,	0},
+	{"BSIZE"                       ,	0,	16,	283,	"R/W",	0,	1,	1024ull,	0},
+	{"ISIZE"                       ,	16,	7,	283,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	283,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	284,	"R/W",	0,	1,	16ull,	0},
+	{"PCTL"                        ,	5,	5,	284,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	284,	"RAZ",	1,	1,	0,	0},
+	{"TIMER"                       ,	0,	10,	285,	"R/W",	0,	0,	0ull,	50ull},
+	{"RESERVED_10_31"              ,	10,	22,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WORD"                    ,	32,	5,	285,	"R/W",	0,	0,	2ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WAIT_COM"                    ,	40,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_WDIS"                    ,	41,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"INS0_64B"                    ,	42,	1,	285,	"R/W",	0,	1,	0ull,	0},
+	{"INS1_64B"                    ,	43,	1,	285,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_45"              ,	44,	2,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INS0_ENB"                    ,	46,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"INS1_ENB"                    ,	47,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_48_49"              ,	48,	2,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT0_ENB"                    ,	50,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"OUT1_ENB"                    ,	51,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_52_53"              ,	52,	2,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIS_PNIW"                    ,	54,	1,	285,	"R/W",	0,	0,	0ull,	1ull},
+	{"CHIP_REV"                    ,	55,	8,	285,	"RO",	1,	1,	0,	0},
+	{"RESERVED_63_63"              ,	63,	1,	285,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	286,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	286,	"RAZ",	1,	1,	0,	0},
+	{"CSIZE"                       ,	0,	14,	287,	"R/W",	0,	1,	0ull,	0},
+	{"LP_ENB"                      ,	14,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"HP_ENB"                      ,	15,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_MODE"                      ,	16,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	17,	2,	287,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	19,	1,	287,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	20,	1,	287,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	21,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	22,	3,	287,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	25,	9,	287,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	34,	1,	287,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	35,	1,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	287,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	288,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	289,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	289,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	290,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	291,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	4,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	291,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	292,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	293,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	293,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	1,	294,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	294,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	294,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	294,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	294,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	294,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	294,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	294,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_RR"                      ,	22,	1,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	294,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCI_RSL"                     ,	2,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO0_2SML"                    ,	3,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PO1_2SML"                    ,	4,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_RTOUT"                    ,	7,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_RTOUT"                    ,	8,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_10"               ,	9,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_OVERF"                    ,	11,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_OVERF"                    ,	12,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_RTOUT"                    ,	15,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RTOUT"                    ,	16,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_18"              ,	17,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PERR"                     ,	19,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PERR"                     ,	20,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_22"              ,	21,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"G0_RTOUT"                    ,	23,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"G1_RTOUT"                    ,	24,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_25_26"              ,	25,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PPERR"                    ,	27,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PPERR"                    ,	28,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_29_30"              ,	29,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"P0_PTOUT"                    ,	31,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_PTOUT"                    ,	32,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_33_34"              ,	33,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"I0_PPERR"                    ,	35,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"I1_PPERR"                    ,	36,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_37_38"              ,	37,	2,	295,	"RAZ",	0,	0,	0ull,	1ull},
+	{"WIN_RTO"                     ,	39,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_DPERR"                     ,	40,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	41,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_S_E"                     ,	42,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"FCR_A_F"                     ,	43,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_S_E"                     ,	44,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCR_A_F"                     ,	45,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_S_E"                      ,	46,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q2_A_F"                      ,	47,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_S_E"                      ,	48,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q3_A_F"                      ,	49,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_S_E"                     ,	50,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"COM_A_F"                     ,	51,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_S_E"                     ,	52,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PNC_A_F"                     ,	53,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RWX_S_E"                     ,	54,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RDX_S_E"                     ,	55,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_E"                     ,	56,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCF_P_F"                     ,	57,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_E"                     ,	58,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDF_P_F"                     ,	59,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_S_E"                      ,	60,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"Q1_A_F"                      ,	61,	1,	295,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	295,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_RSL"                     ,	2,	1,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"PO0_2SML"                    ,	3,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PO1_2SML"                    ,	4,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_RTOUT"                    ,	7,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_RTOUT"                    ,	8,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_OVERF"                    ,	11,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_OVERF"                    ,	12,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_14"              ,	13,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_RTOUT"                    ,	15,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RTOUT"                    ,	16,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_18"              ,	17,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PERR"                     ,	19,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PERR"                     ,	20,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_22"              ,	21,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"G0_RTOUT"                    ,	23,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"G1_RTOUT"                    ,	24,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_26"              ,	25,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PPERR"                    ,	27,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PPERR"                    ,	28,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_30"              ,	29,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_PTOUT"                    ,	31,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_PTOUT"                    ,	32,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_34"              ,	33,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"I0_PPERR"                    ,	35,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I1_PPERR"                    ,	36,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_38"              ,	37,	2,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WIN_RTO"                     ,	39,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DPERR"                     ,	40,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOBDMA"                      ,	41,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_S_E"                     ,	42,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCR_A_F"                     ,	43,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_S_E"                     ,	44,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCR_A_F"                     ,	45,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_S_E"                      ,	46,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_A_F"                      ,	47,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_S_E"                      ,	48,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_A_F"                      ,	49,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_S_E"                     ,	50,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COM_A_F"                     ,	51,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_S_E"                     ,	52,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PNC_A_F"                     ,	53,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RWX_S_E"                     ,	54,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDX_S_E"                     ,	55,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_E"                     ,	56,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCF_P_F"                     ,	57,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_E"                     ,	58,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDF_P_F"                     ,	59,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_S_E"                      ,	60,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_A_F"                      ,	61,	1,	296,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	296,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	297,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	297,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	0,	36,	298,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	298,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	28,	299,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	28,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	29,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	30,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	31,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	32,	2,	299,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	34,	2,	299,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	36,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"SHORTL"                      ,	37,	1,	299,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	299,	"RAZ",	1,	1,	0,	0},
+	{"INT_VEC"                     ,	0,	64,	300,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	301,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	301,	"RAZ",	1,	1,	0,	0},
+	{"ROR_SL0"                     ,	0,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL0"                     ,	1,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL0"                     ,	2,	2,	302,	"R/W",	0,	1,	0ull,	0},
+	{"ROR_SL1"                     ,	4,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"NSR_SL1"                     ,	5,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"ESR_SL1"                     ,	6,	2,	302,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	302,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPTR_O0"                     ,	16,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"IPTR_O1"                     ,	17,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_18_23"              ,	18,	6,	302,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_CSRM"                     ,	24,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"O1_CSRM"                     ,	25,	1,	302,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_26_27"              ,	26,	2,	302,	"RAZ",	0,	0,	0ull,	0ull},
+	{"O0_RO"                       ,	28,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"O0_NS"                       ,	29,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"O0_ES"                       ,	30,	2,	302,	"R/W",	0,	1,	0ull,	0},
+	{"O1_RO"                       ,	32,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"O1_NS"                       ,	33,	1,	302,	"R/W",	0,	1,	0ull,	0},
+	{"O1_ES"                       ,	34,	2,	302,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_43"              ,	36,	8,	302,	"RAZ",	0,	0,	0ull,	0ull},
+	{"P0_BMODE"                    ,	44,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"P1_BMODE"                    ,	45,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_47"              ,	46,	2,	302,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	48,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	302,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	303,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	2,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_63_63"              ,	63,	1,	303,	"RAZ",	1,	1,	0,	0},
+	{"NADDR"                       ,	0,	61,	304,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	61,	3,	304,	"RO",	0,	0,	0ull,	0ull},
+	{"AVAIL"                       ,	0,	32,	305,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	6,	305,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	305,	"RAZ",	1,	1,	0,	0},
+	{"AVAIL"                       ,	0,	32,	306,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	5,	306,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	306,	"RAZ",	1,	1,	0,	0},
+	{"RD_BRST"                     ,	0,	7,	307,	"R/W",	0,	0,	17ull,	64ull},
+	{"WR_BRST"                     ,	7,	7,	307,	"R/W",	0,	0,	16ull,	64ull},
+	{"RESERVED_14_63"              ,	14,	50,	307,	"RAZ",	1,	1,	0,	0},
+	{"PARK_DEV"                    ,	0,	3,	308,	"R/W",	0,	1,	0ull,	0},
+	{"PARK_MOD"                    ,	3,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	4,	1,	308,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	308,	"RAZ",	1,	1,	0,	0},
+	{"PCI_OVR"                     ,	8,	4,	308,	"R/W",	0,	1,	0ull,	0},
+	{"HOSTMODE"                    ,	12,	1,	308,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	308,	"RAZ",	1,	1,	0,	0},
+	{"CMD_SIZE"                    ,	0,	11,	309,	"R/W",	0,	0,	9ull,	9ull},
+	{"RESERVED_11_63"              ,	11,	53,	309,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	310,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	310,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	310,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	310,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	310,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	310,	"RAZ",	1,	1,	0,	0},
+	{"RSV_A"                       ,	0,	6,	311,	"R/W",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_B"                       ,	13,	1,	311,	"R/W",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_C"                       ,	16,	5,	311,	"R/W",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_D"                       ,	22,	6,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	311,	"R/W",	0,	1,	8ull,	0},
+	{"RSV_E"                       ,	35,	1,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RSV_F"                       ,	38,	5,	311,	"R/W",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	311,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	311,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	4,	312,	"R/W",	0,	0,	15ull,	15ull},
+	{"BP_ON"                       ,	4,	4,	312,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	312,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"NPI"                         ,	3,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC"                         ,	17,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX0"                        ,	22,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"ASX1"                        ,	23,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_27"              ,	24,	4,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	28,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC1"                        ,	29,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	32,	314,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	314,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	315,	"R/W",	0,	0,	0ull,	131072ull},
+	{"RESERVED_32_63"              ,	32,	32,	315,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	316,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	316,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	316,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	316,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	316,	"RAZ",	1,	1,	0,	0},
+	{"DBG2N_BS"                    ,	0,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"DAT2N_BS"                    ,	1,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR2N_BS"                    ,	2,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"RSP2P_BS"                    ,	3,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"CSRR_BS"                     ,	4,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR2P_BS"                    ,	5,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD_BS"                      ,	6,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD0_BS"                     ,	7,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA0_BS"                     ,	8,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"RSP_BS"                      ,	9,	1,	317,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	317,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	318,	"RO",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	318,	"RO",	0,	0,	112ull,	32ull},
+	{"ISAE"                        ,	0,	1,	319,	"RO",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	319,	"R/W",	0,	0,	0ull,	1ull},
+	{"ME"                          ,	2,	1,	319,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCSE"                        ,	3,	1,	319,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	319,	"RO",	0,	0,	0ull,	0ull},
+	{"PEE"                         ,	6,	1,	319,	"R/W",	0,	0,	0ull,	1ull},
+	{"ADS"                         ,	7,	1,	319,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	319,	"R/W",	0,	0,	0ull,	1ull},
+	{"FBBE"                        ,	9,	1,	319,	"R/W",	0,	0,	0ull,	1ull},
+	{"I_DIS"                       ,	10,	1,	319,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	319,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	319,	"RO",	0,	0,	0ull,	0ull},
+	{"CLE"                         ,	20,	1,	319,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	319,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_22"              ,	22,	1,	319,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	319,	"RO",	0,	1,	1ull,	0},
+	{"MDPE"                        ,	24,	1,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	319,	"RO",	0,	0,	1ull,	1ull},
+	{"STA"                         ,	27,	1,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	319,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	320,	"RO",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	8,	24,	320,	"RO",	0,	0,	733184ull,	733184ull},
+	{"CLS"                         ,	0,	8,	321,	"R/W",	0,	1,	0ull,	0},
+	{"LT"                          ,	8,	8,	321,	"R/W",	0,	0,	0ull,	64ull},
+	{"HT"                          ,	16,	8,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"BCOD"                        ,	24,	4,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_29"              ,	28,	2,	321,	"RAZ",	1,	1,	0,	0},
+	{"BRB"                         ,	30,	1,	321,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCAP"                        ,	31,	1,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	322,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	322,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	8,	322,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	12,	20,	322,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	323,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	324,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	324,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	23,	324,	"RO",	0,	0,	0ull,	0ull},
+	{"LBASE"                       ,	27,	5,	324,	"R/W",	0,	1,	0ull,	0},
+	{"HBASE"                       ,	0,	32,	325,	"R/W",	0,	1,	0ull,	0},
+	{"MSPC"                        ,	0,	1,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	326,	"RO",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	326,	"RO",	0,	0,	1ull,	1ull},
+	{"LBASEZ"                      ,	4,	28,	326,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASEZ"                      ,	0,	7,	327,	"RO",	0,	0,	0ull,	0ull},
+	{"HBASE"                       ,	7,	25,	327,	"R/W",	0,	1,	0ull,	0},
+	{"CISP"                        ,	0,	32,	328,	"RO",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	329,	"RO",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	329,	"RO",	0,	0,	1ull,	1ull},
+	{"ERBAR_EN"                    ,	0,	1,	330,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_10"               ,	1,	10,	330,	"RAZ",	1,	1,	0,	0},
+	{"ERBARZ"                      ,	11,	5,	330,	"RO",	0,	0,	0ull,	0ull},
+	{"ERBAR"                       ,	16,	16,	330,	"R/W",	0,	1,	0ull,	0},
+	{"CP"                          ,	0,	8,	331,	"RO",	0,	0,	224ull,	224ull},
+	{"RESERVED_8_31"               ,	8,	24,	331,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	332,	"R/W",	0,	1,	0ull,	0},
+	{"INTA"                        ,	8,	8,	332,	"RO",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	332,	"RO",	0,	0,	64ull,	64ull},
+	{"ML"                          ,	24,	8,	332,	"RO",	0,	0,	64ull,	64ull},
+	{"MLTD"                        ,	0,	1,	333,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSWC"                        ,	1,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	333,	"RAZ",	1,	1,	0,	0},
+	{"DPPMR"                       ,	3,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBE"                         ,	4,	12,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TILT"                        ,	16,	4,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TSLTE"                       ,	20,	3,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMAE"                        ,	23,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWTAE"                       ,	24,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEN"                       ,	25,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSEI"                       ,	26,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRTAE"                       ,	27,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDRS"                       ,	28,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDSATI"                      ,	29,	1,	333,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRDARD"                      ,	30,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRDNPR"                      ,	31,	1,	333,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSCME"                       ,	0,	32,	334,	"R/W1C",	0,	1,	0ull,	0},
+	{"TDSRPS"                      ,	0,	32,	335,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TDOMC"                       ,	0,	5,	336,	"R/W",	0,	0,	1ull,	1ull},
+	{"TIDOMC"                      ,	5,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	336,	"RAZ",	1,	1,	0,	0},
+	{"TIBDE"                       ,	7,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIBCD"                       ,	8,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_10"               ,	9,	2,	336,	"RAZ",	1,	1,	0,	0},
+	{"TMAPES"                      ,	11,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMDPES"                      ,	12,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMSE"                        ,	13,	1,	336,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TMEI"                        ,	14,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"TECI"                        ,	15,	1,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"TMES"                        ,	16,	8,	336,	"RO",	0,	0,	0ull,	0ull},
+	{"MDRRMC"                      ,	24,	3,	336,	"R/W",	0,	0,	2ull,	2ull},
+	{"MDRIMC"                      ,	27,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDRE"                        ,	28,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"MDWE"                        ,	29,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCI"                       ,	30,	1,	336,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRBCM"                       ,	31,	1,	336,	"R/W",	0,	0,	1ull,	1ull},
+	{"MDSP"                        ,	0,	32,	337,	"R/W1C",	0,	1,	0ull,	0},
+	{"SCMRE"                       ,	0,	32,	338,	"R/W1C",	0,	1,	0ull,	0},
+	{"MTTV"                        ,	0,	8,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRV"                         ,	8,	8,	339,	"R/W",	0,	0,	0ull,	255ull},
+	{"MTTA"                        ,	16,	1,	339,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRA"                         ,	17,	1,	339,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FLUSH"                       ,	18,	1,	339,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_19_24"              ,	19,	6,	339,	"RAZ",	1,	1,	0,	0},
+	{"MAC"                         ,	25,	7,	339,	"R/W",	0,	0,	0ull,	0ull},
+	{"PXCID"                       ,	0,	8,	340,	"RO",	0,	0,	7ull,	7ull},
+	{"NCP"                         ,	8,	8,	340,	"RO",	0,	0,	232ull,	232ull},
+	{"DPERE"                       ,	16,	1,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROE"                         ,	17,	1,	340,	"R/W",	0,	0,	1ull,	1ull},
+	{"MMBC"                        ,	18,	2,	340,	"R/W",	0,	0,	0ull,	0ull},
+	{"MOST"                        ,	20,	3,	340,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_23_31"              ,	23,	9,	340,	"RAZ",	1,	1,	0,	0},
+	{"FN"                          ,	0,	3,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"DN"                          ,	3,	5,	341,	"RO",	0,	0,	31ull,	31ull},
+	{"BN"                          ,	8,	8,	341,	"RO",	0,	1,	17ull,	0},
+	{"W64"                         ,	16,	1,	341,	"RO",	0,	0,	1ull,	1ull},
+	{"M133"                        ,	17,	1,	341,	"RO",	0,	0,	1ull,	1ull},
+	{"SCD"                         ,	18,	1,	341,	"R/W1C",	0,	1,	0ull,	0},
+	{"USC"                         ,	19,	1,	341,	"R/W1C",	0,	1,	0ull,	0},
+	{"DC"                          ,	20,	1,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"MMRBCD"                      ,	21,	2,	341,	"RO",	0,	0,	2ull,	2ull},
+	{"MOSTD"                       ,	23,	3,	341,	"RO",	0,	0,	3ull,	3ull},
+	{"MCRSD"                       ,	26,	3,	341,	"RO",	0,	0,	7ull,	7ull},
+	{"SCEMR"                       ,	29,	1,	341,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_30_31"              ,	30,	2,	341,	"RAZ",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	342,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	342,	"RO",	0,	0,	240ull,	240ull},
+	{"PCIMIV"                      ,	16,	3,	342,	"RO",	0,	0,	2ull,	2ull},
+	{"PMEC"                        ,	19,	1,	342,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	342,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	342,	"RO",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	342,	"RO",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	342,	"RO",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	342,	"RO",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	342,	"RO",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	343,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	343,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	343,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	343,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEN"                      ,	23,	1,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	344,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	344,	"RO",	0,	0,	0ull,	0ull},
+	{"MSIEN"                       ,	16,	1,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	344,	"RO",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	344,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	344,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	344,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	345,	"RAZ",	1,	1,	0,	0},
+	{"MSI31T2"                     ,	2,	30,	345,	"R/W",	0,	1,	0ull,	0},
+	{"MSI"                         ,	0,	32,	346,	"R/W",	0,	1,	0ull,	0},
+	{"MSIMD"                       ,	0,	16,	347,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	347,	"RAZ",	1,	1,	0,	0},
+	{"PCICNT"                      ,	0,	32,	348,	"R/W",	0,	1,	0ull,	0},
+	{"AP_SPEED"                    ,	32,	2,	348,	"RO",	1,	1,	0,	0},
+	{"AP_PCIX"                     ,	34,	1,	348,	"RO",	1,	1,	0,	0},
+	{"HM_SPEED"                    ,	35,	2,	348,	"RO",	0,	1,	0ull,	0},
+	{"HM_PCIX"                     ,	37,	1,	348,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	348,	"RAZ",	1,	1,	0,	0},
+	{"BAR2_CAX"                    ,	0,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	1,	2,	349,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	3,	1,	349,	"R/W",	0,	0,	0ull,	1ull},
+	{"TSR_HWM"                     ,	4,	3,	349,	"R/W",	0,	1,	1ull,	0},
+	{"PMO_FPC"                     ,	7,	3,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMO_AMOD"                    ,	10,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"B12_BIST"                    ,	11,	1,	349,	"RO",	0,	0,	0ull,	0ull},
+	{"AP_64AD"                     ,	12,	1,	349,	"RO",	0,	1,	0ull,	0},
+	{"AP_PCIX"                     ,	13,	1,	349,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_14"              ,	14,	1,	349,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EN_WFILT"                    ,	15,	1,	349,	"R/W",	0,	0,	0ull,	1ull},
+	{"SCM"                         ,	16,	1,	349,	"RO",	0,	1,	0ull,	0},
+	{"SCMTYP"                      ,	17,	1,	349,	"RO",	0,	1,	0ull,	0},
+	{"BAR2PRES"                    ,	18,	1,	349,	"R/W",	1,	1,	0,	0},
+	{"ERST_N"                      ,	19,	1,	349,	"RO",	0,	0,	1ull,	1ull},
+	{"BB0"                         ,	20,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1"                         ,	21,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_ES"                       ,	22,	2,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB_CA"                       ,	24,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_SIZ"                     ,	25,	1,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"BB1_HOLE"                    ,	26,	3,	349,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	349,	"RAZ",	1,	1,	0,	0},
+	{"INC_VAL"                     ,	0,	16,	350,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	350,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	32,	351,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	352,	"R/W",	0,	1,	0ull,	0},
+	{"DMA_TIME"                    ,	0,	32,	353,	"R/W",	0,	1,	0ull,	0},
+	{"ICNT"                        ,	0,	32,	354,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ITR_WABT"                    ,	0,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WABT"                    ,	1,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_WTTO"                    ,	2,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ITR_ABT"                     ,	3,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_ABT"                     ,	4,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMR_TTO"                     ,	5,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_PER"                    ,	6,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_TABT"                   ,	7,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMSI_MABT"                   ,	8,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IMSC_MSG"                    ,	9,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ITSR_ABT"                    ,	10,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ISERR"                       ,	11,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IAPERR"                      ,	12,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IDPERR"                      ,	13,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IRSL_INT"                    ,	16,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT0"                      ,	17,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IPCNT1"                      ,	18,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_20"              ,	19,	2,	355,	"RAZ",	0,	1,	0ull,	0},
+	{"IPTIME0"                     ,	21,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IPTIME1"                     ,	22,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_24"              ,	23,	2,	355,	"RAZ",	0,	1,	0ull,	0},
+	{"IDCNT0"                      ,	25,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IDCNT1"                      ,	26,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME0"                     ,	27,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"IDTIME1"                     ,	28,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	355,	"RAZ",	1,	1,	0,	0},
+	{"RTR_WABT"                    ,	0,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WABT"                    ,	1,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_WTTO"                    ,	2,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RTR_ABT"                     ,	3,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_ABT"                     ,	4,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMR_TTO"                     ,	5,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_PER"                    ,	6,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_TABT"                   ,	7,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMSI_MABT"                   ,	8,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RMSC_MSG"                    ,	9,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RTSR_ABT"                    ,	10,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RSERR"                       ,	11,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RAPERR"                      ,	12,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RDPERR"                      ,	13,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RWR"                     ,	14,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RRD"                     ,	15,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RRSL_INT"                    ,	16,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT0"                      ,	17,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RPCNT1"                      ,	18,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_19_20"              ,	19,	2,	356,	"RAZ",	0,	1,	0ull,	0},
+	{"RPTIME0"                     ,	21,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RPTIME1"                     ,	22,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_24"              ,	23,	2,	356,	"RAZ",	0,	1,	0ull,	0},
+	{"RDCNT0"                      ,	25,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RDCNT1"                      ,	26,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME0"                     ,	27,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RDTIME1"                     ,	28,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0_FI"                     ,	29,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1_FI"                     ,	30,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"WIN_WR"                      ,	31,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_WR"                      ,	32,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"ILL_RD"                      ,	33,	1,	356,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_34_63"              ,	34,	30,	356,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	357,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	357,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	357,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	357,	"RAZ",	1,	1,	0,	0},
+	{"TR_WABT"                     ,	0,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WABT"                     ,	1,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_WTTO"                     ,	2,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TR_ABT"                      ,	3,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_ABT"                      ,	4,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MR_TTO"                      ,	5,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_PER"                     ,	6,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_TABT"                    ,	7,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_MABT"                    ,	8,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSC_MSG"                     ,	9,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TSR_ABT"                     ,	10,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SERR"                        ,	11,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"APERR"                       ,	12,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPERR"                       ,	13,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RWR"                     ,	14,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RRD"                     ,	15,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSL_INT"                     ,	16,	1,	358,	"RO",	0,	0,	0ull,	0ull},
+	{"PCNT0"                       ,	17,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT1"                       ,	18,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_20"              ,	19,	2,	358,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTIME0"                      ,	21,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PTIME1"                      ,	22,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_24"              ,	23,	2,	358,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	25,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	26,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	27,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	28,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0_FI"                     ,	29,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_FI"                     ,	30,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WIN_WR"                      ,	31,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_WR"                      ,	32,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ILL_RD"                      ,	33,	1,	358,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	358,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	6,	359,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_6_31"               ,	6,	26,	359,	"R/W",	1,	1,	0,	0},
+	{"PTR_CNT"                     ,	0,	16,	360,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	16,	16,	360,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_CNT"                     ,	0,	32,	361,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_CNT"                     ,	0,	32,	362,	"R/W",	0,	1,	0ull,	0},
+	{"PKT_TIME"                    ,	0,	32,	363,	"R/W",	0,	1,	0ull,	0},
+	{"PREFETCH"                    ,	0,	3,	364,	"R/W",	0,	0,	0ull,	2ull},
+	{"MIN_DATA"                    ,	3,	6,	364,	"R/W",	0,	0,	0ull,	4ull},
+	{"RESERVED_9_31"               ,	9,	23,	364,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	365,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	365,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	365,	"RAZ",	1,	1,	0,	0},
+	{"PREFETCH"                    ,	0,	3,	366,	"R/W",	0,	0,	0ull,	3ull},
+	{"MIN_DATA"                    ,	3,	6,	366,	"R/W",	0,	0,	0ull,	6ull},
+	{"RESERVED_9_31"               ,	9,	23,	366,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	31,	367,	"R/W",	0,	0,	10000ull,	10000ull},
+	{"ENB"                         ,	31,	1,	367,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_32_63"              ,	32,	32,	367,	"RAZ",	1,	1,	0,	0},
+	{"SCM"                         ,	0,	32,	368,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	368,	"RAZ",	1,	1,	0,	0},
+	{"TSR"                         ,	0,	36,	369,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	369,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	370,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	2,	46,	370,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	370,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	370,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	371,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	372,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	3,	45,	372,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	372,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	372,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	373,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	374,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	374,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	375,	"R/W",	0,	0,	0ull,	8ull},
+	{"FETCHSIZ"                    ,	4,	4,	375,	"R/W",	0,	0,	0ull,	7ull},
+	{"TXRD"                        ,	8,	10,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"USELDT"                      ,	18,	1,	375,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	375,	"RAZ",	1,	1,	0,	0},
+	{"RXST"                        ,	20,	10,	375,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_30_31"              ,	30,	2,	375,	"RAZ",	1,	1,	0,	0},
+	{"TXSLOTS"                     ,	32,	10,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_43"              ,	42,	2,	375,	"RAZ",	1,	1,	0,	0},
+	{"RXSLOTS"                     ,	44,	10,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_62"              ,	54,	9,	375,	"RAZ",	1,	1,	0,	0},
+	{"RDPEND"                      ,	63,	1,	375,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYNCMISSED"                 ,	0,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXWRAP"                      ,	2,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXST"                        ,	3,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXWRAP"                      ,	4,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXRD"                        ,	5,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXEMPTY"                     ,	6,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXOVF"                       ,	7,	1,	376,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_63"               ,	8,	56,	376,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCMISSED"                 ,	0,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYNCEXTRA"                  ,	1,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXWRAP"                      ,	2,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXST"                        ,	3,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXWRAP"                      ,	4,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXRD"                        ,	5,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXEMPTY"                     ,	6,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXOVF"                       ,	7,	1,	377,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	377,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	378,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	378,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	379,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	379,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	380,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	381,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	382,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	383,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	384,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	385,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	386,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	387,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	388,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	388,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	388,	"RAZ",	1,	1,	0,	0},
+	{"ENABLE"                      ,	0,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"USECLK1"                     ,	1,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBFIRST"                    ,	2,	1,	389,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	389,	"RAZ",	1,	1,	0,	0},
+	{"SAMPPT"                      ,	32,	16,	389,	"R/W",	0,	1,	0ull,	0},
+	{"DRVTIM"                      ,	48,	16,	389,	"R/W",	0,	1,	0ull,	0},
+	{"DEBUGINFO"                   ,	0,	64,	390,	"RO",	1,	1,	0,	0},
+	{"FRAM"                        ,	0,	3,	391,	"R/W",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	391,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	391,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	392,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	392,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	393,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	394,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	395,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	396,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	397,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	398,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	399,	"R/W",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	64,	400,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	401,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	33,	401,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_36_63"              ,	36,	28,	401,	"RAZ",	1,	1,	0,	0},
+	{"ENA"                         ,	0,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCPOL"                    ,	1,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCLKPOL"                     ,	2,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"BITLEN"                      ,	3,	2,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXTRABIT"                    ,	5,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUMSLOTS"                    ,	6,	10,	402,	"R/W",	0,	1,	0ull,	0},
+	{"FSYNCLOC"                    ,	16,	5,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSYNCLEN"                    ,	21,	5,	402,	"R/W",	0,	0,	0ull,	2ull},
+	{"RESERVED_26_31"              ,	26,	6,	402,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCSAMP"                   ,	32,	16,	402,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_62"              ,	48,	15,	402,	"RAZ",	1,	1,	0,	0},
+	{"FSYNCGOOD"                   ,	63,	1,	402,	"RO",	0,	0,	0ull,	1ull},
+	{"DEBUGINFO"                   ,	0,	64,	403,	"RO",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	404,	"R/W",	0,	1,	0ull,	0},
+	{"NUMSAMP"                     ,	32,	16,	404,	"R/W",	0,	1,	0ull,	0},
+	{"DELTASAMP"                   ,	48,	16,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	0,	17,	405,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	405,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	406,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	406,	"RAZ",	1,	1,	0,	0},
+	{"MINLEN"                      ,	0,	16,	407,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	407,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	407,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	408,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	408,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	408,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	408,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	409,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	409,	"RAZ",	0,	1,	0ull,	0},
+	{"L4_MAL"                      ,	8,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	409,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	409,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PKTDRP"                      ,	0,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	410,	"RAZ",	1,	1,	0,	0},
+	{"BCKPRS"                      ,	2,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	410,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	410,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	411,	"RAZ",	1,	1,	0,	0},
+	{"BCKPRS"                      ,	2,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	411,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	411,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	412,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	412,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	413,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	413,	"RAZ",	1,	1,	0,	0},
+	{"CRC_EN"                      ,	12,	1,	413,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	413,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	413,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT"                     ,	20,	4,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	413,	"RAZ",	1,	1,	0,	0},
+	{"GRP_WAT"                     ,	28,	4,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	413,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	413,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	413,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	414,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	414,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	415,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	416,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	417,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	417,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	417,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	417,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	418,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	419,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	420,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	420,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	421,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	421,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	422,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	422,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	423,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	423,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	424,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	424,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	425,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	425,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	426,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	426,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	427,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	427,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	429,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	430,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	430,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	431,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	431,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	432,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	432,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	433,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	433,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	434,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	434,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	435,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	435,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	436,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	437,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	437,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	437,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	438,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	438,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	439,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	439,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	440,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	440,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	440,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	440,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	441,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	441,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	441,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	441,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	441,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	442,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	442,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	442,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	443,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	443,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	443,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	443,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	443,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	444,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	444,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	444,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	444,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	445,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	445,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	445,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	445,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	445,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	446,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	446,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	446,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	446,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	446,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	447,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	448,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	448,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	6,	8,	448,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	14,	4,	448,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF_MAX"                 ,	18,	4,	448,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	22,	5,	448,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	27,	3,	448,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	30,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	31,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	32,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	33,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	34,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	35,	1,	448,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	36,	3,	448,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	39,	6,	448,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	45,	16,	448,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	61,	3,	448,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	0,	3,	449,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	3,	16,	449,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	19,	16,	449,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	35,	29,	449,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	0,	11,	450,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	450,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	451,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	451,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	451,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	451,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	451,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	451,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	452,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	452,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	452,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	452,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	452,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	452,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	452,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	453,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	453,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	453,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	453,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	454,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	454,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	454,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	454,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	454,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	454,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	454,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	454,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	454,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	455,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	455,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	455,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	455,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	455,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	456,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	4,	456,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	456,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	456,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	6,	456,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	21,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	22,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	25,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	26,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	27,	3,	456,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CRC"                     ,	30,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	31,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	32,	1,	456,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	456,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	457,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	457,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	457,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	64,	458,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	460,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	461,	"RO",	0,	0,	0ull,	0ull},
+	{"PARITY"                      ,	0,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	462,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	462,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	463,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	463,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	463,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE1"                       ,	3,	3,	464,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	464,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	465,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	465,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	466,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	466,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	467,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	467,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	468,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	468,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	468,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR"                         ,	0,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	2,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	3,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	4,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	5,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT0"                        ,	6,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT1"                        ,	7,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	8,	1,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	469,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	2,	469,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	469,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	470,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	470,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	471,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	471,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	471,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	471,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	471,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	471,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	471,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	471,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	472,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	472,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	472,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	473,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	473,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	474,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	474,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	9,	475,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	475,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	476,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	476,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	477,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	477,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	478,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	478,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	478,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	479,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	479,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	479,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	479,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	479,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	8,	480,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_11"               ,	8,	4,	480,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	8,	480,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_20_23"              ,	20,	4,	480,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	9,	480,	"RO",	0,	1,	249ull,	0},
+	{"RESERVED_33_35"              ,	33,	3,	480,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	9,	480,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	480,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	9,	480,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_57_63"              ,	57,	7,	480,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	481,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	481,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	482,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	482,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	483,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	483,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	484,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	484,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	484,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	9,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	485,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	9,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	485,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	485,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	485,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	486,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	486,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	486,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	486,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	486,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	8,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_11"               ,	8,	4,	487,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	8,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_23"              ,	20,	4,	487,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	487,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	487,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	487,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	488,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	488,	"RAZ",	1,	1,	0,	0},
+	{"MEM"                         ,	0,	1,	489,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	489,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	489,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	490,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	490,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	491,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	491,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	491,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	491,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	491,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	491,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	491,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	491,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	492,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	492,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	492,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	493,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	493,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	494,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	494,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	494,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	494,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	495,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	495,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	495,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	495,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	496,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	496,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	496,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	496,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	497,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	497,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	497,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	498,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	498,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	498,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	498,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	498,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	499,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	499,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	500,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	501,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	501,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	501,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	501,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	502,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	502,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	503,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	503,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	503,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	504,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	505,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	505,	"RAZ",	1,	0,	0,	0ull},
+	{"INEPINT"                     ,	0,	16,	506,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	506,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	507,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	508,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	508,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	508,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	508,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	508,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	509,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	509,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	509,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	509,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	509,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	509,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	509,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	510,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	510,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	510,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	510,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	510,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	510,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	510,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	510,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	511,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	511,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	511,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	512,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	512,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	513,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	514,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	514,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	514,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	514,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	514,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	514,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	514,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	514,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	514,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	515,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	516,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	517,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	518,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	518,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	519,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	519,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	520,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	522,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	523,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	524,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	524,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	524,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	525,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	526,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	526,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	526,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	526,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	526,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	526,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	526,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	526,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	526,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	526,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	526,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	526,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	526,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	526,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	527,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	527,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	527,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	527,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	527,	"RO",	0,	0,	1ull,	1ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	527,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	527,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	527,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	528,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	528,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	528,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	528,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	528,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	528,	"RO",	0,	0,	1ull,	1ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	528,	"RO",	0,	0,	1ull,	1ull},
+	{"AVALIDFLTR"                  ,	22,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"BVALIDFLTR"                  ,	23,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"SESSENDFLTR"                 ,	24,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDEDTRFIFO"                 ,	25,	1,	528,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVMODINEND"              ,	26,	4,	528,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_30_31"              ,	30,	2,	528,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	529,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	529,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	529,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	529,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	530,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	530,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	530,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	530,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	531,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	531,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	532,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	533,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	533,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	533,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	533,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	533,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	533,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	533,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	534,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	534,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	534,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	534,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	534,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	535,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	535,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	535,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	536,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	536,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	537,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	538,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	539,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	539,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	540,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	540,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	541,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	542,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	542,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	542,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	542,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	542,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	542,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	543,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	543,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	544,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	545,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	546,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	547,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	547,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	548,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	549,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	551,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	551,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	552,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	552,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	553,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	553,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	553,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	553,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	553,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	553,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	554,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	554,	"R/W",	0,	0,	256ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	555,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	557,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	557,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"N2UF_BIS"                    ,	3,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"E2HC_BIS"                    ,	4,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NF_BIS"                    ,	5,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NC_BIS"                    ,	6,	1,	558,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	558,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	559,	"R/W",	0,	0,	4ull,	0ull},
+	{"HRST"                        ,	3,	1,	559,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	559,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	559,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	559,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	559,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	559,	"R/W",	0,	0,	2ull,	0ull},
+	{"P_COM_ON"                    ,	13,	1,	559,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_RTYPE"                     ,	14,	2,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	559,	"RAZ",	1,	1,	0,	0},
+	{"HCLK_RST"                    ,	17,	1,	559,	"R/W",	0,	0,	1ull,	1ull},
+	{"DIVIDE2"                     ,	18,	2,	559,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_63"              ,	20,	44,	559,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	560,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	560,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	560,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	561,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	561,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	562,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	562,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	563,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	563,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	564,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	564,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	565,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	565,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	566,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	566,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	567,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	567,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	568,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	568,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	569,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	569,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	570,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	570,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	571,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	571,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	572,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	572,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	573,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	573,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	574,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	574,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	575,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	575,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	576,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	576,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	577,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	578,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	578,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	578,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	579,	"RAZ",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	579,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	579,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	579,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_22"              ,	19,	4,	580,	"RAZ",	0,	0,	0ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXPREEMPHASISTUNE"           ,	30,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	580,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	580,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	580,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	580,	"RO",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	38,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	39,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	40,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRVVBUS"                     ,	41,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	42,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGDISABLE"                  ,	43,	1,	580,	"R/W",	0,	0,	1ull,	1ull},
+	{"OTGTUNE"                     ,	44,	3,	580,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMPDISTUNE"                 ,	47,	3,	580,	"R/W",	0,	0,	2ull,	2ull},
+	{"SQRXTUNE"                    ,	50,	3,	580,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXHSXVTUNE"                  ,	53,	2,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFSLSTUNE"                  ,	55,	4,	580,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXVREFTUNE"                  ,	59,	4,	580,	"R/W",	0,	0,	7ull,	7ull},
+	{"TXRISETUNE"                  ,	63,	1,	580,	"R/W",	0,	0,	0ull,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_drv_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	12,	16},
+	{"cvmx_agl_gmx_inf_mode"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	3,	28},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	7,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	38},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	39},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	40},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	1,	41},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	1,	42},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	1,	43},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	44},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	4,	46},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	50},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	10,	52},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	11,	62},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	73},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	75},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	2,	77},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	19,	79},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	19,	98},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	117},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	40,	2,	119},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	121},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	123},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	125},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	127},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	129},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	131},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	133},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	135},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	137},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	139},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	4,	141},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	2,	145},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	147},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	149},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	4,	151},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	4,	155},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	2,	159},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	3,	161},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	5,	164},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	3,	169},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	2,	172},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	81,	2,	174},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	176},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	85,	2,	178},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	180},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	182},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	184},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	93,	2,	186},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	2,	188},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	190},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	2,	192},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	194},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	196},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	2,	198},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	2,	200},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	2,	202},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	111,	2,	204},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	206},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	208},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	116,	2,	210},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	117,	3,	212},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	10,	215},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	10,	225},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	120,	2,	235},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	2,	237},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	6,	239},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	123,	2,	245},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	124,	2,	247},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	125,	2,	249},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	126,	2,	251},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	127,	2,	253},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	128,	2,	255},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	129,	22,	257},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	138,	6,	279},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	147,	22,	285},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	151,	6,	307},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	155,	22,	313},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	164,	22,	335},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	168,	6,	357},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	169,	2,	363},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	173,	2,	365},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	177,	2,	367},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	178,	2,	369},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	179,	2,	371},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	180,	1,	373},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	184,	3,	374},
+	{"cvmx_ciu_qlm_dcok"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	185,	2,	377},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	186,	6,	379},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	187,	8,	385},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	188,	2,	393},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	189,	2,	395},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	190,	2,	397},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	191,	2,	399},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	192,	3,	401},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	196,	7,	404},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	200,	6,	411},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	201,	7,	417},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	202,	29,	424},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	203,	29,	453},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	204,	2,	482},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	212,	2,	484},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	220,	3,	486},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	221,	3,	489},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	222,	2,	492},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	223,	2,	494},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	224,	7,	496},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	225,	2,	503},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	226,	2,	505},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	227,	5,	507},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	228,	7,	512},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	229,	2,	519},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	230,	10,	521},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	234,	1,	531},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	238,	1,	532},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	242,	1,	533},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	246,	1,	534},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	250,	1,	535},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	254,	1,	536},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	258,	2,	537},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	262,	4,	539},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	266,	2,	543},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	270,	9,	545},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	274,	11,	554},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	278,	2,	565},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	282,	27,	567},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	286,	27,	594},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	290,	2,	621},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	294,	2,	623},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	298,	2,	625},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	302,	2,	627},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	306,	2,	629},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	310,	2,	631},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	314,	2,	633},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	318,	2,	635},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	322,	2,	637},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	326,	2,	639},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	330,	2,	641},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	334,	2,	643},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	338,	4,	645},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	342,	2,	649},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	346,	2,	651},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	350,	2,	653},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	354,	4,	655},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	355,	4,	659},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	356,	2,	663},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	357,	5,	665},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	358,	2,	670},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	359,	2,	672},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	363,	3,	674},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	364,	5,	677},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	368,	2,	682},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	372,	3,	684},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	376,	2,	687},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	380,	2,	689},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	384,	2,	691},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	388,	3,	693},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	392,	2,	696},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	396,	2,	698},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	400,	2,	700},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	404,	2,	702},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	2,	704},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	412,	2,	706},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	2,	708},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	420,	2,	710},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	424,	2,	712},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	428,	2,	714},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	432,	2,	716},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	436,	2,	718},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	440,	2,	720},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	444,	2,	722},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	448,	2,	724},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	452,	2,	726},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	456,	2,	728},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	457,	2,	730},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	458,	2,	732},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	459,	2,	734},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	460,	2,	736},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	461,	3,	738},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	462,	8,	741},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	463,	8,	749},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	464,	2,	757},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	465,	2,	759},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	466,	6,	761},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	467,	2,	767},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	468,	2,	769},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	469,	2,	771},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	470,	9,	773},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	3,	782},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	472,	9,	785},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	488,	2,	794},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	492,	2,	796},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	493,	2,	798},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	494,	2,	800},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	495,	2,	802},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	496,	19,	804},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	497,	6,	823},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	498,	3,	829},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	499,	3,	832},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	500,	3,	835},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	501,	5,	838},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	502,	5,	843},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	503,	1,	848},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	504,	1,	849},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	505,	7,	850},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	506,	7,	857},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	507,	3,	864},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	508,	3,	867},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	509,	3,	870},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	510,	5,	873},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	511,	5,	878},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	512,	1,	883},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	513,	1,	884},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	514,	3,	885},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	515,	3,	888},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	516,	3,	891},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	517,	2,	894},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	518,	2,	896},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	519,	2,	898},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	520,	2,	900},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	521,	19,	902},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	522,	2,	921},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	523,	1,	923},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	524,	15,	924},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	525,	13,	939},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	526,	13,	952},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	527,	2,	965},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	528,	2,	967},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	529,	2,	969},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	530,	3,	971},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	534,	3,	974},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	538,	2,	977},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	542,	2,	979},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	546,	2,	981},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	610,	1,	983},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	612,	1,	984},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	614,	6,	985},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	615,	5,	991},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	616,	6,	996},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	617,	7,	1002},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	618,	2,	1009},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	626,	2,	1011},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	627,	3,	1013},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	628,	2,	1016},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	629,	5,	1018},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	637,	3,	1023},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	638,	4,	1026},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	639,	3,	1030},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	640,	2,	1033},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	641,	2,	1035},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	642,	8,	1037},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	643,	9,	1045},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	644,	8,	1054},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	645,	12,	1062},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	646,	9,	1074},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	647,	5,	1083},
+	{"cvmx_l2c_grpwrr0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	648,	2,	1088},
+	{"cvmx_l2c_grpwrr1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	649,	2,	1090},
+	{"cvmx_l2c_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	650,	10,	1092},
+	{"cvmx_l2c_int_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	651,	10,	1102},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	652,	4,	1112},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	653,	2,	1116},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	654,	16,	1118},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	655,	19,	1134},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	656,	3,	1153},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	657,	4,	1156},
+	{"cvmx_l2c_oob"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	658,	3,	1160},
+	{"cvmx_l2c_oob1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	659,	6,	1163},
+	{"cvmx_l2c_oob2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	660,	6,	1169},
+	{"cvmx_l2c_oob3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	661,	6,	1175},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	662,	2,	1181},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	666,	17,	1183},
+	{"cvmx_l2c_ppgrp"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	667,	5,	1200},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	668,	5,	1205},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	669,	2,	1210},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	670,	3,	1212},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	671,	2,	1215},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	672,	2,	1217},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	673,	2,	1219},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	674,	7,	1221},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	675,	5,	1228},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	676,	3,	1233},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	677,	3,	1236},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	678,	2,	1239},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	679,	2,	1241},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	680,	2,	1243},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	681,	6,	1245},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	682,	14,	1251},
+	{"cvmx_lmc#_bist_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	683,	2,	1265},
+	{"cvmx_lmc#_bist_result"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	684,	8,	1267},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	685,	7,	1275},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	686,	19,	1282},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	687,	8,	1301},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	688,	2,	1309},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	689,	2,	1311},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	690,	18,	1313},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	691,	6,	1331},
+	{"cvmx_lmc#_dll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	692,	5,	1337},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	693,	5,	1342},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	694,	5,	1347},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	695,	6,	1352},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	696,	2,	1358},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	697,	2,	1360},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	698,	14,	1362},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	699,	9,	1376},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	700,	2,	1385},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	701,	2,	1387},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	702,	14,	1389},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	703,	6,	1403},
+	{"cvmx_lmc#_read_level_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	704,	7,	1409},
+	{"cvmx_lmc#_read_level_dbg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	705,	4,	1416},
+	{"cvmx_lmc#_read_level_rank#"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	706,	11,	1420},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	710,	6,	1431},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	711,	9,	1437},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	712,	5,	1446},
+	{"cvmx_lmc#_wodt_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	713,	5,	1451},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	714,	5,	1456},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	715,	3,	1461},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	716,	10,	1464},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	718,	3,	1474},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	720,	3,	1477},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	722,	15,	1480},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	724,	3,	1495},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	725,	3,	1498},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	726,	3,	1501},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	727,	5,	1504},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	729,	1,	1509},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	730,	13,	1510},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	738,	13,	1523},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	746,	6,	1536},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	747,	1,	1542},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	751,	2,	1543},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	752,	2,	1545},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	753,	13,	1547},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	754,	8,	1560},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	755,	4,	1568},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	756,	1,	1572},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	757,	3,	1573},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	758,	2,	1576},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	759,	6,	1578},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	760,	7,	1584},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	761,	4,	1591},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	762,	2,	1595},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	763,	2,	1597},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	764,	13,	1599},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	766,	12,	1612},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	768,	3,	1624},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	770,	3,	1627},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	772,	2,	1630},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	774,	2,	1632},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	776,	2,	1634},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	778,	7,	1636},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	780,	2,	1643},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	782,	7,	1645},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	784,	4,	1652},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	786,	8,	1656},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	788,	9,	1664},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	790,	7,	1673},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	792,	9,	1680},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	794,	2,	1689},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	796,	2,	1691},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	798,	4,	1693},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	800,	2,	1697},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	2,	1699},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	804,	2,	1701},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	806,	4,	1703},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	808,	2,	1707},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	2,	1709},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	2,	1711},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	814,	2,	1713},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	816,	2,	1715},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	818,	2,	1717},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	820,	6,	1719},
+	{"cvmx_mio_uart2_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	822,	2,	1725},
+	{"cvmx_mio_uart2_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	823,	2,	1727},
+	{"cvmx_mio_uart2_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	824,	2,	1729},
+	{"cvmx_mio_uart2_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	825,	7,	1731},
+	{"cvmx_mio_uart2_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	826,	2,	1738},
+	{"cvmx_mio_uart2_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	827,	7,	1740},
+	{"cvmx_mio_uart2_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	828,	4,	1747},
+	{"cvmx_mio_uart2_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	829,	8,	1751},
+	{"cvmx_mio_uart2_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	830,	9,	1759},
+	{"cvmx_mio_uart2_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	831,	7,	1768},
+	{"cvmx_mio_uart2_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	832,	9,	1775},
+	{"cvmx_mio_uart2_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	833,	2,	1784},
+	{"cvmx_mio_uart2_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	834,	2,	1786},
+	{"cvmx_mio_uart2_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	835,	4,	1788},
+	{"cvmx_mio_uart2_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	836,	2,	1792},
+	{"cvmx_mio_uart2_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	837,	2,	1794},
+	{"cvmx_mio_uart2_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	838,	2,	1796},
+	{"cvmx_mio_uart2_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	839,	4,	1798},
+	{"cvmx_mio_uart2_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	840,	2,	1802},
+	{"cvmx_mio_uart2_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	841,	2,	1804},
+	{"cvmx_mio_uart2_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	842,	2,	1806},
+	{"cvmx_mio_uart2_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	843,	2,	1808},
+	{"cvmx_mio_uart2_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	844,	2,	1810},
+	{"cvmx_mio_uart2_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	845,	2,	1812},
+	{"cvmx_mio_uart2_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	846,	6,	1814},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	847,	5,	1820},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	849,	8,	1825},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	851,	8,	1833},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	853,	2,	1841},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	855,	3,	1843},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	857,	5,	1846},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	859,	4,	1851},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	861,	8,	1855},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	863,	2,	1863},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	865,	2,	1865},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	867,	5,	1867},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	869,	4,	1872},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	871,	4,	1876},
+	{"cvmx_npei_bar1_index#"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	873,	5,	1880},
+	{"cvmx_npei_bist_status"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	905,	47,	1885},
+	{"cvmx_npei_ctl_port0"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	906,	17,	1932},
+	{"cvmx_npei_ctl_port1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	907,	17,	1949},
+	{"cvmx_npei_ctl_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	908,	10,	1966},
+	{"cvmx_npei_ctl_status2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	909,	11,	1976},
+	{"cvmx_npei_data_out_cnt"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	910,	5,	1987},
+	{"cvmx_npei_dbg_data"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	911,	8,	1992},
+	{"cvmx_npei_dbg_select"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	912,	2,	2000},
+	{"cvmx_npei_dma#_counts"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	913,	3,	2002},
+	{"cvmx_npei_dma#_dbell"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	917,	2,	2005},
+	{"cvmx_npei_dma#_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	921,	3,	2007},
+	{"cvmx_npei_dma#_naddr"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	925,	2,	2010},
+	{"cvmx_npei_dma0_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	929,	2,	2012},
+	{"cvmx_npei_dma1_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	930,	2,	2014},
+	{"cvmx_npei_dma_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	931,	2,	2016},
+	{"cvmx_npei_dma_control"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	932,	15,	2018},
+	{"cvmx_npei_dma_state1_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	933,	11,	2033},
+	{"cvmx_npei_dma_state2_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	934,	6,	2044},
+	{"cvmx_npei_dma_state3_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	935,	5,	2050},
+	{"cvmx_npei_dma_state4_p1"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	936,	5,	2055},
+	{"cvmx_npei_int_a_enb"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	937,	3,	2060},
+	{"cvmx_npei_int_a_enb2"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	938,	3,	2063},
+	{"cvmx_npei_int_a_sum"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	939,	3,	2066},
+	{"cvmx_npei_int_enb"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	940,	64,	2069},
+	{"cvmx_npei_int_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	941,	63,	2133},
+	{"cvmx_npei_int_sum"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	942,	61,	2196},
+	{"cvmx_npei_int_sum2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	943,	61,	2257},
+	{"cvmx_npei_last_win_rdata0"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	944,	1,	2318},
+	{"cvmx_npei_last_win_rdata1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	945,	1,	2319},
+	{"cvmx_npei_mem_access_ctl"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	946,	3,	2320},
+	{"cvmx_npei_mem_access_subid#" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	947,	11,	2323},
+	{"cvmx_npei_msi_enb0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	963,	1,	2334},
+	{"cvmx_npei_msi_enb1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	964,	1,	2335},
+	{"cvmx_npei_msi_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	965,	1,	2336},
+	{"cvmx_npei_msi_enb3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	966,	1,	2337},
+	{"cvmx_npei_msi_rcv0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	967,	1,	2338},
+	{"cvmx_npei_msi_rcv1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	968,	1,	2339},
+	{"cvmx_npei_msi_rcv2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	969,	1,	2340},
+	{"cvmx_npei_msi_rcv3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	970,	1,	2341},
+	{"cvmx_npei_msi_rd_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	971,	3,	2342},
+	{"cvmx_npei_msi_wr_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	972,	3,	2345},
+	{"cvmx_npei_pcie_msi_rcv"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	973,	2,	2348},
+	{"cvmx_npei_pcie_msi_rcv_b1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	974,	3,	2350},
+	{"cvmx_npei_pcie_msi_rcv_b2"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	975,	3,	2353},
+	{"cvmx_npei_pcie_msi_rcv_b3"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	976,	3,	2356},
+	{"cvmx_npei_rsl_int_blocks"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	977,	29,	2359},
+	{"cvmx_npei_scratch_1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	978,	1,	2388},
+	{"cvmx_npei_state1"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	979,	4,	2389},
+	{"cvmx_npei_state2"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	980,	7,	2393},
+	{"cvmx_npei_state3"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	981,	5,	2400},
+	{"cvmx_npei_win_rd_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	982,	4,	2405},
+	{"cvmx_npei_win_rd_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	983,	1,	2409},
+	{"cvmx_npei_win_wr_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	984,	4,	2410},
+	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	985,	1,	2414},
+	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	986,	2,	2415},
+	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	987,	2,	2417},
+	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	988,	2,	2419},
+	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	989,	24,	2421},
+	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	990,	4,	2445},
+	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	991,	5,	2449},
+	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	992,	5,	2454},
+	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	993,	2,	2459},
+	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	994,	1,	2461},
+	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	995,	1,	2462},
+	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	996,	5,	2463},
+	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	997,	2,	2468},
+	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	998,	1,	2470},
+	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	999,	1,	2471},
+	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1000,	4,	2472},
+	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1001,	2,	2476},
+	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1002,	2,	2478},
+	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1003,	1,	2480},
+	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1004,	1,	2481},
+	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1005,	2,	2482},
+	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1006,	3,	2484},
+	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1007,	2,	2487},
+	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1008,	2,	2489},
+	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1009,	4,	2491},
+	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1010,	10,	2495},
+	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1011,	12,	2505},
+	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1012,	7,	2517},
+	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1013,	2,	2524},
+	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1014,	1,	2526},
+	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1015,	2,	2527},
+	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1016,	7,	2529},
+	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1017,	11,	2536},
+	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1018,	19,	2547},
+	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1019,	11,	2566},
+	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1020,	17,	2577},
+	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1021,	12,	2594},
+	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1022,	22,	2606},
+	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1023,	3,	2628},
+	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1024,	3,	2631},
+	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1025,	1,	2634},
+	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1026,	1,	2635},
+	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1027,	1,	2636},
+	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1028,	1,	2637},
+	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1029,	3,	2638},
+	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1030,	14,	2641},
+	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1031,	14,	2655},
+	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1032,	14,	2669},
+	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1033,	9,	2683},
+	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1034,	9,	2692},
+	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1035,	6,	2701},
+	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1036,	1,	2707},
+	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1037,	1,	2708},
+	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1038,	1,	2709},
+	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1039,	1,	2710},
+	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1040,	2,	2711},
+	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1041,	1,	2713},
+	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1042,	6,	2714},
+	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1043,	6,	2720},
+	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1044,	13,	2726},
+	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1045,	5,	2739},
+	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1046,	8,	2744},
+	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1047,	19,	2752},
+	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1048,	3,	2771},
+	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1049,	1,	2774},
+	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1050,	1,	2775},
+	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1051,	3,	2776},
+	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1052,	3,	2779},
+	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1053,	3,	2782},
+	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1054,	4,	2785},
+	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1055,	4,	2789},
+	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1056,	4,	2793},
+	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1057,	7,	2797},
+	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1058,	5,	2804},
+	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1059,	5,	2809},
+	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1060,	4,	2814},
+	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1061,	4,	2818},
+	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1062,	4,	2822},
+	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1063,	1,	2826},
+	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1064,	1,	2827},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1065,	2,	2828},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1067,	24,	2830},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1069,	4,	2854},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1071,	5,	2858},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1073,	1,	2863},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1075,	1,	2864},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1077,	4,	2865},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1079,	17,	2869},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1081,	4,	2886},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1083,	6,	2890},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1085,	1,	2896},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1087,	1,	2897},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1089,	2,	2898},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1091,	2,	2900},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1093,	1,	2902},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1095,	15,	2903},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1097,	10,	2918},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1099,	12,	2928},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1101,	7,	2940},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1103,	2,	2947},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1105,	1,	2949},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1107,	2,	2950},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1109,	7,	2952},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1111,	11,	2959},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1113,	19,	2970},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1115,	11,	2989},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1117,	20,	3000},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1119,	12,	3020},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1121,	22,	3032},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1123,	8,	3054},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1125,	4,	3062},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1127,	3,	3066},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1129,	3,	3069},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1131,	1,	3072},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1133,	1,	3073},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1135,	1,	3074},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1137,	1,	3075},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1139,	3,	3076},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1141,	14,	3079},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1143,	14,	3093},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1145,	14,	3107},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1147,	9,	3121},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1149,	9,	3130},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1151,	6,	3139},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1153,	1,	3145},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1155,	1,	3146},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1157,	1,	3147},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1159,	1,	3148},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1161,	4,	3149},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1163,	9,	3153},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1165,	2,	3162},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1167,	2,	3164},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1169,	1,	3166},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1171,	6,	3167},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1173,	6,	3173},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1175,	13,	3179},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1177,	5,	3192},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1179,	8,	3197},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1181,	19,	3205},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1183,	3,	3224},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1185,	1,	3227},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1187,	1,	3228},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1189,	3,	3229},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1191,	3,	3232},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1193,	3,	3235},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1195,	4,	3238},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1197,	4,	3242},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1199,	4,	3246},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1201,	7,	3250},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1203,	5,	3257},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1205,	5,	3262},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1207,	4,	3267},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1209,	4,	3271},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1211,	4,	3275},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1213,	1,	3279},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1215,	1,	3280},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1217,	9,	3281},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1221,	6,	3290},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1225,	9,	3296},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1229,	6,	3305},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1233,	13,	3311},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1237,	13,	3324},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1241,	2,	3337},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1245,	4,	3339},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1249,	8,	3343},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1253,	13,	3351},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1257,	17,	3364},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1261,	7,	3381},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1265,	3,	3388},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1269,	8,	3391},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1273,	7,	3399},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1277,	4,	3406},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1281,	5,	3410},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1285,	8,	3415},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1287,	2,	3423},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1289,	5,	3425},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1291,	10,	3430},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1293,	2,	3440},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1295,	7,	3442},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1297,	7,	3449},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1299,	6,	3456},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1301,	5,	3462},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1303,	5,	3467},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1305,	3,	3472},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1307,	6,	3475},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1309,	9,	3481},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1311,	3,	3490},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1313,	9,	3493},
+	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1315,	13,	3502},
+	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1317,	15,	3515},
+	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1319,	2,	3530},
+	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1321,	2,	3532},
+	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1323,	2,	3534},
+	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1325,	16,	3536},
+	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1327,	2,	3552},
+	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1329,	32,	3554},
+	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1331,	32,	3586},
+	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1333,	5,	3618},
+	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1335,	2,	3623},
+	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1337,	2,	3625},
+	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1339,	2,	3627},
+	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1341,	2,	3629},
+	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1349,	2,	3631},
+	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1357,	8,	3633},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1359,	2,	3641},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1360,	4,	3643},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1364,	16,	3647},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1365,	16,	3663},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1366,	3,	3679},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1368,	8,	3682},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1369,	22,	3690},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1370,	6,	3712},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1371,	14,	3718},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1372,	14,	3732},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1373,	2,	3746},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1374,	28,	3748},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1382,	25,	3776},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1390,	2,	3801},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1454,	4,	3803},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1462,	9,	3807},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1470,	2,	3816},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1471,	2,	3818},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1472,	2,	3820},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1480,	2,	3822},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1488,	2,	3824},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1496,	2,	3826},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1504,	2,	3828},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1512,	2,	3830},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1520,	2,	3832},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1528,	2,	3834},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1536,	2,	3836},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1544,	2,	3838},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1552,	2,	3840},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1553,	2,	3842},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1561,	2,	3844},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1569,	2,	3846},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1577,	2,	3848},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1641,	2,	3850},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1642,	3,	3852},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1643,	3,	3855},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1644,	2,	3858},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1645,	2,	3860},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1646,	4,	3862},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1647,	5,	3866},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1648,	4,	3871},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1649,	8,	3875},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1650,	4,	3883},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1651,	5,	3887},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1652,	1,	3892},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1653,	5,	3893},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1654,	1,	3898},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1655,	13,	3899},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1656,	4,	3912},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1657,	13,	3916},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1658,	6,	3929},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1659,	9,	3935},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1660,	4,	3944},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1661,	7,	3948},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1662,	5,	3955},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1663,	5,	3960},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1664,	4,	3965},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1665,	9,	3969},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1666,	5,	3978},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1667,	16,	3983},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1668,	4,	3999},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1669,	1,	4003},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1670,	1,	4004},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1671,	1,	4005},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1672,	1,	4006},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	1673,	11,	4007},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1674,	2,	4018},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1675,	4,	4020},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1676,	5,	4024},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1677,	3,	4029},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1678,	4,	4032},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1679,	2,	4036},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1680,	3,	4038},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1681,	3,	4041},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1682,	12,	4044},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1683,	2,	4056},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1684,	13,	4058},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1685,	3,	4071},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1686,	2,	4074},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1694,	2,	4076},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1695,	2,	4078},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1696,	2,	4080},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1697,	2,	4082},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	1705,	2,	4084},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1706,	2,	4086},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	1707,	2,	4088},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1708,	10,	4090},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1712,	5,	4100},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	1720,	10,	4105},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	1728,	2,	4115},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1729,	2,	4117},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1730,	2,	4119},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1738,	3,	4121},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1739,	6,	4124},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	1755,	5,	4130},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	1756,	7,	4135},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	1772,	2,	4142},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	1,	4144},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1789,	1,	4145},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1790,	1,	4146},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1791,	5,	4147},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1792,	5,	4152},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1793,	4,	4157},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1794,	10,	4161},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1795,	1,	4171},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1796,	3,	4172},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1797,	7,	4175},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1798,	2,	4182},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1799,	1,	4184},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1800,	1,	4185},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1801,	1,	4186},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1802,	18,	4187},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1803,	3,	4205},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	2,	4208},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1805,	3,	4210},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1806,	7,	4213},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1807,	2,	4220},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	2,	4222},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1809,	2,	4224},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1810,	3,	4226},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1811,	3,	4229},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1812,	7,	4232},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1813,	10,	4239},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	1815,	6,	4249},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1817,	2,	4255},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1819,	4,	4257},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1821,	4,	4261},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1823,	6,	4265},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1824,	3,	4271},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1825,	5,	4274},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	4,	4279},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1827,	6,	4283},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	4,	4289},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	2,	4293},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1830,	4,	4295},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1831,	2,	4299},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1832,	3,	4301},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	4,	4304},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	12,	4308},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	3,	4320},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1836,	5,	4323},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	2,	4328},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	2,	4330},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1839,	18,	4332},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1840,	12,	4350},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1841,	6,	4362},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1842,	5,	4368},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1843,	1,	4373},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1844,	2,	4374},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1845,	2,	4376},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1846,	18,	4378},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1847,	12,	4396},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1848,	6,	4408},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1849,	2,	4414},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1850,	2,	4416},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1851,	18,	4418},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1852,	12,	4436},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1853,	6,	4448},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1854,	2,	4454},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1856,	2,	4456},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1858,	8,	4458},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1860,	11,	4466},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1862,	15,	4477},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1872,	8,	4492},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1882,	8,	4500},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1884,	4,	4508},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1894,	15,	4512},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1904,	6,	4527},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1914,	6,	4533},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1916,	4,	4539},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1926,	2,	4543},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	1934,	6,	4545},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1936,	4,	4551},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1938,	1,	4555},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1940,	1,	4556},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1942,	1,	4557},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1944,	7,	4558},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1946,	1,	4565},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1948,	14,	4566},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1950,	10,	4580},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1952,	14,	4590},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1954,	32,	4604},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1956,	32,	4636},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	1958,	2,	4668},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1960,	4,	4670},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1962,	13,	4674},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1964,	10,	4687},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1966,	10,	4697},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1968,	2,	4707},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1970,	6,	4709},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1972,	5,	4715},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1974,	6,	4720},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1976,	5,	4726},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1978,	1,	4731},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1980,	13,	4732},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	1982,	2,	4745},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	1984,	2,	4747},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	1986,	11,	4749},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2002,	3,	4760},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	2004,	12,	4763},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2020,	12,	4775},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2036,	6,	4787},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2052,	4,	4793},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2068,	2,	4797},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2070,	2,	4799},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2072,	15,	4801},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2074,	2,	4816},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2076,	3,	4818},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2078,	1,	4821},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2094,	6,	4822},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2096,	8,	4828},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2098,	15,	4836},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2100,	6,	4851},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2102,	2,	4857},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2104,	2,	4859},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2106,	2,	4861},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2108,	2,	4863},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2110,	2,	4865},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2112,	2,	4867},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2114,	2,	4869},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2116,	2,	4871},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2118,	2,	4873},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2120,	2,	4875},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2122,	2,	4877},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2124,	2,	4879},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2126,	2,	4881},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2128,	2,	4883},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2130,	2,	4885},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2132,	2,	4887},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2134,	7,	4889},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2136,	34,	4896},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2138,	34,	4930},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2140,	35,	4964},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800E0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800E0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800E0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800E0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800E0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800E00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800E00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800E0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800E0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800E0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800E0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800E0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800E0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800E0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800E0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800E0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800E0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800E0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800E0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800E0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800E0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800E0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800E00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800E00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800E0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800E00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800E0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800E00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800E00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800E0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800E0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800E0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800E0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_SMAC1"               ,	   0x11800E0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800E0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800E0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800E0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800E0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800E0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800E0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800E0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800E0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800E0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800E0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800E0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800E0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800E0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800E0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800E0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800E0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800E0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800E0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800E0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800E0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_QLM_DCOK"                ,	   0x1070000000760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	98},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	99},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	100},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	101},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	102},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	103},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	104},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	105},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	191},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	192},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	193},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	194},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	195},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	196},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	202},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	203},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	204},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	205},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	206},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	207},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	219},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	220},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	221},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	222},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	223},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	224},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	225},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	226},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	227},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	228},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	229},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	230},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	252},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	253},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	254},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	255},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	256},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	257},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	258},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	259},
+	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	260},
+	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	261},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	262},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	263},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART2_DLH"               ,	   0x1180000000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART2_DLL"               ,	   0x1180000000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART2_FAR"               ,	   0x1180000000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART2_FCR"               ,	   0x1180000000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART2_HTX"               ,	   0x1180000000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART2_IER"               ,	   0x1180000000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART2_IIR"               ,	   0x1180000000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART2_LCR"               ,	   0x1180000000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART2_LSR"               ,	   0x1180000000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART2_MCR"               ,	   0x1180000000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART2_MSR"               ,	   0x1180000000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART2_RBR"               ,	   0x1180000000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART2_RFL"               ,	   0x1180000000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART2_RFW"               ,	   0x1180000000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART2_SBCR"              ,	   0x1180000000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART2_SCR"               ,	   0x1180000000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART2_SFE"               ,	   0x1180000000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART2_SRR"               ,	   0x1180000000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART2_SRT"               ,	   0x1180000000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART2_SRTS"              ,	   0x1180000000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART2_STT"               ,	   0x1180000000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"MIO_UART2_TFL"               ,	   0x1180000000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"MIO_UART2_TFR"               ,	   0x1180000000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"MIO_UART2_THR"               ,	   0x1180000000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"MIO_UART2_USR"               ,	   0x1180000000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"MIX1_BIST"                   ,	   0x1070000100878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	400},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"MIX1_CTL"                    ,	   0x1070000100820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	401},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"MIX1_INTENA"                 ,	   0x1070000100850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	402},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"MIX1_IRCNT"                  ,	   0x1070000100830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	403},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"MIX1_IRHWM"                  ,	   0x1070000100828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	404},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"MIX1_IRING1"                 ,	   0x1070000100810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	405},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"MIX1_IRING2"                 ,	   0x1070000100818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	406},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"MIX1_ISR"                    ,	   0x1070000100848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	407},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
+	{"MIX1_ORCNT"                  ,	   0x1070000100840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	408},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
+	{"MIX1_ORHWM"                  ,	   0x1070000100838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	409},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"MIX1_ORING1"                 ,	   0x1070000100800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	410},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	411},
+	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	411},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
+	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	412},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	413},
+	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	414},
+	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	415},
+	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	416},
+	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	417},
+	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	418},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	419},
+	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	420},
+	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	421},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	422},
+	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	423},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	424},
+	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	425},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	426},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	427},
+	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	428},
+	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	429},
+	{"NPEI_DMA_STATE1_P1"          ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	430},
+	{"NPEI_DMA_STATE2_P1"          ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	431},
+	{"NPEI_DMA_STATE3_P1"          ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	432},
+	{"NPEI_DMA_STATE4_P1"          ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	433},
+	{"NPEI_INT_A_ENB"              ,	   0x11F0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	434},
+	{"NPEI_INT_A_ENB2"             ,	   0x11F000000BCE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	435},
+	{"NPEI_INT_A_SUM"              ,	   0x11F0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	436},
+	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	437},
+	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	438},
+	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_INT_SUM2"               ,	   0x11F000000BCC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	449},
+	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
+	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
+	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
+	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
+	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	464},
+	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	465},
+	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	466},
+	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	467},
+	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	468},
+	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
+	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	470},
+	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	471},
+	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	472},
+	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	473},
+	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	474},
+	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	475},
+	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	476},
+	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	477},
+	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	478},
+	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	479},
+	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	480},
+	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	481},
+	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	482},
+	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	483},
+	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	484},
+	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	485},
+	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	486},
+	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	487},
+	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	488},
+	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	489},
+	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	490},
+	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	491},
+	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	492},
+	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	493},
+	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	494},
+	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	495},
+	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	496},
+	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	497},
+	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	498},
+	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	499},
+	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	500},
+	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	501},
+	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	502},
+	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	503},
+	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	504},
+	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	505},
+	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	506},
+	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	507},
+	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	508},
+	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	509},
+	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	510},
+	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	511},
+	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	512},
+	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	513},
+	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	514},
+	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	515},
+	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	516},
+	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	517},
+	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	518},
+	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	519},
+	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	520},
+	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	521},
+	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	522},
+	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	523},
+	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	524},
+	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	525},
+	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	526},
+	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	527},
+	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	528},
+	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	529},
+	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	530},
+	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	531},
+	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	532},
+	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	533},
+	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	534},
+	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	535},
+	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	536},
+	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	537},
+	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	538},
+	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	539},
+	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	540},
+	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
+	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
+	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	547},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	548},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	549},
+	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
+	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	550},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	551},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	552},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	553},
+	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
+	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	554},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	555},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	556},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	557},
+	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
+	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	558},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	559},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	560},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	561},
+	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
+	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	562},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	563},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	564},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	565},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	566},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	567},
+	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
+	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	568},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	569},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	570},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	571},
+	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
+	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	572},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	573},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	574},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	575},
+	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	576},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	577},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	578},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	579},
+	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	580},
+	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
+	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	581},
+	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
+	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	582},
+	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
+	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	583},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	584},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	585},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	586},
+	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
+	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	587},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	588},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	589},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	590},
+	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
+	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	591},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	592},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	593},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	594},
+	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
+	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	595},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	596},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	597},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	598},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	599},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	600},
+	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	601},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	602},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	603},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	604},
+	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	605},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	606},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	607},
+	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	608},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	609},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	610},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	611},
+	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	612},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	613},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	614},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	615},
+	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
+	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	616},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	617},
+	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	623},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	624},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	625},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	626},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	627},
+	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	628},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	629},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	630},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	631},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	632},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	633},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	634},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	635},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	636},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	637},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	638},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	639},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	640},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	641},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	642},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	643},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	644},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	645},
+	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	646},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	647},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	648},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	649},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	650},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	651},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	652},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	653},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	654},
+	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	655},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	656},
+	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	657},
+	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	658},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	659},
+	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	660},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	661},
+	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	662},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	663},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	664},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	665},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	666},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	667},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	668},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	669},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	670},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	671},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	672},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800A0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	673},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800A0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	674},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	675},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	676},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	677},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800A00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	678},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	679},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	680},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	681},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	682},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	683},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	684},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	685},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	686},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	687},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	688},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	689},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	690},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	691},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	692},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	693},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	745},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	746},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	747},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	748},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	749},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	750},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	751},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	752},
+	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	753},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	754},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	755},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	756},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	757},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	758},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	759},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	760},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	761},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	762},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	763},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	764},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	765},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	766},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	767},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	816},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	817},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	818},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	819},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	820},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	821},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	822},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	823},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	824},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	825},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	826},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	827},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	828},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC1_DAINT"                 ,	   0x17F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	829},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
+	{"USBC1_DAINTMSK"              ,	   0x17F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	830},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC1_DCFG"                  ,	   0x17F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	831},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC1_DCTL"                  ,	   0x17F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	832},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL000"            ,	   0x17F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL001"            ,	   0x17F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL002"            ,	   0x17F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL003"            ,	   0x17F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC1_DIEPCTL004"            ,	   0x17F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	833},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT000"            ,	   0x17F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT001"            ,	   0x17F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT002"            ,	   0x17F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT003"            ,	   0x17F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC1_DIEPINT004"            ,	   0x17F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	834},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
+	{"USBC1_DIEPMSK"               ,	   0x17F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	835},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ000"           ,	   0x17F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ001"           ,	   0x17F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ002"           ,	   0x17F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ003"           ,	   0x17F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC1_DIEPTSIZ004"           ,	   0x17F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	836},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL000"            ,	   0x17F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL001"            ,	   0x17F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL002"            ,	   0x17F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL003"            ,	   0x17F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC1_DOEPCTL004"            ,	   0x17F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	837},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT000"            ,	   0x17F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT001"            ,	   0x17F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT002"            ,	   0x17F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT003"            ,	   0x17F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC1_DOEPINT004"            ,	   0x17F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	838},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
+	{"USBC1_DOEPMSK"               ,	   0x17F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	839},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ000"           ,	   0x17F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ001"           ,	   0x17F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ002"           ,	   0x17F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ003"           ,	   0x17F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC1_DOEPTSIZ004"           ,	   0x17F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	840},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ001"           ,	   0x17F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ002"           ,	   0x17F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ003"           ,	   0x17F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC1_DPTXFSIZ004"           ,	   0x17F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	841},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
+	{"USBC1_DSTS"                  ,	   0x17F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	842},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
+	{"USBC1_DTKNQR1"               ,	   0x17F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	843},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
+	{"USBC1_DTKNQR2"               ,	   0x17F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	844},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
+	{"USBC1_DTKNQR3"               ,	   0x17F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	845},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
+	{"USBC1_DTKNQR4"               ,	   0x17F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	846},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
+	{"USBC1_GAHBCFG"               ,	   0x17F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	847},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
+	{"USBC1_GHWCFG1"               ,	   0x17F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	848},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
+	{"USBC1_GHWCFG2"               ,	   0x17F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	849},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
+	{"USBC1_GHWCFG3"               ,	   0x17F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	850},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
+	{"USBC1_GHWCFG4"               ,	   0x17F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	851},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
+	{"USBC1_GINTMSK"               ,	   0x17F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	852},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
+	{"USBC1_GINTSTS"               ,	   0x17F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	853},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
+	{"USBC1_GNPTXFSIZ"             ,	   0x17F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	854},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
+	{"USBC1_GNPTXSTS"              ,	   0x17F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	855},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
+	{"USBC1_GOTGCTL"               ,	   0x17F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	856},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
+	{"USBC1_GOTGINT"               ,	   0x17F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	857},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
+	{"USBC1_GRSTCTL"               ,	   0x17F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	858},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC1_GRXFSIZ"               ,	   0x17F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	859},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
+	{"USBC1_GRXSTSPD"              ,	   0x17F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	860},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC1_GRXSTSPH"              ,	   0x17F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	861},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC1_GRXSTSRD"              ,	   0x17F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	862},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC1_GRXSTSRH"              ,	   0x17F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	863},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC1_GSNPSID"               ,	   0x17F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	864},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
+	{"USBC1_GUSBCFG"               ,	   0x17F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	865},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
+	{"USBC1_HAINT"                 ,	   0x17F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	866},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
+	{"USBC1_HAINTMSK"              ,	   0x17F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	867},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR000"             ,	   0x17F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR001"             ,	   0x17F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR002"             ,	   0x17F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR003"             ,	   0x17F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR004"             ,	   0x17F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR005"             ,	   0x17F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR006"             ,	   0x17F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC1_HCCHAR007"             ,	   0x17F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	868},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
+	{"USBC1_HCFG"                  ,	   0x17F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	869},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT000"              ,	   0x17F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT001"              ,	   0x17F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT002"              ,	   0x17F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT003"              ,	   0x17F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT004"              ,	   0x17F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT005"              ,	   0x17F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT006"              ,	   0x17F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC1_HCINT007"              ,	   0x17F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	870},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK000"           ,	   0x17F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK001"           ,	   0x17F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK002"           ,	   0x17F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK003"           ,	   0x17F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK004"           ,	   0x17F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK005"           ,	   0x17F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK006"           ,	   0x17F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC1_HCINTMSK007"           ,	   0x17F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	871},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT000"             ,	   0x17F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT001"             ,	   0x17F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT002"             ,	   0x17F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT003"             ,	   0x17F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT004"             ,	   0x17F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT005"             ,	   0x17F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT006"             ,	   0x17F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC1_HCSPLT007"             ,	   0x17F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	872},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ000"             ,	   0x17F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ001"             ,	   0x17F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ002"             ,	   0x17F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ003"             ,	   0x17F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ004"             ,	   0x17F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ005"             ,	   0x17F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ006"             ,	   0x17F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC1_HCTSIZ007"             ,	   0x17F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	873},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	874},
+	{"USBC1_HFIR"                  ,	   0x17F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	874},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	875},
+	{"USBC1_HFNUM"                 ,	   0x17F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	875},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	876},
+	{"USBC1_HPRT"                  ,	   0x17F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	876},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	877},
+	{"USBC1_HPTXFSIZ"              ,	   0x17F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	877},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	878},
+	{"USBC1_HPTXSTS"               ,	   0x17F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	878},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO000"          ,	   0x17F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO001"          ,	   0x17F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO002"          ,	   0x17F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO003"          ,	   0x17F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO004"          ,	   0x17F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO005"          ,	   0x17F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO006"          ,	   0x17F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC1_NPTXDFIFO007"          ,	   0x17F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	879},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	880},
+	{"USBC1_PCGCCTL"               ,	   0x17F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	880},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"USBN1_BIST_STATUS"           ,	   0x11800780007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"USBN1_CLK_CTL"               ,	   0x1180078000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
+	{"USBN1_CTL_STATUS"            ,	   0x17F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	883},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
+	{"USBN1_DMA0_INB_CHN0"         ,	   0x17F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	884},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
+	{"USBN1_DMA0_INB_CHN1"         ,	   0x17F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	885},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
+	{"USBN1_DMA0_INB_CHN2"         ,	   0x17F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	886},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
+	{"USBN1_DMA0_INB_CHN3"         ,	   0x17F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	887},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
+	{"USBN1_DMA0_INB_CHN4"         ,	   0x17F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	888},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
+	{"USBN1_DMA0_INB_CHN5"         ,	   0x17F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	889},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
+	{"USBN1_DMA0_INB_CHN6"         ,	   0x17F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	890},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
+	{"USBN1_DMA0_INB_CHN7"         ,	   0x17F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	891},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	892},
+	{"USBN1_DMA0_OUTB_CHN0"        ,	   0x17F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	892},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	893},
+	{"USBN1_DMA0_OUTB_CHN1"        ,	   0x17F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	893},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	894},
+	{"USBN1_DMA0_OUTB_CHN2"        ,	   0x17F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	894},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	895},
+	{"USBN1_DMA0_OUTB_CHN3"        ,	   0x17F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	895},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	896},
+	{"USBN1_DMA0_OUTB_CHN4"        ,	   0x17F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	896},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	897},
+	{"USBN1_DMA0_OUTB_CHN5"        ,	   0x17F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	897},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
+	{"USBN1_DMA0_OUTB_CHN6"        ,	   0x17F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	898},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
+	{"USBN1_DMA0_OUTB_CHN7"        ,	   0x17F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	899},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
+	{"USBN1_DMA_TEST"              ,	   0x17F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	900},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
+	{"USBN1_INT_ENB"               ,	   0x1180078000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	901},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	902},
+	{"USBN1_INT_SUM"               ,	   0x1180078000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	902},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	903},
+	{"USBN1_USBP_CTL_STATUS"       ,	   0x1180078000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	903},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_25"              ,	23,	3,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYP_EN"                      ,	16,	1,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	2,	"RAZ",	1,	1,	0,	0},
+	{"NCTL1"                       ,	32,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"PCTL1"                       ,	40,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYP_EN1"                     ,	48,	1,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	2,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	3,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"DUPLEX"                      ,	2,	1,	4,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_EN"                       ,	4,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	4,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	9,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	10,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	11,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	11,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	12,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	12,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	12,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	12,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	13,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	13,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	14,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	14,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	15,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	16,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	16,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	17,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	17,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	18,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	18,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"MAXERR"                      ,	2,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	19,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	19,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	20,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	21,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	21,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	22,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	22,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	32,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	32,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	33,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	35,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	35,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	36,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	36,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	37,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	37,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	38,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	38,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	39,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	39,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	40,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	40,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	40,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	3,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	71,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	4,	72,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	72,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	4,	73,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	73,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	74,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	74,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	75,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	76,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	76,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	76,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	77,	"R/W",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	78,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	78,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	79,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	79,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	79,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	80,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	80,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	80,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	80,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	80,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	81,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	81,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	81,	"RO",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	81,	"RO",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	81,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	81,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	82,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	83,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	4,	84,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	84,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	85,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	85,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	4,	86,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	86,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	87,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	88,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	3,	88,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	88,	"RAZ",	1,	1,	0,	0},
+	{"QLM_DCOK"                    ,	0,	2,	89,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	89,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	2,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	90,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	1,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	90,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	90,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	90,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	91,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	91,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	91,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	2,	91,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_60"              ,	42,	19,	91,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	91,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	91,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	91,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	92,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	92,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	93,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	93,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	94,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	94,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	95,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	95,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	96,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	96,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	97,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	97,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	97,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	97,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	98,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	98,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	99,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	99,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	100,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	101,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	101,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	102,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	102,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	103,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	103,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	104,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	104,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	104,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	105,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	105,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	105,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	106,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	106,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	107,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	107,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	108,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	108,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	108,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	108,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	108,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	108,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	108,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	109,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	109,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	110,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	110,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	111,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	111,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	111,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	111,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	112,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	112,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	112,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	2,	112,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	112,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	2,	112,	"RO",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	112,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	113,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	113,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	114,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	114,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	114,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	114,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	114,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	114,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	114,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	114,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	114,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	114,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	115,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	116,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	117,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	118,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	119,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	120,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	121,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	121,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	122,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	122,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	122,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	122,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	123,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	123,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	124,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	124,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	124,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	124,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	124,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	125,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	125,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	125,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	125,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	125,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	125,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	125,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	125,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	125,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	126,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	126,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	127,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	127,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	127,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	127,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	127,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	128,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	128,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	128,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	128,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	128,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	128,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	128,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	129,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	129,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	130,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	130,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	131,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	131,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	132,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	132,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	133,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	133,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	134,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	134,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	135,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	135,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	136,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	136,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	137,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	137,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	138,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	138,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	139,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	139,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	140,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	140,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	141,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	141,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	141,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	142,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	142,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	143,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	143,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	144,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	144,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	145,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	145,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	145,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	145,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	146,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	146,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	146,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	147,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	147,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	148,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	148,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	148,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	148,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	148,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	149,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	149,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	150,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	150,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	151,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	151,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	151,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	152,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	152,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	152,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	152,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	152,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	153,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	153,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	154,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	154,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	154,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	155,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	155,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	156,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	156,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	157,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	157,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	158,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	158,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	158,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	159,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	159,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	160,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	160,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	161,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	161,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	162,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	162,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	163,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	163,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	164,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	164,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	165,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	165,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	166,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	166,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	167,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	167,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	168,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	168,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	169,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	169,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	170,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	170,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	171,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	171,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	172,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	172,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	173,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	173,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	174,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	174,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	175,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	175,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	176,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	176,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	177,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	177,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	178,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	178,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	179,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	179,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	180,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	180,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	180,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	181,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	181,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	181,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	181,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	182,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	182,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	182,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	183,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	183,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	184,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	184,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	185,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	185,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	185,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	186,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	186,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	187,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	187,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	188,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	188,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	189,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	189,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	189,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	189,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	189,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	189,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	190,	"R/W",	0,	0,	8ull,	8ull},
+	{"EN"                          ,	4,	1,	190,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	190,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	191,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	191,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	192,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	192,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	193,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	193,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	194,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	194,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	195,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	195,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	196,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	196,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	197,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	197,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	198,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	198,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	198,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	198,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	198,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	199,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	199,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	200,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	200,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	200,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	201,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	202,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	202,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	202,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	202,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	202,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	203,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	203,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	203,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	203,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	203,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	204,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	205,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	206,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	206,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	207,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	207,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	208,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	208,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	209,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	210,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	211,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	211,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	211,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	211,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	211,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	212,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	212,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	212,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	212,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	212,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	213,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	214,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	215,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	215,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	216,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	216,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	217,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	218,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	218,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	219,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	220,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	221,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	222,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	222,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	40,	223,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	223,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	224,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	225,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	225,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	225,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	226,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	227,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	227,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	228,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	229,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	229,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	230,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	230,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	231,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	232,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	233,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	233,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	234,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	234,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	235,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	235,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	236,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	237,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	238,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	238,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	238,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	238,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	238,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	239,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	239,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	239,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	239,	"RO",	0,	0,	8ull,	8ull},
+	{"RESERVED_44_63"              ,	44,	20,	239,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	240,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	240,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	241,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	241,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	241,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	241,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	241,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	241,	"RO",	0,	0,	8ull,	8ull},
+	{"RESERVED_61_63"              ,	61,	3,	241,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	242,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	242,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	243,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	243,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	244,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	4,	245,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	245,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	246,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	246,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	246,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	246,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	246,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	247,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	247,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	247,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	248,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	248,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	248,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	248,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	249,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	249,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	249,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	250,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	250,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	251,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	251,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	10,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	252,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	252,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"ILC"                         ,	10,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	253,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC0"                        ,	16,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC1"                        ,	17,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC2"                        ,	18,	1,	253,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	253,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	254,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	254,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	255,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	255,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	255,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	255,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	255,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	255,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	255,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	255,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_17"              ,	14,	4,	255,	"RAZ",	1,	1,	0,	0},
+	{"LBIST"                       ,	18,	1,	255,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSTRUN"                      ,	19,	1,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	255,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	2,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_9"                ,	8,	2,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	3,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	256,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	257,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	257,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	257,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PLC0RMSK"                    ,	0,	32,	258,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC1RMSK"                    ,	32,	32,	258,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC2RMSK"                    ,	0,	32,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILCRMSK"                     ,	32,	32,	259,	"R/W",	0,	0,	0ull,	0ull},
+	{"OOB1EN"                      ,	0,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB2EN"                      ,	1,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB3EN"                      ,	2,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TSECEN"                    ,	3,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TDEDEN"                    ,	4,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DSECEN"                    ,	5,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDEDEN"                    ,	6,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKENA"                      ,	7,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCK2ENA"                     ,	8,	1,	260,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	260,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OOB1"                        ,	0,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB2"                        ,	1,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB3"                        ,	2,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TSEC"                      ,	3,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TDED"                      ,	4,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DSEC"                      ,	5,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DDED"                      ,	6,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK"                         ,	7,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK2"                        ,	8,	1,	261,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	261,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	262,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	262,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	262,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	262,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	263,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	263,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	3,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	3,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	265,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	9,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	9,	18,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	3,	267,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_3"                ,	3,	1,	267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STPARTDIS"                   ,	4,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	267,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STENA"                       ,	0,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWBENA"                      ,	1,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	268,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	270,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	270,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	270,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	270,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	270,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	270,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	271,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	271,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	271,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	271,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	271,	"RO",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	272,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	273,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	273,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP0GRP"                      ,	0,	2,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP1GRP"                      ,	2,	2,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP2GRP"                      ,	4,	2,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP3GRP"                      ,	6,	2,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	274,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	276,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	278,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	279,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	279,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	280,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	281,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	281,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	281,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	10,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	284,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	285,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	286,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	287,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	287,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_256K"                   ,	34,	1,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_128K"                   ,	35,	1,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	3,	288,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	289,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	289,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	289,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	289,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	289,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	9,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	289,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	289,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	289,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	289,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	289,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	289,	"RAZ",	0,	0,	0ull,	0ull},
+	{"START"                       ,	0,	1,	290,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	290,	"RAZ",	1,	0,	0,	0ull},
+	{"MRD"                         ,	0,	3,	291,	"RO",	1,	0,	0,	0ull},
+	{"MRF"                         ,	3,	1,	291,	"RO",	1,	0,	0,	0ull},
+	{"MWC"                         ,	4,	1,	291,	"RO",	1,	0,	0,	0ull},
+	{"MWD"                         ,	5,	3,	291,	"RO",	1,	0,	0,	0ull},
+	{"MWF"                         ,	8,	1,	291,	"RO",	1,	0,	0,	0ull},
+	{"CSRE2D"                      ,	9,	1,	291,	"RO",	1,	0,	0,	0ull},
+	{"CSRD2E"                      ,	10,	1,	291,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	291,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL_DAT"                    ,	0,	5,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_11"               ,	5,	7,	292,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	292,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	292,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	292,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	292,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	293,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	293,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	293,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	11,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	293,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	293,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	293,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	293,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	293,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	294,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	294,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEQUENCE"                    ,	10,	3,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLEPOWER"                   ,	13,	3,	294,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	16,	4,	294,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	20,	1,	294,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_63"              ,	21,	43,	294,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	295,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	296,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	297,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	297,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	297,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	297,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	297,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	297,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	297,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	297,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	297,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	298,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	298,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	298,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	298,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	0,	5,	299,	"R/W",	0,	1,	0ull,	0},
+	{"DLL90_ENA"                   ,	5,	1,	299,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	6,	1,	299,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	7,	1,	299,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	299,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	300,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	300,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	300,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	300,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	301,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	302,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	302,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	303,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	303,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	304,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	304,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	305,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	305,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	305,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	305,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	305,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	305,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	305,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	305,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	305,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	305,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	305,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	306,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	306,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	306,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	306,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	306,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	306,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	306,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	306,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	306,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	307,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	308,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	308,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	309,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	309,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	309,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	309,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	309,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	309,	"R/W",	0,	0,	1ull,	0ull},
+	{"FASTEN_N"                    ,	28,	1,	309,	"R/W",	0,	0,	0ull,	1ull},
+	{"BYPASS"                      ,	29,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	309,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	310,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	310,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_21"               ,	2,	20,	310,	"RAZ",	1,	1,	0,	0},
+	{"DDR__PCTL"                   ,	22,	5,	310,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	27,	5,	310,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	310,	"RAZ",	1,	1,	0,	0},
+	{"BNK"                         ,	0,	3,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	311,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COL"                         ,	4,	12,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW"                         ,	16,	16,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"PATTERN"                     ,	32,	8,	311,	"R/W",	0,	0,	170ull,	170ull},
+	{"RANKMASK"                    ,	40,	4,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	311,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE"                        ,	0,	4,	312,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	312,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	16,	16,	312,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	312,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	4,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	8,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	12,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	16,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	20,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	24,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	28,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	32,	4,	313,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	36,	2,	313,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	313,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL"                        ,	0,	5,	314,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	314,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	314,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	314,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	314,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	314,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO1"                    ,	4,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO2"                    ,	8,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_LO3"                    ,	12,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI0"                    ,	16,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI1"                    ,	20,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI2"                    ,	24,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RODT_HI3"                    ,	28,	4,	315,	"R/W",	0,	0,	15ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	315,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	316,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	316,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	316,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	316,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	316,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WODT_D2_R0"                  ,	0,	8,	317,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	8,	8,	317,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	16,	8,	317,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	24,	8,	317,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	317,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NCBI"                        ,	0,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA"                         ,	2,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	3,	1,	318,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	318,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	319,	"R/W",	0,	1,	31ull,	0},
+	{"PCTL"                        ,	5,	5,	319,	"R/W",	0,	1,	31ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	319,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	320,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	320,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	320,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	320,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	321,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	321,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	321,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	322,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	323,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	323,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	323,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	323,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	323,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	323,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	323,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	323,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	324,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	324,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	325,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	325,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	326,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	326,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	326,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	327,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	327,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	327,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	328,	"R/W",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	329,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	329,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	329,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	329,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	329,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	329,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	329,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	329,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	330,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	330,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	330,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	331,	"R/W",	0,	0,	26ull,	26ull},
+	{"RESERVED_6_7"                ,	6,	2,	331,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	331,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	331,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	331,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	331,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	332,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	333,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	333,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	334,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	334,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	4,	335,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_15"               ,	4,	12,	335,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	335,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	335,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	335,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	335,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	335,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	335,	"RO",	1,	1,	0,	0},
+	{"NOKASU"                      ,	29,	1,	335,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_31"              ,	30,	2,	335,	"RAZ",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	335,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	335,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	335,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	336,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	336,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	336,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	336,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	336,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	336,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	336,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	336,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	337,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	337,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	337,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	337,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	338,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	339,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	339,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	339,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	340,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	340,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	341,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	341,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	341,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	341,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	341,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	341,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	342,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	342,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	342,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	342,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	342,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	342,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	342,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	343,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	343,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	344,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	344,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	3,	345,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_3_63"               ,	3,	61,	345,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	346,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	346,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	346,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	346,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	346,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	346,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	346,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	346,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	346,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	347,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	347,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	347,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	347,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	347,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	347,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	347,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	347,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	347,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	348,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	348,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	348,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	349,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	349,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	349,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	350,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	350,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	351,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	351,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	352,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	352,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	353,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	353,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	353,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	353,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	353,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	353,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	353,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	354,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	354,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	355,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	355,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	355,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	356,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	356,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	356,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	356,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	357,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	357,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	357,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	357,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	358,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	358,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	358,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	358,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	358,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	358,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	358,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	358,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	358,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	359,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	359,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	360,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	360,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	360,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	360,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	360,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	360,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	360,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	360,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	360,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	361,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	361,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	362,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	362,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	363,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	363,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	363,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	363,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	364,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	365,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	366,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	366,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	367,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	367,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	367,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	367,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	368,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	369,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	369,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	370,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	370,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	371,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	371,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	372,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	372,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	373,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	373,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	374,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	374,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	374,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	374,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	374,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	374,	"RAZ",	1,	1,	0,	0},
+	{"DLH"                         ,	0,	8,	375,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	375,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	376,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	377,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	377,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	378,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	378,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	378,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	378,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	378,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	378,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	378,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	379,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	379,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	380,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	380,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	380,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	380,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	380,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	380,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	380,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	381,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	381,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	381,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	381,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	382,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	382,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	382,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	382,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	382,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	382,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	382,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	382,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	383,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	383,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	383,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	383,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	383,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	383,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	383,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	383,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	383,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	384,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	384,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	385,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	385,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	385,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	385,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	385,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	385,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	385,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	385,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	385,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	386,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	386,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	387,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	387,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	388,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	388,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	388,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	388,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	389,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	389,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	390,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	390,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	391,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	391,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	392,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	392,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	392,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	392,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	393,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	393,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	394,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	395,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	395,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	396,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	396,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	397,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	397,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	398,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	398,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	399,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	399,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	399,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	399,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	399,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	399,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	400,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	400,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	400,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	400,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	400,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	401,	"R/W",	0,	0,	1ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	401,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	401,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	401,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	401,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	402,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	402,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	403,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	403,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	404,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	404,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	405,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	33,	405,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	405,	"RAZ",	1,	1,	0,	0},
+	{"ISIZE"                       ,	40,	20,	405,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	405,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	406,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	406,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	406,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	406,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	407,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	407,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	407,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	408,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	408,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	409,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	409,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	410,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	33,	410,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	410,	"RAZ",	1,	1,	0,	0},
+	{"OSIZE"                       ,	40,	20,	410,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	410,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	411,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	411,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	411,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	411,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	412,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	412,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	412,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	413,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	413,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	413,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	413,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	413,	"RAZ",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DR3_MEM"                     ,	2,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF3"                        ,	3,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF2"                        ,	4,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF1"                        ,	5,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF0"                        ,	6,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM1"                        ,	7,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM0"                        ,	8,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P1"                     ,	9,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_CO"                     ,	19,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_NO"                     ,	20,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_PO"                     ,	21,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_CO"                     ,	22,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_NO"                     ,	23,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_PO"                     ,	24,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P1"                      ,	25,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DR2_MEM"                     ,	31,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_PST"                      ,	32,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_PST"                      ,	33,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_PST"                      ,	34,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_PST"                      ,	35,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DR1_MEM"                     ,	36,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_MEM"                      ,	37,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_MEM"                      ,	38,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_MEM"                      ,	39,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_MEM"                      ,	40,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"DR0_MEM"                     ,	41,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_MEM3"                     ,	42,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_MEM2"                     ,	43,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_MEM1"                     ,	44,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_MEM0"                     ,	45,	1,	414,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	414,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	415,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	415,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	415,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	415,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	415,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	415,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	415,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	415,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	415,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	415,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	415,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	415,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	415,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	416,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	416,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	416,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	416,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	416,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	416,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	416,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	416,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	416,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	416,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	416,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	416,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	416,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	417,	"RO",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	8,	1,	417,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_12"               ,	9,	4,	417,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ARB"                         ,	13,	1,	417,	"R/W",	0,	0,	0ull,	1ull},
+	{"LNK_RST"                     ,	14,	1,	417,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_15"              ,	15,	1,	417,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	417,	"R/W",	0,	0,	0ull,	0ull},
+	{"P0_NTAGS"                    ,	32,	6,	417,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	38,	6,	417,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_44_63"              ,	44,	20,	417,	"RAZ",	1,	1,	0,	0},
+	{"C0_B0_D"                     ,	0,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_WI_D"                     ,	1,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_B0_D"                     ,	2,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_WI_D"                     ,	3,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_B1_S"                     ,	4,	3,	418,	"R/W",	0,	0,	1ull,	1ull},
+	{"C1_B1_S"                     ,	7,	3,	418,	"R/W",	0,	0,	1ull,	1ull},
+	{"C0_W_FLT"                    ,	10,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_W_FLT"                    ,	11,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRRS"                        ,	12,	3,	418,	"R/W",	0,	0,	2ull,	2ull},
+	{"MPS"                         ,	15,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	418,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	419,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	419,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	419,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	419,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	419,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	420,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	420,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	420,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	23,	2,	420,	"RO",	1,	1,	0,	0},
+	{"QLM1_MODE"                   ,	25,	2,	420,	"RO",	1,	1,	0,	0},
+	{"QLM0_REV_LANES"              ,	27,	1,	420,	"RO",	1,	1,	0,	0},
+	{"QLM0_LINK_WIDTH"             ,	28,	1,	420,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	420,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	421,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	421,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	422,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	422,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	422,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	423,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	423,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	424,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	424,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	424,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	425,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	425,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	426,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	426,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	32,	427,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	427,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0"                        ,	0,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1"                        ,	32,	32,	428,	"R/W",	0,	1,	0ull,	0},
+	{"CSIZE"                       ,	0,	14,	429,	"R/W",	0,	1,	0ull,	0},
+	{"O_MODE"                      ,	14,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	429,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	429,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	429,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	429,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	429,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	429,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA0_ENB"                    ,	34,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_ENB"                    ,	35,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2_ENB"                    ,	36,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3_ENB"                    ,	37,	1,	429,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_38_63"              ,	38,	26,	429,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	430,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_REQST"                    ,	5,	5,	430,	"RO",	0,	1,	0ull,	0},
+	{"D2_REQST"                    ,	10,	5,	430,	"RO",	0,	1,	0ull,	0},
+	{"D1_REQST"                    ,	15,	5,	430,	"RO",	0,	1,	0ull,	0},
+	{"D0_REQST"                    ,	20,	5,	430,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_31"              ,	25,	7,	430,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_DIFST"                    ,	32,	7,	430,	"RO",	0,	1,	0ull,	0},
+	{"D2_DIFST"                    ,	39,	7,	430,	"RO",	0,	1,	0ull,	0},
+	{"D1_DIFST"                    ,	46,	7,	430,	"RO",	0,	1,	0ull,	0},
+	{"D0_DIFST"                    ,	53,	7,	430,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	430,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_8"                ,	0,	9,	431,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_DFFST"                    ,	9,	9,	431,	"RO",	0,	1,	0ull,	0},
+	{"D2_DFFST"                    ,	18,	9,	431,	"RO",	0,	1,	0ull,	0},
+	{"D1_DFFST"                    ,	27,	9,	431,	"RO",	0,	1,	0ull,	0},
+	{"D0_DFFST"                    ,	36,	9,	431,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	431,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_DREST"                    ,	0,	15,	432,	"RO",	0,	1,	0ull,	0},
+	{"D2_DREST"                    ,	15,	15,	432,	"RO",	0,	1,	0ull,	0},
+	{"D1_DREST"                    ,	30,	15,	432,	"RO",	0,	1,	0ull,	0},
+	{"D0_DREST"                    ,	45,	15,	432,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	432,	"RAZ",	0,	0,	0ull,	0ull},
+	{"D3_DWEST"                    ,	0,	13,	433,	"RO",	0,	1,	0ull,	0},
+	{"D2_DWEST"                    ,	13,	13,	433,	"RO",	0,	1,	0ull,	0},
+	{"D1_DWEST"                    ,	26,	13,	433,	"RO",	0,	1,	0ull,	0},
+	{"D0_DWEST"                    ,	39,	13,	433,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	433,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DMA0_CPL"                    ,	0,	1,	434,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_CPL"                    ,	1,	1,	434,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	434,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	435,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_CPL"                    ,	1,	1,	435,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	435,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	436,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_CPL"                    ,	1,	1,	436,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	436,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_8"                ,	8,	1,	437,	"RAZ",	1,	1,	0,	0},
+	{"DMA0FI"                      ,	9,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_ER"                     ,	20,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_DR"                     ,	22,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_ER"                     ,	27,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_DR"                     ,	29,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_A"                       ,	61,	1,	437,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_62_62"              ,	62,	1,	437,	"RAZ",	0,	1,	0ull,	0},
+	{"MIO_INTA"                    ,	63,	1,	437,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_RTO"                     ,	0,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_8_8"                ,	8,	1,	438,	"RAZ",	1,	1,	0,	0},
+	{"DMA0FI"                      ,	9,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_ER"                     ,	20,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_DR"                     ,	22,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_ER"                     ,	27,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_DR"                     ,	29,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	438,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_A"                       ,	61,	1,	438,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	438,	"RAZ",	0,	1,	0ull,	0},
+	{"RML_RTO"                     ,	0,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	439,	"RAZ",	1,	1,	0,	0},
+	{"DMA0FI"                      ,	9,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_18"              ,	15,	4,	439,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_ER"                     ,	20,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS0_DR"                     ,	22,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_ER"                     ,	27,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS1_DR"                     ,	29,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	439,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INT_A"                       ,	61,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	439,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	440,	"RAZ",	1,	1,	0,	0},
+	{"DMA0FI"                      ,	9,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_18"              ,	15,	4,	440,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_ER"                     ,	20,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_DR"                     ,	22,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_ER"                     ,	27,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_DR"                     ,	29,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"INT_A"                       ,	61,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	440,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	441,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	442,	"RO",	0,	1,	0ull,	0},
+	{"TIMER"                       ,	0,	10,	443,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	443,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	443,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	444,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	30,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	31,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	32,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	33,	1,	444,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	444,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	444,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	2,	444,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	41,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	444,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	445,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	446,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	447,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	448,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	449,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	450,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	451,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	452,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	453,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	453,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	453,	"RAZ",	1,	1,	0,	0},
+	{"MSI_INT"                     ,	0,	8,	454,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	454,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	454,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	455,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	455,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	456,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	456,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	456,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	457,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	457,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	457,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	458,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	458,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	458,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"NPEI"                        ,	3,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	15,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASXPCS0"                     ,	22,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"ASXPCS1"                     ,	23,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_27"              ,	24,	4,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	28,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC1"                        ,	29,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	459,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	459,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	460,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	461,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	461,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	461,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	461,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	462,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	462,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	462,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	462,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	462,	"RO",	0,	1,	1ull,	0},
+	{"NPEI"                        ,	47,	1,	462,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	462,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	463,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	463,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	463,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	463,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	463,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	464,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	464,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	464,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	464,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	465,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_1"                ,	0,	2,	466,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	2,	46,	466,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	466,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	466,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	467,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	468,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	468,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	469,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	469,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	470,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	470,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"ISAE"                        ,	0,	1,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	471,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	471,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	471,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	471,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	471,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	471,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	472,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	472,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	472,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	472,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	473,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	473,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	473,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	473,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	473,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	474,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	474,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	474,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	474,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	474,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	475,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	475,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	476,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	477,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	478,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	478,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	478,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	478,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	478,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	479,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	479,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	481,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	482,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	482,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	482,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	482,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	483,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	483,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_6"                ,	0,	7,	484,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	7,	25,	484,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	485,	"WORSL",	0,	0,	127ull,	127ull},
+	{"CISP"                        ,	0,	32,	486,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	487,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	487,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	488,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	488,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	488,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	489,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	489,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"CP"                          ,	0,	8,	490,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	490,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	491,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	491,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	491,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	491,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	492,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	492,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	492,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	492,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	492,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	492,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	493,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	493,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	493,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	493,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	493,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	493,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	493,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	494,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	494,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	494,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	494,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	494,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	495,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	496,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	497,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	498,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	498,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	498,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	498,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	498,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	498,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	498,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	499,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	499,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	499,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	499,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	499,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	499,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	499,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	499,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	499,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	499,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	499,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	500,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	500,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	500,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	500,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	500,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	500,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	500,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	500,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	500,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	500,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	500,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	501,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	501,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	501,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	501,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	501,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	501,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	501,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	501,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	501,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	502,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	502,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	502,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	502,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	502,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	502,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	502,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	502,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	502,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	502,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	502,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	502,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	502,	"RAZ",	1,	1,	0,	0},
+	{"ABP"                         ,	0,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	503,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIC"                         ,	8,	2,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCC"                         ,	10,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	504,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	504,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	504,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	504,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	504,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	504,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	504,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"EMIS"                        ,	23,	1,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	504,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	504,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	505,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	505,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	505,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	506,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	506,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	506,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	507,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	508,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	509,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	510,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	511,	"RO",	0,	0,	1ull,	0ull},
+	{"CV"                          ,	16,	4,	511,	"RO",	0,	0,	1ull,	0ull},
+	{"NCO"                         ,	20,	12,	511,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	512,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	512,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	512,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	512,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	512,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	513,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	513,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	513,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	513,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	514,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	514,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	514,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	514,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	514,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	514,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	514,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	514,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	514,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	515,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	515,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	515,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	515,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	516,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	516,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	516,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	516,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	516,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	517,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	517,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	517,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	517,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	517,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	518,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	519,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	520,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	521,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	522,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	522,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	523,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	524,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	524,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	524,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	524,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	524,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	525,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	525,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	525,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	525,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	525,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	525,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	526,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	526,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	526,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	526,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	526,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_22_24"              ,	22,	3,	526,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	526,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	526,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	527,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	527,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	528,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	528,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	528,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	528,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	528,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	528,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	528,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	529,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	529,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	529,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	530,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	530,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	531,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	532,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	533,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	533,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	534,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	534,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	535,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	535,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	536,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	536,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	536,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	536,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	537,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	537,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	538,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	539,	"RO/WRSL",	0,	0,	72ull,	72ull},
+	{"HEADER_CREDITS"              ,	12,	8,	539,	"RO/WRSL",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	539,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	539,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	539,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	539,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	539,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	540,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	540,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	540,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	540,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	540,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	541,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	541,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	541,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	541,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	541,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	542,	"RO/WRSL",	0,	0,	216ull,	216ull},
+	{"RESERVED_14_15"              ,	14,	2,	542,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	542,	"RO/WRSL",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	542,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	543,	"RO/WRSL",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	543,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	543,	"RO/WRSL",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	543,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	544,	"RO/WRSL",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	544,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	544,	"RO/WRSL",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	544,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	545,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	546,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	547,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	547,	"R/W",	0,	0,	128ull,	128ull},
+	{"ISAE"                        ,	0,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	548,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	548,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	548,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	548,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	548,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	548,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	548,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	548,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	548,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	548,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	548,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"PI"                          ,	8,	8,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	549,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	549,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	550,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	550,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	550,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	550,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	551,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	552,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	553,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	553,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	554,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	554,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	554,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	554,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	554,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	554,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	554,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	554,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	554,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	554,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	554,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	554,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	554,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	554,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	555,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	555,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	556,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	556,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	556,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	556,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	556,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	557,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	558,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	560,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	560,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	561,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	562,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	562,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	562,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	562,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	563,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	563,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	563,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	563,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	563,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	564,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	564,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	564,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	564,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	565,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	565,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	565,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	565,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	566,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	568,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	569,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	569,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	569,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	569,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	569,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	570,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	570,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	570,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	570,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	570,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	570,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	570,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	570,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	571,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	571,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	571,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	571,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	571,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	572,	"R/W",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	572,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	572,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	572,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	572,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	572,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	572,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	572,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	572,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	573,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	573,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	573,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	573,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	573,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	573,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	573,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	573,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	573,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	574,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	575,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	575,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	575,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	575,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	575,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	576,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	576,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	576,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	577,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	577,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	578,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	578,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	578,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	579,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	579,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	579,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	580,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	581,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	582,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	583,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	584,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	584,	"RO",	0,	0,	1ull,	1ull},
+	{"NCO"                         ,	20,	12,	584,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	585,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	585,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	585,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	585,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	585,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	586,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	586,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	586,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	586,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	586,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	587,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	587,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	587,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	587,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	588,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	588,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	588,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	588,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	589,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	589,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	589,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	589,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	589,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	590,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	590,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	590,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	590,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	593,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	594,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	595,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	596,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	596,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	597,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	597,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	598,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	598,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	599,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	600,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	600,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	600,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	600,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	601,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	601,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	601,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	601,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	601,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	602,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	602,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	602,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	602,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	602,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_24"              ,	22,	3,	602,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	602,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	602,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	603,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	603,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	604,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	604,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	604,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	604,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	604,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	604,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	604,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	605,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	605,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	605,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	606,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	606,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	609,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	610,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	610,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	611,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	611,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	612,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	612,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	613,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	613,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	614,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	615,	"R/W",	0,	0,	72ull,	72ull},
+	{"HEADER_CREDITS"              ,	12,	8,	615,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_20_20"              ,	20,	1,	615,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	615,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	615,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	615,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	615,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	616,	"R/W",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	616,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	616,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	616,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	616,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	617,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	617,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_20_20"              ,	20,	1,	617,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	617,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	617,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	618,	"R/W",	0,	0,	216ull,	216ull},
+	{"RESERVED_14_15"              ,	14,	2,	618,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	618,	"R/W",	0,	0,	38ull,	38ull},
+	{"RESERVED_26_31"              ,	26,	6,	618,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	619,	"R/W",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	619,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	619,	"R/W",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	619,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	620,	"R/W",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	620,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	620,	"R/W",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	620,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	621,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	622,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	623,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	623,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	623,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	623,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	623,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	623,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	623,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	623,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	624,	"RAZ",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	624,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	624,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	624,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	624,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	624,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	625,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	625,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	625,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	625,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	626,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	626,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	626,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	627,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	627,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	628,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	628,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	629,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	629,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	630,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	630,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	631,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	631,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	631,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	631,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	632,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	632,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	632,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	632,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	632,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	632,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	632,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	633,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	633,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	633,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	633,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	633,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	633,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	633,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	634,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	635,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	636,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	636,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	636,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	636,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	636,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	636,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	636,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	636,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	637,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	637,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	637,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	637,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	637,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	637,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	637,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	638,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	638,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	638,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	639,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	639,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	640,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	640,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	640,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	640,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	640,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	640,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	640,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	640,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	641,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	642,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	642,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	642,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	642,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	642,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	643,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	643,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	643,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	643,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	643,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	643,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	643,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	643,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	644,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	644,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	645,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	645,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	645,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	645,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	645,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	645,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	645,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	646,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	647,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	647,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	648,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	648,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	648,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	648,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	648,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	649,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	649,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	649,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	649,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	649,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	650,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	650,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	651,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	651,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	651,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	651,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	651,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	651,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	652,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	652,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	652,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	652,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	652,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	652,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	652,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	652,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	653,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	653,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	654,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	654,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	654,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	654,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	654,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA4"                     ,	3,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	4,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	5,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	6,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	7,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	8,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"PTLP_OR"                     ,	9,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"NTLP_OR"                     ,	10,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"CTLP_OR"                     ,	11,	1,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	655,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"RSL_P2E"                     ,	6,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	7,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_P2E"                     ,	8,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_RSL"                     ,	9,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	10,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	11,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	12,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"CTO_P2E"                     ,	13,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	656,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	657,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	657,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	658,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	658,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	659,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	659,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	660,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	660,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"LANE_SWP"                    ,	12,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	13,	2,	660,	"RO",	1,	1,	0,	0},
+	{"PBUS"                        ,	15,	8,	660,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	23,	5,	660,	"RO",	1,	1,	0,	0},
+	{"RESERVED_28_63"              ,	28,	36,	660,	"RAZ",	1,	1,	0,	0},
+	{"PCIERST"                     ,	0,	1,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	661,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	662,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	662,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	663,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	663,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	664,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	665,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	665,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	666,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_38"               ,	0,	39,	667,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	39,	25,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	668,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	668,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	669,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	669,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"NPEI_P"                      ,	0,	5,	670,	"R/W",	0,	0,	2ull,	2ull},
+	{"NPEI_NP"                     ,	5,	5,	670,	"R/W",	0,	0,	2ull,	2ull},
+	{"NPEI_CPL"                    ,	10,	5,	670,	"R/W",	0,	0,	2ull,	2ull},
+	{"PESC_P"                      ,	15,	5,	670,	"R/W",	0,	0,	2ull,	2ull},
+	{"PESC_NP"                     ,	20,	5,	670,	"R/W",	0,	0,	2ull,	2ull},
+	{"PESC_CPL"                    ,	25,	5,	670,	"R/W",	0,	0,	2ull,	2ull},
+	{"PEAI_PPF"                    ,	30,	8,	670,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_38_63"              ,	38,	26,	670,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	18,	671,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	671,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	672,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	675,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	675,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	675,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	676,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	676,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	676,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	676,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	677,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	677,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	677,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	677,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	677,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	677,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	678,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	678,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	678,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	678,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	678,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	678,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	679,	"RAZ",	1,	1,	0,	0},
+	{"BCKPRS"                      ,	2,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	679,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	679,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	680,	"RAZ",	1,	1,	0,	0},
+	{"BCKPRS"                      ,	2,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	680,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	680,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	681,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	681,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	682,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	682,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	682,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	682,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	682,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	682,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	682,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	682,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	683,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	683,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	684,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	684,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	685,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	685,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	685,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	686,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	686,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	686,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	686,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	687,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	687,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	688,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	688,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	689,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	689,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	690,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	690,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	691,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	691,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	692,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	692,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	693,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	693,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	694,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	694,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	695,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	695,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	696,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	696,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	697,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	697,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	698,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	698,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	699,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	699,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	700,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	700,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	701,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	701,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	702,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	702,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	703,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	704,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	704,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	705,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	705,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	706,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	706,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	706,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	707,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	707,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	708,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	708,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	709,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	709,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	709,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	709,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	710,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	710,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	710,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	710,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	710,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	711,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	711,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	711,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	711,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	712,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	712,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	712,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	712,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	712,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	712,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	712,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	712,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	713,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	713,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	713,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	713,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	714,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	714,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	714,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	714,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	714,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	715,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	716,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	716,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	716,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	716,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	716,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	717,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	718,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	718,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	718,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	718,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	718,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	718,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	718,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	718,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	718,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	718,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	718,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	718,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	718,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	719,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	719,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	719,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	719,	"RAZ",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	0,	8,	720,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	720,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	720,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	720,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	720,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	720,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	720,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	720,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	720,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	720,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	720,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	720,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	720,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	721,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	721,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	721,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	721,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	721,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	721,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	722,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	722,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	722,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	722,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	722,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	722,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	722,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	722,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	722,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	723,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	723,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	723,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	723,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	724,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	724,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	724,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	724,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	724,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	724,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	724,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	725,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	725,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	725,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	725,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	725,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	726,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	726,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_PKT"                    ,	8,	24,	726,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	726,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	726,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	727,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	727,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_LIM"                    ,	8,	24,	727,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	727,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	728,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	728,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	728,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	728,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	728,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	728,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	728,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	728,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	728,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	729,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	729,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	729,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	729,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	729,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	730,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	730,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	730,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	730,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	730,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	730,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	730,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	730,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	730,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	730,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	730,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	730,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	730,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	730,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	730,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	730,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	731,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	731,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	64,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	733,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	734,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE5"                     ,	20,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE6"                     ,	24,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE7"                     ,	28,	4,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE8"                     ,	32,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	736,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_40_63"              ,	40,	24,	736,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	10,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	737,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	738,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	738,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	739,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	739,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	739,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	740,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	740,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	740,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	741,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	741,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	741,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	741,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	742,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	742,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	743,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	744,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR"                         ,	0,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	2,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	3,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	4,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	5,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT0"                        ,	6,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT1"                        ,	7,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	8,	1,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	745,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	4,	745,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	745,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	746,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	746,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	747,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	747,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	747,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	747,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	747,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	747,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	747,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	747,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	747,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	747,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	748,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	748,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	749,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	749,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	750,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	750,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	751,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	751,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	752,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	752,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	753,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	753,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	10,	754,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	754,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	755,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	755,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	756,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	756,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	757,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	757,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	757,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	758,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	758,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	758,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	758,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	758,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	9,	759,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	759,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	9,	759,	"R/W",	0,	1,	511ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	759,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	10,	759,	"RO",	0,	1,	503ull,	0},
+	{"RESERVED_34_35"              ,	34,	2,	759,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	10,	759,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	759,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	10,	759,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	759,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	760,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	760,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	761,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	761,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	762,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	762,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	763,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	763,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	763,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	10,	764,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	764,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	10,	764,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	764,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	764,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	764,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	765,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	765,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	765,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	765,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	765,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	9,	766,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	766,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	9,	766,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	766,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	766,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	766,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	766,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	767,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	767,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	768,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	769,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	770,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	771,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	771,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	771,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	771,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	771,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	33,	772,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	772,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	772,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	772,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	772,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	773,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	773,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	773,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	773,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	774,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	774,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	774,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	774,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	774,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	774,	"RAZ",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	774,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	774,	"RAZ",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	774,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	774,	"RAZ",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	775,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	776,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	776,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	776,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	777,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	777,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	777,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	777,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	777,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	777,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	777,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	15,	778,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	778,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OWORDP"                      ,	0,	64,	779,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	780,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	781,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	782,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	782,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	782,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	782,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FPACREDS"                    ,	12,	2,	782,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	782,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	782,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	782,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	782,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	782,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	782,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	782,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	782,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	782,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	782,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	782,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	782,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	782,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	40,	783,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	783,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	783,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	784,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	784,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	40,	785,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	785,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	785,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	786,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	786,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	786,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	786,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	786,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	786,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	786,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	0,	1,	787,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	787,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	0,	1,	788,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	788,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COEFFS"                      ,	0,	8,	789,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	789,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	790,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	790,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	0,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	791,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	791,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	792,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	792,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	793,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	793,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	793,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	793,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	793,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	793,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	793,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	793,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	793,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	793,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	794,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	794,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	794,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	794,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	794,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	794,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	795,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	795,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	796,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	796,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	796,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	796,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	797,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	797,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	797,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	797,	"RAZ",	1,	1,	0,	0},
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+	{"RESERVED_22_23"              ,	22,	2,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	798,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	798,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	799,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	799,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	799,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	800,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	800,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	800,	"RO",	1,	0,	0,	0ull},
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+	{"RING"                        ,	0,	4,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	801,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	801,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RING"                        ,	0,	4,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	802,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	803,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	803,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	803,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	803,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	804,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	804,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	805,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	805,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	805,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	806,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	806,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	807,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	808,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	808,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	808,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	808,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	809,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	809,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	810,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	810,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	810,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	811,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	12,	10,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	811,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	24,	40,	811,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	812,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	812,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	813,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	813,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	814,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	814,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	815,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	815,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	815,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	815,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	815,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	816,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	816,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	817,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	817,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	817,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	817,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	817,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	818,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	819,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	819,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	820,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	820,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
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+	{"STT"                         ,	9,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	821,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	821,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	822,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	822,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	822,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	822,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	822,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	823,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	823,	"R/W",	0,	0,	0ull,	0ull},
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+	{"RESERVED_20_63"              ,	20,	44,	823,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	824,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	824,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	825,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	825,	"RAZ",	0,	0,	0ull,	0ull},
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+	{"PSL1"                        ,	2,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
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+	{"LDI"                         ,	4,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
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+	{"IOBLD8"                      ,	10,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	826,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	826,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	827,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
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+	{"FPA"                         ,	5,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	827,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	827,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	827,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	827,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	828,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	828,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INEPINT"                     ,	0,	16,	829,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	829,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	830,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	831,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	831,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	831,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	831,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	831,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	832,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	832,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	832,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	832,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	832,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	832,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	832,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	833,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	833,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	833,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	833,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	833,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	833,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	833,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	833,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	834,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	834,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	834,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	834,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	834,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	834,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	834,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	834,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	835,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	835,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	836,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	836,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	837,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	837,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	837,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	837,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	837,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	837,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	837,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	837,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	837,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	838,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	838,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	838,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	838,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	838,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	838,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	839,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	839,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	840,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	840,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	841,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	841,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	842,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	842,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	842,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	843,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	843,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	844,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	845,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	846,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	847,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	847,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	847,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	847,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	847,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	847,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	848,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	849,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	849,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	849,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	849,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	849,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	849,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	849,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	849,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	849,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	849,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	849,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	849,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	849,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	849,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	850,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	850,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	850,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	850,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	850,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	850,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	850,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	851,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	851,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	851,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	851,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	851,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	851,	"RO",	0,	0,	1ull,	1ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	851,	"RO",	0,	0,	1ull,	1ull},
+	{"AVALIDFLTR"                  ,	22,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"BVALIDFLTR"                  ,	23,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"SESSENDFLTR"                 ,	24,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDEDTRFIFO"                 ,	25,	1,	851,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVMODINEND"              ,	26,	4,	851,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_30_31"              ,	30,	2,	851,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	852,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	852,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	852,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	852,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	852,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	853,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	853,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	853,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	853,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	854,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	854,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	855,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	855,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	855,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	855,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	856,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	856,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	856,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	856,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	856,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	856,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	856,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	856,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	857,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	857,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	857,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	857,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	857,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	857,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	857,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	857,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	857,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	857,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	858,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	858,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	858,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	858,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	859,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	859,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	860,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	860,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	861,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	861,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	861,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	861,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	861,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	862,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	863,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	863,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	864,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	865,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	865,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	865,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	865,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	865,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	865,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	865,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	865,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	865,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	865,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	866,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	866,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	867,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	867,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	868,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	868,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	869,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	869,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	869,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	870,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	870,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	871,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	871,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	872,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	874,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	874,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	875,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	875,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	876,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	876,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	876,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	876,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	876,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	876,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	876,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	877,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	877,	"R/W",	0,	0,	256ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	878,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	879,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	880,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	880,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"N2UF_BIS"                    ,	3,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"E2HC_BIS"                    ,	4,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NF_BIS"                    ,	5,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NC_BIS"                    ,	6,	1,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	881,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	882,	"R/W",	0,	0,	4ull,	0ull},
+	{"HRST"                        ,	3,	1,	882,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	882,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	882,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	882,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	882,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	882,	"R/W",	0,	0,	2ull,	0ull},
+	{"P_COM_ON"                    ,	13,	1,	882,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_RTYPE"                     ,	14,	2,	882,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	882,	"RAZ",	1,	1,	0,	0},
+	{"HCLK_RST"                    ,	17,	1,	882,	"R/W",	0,	0,	1ull,	1ull},
+	{"DIVIDE2"                     ,	18,	2,	882,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_63"              ,	20,	44,	882,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	883,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	883,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	883,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	884,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	884,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	885,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	885,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	886,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	886,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	887,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	887,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	888,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	888,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	889,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	889,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	890,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	890,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	891,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	891,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	892,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	892,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	893,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	893,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	894,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	894,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	895,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	895,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	896,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	896,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	897,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	897,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	898,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	898,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	899,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	899,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	900,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	900,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	900,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	901,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	901,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	902,	"RAZ",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	902,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	902,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	902,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_22"              ,	19,	4,	903,	"RAZ",	0,	0,	0ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXPREEMPHASISTUNE"           ,	30,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	903,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	903,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	38,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	39,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	40,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRVVBUS"                     ,	41,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	42,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGDISABLE"                  ,	43,	1,	903,	"R/W",	0,	0,	1ull,	1ull},
+	{"OTGTUNE"                     ,	44,	3,	903,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMPDISTUNE"                 ,	47,	3,	903,	"R/W",	0,	0,	2ull,	2ull},
+	{"SQRXTUNE"                    ,	50,	3,	903,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXHSXVTUNE"                  ,	53,	2,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFSLSTUNE"                  ,	55,	4,	903,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXVREFTUNE"                  ,	59,	4,	903,	"R/W",	0,	0,	7ull,	7ull},
+	{"TXRISETUNE"                  ,	63,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
+	 /* name                       ,	---------------type,	bits,	off,	#field,	fld of */
+	{"cvmx_agl_gmx_bad_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	0,	14,	0},
+	{"cvmx_agl_gmx_bist"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1,	2,	14},
+	{"cvmx_agl_gmx_drv_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2,	12,	16},
+	{"cvmx_agl_gmx_inf_mode"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	3,	3,	28},
+	{"cvmx_agl_gmx_prt#_cfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	4,	7,	31},
+	{"cvmx_agl_gmx_rx#_adr_cam0"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	6,	1,	38},
+	{"cvmx_agl_gmx_rx#_adr_cam1"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	8,	1,	39},
+	{"cvmx_agl_gmx_rx#_adr_cam2"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	10,	1,	40},
+	{"cvmx_agl_gmx_rx#_adr_cam3"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	12,	1,	41},
+	{"cvmx_agl_gmx_rx#_adr_cam4"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	14,	1,	42},
+	{"cvmx_agl_gmx_rx#_adr_cam5"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	16,	1,	43},
+	{"cvmx_agl_gmx_rx#_adr_cam_en" ,	CVMX_CSR_DB_TYPE_RSL,	64,	18,	2,	44},
+	{"cvmx_agl_gmx_rx#_adr_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	20,	4,	46},
+	{"cvmx_agl_gmx_rx#_decision"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	22,	2,	50},
+	{"cvmx_agl_gmx_rx#_frm_chk"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	24,	10,	52},
+	{"cvmx_agl_gmx_rx#_frm_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	26,	11,	62},
+	{"cvmx_agl_gmx_rx#_frm_max"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	28,	2,	73},
+	{"cvmx_agl_gmx_rx#_frm_min"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	30,	2,	75},
+	{"cvmx_agl_gmx_rx#_ifg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	32,	2,	77},
+	{"cvmx_agl_gmx_rx#_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	34,	19,	79},
+	{"cvmx_agl_gmx_rx#_int_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	36,	19,	98},
+	{"cvmx_agl_gmx_rx#_jabber"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	38,	2,	117},
+	{"cvmx_agl_gmx_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	40,	2,	119},
+	{"cvmx_agl_gmx_rx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	42,	2,	121},
+	{"cvmx_agl_gmx_rx#_stats_octs" ,	CVMX_CSR_DB_TYPE_RSL,	64,	44,	2,	123},
+	{"cvmx_agl_gmx_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	46,	2,	125},
+	{"cvmx_agl_gmx_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	48,	2,	127},
+	{"cvmx_agl_gmx_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	50,	2,	129},
+	{"cvmx_agl_gmx_rx#_stats_pkts" ,	CVMX_CSR_DB_TYPE_RSL,	64,	52,	2,	131},
+	{"cvmx_agl_gmx_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	54,	2,	133},
+	{"cvmx_agl_gmx_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	56,	2,	135},
+	{"cvmx_agl_gmx_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	58,	2,	137},
+	{"cvmx_agl_gmx_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	60,	2,	139},
+	{"cvmx_agl_gmx_rx#_udd_skp"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	62,	4,	141},
+	{"cvmx_agl_gmx_rx_bp_drop#"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	64,	2,	145},
+	{"cvmx_agl_gmx_rx_bp_off#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	66,	2,	147},
+	{"cvmx_agl_gmx_rx_bp_on#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	68,	2,	149},
+	{"cvmx_agl_gmx_rx_prt_info"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	70,	4,	151},
+	{"cvmx_agl_gmx_rx_tx_status"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	71,	4,	155},
+	{"cvmx_agl_gmx_smac#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	72,	2,	159},
+	{"cvmx_agl_gmx_stat_bp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	74,	3,	161},
+	{"cvmx_agl_gmx_tx#_append"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	75,	5,	164},
+	{"cvmx_agl_gmx_tx#_ctl"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	77,	3,	169},
+	{"cvmx_agl_gmx_tx#_min_pkt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	79,	2,	172},
+	{"cvmx_agl_gmx_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	81,	2,	174},
+	{"cvmx_agl_gmx_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	83,	2,	176},
+	{"cvmx_agl_gmx_tx#_pause_togo" ,	CVMX_CSR_DB_TYPE_RSL,	64,	85,	2,	178},
+	{"cvmx_agl_gmx_tx#_pause_zero" ,	CVMX_CSR_DB_TYPE_RSL,	64,	87,	2,	180},
+	{"cvmx_agl_gmx_tx#_soft_pause" ,	CVMX_CSR_DB_TYPE_RSL,	64,	89,	2,	182},
+	{"cvmx_agl_gmx_tx#_stat0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	91,	2,	184},
+	{"cvmx_agl_gmx_tx#_stat1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	93,	2,	186},
+	{"cvmx_agl_gmx_tx#_stat2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	95,	2,	188},
+	{"cvmx_agl_gmx_tx#_stat3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	97,	2,	190},
+	{"cvmx_agl_gmx_tx#_stat4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	99,	2,	192},
+	{"cvmx_agl_gmx_tx#_stat5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	101,	2,	194},
+	{"cvmx_agl_gmx_tx#_stat6"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	103,	2,	196},
+	{"cvmx_agl_gmx_tx#_stat7"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	105,	2,	198},
+	{"cvmx_agl_gmx_tx#_stat8"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	107,	2,	200},
+	{"cvmx_agl_gmx_tx#_stat9"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	109,	2,	202},
+	{"cvmx_agl_gmx_tx#_stats_ctl"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	111,	2,	204},
+	{"cvmx_agl_gmx_tx#_thresh"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	113,	2,	206},
+	{"cvmx_agl_gmx_tx_bp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	115,	2,	208},
+	{"cvmx_agl_gmx_tx_col_attempt" ,	CVMX_CSR_DB_TYPE_RSL,	64,	116,	2,	210},
+	{"cvmx_agl_gmx_tx_ifg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	117,	3,	212},
+	{"cvmx_agl_gmx_tx_int_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	118,	10,	215},
+	{"cvmx_agl_gmx_tx_int_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	119,	10,	225},
+	{"cvmx_agl_gmx_tx_jam"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	120,	2,	235},
+	{"cvmx_agl_gmx_tx_lfsr"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	121,	2,	237},
+	{"cvmx_agl_gmx_tx_ovr_bp"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	122,	6,	239},
+	{"cvmx_agl_gmx_tx_pause_pkt_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	123,	2,	245},
+	{"cvmx_agl_gmx_tx_pause_pkt_type",	CVMX_CSR_DB_TYPE_RSL,	64,	124,	2,	247},
+	{"cvmx_ciu_bist"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	125,	2,	249},
+	{"cvmx_ciu_dint"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	126,	2,	251},
+	{"cvmx_ciu_fuse"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	127,	2,	253},
+	{"cvmx_ciu_gstop"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	128,	2,	255},
+	{"cvmx_ciu_int#_en0"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	129,	22,	257},
+	{"cvmx_ciu_int#_en0_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	138,	22,	279},
+	{"cvmx_ciu_int#_en0_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	147,	22,	301},
+	{"cvmx_ciu_int#_en1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	156,	7,	323},
+	{"cvmx_ciu_int#_en1_w1c"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	165,	7,	330},
+	{"cvmx_ciu_int#_en1_w1s"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	174,	7,	337},
+	{"cvmx_ciu_int#_en4_0"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	183,	22,	344},
+	{"cvmx_ciu_int#_en4_0_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	187,	22,	366},
+	{"cvmx_ciu_int#_en4_0_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	191,	22,	388},
+	{"cvmx_ciu_int#_en4_1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	195,	7,	410},
+	{"cvmx_ciu_int#_en4_1_w1c"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	199,	7,	417},
+	{"cvmx_ciu_int#_en4_1_w1s"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	203,	7,	424},
+	{"cvmx_ciu_int#_sum0"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	207,	22,	431},
+	{"cvmx_ciu_int#_sum4"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	216,	22,	453},
+	{"cvmx_ciu_int_sum1"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	220,	7,	475},
+	{"cvmx_ciu_mbox_clr#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	221,	2,	482},
+	{"cvmx_ciu_mbox_set#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	225,	2,	484},
+	{"cvmx_ciu_nmi"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	229,	2,	486},
+	{"cvmx_ciu_pci_inta"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	230,	2,	488},
+	{"cvmx_ciu_pp_dbg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	231,	2,	490},
+	{"cvmx_ciu_pp_poke#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	232,	1,	492},
+	{"cvmx_ciu_pp_rst"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	236,	3,	493},
+	{"cvmx_ciu_qlm_dcok"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	237,	2,	496},
+	{"cvmx_ciu_qlm_jtgc"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	238,	6,	498},
+	{"cvmx_ciu_qlm_jtgd"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	239,	8,	504},
+	{"cvmx_ciu_soft_bist"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	240,	2,	512},
+	{"cvmx_ciu_soft_prst"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	241,	2,	514},
+	{"cvmx_ciu_soft_prst1"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	242,	2,	516},
+	{"cvmx_ciu_soft_rst"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	243,	2,	518},
+	{"cvmx_ciu_tim#"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	244,	3,	520},
+	{"cvmx_ciu_wdog#"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	248,	7,	523},
+	{"cvmx_fpa_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	252,	6,	530},
+	{"cvmx_fpa_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	253,	7,	536},
+	{"cvmx_fpa_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	254,	29,	543},
+	{"cvmx_fpa_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	255,	29,	572},
+	{"cvmx_fpa_que#_available"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	256,	2,	601},
+	{"cvmx_fpa_que#_page_index"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	264,	2,	603},
+	{"cvmx_fpa_que_act"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	272,	3,	605},
+	{"cvmx_fpa_que_exp"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	273,	3,	608},
+	{"cvmx_fpa_wart_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	274,	2,	611},
+	{"cvmx_fpa_wart_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	275,	2,	613},
+	{"cvmx_gmx#_bad_reg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	276,	7,	615},
+	{"cvmx_gmx#_bist"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	277,	2,	622},
+	{"cvmx_gmx#_clk_en"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	278,	2,	624},
+	{"cvmx_gmx#_hg2_control"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	279,	5,	626},
+	{"cvmx_gmx#_inf_mode"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	280,	7,	631},
+	{"cvmx_gmx#_nxa_adr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	281,	2,	638},
+	{"cvmx_gmx#_prt#_cbfc_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	282,	8,	640},
+	{"cvmx_gmx#_prt#_cfg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	283,	10,	648},
+	{"cvmx_gmx#_rx#_adr_cam0"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	287,	1,	658},
+	{"cvmx_gmx#_rx#_adr_cam1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	291,	1,	659},
+	{"cvmx_gmx#_rx#_adr_cam2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	295,	1,	660},
+	{"cvmx_gmx#_rx#_adr_cam3"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	299,	1,	661},
+	{"cvmx_gmx#_rx#_adr_cam4"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	303,	1,	662},
+	{"cvmx_gmx#_rx#_adr_cam5"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	307,	1,	663},
+	{"cvmx_gmx#_rx#_adr_cam_en"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	311,	2,	664},
+	{"cvmx_gmx#_rx#_adr_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	315,	4,	666},
+	{"cvmx_gmx#_rx#_decision"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	319,	2,	670},
+	{"cvmx_gmx#_rx#_frm_chk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	323,	9,	672},
+	{"cvmx_gmx#_rx#_frm_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	327,	11,	681},
+	{"cvmx_gmx#_rx#_ifg"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	331,	2,	692},
+	{"cvmx_gmx#_rx#_int_en"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	335,	27,	694},
+	{"cvmx_gmx#_rx#_int_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	339,	27,	721},
+	{"cvmx_gmx#_rx#_jabber"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	343,	2,	748},
+	{"cvmx_gmx#_rx#_pause_drop_time",	CVMX_CSR_DB_TYPE_RSL,	64,	347,	2,	750},
+	{"cvmx_gmx#_rx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	351,	2,	752},
+	{"cvmx_gmx#_rx#_stats_octs"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	355,	2,	754},
+	{"cvmx_gmx#_rx#_stats_octs_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	359,	2,	756},
+	{"cvmx_gmx#_rx#_stats_octs_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	363,	2,	758},
+	{"cvmx_gmx#_rx#_stats_octs_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	367,	2,	760},
+	{"cvmx_gmx#_rx#_stats_pkts"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	371,	2,	762},
+	{"cvmx_gmx#_rx#_stats_pkts_bad",	CVMX_CSR_DB_TYPE_RSL,	64,	375,	2,	764},
+	{"cvmx_gmx#_rx#_stats_pkts_ctl",	CVMX_CSR_DB_TYPE_RSL,	64,	379,	2,	766},
+	{"cvmx_gmx#_rx#_stats_pkts_dmac",	CVMX_CSR_DB_TYPE_RSL,	64,	383,	2,	768},
+	{"cvmx_gmx#_rx#_stats_pkts_drp",	CVMX_CSR_DB_TYPE_RSL,	64,	387,	2,	770},
+	{"cvmx_gmx#_rx#_udd_skp"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	391,	4,	772},
+	{"cvmx_gmx#_rx_bp_drop#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	395,	2,	776},
+	{"cvmx_gmx#_rx_bp_off#"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	399,	2,	778},
+	{"cvmx_gmx#_rx_bp_on#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	403,	2,	780},
+	{"cvmx_gmx#_rx_hg2_status"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	407,	4,	782},
+	{"cvmx_gmx#_rx_prt_info"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	408,	4,	786},
+	{"cvmx_gmx#_rx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	409,	2,	790},
+	{"cvmx_gmx#_rx_xaui_bad_col"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	410,	5,	792},
+	{"cvmx_gmx#_rx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	411,	2,	797},
+	{"cvmx_gmx#_smac#"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	412,	2,	799},
+	{"cvmx_gmx#_stat_bp"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	416,	3,	801},
+	{"cvmx_gmx#_tx#_append"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	417,	5,	804},
+	{"cvmx_gmx#_tx#_burst"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	421,	2,	809},
+	{"cvmx_gmx#_tx#_cbfc_xoff"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	425,	2,	811},
+	{"cvmx_gmx#_tx#_cbfc_xon"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	426,	2,	813},
+	{"cvmx_gmx#_tx#_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	427,	3,	815},
+	{"cvmx_gmx#_tx#_min_pkt"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	431,	2,	818},
+	{"cvmx_gmx#_tx#_pause_pkt_interval",	CVMX_CSR_DB_TYPE_RSL,	64,	435,	2,	820},
+	{"cvmx_gmx#_tx#_pause_pkt_time",	CVMX_CSR_DB_TYPE_RSL,	64,	439,	2,	822},
+	{"cvmx_gmx#_tx#_pause_togo"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	443,	3,	824},
+	{"cvmx_gmx#_tx#_pause_zero"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	447,	2,	827},
+	{"cvmx_gmx#_tx#_sgmii_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	451,	2,	829},
+	{"cvmx_gmx#_tx#_slot"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	455,	2,	831},
+	{"cvmx_gmx#_tx#_soft_pause"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	459,	2,	833},
+	{"cvmx_gmx#_tx#_stat0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	463,	2,	835},
+	{"cvmx_gmx#_tx#_stat1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	467,	2,	837},
+	{"cvmx_gmx#_tx#_stat2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	471,	2,	839},
+	{"cvmx_gmx#_tx#_stat3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	475,	2,	841},
+	{"cvmx_gmx#_tx#_stat4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	479,	2,	843},
+	{"cvmx_gmx#_tx#_stat5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	483,	2,	845},
+	{"cvmx_gmx#_tx#_stat6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	487,	2,	847},
+	{"cvmx_gmx#_tx#_stat7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	491,	2,	849},
+	{"cvmx_gmx#_tx#_stat8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	495,	2,	851},
+	{"cvmx_gmx#_tx#_stat9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	499,	2,	853},
+	{"cvmx_gmx#_tx#_stats_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	503,	2,	855},
+	{"cvmx_gmx#_tx#_thresh"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	507,	2,	857},
+	{"cvmx_gmx#_tx_bp"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	511,	2,	859},
+	{"cvmx_gmx#_tx_col_attempt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	512,	2,	861},
+	{"cvmx_gmx#_tx_corrupt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	513,	2,	863},
+	{"cvmx_gmx#_tx_hg2_reg1"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	514,	2,	865},
+	{"cvmx_gmx#_tx_hg2_reg2"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	515,	2,	867},
+	{"cvmx_gmx#_tx_ifg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	516,	3,	869},
+	{"cvmx_gmx#_tx_int_en"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	517,	8,	872},
+	{"cvmx_gmx#_tx_int_reg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	518,	8,	880},
+	{"cvmx_gmx#_tx_jam"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	519,	2,	888},
+	{"cvmx_gmx#_tx_lfsr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	520,	2,	890},
+	{"cvmx_gmx#_tx_ovr_bp"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	521,	6,	892},
+	{"cvmx_gmx#_tx_pause_pkt_dmac" ,	CVMX_CSR_DB_TYPE_RSL,	64,	522,	2,	898},
+	{"cvmx_gmx#_tx_pause_pkt_type" ,	CVMX_CSR_DB_TYPE_RSL,	64,	523,	2,	900},
+	{"cvmx_gmx#_tx_prts"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	524,	2,	902},
+	{"cvmx_gmx#_tx_xaui_ctl"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	525,	9,	904},
+	{"cvmx_gmx#_xaui_ext_loopback" ,	CVMX_CSR_DB_TYPE_RSL,	64,	526,	3,	913},
+	{"cvmx_gpio_bit_cfg#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	527,	9,	916},
+	{"cvmx_gpio_clk_gen#"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	543,	2,	925},
+	{"cvmx_gpio_int_clr"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	547,	2,	927},
+	{"cvmx_gpio_rx_dat"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	548,	2,	929},
+	{"cvmx_gpio_tx_clr"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	549,	2,	931},
+	{"cvmx_gpio_tx_set"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	550,	2,	933},
+	{"cvmx_iob_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	551,	19,	935},
+	{"cvmx_iob_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	552,	7,	954},
+	{"cvmx_iob_dwb_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	553,	3,	961},
+	{"cvmx_iob_fau_timeout"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	554,	3,	964},
+	{"cvmx_iob_i2c_pri_cnt"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	555,	3,	967},
+	{"cvmx_iob_inb_control_match"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	556,	5,	970},
+	{"cvmx_iob_inb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	557,	5,	975},
+	{"cvmx_iob_inb_data_match"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	558,	1,	980},
+	{"cvmx_iob_inb_data_match_enb" ,	CVMX_CSR_DB_TYPE_RSL,	64,	559,	1,	981},
+	{"cvmx_iob_int_enb"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	560,	7,	982},
+	{"cvmx_iob_int_sum"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	561,	7,	989},
+	{"cvmx_iob_n2c_l2c_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	562,	3,	996},
+	{"cvmx_iob_n2c_rsp_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	563,	3,	999},
+	{"cvmx_iob_outb_com_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	564,	3,	1002},
+	{"cvmx_iob_outb_control_match" ,	CVMX_CSR_DB_TYPE_RSL,	64,	565,	5,	1005},
+	{"cvmx_iob_outb_control_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	566,	5,	1010},
+	{"cvmx_iob_outb_data_match"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	567,	1,	1015},
+	{"cvmx_iob_outb_data_match_enb",	CVMX_CSR_DB_TYPE_RSL,	64,	568,	1,	1016},
+	{"cvmx_iob_outb_fpa_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	569,	3,	1017},
+	{"cvmx_iob_outb_req_pri_cnt"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	570,	3,	1020},
+	{"cvmx_iob_p2c_req_pri_cnt"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	571,	3,	1023},
+	{"cvmx_iob_pkt_err"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	572,	2,	1026},
+	{"cvmx_iob_to_cmb_credits"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	573,	4,	1028},
+	{"cvmx_ipd_1st_mbuff_skip"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	574,	2,	1032},
+	{"cvmx_ipd_1st_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	575,	2,	1034},
+	{"cvmx_ipd_2nd_next_ptr_back"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	576,	2,	1036},
+	{"cvmx_ipd_bist_status"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	577,	19,	1038},
+	{"cvmx_ipd_bp_prt_red_end"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	578,	2,	1057},
+	{"cvmx_ipd_clk_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	579,	1,	1059},
+	{"cvmx_ipd_ctl_status"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	580,	15,	1060},
+	{"cvmx_ipd_int_enb"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	581,	13,	1075},
+	{"cvmx_ipd_int_sum"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	582,	13,	1088},
+	{"cvmx_ipd_not_1st_mbuff_skip" ,	CVMX_CSR_DB_TYPE_NCB,	64,	583,	2,	1101},
+	{"cvmx_ipd_packet_mbuff_size"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	584,	2,	1103},
+	{"cvmx_ipd_pkt_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	585,	2,	1105},
+	{"cvmx_ipd_port#_bp_page_cnt"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	586,	3,	1107},
+	{"cvmx_ipd_port#_bp_page_cnt2" ,	CVMX_CSR_DB_TYPE_NCB,	64,	594,	3,	1110},
+	{"cvmx_ipd_port_bp_counters2_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	598,	2,	1113},
+	{"cvmx_ipd_port_bp_counters_pair#",	CVMX_CSR_DB_TYPE_NCB,	64,	602,	2,	1115},
+	{"cvmx_ipd_port_qos_#_cnt"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	610,	2,	1117},
+	{"cvmx_ipd_port_qos_int#"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	706,	1,	1119},
+	{"cvmx_ipd_port_qos_int_enb#"  ,	CVMX_CSR_DB_TYPE_NCB,	64,	708,	1,	1120},
+	{"cvmx_ipd_prc_hold_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	710,	6,	1121},
+	{"cvmx_ipd_prc_port_ptr_fifo_ctl",	CVMX_CSR_DB_TYPE_NCB,	64,	711,	5,	1127},
+	{"cvmx_ipd_ptr_count"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	712,	6,	1132},
+	{"cvmx_ipd_pwp_ptr_fifo_ctl"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	713,	7,	1138},
+	{"cvmx_ipd_qos#_red_marks"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	714,	2,	1145},
+	{"cvmx_ipd_que0_free_page_cnt" ,	CVMX_CSR_DB_TYPE_NCB,	64,	722,	2,	1147},
+	{"cvmx_ipd_red_port_enable"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	723,	3,	1149},
+	{"cvmx_ipd_red_port_enable2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	724,	2,	1152},
+	{"cvmx_ipd_red_que#_param"     ,	CVMX_CSR_DB_TYPE_NCB,	64,	725,	5,	1154},
+	{"cvmx_ipd_sub_port_bp_page_cnt",	CVMX_CSR_DB_TYPE_NCB,	64,	733,	3,	1159},
+	{"cvmx_ipd_sub_port_fcs"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	734,	4,	1162},
+	{"cvmx_ipd_sub_port_qos_cnt"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	735,	3,	1166},
+	{"cvmx_ipd_wqe_fpa_queue"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	736,	2,	1169},
+	{"cvmx_ipd_wqe_ptr_valid"      ,	CVMX_CSR_DB_TYPE_NCB,	64,	737,	2,	1171},
+	{"cvmx_l2c_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	738,	8,	1173},
+	{"cvmx_l2c_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	739,	9,	1181},
+	{"cvmx_l2c_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	740,	8,	1190},
+	{"cvmx_l2c_cfg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	741,	12,	1198},
+	{"cvmx_l2c_dbg"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	742,	9,	1210},
+	{"cvmx_l2c_dut"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	743,	5,	1219},
+	{"cvmx_l2c_grpwrr0"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	744,	2,	1224},
+	{"cvmx_l2c_grpwrr1"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	745,	2,	1226},
+	{"cvmx_l2c_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	746,	10,	1228},
+	{"cvmx_l2c_int_stat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	747,	10,	1238},
+	{"cvmx_l2c_lckbase"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	748,	4,	1248},
+	{"cvmx_l2c_lckoff"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	749,	2,	1252},
+	{"cvmx_l2c_lfb0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	750,	16,	1254},
+	{"cvmx_l2c_lfb1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	751,	19,	1270},
+	{"cvmx_l2c_lfb2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	752,	3,	1289},
+	{"cvmx_l2c_lfb3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	753,	4,	1292},
+	{"cvmx_l2c_oob"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	754,	3,	1296},
+	{"cvmx_l2c_oob1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	755,	6,	1299},
+	{"cvmx_l2c_oob2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	756,	6,	1305},
+	{"cvmx_l2c_oob3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	757,	6,	1311},
+	{"cvmx_l2c_pfc#"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	758,	2,	1317},
+	{"cvmx_l2c_pfctl"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	762,	17,	1319},
+	{"cvmx_l2c_ppgrp"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	763,	5,	1336},
+	{"cvmx_l2c_spar0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	764,	5,	1341},
+	{"cvmx_l2c_spar4"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	765,	2,	1346},
+	{"cvmx_l2d_bst0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	766,	3,	1348},
+	{"cvmx_l2d_bst1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	767,	2,	1351},
+	{"cvmx_l2d_bst2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	768,	2,	1353},
+	{"cvmx_l2d_bst3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	769,	2,	1355},
+	{"cvmx_l2d_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	770,	7,	1357},
+	{"cvmx_l2d_fadr"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	771,	5,	1364},
+	{"cvmx_l2d_fsyn0"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	772,	3,	1369},
+	{"cvmx_l2d_fsyn1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	773,	3,	1372},
+	{"cvmx_l2d_fus0"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	774,	2,	1375},
+	{"cvmx_l2d_fus1"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	775,	2,	1377},
+	{"cvmx_l2d_fus2"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	776,	2,	1379},
+	{"cvmx_l2d_fus3"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	777,	6,	1381},
+	{"cvmx_l2t_err"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	778,	14,	1387},
+	{"cvmx_lmc#_bist_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	779,	2,	1401},
+	{"cvmx_lmc#_bist_result"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	780,	8,	1403},
+	{"cvmx_lmc#_comp_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	781,	7,	1411},
+	{"cvmx_lmc#_ctl"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	782,	19,	1418},
+	{"cvmx_lmc#_ctl1"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	783,	8,	1437},
+	{"cvmx_lmc#_dclk_cnt_hi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	784,	2,	1445},
+	{"cvmx_lmc#_dclk_cnt_lo"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	785,	2,	1447},
+	{"cvmx_lmc#_ddr2_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	786,	18,	1449},
+	{"cvmx_lmc#_delay_cfg"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	787,	6,	1467},
+	{"cvmx_lmc#_dll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	788,	5,	1473},
+	{"cvmx_lmc#_dual_memcfg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	789,	5,	1478},
+	{"cvmx_lmc#_ecc_synd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	790,	5,	1483},
+	{"cvmx_lmc#_fadr"              ,	CVMX_CSR_DB_TYPE_RSL,	64,	791,	6,	1488},
+	{"cvmx_lmc#_ifb_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	792,	2,	1494},
+	{"cvmx_lmc#_ifb_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	793,	2,	1496},
+	{"cvmx_lmc#_mem_cfg0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	794,	14,	1498},
+	{"cvmx_lmc#_mem_cfg1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	795,	9,	1512},
+	{"cvmx_lmc#_nxm"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	796,	2,	1521},
+	{"cvmx_lmc#_ops_cnt_hi"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	797,	2,	1523},
+	{"cvmx_lmc#_ops_cnt_lo"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	798,	2,	1525},
+	{"cvmx_lmc#_pll_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	799,	14,	1527},
+	{"cvmx_lmc#_pll_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	800,	6,	1541},
+	{"cvmx_lmc#_read_level_ctl"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	801,	7,	1547},
+	{"cvmx_lmc#_read_level_dbg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	802,	4,	1554},
+	{"cvmx_lmc#_read_level_rank#"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	803,	11,	1558},
+	{"cvmx_lmc#_rodt_comp_ctl"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	807,	6,	1569},
+	{"cvmx_lmc#_rodt_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	808,	9,	1575},
+	{"cvmx_lmc#_wodt_ctl0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	809,	5,	1584},
+	{"cvmx_lmc#_wodt_ctl1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	810,	5,	1589},
+	{"cvmx_mio_boot_bist_stat"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	811,	6,	1594},
+	{"cvmx_mio_boot_comp"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	812,	3,	1600},
+	{"cvmx_mio_boot_dma_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	813,	10,	1603},
+	{"cvmx_mio_boot_dma_int#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	815,	3,	1613},
+	{"cvmx_mio_boot_dma_int_en#"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	817,	3,	1616},
+	{"cvmx_mio_boot_dma_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	819,	15,	1619},
+	{"cvmx_mio_boot_err"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	821,	3,	1634},
+	{"cvmx_mio_boot_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	822,	3,	1637},
+	{"cvmx_mio_boot_loc_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	823,	3,	1640},
+	{"cvmx_mio_boot_loc_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	824,	5,	1643},
+	{"cvmx_mio_boot_loc_dat"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	826,	1,	1648},
+	{"cvmx_mio_boot_pin_defs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	827,	9,	1649},
+	{"cvmx_mio_boot_reg_cfg#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	828,	13,	1658},
+	{"cvmx_mio_boot_reg_tim#"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	836,	13,	1671},
+	{"cvmx_mio_boot_thr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	844,	6,	1684},
+	{"cvmx_mio_fus_bnk_dat#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	845,	1,	1690},
+	{"cvmx_mio_fus_dat0"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	849,	2,	1691},
+	{"cvmx_mio_fus_dat1"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	850,	2,	1693},
+	{"cvmx_mio_fus_dat2"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	851,	13,	1695},
+	{"cvmx_mio_fus_dat3"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	852,	8,	1708},
+	{"cvmx_mio_fus_ema"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	853,	4,	1716},
+	{"cvmx_mio_fus_pdf"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	854,	1,	1720},
+	{"cvmx_mio_fus_pll"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	855,	3,	1721},
+	{"cvmx_mio_fus_prog"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	856,	2,	1724},
+	{"cvmx_mio_fus_prog_times"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	857,	6,	1726},
+	{"cvmx_mio_fus_rcmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	858,	7,	1732},
+	{"cvmx_mio_fus_spr_repair_res" ,	CVMX_CSR_DB_TYPE_RSL,	64,	859,	4,	1739},
+	{"cvmx_mio_fus_spr_repair_sum" ,	CVMX_CSR_DB_TYPE_RSL,	64,	860,	2,	1743},
+	{"cvmx_mio_fus_wadr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	861,	2,	1745},
+	{"cvmx_mio_ndf_dma_cfg"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	862,	10,	1747},
+	{"cvmx_mio_ndf_dma_int"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	863,	2,	1757},
+	{"cvmx_mio_ndf_dma_int_en"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	864,	2,	1759},
+	{"cvmx_mio_tws#_int"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	865,	13,	1761},
+	{"cvmx_mio_tws#_sw_twsi"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	867,	12,	1774},
+	{"cvmx_mio_tws#_sw_twsi_ext"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	869,	3,	1786},
+	{"cvmx_mio_tws#_twsi_sw"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	871,	3,	1789},
+	{"cvmx_mio_uart#_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	873,	2,	1792},
+	{"cvmx_mio_uart#_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	875,	2,	1794},
+	{"cvmx_mio_uart#_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	877,	2,	1796},
+	{"cvmx_mio_uart#_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	879,	7,	1798},
+	{"cvmx_mio_uart#_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	881,	2,	1805},
+	{"cvmx_mio_uart#_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	883,	7,	1807},
+	{"cvmx_mio_uart#_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	885,	4,	1814},
+	{"cvmx_mio_uart#_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	887,	8,	1818},
+	{"cvmx_mio_uart#_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	889,	9,	1826},
+	{"cvmx_mio_uart#_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	891,	7,	1835},
+	{"cvmx_mio_uart#_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	893,	9,	1842},
+	{"cvmx_mio_uart#_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	895,	2,	1851},
+	{"cvmx_mio_uart#_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	897,	2,	1853},
+	{"cvmx_mio_uart#_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	899,	4,	1855},
+	{"cvmx_mio_uart#_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	901,	2,	1859},
+	{"cvmx_mio_uart#_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	903,	2,	1861},
+	{"cvmx_mio_uart#_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	905,	2,	1863},
+	{"cvmx_mio_uart#_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	907,	4,	1865},
+	{"cvmx_mio_uart#_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	909,	2,	1869},
+	{"cvmx_mio_uart#_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	911,	2,	1871},
+	{"cvmx_mio_uart#_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	913,	2,	1873},
+	{"cvmx_mio_uart#_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	915,	2,	1875},
+	{"cvmx_mio_uart#_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	917,	2,	1877},
+	{"cvmx_mio_uart#_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	919,	2,	1879},
+	{"cvmx_mio_uart#_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	921,	6,	1881},
+	{"cvmx_mio_uart2_dlh"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	923,	2,	1887},
+	{"cvmx_mio_uart2_dll"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	924,	2,	1889},
+	{"cvmx_mio_uart2_far"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	925,	2,	1891},
+	{"cvmx_mio_uart2_fcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	926,	7,	1893},
+	{"cvmx_mio_uart2_htx"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	927,	2,	1900},
+	{"cvmx_mio_uart2_ier"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	928,	7,	1902},
+	{"cvmx_mio_uart2_iir"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	929,	4,	1909},
+	{"cvmx_mio_uart2_lcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	930,	8,	1913},
+	{"cvmx_mio_uart2_lsr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	931,	9,	1921},
+	{"cvmx_mio_uart2_mcr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	932,	7,	1930},
+	{"cvmx_mio_uart2_msr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	933,	9,	1937},
+	{"cvmx_mio_uart2_rbr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	934,	2,	1946},
+	{"cvmx_mio_uart2_rfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	935,	2,	1948},
+	{"cvmx_mio_uart2_rfw"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	936,	4,	1950},
+	{"cvmx_mio_uart2_sbcr"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	937,	2,	1954},
+	{"cvmx_mio_uart2_scr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	938,	2,	1956},
+	{"cvmx_mio_uart2_sfe"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	939,	2,	1958},
+	{"cvmx_mio_uart2_srr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	940,	4,	1960},
+	{"cvmx_mio_uart2_srt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	941,	2,	1964},
+	{"cvmx_mio_uart2_srts"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	942,	2,	1966},
+	{"cvmx_mio_uart2_stt"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	943,	2,	1968},
+	{"cvmx_mio_uart2_tfl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	944,	2,	1970},
+	{"cvmx_mio_uart2_tfr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	945,	2,	1972},
+	{"cvmx_mio_uart2_thr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	946,	2,	1974},
+	{"cvmx_mio_uart2_usr"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	947,	6,	1976},
+	{"cvmx_mix#_bist"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	948,	5,	1982},
+	{"cvmx_mix#_ctl"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	950,	8,	1987},
+	{"cvmx_mix#_intena"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	952,	8,	1995},
+	{"cvmx_mix#_ircnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	954,	2,	2003},
+	{"cvmx_mix#_irhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	956,	3,	2005},
+	{"cvmx_mix#_iring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	958,	5,	2008},
+	{"cvmx_mix#_iring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	960,	4,	2013},
+	{"cvmx_mix#_isr"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	962,	8,	2017},
+	{"cvmx_mix#_orcnt"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	964,	2,	2025},
+	{"cvmx_mix#_orhwm"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	966,	2,	2027},
+	{"cvmx_mix#_oring1"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	968,	5,	2029},
+	{"cvmx_mix#_oring2"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	970,	4,	2034},
+	{"cvmx_mix#_remcnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	972,	4,	2038},
+	{"cvmx_ndf_bt_pg_info"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	974,	4,	2042},
+	{"cvmx_ndf_cmd"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	975,	1,	2046},
+	{"cvmx_ndf_drbell"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	976,	2,	2047},
+	{"cvmx_ndf_ecc_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	977,	3,	2049},
+	{"cvmx_ndf_int"                ,	CVMX_CSR_DB_TYPE_NCB,	64,	978,	8,	2052},
+	{"cvmx_ndf_int_en"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	979,	8,	2060},
+	{"cvmx_ndf_misc"               ,	CVMX_CSR_DB_TYPE_NCB,	64,	980,	11,	2068},
+	{"cvmx_ndf_st_reg"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	981,	8,	2079},
+	{"cvmx_npei_bar1_index#"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	982,	5,	2087},
+	{"cvmx_npei_bist_status"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1014,	58,	2092},
+	{"cvmx_npei_bist_status2"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1015,	15,	2150},
+	{"cvmx_npei_ctl_port0"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1016,	17,	2165},
+	{"cvmx_npei_ctl_port1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1017,	17,	2182},
+	{"cvmx_npei_ctl_status"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1018,	10,	2199},
+	{"cvmx_npei_ctl_status2"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1019,	11,	2209},
+	{"cvmx_npei_data_out_cnt"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1020,	5,	2220},
+	{"cvmx_npei_dbg_data"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1021,	8,	2225},
+	{"cvmx_npei_dbg_select"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1022,	2,	2233},
+	{"cvmx_npei_dma#_counts"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1023,	3,	2235},
+	{"cvmx_npei_dma#_dbell"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	1028,	2,	2238},
+	{"cvmx_npei_dma#_ibuff_saddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1033,	4,	2240},
+	{"cvmx_npei_dma#_naddr"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1038,	2,	2244},
+	{"cvmx_npei_dma0_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1043,	2,	2246},
+	{"cvmx_npei_dma1_int_level"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1044,	2,	2248},
+	{"cvmx_npei_dma_cnts"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1045,	2,	2250},
+	{"cvmx_npei_dma_control"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1046,	17,	2252},
+	{"cvmx_npei_dma_pcie_req_num"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1047,	15,	2269},
+	{"cvmx_npei_dma_state1"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1048,	6,	2284},
+	{"cvmx_npei_dma_state2"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1049,	6,	2290},
+	{"cvmx_npei_int_a_enb"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1050,	11,	2296},
+	{"cvmx_npei_int_a_enb2"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1051,	11,	2307},
+	{"cvmx_npei_int_a_sum"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1052,	11,	2318},
+	{"cvmx_npei_int_enb"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1053,	64,	2329},
+	{"cvmx_npei_int_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1054,	63,	2393},
+	{"cvmx_npei_int_info"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1055,	3,	2456},
+	{"cvmx_npei_int_sum"           ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1056,	64,	2459},
+	{"cvmx_npei_int_sum2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1057,	61,	2523},
+	{"cvmx_npei_last_win_rdata0"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1058,	1,	2584},
+	{"cvmx_npei_last_win_rdata1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1059,	1,	2585},
+	{"cvmx_npei_mem_access_ctl"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1060,	3,	2586},
+	{"cvmx_npei_mem_access_subid#" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1061,	11,	2589},
+	{"cvmx_npei_msi_enb0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1077,	1,	2600},
+	{"cvmx_npei_msi_enb1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1078,	1,	2601},
+	{"cvmx_npei_msi_enb2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1079,	1,	2602},
+	{"cvmx_npei_msi_enb3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1080,	1,	2603},
+	{"cvmx_npei_msi_rcv0"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1081,	1,	2604},
+	{"cvmx_npei_msi_rcv1"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1082,	1,	2605},
+	{"cvmx_npei_msi_rcv2"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1083,	1,	2606},
+	{"cvmx_npei_msi_rcv3"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1084,	1,	2607},
+	{"cvmx_npei_msi_rd_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1085,	3,	2608},
+	{"cvmx_npei_msi_w1c_enb0"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1086,	1,	2611},
+	{"cvmx_npei_msi_w1c_enb1"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1087,	1,	2612},
+	{"cvmx_npei_msi_w1c_enb2"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1088,	1,	2613},
+	{"cvmx_npei_msi_w1c_enb3"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1089,	1,	2614},
+	{"cvmx_npei_msi_w1s_enb0"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1090,	1,	2615},
+	{"cvmx_npei_msi_w1s_enb1"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1091,	1,	2616},
+	{"cvmx_npei_msi_w1s_enb2"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1092,	1,	2617},
+	{"cvmx_npei_msi_w1s_enb3"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1093,	1,	2618},
+	{"cvmx_npei_msi_wr_map"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1094,	3,	2619},
+	{"cvmx_npei_pcie_credit_cnt"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1095,	7,	2622},
+	{"cvmx_npei_pcie_msi_rcv"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1096,	2,	2629},
+	{"cvmx_npei_pcie_msi_rcv_b1"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1097,	3,	2631},
+	{"cvmx_npei_pcie_msi_rcv_b2"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1098,	3,	2634},
+	{"cvmx_npei_pcie_msi_rcv_b3"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1099,	3,	2637},
+	{"cvmx_npei_pkt#_cnts"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1100,	3,	2640},
+	{"cvmx_npei_pkt#_in_bp"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1132,	2,	2643},
+	{"cvmx_npei_pkt#_instr_baddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1164,	2,	2645},
+	{"cvmx_npei_pkt#_instr_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1196,	2,	2647},
+	{"cvmx_npei_pkt#_instr_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1228,	5,	2649},
+	{"cvmx_npei_pkt#_instr_header" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1260,	13,	2654},
+	{"cvmx_npei_pkt#_slist_baddr"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1292,	2,	2667},
+	{"cvmx_npei_pkt#_slist_baoff_dbell",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1324,	2,	2669},
+	{"cvmx_npei_pkt#_slist_fifo_rsize",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1356,	2,	2671},
+	{"cvmx_npei_pkt_cnt_int"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1388,	2,	2673},
+	{"cvmx_npei_pkt_cnt_int_enb"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1389,	2,	2675},
+	{"cvmx_npei_pkt_data_out_es"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1390,	1,	2677},
+	{"cvmx_npei_pkt_data_out_ns"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1391,	2,	2678},
+	{"cvmx_npei_pkt_data_out_ror"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1392,	2,	2680},
+	{"cvmx_npei_pkt_dpaddr"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1393,	2,	2682},
+	{"cvmx_npei_pkt_in_bp"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1394,	2,	2684},
+	{"cvmx_npei_pkt_in_done#_cnts" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1395,	2,	2686},
+	{"cvmx_npei_pkt_in_instr_counts",	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1427,	2,	2688},
+	{"cvmx_npei_pkt_in_pcie_port"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1428,	1,	2690},
+	{"cvmx_npei_pkt_input_control" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1429,	10,	2691},
+	{"cvmx_npei_pkt_instr_enb"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1430,	2,	2701},
+	{"cvmx_npei_pkt_instr_rd_size" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1431,	1,	2703},
+	{"cvmx_npei_pkt_instr_size"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1432,	2,	2704},
+	{"cvmx_npei_pkt_int_levels"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1433,	3,	2706},
+	{"cvmx_npei_pkt_iptr"          ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1434,	2,	2709},
+	{"cvmx_npei_pkt_out_bmode"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1435,	2,	2711},
+	{"cvmx_npei_pkt_out_enb"       ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1436,	2,	2713},
+	{"cvmx_npei_pkt_output_wmark"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1437,	2,	2715},
+	{"cvmx_npei_pkt_pcie_port"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1438,	1,	2717},
+	{"cvmx_npei_pkt_port_in_rst"   ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1439,	2,	2718},
+	{"cvmx_npei_pkt_slist_es"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1440,	1,	2720},
+	{"cvmx_npei_pkt_slist_id_size" ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1441,	3,	2721},
+	{"cvmx_npei_pkt_slist_ns"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1442,	2,	2724},
+	{"cvmx_npei_pkt_slist_ror"     ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1443,	2,	2726},
+	{"cvmx_npei_pkt_time_int"      ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1444,	2,	2728},
+	{"cvmx_npei_pkt_time_int_enb"  ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1445,	2,	2730},
+	{"cvmx_npei_rsl_int_blocks"    ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1446,	29,	2732},
+	{"cvmx_npei_scratch_1"         ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1447,	1,	2761},
+	{"cvmx_npei_state1"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1448,	4,	2762},
+	{"cvmx_npei_state2"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1449,	7,	2766},
+	{"cvmx_npei_state3"            ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1450,	5,	2773},
+	{"cvmx_npei_win_rd_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1451,	4,	2778},
+	{"cvmx_npei_win_rd_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1452,	1,	2782},
+	{"cvmx_npei_win_wr_addr"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1453,	4,	2783},
+	{"cvmx_npei_win_wr_data"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1454,	1,	2787},
+	{"cvmx_npei_win_wr_mask"       ,	CVMX_CSR_DB_TYPE_PEXP,	64,	1455,	2,	2788},
+	{"cvmx_npei_window_ctl"        ,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	1456,	2,	2790},
+	{"cvmx_pcieep_cfg000"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1457,	2,	2792},
+	{"cvmx_pcieep_cfg001"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1458,	24,	2794},
+	{"cvmx_pcieep_cfg002"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1459,	4,	2818},
+	{"cvmx_pcieep_cfg003"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1460,	5,	2822},
+	{"cvmx_pcieep_cfg004"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1461,	5,	2827},
+	{"cvmx_pcieep_cfg004_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1462,	2,	2832},
+	{"cvmx_pcieep_cfg005"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1463,	1,	2834},
+	{"cvmx_pcieep_cfg005_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1464,	1,	2835},
+	{"cvmx_pcieep_cfg006"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1465,	5,	2836},
+	{"cvmx_pcieep_cfg006_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1466,	2,	2841},
+	{"cvmx_pcieep_cfg007"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1467,	1,	2843},
+	{"cvmx_pcieep_cfg007_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1468,	1,	2844},
+	{"cvmx_pcieep_cfg008"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1469,	4,	2845},
+	{"cvmx_pcieep_cfg008_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1470,	2,	2849},
+	{"cvmx_pcieep_cfg009"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1471,	2,	2851},
+	{"cvmx_pcieep_cfg009_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1472,	1,	2853},
+	{"cvmx_pcieep_cfg010"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1473,	1,	2854},
+	{"cvmx_pcieep_cfg011"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1474,	2,	2855},
+	{"cvmx_pcieep_cfg012"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1475,	3,	2857},
+	{"cvmx_pcieep_cfg012_mask"     ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1476,	2,	2860},
+	{"cvmx_pcieep_cfg013"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1477,	2,	2862},
+	{"cvmx_pcieep_cfg015"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1478,	4,	2864},
+	{"cvmx_pcieep_cfg016"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1479,	10,	2868},
+	{"cvmx_pcieep_cfg017"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1480,	12,	2878},
+	{"cvmx_pcieep_cfg020"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1481,	7,	2890},
+	{"cvmx_pcieep_cfg021"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1482,	2,	2897},
+	{"cvmx_pcieep_cfg022"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1483,	1,	2899},
+	{"cvmx_pcieep_cfg023"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1484,	2,	2900},
+	{"cvmx_pcieep_cfg028"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1485,	7,	2902},
+	{"cvmx_pcieep_cfg029"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1486,	11,	2909},
+	{"cvmx_pcieep_cfg030"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1487,	19,	2920},
+	{"cvmx_pcieep_cfg031"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1488,	11,	2939},
+	{"cvmx_pcieep_cfg032"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1489,	17,	2950},
+	{"cvmx_pcieep_cfg033"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1490,	12,	2967},
+	{"cvmx_pcieep_cfg034"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1491,	22,	2979},
+	{"cvmx_pcieep_cfg037"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1492,	3,	3001},
+	{"cvmx_pcieep_cfg038"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1493,	3,	3004},
+	{"cvmx_pcieep_cfg039"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1494,	1,	3007},
+	{"cvmx_pcieep_cfg040"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1495,	1,	3008},
+	{"cvmx_pcieep_cfg041"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1496,	1,	3009},
+	{"cvmx_pcieep_cfg042"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1497,	1,	3010},
+	{"cvmx_pcieep_cfg064"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1498,	3,	3011},
+	{"cvmx_pcieep_cfg065"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1499,	14,	3014},
+	{"cvmx_pcieep_cfg066"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1500,	14,	3028},
+	{"cvmx_pcieep_cfg067"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1501,	14,	3042},
+	{"cvmx_pcieep_cfg068"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1502,	9,	3056},
+	{"cvmx_pcieep_cfg069"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1503,	9,	3065},
+	{"cvmx_pcieep_cfg070"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1504,	6,	3074},
+	{"cvmx_pcieep_cfg071"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1505,	1,	3080},
+	{"cvmx_pcieep_cfg072"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1506,	1,	3081},
+	{"cvmx_pcieep_cfg073"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1507,	1,	3082},
+	{"cvmx_pcieep_cfg074"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1508,	1,	3083},
+	{"cvmx_pcieep_cfg448"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1509,	2,	3084},
+	{"cvmx_pcieep_cfg449"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1510,	1,	3086},
+	{"cvmx_pcieep_cfg450"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1511,	6,	3087},
+	{"cvmx_pcieep_cfg451"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1512,	6,	3093},
+	{"cvmx_pcieep_cfg452"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1513,	13,	3099},
+	{"cvmx_pcieep_cfg453"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1514,	5,	3112},
+	{"cvmx_pcieep_cfg454"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1515,	8,	3117},
+	{"cvmx_pcieep_cfg455"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1516,	19,	3125},
+	{"cvmx_pcieep_cfg456"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1517,	3,	3144},
+	{"cvmx_pcieep_cfg458"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1518,	1,	3147},
+	{"cvmx_pcieep_cfg459"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1519,	1,	3148},
+	{"cvmx_pcieep_cfg460"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1520,	3,	3149},
+	{"cvmx_pcieep_cfg461"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1521,	3,	3152},
+	{"cvmx_pcieep_cfg462"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1522,	3,	3155},
+	{"cvmx_pcieep_cfg463"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1523,	4,	3158},
+	{"cvmx_pcieep_cfg464"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1524,	4,	3162},
+	{"cvmx_pcieep_cfg465"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1525,	4,	3166},
+	{"cvmx_pcieep_cfg466"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1526,	7,	3170},
+	{"cvmx_pcieep_cfg467"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1527,	5,	3177},
+	{"cvmx_pcieep_cfg468"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1528,	5,	3182},
+	{"cvmx_pcieep_cfg490"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1529,	4,	3187},
+	{"cvmx_pcieep_cfg491"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1530,	4,	3191},
+	{"cvmx_pcieep_cfg492"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1531,	4,	3195},
+	{"cvmx_pcieep_cfg516"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1532,	1,	3199},
+	{"cvmx_pcieep_cfg517"          ,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	1533,	1,	3200},
+	{"cvmx_pcierc#_cfg000"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1534,	2,	3201},
+	{"cvmx_pcierc#_cfg001"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1536,	24,	3203},
+	{"cvmx_pcierc#_cfg002"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1538,	4,	3227},
+	{"cvmx_pcierc#_cfg003"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1540,	5,	3231},
+	{"cvmx_pcierc#_cfg004"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1542,	1,	3236},
+	{"cvmx_pcierc#_cfg005"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1544,	1,	3237},
+	{"cvmx_pcierc#_cfg006"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1546,	4,	3238},
+	{"cvmx_pcierc#_cfg007"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1548,	17,	3242},
+	{"cvmx_pcierc#_cfg008"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1550,	4,	3259},
+	{"cvmx_pcierc#_cfg009"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1552,	6,	3263},
+	{"cvmx_pcierc#_cfg010"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1554,	1,	3269},
+	{"cvmx_pcierc#_cfg011"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1556,	1,	3270},
+	{"cvmx_pcierc#_cfg012"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1558,	2,	3271},
+	{"cvmx_pcierc#_cfg013"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1560,	2,	3273},
+	{"cvmx_pcierc#_cfg014"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1562,	1,	3275},
+	{"cvmx_pcierc#_cfg015"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1564,	15,	3276},
+	{"cvmx_pcierc#_cfg016"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1566,	10,	3291},
+	{"cvmx_pcierc#_cfg017"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1568,	12,	3301},
+	{"cvmx_pcierc#_cfg020"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1570,	7,	3313},
+	{"cvmx_pcierc#_cfg021"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1572,	2,	3320},
+	{"cvmx_pcierc#_cfg022"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1574,	1,	3322},
+	{"cvmx_pcierc#_cfg023"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1576,	2,	3323},
+	{"cvmx_pcierc#_cfg028"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1578,	7,	3325},
+	{"cvmx_pcierc#_cfg029"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1580,	11,	3332},
+	{"cvmx_pcierc#_cfg030"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1582,	19,	3343},
+	{"cvmx_pcierc#_cfg031"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1584,	11,	3362},
+	{"cvmx_pcierc#_cfg032"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1586,	20,	3373},
+	{"cvmx_pcierc#_cfg033"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1588,	12,	3393},
+	{"cvmx_pcierc#_cfg034"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1590,	22,	3405},
+	{"cvmx_pcierc#_cfg035"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1592,	8,	3427},
+	{"cvmx_pcierc#_cfg036"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1594,	4,	3435},
+	{"cvmx_pcierc#_cfg037"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1596,	3,	3439},
+	{"cvmx_pcierc#_cfg038"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1598,	3,	3442},
+	{"cvmx_pcierc#_cfg039"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1600,	1,	3445},
+	{"cvmx_pcierc#_cfg040"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1602,	1,	3446},
+	{"cvmx_pcierc#_cfg041"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1604,	1,	3447},
+	{"cvmx_pcierc#_cfg042"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1606,	1,	3448},
+	{"cvmx_pcierc#_cfg064"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1608,	3,	3449},
+	{"cvmx_pcierc#_cfg065"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1610,	14,	3452},
+	{"cvmx_pcierc#_cfg066"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1612,	14,	3466},
+	{"cvmx_pcierc#_cfg067"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1614,	14,	3480},
+	{"cvmx_pcierc#_cfg068"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1616,	9,	3494},
+	{"cvmx_pcierc#_cfg069"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1618,	9,	3503},
+	{"cvmx_pcierc#_cfg070"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1620,	6,	3512},
+	{"cvmx_pcierc#_cfg071"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1622,	1,	3518},
+	{"cvmx_pcierc#_cfg072"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1624,	1,	3519},
+	{"cvmx_pcierc#_cfg073"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1626,	1,	3520},
+	{"cvmx_pcierc#_cfg074"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1628,	1,	3521},
+	{"cvmx_pcierc#_cfg075"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1630,	4,	3522},
+	{"cvmx_pcierc#_cfg076"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1632,	9,	3526},
+	{"cvmx_pcierc#_cfg077"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1634,	2,	3535},
+	{"cvmx_pcierc#_cfg448"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1636,	2,	3537},
+	{"cvmx_pcierc#_cfg449"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1638,	1,	3539},
+	{"cvmx_pcierc#_cfg450"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1640,	6,	3540},
+	{"cvmx_pcierc#_cfg451"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1642,	6,	3546},
+	{"cvmx_pcierc#_cfg452"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1644,	13,	3552},
+	{"cvmx_pcierc#_cfg453"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1646,	5,	3565},
+	{"cvmx_pcierc#_cfg454"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1648,	8,	3570},
+	{"cvmx_pcierc#_cfg455"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1650,	19,	3578},
+	{"cvmx_pcierc#_cfg456"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1652,	3,	3597},
+	{"cvmx_pcierc#_cfg458"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1654,	1,	3600},
+	{"cvmx_pcierc#_cfg459"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1656,	1,	3601},
+	{"cvmx_pcierc#_cfg460"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1658,	3,	3602},
+	{"cvmx_pcierc#_cfg461"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1660,	3,	3605},
+	{"cvmx_pcierc#_cfg462"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1662,	3,	3608},
+	{"cvmx_pcierc#_cfg463"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1664,	4,	3611},
+	{"cvmx_pcierc#_cfg464"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1666,	4,	3615},
+	{"cvmx_pcierc#_cfg465"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1668,	4,	3619},
+	{"cvmx_pcierc#_cfg466"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1670,	7,	3623},
+	{"cvmx_pcierc#_cfg467"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1672,	5,	3630},
+	{"cvmx_pcierc#_cfg468"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1674,	5,	3635},
+	{"cvmx_pcierc#_cfg490"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1676,	4,	3640},
+	{"cvmx_pcierc#_cfg491"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1678,	4,	3644},
+	{"cvmx_pcierc#_cfg492"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1680,	4,	3648},
+	{"cvmx_pcierc#_cfg516"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1682,	1,	3652},
+	{"cvmx_pcierc#_cfg517"         ,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	1684,	1,	3653},
+	{"cvmx_pcs#_an#_adv_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1686,	9,	3654},
+	{"cvmx_pcs#_an#_ext_st_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1690,	6,	3663},
+	{"cvmx_pcs#_an#_lp_abil_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1694,	9,	3669},
+	{"cvmx_pcs#_an#_results_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1698,	6,	3678},
+	{"cvmx_pcs#_int#_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1702,	13,	3684},
+	{"cvmx_pcs#_int#_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1706,	13,	3697},
+	{"cvmx_pcs#_link#_timer_count_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1710,	2,	3710},
+	{"cvmx_pcs#_log_anl#_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1714,	4,	3712},
+	{"cvmx_pcs#_misc#_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1718,	8,	3716},
+	{"cvmx_pcs#_mr#_control_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1722,	13,	3724},
+	{"cvmx_pcs#_mr#_status_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1726,	17,	3737},
+	{"cvmx_pcs#_rx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1730,	7,	3754},
+	{"cvmx_pcs#_rx#_sync_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1734,	3,	3761},
+	{"cvmx_pcs#_sgm#_an_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1738,	8,	3764},
+	{"cvmx_pcs#_sgm#_lp_adv_reg"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1742,	7,	3772},
+	{"cvmx_pcs#_tx#_states_reg"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1746,	4,	3779},
+	{"cvmx_pcs#_tx_rx#_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1750,	5,	3783},
+	{"cvmx_pcsx#_10gbx_status_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1754,	8,	3788},
+	{"cvmx_pcsx#_bist_status_reg"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	1756,	2,	3796},
+	{"cvmx_pcsx#_bit_lock_status_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1758,	5,	3798},
+	{"cvmx_pcsx#_control1_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1760,	10,	3803},
+	{"cvmx_pcsx#_control2_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1762,	2,	3813},
+	{"cvmx_pcsx#_int_en_reg"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1764,	7,	3815},
+	{"cvmx_pcsx#_int_reg"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1766,	7,	3822},
+	{"cvmx_pcsx#_log_anl_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1768,	6,	3829},
+	{"cvmx_pcsx#_misc_ctl_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1770,	5,	3835},
+	{"cvmx_pcsx#_rx_sync_states_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1772,	5,	3840},
+	{"cvmx_pcsx#_spd_abil_reg"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1774,	3,	3845},
+	{"cvmx_pcsx#_status1_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1776,	6,	3848},
+	{"cvmx_pcsx#_status2_reg"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1778,	9,	3854},
+	{"cvmx_pcsx#_tx_rx_polarity_reg",	CVMX_CSR_DB_TYPE_RSL,	64,	1780,	5,	3863},
+	{"cvmx_pcsx#_tx_rx_states_reg" ,	CVMX_CSR_DB_TYPE_RSL,	64,	1782,	10,	3868},
+	{"cvmx_pesc#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1784,	14,	3878},
+	{"cvmx_pesc#_bist_status2"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1786,	15,	3892},
+	{"cvmx_pesc#_cfg_rd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1788,	2,	3907},
+	{"cvmx_pesc#_cfg_wr"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1790,	2,	3909},
+	{"cvmx_pesc#_cpl_lut_valid"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	1792,	2,	3911},
+	{"cvmx_pesc#_ctl_status"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1794,	16,	3913},
+	{"cvmx_pesc#_ctl_status2"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1796,	3,	3929},
+	{"cvmx_pesc#_dbg_info"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1798,	32,	3932},
+	{"cvmx_pesc#_dbg_info_en"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1800,	32,	3964},
+	{"cvmx_pesc#_diag_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1802,	5,	3996},
+	{"cvmx_pesc#_p2n_bar0_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1804,	2,	4001},
+	{"cvmx_pesc#_p2n_bar1_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1806,	2,	4003},
+	{"cvmx_pesc#_p2n_bar2_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1808,	2,	4005},
+	{"cvmx_pesc#_p2p_bar#_end"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	1810,	2,	4007},
+	{"cvmx_pesc#_p2p_bar#_start"   ,	CVMX_CSR_DB_TYPE_RSL,	64,	1818,	2,	4009},
+	{"cvmx_pesc#_tlp_credits"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	1826,	8,	4011},
+	{"cvmx_pip_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1828,	2,	4019},
+	{"cvmx_pip_dec_ipsec#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1829,	4,	4021},
+	{"cvmx_pip_dsa_src_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1833,	16,	4025},
+	{"cvmx_pip_dsa_vid_grp"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	1834,	16,	4041},
+	{"cvmx_pip_frm_len_chk#"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	1835,	3,	4057},
+	{"cvmx_pip_gbl_cfg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1837,	8,	4060},
+	{"cvmx_pip_gbl_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1838,	22,	4068},
+	{"cvmx_pip_hg_pri_qos"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1839,	6,	4090},
+	{"cvmx_pip_int_en"             ,	CVMX_CSR_DB_TYPE_RSL,	64,	1840,	14,	4096},
+	{"cvmx_pip_int_reg"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1841,	14,	4110},
+	{"cvmx_pip_ip_offset"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1842,	2,	4124},
+	{"cvmx_pip_prt_cfg#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1843,	28,	4126},
+	{"cvmx_pip_prt_tag#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1855,	25,	4154},
+	{"cvmx_pip_qos_diff#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1867,	2,	4179},
+	{"cvmx_pip_qos_vlan#"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	1931,	4,	4181},
+	{"cvmx_pip_qos_watch#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1939,	9,	4185},
+	{"cvmx_pip_raw_word"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	1947,	2,	4194},
+	{"cvmx_pip_sft_rst"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	1948,	2,	4196},
+	{"cvmx_pip_stat0_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1949,	2,	4198},
+	{"cvmx_pip_stat1_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1961,	2,	4200},
+	{"cvmx_pip_stat2_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1973,	2,	4202},
+	{"cvmx_pip_stat3_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1985,	2,	4204},
+	{"cvmx_pip_stat4_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	1997,	2,	4206},
+	{"cvmx_pip_stat5_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2009,	2,	4208},
+	{"cvmx_pip_stat6_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2021,	2,	4210},
+	{"cvmx_pip_stat7_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2033,	2,	4212},
+	{"cvmx_pip_stat8_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2045,	2,	4214},
+	{"cvmx_pip_stat9_prt#"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2057,	2,	4216},
+	{"cvmx_pip_stat_ctl"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2069,	2,	4218},
+	{"cvmx_pip_stat_inb_errs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2070,	2,	4220},
+	{"cvmx_pip_stat_inb_octs#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2082,	2,	4222},
+	{"cvmx_pip_stat_inb_pkts#"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2094,	2,	4224},
+	{"cvmx_pip_tag_inc#"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2106,	2,	4226},
+	{"cvmx_pip_tag_mask"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2170,	2,	4228},
+	{"cvmx_pip_tag_secret"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2171,	3,	4230},
+	{"cvmx_pip_todo_entry"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2172,	3,	4233},
+	{"cvmx_pko_mem_count0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2173,	2,	4236},
+	{"cvmx_pko_mem_count1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2174,	2,	4238},
+	{"cvmx_pko_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2175,	4,	4240},
+	{"cvmx_pko_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2176,	5,	4244},
+	{"cvmx_pko_mem_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2177,	4,	4249},
+	{"cvmx_pko_mem_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2178,	8,	4253},
+	{"cvmx_pko_mem_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2179,	4,	4261},
+	{"cvmx_pko_mem_debug13"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2180,	5,	4265},
+	{"cvmx_pko_mem_debug14"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2181,	1,	4270},
+	{"cvmx_pko_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2182,	5,	4271},
+	{"cvmx_pko_mem_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2183,	1,	4276},
+	{"cvmx_pko_mem_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2184,	13,	4277},
+	{"cvmx_pko_mem_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2185,	4,	4290},
+	{"cvmx_pko_mem_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2186,	13,	4294},
+	{"cvmx_pko_mem_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2187,	6,	4307},
+	{"cvmx_pko_mem_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2188,	9,	4313},
+	{"cvmx_pko_mem_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2189,	4,	4322},
+	{"cvmx_pko_mem_port_ptrs"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2190,	7,	4326},
+	{"cvmx_pko_mem_port_qos"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2191,	5,	4333},
+	{"cvmx_pko_mem_port_rate0"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2192,	5,	4338},
+	{"cvmx_pko_mem_port_rate1"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2193,	4,	4343},
+	{"cvmx_pko_mem_queue_ptrs"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2194,	9,	4347},
+	{"cvmx_pko_mem_queue_qos"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2195,	5,	4356},
+	{"cvmx_pko_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2196,	16,	4361},
+	{"cvmx_pko_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2197,	4,	4377},
+	{"cvmx_pko_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2198,	1,	4381},
+	{"cvmx_pko_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2199,	1,	4382},
+	{"cvmx_pko_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2200,	1,	4383},
+	{"cvmx_pko_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2201,	1,	4384},
+	{"cvmx_pko_reg_engine_inflight",	CVMX_CSR_DB_TYPE_RSL,	64,	2202,	11,	4385},
+	{"cvmx_pko_reg_engine_thresh"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2203,	2,	4396},
+	{"cvmx_pko_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2204,	4,	4398},
+	{"cvmx_pko_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2205,	5,	4402},
+	{"cvmx_pko_reg_gmx_port_mode"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2206,	3,	4407},
+	{"cvmx_pko_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2207,	4,	4410},
+	{"cvmx_pko_reg_queue_mode"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2208,	2,	4414},
+	{"cvmx_pko_reg_queue_ptrs1"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2209,	3,	4416},
+	{"cvmx_pko_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2210,	3,	4419},
+	{"cvmx_pow_bist_stat"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2211,	12,	4422},
+	{"cvmx_pow_ds_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2212,	2,	4434},
+	{"cvmx_pow_ecc_err"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2213,	13,	4436},
+	{"cvmx_pow_int_ctl"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2214,	3,	4449},
+	{"cvmx_pow_iq_cnt#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2215,	2,	4452},
+	{"cvmx_pow_iq_com_cnt"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2223,	2,	4454},
+	{"cvmx_pow_iq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2224,	2,	4456},
+	{"cvmx_pow_iq_int_en"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2225,	2,	4458},
+	{"cvmx_pow_iq_thr#"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2226,	2,	4460},
+	{"cvmx_pow_nos_cnt"            ,	CVMX_CSR_DB_TYPE_NCB,	64,	2234,	2,	4462},
+	{"cvmx_pow_nw_tim"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2235,	2,	4464},
+	{"cvmx_pow_pf_rst_msk"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2236,	2,	4466},
+	{"cvmx_pow_pp_grp_msk#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2237,	10,	4468},
+	{"cvmx_pow_qos_rnd#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2241,	5,	4478},
+	{"cvmx_pow_qos_thr#"           ,	CVMX_CSR_DB_TYPE_NCB,	64,	2249,	10,	4483},
+	{"cvmx_pow_ts_pc"              ,	CVMX_CSR_DB_TYPE_NCB,	64,	2257,	2,	4493},
+	{"cvmx_pow_wa_com_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2258,	2,	4495},
+	{"cvmx_pow_wa_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2259,	2,	4497},
+	{"cvmx_pow_wq_int"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2267,	3,	4499},
+	{"cvmx_pow_wq_int_cnt#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2268,	6,	4502},
+	{"cvmx_pow_wq_int_pc"          ,	CVMX_CSR_DB_TYPE_NCB,	64,	2284,	5,	4508},
+	{"cvmx_pow_wq_int_thr#"        ,	CVMX_CSR_DB_TYPE_NCB,	64,	2285,	7,	4513},
+	{"cvmx_pow_ws_pc#"             ,	CVMX_CSR_DB_TYPE_NCB,	64,	2301,	2,	4520},
+	{"cvmx_rad_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2317,	1,	4522},
+	{"cvmx_rad_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2318,	1,	4523},
+	{"cvmx_rad_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2319,	1,	4524},
+	{"cvmx_rad_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2320,	5,	4525},
+	{"cvmx_rad_reg_cmd_buf"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2321,	5,	4530},
+	{"cvmx_rad_reg_ctl"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2322,	4,	4535},
+	{"cvmx_rad_reg_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2323,	10,	4539},
+	{"cvmx_rad_reg_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2324,	1,	4549},
+	{"cvmx_rad_reg_debug10"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2325,	3,	4550},
+	{"cvmx_rad_reg_debug11"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2326,	7,	4553},
+	{"cvmx_rad_reg_debug12"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2327,	2,	4560},
+	{"cvmx_rad_reg_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2328,	1,	4562},
+	{"cvmx_rad_reg_debug3"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2329,	1,	4563},
+	{"cvmx_rad_reg_debug4"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2330,	1,	4564},
+	{"cvmx_rad_reg_debug5"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2331,	18,	4565},
+	{"cvmx_rad_reg_debug6"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2332,	3,	4583},
+	{"cvmx_rad_reg_debug7"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2333,	2,	4586},
+	{"cvmx_rad_reg_debug8"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2334,	3,	4588},
+	{"cvmx_rad_reg_debug9"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2335,	7,	4591},
+	{"cvmx_rad_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2336,	2,	4598},
+	{"cvmx_rad_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2337,	2,	4600},
+	{"cvmx_rad_reg_polynomial"     ,	CVMX_CSR_DB_TYPE_RSL,	64,	2338,	2,	4602},
+	{"cvmx_rad_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2339,	3,	4604},
+	{"cvmx_rnm_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2340,	3,	4607},
+	{"cvmx_rnm_ctl_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2341,	7,	4610},
+	{"cvmx_smi#_clk"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2342,	10,	4617},
+	{"cvmx_smi#_cmd"               ,	CVMX_CSR_DB_TYPE_RSL,	64,	2344,	6,	4627},
+	{"cvmx_smi#_en"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2346,	2,	4633},
+	{"cvmx_smi#_rd_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2348,	4,	4635},
+	{"cvmx_smi#_wr_dat"            ,	CVMX_CSR_DB_TYPE_RSL,	64,	2350,	4,	4639},
+	{"cvmx_tim_mem_debug0"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2352,	6,	4643},
+	{"cvmx_tim_mem_debug1"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2353,	3,	4649},
+	{"cvmx_tim_mem_debug2"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2354,	5,	4652},
+	{"cvmx_tim_mem_ring0"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2355,	4,	4657},
+	{"cvmx_tim_mem_ring1"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2356,	6,	4661},
+	{"cvmx_tim_reg_bist_result"    ,	CVMX_CSR_DB_TYPE_RSL,	64,	2357,	4,	4667},
+	{"cvmx_tim_reg_error"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2358,	2,	4671},
+	{"cvmx_tim_reg_flags"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2359,	4,	4673},
+	{"cvmx_tim_reg_int_mask"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2360,	2,	4677},
+	{"cvmx_tim_reg_read_idx"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2361,	3,	4679},
+	{"cvmx_tra_bist_status"        ,	CVMX_CSR_DB_TYPE_RSL,	64,	2362,	4,	4682},
+	{"cvmx_tra_ctl"                ,	CVMX_CSR_DB_TYPE_RSL,	64,	2363,	12,	4686},
+	{"cvmx_tra_cycles_since"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2364,	3,	4698},
+	{"cvmx_tra_cycles_since1"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2365,	5,	4701},
+	{"cvmx_tra_filt_adr_adr"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2366,	2,	4706},
+	{"cvmx_tra_filt_adr_msk"       ,	CVMX_CSR_DB_TYPE_RSL,	64,	2367,	2,	4708},
+	{"cvmx_tra_filt_cmd"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2368,	18,	4710},
+	{"cvmx_tra_filt_did"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2369,	12,	4728},
+	{"cvmx_tra_filt_sid"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2370,	6,	4740},
+	{"cvmx_tra_int_status"         ,	CVMX_CSR_DB_TYPE_RSL,	64,	2371,	5,	4746},
+	{"cvmx_tra_read_dat"           ,	CVMX_CSR_DB_TYPE_RSL,	64,	2372,	1,	4751},
+	{"cvmx_tra_trig0_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2373,	2,	4752},
+	{"cvmx_tra_trig0_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2374,	2,	4754},
+	{"cvmx_tra_trig0_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2375,	18,	4756},
+	{"cvmx_tra_trig0_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2376,	12,	4774},
+	{"cvmx_tra_trig0_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2377,	6,	4786},
+	{"cvmx_tra_trig1_adr_adr"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2378,	2,	4792},
+	{"cvmx_tra_trig1_adr_msk"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2379,	2,	4794},
+	{"cvmx_tra_trig1_cmd"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2380,	18,	4796},
+	{"cvmx_tra_trig1_did"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2381,	12,	4814},
+	{"cvmx_tra_trig1_sid"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2382,	6,	4826},
+	{"cvmx_usbc#_daint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2383,	2,	4832},
+	{"cvmx_usbc#_daintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2385,	2,	4834},
+	{"cvmx_usbc#_dcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2387,	8,	4836},
+	{"cvmx_usbc#_dctl"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2389,	11,	4844},
+	{"cvmx_usbc#_diepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2391,	15,	4855},
+	{"cvmx_usbc#_diepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2401,	8,	4870},
+	{"cvmx_usbc#_diepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2411,	8,	4878},
+	{"cvmx_usbc#_dieptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2413,	4,	4886},
+	{"cvmx_usbc#_doepctl#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2423,	15,	4890},
+	{"cvmx_usbc#_doepint#"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2433,	6,	4905},
+	{"cvmx_usbc#_doepmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2443,	6,	4911},
+	{"cvmx_usbc#_doeptsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2445,	4,	4917},
+	{"cvmx_usbc#_dptxfsiz#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2455,	2,	4921},
+	{"cvmx_usbc#_dsts"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2463,	6,	4923},
+	{"cvmx_usbc#_dtknqr1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2465,	4,	4929},
+	{"cvmx_usbc#_dtknqr2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2467,	1,	4933},
+	{"cvmx_usbc#_dtknqr3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2469,	1,	4934},
+	{"cvmx_usbc#_dtknqr4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2471,	1,	4935},
+	{"cvmx_usbc#_gahbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2473,	7,	4936},
+	{"cvmx_usbc#_ghwcfg1"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2475,	1,	4943},
+	{"cvmx_usbc#_ghwcfg2"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2477,	14,	4944},
+	{"cvmx_usbc#_ghwcfg3"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2479,	10,	4958},
+	{"cvmx_usbc#_ghwcfg4"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2481,	14,	4968},
+	{"cvmx_usbc#_gintmsk"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2483,	32,	4982},
+	{"cvmx_usbc#_gintsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2485,	32,	5014},
+	{"cvmx_usbc#_gnptxfsiz"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2487,	2,	5046},
+	{"cvmx_usbc#_gnptxsts"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2489,	4,	5048},
+	{"cvmx_usbc#_gotgctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2491,	13,	5052},
+	{"cvmx_usbc#_gotgint"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2493,	10,	5065},
+	{"cvmx_usbc#_grstctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2495,	10,	5075},
+	{"cvmx_usbc#_grxfsiz"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2497,	2,	5085},
+	{"cvmx_usbc#_grxstspd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2499,	6,	5087},
+	{"cvmx_usbc#_grxstsph"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2501,	5,	5093},
+	{"cvmx_usbc#_grxstsrd"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2503,	6,	5098},
+	{"cvmx_usbc#_grxstsrh"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2505,	5,	5104},
+	{"cvmx_usbc#_gsnpsid"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2507,	1,	5109},
+	{"cvmx_usbc#_gusbcfg"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2509,	13,	5110},
+	{"cvmx_usbc#_haint"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2511,	2,	5123},
+	{"cvmx_usbc#_haintmsk"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2513,	2,	5125},
+	{"cvmx_usbc#_hcchar#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2515,	11,	5127},
+	{"cvmx_usbc#_hcfg"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2531,	3,	5138},
+	{"cvmx_usbc#_hcint#"           ,	CVMX_CSR_DB_TYPE_NCB,	32,	2533,	12,	5141},
+	{"cvmx_usbc#_hcintmsk#"        ,	CVMX_CSR_DB_TYPE_NCB,	32,	2549,	12,	5153},
+	{"cvmx_usbc#_hcsplt#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2565,	6,	5165},
+	{"cvmx_usbc#_hctsiz#"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2581,	4,	5171},
+	{"cvmx_usbc#_hfir"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2597,	2,	5175},
+	{"cvmx_usbc#_hfnum"            ,	CVMX_CSR_DB_TYPE_NCB,	32,	2599,	2,	5177},
+	{"cvmx_usbc#_hprt"             ,	CVMX_CSR_DB_TYPE_NCB,	32,	2601,	15,	5179},
+	{"cvmx_usbc#_hptxfsiz"         ,	CVMX_CSR_DB_TYPE_NCB,	32,	2603,	2,	5194},
+	{"cvmx_usbc#_hptxsts"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2605,	3,	5196},
+	{"cvmx_usbc#_nptxdfifo#"       ,	CVMX_CSR_DB_TYPE_NCB,	32,	2607,	1,	5199},
+	{"cvmx_usbc#_pcgcctl"          ,	CVMX_CSR_DB_TYPE_NCB,	32,	2623,	6,	5200},
+	{"cvmx_usbn#_bist_status"      ,	CVMX_CSR_DB_TYPE_RSL,	64,	2625,	8,	5206},
+	{"cvmx_usbn#_clk_ctl"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2627,	15,	5214},
+	{"cvmx_usbn#_ctl_status"       ,	CVMX_CSR_DB_TYPE_NCB,	64,	2629,	6,	5229},
+	{"cvmx_usbn#_dma0_inb_chn0"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2631,	2,	5235},
+	{"cvmx_usbn#_dma0_inb_chn1"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2633,	2,	5237},
+	{"cvmx_usbn#_dma0_inb_chn2"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2635,	2,	5239},
+	{"cvmx_usbn#_dma0_inb_chn3"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2637,	2,	5241},
+	{"cvmx_usbn#_dma0_inb_chn4"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2639,	2,	5243},
+	{"cvmx_usbn#_dma0_inb_chn5"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2641,	2,	5245},
+	{"cvmx_usbn#_dma0_inb_chn6"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2643,	2,	5247},
+	{"cvmx_usbn#_dma0_inb_chn7"    ,	CVMX_CSR_DB_TYPE_NCB,	64,	2645,	2,	5249},
+	{"cvmx_usbn#_dma0_outb_chn0"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2647,	2,	5251},
+	{"cvmx_usbn#_dma0_outb_chn1"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2649,	2,	5253},
+	{"cvmx_usbn#_dma0_outb_chn2"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2651,	2,	5255},
+	{"cvmx_usbn#_dma0_outb_chn3"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2653,	2,	5257},
+	{"cvmx_usbn#_dma0_outb_chn4"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2655,	2,	5259},
+	{"cvmx_usbn#_dma0_outb_chn5"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2657,	2,	5261},
+	{"cvmx_usbn#_dma0_outb_chn6"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2659,	2,	5263},
+	{"cvmx_usbn#_dma0_outb_chn7"   ,	CVMX_CSR_DB_TYPE_NCB,	64,	2661,	2,	5265},
+	{"cvmx_usbn#_dma_test"         ,	CVMX_CSR_DB_TYPE_NCB,	64,	2663,	7,	5267},
+	{"cvmx_usbn#_int_enb"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2665,	34,	5274},
+	{"cvmx_usbn#_int_sum"          ,	CVMX_CSR_DB_TYPE_RSL,	64,	2667,	34,	5308},
+	{"cvmx_usbn#_usbp_ctl_status"  ,	CVMX_CSR_DB_TYPE_RSL,	64,	2669,	35,	5342},
+	{NULL,0,0,0,0,0}
+};
+static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
+	/* name                        ,	--------------address,	---------------type,	bits,	csr offset */
+	{"AGL_GMX_BAD_REG"             ,	   0x11800E0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	0},
+	{"AGL_GMX_BIST"                ,	   0x11800E0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	1},
+	{"AGL_GMX_DRV_CTL"             ,	   0x11800E00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	2},
+	{"AGL_GMX_INF_MODE"            ,	   0x11800E00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	3},
+	{"AGL_GMX_PRT0_CFG"            ,	   0x11800E0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_PRT1_CFG"            ,	   0x11800E0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	4},
+	{"AGL_GMX_RX0_ADR_CAM0"        ,	   0x11800E0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX1_ADR_CAM0"        ,	   0x11800E0000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	5},
+	{"AGL_GMX_RX0_ADR_CAM1"        ,	   0x11800E0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX1_ADR_CAM1"        ,	   0x11800E0000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	6},
+	{"AGL_GMX_RX0_ADR_CAM2"        ,	   0x11800E0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX1_ADR_CAM2"        ,	   0x11800E0000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	7},
+	{"AGL_GMX_RX0_ADR_CAM3"        ,	   0x11800E0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX1_ADR_CAM3"        ,	   0x11800E0000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	8},
+	{"AGL_GMX_RX0_ADR_CAM4"        ,	   0x11800E00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX1_ADR_CAM4"        ,	   0x11800E00009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	9},
+	{"AGL_GMX_RX0_ADR_CAM5"        ,	   0x11800E00001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX1_ADR_CAM5"        ,	   0x11800E00009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	10},
+	{"AGL_GMX_RX0_ADR_CAM_EN"      ,	   0x11800E0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX1_ADR_CAM_EN"      ,	   0x11800E0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	11},
+	{"AGL_GMX_RX0_ADR_CTL"         ,	   0x11800E0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX1_ADR_CTL"         ,	   0x11800E0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	12},
+	{"AGL_GMX_RX0_DECISION"        ,	   0x11800E0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX1_DECISION"        ,	   0x11800E0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	13},
+	{"AGL_GMX_RX0_FRM_CHK"         ,	   0x11800E0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX1_FRM_CHK"         ,	   0x11800E0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	14},
+	{"AGL_GMX_RX0_FRM_CTL"         ,	   0x11800E0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX1_FRM_CTL"         ,	   0x11800E0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	15},
+	{"AGL_GMX_RX0_FRM_MAX"         ,	   0x11800E0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX1_FRM_MAX"         ,	   0x11800E0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	16},
+	{"AGL_GMX_RX0_FRM_MIN"         ,	   0x11800E0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX1_FRM_MIN"         ,	   0x11800E0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	17},
+	{"AGL_GMX_RX0_IFG"             ,	   0x11800E0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX1_IFG"             ,	   0x11800E0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	18},
+	{"AGL_GMX_RX0_INT_EN"          ,	   0x11800E0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX1_INT_EN"          ,	   0x11800E0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	19},
+	{"AGL_GMX_RX0_INT_REG"         ,	   0x11800E0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX1_INT_REG"         ,	   0x11800E0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	20},
+	{"AGL_GMX_RX0_JABBER"          ,	   0x11800E0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX1_JABBER"          ,	   0x11800E0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	21},
+	{"AGL_GMX_RX0_PAUSE_DROP_TIME" ,	   0x11800E0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX1_PAUSE_DROP_TIME" ,	   0x11800E0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	22},
+	{"AGL_GMX_RX0_STATS_CTL"       ,	   0x11800E0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX1_STATS_CTL"       ,	   0x11800E0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	23},
+	{"AGL_GMX_RX0_STATS_OCTS"      ,	   0x11800E0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX1_STATS_OCTS"      ,	   0x11800E0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	24},
+	{"AGL_GMX_RX0_STATS_OCTS_CTL"  ,	   0x11800E0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX1_STATS_OCTS_CTL"  ,	   0x11800E0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	25},
+	{"AGL_GMX_RX0_STATS_OCTS_DMAC" ,	   0x11800E00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX1_STATS_OCTS_DMAC" ,	   0x11800E00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	26},
+	{"AGL_GMX_RX0_STATS_OCTS_DRP"  ,	   0x11800E00000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX1_STATS_OCTS_DRP"  ,	   0x11800E00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	27},
+	{"AGL_GMX_RX0_STATS_PKTS"      ,	   0x11800E0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX1_STATS_PKTS"      ,	   0x11800E0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	28},
+	{"AGL_GMX_RX0_STATS_PKTS_BAD"  ,	   0x11800E00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX1_STATS_PKTS_BAD"  ,	   0x11800E00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	29},
+	{"AGL_GMX_RX0_STATS_PKTS_CTL"  ,	   0x11800E0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX1_STATS_PKTS_CTL"  ,	   0x11800E0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	30},
+	{"AGL_GMX_RX0_STATS_PKTS_DMAC" ,	   0x11800E00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX1_STATS_PKTS_DMAC" ,	   0x11800E00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	31},
+	{"AGL_GMX_RX0_STATS_PKTS_DRP"  ,	   0x11800E00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX1_STATS_PKTS_DRP"  ,	   0x11800E00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	32},
+	{"AGL_GMX_RX0_UDD_SKP"         ,	   0x11800E0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX1_UDD_SKP"         ,	   0x11800E0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	33},
+	{"AGL_GMX_RX_BP_DROP0"         ,	   0x11800E0000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_DROP1"         ,	   0x11800E0000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	34},
+	{"AGL_GMX_RX_BP_OFF0"          ,	   0x11800E0000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_OFF1"          ,	   0x11800E0000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	35},
+	{"AGL_GMX_RX_BP_ON0"           ,	   0x11800E0000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_BP_ON1"           ,	   0x11800E0000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	36},
+	{"AGL_GMX_RX_PRT_INFO"         ,	   0x11800E00004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	37},
+	{"AGL_GMX_RX_TX_STATUS"        ,	   0x11800E00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	38},
+	{"AGL_GMX_SMAC0"               ,	   0x11800E0000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_SMAC1"               ,	   0x11800E0000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	39},
+	{"AGL_GMX_STAT_BP"             ,	   0x11800E0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	40},
+	{"AGL_GMX_TX0_APPEND"          ,	   0x11800E0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX1_APPEND"          ,	   0x11800E0000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	41},
+	{"AGL_GMX_TX0_CTL"             ,	   0x11800E0000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX1_CTL"             ,	   0x11800E0000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	42},
+	{"AGL_GMX_TX0_MIN_PKT"         ,	   0x11800E0000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX1_MIN_PKT"         ,	   0x11800E0000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	43},
+	{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",	   0x11800E0000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",	   0x11800E0000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	44},
+	{"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,	   0x11800E0000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,	   0x11800E0000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	45},
+	{"AGL_GMX_TX0_PAUSE_TOGO"      ,	   0x11800E0000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX1_PAUSE_TOGO"      ,	   0x11800E0000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	46},
+	{"AGL_GMX_TX0_PAUSE_ZERO"      ,	   0x11800E0000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX1_PAUSE_ZERO"      ,	   0x11800E0000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	47},
+	{"AGL_GMX_TX0_SOFT_PAUSE"      ,	   0x11800E0000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX1_SOFT_PAUSE"      ,	   0x11800E0000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	48},
+	{"AGL_GMX_TX0_STAT0"           ,	   0x11800E0000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX1_STAT0"           ,	   0x11800E0000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	49},
+	{"AGL_GMX_TX0_STAT1"           ,	   0x11800E0000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX1_STAT1"           ,	   0x11800E0000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	50},
+	{"AGL_GMX_TX0_STAT2"           ,	   0x11800E0000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX1_STAT2"           ,	   0x11800E0000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	51},
+	{"AGL_GMX_TX0_STAT3"           ,	   0x11800E0000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX1_STAT3"           ,	   0x11800E0000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	52},
+	{"AGL_GMX_TX0_STAT4"           ,	   0x11800E00002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX1_STAT4"           ,	   0x11800E0000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	53},
+	{"AGL_GMX_TX0_STAT5"           ,	   0x11800E00002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX1_STAT5"           ,	   0x11800E0000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	54},
+	{"AGL_GMX_TX0_STAT6"           ,	   0x11800E00002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX1_STAT6"           ,	   0x11800E0000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	55},
+	{"AGL_GMX_TX0_STAT7"           ,	   0x11800E00002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX1_STAT7"           ,	   0x11800E0000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	56},
+	{"AGL_GMX_TX0_STAT8"           ,	   0x11800E00002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX1_STAT8"           ,	   0x11800E0000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	57},
+	{"AGL_GMX_TX0_STAT9"           ,	   0x11800E00002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX1_STAT9"           ,	   0x11800E0000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	58},
+	{"AGL_GMX_TX0_STATS_CTL"       ,	   0x11800E0000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX1_STATS_CTL"       ,	   0x11800E0000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	59},
+	{"AGL_GMX_TX0_THRESH"          ,	   0x11800E0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX1_THRESH"          ,	   0x11800E0000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	60},
+	{"AGL_GMX_TX_BP"               ,	   0x11800E00004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	61},
+	{"AGL_GMX_TX_COL_ATTEMPT"      ,	   0x11800E0000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	62},
+	{"AGL_GMX_TX_IFG"              ,	   0x11800E0000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	63},
+	{"AGL_GMX_TX_INT_EN"           ,	   0x11800E0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	64},
+	{"AGL_GMX_TX_INT_REG"          ,	   0x11800E0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	65},
+	{"AGL_GMX_TX_JAM"              ,	   0x11800E0000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	66},
+	{"AGL_GMX_TX_LFSR"             ,	   0x11800E00004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	67},
+	{"AGL_GMX_TX_OVR_BP"           ,	   0x11800E00004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	68},
+	{"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,	   0x11800E00004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	69},
+	{"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,	   0x11800E00004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	70},
+	{"CIU_BIST"                    ,	   0x1070000000730ull,	CVMX_CSR_DB_TYPE_NCB,	64,	71},
+	{"CIU_DINT"                    ,	   0x1070000000720ull,	CVMX_CSR_DB_TYPE_NCB,	64,	72},
+	{"CIU_FUSE"                    ,	   0x1070000000728ull,	CVMX_CSR_DB_TYPE_NCB,	64,	73},
+	{"CIU_GSTOP"                   ,	   0x1070000000710ull,	CVMX_CSR_DB_TYPE_NCB,	64,	74},
+	{"CIU_INT0_EN0"                ,	   0x1070000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT1_EN0"                ,	   0x1070000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT2_EN0"                ,	   0x1070000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT3_EN0"                ,	   0x1070000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT4_EN0"                ,	   0x1070000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT5_EN0"                ,	   0x1070000000250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT6_EN0"                ,	   0x1070000000260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT7_EN0"                ,	   0x1070000000270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT32_EN0"               ,	   0x1070000000400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	75},
+	{"CIU_INT0_EN0_W1C"            ,	   0x1070000002200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT1_EN0_W1C"            ,	   0x1070000002210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT2_EN0_W1C"            ,	   0x1070000002220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT3_EN0_W1C"            ,	   0x1070000002230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT4_EN0_W1C"            ,	   0x1070000002240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT5_EN0_W1C"            ,	   0x1070000002250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT6_EN0_W1C"            ,	   0x1070000002260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT7_EN0_W1C"            ,	   0x1070000002270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT32_EN0_W1C"           ,	   0x1070000002400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	76},
+	{"CIU_INT0_EN0_W1S"            ,	   0x1070000006200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT1_EN0_W1S"            ,	   0x1070000006210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT2_EN0_W1S"            ,	   0x1070000006220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT3_EN0_W1S"            ,	   0x1070000006230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT4_EN0_W1S"            ,	   0x1070000006240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT5_EN0_W1S"            ,	   0x1070000006250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT6_EN0_W1S"            ,	   0x1070000006260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT7_EN0_W1S"            ,	   0x1070000006270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT32_EN0_W1S"           ,	   0x1070000006400ull,	CVMX_CSR_DB_TYPE_NCB,	64,	77},
+	{"CIU_INT0_EN1"                ,	   0x1070000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT1_EN1"                ,	   0x1070000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT2_EN1"                ,	   0x1070000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT3_EN1"                ,	   0x1070000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT4_EN1"                ,	   0x1070000000248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT5_EN1"                ,	   0x1070000000258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT6_EN1"                ,	   0x1070000000268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT7_EN1"                ,	   0x1070000000278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT32_EN1"               ,	   0x1070000000408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	78},
+	{"CIU_INT0_EN1_W1C"            ,	   0x1070000002208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT1_EN1_W1C"            ,	   0x1070000002218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT2_EN1_W1C"            ,	   0x1070000002228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT3_EN1_W1C"            ,	   0x1070000002238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT4_EN1_W1C"            ,	   0x1070000002248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT5_EN1_W1C"            ,	   0x1070000002258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT6_EN1_W1C"            ,	   0x1070000002268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT7_EN1_W1C"            ,	   0x1070000002278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT32_EN1_W1C"           ,	   0x1070000002408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	79},
+	{"CIU_INT0_EN1_W1S"            ,	   0x1070000006208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT1_EN1_W1S"            ,	   0x1070000006218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT2_EN1_W1S"            ,	   0x1070000006228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT3_EN1_W1S"            ,	   0x1070000006238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT4_EN1_W1S"            ,	   0x1070000006248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT5_EN1_W1S"            ,	   0x1070000006258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT6_EN1_W1S"            ,	   0x1070000006268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT7_EN1_W1S"            ,	   0x1070000006278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT32_EN1_W1S"           ,	   0x1070000006408ull,	CVMX_CSR_DB_TYPE_NCB,	64,	80},
+	{"CIU_INT0_EN4_0"              ,	   0x1070000000C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT1_EN4_0"              ,	   0x1070000000C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT2_EN4_0"              ,	   0x1070000000CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT3_EN4_0"              ,	   0x1070000000CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	81},
+	{"CIU_INT0_EN4_0_W1C"          ,	   0x1070000002C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT1_EN4_0_W1C"          ,	   0x1070000002C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT2_EN4_0_W1C"          ,	   0x1070000002CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT3_EN4_0_W1C"          ,	   0x1070000002CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	82},
+	{"CIU_INT0_EN4_0_W1S"          ,	   0x1070000006C80ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT1_EN4_0_W1S"          ,	   0x1070000006C90ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT2_EN4_0_W1S"          ,	   0x1070000006CA0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT3_EN4_0_W1S"          ,	   0x1070000006CB0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	83},
+	{"CIU_INT0_EN4_1"              ,	   0x1070000000C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT1_EN4_1"              ,	   0x1070000000C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT2_EN4_1"              ,	   0x1070000000CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT3_EN4_1"              ,	   0x1070000000CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	84},
+	{"CIU_INT0_EN4_1_W1C"          ,	   0x1070000002C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT1_EN4_1_W1C"          ,	   0x1070000002C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT2_EN4_1_W1C"          ,	   0x1070000002CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT3_EN4_1_W1C"          ,	   0x1070000002CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	85},
+	{"CIU_INT0_EN4_1_W1S"          ,	   0x1070000006C88ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT1_EN4_1_W1S"          ,	   0x1070000006C98ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT2_EN4_1_W1S"          ,	   0x1070000006CA8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT3_EN4_1_W1S"          ,	   0x1070000006CB8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	86},
+	{"CIU_INT0_SUM0"               ,	   0x1070000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT1_SUM0"               ,	   0x1070000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT2_SUM0"               ,	   0x1070000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT3_SUM0"               ,	   0x1070000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT4_SUM0"               ,	   0x1070000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT5_SUM0"               ,	   0x1070000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT6_SUM0"               ,	   0x1070000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT7_SUM0"               ,	   0x1070000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT32_SUM0"              ,	   0x1070000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	87},
+	{"CIU_INT0_SUM4"               ,	   0x1070000000C00ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT1_SUM4"               ,	   0x1070000000C08ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT2_SUM4"               ,	   0x1070000000C10ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT3_SUM4"               ,	   0x1070000000C18ull,	CVMX_CSR_DB_TYPE_NCB,	64,	88},
+	{"CIU_INT_SUM1"                ,	   0x1070000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	89},
+	{"CIU_MBOX_CLR0"               ,	   0x1070000000680ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR1"               ,	   0x1070000000688ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR2"               ,	   0x1070000000690ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_CLR3"               ,	   0x1070000000698ull,	CVMX_CSR_DB_TYPE_NCB,	64,	90},
+	{"CIU_MBOX_SET0"               ,	   0x1070000000600ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET1"               ,	   0x1070000000608ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET2"               ,	   0x1070000000610ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_MBOX_SET3"               ,	   0x1070000000618ull,	CVMX_CSR_DB_TYPE_NCB,	64,	91},
+	{"CIU_NMI"                     ,	   0x1070000000718ull,	CVMX_CSR_DB_TYPE_NCB,	64,	92},
+	{"CIU_PCI_INTA"                ,	   0x1070000000750ull,	CVMX_CSR_DB_TYPE_NCB,	64,	93},
+	{"CIU_PP_DBG"                  ,	   0x1070000000708ull,	CVMX_CSR_DB_TYPE_NCB,	64,	94},
+	{"CIU_PP_POKE0"                ,	   0x1070000000580ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE1"                ,	   0x1070000000588ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE2"                ,	   0x1070000000590ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_POKE3"                ,	   0x1070000000598ull,	CVMX_CSR_DB_TYPE_NCB,	64,	95},
+	{"CIU_PP_RST"                  ,	   0x1070000000700ull,	CVMX_CSR_DB_TYPE_NCB,	64,	96},
+	{"CIU_QLM_DCOK"                ,	   0x1070000000760ull,	CVMX_CSR_DB_TYPE_NCB,	64,	97},
+	{"CIU_QLM_JTGC"                ,	   0x1070000000768ull,	CVMX_CSR_DB_TYPE_NCB,	64,	98},
+	{"CIU_QLM_JTGD"                ,	   0x1070000000770ull,	CVMX_CSR_DB_TYPE_NCB,	64,	99},
+	{"CIU_SOFT_BIST"               ,	   0x1070000000738ull,	CVMX_CSR_DB_TYPE_NCB,	64,	100},
+	{"CIU_SOFT_PRST"               ,	   0x1070000000748ull,	CVMX_CSR_DB_TYPE_NCB,	64,	101},
+	{"CIU_SOFT_PRST1"              ,	   0x1070000000758ull,	CVMX_CSR_DB_TYPE_NCB,	64,	102},
+	{"CIU_SOFT_RST"                ,	   0x1070000000740ull,	CVMX_CSR_DB_TYPE_NCB,	64,	103},
+	{"CIU_TIM0"                    ,	   0x1070000000480ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_TIM1"                    ,	   0x1070000000488ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_TIM2"                    ,	   0x1070000000490ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_TIM3"                    ,	   0x1070000000498ull,	CVMX_CSR_DB_TYPE_NCB,	64,	104},
+	{"CIU_WDOG0"                   ,	   0x1070000000500ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG1"                   ,	   0x1070000000508ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG2"                   ,	   0x1070000000510ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"CIU_WDOG3"                   ,	   0x1070000000518ull,	CVMX_CSR_DB_TYPE_NCB,	64,	105},
+	{"FPA_BIST_STATUS"             ,	   0x11800280000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	106},
+	{"FPA_CTL_STATUS"              ,	   0x1180028000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	107},
+	{"FPA_INT_ENB"                 ,	   0x1180028000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	108},
+	{"FPA_INT_SUM"                 ,	   0x1180028000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	109},
+	{"FPA_QUE0_AVAILABLE"          ,	   0x1180028000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE1_AVAILABLE"          ,	   0x11800280000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE2_AVAILABLE"          ,	   0x11800280000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE3_AVAILABLE"          ,	   0x11800280000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE4_AVAILABLE"          ,	   0x11800280000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE5_AVAILABLE"          ,	   0x11800280000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE6_AVAILABLE"          ,	   0x11800280000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE7_AVAILABLE"          ,	   0x11800280000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	110},
+	{"FPA_QUE0_PAGE_INDEX"         ,	   0x11800280000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE1_PAGE_INDEX"         ,	   0x11800280000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE2_PAGE_INDEX"         ,	   0x1180028000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE3_PAGE_INDEX"         ,	   0x1180028000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE4_PAGE_INDEX"         ,	   0x1180028000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE5_PAGE_INDEX"         ,	   0x1180028000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE6_PAGE_INDEX"         ,	   0x1180028000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE7_PAGE_INDEX"         ,	   0x1180028000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	111},
+	{"FPA_QUE_ACT"                 ,	   0x1180028000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	112},
+	{"FPA_QUE_EXP"                 ,	   0x1180028000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	113},
+	{"FPA_WART_CTL"                ,	   0x11800280000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	114},
+	{"FPA_WART_STATUS"             ,	   0x11800280000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	115},
+	{"GMX0_BAD_REG"                ,	   0x1180008000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	116},
+	{"GMX0_BIST"                   ,	   0x1180008000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	117},
+	{"GMX0_CLK_EN"                 ,	   0x11800080007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	118},
+	{"GMX0_HG2_CONTROL"            ,	   0x1180008000550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	119},
+	{"GMX0_INF_MODE"               ,	   0x11800080007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	120},
+	{"GMX0_NXA_ADR"                ,	   0x1180008000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	121},
+	{"GMX0_PRT000_CBFC_CTL"        ,	   0x1180008000580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	122},
+	{"GMX0_PRT000_CFG"             ,	   0x1180008000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_PRT001_CFG"             ,	   0x1180008000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_PRT002_CFG"             ,	   0x1180008001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_PRT003_CFG"             ,	   0x1180008001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	123},
+	{"GMX0_RX000_ADR_CAM0"         ,	   0x1180008000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX001_ADR_CAM0"         ,	   0x1180008000980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX002_ADR_CAM0"         ,	   0x1180008001180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX003_ADR_CAM0"         ,	   0x1180008001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	124},
+	{"GMX0_RX000_ADR_CAM1"         ,	   0x1180008000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX001_ADR_CAM1"         ,	   0x1180008000988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX002_ADR_CAM1"         ,	   0x1180008001188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX003_ADR_CAM1"         ,	   0x1180008001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	125},
+	{"GMX0_RX000_ADR_CAM2"         ,	   0x1180008000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX001_ADR_CAM2"         ,	   0x1180008000990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX002_ADR_CAM2"         ,	   0x1180008001190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX003_ADR_CAM2"         ,	   0x1180008001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	126},
+	{"GMX0_RX000_ADR_CAM3"         ,	   0x1180008000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX001_ADR_CAM3"         ,	   0x1180008000998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX002_ADR_CAM3"         ,	   0x1180008001198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX003_ADR_CAM3"         ,	   0x1180008001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	127},
+	{"GMX0_RX000_ADR_CAM4"         ,	   0x11800080001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX001_ADR_CAM4"         ,	   0x11800080009A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX002_ADR_CAM4"         ,	   0x11800080011A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX003_ADR_CAM4"         ,	   0x11800080019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	128},
+	{"GMX0_RX000_ADR_CAM5"         ,	   0x11800080001A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX001_ADR_CAM5"         ,	   0x11800080009A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX002_ADR_CAM5"         ,	   0x11800080011A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX003_ADR_CAM5"         ,	   0x11800080019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	129},
+	{"GMX0_RX000_ADR_CAM_EN"       ,	   0x1180008000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX001_ADR_CAM_EN"       ,	   0x1180008000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX002_ADR_CAM_EN"       ,	   0x1180008001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX003_ADR_CAM_EN"       ,	   0x1180008001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	130},
+	{"GMX0_RX000_ADR_CTL"          ,	   0x1180008000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX001_ADR_CTL"          ,	   0x1180008000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX002_ADR_CTL"          ,	   0x1180008001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX003_ADR_CTL"          ,	   0x1180008001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	131},
+	{"GMX0_RX000_DECISION"         ,	   0x1180008000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX001_DECISION"         ,	   0x1180008000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX002_DECISION"         ,	   0x1180008001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX003_DECISION"         ,	   0x1180008001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	132},
+	{"GMX0_RX000_FRM_CHK"          ,	   0x1180008000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX001_FRM_CHK"          ,	   0x1180008000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX002_FRM_CHK"          ,	   0x1180008001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX003_FRM_CHK"          ,	   0x1180008001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	133},
+	{"GMX0_RX000_FRM_CTL"          ,	   0x1180008000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX001_FRM_CTL"          ,	   0x1180008000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX002_FRM_CTL"          ,	   0x1180008001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX003_FRM_CTL"          ,	   0x1180008001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	134},
+	{"GMX0_RX000_IFG"              ,	   0x1180008000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX001_IFG"              ,	   0x1180008000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX002_IFG"              ,	   0x1180008001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX003_IFG"              ,	   0x1180008001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	135},
+	{"GMX0_RX000_INT_EN"           ,	   0x1180008000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX001_INT_EN"           ,	   0x1180008000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX002_INT_EN"           ,	   0x1180008001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX003_INT_EN"           ,	   0x1180008001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	136},
+	{"GMX0_RX000_INT_REG"          ,	   0x1180008000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX001_INT_REG"          ,	   0x1180008000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX002_INT_REG"          ,	   0x1180008001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX003_INT_REG"          ,	   0x1180008001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	137},
+	{"GMX0_RX000_JABBER"           ,	   0x1180008000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX001_JABBER"           ,	   0x1180008000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX002_JABBER"           ,	   0x1180008001038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX003_JABBER"           ,	   0x1180008001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	138},
+	{"GMX0_RX000_PAUSE_DROP_TIME"  ,	   0x1180008000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX001_PAUSE_DROP_TIME"  ,	   0x1180008000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX002_PAUSE_DROP_TIME"  ,	   0x1180008001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX003_PAUSE_DROP_TIME"  ,	   0x1180008001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	139},
+	{"GMX0_RX000_STATS_CTL"        ,	   0x1180008000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX001_STATS_CTL"        ,	   0x1180008000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX002_STATS_CTL"        ,	   0x1180008001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX003_STATS_CTL"        ,	   0x1180008001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	140},
+	{"GMX0_RX000_STATS_OCTS"       ,	   0x1180008000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX001_STATS_OCTS"       ,	   0x1180008000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX002_STATS_OCTS"       ,	   0x1180008001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX003_STATS_OCTS"       ,	   0x1180008001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	141},
+	{"GMX0_RX000_STATS_OCTS_CTL"   ,	   0x1180008000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX001_STATS_OCTS_CTL"   ,	   0x1180008000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX002_STATS_OCTS_CTL"   ,	   0x1180008001098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX003_STATS_OCTS_CTL"   ,	   0x1180008001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	142},
+	{"GMX0_RX000_STATS_OCTS_DMAC"  ,	   0x11800080000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX001_STATS_OCTS_DMAC"  ,	   0x11800080008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX002_STATS_OCTS_DMAC"  ,	   0x11800080010A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX003_STATS_OCTS_DMAC"  ,	   0x11800080018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	143},
+	{"GMX0_RX000_STATS_OCTS_DRP"   ,	   0x11800080000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX001_STATS_OCTS_DRP"   ,	   0x11800080008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX002_STATS_OCTS_DRP"   ,	   0x11800080010B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX003_STATS_OCTS_DRP"   ,	   0x11800080018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	144},
+	{"GMX0_RX000_STATS_PKTS"       ,	   0x1180008000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX001_STATS_PKTS"       ,	   0x1180008000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX002_STATS_PKTS"       ,	   0x1180008001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX003_STATS_PKTS"       ,	   0x1180008001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	145},
+	{"GMX0_RX000_STATS_PKTS_BAD"   ,	   0x11800080000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX001_STATS_PKTS_BAD"   ,	   0x11800080008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX002_STATS_PKTS_BAD"   ,	   0x11800080010C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX003_STATS_PKTS_BAD"   ,	   0x11800080018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	146},
+	{"GMX0_RX000_STATS_PKTS_CTL"   ,	   0x1180008000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX001_STATS_PKTS_CTL"   ,	   0x1180008000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX002_STATS_PKTS_CTL"   ,	   0x1180008001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX003_STATS_PKTS_CTL"   ,	   0x1180008001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	147},
+	{"GMX0_RX000_STATS_PKTS_DMAC"  ,	   0x11800080000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX001_STATS_PKTS_DMAC"  ,	   0x11800080008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX002_STATS_PKTS_DMAC"  ,	   0x11800080010A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX003_STATS_PKTS_DMAC"  ,	   0x11800080018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	148},
+	{"GMX0_RX000_STATS_PKTS_DRP"   ,	   0x11800080000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX001_STATS_PKTS_DRP"   ,	   0x11800080008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX002_STATS_PKTS_DRP"   ,	   0x11800080010B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX003_STATS_PKTS_DRP"   ,	   0x11800080018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	149},
+	{"GMX0_RX000_UDD_SKP"          ,	   0x1180008000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX001_UDD_SKP"          ,	   0x1180008000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX002_UDD_SKP"          ,	   0x1180008001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX003_UDD_SKP"          ,	   0x1180008001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	150},
+	{"GMX0_RX_BP_DROP000"          ,	   0x1180008000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX_BP_DROP001"          ,	   0x1180008000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX_BP_DROP002"          ,	   0x1180008000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX_BP_DROP003"          ,	   0x1180008000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	151},
+	{"GMX0_RX_BP_OFF000"           ,	   0x1180008000460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX_BP_OFF001"           ,	   0x1180008000468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX_BP_OFF002"           ,	   0x1180008000470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX_BP_OFF003"           ,	   0x1180008000478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	152},
+	{"GMX0_RX_BP_ON000"            ,	   0x1180008000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX_BP_ON001"            ,	   0x1180008000448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX_BP_ON002"            ,	   0x1180008000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX_BP_ON003"            ,	   0x1180008000458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	153},
+	{"GMX0_RX_HG2_STATUS"          ,	   0x1180008000548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	154},
+	{"GMX0_RX_PRT_INFO"            ,	   0x11800080004E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	155},
+	{"GMX0_RX_PRTS"                ,	   0x1180008000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	156},
+	{"GMX0_RX_XAUI_BAD_COL"        ,	   0x1180008000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	157},
+	{"GMX0_RX_XAUI_CTL"            ,	   0x1180008000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	158},
+	{"GMX0_SMAC000"                ,	   0x1180008000230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_SMAC001"                ,	   0x1180008000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_SMAC002"                ,	   0x1180008001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_SMAC003"                ,	   0x1180008001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	159},
+	{"GMX0_STAT_BP"                ,	   0x1180008000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	160},
+	{"GMX0_TX000_APPEND"           ,	   0x1180008000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX001_APPEND"           ,	   0x1180008000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX002_APPEND"           ,	   0x1180008001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX003_APPEND"           ,	   0x1180008001A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	161},
+	{"GMX0_TX000_BURST"            ,	   0x1180008000228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX001_BURST"            ,	   0x1180008000A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX002_BURST"            ,	   0x1180008001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX003_BURST"            ,	   0x1180008001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	162},
+	{"GMX0_TX000_CBFC_XOFF"        ,	   0x11800080005A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	163},
+	{"GMX0_TX000_CBFC_XON"         ,	   0x11800080005C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	164},
+	{"GMX0_TX000_CTL"              ,	   0x1180008000270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX001_CTL"              ,	   0x1180008000A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX002_CTL"              ,	   0x1180008001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX003_CTL"              ,	   0x1180008001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	165},
+	{"GMX0_TX000_MIN_PKT"          ,	   0x1180008000240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX001_MIN_PKT"          ,	   0x1180008000A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX002_MIN_PKT"          ,	   0x1180008001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX003_MIN_PKT"          ,	   0x1180008001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	166},
+	{"GMX0_TX000_PAUSE_PKT_INTERVAL",	   0x1180008000248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX001_PAUSE_PKT_INTERVAL",	   0x1180008000A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX002_PAUSE_PKT_INTERVAL",	   0x1180008001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX003_PAUSE_PKT_INTERVAL",	   0x1180008001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	167},
+	{"GMX0_TX000_PAUSE_PKT_TIME"   ,	   0x1180008000238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX001_PAUSE_PKT_TIME"   ,	   0x1180008000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX002_PAUSE_PKT_TIME"   ,	   0x1180008001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX003_PAUSE_PKT_TIME"   ,	   0x1180008001A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	168},
+	{"GMX0_TX000_PAUSE_TOGO"       ,	   0x1180008000258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX001_PAUSE_TOGO"       ,	   0x1180008000A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX002_PAUSE_TOGO"       ,	   0x1180008001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX003_PAUSE_TOGO"       ,	   0x1180008001A58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	169},
+	{"GMX0_TX000_PAUSE_ZERO"       ,	   0x1180008000260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX001_PAUSE_ZERO"       ,	   0x1180008000A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX002_PAUSE_ZERO"       ,	   0x1180008001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX003_PAUSE_ZERO"       ,	   0x1180008001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	170},
+	{"GMX0_TX000_SGMII_CTL"        ,	   0x1180008000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX001_SGMII_CTL"        ,	   0x1180008000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX002_SGMII_CTL"        ,	   0x1180008001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX003_SGMII_CTL"        ,	   0x1180008001B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	171},
+	{"GMX0_TX000_SLOT"             ,	   0x1180008000220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX001_SLOT"             ,	   0x1180008000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX002_SLOT"             ,	   0x1180008001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX003_SLOT"             ,	   0x1180008001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	172},
+	{"GMX0_TX000_SOFT_PAUSE"       ,	   0x1180008000250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX001_SOFT_PAUSE"       ,	   0x1180008000A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX002_SOFT_PAUSE"       ,	   0x1180008001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX003_SOFT_PAUSE"       ,	   0x1180008001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	173},
+	{"GMX0_TX000_STAT0"            ,	   0x1180008000280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX001_STAT0"            ,	   0x1180008000A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX002_STAT0"            ,	   0x1180008001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX003_STAT0"            ,	   0x1180008001A80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	174},
+	{"GMX0_TX000_STAT1"            ,	   0x1180008000288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX001_STAT1"            ,	   0x1180008000A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX002_STAT1"            ,	   0x1180008001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX003_STAT1"            ,	   0x1180008001A88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	175},
+	{"GMX0_TX000_STAT2"            ,	   0x1180008000290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX001_STAT2"            ,	   0x1180008000A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX002_STAT2"            ,	   0x1180008001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX003_STAT2"            ,	   0x1180008001A90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	176},
+	{"GMX0_TX000_STAT3"            ,	   0x1180008000298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX001_STAT3"            ,	   0x1180008000A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX002_STAT3"            ,	   0x1180008001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX003_STAT3"            ,	   0x1180008001A98ull,	CVMX_CSR_DB_TYPE_RSL,	64,	177},
+	{"GMX0_TX000_STAT4"            ,	   0x11800080002A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX001_STAT4"            ,	   0x1180008000AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX002_STAT4"            ,	   0x11800080012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX003_STAT4"            ,	   0x1180008001AA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	178},
+	{"GMX0_TX000_STAT5"            ,	   0x11800080002A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX001_STAT5"            ,	   0x1180008000AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX002_STAT5"            ,	   0x11800080012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX003_STAT5"            ,	   0x1180008001AA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	179},
+	{"GMX0_TX000_STAT6"            ,	   0x11800080002B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX001_STAT6"            ,	   0x1180008000AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX002_STAT6"            ,	   0x11800080012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX003_STAT6"            ,	   0x1180008001AB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	180},
+	{"GMX0_TX000_STAT7"            ,	   0x11800080002B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX001_STAT7"            ,	   0x1180008000AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX002_STAT7"            ,	   0x11800080012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX003_STAT7"            ,	   0x1180008001AB8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	181},
+	{"GMX0_TX000_STAT8"            ,	   0x11800080002C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX001_STAT8"            ,	   0x1180008000AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX002_STAT8"            ,	   0x11800080012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX003_STAT8"            ,	   0x1180008001AC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	182},
+	{"GMX0_TX000_STAT9"            ,	   0x11800080002C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX001_STAT9"            ,	   0x1180008000AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX002_STAT9"            ,	   0x11800080012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX003_STAT9"            ,	   0x1180008001AC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	183},
+	{"GMX0_TX000_STATS_CTL"        ,	   0x1180008000268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX001_STATS_CTL"        ,	   0x1180008000A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX002_STATS_CTL"        ,	   0x1180008001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX003_STATS_CTL"        ,	   0x1180008001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	184},
+	{"GMX0_TX000_THRESH"           ,	   0x1180008000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX001_THRESH"           ,	   0x1180008000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX002_THRESH"           ,	   0x1180008001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX003_THRESH"           ,	   0x1180008001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	185},
+	{"GMX0_TX_BP"                  ,	   0x11800080004D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	186},
+	{"GMX0_TX_COL_ATTEMPT"         ,	   0x1180008000498ull,	CVMX_CSR_DB_TYPE_RSL,	64,	187},
+	{"GMX0_TX_CORRUPT"             ,	   0x11800080004D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	188},
+	{"GMX0_TX_HG2_REG1"            ,	   0x1180008000558ull,	CVMX_CSR_DB_TYPE_RSL,	64,	189},
+	{"GMX0_TX_HG2_REG2"            ,	   0x1180008000560ull,	CVMX_CSR_DB_TYPE_RSL,	64,	190},
+	{"GMX0_TX_IFG"                 ,	   0x1180008000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	191},
+	{"GMX0_TX_INT_EN"              ,	   0x1180008000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	192},
+	{"GMX0_TX_INT_REG"             ,	   0x1180008000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	193},
+	{"GMX0_TX_JAM"                 ,	   0x1180008000490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	194},
+	{"GMX0_TX_LFSR"                ,	   0x11800080004F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	195},
+	{"GMX0_TX_OVR_BP"              ,	   0x11800080004C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	196},
+	{"GMX0_TX_PAUSE_PKT_DMAC"      ,	   0x11800080004A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	197},
+	{"GMX0_TX_PAUSE_PKT_TYPE"      ,	   0x11800080004A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	198},
+	{"GMX0_TX_PRTS"                ,	   0x1180008000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	199},
+	{"GMX0_TX_XAUI_CTL"            ,	   0x1180008000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	200},
+	{"GMX0_XAUI_EXT_LOOPBACK"      ,	   0x1180008000540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	201},
+	{"GPIO_BIT_CFG0"               ,	   0x1070000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG1"               ,	   0x1070000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG2"               ,	   0x1070000000810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG3"               ,	   0x1070000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG4"               ,	   0x1070000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG5"               ,	   0x1070000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG6"               ,	   0x1070000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG7"               ,	   0x1070000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG8"               ,	   0x1070000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG9"               ,	   0x1070000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG10"              ,	   0x1070000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG11"              ,	   0x1070000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG12"              ,	   0x1070000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG13"              ,	   0x1070000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG14"              ,	   0x1070000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_BIT_CFG15"              ,	   0x1070000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	202},
+	{"GPIO_CLK_GEN0"               ,	   0x10700000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN1"               ,	   0x10700000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN2"               ,	   0x10700000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_CLK_GEN3"               ,	   0x10700000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	203},
+	{"GPIO_INT_CLR"                ,	   0x1070000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	204},
+	{"GPIO_RX_DAT"                 ,	   0x1070000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	205},
+	{"GPIO_TX_CLR"                 ,	   0x1070000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	206},
+	{"GPIO_TX_SET"                 ,	   0x1070000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	207},
+	{"IOB_BIST_STATUS"             ,	   0x11800F00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	208},
+	{"IOB_CTL_STATUS"              ,	   0x11800F0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	209},
+	{"IOB_DWB_PRI_CNT"             ,	   0x11800F0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	210},
+	{"IOB_FAU_TIMEOUT"             ,	   0x11800F0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	211},
+	{"IOB_I2C_PRI_CNT"             ,	   0x11800F0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	212},
+	{"IOB_INB_CONTROL_MATCH"       ,	   0x11800F0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	213},
+	{"IOB_INB_CONTROL_MATCH_ENB"   ,	   0x11800F0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	214},
+	{"IOB_INB_DATA_MATCH"          ,	   0x11800F0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	215},
+	{"IOB_INB_DATA_MATCH_ENB"      ,	   0x11800F0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	216},
+	{"IOB_INT_ENB"                 ,	   0x11800F0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	217},
+	{"IOB_INT_SUM"                 ,	   0x11800F0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	218},
+	{"IOB_N2C_L2C_PRI_CNT"         ,	   0x11800F0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	219},
+	{"IOB_N2C_RSP_PRI_CNT"         ,	   0x11800F0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	220},
+	{"IOB_OUTB_COM_PRI_CNT"        ,	   0x11800F0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	221},
+	{"IOB_OUTB_CONTROL_MATCH"      ,	   0x11800F0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	222},
+	{"IOB_OUTB_CONTROL_MATCH_ENB"  ,	   0x11800F00000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	223},
+	{"IOB_OUTB_DATA_MATCH"         ,	   0x11800F0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	224},
+	{"IOB_OUTB_DATA_MATCH_ENB"     ,	   0x11800F00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	225},
+	{"IOB_OUTB_FPA_PRI_CNT"        ,	   0x11800F0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	226},
+	{"IOB_OUTB_REQ_PRI_CNT"        ,	   0x11800F0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	227},
+	{"IOB_P2C_REQ_PRI_CNT"         ,	   0x11800F0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	228},
+	{"IOB_PKT_ERR"                 ,	   0x11800F0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	229},
+	{"IOB_TO_CMB_CREDITS"          ,	   0x11800F00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	230},
+	{"IPD_1ST_MBUFF_SKIP"          ,	   0x14F0000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	231},
+	{"IPD_1ST_NEXT_PTR_BACK"       ,	   0x14F0000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	232},
+	{"IPD_2ND_NEXT_PTR_BACK"       ,	   0x14F0000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	233},
+	{"IPD_BIST_STATUS"             ,	   0x14F00000007F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	234},
+	{"IPD_BP_PRT_RED_END"          ,	   0x14F0000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	235},
+	{"IPD_CLK_COUNT"               ,	   0x14F0000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	236},
+	{"IPD_CTL_STATUS"              ,	   0x14F0000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	237},
+	{"IPD_INT_ENB"                 ,	   0x14F0000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	238},
+	{"IPD_INT_SUM"                 ,	   0x14F0000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	239},
+	{"IPD_NOT_1ST_MBUFF_SKIP"      ,	   0x14F0000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	240},
+	{"IPD_PACKET_MBUFF_SIZE"       ,	   0x14F0000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	241},
+	{"IPD_PKT_PTR_VALID"           ,	   0x14F0000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	242},
+	{"IPD_PORT0_BP_PAGE_CNT"       ,	   0x14F0000000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT1_BP_PAGE_CNT"       ,	   0x14F0000000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT2_BP_PAGE_CNT"       ,	   0x14F0000000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT3_BP_PAGE_CNT"       ,	   0x14F0000000040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT32_BP_PAGE_CNT"      ,	   0x14F0000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT33_BP_PAGE_CNT"      ,	   0x14F0000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT34_BP_PAGE_CNT"      ,	   0x14F0000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT35_BP_PAGE_CNT"      ,	   0x14F0000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	243},
+	{"IPD_PORT36_BP_PAGE_CNT2"     ,	   0x14F0000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT37_BP_PAGE_CNT2"     ,	   0x14F0000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT38_BP_PAGE_CNT2"     ,	   0x14F0000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT39_BP_PAGE_CNT2"     ,	   0x14F0000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	244},
+	{"IPD_PORT_BP_COUNTERS2_PAIR36",	   0x14F0000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS2_PAIR37",	   0x14F0000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS2_PAIR38",	   0x14F0000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS2_PAIR39",	   0x14F00000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	245},
+	{"IPD_PORT_BP_COUNTERS_PAIR0"  ,	   0x14F00000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR1"  ,	   0x14F00000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR2"  ,	   0x14F00000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR3"  ,	   0x14F00000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR32" ,	   0x14F00000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR33" ,	   0x14F00000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR34" ,	   0x14F00000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_BP_COUNTERS_PAIR35" ,	   0x14F00000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	246},
+	{"IPD_PORT_QOS_0_CNT"          ,	   0x14F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_1_CNT"          ,	   0x14F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_2_CNT"          ,	   0x14F0000000898ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_3_CNT"          ,	   0x14F00000008A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_4_CNT"          ,	   0x14F00000008A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_5_CNT"          ,	   0x14F00000008B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_6_CNT"          ,	   0x14F00000008B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_7_CNT"          ,	   0x14F00000008C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_8_CNT"          ,	   0x14F00000008C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_9_CNT"          ,	   0x14F00000008D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_10_CNT"         ,	   0x14F00000008D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_11_CNT"         ,	   0x14F00000008E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_12_CNT"         ,	   0x14F00000008E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_13_CNT"         ,	   0x14F00000008F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_14_CNT"         ,	   0x14F00000008F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_15_CNT"         ,	   0x14F0000000900ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_16_CNT"         ,	   0x14F0000000908ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_17_CNT"         ,	   0x14F0000000910ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_18_CNT"         ,	   0x14F0000000918ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_19_CNT"         ,	   0x14F0000000920ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_20_CNT"         ,	   0x14F0000000928ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_21_CNT"         ,	   0x14F0000000930ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_22_CNT"         ,	   0x14F0000000938ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_23_CNT"         ,	   0x14F0000000940ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_24_CNT"         ,	   0x14F0000000948ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_25_CNT"         ,	   0x14F0000000950ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_26_CNT"         ,	   0x14F0000000958ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_27_CNT"         ,	   0x14F0000000960ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_28_CNT"         ,	   0x14F0000000968ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_29_CNT"         ,	   0x14F0000000970ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_30_CNT"         ,	   0x14F0000000978ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_31_CNT"         ,	   0x14F0000000980ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_256_CNT"        ,	   0x14F0000001088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_257_CNT"        ,	   0x14F0000001090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_258_CNT"        ,	   0x14F0000001098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_259_CNT"        ,	   0x14F00000010A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_260_CNT"        ,	   0x14F00000010A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_261_CNT"        ,	   0x14F00000010B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_262_CNT"        ,	   0x14F00000010B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_263_CNT"        ,	   0x14F00000010C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_264_CNT"        ,	   0x14F00000010C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_265_CNT"        ,	   0x14F00000010D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_266_CNT"        ,	   0x14F00000010D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_267_CNT"        ,	   0x14F00000010E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_268_CNT"        ,	   0x14F00000010E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_269_CNT"        ,	   0x14F00000010F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_270_CNT"        ,	   0x14F00000010F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_271_CNT"        ,	   0x14F0000001100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_272_CNT"        ,	   0x14F0000001108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_273_CNT"        ,	   0x14F0000001110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_274_CNT"        ,	   0x14F0000001118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_275_CNT"        ,	   0x14F0000001120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_276_CNT"        ,	   0x14F0000001128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_277_CNT"        ,	   0x14F0000001130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_278_CNT"        ,	   0x14F0000001138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_279_CNT"        ,	   0x14F0000001140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_280_CNT"        ,	   0x14F0000001148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_281_CNT"        ,	   0x14F0000001150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_282_CNT"        ,	   0x14F0000001158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_283_CNT"        ,	   0x14F0000001160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_284_CNT"        ,	   0x14F0000001168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_285_CNT"        ,	   0x14F0000001170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_286_CNT"        ,	   0x14F0000001178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_287_CNT"        ,	   0x14F0000001180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_288_CNT"        ,	   0x14F0000001188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_289_CNT"        ,	   0x14F0000001190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_290_CNT"        ,	   0x14F0000001198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_291_CNT"        ,	   0x14F00000011A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_292_CNT"        ,	   0x14F00000011A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_293_CNT"        ,	   0x14F00000011B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_294_CNT"        ,	   0x14F00000011B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_295_CNT"        ,	   0x14F00000011C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_296_CNT"        ,	   0x14F00000011C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_297_CNT"        ,	   0x14F00000011D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_298_CNT"        ,	   0x14F00000011D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_299_CNT"        ,	   0x14F00000011E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_300_CNT"        ,	   0x14F00000011E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_301_CNT"        ,	   0x14F00000011F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_302_CNT"        ,	   0x14F00000011F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_303_CNT"        ,	   0x14F0000001200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_304_CNT"        ,	   0x14F0000001208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_305_CNT"        ,	   0x14F0000001210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_306_CNT"        ,	   0x14F0000001218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_307_CNT"        ,	   0x14F0000001220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_308_CNT"        ,	   0x14F0000001228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_309_CNT"        ,	   0x14F0000001230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_310_CNT"        ,	   0x14F0000001238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_311_CNT"        ,	   0x14F0000001240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_312_CNT"        ,	   0x14F0000001248ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_313_CNT"        ,	   0x14F0000001250ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_314_CNT"        ,	   0x14F0000001258ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_315_CNT"        ,	   0x14F0000001260ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_316_CNT"        ,	   0x14F0000001268ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_317_CNT"        ,	   0x14F0000001270ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_318_CNT"        ,	   0x14F0000001278ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_319_CNT"        ,	   0x14F0000001280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	247},
+	{"IPD_PORT_QOS_INT0"           ,	   0x14F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_QOS_INT4"           ,	   0x14F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	248},
+	{"IPD_PORT_QOS_INT_ENB0"       ,	   0x14F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PORT_QOS_INT_ENB4"       ,	   0x14F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	249},
+	{"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,	   0x14F0000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	250},
+	{"IPD_PRC_PORT_PTR_FIFO_CTL"   ,	   0x14F0000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	251},
+	{"IPD_PTR_COUNT"               ,	   0x14F0000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	252},
+	{"IPD_PWP_PTR_FIFO_CTL"        ,	   0x14F0000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	253},
+	{"IPD_QOS0_RED_MARKS"          ,	   0x14F0000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS1_RED_MARKS"          ,	   0x14F0000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS2_RED_MARKS"          ,	   0x14F0000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS3_RED_MARKS"          ,	   0x14F0000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS4_RED_MARKS"          ,	   0x14F0000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS5_RED_MARKS"          ,	   0x14F00000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS6_RED_MARKS"          ,	   0x14F00000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QOS7_RED_MARKS"          ,	   0x14F00000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	254},
+	{"IPD_QUE0_FREE_PAGE_CNT"      ,	   0x14F0000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	255},
+	{"IPD_RED_PORT_ENABLE"         ,	   0x14F00000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	256},
+	{"IPD_RED_PORT_ENABLE2"        ,	   0x14F00000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	257},
+	{"IPD_RED_QUE0_PARAM"          ,	   0x14F00000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE1_PARAM"          ,	   0x14F00000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE2_PARAM"          ,	   0x14F00000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE3_PARAM"          ,	   0x14F00000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE4_PARAM"          ,	   0x14F0000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE5_PARAM"          ,	   0x14F0000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE6_PARAM"          ,	   0x14F0000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_RED_QUE7_PARAM"          ,	   0x14F0000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	258},
+	{"IPD_SUB_PORT_BP_PAGE_CNT"    ,	   0x14F0000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	259},
+	{"IPD_SUB_PORT_FCS"            ,	   0x14F0000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	260},
+	{"IPD_SUB_PORT_QOS_CNT"        ,	   0x14F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	261},
+	{"IPD_WQE_FPA_QUEUE"           ,	   0x14F0000000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	262},
+	{"IPD_WQE_PTR_VALID"           ,	   0x14F0000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	263},
+	{"L2C_BST0"                    ,	   0x11800800007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	264},
+	{"L2C_BST1"                    ,	   0x11800800007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	265},
+	{"L2C_BST2"                    ,	   0x11800800007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	266},
+	{"L2C_CFG"                     ,	   0x1180080000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	267},
+	{"L2C_DBG"                     ,	   0x1180080000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	268},
+	{"L2C_DUT"                     ,	   0x1180080000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	269},
+	{"L2C_GRPWRR0"                 ,	   0x11800800000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	270},
+	{"L2C_GRPWRR1"                 ,	   0x11800800000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	271},
+	{"L2C_INT_EN"                  ,	   0x1180080000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	272},
+	{"L2C_INT_STAT"                ,	   0x11800800000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	273},
+	{"L2C_LCKBASE"                 ,	   0x1180080000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	274},
+	{"L2C_LCKOFF"                  ,	   0x1180080000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	275},
+	{"L2C_LFB0"                    ,	   0x1180080000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	276},
+	{"L2C_LFB1"                    ,	   0x1180080000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	277},
+	{"L2C_LFB2"                    ,	   0x1180080000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	278},
+	{"L2C_LFB3"                    ,	   0x11800800000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	279},
+	{"L2C_OOB"                     ,	   0x11800800000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	280},
+	{"L2C_OOB1"                    ,	   0x11800800000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	281},
+	{"L2C_OOB2"                    ,	   0x11800800000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	282},
+	{"L2C_OOB3"                    ,	   0x11800800000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	283},
+	{"L2C_PFC0"                    ,	   0x1180080000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFC1"                    ,	   0x11800800000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFC2"                    ,	   0x11800800000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFC3"                    ,	   0x11800800000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	284},
+	{"L2C_PFCTL"                   ,	   0x1180080000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	285},
+	{"L2C_PPGRP"                   ,	   0x11800800000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	286},
+	{"L2C_SPAR0"                   ,	   0x1180080000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	287},
+	{"L2C_SPAR4"                   ,	   0x1180080000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	288},
+	{"L2D_BST0"                    ,	   0x1180080000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	289},
+	{"L2D_BST1"                    ,	   0x1180080000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	290},
+	{"L2D_BST2"                    ,	   0x1180080000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	291},
+	{"L2D_BST3"                    ,	   0x1180080000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	292},
+	{"L2D_ERR"                     ,	   0x1180080000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	293},
+	{"L2D_FADR"                    ,	   0x1180080000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	294},
+	{"L2D_FSYN0"                   ,	   0x1180080000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	295},
+	{"L2D_FSYN1"                   ,	   0x1180080000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	296},
+	{"L2D_FUS0"                    ,	   0x11800800007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	297},
+	{"L2D_FUS1"                    ,	   0x11800800007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	298},
+	{"L2D_FUS2"                    ,	   0x11800800007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	299},
+	{"L2D_FUS3"                    ,	   0x11800800007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	300},
+	{"L2T_ERR"                     ,	   0x1180080000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	301},
+	{"LMC0_BIST_CTL"               ,	   0x11800880000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	302},
+	{"LMC0_BIST_RESULT"            ,	   0x11800880000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	303},
+	{"LMC0_COMP_CTL"               ,	   0x1180088000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	304},
+	{"LMC0_CTL"                    ,	   0x1180088000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	305},
+	{"LMC0_CTL1"                   ,	   0x1180088000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	306},
+	{"LMC0_DCLK_CNT_HI"            ,	   0x1180088000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	307},
+	{"LMC0_DCLK_CNT_LO"            ,	   0x1180088000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	308},
+	{"LMC0_DDR2_CTL"               ,	   0x1180088000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	309},
+	{"LMC0_DELAY_CFG"              ,	   0x1180088000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	310},
+	{"LMC0_DLL_CTL"                ,	   0x11800880000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	311},
+	{"LMC0_DUAL_MEMCFG"            ,	   0x1180088000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	312},
+	{"LMC0_ECC_SYND"               ,	   0x1180088000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	313},
+	{"LMC0_FADR"                   ,	   0x1180088000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	314},
+	{"LMC0_IFB_CNT_HI"             ,	   0x1180088000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	315},
+	{"LMC0_IFB_CNT_LO"             ,	   0x1180088000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	316},
+	{"LMC0_MEM_CFG0"               ,	   0x1180088000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	317},
+	{"LMC0_MEM_CFG1"               ,	   0x1180088000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	318},
+	{"LMC0_NXM"                    ,	   0x11800880000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	319},
+	{"LMC0_OPS_CNT_HI"             ,	   0x1180088000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	320},
+	{"LMC0_OPS_CNT_LO"             ,	   0x1180088000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	321},
+	{"LMC0_PLL_CTL"                ,	   0x11800880000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	322},
+	{"LMC0_PLL_STATUS"             ,	   0x11800880000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	323},
+	{"LMC0_READ_LEVEL_CTL"         ,	   0x1180088000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	324},
+	{"LMC0_READ_LEVEL_DBG"         ,	   0x1180088000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	325},
+	{"LMC0_READ_LEVEL_RANK000"     ,	   0x1180088000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC0_READ_LEVEL_RANK001"     ,	   0x1180088000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC0_READ_LEVEL_RANK002"     ,	   0x1180088000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC0_READ_LEVEL_RANK003"     ,	   0x1180088000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	326},
+	{"LMC0_RODT_COMP_CTL"          ,	   0x11800880000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	327},
+	{"LMC0_RODT_CTL"               ,	   0x1180088000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	328},
+	{"LMC0_WODT_CTL0"              ,	   0x1180088000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	329},
+	{"LMC0_WODT_CTL1"              ,	   0x1180088000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	330},
+	{"MIO_BOOT_BIST_STAT"          ,	   0x11800000000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	331},
+	{"MIO_BOOT_COMP"               ,	   0x11800000000B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	332},
+	{"MIO_BOOT_DMA_CFG0"           ,	   0x1180000000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_BOOT_DMA_CFG1"           ,	   0x1180000000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	333},
+	{"MIO_BOOT_DMA_INT0"           ,	   0x1180000000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_BOOT_DMA_INT1"           ,	   0x1180000000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	334},
+	{"MIO_BOOT_DMA_INT_EN0"        ,	   0x1180000000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"MIO_BOOT_DMA_INT_EN1"        ,	   0x1180000000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	335},
+	{"MIO_BOOT_DMA_TIM0"           ,	   0x1180000000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_BOOT_DMA_TIM1"           ,	   0x1180000000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	336},
+	{"MIO_BOOT_ERR"                ,	   0x11800000000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	337},
+	{"MIO_BOOT_INT"                ,	   0x11800000000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	338},
+	{"MIO_BOOT_LOC_ADR"            ,	   0x1180000000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	339},
+	{"MIO_BOOT_LOC_CFG0"           ,	   0x1180000000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_BOOT_LOC_CFG1"           ,	   0x1180000000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	340},
+	{"MIO_BOOT_LOC_DAT"            ,	   0x1180000000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	341},
+	{"MIO_BOOT_PIN_DEFS"           ,	   0x11800000000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	342},
+	{"MIO_BOOT_REG_CFG0"           ,	   0x1180000000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG1"           ,	   0x1180000000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG2"           ,	   0x1180000000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG3"           ,	   0x1180000000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG4"           ,	   0x1180000000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG5"           ,	   0x1180000000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG6"           ,	   0x1180000000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_CFG7"           ,	   0x1180000000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	343},
+	{"MIO_BOOT_REG_TIM0"           ,	   0x1180000000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM1"           ,	   0x1180000000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM2"           ,	   0x1180000000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM3"           ,	   0x1180000000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM4"           ,	   0x1180000000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM5"           ,	   0x1180000000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM6"           ,	   0x1180000000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_REG_TIM7"           ,	   0x1180000000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	344},
+	{"MIO_BOOT_THR"                ,	   0x11800000000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	345},
+	{"MIO_FUS_BNK_DAT0"            ,	   0x1180000001520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_FUS_BNK_DAT1"            ,	   0x1180000001528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_FUS_BNK_DAT2"            ,	   0x1180000001530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_FUS_BNK_DAT3"            ,	   0x1180000001538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	346},
+	{"MIO_FUS_DAT0"                ,	   0x1180000001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	347},
+	{"MIO_FUS_DAT1"                ,	   0x1180000001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	348},
+	{"MIO_FUS_DAT2"                ,	   0x1180000001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	349},
+	{"MIO_FUS_DAT3"                ,	   0x1180000001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	350},
+	{"MIO_FUS_EMA"                 ,	   0x1180000001550ull,	CVMX_CSR_DB_TYPE_RSL,	64,	351},
+	{"MIO_FUS_PDF"                 ,	   0x1180000001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	352},
+	{"MIO_FUS_PLL"                 ,	   0x1180000001580ull,	CVMX_CSR_DB_TYPE_RSL,	64,	353},
+	{"MIO_FUS_PROG"                ,	   0x1180000001510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	354},
+	{"MIO_FUS_PROG_TIMES"          ,	   0x1180000001518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	355},
+	{"MIO_FUS_RCMD"                ,	   0x1180000001500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	356},
+	{"MIO_FUS_SPR_REPAIR_RES"      ,	   0x1180000001548ull,	CVMX_CSR_DB_TYPE_RSL,	64,	357},
+	{"MIO_FUS_SPR_REPAIR_SUM"      ,	   0x1180000001540ull,	CVMX_CSR_DB_TYPE_RSL,	64,	358},
+	{"MIO_FUS_WADR"                ,	   0x1180000001508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	359},
+	{"MIO_NDF_DMA_CFG"             ,	   0x1180000000168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	360},
+	{"MIO_NDF_DMA_INT"             ,	   0x1180000000170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	361},
+	{"MIO_NDF_DMA_INT_EN"          ,	   0x1180000000178ull,	CVMX_CSR_DB_TYPE_RSL,	64,	362},
+	{"MIO_TWS0_INT"                ,	   0x1180000001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_TWS1_INT"                ,	   0x1180000001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	363},
+	{"MIO_TWS0_SW_TWSI"            ,	   0x1180000001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_TWS1_SW_TWSI"            ,	   0x1180000001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	364},
+	{"MIO_TWS0_SW_TWSI_EXT"        ,	   0x1180000001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_TWS1_SW_TWSI_EXT"        ,	   0x1180000001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	365},
+	{"MIO_TWS0_TWSI_SW"            ,	   0x1180000001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_TWS1_TWSI_SW"            ,	   0x1180000001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	366},
+	{"MIO_UART0_DLH"               ,	   0x1180000000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART1_DLH"               ,	   0x1180000000C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	367},
+	{"MIO_UART0_DLL"               ,	   0x1180000000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART1_DLL"               ,	   0x1180000000C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	368},
+	{"MIO_UART0_FAR"               ,	   0x1180000000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART1_FAR"               ,	   0x1180000000D20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	369},
+	{"MIO_UART0_FCR"               ,	   0x1180000000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART1_FCR"               ,	   0x1180000000C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	370},
+	{"MIO_UART0_HTX"               ,	   0x1180000000B08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART1_HTX"               ,	   0x1180000000F08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	371},
+	{"MIO_UART0_IER"               ,	   0x1180000000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART1_IER"               ,	   0x1180000000C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	372},
+	{"MIO_UART0_IIR"               ,	   0x1180000000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART1_IIR"               ,	   0x1180000000C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	373},
+	{"MIO_UART0_LCR"               ,	   0x1180000000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART1_LCR"               ,	   0x1180000000C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	374},
+	{"MIO_UART0_LSR"               ,	   0x1180000000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART1_LSR"               ,	   0x1180000000C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	375},
+	{"MIO_UART0_MCR"               ,	   0x1180000000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART1_MCR"               ,	   0x1180000000C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	376},
+	{"MIO_UART0_MSR"               ,	   0x1180000000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART1_MSR"               ,	   0x1180000000C30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	377},
+	{"MIO_UART0_RBR"               ,	   0x1180000000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART1_RBR"               ,	   0x1180000000C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	378},
+	{"MIO_UART0_RFL"               ,	   0x1180000000A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART1_RFL"               ,	   0x1180000000E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	379},
+	{"MIO_UART0_RFW"               ,	   0x1180000000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART1_RFW"               ,	   0x1180000000D30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	380},
+	{"MIO_UART0_SBCR"              ,	   0x1180000000A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART1_SBCR"              ,	   0x1180000000E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	381},
+	{"MIO_UART0_SCR"               ,	   0x1180000000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART1_SCR"               ,	   0x1180000000C38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	382},
+	{"MIO_UART0_SFE"               ,	   0x1180000000A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART1_SFE"               ,	   0x1180000000E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	383},
+	{"MIO_UART0_SRR"               ,	   0x1180000000A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART1_SRR"               ,	   0x1180000000E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	384},
+	{"MIO_UART0_SRT"               ,	   0x1180000000A38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART1_SRT"               ,	   0x1180000000E38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	385},
+	{"MIO_UART0_SRTS"              ,	   0x1180000000A18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART1_SRTS"              ,	   0x1180000000E18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	386},
+	{"MIO_UART0_STT"               ,	   0x1180000000B00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART1_STT"               ,	   0x1180000000F00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	387},
+	{"MIO_UART0_TFL"               ,	   0x1180000000A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART1_TFL"               ,	   0x1180000000E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	388},
+	{"MIO_UART0_TFR"               ,	   0x1180000000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART1_TFR"               ,	   0x1180000000D28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	389},
+	{"MIO_UART0_THR"               ,	   0x1180000000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART1_THR"               ,	   0x1180000000C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	390},
+	{"MIO_UART0_USR"               ,	   0x1180000000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART1_USR"               ,	   0x1180000000D38ull,	CVMX_CSR_DB_TYPE_RSL,	64,	391},
+	{"MIO_UART2_DLH"               ,	   0x1180000000488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	392},
+	{"MIO_UART2_DLL"               ,	   0x1180000000480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	393},
+	{"MIO_UART2_FAR"               ,	   0x1180000000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	394},
+	{"MIO_UART2_FCR"               ,	   0x1180000000450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	395},
+	{"MIO_UART2_HTX"               ,	   0x1180000000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	396},
+	{"MIO_UART2_IER"               ,	   0x1180000000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	397},
+	{"MIO_UART2_IIR"               ,	   0x1180000000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	398},
+	{"MIO_UART2_LCR"               ,	   0x1180000000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	399},
+	{"MIO_UART2_LSR"               ,	   0x1180000000428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	400},
+	{"MIO_UART2_MCR"               ,	   0x1180000000420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	401},
+	{"MIO_UART2_MSR"               ,	   0x1180000000430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	402},
+	{"MIO_UART2_RBR"               ,	   0x1180000000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	403},
+	{"MIO_UART2_RFL"               ,	   0x1180000000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	404},
+	{"MIO_UART2_RFW"               ,	   0x1180000000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	405},
+	{"MIO_UART2_SBCR"              ,	   0x1180000000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	406},
+	{"MIO_UART2_SCR"               ,	   0x1180000000438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	407},
+	{"MIO_UART2_SFE"               ,	   0x1180000000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	408},
+	{"MIO_UART2_SRR"               ,	   0x1180000000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	409},
+	{"MIO_UART2_SRT"               ,	   0x1180000000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	410},
+	{"MIO_UART2_SRTS"              ,	   0x1180000000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	411},
+	{"MIO_UART2_STT"               ,	   0x1180000000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	412},
+	{"MIO_UART2_TFL"               ,	   0x1180000000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	413},
+	{"MIO_UART2_TFR"               ,	   0x1180000000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	414},
+	{"MIO_UART2_THR"               ,	   0x1180000000440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	415},
+	{"MIO_UART2_USR"               ,	   0x1180000000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	416},
+	{"MIX0_BIST"                   ,	   0x1070000100078ull,	CVMX_CSR_DB_TYPE_NCB,	64,	417},
+	{"MIX1_BIST"                   ,	   0x1070000100878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	417},
+	{"MIX0_CTL"                    ,	   0x1070000100020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	418},
+	{"MIX1_CTL"                    ,	   0x1070000100820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	418},
+	{"MIX0_INTENA"                 ,	   0x1070000100050ull,	CVMX_CSR_DB_TYPE_NCB,	64,	419},
+	{"MIX1_INTENA"                 ,	   0x1070000100850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	419},
+	{"MIX0_IRCNT"                  ,	   0x1070000100030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	420},
+	{"MIX1_IRCNT"                  ,	   0x1070000100830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	420},
+	{"MIX0_IRHWM"                  ,	   0x1070000100028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	421},
+	{"MIX1_IRHWM"                  ,	   0x1070000100828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	421},
+	{"MIX0_IRING1"                 ,	   0x1070000100010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	422},
+	{"MIX1_IRING1"                 ,	   0x1070000100810ull,	CVMX_CSR_DB_TYPE_NCB,	64,	422},
+	{"MIX0_IRING2"                 ,	   0x1070000100018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
+	{"MIX1_IRING2"                 ,	   0x1070000100818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	423},
+	{"MIX0_ISR"                    ,	   0x1070000100048ull,	CVMX_CSR_DB_TYPE_NCB,	64,	424},
+	{"MIX1_ISR"                    ,	   0x1070000100848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	424},
+	{"MIX0_ORCNT"                  ,	   0x1070000100040ull,	CVMX_CSR_DB_TYPE_NCB,	64,	425},
+	{"MIX1_ORCNT"                  ,	   0x1070000100840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	425},
+	{"MIX0_ORHWM"                  ,	   0x1070000100038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	426},
+	{"MIX1_ORHWM"                  ,	   0x1070000100838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	426},
+	{"MIX0_ORING1"                 ,	   0x1070000100000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	427},
+	{"MIX1_ORING1"                 ,	   0x1070000100800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	427},
+	{"MIX0_ORING2"                 ,	   0x1070000100008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	428},
+	{"MIX1_ORING2"                 ,	   0x1070000100808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	428},
+	{"MIX0_REMCNT"                 ,	   0x1070000100058ull,	CVMX_CSR_DB_TYPE_NCB,	64,	429},
+	{"MIX1_REMCNT"                 ,	   0x1070000100858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	429},
+	{"NDF_BT_PG_INFO"              ,	   0x1070001000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	430},
+	{"NDF_CMD"                     ,	   0x1070001000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	431},
+	{"NDF_DRBELL"                  ,	   0x1070001000030ull,	CVMX_CSR_DB_TYPE_NCB,	64,	432},
+	{"NDF_ECC_CNT"                 ,	   0x1070001000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	433},
+	{"NDF_INT"                     ,	   0x1070001000020ull,	CVMX_CSR_DB_TYPE_NCB,	64,	434},
+	{"NDF_INT_EN"                  ,	   0x1070001000028ull,	CVMX_CSR_DB_TYPE_NCB,	64,	435},
+	{"NDF_MISC"                    ,	   0x1070001000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	436},
+	{"NDF_ST_REG"                  ,	   0x1070001000038ull,	CVMX_CSR_DB_TYPE_NCB,	64,	437},
+	{"NPEI_BAR1_INDEX0"            ,	   0x11F0000008000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX1"            ,	   0x11F0000008010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX2"            ,	   0x11F0000008020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX3"            ,	   0x11F0000008030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX4"            ,	   0x11F0000008040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX5"            ,	   0x11F0000008050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX6"            ,	   0x11F0000008060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX7"            ,	   0x11F0000008070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX8"            ,	   0x11F0000008080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX9"            ,	   0x11F0000008090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX10"           ,	   0x11F00000080A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX11"           ,	   0x11F00000080B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX12"           ,	   0x11F00000080C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX13"           ,	   0x11F00000080D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX14"           ,	   0x11F00000080E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX15"           ,	   0x11F00000080F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX16"           ,	   0x11F0000008100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX17"           ,	   0x11F0000008110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX18"           ,	   0x11F0000008120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX19"           ,	   0x11F0000008130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX20"           ,	   0x11F0000008140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX21"           ,	   0x11F0000008150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX22"           ,	   0x11F0000008160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX23"           ,	   0x11F0000008170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX24"           ,	   0x11F0000008180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX25"           ,	   0x11F0000008190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX26"           ,	   0x11F00000081A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX27"           ,	   0x11F00000081B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX28"           ,	   0x11F00000081C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX29"           ,	   0x11F00000081D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX30"           ,	   0x11F00000081E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BAR1_INDEX31"           ,	   0x11F00000081F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	438},
+	{"NPEI_BIST_STATUS"            ,	   0x11F0000008580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	439},
+	{"NPEI_BIST_STATUS2"           ,	   0x11F0000008680ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	440},
+	{"NPEI_CTL_PORT0"              ,	   0x11F0000008250ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	441},
+	{"NPEI_CTL_PORT1"              ,	   0x11F0000008260ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	442},
+	{"NPEI_CTL_STATUS"             ,	   0x11F0000008570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	443},
+	{"NPEI_CTL_STATUS2"            ,	   0x11F000000BC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	444},
+	{"NPEI_DATA_OUT_CNT"           ,	   0x11F00000085F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	445},
+	{"NPEI_DBG_DATA"               ,	   0x11F0000008510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	446},
+	{"NPEI_DBG_SELECT"             ,	   0x11F0000008500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	447},
+	{"NPEI_DMA0_COUNTS"            ,	   0x11F0000008450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA1_COUNTS"            ,	   0x11F0000008460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA2_COUNTS"            ,	   0x11F0000008470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA3_COUNTS"            ,	   0x11F0000008480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA4_COUNTS"            ,	   0x11F0000008490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	448},
+	{"NPEI_DMA0_DBELL"             ,	   0x11F00000083B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA1_DBELL"             ,	   0x11F00000083C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA2_DBELL"             ,	   0x11F00000083D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA3_DBELL"             ,	   0x11F00000083E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA4_DBELL"             ,	   0x11F00000083F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	32,	449},
+	{"NPEI_DMA0_IBUFF_SADDR"       ,	   0x11F0000008400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA1_IBUFF_SADDR"       ,	   0x11F0000008410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA2_IBUFF_SADDR"       ,	   0x11F0000008420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA3_IBUFF_SADDR"       ,	   0x11F0000008430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA4_IBUFF_SADDR"       ,	   0x11F0000008440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	450},
+	{"NPEI_DMA0_NADDR"             ,	   0x11F00000084A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA1_NADDR"             ,	   0x11F00000084B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA2_NADDR"             ,	   0x11F00000084C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA3_NADDR"             ,	   0x11F00000084D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA4_NADDR"             ,	   0x11F00000084E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	451},
+	{"NPEI_DMA0_INT_LEVEL"         ,	   0x11F00000085C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	452},
+	{"NPEI_DMA1_INT_LEVEL"         ,	   0x11F00000085D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	453},
+	{"NPEI_DMA_CNTS"               ,	   0x11F00000085E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	454},
+	{"NPEI_DMA_CONTROL"            ,	   0x11F00000083A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	455},
+	{"NPEI_DMA_PCIE_REQ_NUM"       ,	   0x11F00000085B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	456},
+	{"NPEI_DMA_STATE1"             ,	   0x11F00000086C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	457},
+	{"NPEI_DMA_STATE2"             ,	   0x11F00000086D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	458},
+	{"NPEI_INT_A_ENB"              ,	   0x11F0000008560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	459},
+	{"NPEI_INT_A_ENB2"             ,	   0x11F000000BCE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	460},
+	{"NPEI_INT_A_SUM"              ,	   0x11F0000008550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	461},
+	{"NPEI_INT_ENB"                ,	   0x11F0000008540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	462},
+	{"NPEI_INT_ENB2"               ,	   0x11F000000BCD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	463},
+	{"NPEI_INT_INFO"               ,	   0x11F0000008590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	464},
+	{"NPEI_INT_SUM"                ,	   0x11F0000008530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	465},
+	{"NPEI_INT_SUM2"               ,	   0x11F000000BCC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	466},
+	{"NPEI_LAST_WIN_RDATA0"        ,	   0x11F0000008600ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	467},
+	{"NPEI_LAST_WIN_RDATA1"        ,	   0x11F0000008610ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	468},
+	{"NPEI_MEM_ACCESS_CTL"         ,	   0x11F00000084F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	469},
+	{"NPEI_MEM_ACCESS_SUBID12"     ,	   0x11F0000008280ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID13"     ,	   0x11F0000008290ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID14"     ,	   0x11F00000082A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID15"     ,	   0x11F00000082B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID16"     ,	   0x11F00000082C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID17"     ,	   0x11F00000082D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID18"     ,	   0x11F00000082E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID19"     ,	   0x11F00000082F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID20"     ,	   0x11F0000008300ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID21"     ,	   0x11F0000008310ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID22"     ,	   0x11F0000008320ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID23"     ,	   0x11F0000008330ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID24"     ,	   0x11F0000008340ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID25"     ,	   0x11F0000008350ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID26"     ,	   0x11F0000008360ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MEM_ACCESS_SUBID27"     ,	   0x11F0000008370ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	470},
+	{"NPEI_MSI_ENB0"               ,	   0x11F000000BC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	471},
+	{"NPEI_MSI_ENB1"               ,	   0x11F000000BC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	472},
+	{"NPEI_MSI_ENB2"               ,	   0x11F000000BC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	473},
+	{"NPEI_MSI_ENB3"               ,	   0x11F000000BC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	474},
+	{"NPEI_MSI_RCV0"               ,	   0x11F000000BC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	475},
+	{"NPEI_MSI_RCV1"               ,	   0x11F000000BC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	476},
+	{"NPEI_MSI_RCV2"               ,	   0x11F000000BC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	477},
+	{"NPEI_MSI_RCV3"               ,	   0x11F000000BC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	478},
+	{"NPEI_MSI_RD_MAP"             ,	   0x11F000000BCA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	479},
+	{"NPEI_MSI_W1C_ENB0"           ,	   0x11F000000BCF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	480},
+	{"NPEI_MSI_W1C_ENB1"           ,	   0x11F000000BD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	481},
+	{"NPEI_MSI_W1C_ENB2"           ,	   0x11F000000BD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	482},
+	{"NPEI_MSI_W1C_ENB3"           ,	   0x11F000000BD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	483},
+	{"NPEI_MSI_W1S_ENB0"           ,	   0x11F000000BD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	484},
+	{"NPEI_MSI_W1S_ENB1"           ,	   0x11F000000BD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	485},
+	{"NPEI_MSI_W1S_ENB2"           ,	   0x11F000000BD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	486},
+	{"NPEI_MSI_W1S_ENB3"           ,	   0x11F000000BD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	487},
+	{"NPEI_MSI_WR_MAP"             ,	   0x11F000000BC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	488},
+	{"NPEI_PCIE_CREDIT_CNT"        ,	   0x11F000000BD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	489},
+	{"NPEI_PCIE_MSI_RCV"           ,	   0x11F000000BCB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	490},
+	{"NPEI_PCIE_MSI_RCV_B1"        ,	   0x11F0000008650ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	491},
+	{"NPEI_PCIE_MSI_RCV_B2"        ,	   0x11F0000008660ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	492},
+	{"NPEI_PCIE_MSI_RCV_B3"        ,	   0x11F0000008670ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	493},
+	{"NPEI_PKT0_CNTS"              ,	   0x11F000000A400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT1_CNTS"              ,	   0x11F000000A410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT2_CNTS"              ,	   0x11F000000A420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT3_CNTS"              ,	   0x11F000000A430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT4_CNTS"              ,	   0x11F000000A440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT5_CNTS"              ,	   0x11F000000A450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT6_CNTS"              ,	   0x11F000000A460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT7_CNTS"              ,	   0x11F000000A470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT8_CNTS"              ,	   0x11F000000A480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT9_CNTS"              ,	   0x11F000000A490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT10_CNTS"             ,	   0x11F000000A4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT11_CNTS"             ,	   0x11F000000A4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT12_CNTS"             ,	   0x11F000000A4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT13_CNTS"             ,	   0x11F000000A4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT14_CNTS"             ,	   0x11F000000A4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT15_CNTS"             ,	   0x11F000000A4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT16_CNTS"             ,	   0x11F000000A500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT17_CNTS"             ,	   0x11F000000A510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT18_CNTS"             ,	   0x11F000000A520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT19_CNTS"             ,	   0x11F000000A530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT20_CNTS"             ,	   0x11F000000A540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT21_CNTS"             ,	   0x11F000000A550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT22_CNTS"             ,	   0x11F000000A560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT23_CNTS"             ,	   0x11F000000A570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT24_CNTS"             ,	   0x11F000000A580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT25_CNTS"             ,	   0x11F000000A590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT26_CNTS"             ,	   0x11F000000A5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT27_CNTS"             ,	   0x11F000000A5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT28_CNTS"             ,	   0x11F000000A5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT29_CNTS"             ,	   0x11F000000A5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT30_CNTS"             ,	   0x11F000000A5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT31_CNTS"             ,	   0x11F000000A5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	494},
+	{"NPEI_PKT0_IN_BP"             ,	   0x11F000000B800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT1_IN_BP"             ,	   0x11F000000B810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT2_IN_BP"             ,	   0x11F000000B820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT3_IN_BP"             ,	   0x11F000000B830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT4_IN_BP"             ,	   0x11F000000B840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT5_IN_BP"             ,	   0x11F000000B850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT6_IN_BP"             ,	   0x11F000000B860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT7_IN_BP"             ,	   0x11F000000B870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT8_IN_BP"             ,	   0x11F000000B880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT9_IN_BP"             ,	   0x11F000000B890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT10_IN_BP"            ,	   0x11F000000B8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT11_IN_BP"            ,	   0x11F000000B8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT12_IN_BP"            ,	   0x11F000000B8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT13_IN_BP"            ,	   0x11F000000B8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT14_IN_BP"            ,	   0x11F000000B8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT15_IN_BP"            ,	   0x11F000000B8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT16_IN_BP"            ,	   0x11F000000B900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT17_IN_BP"            ,	   0x11F000000B910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT18_IN_BP"            ,	   0x11F000000B920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT19_IN_BP"            ,	   0x11F000000B930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT20_IN_BP"            ,	   0x11F000000B940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT21_IN_BP"            ,	   0x11F000000B950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT22_IN_BP"            ,	   0x11F000000B960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT23_IN_BP"            ,	   0x11F000000B970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT24_IN_BP"            ,	   0x11F000000B980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT25_IN_BP"            ,	   0x11F000000B990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT26_IN_BP"            ,	   0x11F000000B9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT27_IN_BP"            ,	   0x11F000000B9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT28_IN_BP"            ,	   0x11F000000B9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT29_IN_BP"            ,	   0x11F000000B9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT30_IN_BP"            ,	   0x11F000000B9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT31_IN_BP"            ,	   0x11F000000B9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	495},
+	{"NPEI_PKT0_INSTR_BADDR"       ,	   0x11F000000A800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT1_INSTR_BADDR"       ,	   0x11F000000A810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT2_INSTR_BADDR"       ,	   0x11F000000A820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT3_INSTR_BADDR"       ,	   0x11F000000A830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT4_INSTR_BADDR"       ,	   0x11F000000A840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT5_INSTR_BADDR"       ,	   0x11F000000A850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT6_INSTR_BADDR"       ,	   0x11F000000A860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT7_INSTR_BADDR"       ,	   0x11F000000A870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT8_INSTR_BADDR"       ,	   0x11F000000A880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT9_INSTR_BADDR"       ,	   0x11F000000A890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT10_INSTR_BADDR"      ,	   0x11F000000A8A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT11_INSTR_BADDR"      ,	   0x11F000000A8B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT12_INSTR_BADDR"      ,	   0x11F000000A8C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT13_INSTR_BADDR"      ,	   0x11F000000A8D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT14_INSTR_BADDR"      ,	   0x11F000000A8E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT15_INSTR_BADDR"      ,	   0x11F000000A8F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT16_INSTR_BADDR"      ,	   0x11F000000A900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT17_INSTR_BADDR"      ,	   0x11F000000A910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT18_INSTR_BADDR"      ,	   0x11F000000A920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT19_INSTR_BADDR"      ,	   0x11F000000A930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT20_INSTR_BADDR"      ,	   0x11F000000A940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT21_INSTR_BADDR"      ,	   0x11F000000A950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT22_INSTR_BADDR"      ,	   0x11F000000A960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT23_INSTR_BADDR"      ,	   0x11F000000A970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT24_INSTR_BADDR"      ,	   0x11F000000A980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT25_INSTR_BADDR"      ,	   0x11F000000A990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT26_INSTR_BADDR"      ,	   0x11F000000A9A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT27_INSTR_BADDR"      ,	   0x11F000000A9B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT28_INSTR_BADDR"      ,	   0x11F000000A9C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT29_INSTR_BADDR"      ,	   0x11F000000A9D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT30_INSTR_BADDR"      ,	   0x11F000000A9E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT31_INSTR_BADDR"      ,	   0x11F000000A9F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	496},
+	{"NPEI_PKT0_INSTR_BAOFF_DBELL" ,	   0x11F000000AC00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT1_INSTR_BAOFF_DBELL" ,	   0x11F000000AC10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT2_INSTR_BAOFF_DBELL" ,	   0x11F000000AC20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT3_INSTR_BAOFF_DBELL" ,	   0x11F000000AC30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT4_INSTR_BAOFF_DBELL" ,	   0x11F000000AC40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT5_INSTR_BAOFF_DBELL" ,	   0x11F000000AC50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT6_INSTR_BAOFF_DBELL" ,	   0x11F000000AC60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT7_INSTR_BAOFF_DBELL" ,	   0x11F000000AC70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT8_INSTR_BAOFF_DBELL" ,	   0x11F000000AC80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT9_INSTR_BAOFF_DBELL" ,	   0x11F000000AC90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT10_INSTR_BAOFF_DBELL",	   0x11F000000ACA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT11_INSTR_BAOFF_DBELL",	   0x11F000000ACB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT12_INSTR_BAOFF_DBELL",	   0x11F000000ACC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT13_INSTR_BAOFF_DBELL",	   0x11F000000ACD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT14_INSTR_BAOFF_DBELL",	   0x11F000000ACE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT15_INSTR_BAOFF_DBELL",	   0x11F000000ACF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT16_INSTR_BAOFF_DBELL",	   0x11F000000AD00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT17_INSTR_BAOFF_DBELL",	   0x11F000000AD10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT18_INSTR_BAOFF_DBELL",	   0x11F000000AD20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT19_INSTR_BAOFF_DBELL",	   0x11F000000AD30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT20_INSTR_BAOFF_DBELL",	   0x11F000000AD40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT21_INSTR_BAOFF_DBELL",	   0x11F000000AD50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT22_INSTR_BAOFF_DBELL",	   0x11F000000AD60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT23_INSTR_BAOFF_DBELL",	   0x11F000000AD70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT24_INSTR_BAOFF_DBELL",	   0x11F000000AD80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT25_INSTR_BAOFF_DBELL",	   0x11F000000AD90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT26_INSTR_BAOFF_DBELL",	   0x11F000000ADA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT27_INSTR_BAOFF_DBELL",	   0x11F000000ADB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT28_INSTR_BAOFF_DBELL",	   0x11F000000ADC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT29_INSTR_BAOFF_DBELL",	   0x11F000000ADD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT30_INSTR_BAOFF_DBELL",	   0x11F000000ADE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT31_INSTR_BAOFF_DBELL",	   0x11F000000ADF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	497},
+	{"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,	   0x11F000000B000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,	   0x11F000000B010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,	   0x11F000000B020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,	   0x11F000000B030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,	   0x11F000000B040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,	   0x11F000000B050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,	   0x11F000000B060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,	   0x11F000000B070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,	   0x11F000000B080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,	   0x11F000000B090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT10_INSTR_FIFO_RSIZE" ,	   0x11F000000B0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT11_INSTR_FIFO_RSIZE" ,	   0x11F000000B0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT12_INSTR_FIFO_RSIZE" ,	   0x11F000000B0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT13_INSTR_FIFO_RSIZE" ,	   0x11F000000B0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT14_INSTR_FIFO_RSIZE" ,	   0x11F000000B0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT15_INSTR_FIFO_RSIZE" ,	   0x11F000000B0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT16_INSTR_FIFO_RSIZE" ,	   0x11F000000B100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT17_INSTR_FIFO_RSIZE" ,	   0x11F000000B110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT18_INSTR_FIFO_RSIZE" ,	   0x11F000000B120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT19_INSTR_FIFO_RSIZE" ,	   0x11F000000B130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT20_INSTR_FIFO_RSIZE" ,	   0x11F000000B140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT21_INSTR_FIFO_RSIZE" ,	   0x11F000000B150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT22_INSTR_FIFO_RSIZE" ,	   0x11F000000B160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT23_INSTR_FIFO_RSIZE" ,	   0x11F000000B170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT24_INSTR_FIFO_RSIZE" ,	   0x11F000000B180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT25_INSTR_FIFO_RSIZE" ,	   0x11F000000B190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT26_INSTR_FIFO_RSIZE" ,	   0x11F000000B1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT27_INSTR_FIFO_RSIZE" ,	   0x11F000000B1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT28_INSTR_FIFO_RSIZE" ,	   0x11F000000B1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT29_INSTR_FIFO_RSIZE" ,	   0x11F000000B1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT30_INSTR_FIFO_RSIZE" ,	   0x11F000000B1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT31_INSTR_FIFO_RSIZE" ,	   0x11F000000B1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	498},
+	{"NPEI_PKT0_INSTR_HEADER"      ,	   0x11F000000B400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT1_INSTR_HEADER"      ,	   0x11F000000B410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT2_INSTR_HEADER"      ,	   0x11F000000B420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT3_INSTR_HEADER"      ,	   0x11F000000B430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT4_INSTR_HEADER"      ,	   0x11F000000B440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT5_INSTR_HEADER"      ,	   0x11F000000B450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT6_INSTR_HEADER"      ,	   0x11F000000B460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT7_INSTR_HEADER"      ,	   0x11F000000B470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT8_INSTR_HEADER"      ,	   0x11F000000B480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT9_INSTR_HEADER"      ,	   0x11F000000B490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT10_INSTR_HEADER"     ,	   0x11F000000B4A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT11_INSTR_HEADER"     ,	   0x11F000000B4B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT12_INSTR_HEADER"     ,	   0x11F000000B4C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT13_INSTR_HEADER"     ,	   0x11F000000B4D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT14_INSTR_HEADER"     ,	   0x11F000000B4E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT15_INSTR_HEADER"     ,	   0x11F000000B4F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT16_INSTR_HEADER"     ,	   0x11F000000B500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT17_INSTR_HEADER"     ,	   0x11F000000B510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT18_INSTR_HEADER"     ,	   0x11F000000B520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT19_INSTR_HEADER"     ,	   0x11F000000B530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT20_INSTR_HEADER"     ,	   0x11F000000B540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT21_INSTR_HEADER"     ,	   0x11F000000B550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT22_INSTR_HEADER"     ,	   0x11F000000B560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT23_INSTR_HEADER"     ,	   0x11F000000B570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT24_INSTR_HEADER"     ,	   0x11F000000B580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT25_INSTR_HEADER"     ,	   0x11F000000B590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT26_INSTR_HEADER"     ,	   0x11F000000B5A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT27_INSTR_HEADER"     ,	   0x11F000000B5B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT28_INSTR_HEADER"     ,	   0x11F000000B5C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT29_INSTR_HEADER"     ,	   0x11F000000B5D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT30_INSTR_HEADER"     ,	   0x11F000000B5E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT31_INSTR_HEADER"     ,	   0x11F000000B5F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	499},
+	{"NPEI_PKT0_SLIST_BADDR"       ,	   0x11F0000009400ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT1_SLIST_BADDR"       ,	   0x11F0000009410ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT2_SLIST_BADDR"       ,	   0x11F0000009420ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT3_SLIST_BADDR"       ,	   0x11F0000009430ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT4_SLIST_BADDR"       ,	   0x11F0000009440ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT5_SLIST_BADDR"       ,	   0x11F0000009450ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT6_SLIST_BADDR"       ,	   0x11F0000009460ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT7_SLIST_BADDR"       ,	   0x11F0000009470ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT8_SLIST_BADDR"       ,	   0x11F0000009480ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT9_SLIST_BADDR"       ,	   0x11F0000009490ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT10_SLIST_BADDR"      ,	   0x11F00000094A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT11_SLIST_BADDR"      ,	   0x11F00000094B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT12_SLIST_BADDR"      ,	   0x11F00000094C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT13_SLIST_BADDR"      ,	   0x11F00000094D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT14_SLIST_BADDR"      ,	   0x11F00000094E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT15_SLIST_BADDR"      ,	   0x11F00000094F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT16_SLIST_BADDR"      ,	   0x11F0000009500ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT17_SLIST_BADDR"      ,	   0x11F0000009510ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT18_SLIST_BADDR"      ,	   0x11F0000009520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT19_SLIST_BADDR"      ,	   0x11F0000009530ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT20_SLIST_BADDR"      ,	   0x11F0000009540ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT21_SLIST_BADDR"      ,	   0x11F0000009550ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT22_SLIST_BADDR"      ,	   0x11F0000009560ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT23_SLIST_BADDR"      ,	   0x11F0000009570ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT24_SLIST_BADDR"      ,	   0x11F0000009580ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT25_SLIST_BADDR"      ,	   0x11F0000009590ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT26_SLIST_BADDR"      ,	   0x11F00000095A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT27_SLIST_BADDR"      ,	   0x11F00000095B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT28_SLIST_BADDR"      ,	   0x11F00000095C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT29_SLIST_BADDR"      ,	   0x11F00000095D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT30_SLIST_BADDR"      ,	   0x11F00000095E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT31_SLIST_BADDR"      ,	   0x11F00000095F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	500},
+	{"NPEI_PKT0_SLIST_BAOFF_DBELL" ,	   0x11F0000009800ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT1_SLIST_BAOFF_DBELL" ,	   0x11F0000009810ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT2_SLIST_BAOFF_DBELL" ,	   0x11F0000009820ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT3_SLIST_BAOFF_DBELL" ,	   0x11F0000009830ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT4_SLIST_BAOFF_DBELL" ,	   0x11F0000009840ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT5_SLIST_BAOFF_DBELL" ,	   0x11F0000009850ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT6_SLIST_BAOFF_DBELL" ,	   0x11F0000009860ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT7_SLIST_BAOFF_DBELL" ,	   0x11F0000009870ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT8_SLIST_BAOFF_DBELL" ,	   0x11F0000009880ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT9_SLIST_BAOFF_DBELL" ,	   0x11F0000009890ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT10_SLIST_BAOFF_DBELL",	   0x11F00000098A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT11_SLIST_BAOFF_DBELL",	   0x11F00000098B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT12_SLIST_BAOFF_DBELL",	   0x11F00000098C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT13_SLIST_BAOFF_DBELL",	   0x11F00000098D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT14_SLIST_BAOFF_DBELL",	   0x11F00000098E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT15_SLIST_BAOFF_DBELL",	   0x11F00000098F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT16_SLIST_BAOFF_DBELL",	   0x11F0000009900ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT17_SLIST_BAOFF_DBELL",	   0x11F0000009910ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT18_SLIST_BAOFF_DBELL",	   0x11F0000009920ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT19_SLIST_BAOFF_DBELL",	   0x11F0000009930ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT20_SLIST_BAOFF_DBELL",	   0x11F0000009940ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT21_SLIST_BAOFF_DBELL",	   0x11F0000009950ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT22_SLIST_BAOFF_DBELL",	   0x11F0000009960ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT23_SLIST_BAOFF_DBELL",	   0x11F0000009970ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT24_SLIST_BAOFF_DBELL",	   0x11F0000009980ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT25_SLIST_BAOFF_DBELL",	   0x11F0000009990ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT26_SLIST_BAOFF_DBELL",	   0x11F00000099A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT27_SLIST_BAOFF_DBELL",	   0x11F00000099B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT28_SLIST_BAOFF_DBELL",	   0x11F00000099C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT29_SLIST_BAOFF_DBELL",	   0x11F00000099D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT30_SLIST_BAOFF_DBELL",	   0x11F00000099E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT31_SLIST_BAOFF_DBELL",	   0x11F00000099F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	501},
+	{"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,	   0x11F0000009C90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT10_SLIST_FIFO_RSIZE" ,	   0x11F0000009CA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT11_SLIST_FIFO_RSIZE" ,	   0x11F0000009CB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT12_SLIST_FIFO_RSIZE" ,	   0x11F0000009CC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT13_SLIST_FIFO_RSIZE" ,	   0x11F0000009CD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT14_SLIST_FIFO_RSIZE" ,	   0x11F0000009CE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT15_SLIST_FIFO_RSIZE" ,	   0x11F0000009CF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT16_SLIST_FIFO_RSIZE" ,	   0x11F0000009D00ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT17_SLIST_FIFO_RSIZE" ,	   0x11F0000009D10ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT18_SLIST_FIFO_RSIZE" ,	   0x11F0000009D20ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT19_SLIST_FIFO_RSIZE" ,	   0x11F0000009D30ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT20_SLIST_FIFO_RSIZE" ,	   0x11F0000009D40ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT21_SLIST_FIFO_RSIZE" ,	   0x11F0000009D50ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT22_SLIST_FIFO_RSIZE" ,	   0x11F0000009D60ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT23_SLIST_FIFO_RSIZE" ,	   0x11F0000009D70ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT24_SLIST_FIFO_RSIZE" ,	   0x11F0000009D80ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT25_SLIST_FIFO_RSIZE" ,	   0x11F0000009D90ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT26_SLIST_FIFO_RSIZE" ,	   0x11F0000009DA0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT27_SLIST_FIFO_RSIZE" ,	   0x11F0000009DB0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT28_SLIST_FIFO_RSIZE" ,	   0x11F0000009DC0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT29_SLIST_FIFO_RSIZE" ,	   0x11F0000009DD0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT30_SLIST_FIFO_RSIZE" ,	   0x11F0000009DE0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT31_SLIST_FIFO_RSIZE" ,	   0x11F0000009DF0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	502},
+	{"NPEI_PKT_CNT_INT"            ,	   0x11F0000009110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	503},
+	{"NPEI_PKT_CNT_INT_ENB"        ,	   0x11F0000009130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	504},
+	{"NPEI_PKT_DATA_OUT_ES"        ,	   0x11F00000090B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	505},
+	{"NPEI_PKT_DATA_OUT_NS"        ,	   0x11F00000090A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	506},
+	{"NPEI_PKT_DATA_OUT_ROR"       ,	   0x11F0000009090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	507},
+	{"NPEI_PKT_DPADDR"             ,	   0x11F0000009080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	508},
+	{"NPEI_PKT_IN_BP"              ,	   0x11F00000086B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	509},
+	{"NPEI_PKT_IN_DONE0_CNTS"      ,	   0x11F000000A000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE1_CNTS"      ,	   0x11F000000A010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE2_CNTS"      ,	   0x11F000000A020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE3_CNTS"      ,	   0x11F000000A030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE4_CNTS"      ,	   0x11F000000A040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE5_CNTS"      ,	   0x11F000000A050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE6_CNTS"      ,	   0x11F000000A060ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE7_CNTS"      ,	   0x11F000000A070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE8_CNTS"      ,	   0x11F000000A080ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE9_CNTS"      ,	   0x11F000000A090ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE10_CNTS"     ,	   0x11F000000A0A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE11_CNTS"     ,	   0x11F000000A0B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE12_CNTS"     ,	   0x11F000000A0C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE13_CNTS"     ,	   0x11F000000A0D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE14_CNTS"     ,	   0x11F000000A0E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE15_CNTS"     ,	   0x11F000000A0F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE16_CNTS"     ,	   0x11F000000A100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE17_CNTS"     ,	   0x11F000000A110ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE18_CNTS"     ,	   0x11F000000A120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE19_CNTS"     ,	   0x11F000000A130ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE20_CNTS"     ,	   0x11F000000A140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE21_CNTS"     ,	   0x11F000000A150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE22_CNTS"     ,	   0x11F000000A160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE23_CNTS"     ,	   0x11F000000A170ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE24_CNTS"     ,	   0x11F000000A180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE25_CNTS"     ,	   0x11F000000A190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE26_CNTS"     ,	   0x11F000000A1A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE27_CNTS"     ,	   0x11F000000A1B0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE28_CNTS"     ,	   0x11F000000A1C0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE29_CNTS"     ,	   0x11F000000A1D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE30_CNTS"     ,	   0x11F000000A1E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_DONE31_CNTS"     ,	   0x11F000000A1F0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	510},
+	{"NPEI_PKT_IN_INSTR_COUNTS"    ,	   0x11F00000086A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	511},
+	{"NPEI_PKT_IN_PCIE_PORT"       ,	   0x11F00000091A0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	512},
+	{"NPEI_PKT_INPUT_CONTROL"      ,	   0x11F0000009150ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	513},
+	{"NPEI_PKT_INSTR_ENB"          ,	   0x11F0000009000ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	514},
+	{"NPEI_PKT_INSTR_RD_SIZE"      ,	   0x11F0000009190ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	515},
+	{"NPEI_PKT_INSTR_SIZE"         ,	   0x11F0000009020ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	516},
+	{"NPEI_PKT_INT_LEVELS"         ,	   0x11F0000009100ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	517},
+	{"NPEI_PKT_IPTR"               ,	   0x11F0000009070ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	518},
+	{"NPEI_PKT_OUT_BMODE"          ,	   0x11F00000090D0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	519},
+	{"NPEI_PKT_OUT_ENB"            ,	   0x11F0000009010ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	520},
+	{"NPEI_PKT_OUTPUT_WMARK"       ,	   0x11F0000009160ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	521},
+	{"NPEI_PKT_PCIE_PORT"          ,	   0x11F00000090E0ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	522},
+	{"NPEI_PKT_PORT_IN_RST"        ,	   0x11F0000008690ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	523},
+	{"NPEI_PKT_SLIST_ES"           ,	   0x11F0000009050ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	524},
+	{"NPEI_PKT_SLIST_ID_SIZE"      ,	   0x11F0000009180ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	525},
+	{"NPEI_PKT_SLIST_NS"           ,	   0x11F0000009040ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	526},
+	{"NPEI_PKT_SLIST_ROR"          ,	   0x11F0000009030ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	527},
+	{"NPEI_PKT_TIME_INT"           ,	   0x11F0000009120ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	528},
+	{"NPEI_PKT_TIME_INT_ENB"       ,	   0x11F0000009140ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	529},
+	{"NPEI_RSL_INT_BLOCKS"         ,	   0x11F0000008520ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	530},
+	{"NPEI_SCRATCH_1"              ,	   0x11F0000008270ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	531},
+	{"NPEI_STATE1"                 ,	   0x11F0000008620ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	532},
+	{"NPEI_STATE2"                 ,	   0x11F0000008630ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	533},
+	{"NPEI_STATE3"                 ,	   0x11F0000008640ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	534},
+	{"NPEI_WIN_RD_ADDR"            ,	             0x210ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	535},
+	{"NPEI_WIN_RD_DATA"            ,	             0x240ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	536},
+	{"NPEI_WIN_WR_ADDR"            ,	             0x200ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	537},
+	{"NPEI_WIN_WR_DATA"            ,	             0x220ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	538},
+	{"NPEI_WIN_WR_MASK"            ,	             0x230ull,	CVMX_CSR_DB_TYPE_PEXP,	64,	539},
+	{"NPEI_WINDOW_CTL"             ,	   0x11F0000008380ull,	CVMX_CSR_DB_TYPE_PEXP_NCB,	64,	540},
+	{"PCIEEP_CFG000"               ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	541},
+	{"PCIEEP_CFG001"               ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	542},
+	{"PCIEEP_CFG002"               ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	543},
+	{"PCIEEP_CFG003"               ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	544},
+	{"PCIEEP_CFG004"               ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	545},
+	{"PCIEEP_CFG004_MASK"          ,	        0x80000010ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	546},
+	{"PCIEEP_CFG005"               ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	547},
+	{"PCIEEP_CFG005_MASK"          ,	        0x80000014ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	548},
+	{"PCIEEP_CFG006"               ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	549},
+	{"PCIEEP_CFG006_MASK"          ,	        0x80000018ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	550},
+	{"PCIEEP_CFG007"               ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	551},
+	{"PCIEEP_CFG007_MASK"          ,	        0x8000001Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	552},
+	{"PCIEEP_CFG008"               ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	553},
+	{"PCIEEP_CFG008_MASK"          ,	        0x80000020ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	554},
+	{"PCIEEP_CFG009"               ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	555},
+	{"PCIEEP_CFG009_MASK"          ,	        0x80000024ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	556},
+	{"PCIEEP_CFG010"               ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	557},
+	{"PCIEEP_CFG011"               ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	558},
+	{"PCIEEP_CFG012"               ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	559},
+	{"PCIEEP_CFG012_MASK"          ,	        0x80000030ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	560},
+	{"PCIEEP_CFG013"               ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	561},
+	{"PCIEEP_CFG015"               ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	562},
+	{"PCIEEP_CFG016"               ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	563},
+	{"PCIEEP_CFG017"               ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	564},
+	{"PCIEEP_CFG020"               ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	565},
+	{"PCIEEP_CFG021"               ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	566},
+	{"PCIEEP_CFG022"               ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	567},
+	{"PCIEEP_CFG023"               ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	568},
+	{"PCIEEP_CFG028"               ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	569},
+	{"PCIEEP_CFG029"               ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	570},
+	{"PCIEEP_CFG030"               ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	571},
+	{"PCIEEP_CFG031"               ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	572},
+	{"PCIEEP_CFG032"               ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	573},
+	{"PCIEEP_CFG033"               ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	574},
+	{"PCIEEP_CFG034"               ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	575},
+	{"PCIEEP_CFG037"               ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	576},
+	{"PCIEEP_CFG038"               ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	577},
+	{"PCIEEP_CFG039"               ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	578},
+	{"PCIEEP_CFG040"               ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	579},
+	{"PCIEEP_CFG041"               ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	580},
+	{"PCIEEP_CFG042"               ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	581},
+	{"PCIEEP_CFG064"               ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	582},
+	{"PCIEEP_CFG065"               ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	583},
+	{"PCIEEP_CFG066"               ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	584},
+	{"PCIEEP_CFG067"               ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	585},
+	{"PCIEEP_CFG068"               ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	586},
+	{"PCIEEP_CFG069"               ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	587},
+	{"PCIEEP_CFG070"               ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	588},
+	{"PCIEEP_CFG071"               ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	589},
+	{"PCIEEP_CFG072"               ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	590},
+	{"PCIEEP_CFG073"               ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	591},
+	{"PCIEEP_CFG074"               ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	592},
+	{"PCIEEP_CFG448"               ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	593},
+	{"PCIEEP_CFG449"               ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	594},
+	{"PCIEEP_CFG450"               ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	595},
+	{"PCIEEP_CFG451"               ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	596},
+	{"PCIEEP_CFG452"               ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	597},
+	{"PCIEEP_CFG453"               ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	598},
+	{"PCIEEP_CFG454"               ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	599},
+	{"PCIEEP_CFG455"               ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	600},
+	{"PCIEEP_CFG456"               ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	601},
+	{"PCIEEP_CFG458"               ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	602},
+	{"PCIEEP_CFG459"               ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	603},
+	{"PCIEEP_CFG460"               ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	604},
+	{"PCIEEP_CFG461"               ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	605},
+	{"PCIEEP_CFG462"               ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	606},
+	{"PCIEEP_CFG463"               ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	607},
+	{"PCIEEP_CFG464"               ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	608},
+	{"PCIEEP_CFG465"               ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	609},
+	{"PCIEEP_CFG466"               ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	610},
+	{"PCIEEP_CFG467"               ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	611},
+	{"PCIEEP_CFG468"               ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	612},
+	{"PCIEEP_CFG490"               ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	613},
+	{"PCIEEP_CFG491"               ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	614},
+	{"PCIEEP_CFG492"               ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	615},
+	{"PCIEEP_CFG516"               ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	616},
+	{"PCIEEP_CFG517"               ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGEP,	32,	617},
+	{"PCIERC0_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC1_CFG000"              ,	               0x0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	618},
+	{"PCIERC0_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC1_CFG001"              ,	               0x4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	619},
+	{"PCIERC0_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC1_CFG002"              ,	               0x8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	620},
+	{"PCIERC0_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC1_CFG003"              ,	               0xCull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	621},
+	{"PCIERC0_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC1_CFG004"              ,	              0x10ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	622},
+	{"PCIERC0_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
+	{"PCIERC1_CFG005"              ,	              0x14ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	623},
+	{"PCIERC0_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC1_CFG006"              ,	              0x18ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	624},
+	{"PCIERC0_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC1_CFG007"              ,	              0x1Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	625},
+	{"PCIERC0_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
+	{"PCIERC1_CFG008"              ,	              0x20ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	626},
+	{"PCIERC0_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
+	{"PCIERC1_CFG009"              ,	              0x24ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	627},
+	{"PCIERC0_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC1_CFG010"              ,	              0x28ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	628},
+	{"PCIERC0_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC1_CFG011"              ,	              0x2Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	629},
+	{"PCIERC0_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC1_CFG012"              ,	              0x30ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	630},
+	{"PCIERC0_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC1_CFG013"              ,	              0x34ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	631},
+	{"PCIERC0_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC1_CFG014"              ,	              0x38ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	632},
+	{"PCIERC0_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC1_CFG015"              ,	              0x3Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	633},
+	{"PCIERC0_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC1_CFG016"              ,	              0x40ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	634},
+	{"PCIERC0_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC1_CFG017"              ,	              0x44ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	635},
+	{"PCIERC0_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC1_CFG020"              ,	              0x50ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	636},
+	{"PCIERC0_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC1_CFG021"              ,	              0x54ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	637},
+	{"PCIERC0_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC1_CFG022"              ,	              0x58ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	638},
+	{"PCIERC0_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC1_CFG023"              ,	              0x5Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	639},
+	{"PCIERC0_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC1_CFG028"              ,	              0x70ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	640},
+	{"PCIERC0_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC1_CFG029"              ,	              0x74ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	641},
+	{"PCIERC0_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC1_CFG030"              ,	              0x78ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	642},
+	{"PCIERC0_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC1_CFG031"              ,	              0x7Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	643},
+	{"PCIERC0_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC1_CFG032"              ,	              0x80ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	644},
+	{"PCIERC0_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC1_CFG033"              ,	              0x84ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	645},
+	{"PCIERC0_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC1_CFG034"              ,	              0x88ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	646},
+	{"PCIERC0_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC1_CFG035"              ,	              0x8Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	647},
+	{"PCIERC0_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC1_CFG036"              ,	              0x90ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	648},
+	{"PCIERC0_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC1_CFG037"              ,	              0x94ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	649},
+	{"PCIERC0_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC1_CFG038"              ,	              0x98ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	650},
+	{"PCIERC0_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC1_CFG039"              ,	              0x9Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	651},
+	{"PCIERC0_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC1_CFG040"              ,	              0xA0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	652},
+	{"PCIERC0_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC1_CFG041"              ,	              0xA4ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	653},
+	{"PCIERC0_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC1_CFG042"              ,	              0xA8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	654},
+	{"PCIERC0_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC1_CFG064"              ,	             0x100ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	655},
+	{"PCIERC0_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC1_CFG065"              ,	             0x104ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	656},
+	{"PCIERC0_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC1_CFG066"              ,	             0x108ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	657},
+	{"PCIERC0_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC1_CFG067"              ,	             0x10Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	658},
+	{"PCIERC0_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC1_CFG068"              ,	             0x110ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	659},
+	{"PCIERC0_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC1_CFG069"              ,	             0x114ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	660},
+	{"PCIERC0_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC1_CFG070"              ,	             0x118ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	661},
+	{"PCIERC0_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC1_CFG071"              ,	             0x11Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	662},
+	{"PCIERC0_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC1_CFG072"              ,	             0x120ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	663},
+	{"PCIERC0_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC1_CFG073"              ,	             0x124ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	664},
+	{"PCIERC0_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC1_CFG074"              ,	             0x128ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	665},
+	{"PCIERC0_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC1_CFG075"              ,	             0x12Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	666},
+	{"PCIERC0_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC1_CFG076"              ,	             0x130ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	667},
+	{"PCIERC0_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC1_CFG077"              ,	             0x134ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	668},
+	{"PCIERC0_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC1_CFG448"              ,	             0x700ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	669},
+	{"PCIERC0_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC1_CFG449"              ,	             0x704ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	670},
+	{"PCIERC0_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC1_CFG450"              ,	             0x708ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	671},
+	{"PCIERC0_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC1_CFG451"              ,	             0x70Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	672},
+	{"PCIERC0_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC1_CFG452"              ,	             0x710ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	673},
+	{"PCIERC0_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC1_CFG453"              ,	             0x714ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	674},
+	{"PCIERC0_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC1_CFG454"              ,	             0x718ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	675},
+	{"PCIERC0_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC1_CFG455"              ,	             0x71Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	676},
+	{"PCIERC0_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC1_CFG456"              ,	             0x720ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	677},
+	{"PCIERC0_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC1_CFG458"              ,	             0x728ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	678},
+	{"PCIERC0_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC1_CFG459"              ,	             0x72Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	679},
+	{"PCIERC0_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC1_CFG460"              ,	             0x730ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	680},
+	{"PCIERC0_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC1_CFG461"              ,	             0x734ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	681},
+	{"PCIERC0_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC1_CFG462"              ,	             0x738ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	682},
+	{"PCIERC0_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC1_CFG463"              ,	             0x73Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	683},
+	{"PCIERC0_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC1_CFG464"              ,	             0x740ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	684},
+	{"PCIERC0_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC1_CFG465"              ,	             0x744ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	685},
+	{"PCIERC0_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC1_CFG466"              ,	             0x748ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	686},
+	{"PCIERC0_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC1_CFG467"              ,	             0x74Cull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	687},
+	{"PCIERC0_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC1_CFG468"              ,	             0x750ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	688},
+	{"PCIERC0_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC1_CFG490"              ,	             0x7A8ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	689},
+	{"PCIERC0_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC1_CFG491"              ,	             0x7ACull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	690},
+	{"PCIERC0_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC1_CFG492"              ,	             0x7B0ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	691},
+	{"PCIERC0_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC1_CFG516"              ,	             0x810ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	692},
+	{"PCIERC0_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCIERC1_CFG517"              ,	             0x814ull,	CVMX_CSR_DB_TYPE_PCICONFIGRC,	32,	693},
+	{"PCS0_AN000_ADV_REG"          ,	   0x11800B0001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN001_ADV_REG"          ,	   0x11800B0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN002_ADV_REG"          ,	   0x11800B0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN003_ADV_REG"          ,	   0x11800B0001C10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	694},
+	{"PCS0_AN000_EXT_ST_REG"       ,	   0x11800B0001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN001_EXT_ST_REG"       ,	   0x11800B0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN002_EXT_ST_REG"       ,	   0x11800B0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN003_EXT_ST_REG"       ,	   0x11800B0001C28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	695},
+	{"PCS0_AN000_LP_ABIL_REG"      ,	   0x11800B0001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN001_LP_ABIL_REG"      ,	   0x11800B0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN002_LP_ABIL_REG"      ,	   0x11800B0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN003_LP_ABIL_REG"      ,	   0x11800B0001C18ull,	CVMX_CSR_DB_TYPE_RSL,	64,	696},
+	{"PCS0_AN000_RESULTS_REG"      ,	   0x11800B0001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN001_RESULTS_REG"      ,	   0x11800B0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN002_RESULTS_REG"      ,	   0x11800B0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_AN003_RESULTS_REG"      ,	   0x11800B0001C20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	697},
+	{"PCS0_INT000_EN_REG"          ,	   0x11800B0001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT001_EN_REG"          ,	   0x11800B0001488ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT002_EN_REG"          ,	   0x11800B0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT003_EN_REG"          ,	   0x11800B0001C88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	698},
+	{"PCS0_INT000_REG"             ,	   0x11800B0001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_INT001_REG"             ,	   0x11800B0001480ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_INT002_REG"             ,	   0x11800B0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_INT003_REG"             ,	   0x11800B0001C80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	699},
+	{"PCS0_LINK000_TIMER_COUNT_REG",	   0x11800B0001040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LINK001_TIMER_COUNT_REG",	   0x11800B0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LINK002_TIMER_COUNT_REG",	   0x11800B0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LINK003_TIMER_COUNT_REG",	   0x11800B0001C40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	700},
+	{"PCS0_LOG_ANL000_REG"         ,	   0x11800B0001090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_LOG_ANL001_REG"         ,	   0x11800B0001490ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_LOG_ANL002_REG"         ,	   0x11800B0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_LOG_ANL003_REG"         ,	   0x11800B0001C90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	701},
+	{"PCS0_MISC000_CTL_REG"        ,	   0x11800B0001078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MISC001_CTL_REG"        ,	   0x11800B0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MISC002_CTL_REG"        ,	   0x11800B0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MISC003_CTL_REG"        ,	   0x11800B0001C78ull,	CVMX_CSR_DB_TYPE_RSL,	64,	702},
+	{"PCS0_MR000_CONTROL_REG"      ,	   0x11800B0001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR001_CONTROL_REG"      ,	   0x11800B0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR002_CONTROL_REG"      ,	   0x11800B0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR003_CONTROL_REG"      ,	   0x11800B0001C00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	703},
+	{"PCS0_MR000_STATUS_REG"       ,	   0x11800B0001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_MR001_STATUS_REG"       ,	   0x11800B0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_MR002_STATUS_REG"       ,	   0x11800B0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_MR003_STATUS_REG"       ,	   0x11800B0001C08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	704},
+	{"PCS0_RX000_STATES_REG"       ,	   0x11800B0001058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX001_STATES_REG"       ,	   0x11800B0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX002_STATES_REG"       ,	   0x11800B0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX003_STATES_REG"       ,	   0x11800B0001C58ull,	CVMX_CSR_DB_TYPE_RSL,	64,	705},
+	{"PCS0_RX000_SYNC_REG"         ,	   0x11800B0001050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_RX001_SYNC_REG"         ,	   0x11800B0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_RX002_SYNC_REG"         ,	   0x11800B0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_RX003_SYNC_REG"         ,	   0x11800B0001C50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	706},
+	{"PCS0_SGM000_AN_ADV_REG"      ,	   0x11800B0001068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM001_AN_ADV_REG"      ,	   0x11800B0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM002_AN_ADV_REG"      ,	   0x11800B0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM003_AN_ADV_REG"      ,	   0x11800B0001C68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	707},
+	{"PCS0_SGM000_LP_ADV_REG"      ,	   0x11800B0001070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_SGM001_LP_ADV_REG"      ,	   0x11800B0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_SGM002_LP_ADV_REG"      ,	   0x11800B0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_SGM003_LP_ADV_REG"      ,	   0x11800B0001C70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	708},
+	{"PCS0_TX000_STATES_REG"       ,	   0x11800B0001060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX001_STATES_REG"       ,	   0x11800B0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX002_STATES_REG"       ,	   0x11800B0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX003_STATES_REG"       ,	   0x11800B0001C60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	709},
+	{"PCS0_TX_RX000_POLARITY_REG"  ,	   0x11800B0001048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_TX_RX001_POLARITY_REG"  ,	   0x11800B0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_TX_RX002_POLARITY_REG"  ,	   0x11800B0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCS0_TX_RX003_POLARITY_REG"  ,	   0x11800B0001C48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	710},
+	{"PCSX0_10GBX_STATUS_REG"      ,	   0x11800B0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCSX1_10GBX_STATUS_REG"      ,	   0x11800B8000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	711},
+	{"PCSX0_BIST_STATUS_REG"       ,	   0x11800B0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCSX1_BIST_STATUS_REG"       ,	   0x11800B8000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	712},
+	{"PCSX0_BIT_LOCK_STATUS_REG"   ,	   0x11800B0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCSX1_BIT_LOCK_STATUS_REG"   ,	   0x11800B8000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	713},
+	{"PCSX0_CONTROL1_REG"          ,	   0x11800B0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCSX1_CONTROL1_REG"          ,	   0x11800B8000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	714},
+	{"PCSX0_CONTROL2_REG"          ,	   0x11800B0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCSX1_CONTROL2_REG"          ,	   0x11800B8000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	715},
+	{"PCSX0_INT_EN_REG"            ,	   0x11800B0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCSX1_INT_EN_REG"            ,	   0x11800B8000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	716},
+	{"PCSX0_INT_REG"               ,	   0x11800B0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCSX1_INT_REG"               ,	   0x11800B8000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	717},
+	{"PCSX0_LOG_ANL_REG"           ,	   0x11800B0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCSX1_LOG_ANL_REG"           ,	   0x11800B8000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	718},
+	{"PCSX0_MISC_CTL_REG"          ,	   0x11800B0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCSX1_MISC_CTL_REG"          ,	   0x11800B8000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	719},
+	{"PCSX0_RX_SYNC_STATES_REG"    ,	   0x11800B0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCSX1_RX_SYNC_STATES_REG"    ,	   0x11800B8000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	720},
+	{"PCSX0_SPD_ABIL_REG"          ,	   0x11800B0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCSX1_SPD_ABIL_REG"          ,	   0x11800B8000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	721},
+	{"PCSX0_STATUS1_REG"           ,	   0x11800B0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCSX1_STATUS1_REG"           ,	   0x11800B8000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	722},
+	{"PCSX0_STATUS2_REG"           ,	   0x11800B0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PCSX1_STATUS2_REG"           ,	   0x11800B8000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	723},
+	{"PCSX0_TX_RX_POLARITY_REG"    ,	   0x11800B0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PCSX1_TX_RX_POLARITY_REG"    ,	   0x11800B8000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	724},
+	{"PCSX0_TX_RX_STATES_REG"      ,	   0x11800B0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PCSX1_TX_RX_STATES_REG"      ,	   0x11800B8000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	725},
+	{"PESC0_BIST_STATUS"           ,	   0x11800C8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PESC1_BIST_STATUS"           ,	   0x11800D0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	726},
+	{"PESC0_BIST_STATUS2"          ,	   0x11800C8000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PESC1_BIST_STATUS2"          ,	   0x11800D0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	727},
+	{"PESC0_CFG_RD"                ,	   0x11800C8000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PESC1_CFG_RD"                ,	   0x11800D0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	728},
+	{"PESC0_CFG_WR"                ,	   0x11800C8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PESC1_CFG_WR"                ,	   0x11800D0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	729},
+	{"PESC0_CPL_LUT_VALID"         ,	   0x11800C8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PESC1_CPL_LUT_VALID"         ,	   0x11800D0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	730},
+	{"PESC0_CTL_STATUS"            ,	   0x11800C8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PESC1_CTL_STATUS"            ,	   0x11800D0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	731},
+	{"PESC0_CTL_STATUS2"           ,	   0x11800C8000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PESC1_CTL_STATUS2"           ,	   0x11800D0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	732},
+	{"PESC0_DBG_INFO"              ,	   0x11800C8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PESC1_DBG_INFO"              ,	   0x11800D0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	733},
+	{"PESC0_DBG_INFO_EN"           ,	   0x11800C80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PESC1_DBG_INFO_EN"           ,	   0x11800D00000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	734},
+	{"PESC0_DIAG_STATUS"           ,	   0x11800C8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PESC1_DIAG_STATUS"           ,	   0x11800D0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	735},
+	{"PESC0_P2N_BAR0_START"        ,	   0x11800C8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PESC1_P2N_BAR0_START"        ,	   0x11800D0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	736},
+	{"PESC0_P2N_BAR1_START"        ,	   0x11800C8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PESC1_P2N_BAR1_START"        ,	   0x11800D0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	737},
+	{"PESC0_P2N_BAR2_START"        ,	   0x11800C8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PESC1_P2N_BAR2_START"        ,	   0x11800D0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	738},
+	{"PESC0_P2P_BAR000_END"        ,	   0x11800C8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR001_END"        ,	   0x11800C8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR002_END"        ,	   0x11800C8000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR003_END"        ,	   0x11800C8000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR000_END"        ,	   0x11800D0000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR001_END"        ,	   0x11800D0000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR002_END"        ,	   0x11800D0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC1_P2P_BAR003_END"        ,	   0x11800D0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	739},
+	{"PESC0_P2P_BAR000_START"      ,	   0x11800C8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_P2P_BAR001_START"      ,	   0x11800C8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_P2P_BAR002_START"      ,	   0x11800C8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_P2P_BAR003_START"      ,	   0x11800C8000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR000_START"      ,	   0x11800D0000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR001_START"      ,	   0x11800D0000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR002_START"      ,	   0x11800D0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC1_P2P_BAR003_START"      ,	   0x11800D0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	740},
+	{"PESC0_TLP_CREDITS"           ,	   0x11800C8000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PESC1_TLP_CREDITS"           ,	   0x11800D0000038ull,	CVMX_CSR_DB_TYPE_RSL,	64,	741},
+	{"PIP_BIST_STATUS"             ,	   0x11800A0000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	742},
+	{"PIP_DEC_IPSEC0"              ,	   0x11800A0000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DEC_IPSEC1"              ,	   0x11800A0000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DEC_IPSEC2"              ,	   0x11800A0000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DEC_IPSEC3"              ,	   0x11800A0000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	743},
+	{"PIP_DSA_SRC_GRP"             ,	   0x11800A0000190ull,	CVMX_CSR_DB_TYPE_RSL,	64,	744},
+	{"PIP_DSA_VID_GRP"             ,	   0x11800A0000198ull,	CVMX_CSR_DB_TYPE_RSL,	64,	745},
+	{"PIP_FRM_LEN_CHK0"            ,	   0x11800A0000180ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_FRM_LEN_CHK1"            ,	   0x11800A0000188ull,	CVMX_CSR_DB_TYPE_RSL,	64,	746},
+	{"PIP_GBL_CFG"                 ,	   0x11800A0000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	747},
+	{"PIP_GBL_CTL"                 ,	   0x11800A0000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	748},
+	{"PIP_HG_PRI_QOS"              ,	   0x11800A00001A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	749},
+	{"PIP_INT_EN"                  ,	   0x11800A0000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	750},
+	{"PIP_INT_REG"                 ,	   0x11800A0000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	751},
+	{"PIP_IP_OFFSET"               ,	   0x11800A0000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	752},
+	{"PIP_PRT_CFG0"                ,	   0x11800A0000200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG1"                ,	   0x11800A0000208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG2"                ,	   0x11800A0000210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG3"                ,	   0x11800A0000218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG32"               ,	   0x11800A0000300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG33"               ,	   0x11800A0000308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG34"               ,	   0x11800A0000310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG35"               ,	   0x11800A0000318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG36"               ,	   0x11800A0000320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG37"               ,	   0x11800A0000328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG38"               ,	   0x11800A0000330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_CFG39"               ,	   0x11800A0000338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	753},
+	{"PIP_PRT_TAG0"                ,	   0x11800A0000400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG1"                ,	   0x11800A0000408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG2"                ,	   0x11800A0000410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG3"                ,	   0x11800A0000418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG32"               ,	   0x11800A0000500ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG33"               ,	   0x11800A0000508ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG34"               ,	   0x11800A0000510ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG35"               ,	   0x11800A0000518ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG36"               ,	   0x11800A0000520ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG37"               ,	   0x11800A0000528ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG38"               ,	   0x11800A0000530ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_PRT_TAG39"               ,	   0x11800A0000538ull,	CVMX_CSR_DB_TYPE_RSL,	64,	754},
+	{"PIP_QOS_DIFF0"               ,	   0x11800A0000600ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF1"               ,	   0x11800A0000608ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF2"               ,	   0x11800A0000610ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF3"               ,	   0x11800A0000618ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF4"               ,	   0x11800A0000620ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF5"               ,	   0x11800A0000628ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF6"               ,	   0x11800A0000630ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF7"               ,	   0x11800A0000638ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF8"               ,	   0x11800A0000640ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF9"               ,	   0x11800A0000648ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF10"              ,	   0x11800A0000650ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF11"              ,	   0x11800A0000658ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF12"              ,	   0x11800A0000660ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF13"              ,	   0x11800A0000668ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF14"              ,	   0x11800A0000670ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF15"              ,	   0x11800A0000678ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF16"              ,	   0x11800A0000680ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF17"              ,	   0x11800A0000688ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF18"              ,	   0x11800A0000690ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF19"              ,	   0x11800A0000698ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF20"              ,	   0x11800A00006A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF21"              ,	   0x11800A00006A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF22"              ,	   0x11800A00006B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF23"              ,	   0x11800A00006B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF24"              ,	   0x11800A00006C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF25"              ,	   0x11800A00006C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF26"              ,	   0x11800A00006D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF27"              ,	   0x11800A00006D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF28"              ,	   0x11800A00006E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF29"              ,	   0x11800A00006E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF30"              ,	   0x11800A00006F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF31"              ,	   0x11800A00006F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF32"              ,	   0x11800A0000700ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF33"              ,	   0x11800A0000708ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF34"              ,	   0x11800A0000710ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF35"              ,	   0x11800A0000718ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF36"              ,	   0x11800A0000720ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF37"              ,	   0x11800A0000728ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF38"              ,	   0x11800A0000730ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF39"              ,	   0x11800A0000738ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF40"              ,	   0x11800A0000740ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF41"              ,	   0x11800A0000748ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF42"              ,	   0x11800A0000750ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF43"              ,	   0x11800A0000758ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF44"              ,	   0x11800A0000760ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF45"              ,	   0x11800A0000768ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF46"              ,	   0x11800A0000770ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF47"              ,	   0x11800A0000778ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF48"              ,	   0x11800A0000780ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF49"              ,	   0x11800A0000788ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF50"              ,	   0x11800A0000790ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF51"              ,	   0x11800A0000798ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF52"              ,	   0x11800A00007A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF53"              ,	   0x11800A00007A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF54"              ,	   0x11800A00007B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF55"              ,	   0x11800A00007B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF56"              ,	   0x11800A00007C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF57"              ,	   0x11800A00007C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF58"              ,	   0x11800A00007D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF59"              ,	   0x11800A00007D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF60"              ,	   0x11800A00007E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF61"              ,	   0x11800A00007E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF62"              ,	   0x11800A00007F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_DIFF63"              ,	   0x11800A00007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	755},
+	{"PIP_QOS_VLAN0"               ,	   0x11800A00000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN1"               ,	   0x11800A00000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN2"               ,	   0x11800A00000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN3"               ,	   0x11800A00000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN4"               ,	   0x11800A00000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN5"               ,	   0x11800A00000E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN6"               ,	   0x11800A00000F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_VLAN7"               ,	   0x11800A00000F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	756},
+	{"PIP_QOS_WATCH0"              ,	   0x11800A0000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH1"              ,	   0x11800A0000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH2"              ,	   0x11800A0000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH3"              ,	   0x11800A0000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH4"              ,	   0x11800A0000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH5"              ,	   0x11800A0000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH6"              ,	   0x11800A0000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_QOS_WATCH7"              ,	   0x11800A0000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	757},
+	{"PIP_RAW_WORD"                ,	   0x11800A00000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	758},
+	{"PIP_SFT_RST"                 ,	   0x11800A0000030ull,	CVMX_CSR_DB_TYPE_RSL,	64,	759},
+	{"PIP_STAT0_PRT0"              ,	   0x11800A0000800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT1"              ,	   0x11800A0000850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT2"              ,	   0x11800A00008A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT3"              ,	   0x11800A00008F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT32"             ,	   0x11800A0001200ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT33"             ,	   0x11800A0001250ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT34"             ,	   0x11800A00012A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT35"             ,	   0x11800A00012F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT36"             ,	   0x11800A0001340ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT37"             ,	   0x11800A0001390ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT38"             ,	   0x11800A00013E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT0_PRT39"             ,	   0x11800A0001430ull,	CVMX_CSR_DB_TYPE_RSL,	64,	760},
+	{"PIP_STAT1_PRT0"              ,	   0x11800A0000808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT1"              ,	   0x11800A0000858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT2"              ,	   0x11800A00008A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT3"              ,	   0x11800A00008F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT32"             ,	   0x11800A0001208ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT33"             ,	   0x11800A0001258ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT34"             ,	   0x11800A00012A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT35"             ,	   0x11800A00012F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT36"             ,	   0x11800A0001348ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT37"             ,	   0x11800A0001398ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT38"             ,	   0x11800A00013E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT1_PRT39"             ,	   0x11800A0001438ull,	CVMX_CSR_DB_TYPE_RSL,	64,	761},
+	{"PIP_STAT2_PRT0"              ,	   0x11800A0000810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT1"              ,	   0x11800A0000860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT2"              ,	   0x11800A00008B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT3"              ,	   0x11800A0000900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT32"             ,	   0x11800A0001210ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT33"             ,	   0x11800A0001260ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT34"             ,	   0x11800A00012B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT35"             ,	   0x11800A0001300ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT36"             ,	   0x11800A0001350ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT37"             ,	   0x11800A00013A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT38"             ,	   0x11800A00013F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT2_PRT39"             ,	   0x11800A0001440ull,	CVMX_CSR_DB_TYPE_RSL,	64,	762},
+	{"PIP_STAT3_PRT0"              ,	   0x11800A0000818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT1"              ,	   0x11800A0000868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT2"              ,	   0x11800A00008B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT3"              ,	   0x11800A0000908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT32"             ,	   0x11800A0001218ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT33"             ,	   0x11800A0001268ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT34"             ,	   0x11800A00012B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT35"             ,	   0x11800A0001308ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT36"             ,	   0x11800A0001358ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT37"             ,	   0x11800A00013A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT38"             ,	   0x11800A00013F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT3_PRT39"             ,	   0x11800A0001448ull,	CVMX_CSR_DB_TYPE_RSL,	64,	763},
+	{"PIP_STAT4_PRT0"              ,	   0x11800A0000820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT1"              ,	   0x11800A0000870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT2"              ,	   0x11800A00008C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT3"              ,	   0x11800A0000910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT32"             ,	   0x11800A0001220ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT33"             ,	   0x11800A0001270ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT34"             ,	   0x11800A00012C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT35"             ,	   0x11800A0001310ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT36"             ,	   0x11800A0001360ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT37"             ,	   0x11800A00013B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT38"             ,	   0x11800A0001400ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT4_PRT39"             ,	   0x11800A0001450ull,	CVMX_CSR_DB_TYPE_RSL,	64,	764},
+	{"PIP_STAT5_PRT0"              ,	   0x11800A0000828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT1"              ,	   0x11800A0000878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT2"              ,	   0x11800A00008C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT3"              ,	   0x11800A0000918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT32"             ,	   0x11800A0001228ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT33"             ,	   0x11800A0001278ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT34"             ,	   0x11800A00012C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT35"             ,	   0x11800A0001318ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT36"             ,	   0x11800A0001368ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT37"             ,	   0x11800A00013B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT38"             ,	   0x11800A0001408ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT5_PRT39"             ,	   0x11800A0001458ull,	CVMX_CSR_DB_TYPE_RSL,	64,	765},
+	{"PIP_STAT6_PRT0"              ,	   0x11800A0000830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT1"              ,	   0x11800A0000880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT2"              ,	   0x11800A00008D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT3"              ,	   0x11800A0000920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT32"             ,	   0x11800A0001230ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT33"             ,	   0x11800A0001280ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT34"             ,	   0x11800A00012D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT35"             ,	   0x11800A0001320ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT36"             ,	   0x11800A0001370ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT37"             ,	   0x11800A00013C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT38"             ,	   0x11800A0001410ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT6_PRT39"             ,	   0x11800A0001460ull,	CVMX_CSR_DB_TYPE_RSL,	64,	766},
+	{"PIP_STAT7_PRT0"              ,	   0x11800A0000838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT1"              ,	   0x11800A0000888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT2"              ,	   0x11800A00008D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT3"              ,	   0x11800A0000928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT32"             ,	   0x11800A0001238ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT33"             ,	   0x11800A0001288ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT34"             ,	   0x11800A00012D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT35"             ,	   0x11800A0001328ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT36"             ,	   0x11800A0001378ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT37"             ,	   0x11800A00013C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT38"             ,	   0x11800A0001418ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT7_PRT39"             ,	   0x11800A0001468ull,	CVMX_CSR_DB_TYPE_RSL,	64,	767},
+	{"PIP_STAT8_PRT0"              ,	   0x11800A0000840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT1"              ,	   0x11800A0000890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT2"              ,	   0x11800A00008E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT3"              ,	   0x11800A0000930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT32"             ,	   0x11800A0001240ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT33"             ,	   0x11800A0001290ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT34"             ,	   0x11800A00012E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT35"             ,	   0x11800A0001330ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT36"             ,	   0x11800A0001380ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT37"             ,	   0x11800A00013D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT38"             ,	   0x11800A0001420ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT8_PRT39"             ,	   0x11800A0001470ull,	CVMX_CSR_DB_TYPE_RSL,	64,	768},
+	{"PIP_STAT9_PRT0"              ,	   0x11800A0000848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT1"              ,	   0x11800A0000898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT2"              ,	   0x11800A00008E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT3"              ,	   0x11800A0000938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT32"             ,	   0x11800A0001248ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT33"             ,	   0x11800A0001298ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT34"             ,	   0x11800A00012E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT35"             ,	   0x11800A0001338ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT36"             ,	   0x11800A0001388ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT37"             ,	   0x11800A00013D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT38"             ,	   0x11800A0001428ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT9_PRT39"             ,	   0x11800A0001478ull,	CVMX_CSR_DB_TYPE_RSL,	64,	769},
+	{"PIP_STAT_CTL"                ,	   0x11800A0000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	770},
+	{"PIP_STAT_INB_ERRS0"          ,	   0x11800A0001A10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS1"          ,	   0x11800A0001A30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS2"          ,	   0x11800A0001A50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS3"          ,	   0x11800A0001A70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS32"         ,	   0x11800A0001E10ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS33"         ,	   0x11800A0001E30ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS34"         ,	   0x11800A0001E50ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS35"         ,	   0x11800A0001E70ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS36"         ,	   0x11800A0001E90ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS37"         ,	   0x11800A0001EB0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS38"         ,	   0x11800A0001ED0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_ERRS39"         ,	   0x11800A0001EF0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	771},
+	{"PIP_STAT_INB_OCTS0"          ,	   0x11800A0001A08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS1"          ,	   0x11800A0001A28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS2"          ,	   0x11800A0001A48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS3"          ,	   0x11800A0001A68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS32"         ,	   0x11800A0001E08ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS33"         ,	   0x11800A0001E28ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS34"         ,	   0x11800A0001E48ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS35"         ,	   0x11800A0001E68ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS36"         ,	   0x11800A0001E88ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS37"         ,	   0x11800A0001EA8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS38"         ,	   0x11800A0001EC8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_OCTS39"         ,	   0x11800A0001EE8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	772},
+	{"PIP_STAT_INB_PKTS0"          ,	   0x11800A0001A00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS1"          ,	   0x11800A0001A20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS2"          ,	   0x11800A0001A40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS3"          ,	   0x11800A0001A60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS32"         ,	   0x11800A0001E00ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS33"         ,	   0x11800A0001E20ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS34"         ,	   0x11800A0001E40ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS35"         ,	   0x11800A0001E60ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS36"         ,	   0x11800A0001E80ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS37"         ,	   0x11800A0001EA0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS38"         ,	   0x11800A0001EC0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_STAT_INB_PKTS39"         ,	   0x11800A0001EE0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	773},
+	{"PIP_TAG_INC0"                ,	   0x11800A0001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC1"                ,	   0x11800A0001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC2"                ,	   0x11800A0001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC3"                ,	   0x11800A0001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC4"                ,	   0x11800A0001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC5"                ,	   0x11800A0001828ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC6"                ,	   0x11800A0001830ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC7"                ,	   0x11800A0001838ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC8"                ,	   0x11800A0001840ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC9"                ,	   0x11800A0001848ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC10"               ,	   0x11800A0001850ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC11"               ,	   0x11800A0001858ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC12"               ,	   0x11800A0001860ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC13"               ,	   0x11800A0001868ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC14"               ,	   0x11800A0001870ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC15"               ,	   0x11800A0001878ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC16"               ,	   0x11800A0001880ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC17"               ,	   0x11800A0001888ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC18"               ,	   0x11800A0001890ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC19"               ,	   0x11800A0001898ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC20"               ,	   0x11800A00018A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC21"               ,	   0x11800A00018A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC22"               ,	   0x11800A00018B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC23"               ,	   0x11800A00018B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC24"               ,	   0x11800A00018C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC25"               ,	   0x11800A00018C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC26"               ,	   0x11800A00018D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC27"               ,	   0x11800A00018D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC28"               ,	   0x11800A00018E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC29"               ,	   0x11800A00018E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC30"               ,	   0x11800A00018F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC31"               ,	   0x11800A00018F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC32"               ,	   0x11800A0001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC33"               ,	   0x11800A0001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC34"               ,	   0x11800A0001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC35"               ,	   0x11800A0001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC36"               ,	   0x11800A0001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC37"               ,	   0x11800A0001928ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC38"               ,	   0x11800A0001930ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC39"               ,	   0x11800A0001938ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC40"               ,	   0x11800A0001940ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC41"               ,	   0x11800A0001948ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC42"               ,	   0x11800A0001950ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC43"               ,	   0x11800A0001958ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC44"               ,	   0x11800A0001960ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC45"               ,	   0x11800A0001968ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC46"               ,	   0x11800A0001970ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC47"               ,	   0x11800A0001978ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC48"               ,	   0x11800A0001980ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC49"               ,	   0x11800A0001988ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC50"               ,	   0x11800A0001990ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC51"               ,	   0x11800A0001998ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC52"               ,	   0x11800A00019A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC53"               ,	   0x11800A00019A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC54"               ,	   0x11800A00019B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC55"               ,	   0x11800A00019B8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC56"               ,	   0x11800A00019C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC57"               ,	   0x11800A00019C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC58"               ,	   0x11800A00019D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC59"               ,	   0x11800A00019D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC60"               ,	   0x11800A00019E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC61"               ,	   0x11800A00019E8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC62"               ,	   0x11800A00019F0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_INC63"               ,	   0x11800A00019F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	774},
+	{"PIP_TAG_MASK"                ,	   0x11800A0000070ull,	CVMX_CSR_DB_TYPE_RSL,	64,	775},
+	{"PIP_TAG_SECRET"              ,	   0x11800A0000068ull,	CVMX_CSR_DB_TYPE_RSL,	64,	776},
+	{"PIP_TODO_ENTRY"              ,	   0x11800A0000078ull,	CVMX_CSR_DB_TYPE_RSL,	64,	777},
+	{"PKO_MEM_COUNT0"              ,	   0x1180050001080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	778},
+	{"PKO_MEM_COUNT1"              ,	   0x1180050001088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	779},
+	{"PKO_MEM_DEBUG0"              ,	   0x1180050001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	780},
+	{"PKO_MEM_DEBUG1"              ,	   0x1180050001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	781},
+	{"PKO_MEM_DEBUG10"             ,	   0x1180050001150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	782},
+	{"PKO_MEM_DEBUG11"             ,	   0x1180050001158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	783},
+	{"PKO_MEM_DEBUG12"             ,	   0x1180050001160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	784},
+	{"PKO_MEM_DEBUG13"             ,	   0x1180050001168ull,	CVMX_CSR_DB_TYPE_RSL,	64,	785},
+	{"PKO_MEM_DEBUG14"             ,	   0x1180050001170ull,	CVMX_CSR_DB_TYPE_RSL,	64,	786},
+	{"PKO_MEM_DEBUG2"              ,	   0x1180050001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	787},
+	{"PKO_MEM_DEBUG3"              ,	   0x1180050001118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	788},
+	{"PKO_MEM_DEBUG4"              ,	   0x1180050001120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	789},
+	{"PKO_MEM_DEBUG5"              ,	   0x1180050001128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	790},
+	{"PKO_MEM_DEBUG6"              ,	   0x1180050001130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	791},
+	{"PKO_MEM_DEBUG7"              ,	   0x1180050001138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	792},
+	{"PKO_MEM_DEBUG8"              ,	   0x1180050001140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	793},
+	{"PKO_MEM_DEBUG9"              ,	   0x1180050001148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	794},
+	{"PKO_MEM_PORT_PTRS"           ,	   0x1180050001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	795},
+	{"PKO_MEM_PORT_QOS"            ,	   0x1180050001018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	796},
+	{"PKO_MEM_PORT_RATE0"          ,	   0x1180050001020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	797},
+	{"PKO_MEM_PORT_RATE1"          ,	   0x1180050001028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	798},
+	{"PKO_MEM_QUEUE_PTRS"          ,	   0x1180050001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	799},
+	{"PKO_MEM_QUEUE_QOS"           ,	   0x1180050001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	800},
+	{"PKO_REG_BIST_RESULT"         ,	   0x1180050000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	801},
+	{"PKO_REG_CMD_BUF"             ,	   0x1180050000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	802},
+	{"PKO_REG_DEBUG0"              ,	   0x1180050000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	803},
+	{"PKO_REG_DEBUG1"              ,	   0x11800500000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	804},
+	{"PKO_REG_DEBUG2"              ,	   0x11800500000A8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	805},
+	{"PKO_REG_DEBUG3"              ,	   0x11800500000B0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	806},
+	{"PKO_REG_ENGINE_INFLIGHT"     ,	   0x1180050000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	807},
+	{"PKO_REG_ENGINE_THRESH"       ,	   0x1180050000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	808},
+	{"PKO_REG_ERROR"               ,	   0x1180050000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	809},
+	{"PKO_REG_FLAGS"               ,	   0x1180050000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	810},
+	{"PKO_REG_GMX_PORT_MODE"       ,	   0x1180050000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	811},
+	{"PKO_REG_INT_MASK"            ,	   0x1180050000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	812},
+	{"PKO_REG_QUEUE_MODE"          ,	   0x1180050000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	813},
+	{"PKO_REG_QUEUE_PTRS1"         ,	   0x1180050000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	814},
+	{"PKO_REG_READ_IDX"            ,	   0x1180050000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	815},
+	{"POW_BIST_STAT"               ,	   0x16700000003F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	816},
+	{"POW_DS_PC"                   ,	   0x1670000000398ull,	CVMX_CSR_DB_TYPE_NCB,	64,	817},
+	{"POW_ECC_ERR"                 ,	   0x1670000000218ull,	CVMX_CSR_DB_TYPE_NCB,	64,	818},
+	{"POW_INT_CTL"                 ,	   0x1670000000220ull,	CVMX_CSR_DB_TYPE_NCB,	64,	819},
+	{"POW_IQ_CNT0"                 ,	   0x1670000000340ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT1"                 ,	   0x1670000000348ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT2"                 ,	   0x1670000000350ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT3"                 ,	   0x1670000000358ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT4"                 ,	   0x1670000000360ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT5"                 ,	   0x1670000000368ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT6"                 ,	   0x1670000000370ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_CNT7"                 ,	   0x1670000000378ull,	CVMX_CSR_DB_TYPE_NCB,	64,	820},
+	{"POW_IQ_COM_CNT"              ,	   0x1670000000388ull,	CVMX_CSR_DB_TYPE_NCB,	64,	821},
+	{"POW_IQ_INT"                  ,	   0x1670000000238ull,	CVMX_CSR_DB_TYPE_NCB,	64,	822},
+	{"POW_IQ_INT_EN"               ,	   0x1670000000240ull,	CVMX_CSR_DB_TYPE_NCB,	64,	823},
+	{"POW_IQ_THR0"                 ,	   0x16700000003A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR1"                 ,	   0x16700000003A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR2"                 ,	   0x16700000003B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR3"                 ,	   0x16700000003B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR4"                 ,	   0x16700000003C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR5"                 ,	   0x16700000003C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR6"                 ,	   0x16700000003D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_IQ_THR7"                 ,	   0x16700000003D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	824},
+	{"POW_NOS_CNT"                 ,	   0x1670000000228ull,	CVMX_CSR_DB_TYPE_NCB,	64,	825},
+	{"POW_NW_TIM"                  ,	   0x1670000000210ull,	CVMX_CSR_DB_TYPE_NCB,	64,	826},
+	{"POW_PF_RST_MSK"              ,	   0x1670000000230ull,	CVMX_CSR_DB_TYPE_NCB,	64,	827},
+	{"POW_PP_GRP_MSK0"             ,	   0x1670000000000ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"POW_PP_GRP_MSK1"             ,	   0x1670000000008ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"POW_PP_GRP_MSK2"             ,	   0x1670000000010ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"POW_PP_GRP_MSK3"             ,	   0x1670000000018ull,	CVMX_CSR_DB_TYPE_NCB,	64,	828},
+	{"POW_QOS_RND0"                ,	   0x16700000001C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND1"                ,	   0x16700000001C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND2"                ,	   0x16700000001D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND3"                ,	   0x16700000001D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND4"                ,	   0x16700000001E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND5"                ,	   0x16700000001E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND6"                ,	   0x16700000001F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_RND7"                ,	   0x16700000001F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	829},
+	{"POW_QOS_THR0"                ,	   0x1670000000180ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR1"                ,	   0x1670000000188ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR2"                ,	   0x1670000000190ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR3"                ,	   0x1670000000198ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR4"                ,	   0x16700000001A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR5"                ,	   0x16700000001A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR6"                ,	   0x16700000001B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_QOS_THR7"                ,	   0x16700000001B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	830},
+	{"POW_TS_PC"                   ,	   0x1670000000390ull,	CVMX_CSR_DB_TYPE_NCB,	64,	831},
+	{"POW_WA_COM_PC"               ,	   0x1670000000380ull,	CVMX_CSR_DB_TYPE_NCB,	64,	832},
+	{"POW_WA_PC0"                  ,	   0x1670000000300ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC1"                  ,	   0x1670000000308ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC2"                  ,	   0x1670000000310ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC3"                  ,	   0x1670000000318ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC4"                  ,	   0x1670000000320ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC5"                  ,	   0x1670000000328ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC6"                  ,	   0x1670000000330ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WA_PC7"                  ,	   0x1670000000338ull,	CVMX_CSR_DB_TYPE_NCB,	64,	833},
+	{"POW_WQ_INT"                  ,	   0x1670000000200ull,	CVMX_CSR_DB_TYPE_NCB,	64,	834},
+	{"POW_WQ_INT_CNT0"             ,	   0x1670000000100ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT1"             ,	   0x1670000000108ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT2"             ,	   0x1670000000110ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT3"             ,	   0x1670000000118ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT4"             ,	   0x1670000000120ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT5"             ,	   0x1670000000128ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT6"             ,	   0x1670000000130ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT7"             ,	   0x1670000000138ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT8"             ,	   0x1670000000140ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT9"             ,	   0x1670000000148ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT10"            ,	   0x1670000000150ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT11"            ,	   0x1670000000158ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT12"            ,	   0x1670000000160ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT13"            ,	   0x1670000000168ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT14"            ,	   0x1670000000170ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_CNT15"            ,	   0x1670000000178ull,	CVMX_CSR_DB_TYPE_NCB,	64,	835},
+	{"POW_WQ_INT_PC"               ,	   0x1670000000208ull,	CVMX_CSR_DB_TYPE_NCB,	64,	836},
+	{"POW_WQ_INT_THR0"             ,	   0x1670000000080ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR1"             ,	   0x1670000000088ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR2"             ,	   0x1670000000090ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR3"             ,	   0x1670000000098ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR4"             ,	   0x16700000000A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR5"             ,	   0x16700000000A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR6"             ,	   0x16700000000B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR7"             ,	   0x16700000000B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR8"             ,	   0x16700000000C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR9"             ,	   0x16700000000C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR10"            ,	   0x16700000000D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR11"            ,	   0x16700000000D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR12"            ,	   0x16700000000E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR13"            ,	   0x16700000000E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR14"            ,	   0x16700000000F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WQ_INT_THR15"            ,	   0x16700000000F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	837},
+	{"POW_WS_PC0"                  ,	   0x1670000000280ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC1"                  ,	   0x1670000000288ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC2"                  ,	   0x1670000000290ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC3"                  ,	   0x1670000000298ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC4"                  ,	   0x16700000002A0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC5"                  ,	   0x16700000002A8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC6"                  ,	   0x16700000002B0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC7"                  ,	   0x16700000002B8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC8"                  ,	   0x16700000002C0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC9"                  ,	   0x16700000002C8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC10"                 ,	   0x16700000002D0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC11"                 ,	   0x16700000002D8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC12"                 ,	   0x16700000002E0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC13"                 ,	   0x16700000002E8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC14"                 ,	   0x16700000002F0ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"POW_WS_PC15"                 ,	   0x16700000002F8ull,	CVMX_CSR_DB_TYPE_NCB,	64,	838},
+	{"RAD_MEM_DEBUG0"              ,	   0x1180070001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	839},
+	{"RAD_MEM_DEBUG1"              ,	   0x1180070001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	840},
+	{"RAD_MEM_DEBUG2"              ,	   0x1180070001010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	841},
+	{"RAD_REG_BIST_RESULT"         ,	   0x1180070000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	842},
+	{"RAD_REG_CMD_BUF"             ,	   0x1180070000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	843},
+	{"RAD_REG_CTL"                 ,	   0x1180070000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	844},
+	{"RAD_REG_DEBUG0"              ,	   0x1180070000100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	845},
+	{"RAD_REG_DEBUG1"              ,	   0x1180070000108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	846},
+	{"RAD_REG_DEBUG10"             ,	   0x1180070000150ull,	CVMX_CSR_DB_TYPE_RSL,	64,	847},
+	{"RAD_REG_DEBUG11"             ,	   0x1180070000158ull,	CVMX_CSR_DB_TYPE_RSL,	64,	848},
+	{"RAD_REG_DEBUG12"             ,	   0x1180070000160ull,	CVMX_CSR_DB_TYPE_RSL,	64,	849},
+	{"RAD_REG_DEBUG2"              ,	   0x1180070000110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	850},
+	{"RAD_REG_DEBUG3"              ,	   0x1180070000118ull,	CVMX_CSR_DB_TYPE_RSL,	64,	851},
+	{"RAD_REG_DEBUG4"              ,	   0x1180070000120ull,	CVMX_CSR_DB_TYPE_RSL,	64,	852},
+	{"RAD_REG_DEBUG5"              ,	   0x1180070000128ull,	CVMX_CSR_DB_TYPE_RSL,	64,	853},
+	{"RAD_REG_DEBUG6"              ,	   0x1180070000130ull,	CVMX_CSR_DB_TYPE_RSL,	64,	854},
+	{"RAD_REG_DEBUG7"              ,	   0x1180070000138ull,	CVMX_CSR_DB_TYPE_RSL,	64,	855},
+	{"RAD_REG_DEBUG8"              ,	   0x1180070000140ull,	CVMX_CSR_DB_TYPE_RSL,	64,	856},
+	{"RAD_REG_DEBUG9"              ,	   0x1180070000148ull,	CVMX_CSR_DB_TYPE_RSL,	64,	857},
+	{"RAD_REG_ERROR"               ,	   0x1180070000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	858},
+	{"RAD_REG_INT_MASK"            ,	   0x1180070000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	859},
+	{"RAD_REG_POLYNOMIAL"          ,	   0x1180070000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	860},
+	{"RAD_REG_READ_IDX"            ,	   0x1180070000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	861},
+	{"RNM_BIST_STATUS"             ,	   0x1180040000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	862},
+	{"RNM_CTL_STATUS"              ,	   0x1180040000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	863},
+	{"SMI0_CLK"                    ,	   0x1180000001818ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"SMI1_CLK"                    ,	   0x1180000001918ull,	CVMX_CSR_DB_TYPE_RSL,	64,	864},
+	{"SMI0_CMD"                    ,	   0x1180000001800ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"SMI1_CMD"                    ,	   0x1180000001900ull,	CVMX_CSR_DB_TYPE_RSL,	64,	865},
+	{"SMI0_EN"                     ,	   0x1180000001820ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"SMI1_EN"                     ,	   0x1180000001920ull,	CVMX_CSR_DB_TYPE_RSL,	64,	866},
+	{"SMI0_RD_DAT"                 ,	   0x1180000001810ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"SMI1_RD_DAT"                 ,	   0x1180000001910ull,	CVMX_CSR_DB_TYPE_RSL,	64,	867},
+	{"SMI0_WR_DAT"                 ,	   0x1180000001808ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"SMI1_WR_DAT"                 ,	   0x1180000001908ull,	CVMX_CSR_DB_TYPE_RSL,	64,	868},
+	{"TIM_MEM_DEBUG0"              ,	   0x1180058001100ull,	CVMX_CSR_DB_TYPE_RSL,	64,	869},
+	{"TIM_MEM_DEBUG1"              ,	   0x1180058001108ull,	CVMX_CSR_DB_TYPE_RSL,	64,	870},
+	{"TIM_MEM_DEBUG2"              ,	   0x1180058001110ull,	CVMX_CSR_DB_TYPE_RSL,	64,	871},
+	{"TIM_MEM_RING0"               ,	   0x1180058001000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	872},
+	{"TIM_MEM_RING1"               ,	   0x1180058001008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	873},
+	{"TIM_REG_BIST_RESULT"         ,	   0x1180058000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	874},
+	{"TIM_REG_ERROR"               ,	   0x1180058000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	875},
+	{"TIM_REG_FLAGS"               ,	   0x1180058000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	876},
+	{"TIM_REG_INT_MASK"            ,	   0x1180058000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	877},
+	{"TIM_REG_READ_IDX"            ,	   0x1180058000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	878},
+	{"TRA_BIST_STATUS"             ,	   0x11800A8000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	879},
+	{"TRA_CTL"                     ,	   0x11800A8000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	880},
+	{"TRA_CYCLES_SINCE"            ,	   0x11800A8000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	881},
+	{"TRA_CYCLES_SINCE1"           ,	   0x11800A8000028ull,	CVMX_CSR_DB_TYPE_RSL,	64,	882},
+	{"TRA_FILT_ADR_ADR"            ,	   0x11800A8000058ull,	CVMX_CSR_DB_TYPE_RSL,	64,	883},
+	{"TRA_FILT_ADR_MSK"            ,	   0x11800A8000060ull,	CVMX_CSR_DB_TYPE_RSL,	64,	884},
+	{"TRA_FILT_CMD"                ,	   0x11800A8000040ull,	CVMX_CSR_DB_TYPE_RSL,	64,	885},
+	{"TRA_FILT_DID"                ,	   0x11800A8000050ull,	CVMX_CSR_DB_TYPE_RSL,	64,	886},
+	{"TRA_FILT_SID"                ,	   0x11800A8000048ull,	CVMX_CSR_DB_TYPE_RSL,	64,	887},
+	{"TRA_INT_STATUS"              ,	   0x11800A8000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	888},
+	{"TRA_READ_DAT"                ,	   0x11800A8000020ull,	CVMX_CSR_DB_TYPE_RSL,	64,	889},
+	{"TRA_TRIG0_ADR_ADR"           ,	   0x11800A8000098ull,	CVMX_CSR_DB_TYPE_RSL,	64,	890},
+	{"TRA_TRIG0_ADR_MSK"           ,	   0x11800A80000A0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	891},
+	{"TRA_TRIG0_CMD"               ,	   0x11800A8000080ull,	CVMX_CSR_DB_TYPE_RSL,	64,	892},
+	{"TRA_TRIG0_DID"               ,	   0x11800A8000090ull,	CVMX_CSR_DB_TYPE_RSL,	64,	893},
+	{"TRA_TRIG0_SID"               ,	   0x11800A8000088ull,	CVMX_CSR_DB_TYPE_RSL,	64,	894},
+	{"TRA_TRIG1_ADR_ADR"           ,	   0x11800A80000D8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	895},
+	{"TRA_TRIG1_ADR_MSK"           ,	   0x11800A80000E0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	896},
+	{"TRA_TRIG1_CMD"               ,	   0x11800A80000C0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	897},
+	{"TRA_TRIG1_DID"               ,	   0x11800A80000D0ull,	CVMX_CSR_DB_TYPE_RSL,	64,	898},
+	{"TRA_TRIG1_SID"               ,	   0x11800A80000C8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	899},
+	{"USBC0_DAINT"                 ,	   0x16F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
+	{"USBC1_DAINT"                 ,	   0x17F0010000818ull,	CVMX_CSR_DB_TYPE_NCB,	32,	900},
+	{"USBC0_DAINTMSK"              ,	   0x16F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
+	{"USBC1_DAINTMSK"              ,	   0x17F001000081Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	901},
+	{"USBC0_DCFG"                  ,	   0x16F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
+	{"USBC1_DCFG"                  ,	   0x17F0010000800ull,	CVMX_CSR_DB_TYPE_NCB,	32,	902},
+	{"USBC0_DCTL"                  ,	   0x16F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
+	{"USBC1_DCTL"                  ,	   0x17F0010000804ull,	CVMX_CSR_DB_TYPE_NCB,	32,	903},
+	{"USBC0_DIEPCTL000"            ,	   0x16F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL001"            ,	   0x16F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL002"            ,	   0x16F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL003"            ,	   0x16F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPCTL004"            ,	   0x16F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL000"            ,	   0x17F0010000900ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL001"            ,	   0x17F0010000920ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL002"            ,	   0x17F0010000940ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL003"            ,	   0x17F0010000960ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC1_DIEPCTL004"            ,	   0x17F0010000980ull,	CVMX_CSR_DB_TYPE_NCB,	32,	904},
+	{"USBC0_DIEPINT000"            ,	   0x16F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT001"            ,	   0x16F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT002"            ,	   0x16F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT003"            ,	   0x16F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPINT004"            ,	   0x16F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT000"            ,	   0x17F0010000908ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT001"            ,	   0x17F0010000928ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT002"            ,	   0x17F0010000948ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT003"            ,	   0x17F0010000968ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC1_DIEPINT004"            ,	   0x17F0010000988ull,	CVMX_CSR_DB_TYPE_NCB,	32,	905},
+	{"USBC0_DIEPMSK"               ,	   0x16F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
+	{"USBC1_DIEPMSK"               ,	   0x17F0010000810ull,	CVMX_CSR_DB_TYPE_NCB,	32,	906},
+	{"USBC0_DIEPTSIZ000"           ,	   0x16F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ001"           ,	   0x16F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ002"           ,	   0x16F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ003"           ,	   0x16F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DIEPTSIZ004"           ,	   0x16F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ000"           ,	   0x17F0010000910ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ001"           ,	   0x17F0010000930ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ002"           ,	   0x17F0010000950ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ003"           ,	   0x17F0010000970ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC1_DIEPTSIZ004"           ,	   0x17F0010000990ull,	CVMX_CSR_DB_TYPE_NCB,	32,	907},
+	{"USBC0_DOEPCTL000"            ,	   0x16F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL001"            ,	   0x16F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL002"            ,	   0x16F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL003"            ,	   0x16F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPCTL004"            ,	   0x16F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL000"            ,	   0x17F0010000B00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL001"            ,	   0x17F0010000B20ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL002"            ,	   0x17F0010000B40ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL003"            ,	   0x17F0010000B60ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC1_DOEPCTL004"            ,	   0x17F0010000B80ull,	CVMX_CSR_DB_TYPE_NCB,	32,	908},
+	{"USBC0_DOEPINT000"            ,	   0x16F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT001"            ,	   0x16F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT002"            ,	   0x16F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT003"            ,	   0x16F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPINT004"            ,	   0x16F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT000"            ,	   0x17F0010000B08ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT001"            ,	   0x17F0010000B28ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT002"            ,	   0x17F0010000B48ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT003"            ,	   0x17F0010000B68ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC1_DOEPINT004"            ,	   0x17F0010000B88ull,	CVMX_CSR_DB_TYPE_NCB,	32,	909},
+	{"USBC0_DOEPMSK"               ,	   0x16F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
+	{"USBC1_DOEPMSK"               ,	   0x17F0010000814ull,	CVMX_CSR_DB_TYPE_NCB,	32,	910},
+	{"USBC0_DOEPTSIZ000"           ,	   0x16F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ001"           ,	   0x16F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ002"           ,	   0x16F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ003"           ,	   0x16F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DOEPTSIZ004"           ,	   0x16F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ000"           ,	   0x17F0010000B10ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ001"           ,	   0x17F0010000B30ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ002"           ,	   0x17F0010000B50ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ003"           ,	   0x17F0010000B70ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC1_DOEPTSIZ004"           ,	   0x17F0010000B90ull,	CVMX_CSR_DB_TYPE_NCB,	32,	911},
+	{"USBC0_DPTXFSIZ001"           ,	   0x16F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DPTXFSIZ002"           ,	   0x16F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DPTXFSIZ003"           ,	   0x16F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DPTXFSIZ004"           ,	   0x16F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ001"           ,	   0x17F0010000104ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ002"           ,	   0x17F0010000108ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ003"           ,	   0x17F001000010Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC1_DPTXFSIZ004"           ,	   0x17F0010000110ull,	CVMX_CSR_DB_TYPE_NCB,	32,	912},
+	{"USBC0_DSTS"                  ,	   0x16F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
+	{"USBC1_DSTS"                  ,	   0x17F0010000808ull,	CVMX_CSR_DB_TYPE_NCB,	32,	913},
+	{"USBC0_DTKNQR1"               ,	   0x16F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
+	{"USBC1_DTKNQR1"               ,	   0x17F0010000820ull,	CVMX_CSR_DB_TYPE_NCB,	32,	914},
+	{"USBC0_DTKNQR2"               ,	   0x16F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
+	{"USBC1_DTKNQR2"               ,	   0x17F0010000824ull,	CVMX_CSR_DB_TYPE_NCB,	32,	915},
+	{"USBC0_DTKNQR3"               ,	   0x16F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
+	{"USBC1_DTKNQR3"               ,	   0x17F0010000830ull,	CVMX_CSR_DB_TYPE_NCB,	32,	916},
+	{"USBC0_DTKNQR4"               ,	   0x16F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
+	{"USBC1_DTKNQR4"               ,	   0x17F0010000834ull,	CVMX_CSR_DB_TYPE_NCB,	32,	917},
+	{"USBC0_GAHBCFG"               ,	   0x16F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
+	{"USBC1_GAHBCFG"               ,	   0x17F0010000008ull,	CVMX_CSR_DB_TYPE_NCB,	32,	918},
+	{"USBC0_GHWCFG1"               ,	   0x16F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
+	{"USBC1_GHWCFG1"               ,	   0x17F0010000044ull,	CVMX_CSR_DB_TYPE_NCB,	32,	919},
+	{"USBC0_GHWCFG2"               ,	   0x16F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
+	{"USBC1_GHWCFG2"               ,	   0x17F0010000048ull,	CVMX_CSR_DB_TYPE_NCB,	32,	920},
+	{"USBC0_GHWCFG3"               ,	   0x16F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
+	{"USBC1_GHWCFG3"               ,	   0x17F001000004Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	921},
+	{"USBC0_GHWCFG4"               ,	   0x16F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
+	{"USBC1_GHWCFG4"               ,	   0x17F0010000050ull,	CVMX_CSR_DB_TYPE_NCB,	32,	922},
+	{"USBC0_GINTMSK"               ,	   0x16F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
+	{"USBC1_GINTMSK"               ,	   0x17F0010000018ull,	CVMX_CSR_DB_TYPE_NCB,	32,	923},
+	{"USBC0_GINTSTS"               ,	   0x16F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
+	{"USBC1_GINTSTS"               ,	   0x17F0010000014ull,	CVMX_CSR_DB_TYPE_NCB,	32,	924},
+	{"USBC0_GNPTXFSIZ"             ,	   0x16F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC1_GNPTXFSIZ"             ,	   0x17F0010000028ull,	CVMX_CSR_DB_TYPE_NCB,	32,	925},
+	{"USBC0_GNPTXSTS"              ,	   0x16F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
+	{"USBC1_GNPTXSTS"              ,	   0x17F001000002Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	926},
+	{"USBC0_GOTGCTL"               ,	   0x16F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC1_GOTGCTL"               ,	   0x17F0010000000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	927},
+	{"USBC0_GOTGINT"               ,	   0x16F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC1_GOTGINT"               ,	   0x17F0010000004ull,	CVMX_CSR_DB_TYPE_NCB,	32,	928},
+	{"USBC0_GRSTCTL"               ,	   0x16F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC1_GRSTCTL"               ,	   0x17F0010000010ull,	CVMX_CSR_DB_TYPE_NCB,	32,	929},
+	{"USBC0_GRXFSIZ"               ,	   0x16F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC1_GRXFSIZ"               ,	   0x17F0010000024ull,	CVMX_CSR_DB_TYPE_NCB,	32,	930},
+	{"USBC0_GRXSTSPD"              ,	   0x16F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
+	{"USBC1_GRXSTSPD"              ,	   0x17F0010040020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	931},
+	{"USBC0_GRXSTSPH"              ,	   0x16F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
+	{"USBC1_GRXSTSPH"              ,	   0x17F0010000020ull,	CVMX_CSR_DB_TYPE_NCB,	32,	932},
+	{"USBC0_GRXSTSRD"              ,	   0x16F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
+	{"USBC1_GRXSTSRD"              ,	   0x17F001004001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	933},
+	{"USBC0_GRXSTSRH"              ,	   0x16F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
+	{"USBC1_GRXSTSRH"              ,	   0x17F001000001Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	934},
+	{"USBC0_GSNPSID"               ,	   0x16F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
+	{"USBC1_GSNPSID"               ,	   0x17F0010000040ull,	CVMX_CSR_DB_TYPE_NCB,	32,	935},
+	{"USBC0_GUSBCFG"               ,	   0x16F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC1_GUSBCFG"               ,	   0x17F001000000Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	936},
+	{"USBC0_HAINT"                 ,	   0x16F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
+	{"USBC1_HAINT"                 ,	   0x17F0010000414ull,	CVMX_CSR_DB_TYPE_NCB,	32,	937},
+	{"USBC0_HAINTMSK"              ,	   0x16F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	938},
+	{"USBC1_HAINTMSK"              ,	   0x17F0010000418ull,	CVMX_CSR_DB_TYPE_NCB,	32,	938},
+	{"USBC0_HCCHAR000"             ,	   0x16F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR001"             ,	   0x16F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR002"             ,	   0x16F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR003"             ,	   0x16F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR004"             ,	   0x16F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR005"             ,	   0x16F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR006"             ,	   0x16F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCCHAR007"             ,	   0x16F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR000"             ,	   0x17F0010000500ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR001"             ,	   0x17F0010000520ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR002"             ,	   0x17F0010000540ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR003"             ,	   0x17F0010000560ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR004"             ,	   0x17F0010000580ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR005"             ,	   0x17F00100005A0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR006"             ,	   0x17F00100005C0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC1_HCCHAR007"             ,	   0x17F00100005E0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	939},
+	{"USBC0_HCFG"                  ,	   0x16F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	940},
+	{"USBC1_HCFG"                  ,	   0x17F0010000400ull,	CVMX_CSR_DB_TYPE_NCB,	32,	940},
+	{"USBC0_HCINT000"              ,	   0x16F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT001"              ,	   0x16F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT002"              ,	   0x16F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT003"              ,	   0x16F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT004"              ,	   0x16F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT005"              ,	   0x16F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT006"              ,	   0x16F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINT007"              ,	   0x16F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT000"              ,	   0x17F0010000508ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT001"              ,	   0x17F0010000528ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT002"              ,	   0x17F0010000548ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT003"              ,	   0x17F0010000568ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT004"              ,	   0x17F0010000588ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT005"              ,	   0x17F00100005A8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT006"              ,	   0x17F00100005C8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC1_HCINT007"              ,	   0x17F00100005E8ull,	CVMX_CSR_DB_TYPE_NCB,	32,	941},
+	{"USBC0_HCINTMSK000"           ,	   0x16F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK001"           ,	   0x16F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK002"           ,	   0x16F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK003"           ,	   0x16F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK004"           ,	   0x16F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK005"           ,	   0x16F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK006"           ,	   0x16F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCINTMSK007"           ,	   0x16F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK000"           ,	   0x17F001000050Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK001"           ,	   0x17F001000052Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK002"           ,	   0x17F001000054Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK003"           ,	   0x17F001000056Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK004"           ,	   0x17F001000058Cull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK005"           ,	   0x17F00100005ACull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK006"           ,	   0x17F00100005CCull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC1_HCINTMSK007"           ,	   0x17F00100005ECull,	CVMX_CSR_DB_TYPE_NCB,	32,	942},
+	{"USBC0_HCSPLT000"             ,	   0x16F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT001"             ,	   0x16F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT002"             ,	   0x16F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT003"             ,	   0x16F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT004"             ,	   0x16F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT005"             ,	   0x16F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT006"             ,	   0x16F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCSPLT007"             ,	   0x16F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT000"             ,	   0x17F0010000504ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT001"             ,	   0x17F0010000524ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT002"             ,	   0x17F0010000544ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT003"             ,	   0x17F0010000564ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT004"             ,	   0x17F0010000584ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT005"             ,	   0x17F00100005A4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT006"             ,	   0x17F00100005C4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC1_HCSPLT007"             ,	   0x17F00100005E4ull,	CVMX_CSR_DB_TYPE_NCB,	32,	943},
+	{"USBC0_HCTSIZ000"             ,	   0x16F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ001"             ,	   0x16F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ002"             ,	   0x16F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ003"             ,	   0x16F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ004"             ,	   0x16F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ005"             ,	   0x16F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ006"             ,	   0x16F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HCTSIZ007"             ,	   0x16F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ000"             ,	   0x17F0010000510ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ001"             ,	   0x17F0010000530ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ002"             ,	   0x17F0010000550ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ003"             ,	   0x17F0010000570ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ004"             ,	   0x17F0010000590ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ005"             ,	   0x17F00100005B0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ006"             ,	   0x17F00100005D0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC1_HCTSIZ007"             ,	   0x17F00100005F0ull,	CVMX_CSR_DB_TYPE_NCB,	32,	944},
+	{"USBC0_HFIR"                  ,	   0x16F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	945},
+	{"USBC1_HFIR"                  ,	   0x17F0010000404ull,	CVMX_CSR_DB_TYPE_NCB,	32,	945},
+	{"USBC0_HFNUM"                 ,	   0x16F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	946},
+	{"USBC1_HFNUM"                 ,	   0x17F0010000408ull,	CVMX_CSR_DB_TYPE_NCB,	32,	946},
+	{"USBC0_HPRT"                  ,	   0x16F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	947},
+	{"USBC1_HPRT"                  ,	   0x17F0010000440ull,	CVMX_CSR_DB_TYPE_NCB,	32,	947},
+	{"USBC0_HPTXFSIZ"              ,	   0x16F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	948},
+	{"USBC1_HPTXFSIZ"              ,	   0x17F0010000100ull,	CVMX_CSR_DB_TYPE_NCB,	32,	948},
+	{"USBC0_HPTXSTS"               ,	   0x16F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	949},
+	{"USBC1_HPTXSTS"               ,	   0x17F0010000410ull,	CVMX_CSR_DB_TYPE_NCB,	32,	949},
+	{"USBC0_NPTXDFIFO000"          ,	   0x16F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO001"          ,	   0x16F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO002"          ,	   0x16F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO003"          ,	   0x16F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO004"          ,	   0x16F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO005"          ,	   0x16F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO006"          ,	   0x16F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_NPTXDFIFO007"          ,	   0x16F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO000"          ,	   0x17F0010001000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO001"          ,	   0x17F0010002000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO002"          ,	   0x17F0010003000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO003"          ,	   0x17F0010004000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO004"          ,	   0x17F0010005000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO005"          ,	   0x17F0010006000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO006"          ,	   0x17F0010007000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC1_NPTXDFIFO007"          ,	   0x17F0010008000ull,	CVMX_CSR_DB_TYPE_NCB,	32,	950},
+	{"USBC0_PCGCCTL"               ,	   0x16F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	951},
+	{"USBC1_PCGCCTL"               ,	   0x17F0010000E00ull,	CVMX_CSR_DB_TYPE_NCB,	32,	951},
+	{"USBN0_BIST_STATUS"           ,	   0x11800680007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"USBN1_BIST_STATUS"           ,	   0x11800780007F8ull,	CVMX_CSR_DB_TYPE_RSL,	64,	952},
+	{"USBN0_CLK_CTL"               ,	   0x1180068000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"USBN1_CLK_CTL"               ,	   0x1180078000010ull,	CVMX_CSR_DB_TYPE_RSL,	64,	953},
+	{"USBN0_CTL_STATUS"            ,	   0x16F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
+	{"USBN1_CTL_STATUS"            ,	   0x17F0000000800ull,	CVMX_CSR_DB_TYPE_NCB,	64,	954},
+	{"USBN0_DMA0_INB_CHN0"         ,	   0x16F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
+	{"USBN1_DMA0_INB_CHN0"         ,	   0x17F0000000818ull,	CVMX_CSR_DB_TYPE_NCB,	64,	955},
+	{"USBN0_DMA0_INB_CHN1"         ,	   0x16F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
+	{"USBN1_DMA0_INB_CHN1"         ,	   0x17F0000000820ull,	CVMX_CSR_DB_TYPE_NCB,	64,	956},
+	{"USBN0_DMA0_INB_CHN2"         ,	   0x16F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
+	{"USBN1_DMA0_INB_CHN2"         ,	   0x17F0000000828ull,	CVMX_CSR_DB_TYPE_NCB,	64,	957},
+	{"USBN0_DMA0_INB_CHN3"         ,	   0x16F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	958},
+	{"USBN1_DMA0_INB_CHN3"         ,	   0x17F0000000830ull,	CVMX_CSR_DB_TYPE_NCB,	64,	958},
+	{"USBN0_DMA0_INB_CHN4"         ,	   0x16F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	959},
+	{"USBN1_DMA0_INB_CHN4"         ,	   0x17F0000000838ull,	CVMX_CSR_DB_TYPE_NCB,	64,	959},
+	{"USBN0_DMA0_INB_CHN5"         ,	   0x16F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	960},
+	{"USBN1_DMA0_INB_CHN5"         ,	   0x17F0000000840ull,	CVMX_CSR_DB_TYPE_NCB,	64,	960},
+	{"USBN0_DMA0_INB_CHN6"         ,	   0x16F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	961},
+	{"USBN1_DMA0_INB_CHN6"         ,	   0x17F0000000848ull,	CVMX_CSR_DB_TYPE_NCB,	64,	961},
+	{"USBN0_DMA0_INB_CHN7"         ,	   0x16F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	962},
+	{"USBN1_DMA0_INB_CHN7"         ,	   0x17F0000000850ull,	CVMX_CSR_DB_TYPE_NCB,	64,	962},
+	{"USBN0_DMA0_OUTB_CHN0"        ,	   0x16F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	963},
+	{"USBN1_DMA0_OUTB_CHN0"        ,	   0x17F0000000858ull,	CVMX_CSR_DB_TYPE_NCB,	64,	963},
+	{"USBN0_DMA0_OUTB_CHN1"        ,	   0x16F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	964},
+	{"USBN1_DMA0_OUTB_CHN1"        ,	   0x17F0000000860ull,	CVMX_CSR_DB_TYPE_NCB,	64,	964},
+	{"USBN0_DMA0_OUTB_CHN2"        ,	   0x16F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	965},
+	{"USBN1_DMA0_OUTB_CHN2"        ,	   0x17F0000000868ull,	CVMX_CSR_DB_TYPE_NCB,	64,	965},
+	{"USBN0_DMA0_OUTB_CHN3"        ,	   0x16F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	966},
+	{"USBN1_DMA0_OUTB_CHN3"        ,	   0x17F0000000870ull,	CVMX_CSR_DB_TYPE_NCB,	64,	966},
+	{"USBN0_DMA0_OUTB_CHN4"        ,	   0x16F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	967},
+	{"USBN1_DMA0_OUTB_CHN4"        ,	   0x17F0000000878ull,	CVMX_CSR_DB_TYPE_NCB,	64,	967},
+	{"USBN0_DMA0_OUTB_CHN5"        ,	   0x16F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	968},
+	{"USBN1_DMA0_OUTB_CHN5"        ,	   0x17F0000000880ull,	CVMX_CSR_DB_TYPE_NCB,	64,	968},
+	{"USBN0_DMA0_OUTB_CHN6"        ,	   0x16F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	969},
+	{"USBN1_DMA0_OUTB_CHN6"        ,	   0x17F0000000888ull,	CVMX_CSR_DB_TYPE_NCB,	64,	969},
+	{"USBN0_DMA0_OUTB_CHN7"        ,	   0x16F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	970},
+	{"USBN1_DMA0_OUTB_CHN7"        ,	   0x17F0000000890ull,	CVMX_CSR_DB_TYPE_NCB,	64,	970},
+	{"USBN0_DMA_TEST"              ,	   0x16F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	971},
+	{"USBN1_DMA_TEST"              ,	   0x17F0000000808ull,	CVMX_CSR_DB_TYPE_NCB,	64,	971},
+	{"USBN0_INT_ENB"               ,	   0x1180068000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"USBN1_INT_ENB"               ,	   0x1180078000008ull,	CVMX_CSR_DB_TYPE_RSL,	64,	972},
+	{"USBN0_INT_SUM"               ,	   0x1180068000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"USBN1_INT_SUM"               ,	   0x1180078000000ull,	CVMX_CSR_DB_TYPE_RSL,	64,	973},
+	{"USBN0_USBP_CTL_STATUS"       ,	   0x1180068000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{"USBN1_USBP_CTL_STATUS"       ,	   0x1180078000018ull,	CVMX_CSR_DB_TYPE_RSL,	64,	974},
+	{NULL,0,0,0,0}
+};
+static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
+	/* name                        ,	bit,	width,	csr,	type,	rst un,	typ un,	reset,	typical */
+	{"RESERVED_0_1"                ,	0,	2,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OUT_OVR"                     ,	2,	2,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_21"               ,	4,	18,	0,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LOSTSTAT"                    ,	22,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_25"              ,	23,	3,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATOVR"                     ,	26,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_31"              ,	27,	5,	0,	"RAZ",	1,	1,	0,	0},
+	{"OVRFLW"                      ,	32,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP"                       ,	33,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH"                       ,	34,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OVRFLW1"                     ,	35,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPOP1"                      ,	36,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXPSH1"                      ,	37,	1,	0,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	0,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	10,	1,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	1,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"PCTL"                        ,	8,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYP_EN"                      ,	16,	1,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	2,	"RAZ",	1,	1,	0,	0},
+	{"NCTL1"                       ,	32,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"PCTL1"                       ,	40,	5,	2,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	2,	"RAZ",	1,	1,	0,	0},
+	{"BYP_EN1"                     ,	48,	1,	2,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	2,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	1,	1,	3,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	3,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"DUPLEX"                      ,	2,	1,	4,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	4,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_EN"                       ,	4,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"TX_EN"                       ,	5,	1,	4,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	4,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	5,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	6,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	7,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	8,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	9,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	10,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	11,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	11,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	12,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	12,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	12,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	12,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	13,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	13,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_1"                ,	1,	1,	14,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"JABBER"                      ,	3,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"ALNERR"                      ,	5,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR"                      ,	6,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RCVERR"                      ,	7,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	14,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	14,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	7,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	8,	1,	15,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_ALIGN"                   ,	9,	1,	15,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	15,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	16,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_16_63"              ,	16,	48,	16,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	16,	17,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_16_63"              ,	16,	48,	17,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	18,	"R/W",	0,	0,	12ull,	12ull},
+	{"RESERVED_4_63"               ,	4,	60,	18,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"MAXERR"                      ,	2,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	19,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	19,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	19,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	19,	"RAZ",	1,	1,	0,	0},
+	{"MINERR"                      ,	0,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	2,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"JABBER"                      ,	3,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALNERR"                      ,	5,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	6,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCVERR"                      ,	7,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OVRERR"                      ,	10,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	20,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PAUSE_DRP"                   ,	19,	1,	20,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	20,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	21,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	21,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	22,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	22,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	23,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	23,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	24,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	24,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	25,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	25,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	26,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	26,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	27,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	27,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	28,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	28,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	29,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	29,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	30,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	30,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	31,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	31,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	32,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	32,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	33,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	33,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	33,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	34,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	34,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	35,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	35,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	36,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	36,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	2,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_15"               ,	2,	14,	37,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	2,	37,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	37,	"RAZ",	1,	1,	0,	0},
+	{"RX"                          ,	0,	2,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	38,	"RAZ",	1,	1,	0,	0},
+	{"TX"                          ,	4,	2,	38,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	38,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	39,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	39,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	40,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	40,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	40,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	41,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	41,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	42,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	42,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	43,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	43,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	44,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	44,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	45,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	45,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	46,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	46,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	47,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	47,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	48,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	48,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	49,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	50,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	51,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	51,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	52,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	52,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	53,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	54,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	55,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	56,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	57,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	58,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	59,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	59,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	6,	60,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	60,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	2,	61,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	61,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	62,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	62,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	63,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	63,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	63,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	64,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	64,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	64,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	64,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	65,	"RAZ",	1,	1,	0,	0},
+	{"UNDFLW"                      ,	2,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	8,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"XSDEF"                       ,	12,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_15"              ,	14,	2,	65,	"RAZ",	1,	1,	0,	0},
+	{"LATE_COL"                    ,	16,	2,	65,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	65,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	66,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	66,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	67,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	67,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	4,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	68,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	8,	2,	68,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	68,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	69,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	69,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	70,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	70,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	3,	71,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	71,	"RAZ",	1,	1,	0,	0},
+	{"DINT"                        ,	0,	4,	72,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	72,	"RAZ",	1,	1,	0,	0},
+	{"FUSE"                        ,	0,	4,	73,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_63"               ,	4,	60,	73,	"RAZ",	1,	1,	0,	0},
+	{"GSTOP"                       ,	0,	1,	74,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	74,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	75,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	75,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	75,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	76,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	76,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	76,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	76,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	76,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	77,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	77,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	77,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	78,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	78,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	78,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	79,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	79,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	79,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	80,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	80,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	80,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	81,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	81,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	81,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	82,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	82,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	82,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_44"              ,	44,	1,	83,	"RAZ",	1,	1,	0,	0},
+	{"TWSI"                        ,	45,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	83,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	83,	"R/W1",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	84,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	84,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	84,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	85,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	85,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	85,	"RAZ",	1,	1,	0,	0},
+	{"WDOG"                        ,	0,	4,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	86,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	86,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	86,	"RAZ",	1,	1,	0,	0},
+	{"WORKQ"                       ,	0,	16,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	87,	"RAZ",	1,	1,	0,	0},
+	{"IPD_DRP"                     ,	50,	1,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	87,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	87,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	87,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	87,	"RO",	0,	0,	0ull,	0ull},
+	{"WORKQ"                       ,	0,	16,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"GPIO"                        ,	16,	16,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"MBOX"                        ,	32,	2,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"UART"                        ,	34,	2,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_INT"                     ,	36,	4,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"PCI_MSI"                     ,	40,	4,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG_SUM"                    ,	44,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"TWSI"                        ,	45,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"RML"                         ,	46,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"TRACE"                       ,	47,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX_DRP"                     ,	48,	1,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_49"              ,	49,	1,	88,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD_DRP"                     ,	50,	1,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_51_51"              ,	51,	1,	88,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	52,	4,	88,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	56,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_57_58"              ,	57,	2,	88,	"RAZ",	0,	0,	0ull,	0ull},
+	{"TWSI2"                       ,	59,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"POWIQ"                       ,	60,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"IPDPPTHR"                    ,	61,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"MII"                         ,	62,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"BOOTDMA"                     ,	63,	1,	88,	"RO",	0,	0,	0ull,	0ull},
+	{"WDOG"                        ,	0,	4,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	89,	"RAZ",	1,	1,	0,	0},
+	{"UART2"                       ,	16,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	17,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"MII1"                        ,	18,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"NAND"                        ,	19,	1,	89,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	89,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	90,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	90,	"RAZ",	1,	1,	0,	0},
+	{"BITS"                        ,	0,	32,	91,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	91,	"RAZ",	1,	1,	0,	0},
+	{"NMI"                         ,	0,	4,	92,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	92,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	2,	93,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	93,	"RAZ",	1,	1,	0,	0},
+	{"PPDBG"                       ,	0,	4,	94,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	94,	"RAZ",	1,	1,	0,	0},
+	{"POKE"                        ,	0,	64,	95,	"RAZ",	1,	1,	0,	0},
+	{"RST0"                        ,	0,	1,	96,	"R/W",	1,	1,	0,	0},
+	{"RST"                         ,	1,	3,	96,	"R/W",	0,	0,	32767ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	96,	"RAZ",	1,	1,	0,	0},
+	{"QLM_DCOK"                    ,	0,	2,	97,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	97,	"RAZ",	1,	1,	0,	0},
+	{"BYPASS"                      ,	0,	2,	98,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	98,	"RAZ",	1,	1,	0,	0},
+	{"MUX_SEL"                     ,	4,	1,	98,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	98,	"RAZ",	1,	1,	0,	0},
+	{"CLK_DIV"                     ,	8,	3,	98,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	98,	"RAZ",	1,	1,	0,	0},
+	{"SHFT_REG"                    ,	0,	32,	99,	"R/W",	0,	1,	0ull,	0},
+	{"SHFT_CNT"                    ,	32,	5,	99,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	99,	"RAZ",	1,	1,	0,	0},
+	{"SELECT"                      ,	40,	2,	99,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_42_60"              ,	42,	19,	99,	"RAZ",	1,	1,	0,	0},
+	{"UPDATE"                      ,	61,	1,	99,	"R/W",	0,	1,	0ull,	0},
+	{"SHIFT"                       ,	62,	1,	99,	"R/W",	0,	1,	0ull,	0},
+	{"CAPTURE"                     ,	63,	1,	99,	"R/W",	0,	1,	0ull,	0},
+	{"SOFT_BIST"                   ,	0,	1,	100,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	100,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	101,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	101,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_PRST"                   ,	0,	1,	102,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	102,	"RAZ",	1,	1,	0,	0},
+	{"SOFT_RST"                    ,	0,	1,	103,	"WO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	103,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	36,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"ONE_SHOT"                    ,	36,	1,	104,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	104,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	0,	2,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	2,	2,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"LEN"                         ,	4,	16,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT"                         ,	20,	24,	105,	"RO",	0,	0,	0ull,	0ull},
+	{"DSTOP"                       ,	44,	1,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"GSTOPEN"                     ,	45,	1,	105,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_46_63"              ,	46,	18,	105,	"RAZ",	1,	1,	0,	0},
+	{"FDR"                         ,	0,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FFR"                         ,	1,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF1"                        ,	2,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FPF0"                        ,	3,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"FRD"                         ,	4,	1,	106,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	106,	"RAZ",	1,	1,	0,	0},
+	{"MEM0_ERR"                    ,	0,	7,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM1_ERR"                    ,	7,	7,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	14,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_STT"                     ,	15,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"USE_LDT"                     ,	16,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	17,	1,	107,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	107,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	108,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	108,	"RAZ",	1,	1,	0,	0},
+	{"FED0_SBE"                    ,	0,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED0_DBE"                    ,	1,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_SBE"                    ,	2,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FED1_DBE"                    ,	3,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_UND"                      ,	4,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_COFF"                     ,	5,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q0_PERR"                     ,	6,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_UND"                      ,	7,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_COFF"                     ,	8,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q1_PERR"                     ,	9,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_UND"                      ,	10,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_COFF"                     ,	11,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q2_PERR"                     ,	12,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_UND"                      ,	13,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_COFF"                     ,	14,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q3_PERR"                     ,	15,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_UND"                      ,	16,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_COFF"                     ,	17,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q4_PERR"                     ,	18,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_UND"                      ,	19,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_COFF"                     ,	20,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q5_PERR"                     ,	21,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_UND"                      ,	22,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_COFF"                     ,	23,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q6_PERR"                     ,	24,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_UND"                      ,	25,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_COFF"                     ,	26,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"Q7_PERR"                     ,	27,	1,	109,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_63"              ,	28,	36,	109,	"RAZ",	1,	1,	0,	0},
+	{"QUE_SIZ"                     ,	0,	29,	110,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	110,	"RAZ",	1,	1,	0,	0},
+	{"PG_NUM"                      ,	0,	25,	111,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	111,	"RAZ",	1,	1,	0,	0},
+	{"ACT_INDX"                    ,	0,	26,	112,	"RO",	0,	1,	0ull,	0},
+	{"ACT_QUE"                     ,	26,	3,	112,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	112,	"RAZ",	0,	0,	0ull,	7ull},
+	{"EXP_INDX"                    ,	0,	26,	113,	"RO",	0,	1,	0ull,	0},
+	{"EXP_QUE"                     ,	26,	3,	113,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	113,	"RAZ",	0,	0,	0ull,	7ull},
+	{"CTL"                         ,	0,	16,	114,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	114,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	32,	115,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	115,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	116,	"RAZ",	1,	1,	0,	0},
+	{"OUT_OVR"                     ,	2,	4,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_21"               ,	6,	16,	116,	"RAZ",	1,	1,	0,	0},
+	{"LOSTSTAT"                    ,	22,	4,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STATOVR"                     ,	26,	1,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INB_NXA"                     ,	27,	4,	116,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	116,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	117,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	117,	"RAZ",	1,	1,	0,	0},
+	{"CLK_EN"                      ,	0,	1,	118,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	118,	"RAZ",	1,	1,	0,	0},
+	{"LOGL_EN"                     ,	0,	16,	119,	"R/W",	0,	1,	65535ull,	0},
+	{"PHYS_EN"                     ,	16,	1,	119,	"R/W",	0,	1,	1ull,	0},
+	{"HG2RX_EN"                    ,	17,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2TX_EN"                    ,	18,	1,	119,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	119,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	1,	120,	"RO",	0,	1,	0ull,	0},
+	{"EN"                          ,	1,	1,	120,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_3"                ,	2,	2,	120,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	4,	2,	120,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	120,	"RAZ",	1,	1,	0,	0},
+	{"SPEED"                       ,	8,	2,	120,	"RO",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	120,	"RAZ",	1,	1,	0,	0},
+	{"PRT"                         ,	0,	6,	121,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	121,	"RAZ",	1,	1,	0,	0},
+	{"RX_EN"                       ,	0,	1,	122,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_EN"                       ,	1,	1,	122,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRP_EN"                      ,	2,	1,	122,	"R/W",	0,	0,	0ull,	0ull},
+	{"BCK_EN"                      ,	3,	1,	122,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	122,	"RAZ",	1,	1,	0,	0},
+	{"PHYS_BP"                     ,	16,	16,	122,	"R/W",	0,	1,	65535ull,	0},
+	{"LOGL_EN"                     ,	32,	16,	122,	"R/W",	0,	0,	255ull,	255ull},
+	{"PHYS_EN"                     ,	48,	16,	122,	"R/W",	0,	0,	255ull,	255ull},
+	{"EN"                          ,	0,	1,	123,	"R/W",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	1,	1,	123,	"R/W",	0,	1,	1ull,	0},
+	{"DUPLEX"                      ,	2,	1,	123,	"R/W",	0,	1,	1ull,	0},
+	{"SLOTTIME"                    ,	3,	1,	123,	"R/W",	0,	1,	1ull,	0},
+	{"RESERVED_4_7"                ,	4,	4,	123,	"RAZ",	1,	1,	0,	0},
+	{"SPEED_MSB"                   ,	8,	1,	123,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	123,	"RAZ",	1,	1,	0,	0},
+	{"RX_IDLE"                     ,	12,	1,	123,	"RO",	0,	1,	1ull,	0},
+	{"TX_IDLE"                     ,	13,	1,	123,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_14_63"              ,	14,	50,	123,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	64,	124,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	125,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	126,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	127,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	128,	"R/W",	0,	1,	0ull,	0},
+	{"ADR"                         ,	0,	64,	129,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	0,	8,	130,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	130,	"RAZ",	1,	1,	0,	0},
+	{"BCST"                        ,	0,	1,	131,	"R/W",	0,	1,	1ull,	0},
+	{"MCST"                        ,	1,	2,	131,	"R/W",	0,	1,	0ull,	0},
+	{"CAM_MODE"                    ,	3,	1,	131,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	131,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	5,	132,	"R/W",	0,	0,	24ull,	24ull},
+	{"RESERVED_5_63"               ,	5,	59,	132,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	133,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	133,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_2"                ,	2,	1,	133,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	133,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCSERR"                      ,	4,	1,	133,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_6"                ,	5,	2,	133,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	133,	"R/W",	0,	0,	1ull,	1ull},
+	{"SKPERR"                      ,	8,	1,	133,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	133,	"RAZ",	1,	1,	0,	0},
+	{"PRE_CHK"                     ,	0,	1,	134,	"R/W",	0,	0,	1ull,	1ull},
+	{"PRE_STRP"                    ,	1,	1,	134,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_DRP"                     ,	2,	1,	134,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_BCK"                     ,	3,	1,	134,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_MCST"                    ,	4,	1,	134,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTL_SMAC"                    ,	5,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRE_FREE"                    ,	6,	1,	134,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_8"                ,	7,	2,	134,	"RAZ",	1,	1,	0,	0},
+	{"PRE_ALIGN"                   ,	9,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"NULL_DIS"                    ,	10,	1,	134,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	134,	"RAZ",	1,	1,	0,	0},
+	{"IFG"                         ,	0,	4,	135,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_4_63"               ,	4,	60,	135,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	136,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	136,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	136,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	136,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	136,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	136,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	136,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	137,	"RAZ",	1,	1,	0,	0},
+	{"CAREXT"                      ,	1,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	137,	"RAZ",	1,	1,	0,	0},
+	{"JABBER"                      ,	3,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCSERR"                      ,	4,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	137,	"RAZ",	1,	1,	0,	0},
+	{"RCVERR"                      ,	7,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPERR"                      ,	8,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	137,	"RAZ",	1,	1,	0,	0},
+	{"OVRERR"                      ,	10,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCTERR"                      ,	11,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RSVERR"                      ,	12,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FALERR"                      ,	13,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"COLDET"                      ,	14,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IFGERR"                      ,	15,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	137,	"RAZ",	1,	1,	0,	0},
+	{"PAUSE_DRP"                   ,	19,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LOC_FAULT"                   ,	20,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"REM_FAULT"                   ,	21,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_SEQ"                     ,	22,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAD_TERM"                    ,	23,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNSOP"                       ,	24,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNEOP"                       ,	25,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UNDAT"                       ,	26,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2FLD"                      ,	27,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HG2CC"                       ,	28,	1,	137,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	137,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	138,	"R/W",	0,	0,	10240ull,	10240ull},
+	{"RESERVED_16_63"              ,	16,	48,	138,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	16,	139,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	139,	"RAZ",	1,	1,	0,	0},
+	{"RD_CLR"                      ,	0,	1,	140,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	140,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	141,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	141,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	142,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	142,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	143,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	143,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	48,	144,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	144,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	145,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	145,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	146,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	146,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	147,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	147,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	148,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	148,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	149,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	149,	"RAZ",	1,	1,	0,	0},
+	{"LEN"                         ,	0,	7,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	150,	"RAZ",	1,	1,	0,	0},
+	{"FCSSEL"                      ,	8,	1,	150,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	150,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	151,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_6_63"               ,	6,	58,	151,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	6,	152,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_6_63"               ,	6,	58,	152,	"RAZ",	1,	1,	0,	0},
+	{"MARK"                        ,	0,	9,	153,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_9_63"               ,	9,	55,	153,	"RAZ",	1,	1,	0,	0},
+	{"LGTIM2GO"                    ,	0,	16,	154,	"RO",	0,	1,	0ull,	0},
+	{"XOF"                         ,	16,	16,	154,	"RO",	0,	0,	0ull,	0ull},
+	{"PHTIM2GO"                    ,	32,	16,	154,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	154,	"RAZ",	1,	1,	0,	0},
+	{"COMMIT"                      ,	0,	4,	155,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	155,	"RAZ",	1,	1,	0,	0},
+	{"DROP"                        ,	16,	4,	155,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	155,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	3,	156,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_3_63"               ,	3,	61,	156,	"RAZ",	1,	1,	0,	0},
+	{"LANE_RXD"                    ,	0,	32,	157,	"RO",	0,	1,	0ull,	0},
+	{"LANE_RXC"                    ,	32,	4,	157,	"RO",	0,	1,	0ull,	0},
+	{"STATE"                       ,	36,	3,	157,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	39,	1,	157,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	157,	"RAZ",	1,	1,	0,	0},
+	{"STATUS"                      ,	0,	2,	158,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	158,	"RAZ",	1,	1,	0,	0},
+	{"SMAC"                        ,	0,	48,	159,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	159,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	16,	160,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	16,	1,	160,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_63"              ,	17,	47,	160,	"RAZ",	1,	1,	0,	0},
+	{"PREAMBLE"                    ,	0,	1,	161,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAD"                         ,	1,	1,	161,	"R/W",	0,	0,	1ull,	1ull},
+	{"FCS"                         ,	2,	1,	161,	"R/W",	0,	0,	1ull,	1ull},
+	{"FORCE_FCS"                   ,	3,	1,	161,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_63"               ,	4,	60,	161,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	16,	162,	"R/W",	0,	0,	8192ull,	8192ull},
+	{"RESERVED_16_63"              ,	16,	48,	162,	"RAZ",	1,	1,	0,	0},
+	{"XOFF"                        ,	0,	16,	163,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	163,	"RAZ",	1,	1,	0,	0},
+	{"XON"                         ,	0,	16,	164,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	164,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL_EN"                    ,	0,	1,	165,	"R/W",	0,	0,	1ull,	1ull},
+	{"XSDEF_EN"                    ,	1,	1,	165,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	165,	"RAZ",	1,	1,	0,	0},
+	{"MIN_SIZE"                    ,	0,	8,	166,	"R/W",	0,	0,	59ull,	59ull},
+	{"RESERVED_8_63"               ,	8,	56,	166,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	16,	167,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	167,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	168,	"R/W",	0,	1,	96ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	168,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	169,	"RO",	1,	1,	0,	0},
+	{"MSG_TIME"                    ,	16,	16,	169,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	169,	"RAZ",	1,	1,	0,	0},
+	{"SEND"                        ,	0,	1,	170,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	170,	"RAZ",	1,	1,	0,	0},
+	{"ALIGN"                       ,	0,	1,	171,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	171,	"RAZ",	1,	1,	0,	0},
+	{"SLOT"                        ,	0,	10,	172,	"R/W",	0,	0,	512ull,	512ull},
+	{"RESERVED_10_63"              ,	10,	54,	172,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	16,	173,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	173,	"RAZ",	1,	1,	0,	0},
+	{"XSCOL"                       ,	0,	32,	174,	"RC/W",	0,	1,	0ull,	0},
+	{"XSDEF"                       ,	32,	32,	174,	"RC/W",	0,	1,	0ull,	0},
+	{"MCOL"                        ,	0,	32,	175,	"RC/W",	0,	1,	0ull,	0},
+	{"SCOL"                        ,	32,	32,	175,	"RC/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	176,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	176,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	177,	"RC/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	177,	"RAZ",	1,	1,	0,	0},
+	{"HIST0"                       ,	0,	32,	178,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST1"                       ,	32,	32,	178,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST2"                       ,	0,	32,	179,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST3"                       ,	32,	32,	179,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST4"                       ,	0,	32,	180,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST5"                       ,	32,	32,	180,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST6"                       ,	0,	32,	181,	"RC/W",	0,	1,	0ull,	0},
+	{"HIST7"                       ,	32,	32,	181,	"RC/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	0,	32,	182,	"RC/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	32,	32,	182,	"RC/W",	0,	1,	0ull,	0},
+	{"CTL"                         ,	0,	32,	183,	"RC/W",	0,	1,	0ull,	0},
+	{"UNDFLW"                      ,	32,	32,	183,	"RC/W",	0,	1,	0ull,	0},
+	{"RD_CLR"                      ,	0,	1,	184,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	184,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	9,	185,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_9_63"               ,	9,	55,	185,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	4,	186,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	186,	"RAZ",	1,	1,	0,	0},
+	{"LIMIT"                       ,	0,	5,	187,	"R/W",	0,	0,	16ull,	16ull},
+	{"RESERVED_5_63"               ,	5,	59,	187,	"RAZ",	1,	1,	0,	0},
+	{"CORRUPT"                     ,	0,	4,	188,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_4_63"               ,	4,	60,	188,	"RAZ",	1,	1,	0,	0},
+	{"TX_XOF"                      ,	0,	16,	189,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	189,	"RAZ",	1,	1,	0,	0},
+	{"TX_XON"                      ,	0,	16,	190,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	190,	"RAZ",	1,	1,	0,	0},
+	{"IFG1"                        ,	0,	4,	191,	"R/W",	0,	1,	8ull,	0},
+	{"IFG2"                        ,	4,	4,	191,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	191,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	192,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	192,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	192,	"RAZ",	1,	1,	0,	0},
+	{"PKO_NXA"                     ,	0,	1,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UNDFLW"                      ,	2,	4,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	193,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XSCOL"                       ,	8,	4,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XSDEF"                       ,	12,	4,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LATE_COL"                    ,	16,	4,	193,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	193,	"RAZ",	1,	1,	0,	0},
+	{"JAM"                         ,	0,	8,	194,	"R/W",	0,	1,	238ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	194,	"RAZ",	1,	1,	0,	0},
+	{"LFSR"                        ,	0,	16,	195,	"R/W",	0,	1,	65535ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	195,	"RAZ",	1,	1,	0,	0},
+	{"IGN_FULL"                    ,	0,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP"                          ,	4,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"EN"                          ,	8,	4,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	196,	"RAZ",	1,	1,	0,	0},
+	{"TX_PRT_BP"                   ,	32,	16,	196,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	196,	"RAZ",	1,	1,	0,	0},
+	{"DMAC"                        ,	0,	48,	197,	"R/W",	0,	0,	1652522221569ull,	1652522221569ull},
+	{"RESERVED_48_63"              ,	48,	16,	197,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	198,	"R/W",	0,	0,	34824ull,	34824ull},
+	{"RESERVED_16_63"              ,	16,	48,	198,	"RAZ",	1,	1,	0,	0},
+	{"PRTS"                        ,	0,	5,	199,	"R/W",	0,	1,	4ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	199,	"RAZ",	1,	1,	0,	0},
+	{"DIC_EN"                      ,	0,	1,	200,	"R/W",	0,	0,	0ull,	1ull},
+	{"UNI_EN"                      ,	1,	1,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_3"                ,	2,	2,	200,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	4,	2,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"LS_BYP"                      ,	6,	1,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	200,	"RAZ",	1,	1,	0,	0},
+	{"HG_EN"                       ,	8,	1,	200,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_PAUSE_HGI"                ,	9,	2,	200,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_11_63"              ,	11,	53,	200,	"RAZ",	1,	1,	0,	0},
+	{"THRESH"                      ,	0,	4,	201,	"R/W",	0,	0,	6ull,	6ull},
+	{"EN"                          ,	4,	1,	201,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	201,	"RAZ",	1,	1,	0,	0},
+	{"TX_OE"                       ,	0,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RX_XOR"                      ,	1,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_EN"                      ,	2,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"INT_TYPE"                    ,	3,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_CNT"                     ,	4,	4,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIL_SEL"                     ,	8,	4,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_SEL"                     ,	12,	2,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLK_GEN"                     ,	14,	1,	202,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	202,	"RAZ",	1,	1,	0,	0},
+	{"N"                           ,	0,	32,	203,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	203,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	16,	204,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	204,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	205,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	205,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	16,	206,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	206,	"RAZ",	1,	1,	0,	0},
+	{"SET"                         ,	0,	16,	207,	"R/W1",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	207,	"RAZ",	1,	1,	0,	0},
+	{"ICD"                         ,	0,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBD"                         ,	1,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP1"                       ,	2,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRP0"                       ,	3,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN1"                       ,	4,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICRN0"                       ,	5,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ1"                       ,	6,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBRQ0"                       ,	7,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRT"                       ,	8,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR1"                        ,	9,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBR0"                        ,	10,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR1"                       ,	11,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"IBDR0"                       ,	12,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR0"                       ,	13,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNR1"                       ,	14,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR1"                        ,	15,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICR0"                        ,	16,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"ICNRCB"                      ,	17,	1,	208,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	208,	"RAZ",	1,	1,	0,	0},
+	{"FAU_END"                     ,	0,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB_ENB"                     ,	1,	1,	209,	"R/W",	0,	0,	1ull,	1ull},
+	{"PKO_ENB"                     ,	2,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"INB_MAT"                     ,	3,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTB_MAT"                    ,	4,	1,	209,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RR_MODE"                     ,	5,	1,	209,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	209,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	210,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	210,	"RAZ",	1,	1,	0,	0},
+	{"TOUT_VAL"                    ,	0,	12,	211,	"R/W",	0,	0,	4ull,	4ull},
+	{"TOUT_ENB"                    ,	12,	1,	211,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	211,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	212,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	212,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	212,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	213,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	213,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	213,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	213,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	213,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	8,	214,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	8,	9,	214,	"R/W",	0,	1,	0ull,	0},
+	{"OPC"                         ,	17,	4,	214,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	21,	8,	214,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	214,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	215,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	216,	"R/W",	0,	1,	0ull,	0},
+	{"NP_SOP"                      ,	0,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	217,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	217,	"RAZ",	1,	1,	0,	0},
+	{"NP_SOP"                      ,	0,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_EOP"                      ,	1,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_SOP"                       ,	2,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_EOP"                       ,	3,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NP_DAT"                      ,	4,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P_DAT"                       ,	5,	1,	218,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	218,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	219,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	219,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	220,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	220,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	221,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	221,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	222,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	222,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	222,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	222,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	222,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	9,	223,	"R/W",	0,	1,	0ull,	0},
+	{"DST"                         ,	9,	8,	223,	"R/W",	0,	1,	0ull,	0},
+	{"EOT"                         ,	17,	1,	223,	"R/W",	0,	1,	0ull,	0},
+	{"MASK"                        ,	18,	8,	223,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_26_63"              ,	26,	38,	223,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	224,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	225,	"R/W",	0,	1,	0ull,	0},
+	{"CNT_VAL"                     ,	0,	15,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	226,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	226,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	227,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	227,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	15,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT_ENB"                     ,	15,	1,	228,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	228,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	6,	229,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	229,	"RAZ",	1,	1,	0,	0},
+	{"NCB_WR"                      ,	0,	3,	230,	"R/W",	0,	1,	0ull,	0},
+	{"NCB_RD"                      ,	3,	3,	230,	"R/W",	0,	1,	0ull,	0},
+	{"PKO_RD"                      ,	6,	3,	230,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_63"               ,	9,	55,	230,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	231,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	231,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	232,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	232,	"RAZ",	1,	1,	0,	0},
+	{"BACK"                        ,	0,	4,	233,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	233,	"RAZ",	1,	1,	0,	0},
+	{"PWP"                         ,	0,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_NEW"                     ,	1,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_OLD"                     ,	2,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PRC_OFF"                     ,	3,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ0"                        ,	4,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ1"                        ,	5,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM_WORD"                    ,	6,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM0"                        ,	7,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM1"                        ,	8,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM2"                        ,	9,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PBM3"                        ,	10,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE0"                    ,	11,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"IPQ_PBE1"                    ,	12,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_POW"                     ,	13,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WP1"                     ,	14,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"PWQ_WQED"                    ,	15,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_NCMD"                    ,	16,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"CSR_MEM"                     ,	17,	1,	234,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	234,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	40,	235,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	235,	"RAZ",	1,	1,	0,	0},
+	{"CLK_CNT"                     ,	0,	64,	236,	"RO",	0,	0,	0ull,	0ull},
+	{"IPD_EN"                      ,	0,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"OPC_MODE"                    ,	1,	2,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"PBP_EN"                      ,	3,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"WQE_LEND"                    ,	4,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_LEND"                    ,	5,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"NADDBUF"                     ,	6,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDPKT"                      ,	7,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	8,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"LEN_M8"                      ,	9,	1,	237,	"R/W",	0,	0,	0ull,	1ull},
+	{"PKT_OFF"                     ,	10,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"IPD_FULL"                    ,	11,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_NABUF"                    ,	12,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_APKT"                     ,	13,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"NO_WPTR"                     ,	14,	1,	237,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	237,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	238,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	238,	"RAZ",	1,	1,	0,	0},
+	{"PRC_PAR0"                    ,	0,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR1"                    ,	1,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR2"                    ,	2,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRC_PAR3"                    ,	3,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BP_SUB"                      ,	4,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DC_OVR"                      ,	5,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CC_OVR"                      ,	6,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C_COLL"                      ,	7,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"D_COLL"                      ,	8,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BC_OVR"                      ,	9,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_ADD"                      ,	10,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PQ_SUB"                      ,	11,	1,	239,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	239,	"RAZ",	1,	1,	0,	0},
+	{"SKIP_SZ"                     ,	0,	6,	240,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	240,	"RAZ",	1,	1,	0,	0},
+	{"MB_SIZE"                     ,	0,	12,	241,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_12_63"              ,	12,	52,	241,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	242,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	242,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	243,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	243,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	17,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"BP_ENB"                      ,	17,	1,	244,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	244,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	245,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	245,	"RAZ",	1,	1,	0,	0},
+	{"CNT_VAL"                     ,	0,	25,	246,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_25_63"              ,	25,	39,	246,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	247,	"RO",	0,	1,	0ull,	0},
+	{"WMARK"                       ,	32,	32,	247,	"R/W",	0,	1,	4294967295ull,	0},
+	{"INTR"                        ,	0,	64,	248,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	64,	249,	"R/W",	0,	0,	0ull,	1ull},
+	{"RADDR"                       ,	0,	3,	250,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	3,	1,	250,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	4,	29,	250,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	33,	3,	250,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	36,	3,	250,	"RO",	0,	0,	5ull,	5ull},
+	{"RESERVED_39_63"              ,	39,	25,	250,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	7,	251,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	7,	1,	251,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	8,	29,	251,	"RO",	1,	1,	0,	0},
+	{"MAX_PKT"                     ,	37,	7,	251,	"RO",	0,	0,	12ull,	12ull},
+	{"RESERVED_44_63"              ,	44,	20,	251,	"RAZ",	1,	1,	0,	0},
+	{"WQE_PCNT"                    ,	0,	7,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PCNT"                    ,	7,	7,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"PFIF_CNT"                    ,	14,	3,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"WQEV_CNT"                    ,	17,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTV_CNT"                    ,	18,	1,	252,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	252,	"RAZ",	1,	1,	0,	0},
+	{"RADDR"                       ,	0,	8,	253,	"R/W",	0,	0,	0ull,	0ull},
+	{"CENA"                        ,	8,	1,	253,	"R/W",	0,	0,	1ull,	1ull},
+	{"PTR"                         ,	9,	29,	253,	"RO",	1,	1,	0,	0},
+	{"PRADDR"                      ,	38,	8,	253,	"RO",	1,	1,	0,	0},
+	{"WRADDR"                      ,	46,	8,	253,	"RO",	1,	1,	0,	0},
+	{"MAX_CNTS"                    ,	54,	7,	253,	"RO",	0,	0,	8ull,	8ull},
+	{"RESERVED_61_63"              ,	61,	3,	253,	"RAZ",	1,	1,	0,	0},
+	{"PASS"                        ,	0,	32,	254,	"R/W",	0,	1,	0ull,	0},
+	{"DROP"                        ,	32,	32,	254,	"R/W",	0,	1,	0ull,	0},
+	{"Q0_PCNT"                     ,	0,	32,	255,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	255,	"RAZ",	1,	1,	0,	0},
+	{"PRT_ENB"                     ,	0,	36,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"AVG_DLY"                     ,	36,	14,	256,	"R/W",	0,	1,	0ull,	0},
+	{"PRB_DLY"                     ,	50,	14,	256,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRT_ENB"                     ,	0,	4,	257,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	257,	"RAZ",	1,	1,	0,	0},
+	{"PRB_CON"                     ,	0,	32,	258,	"R/W",	0,	1,	0ull,	0},
+	{"AVG_CON"                     ,	32,	8,	258,	"R/W",	0,	1,	0ull,	0},
+	{"NEW_CON"                     ,	40,	8,	258,	"R/W",	0,	1,	0ull,	0},
+	{"USE_PCNT"                    ,	48,	1,	258,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	258,	"RAZ",	1,	1,	0,	0},
+	{"PAGE_CNT"                    ,	0,	25,	259,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	25,	6,	259,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	259,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT"                    ,	0,	32,	260,	"R/W",	0,	0,	4294967295ull,	4294967295ull},
+	{"RESERVED_32_35"              ,	32,	4,	260,	"RAZ",	1,	1,	0,	0},
+	{"PORT_BIT2"                   ,	36,	4,	260,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_40_63"              ,	40,	24,	260,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	261,	"R/W",	1,	0,	0,	0ull},
+	{"PORT_QOS"                    ,	32,	9,	261,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_41_63"              ,	41,	23,	261,	"RAZ",	1,	1,	0,	0},
+	{"WQE_POOL"                    ,	0,	3,	262,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_3_63"               ,	3,	61,	262,	"RAZ",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	29,	263,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	263,	"RAZ",	1,	1,	0,	0},
+	{"WLB_DAT"                     ,	0,	4,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"STIN_MSK"                    ,	4,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"DT"                          ,	5,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"DTCNT"                       ,	6,	10,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_18"              ,	16,	3,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WLB_MSK"                     ,	19,	4,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"DTBNK"                       ,	23,	1,	264,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	264,	"RAZ",	0,	0,	0ull,	0ull},
+	{"L2T"                         ,	0,	9,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"VAB_VWCF"                    ,	9,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"ILC"                         ,	10,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_11"              ,	11,	1,	265,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VWDF"                        ,	12,	4,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC0"                        ,	16,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC1"                        ,	17,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"PLC2"                        ,	18,	1,	265,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	265,	"RAZ",	0,	0,	0ull,	0ull},
+	{"XRDDAT"                      ,	0,	1,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"XRDMSK"                      ,	1,	1,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPCBST"                      ,	3,	1,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RMDF"                        ,	8,	4,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"MRB"                         ,	12,	4,	266,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	266,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LRF_ARB_MODE"                ,	0,	1,	267,	"R/W",	0,	0,	1ull,	1ull},
+	{"RFB_ARB_MODE"                ,	1,	1,	267,	"R/W",	0,	0,	1ull,	1ull},
+	{"RSP_ARB_MODE"                ,	2,	1,	267,	"R/W",	0,	0,	1ull,	1ull},
+	{"MWF_CRD"                     ,	3,	4,	267,	"R/W",	0,	0,	2ull,	2ull},
+	{"IDXALIAS"                    ,	7,	1,	267,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPEN"                        ,	8,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEMPTY"                     ,	9,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"FPEXP"                       ,	10,	4,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_17"              ,	14,	4,	267,	"RAZ",	1,	1,	0,	0},
+	{"LBIST"                       ,	18,	1,	267,	"R/W",	0,	0,	0ull,	0ull},
+	{"BSTRUN"                      ,	19,	1,	267,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	267,	"RAZ",	1,	1,	0,	0},
+	{"L2T"                         ,	0,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2D"                         ,	1,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"FINV"                        ,	2,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	3,	3,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"PPNUM"                       ,	6,	2,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_9"                ,	8,	2,	268,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_DMP"                     ,	10,	1,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"LFB_ENUM"                    ,	11,	3,	268,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	268,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DT_TAG"                      ,	0,	29,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"DT_VLD"                      ,	29,	1,	269,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_30"              ,	30,	1,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DTENA"                       ,	31,	1,	269,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	269,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PLC0RMSK"                    ,	0,	32,	270,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC1RMSK"                    ,	32,	32,	270,	"R/W",	0,	0,	0ull,	0ull},
+	{"PLC2RMSK"                    ,	0,	32,	271,	"R/W",	0,	0,	0ull,	0ull},
+	{"ILCRMSK"                     ,	32,	32,	271,	"R/W",	0,	0,	0ull,	0ull},
+	{"OOB1EN"                      ,	0,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB2EN"                      ,	1,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"OOB3EN"                      ,	2,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TSECEN"                    ,	3,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2TDEDEN"                    ,	4,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DSECEN"                    ,	5,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"L2DDEDEN"                    ,	6,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKENA"                      ,	7,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCK2ENA"                     ,	8,	1,	272,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_63"               ,	9,	55,	272,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OOB1"                        ,	0,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB2"                        ,	1,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OOB3"                        ,	2,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TSEC"                      ,	3,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2TDED"                      ,	4,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DSEC"                      ,	5,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2DDED"                      ,	6,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK"                         ,	7,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK2"                        ,	8,	1,	273,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	273,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_ENA"                     ,	0,	1,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_3"                ,	1,	3,	274,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_BASE"                    ,	4,	27,	274,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	274,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LCK_OFFSET"                  ,	0,	10,	275,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	275,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	1,	4,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"SID"                         ,	5,	9,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"VABNUM"                      ,	14,	3,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_17"              ,	17,	1,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	18,	3,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"IHD"                         ,	21,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"ITL"                         ,	22,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"INXT"                        ,	23,	3,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VAM"                         ,	27,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"STCFL"                       ,	28,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"STINV"                       ,	29,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"STPND"                       ,	30,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"STCPND"                      ,	31,	1,	276,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	276,	"RAZ",	0,	0,	0ull,	0ull},
+	{"VLD"                         ,	0,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTPRB"                       ,	1,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"PRBRTY"                      ,	2,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTMFL"                       ,	3,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTVTM"                       ,	4,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSC"                     ,	5,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTRSP"                     ,	6,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTDT"                      ,	7,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRDA"                       ,	8,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTSTM"                       ,	9,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWRM"                       ,	10,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHF"                       ,	11,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTWHP"                       ,	12,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDQ"                        ,	13,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTDW"                        ,	14,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"WTRSP"                       ,	15,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"BID"                         ,	16,	2,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"DSGOING"                     ,	18,	1,	277,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	277,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_IDX"                     ,	0,	9,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"LFB_TAG"                     ,	9,	18,	278,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	278,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LFB_HWM"                     ,	0,	3,	279,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_3_3"                ,	3,	1,	279,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STPARTDIS"                   ,	4,	1,	279,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_63"               ,	5,	59,	279,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STENA"                       ,	0,	1,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWBENA"                      ,	1,	1,	280,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	280,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	281,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	281,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	281,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	281,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	282,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	282,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	282,	"RO",	0,	0,	0ull,	0ull},
+	{"SIZE"                        ,	0,	14,	283,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_19"              ,	14,	6,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SADR"                        ,	20,	14,	283,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_35"              ,	34,	2,	283,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSRC"                        ,	36,	1,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	37,	27,	283,	"RO",	0,	0,	0ull,	0ull},
+	{"PFCNT0"                      ,	0,	36,	284,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	284,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CNT0SEL"                     ,	0,	6,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0CLR"                     ,	6,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0ENA"                     ,	7,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1SEL"                     ,	8,	6,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1CLR"                     ,	14,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1ENA"                     ,	15,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2SEL"                     ,	16,	6,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2CLR"                     ,	22,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2ENA"                     ,	23,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3SEL"                     ,	24,	6,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3CLR"                     ,	30,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3ENA"                     ,	31,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT0RDCLR"                   ,	32,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT1RDCLR"                   ,	33,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT2RDCLR"                   ,	34,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNT3RDCLR"                   ,	35,	1,	285,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	285,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP0GRP"                      ,	0,	2,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP1GRP"                      ,	2,	2,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP2GRP"                      ,	4,	2,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"PP3GRP"                      ,	6,	2,	286,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	286,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSK0"                       ,	0,	8,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK1"                       ,	8,	8,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK2"                       ,	16,	8,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSK3"                       ,	24,	8,	287,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	287,	"RAZ",	0,	0,	0ull,	0ull},
+	{"UMSKIOB"                     ,	0,	8,	288,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	288,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0STAT"                      ,	0,	34,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"FTL"                         ,	34,	1,	289,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	289,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1STAT"                      ,	0,	34,	290,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	290,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2STAT"                      ,	0,	34,	291,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	291,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3STAT"                      ,	0,	34,	292,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	292,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	293,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	293,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	293,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BMHCLSEL"                    ,	5,	1,	293,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	293,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	0,	10,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	294,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	11,	3,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"FOWMSK"                      ,	14,	4,	294,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	294,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW0"                    ,	0,	10,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW1"                    ,	10,	10,	295,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	295,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSYN_OW2"                    ,	0,	10,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"FSYN_OW3"                    ,	10,	10,	296,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	296,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q0FUS"                       ,	0,	34,	297,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	297,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q1FUS"                       ,	0,	34,	298,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	298,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q2FUS"                       ,	0,	34,	299,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_34_63"              ,	34,	30,	299,	"RAZ",	0,	0,	0ull,	0ull},
+	{"Q3FUS"                       ,	0,	34,	300,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_256K"                   ,	34,	1,	300,	"RO",	0,	0,	0ull,	0ull},
+	{"CRIP_128K"                   ,	35,	1,	300,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_36"              ,	36,	1,	300,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EMA_CTL"                     ,	37,	3,	300,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	300,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	0,	1,	301,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_INTENA"                  ,	1,	1,	301,	"R/W",	0,	0,	0ull,	1ull},
+	{"DED_INTENA"                  ,	2,	1,	301,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	3,	1,	301,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	4,	1,	301,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FSYN"                        ,	5,	6,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"FADR"                        ,	11,	9,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	301,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FSET"                        ,	21,	3,	301,	"RO",	0,	0,	0ull,	0ull},
+	{"LCKERR"                      ,	24,	1,	301,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA"                  ,	25,	1,	301,	"R/W",	0,	0,	0ull,	1ull},
+	{"LCKERR2"                     ,	26,	1,	301,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LCK_INTENA2"                 ,	27,	1,	301,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_28_63"              ,	28,	36,	301,	"RAZ",	0,	0,	0ull,	0ull},
+	{"START"                       ,	0,	1,	302,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	302,	"RAZ",	1,	0,	0,	0ull},
+	{"MRD"                         ,	0,	3,	303,	"RO",	1,	0,	0,	0ull},
+	{"MRF"                         ,	3,	1,	303,	"RO",	1,	0,	0,	0ull},
+	{"MWC"                         ,	4,	1,	303,	"RO",	1,	0,	0,	0ull},
+	{"MWD"                         ,	5,	3,	303,	"RO",	1,	0,	0,	0ull},
+	{"MWF"                         ,	8,	1,	303,	"RO",	1,	0,	0,	0ull},
+	{"CSRE2D"                      ,	9,	1,	303,	"RO",	1,	0,	0,	0ull},
+	{"CSRD2E"                      ,	10,	1,	303,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_11_63"              ,	11,	53,	303,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL_DAT"                    ,	0,	5,	304,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_11"               ,	5,	7,	304,	"RAZ",	0,	1,	0ull,	0},
+	{"PCTL_CSR"                    ,	12,	4,	304,	"R/W",	0,	1,	15ull,	0},
+	{"NCTL_DAT"                    ,	16,	4,	304,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_27"              ,	20,	8,	304,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL_CSR"                    ,	28,	4,	304,	"R/W",	0,	1,	15ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	304,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DIC"                         ,	0,	2,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"QS_DIC"                      ,	2,	2,	305,	"R/W",	0,	0,	2ull,	2ull},
+	{"TSKW"                        ,	4,	2,	305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SIL_LAT"                     ,	6,	2,	305,	"R/W",	0,	0,	1ull,	1ull},
+	{"BPRCH"                       ,	8,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"FPRCH2"                      ,	9,	1,	305,	"R/W",	0,	0,	0ull,	1ull},
+	{"MODE32B"                     ,	10,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	11,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MRF"                 ,	12,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"INORDER_MWF"                 ,	13,	1,	305,	"RAZ",	0,	0,	0ull,	0ull},
+	{"R2R_SLOT"                    ,	14,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDIMM_ENA"                   ,	15,	1,	305,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_17"              ,	16,	2,	305,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MAX_WRITE_BATCH"             ,	18,	4,	305,	"R/W",	0,	0,	8ull,	8ull},
+	{"XOR_BANK"                    ,	22,	1,	305,	"R/W",	0,	0,	0ull,	1ull},
+	{"SLOW_SCF"                    ,	23,	1,	305,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR__PCTL"                   ,	24,	4,	305,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	28,	4,	305,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	305,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	306,	"RAZ",	0,	1,	0ull,	0},
+	{"DCC_ENABLE"                  ,	8,	1,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIL_MODE"                    ,	9,	1,	306,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEQUENCE"                    ,	10,	3,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDLEPOWER"                   ,	13,	3,	306,	"R/W",	0,	0,	0ull,	6ull},
+	{"FORCEWRITE"                  ,	16,	4,	306,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECC_ADR"                     ,	20,	1,	306,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_21_63"              ,	21,	43,	306,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_HI"                  ,	0,	32,	307,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	307,	"RAZ",	1,	1,	0,	0},
+	{"DCLKCNT_LO"                  ,	0,	32,	308,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	308,	"RAZ",	1,	1,	0,	0},
+	{"DDR2"                        ,	0,	1,	309,	"R/W",	0,	0,	1ull,	1ull},
+	{"RDQS"                        ,	1,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	2,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	3,	5,	309,	"R/W",	0,	1,	0ull,	0},
+	{"QDLL_ENA"                    ,	8,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODT_ENA"                     ,	9,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"DDR2T"                       ,	10,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"CRIP_MODE"                   ,	11,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"TFAW"                        ,	12,	5,	309,	"R/W",	0,	0,	0ull,	9ull},
+	{"DDR_EOF"                     ,	17,	4,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"SILO_HC"                     ,	21,	1,	309,	"R/W",	0,	1,	1ull,	0},
+	{"TWR"                         ,	22,	3,	309,	"R/W",	0,	0,	3ull,	1ull},
+	{"BWCNT"                       ,	25,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"POCAS"                       ,	26,	1,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDLAT"                      ,	27,	3,	309,	"R/W",	0,	0,	0ull,	0ull},
+	{"BURST8"                      ,	30,	1,	309,	"R/W",	0,	0,	0ull,	1ull},
+	{"BANK8"                       ,	31,	1,	309,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	309,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CLK"                         ,	0,	4,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CMD"                         ,	5,	4,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DQ"                          ,	10,	4,	310,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	310,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DLL90_VLU"                   ,	0,	5,	311,	"R/W",	0,	1,	0ull,	0},
+	{"DLL90_ENA"                   ,	5,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLL90_BYP"                   ,	6,	1,	311,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRESET"                      ,	7,	1,	311,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	311,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	312,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_15"               ,	8,	8,	312,	"RAZ",	0,	1,	0ull,	0},
+	{"ROW_LSB"                     ,	16,	3,	312,	"R/W",	0,	1,	3ull,	0},
+	{"BANK8"                       ,	19,	1,	312,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_63"              ,	20,	44,	312,	"RAZ",	0,	1,	0ull,	0},
+	{"MRDSYN0"                     ,	0,	8,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN1"                     ,	8,	8,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN2"                     ,	16,	8,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"MRDSYN3"                     ,	24,	8,	313,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	313,	"RAZ",	1,	1,	0,	0},
+	{"FCOL"                        ,	0,	12,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"FROW"                        ,	12,	14,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"FBANK"                       ,	26,	3,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"FBUNK"                       ,	29,	1,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"FDIMM"                       ,	30,	2,	314,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	314,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_HI"                   ,	0,	32,	315,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	315,	"RAZ",	1,	1,	0,	0},
+	{"IFBCNT_LO"                   ,	0,	32,	316,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	316,	"RAZ",	1,	1,	0,	0},
+	{"INIT_START"                  ,	0,	1,	317,	"WR0",	0,	0,	0ull,	0ull},
+	{"ECC_ENA"                     ,	1,	1,	317,	"R/W",	0,	0,	0ull,	1ull},
+	{"ROW_LSB"                     ,	2,	3,	317,	"R/W",	0,	1,	3ull,	0},
+	{"PBANK_LSB"                   ,	5,	4,	317,	"R/W",	0,	1,	5ull,	0},
+	{"REF_INT"                     ,	9,	6,	317,	"R/W",	0,	0,	1ull,	2ull},
+	{"TCL"                         ,	15,	4,	317,	"R/W",	0,	1,	3ull,	0},
+	{"INTR_SEC_ENA"                ,	19,	1,	317,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTR_DED_ENA"                ,	20,	1,	317,	"R/W",	0,	0,	0ull,	1ull},
+	{"SEC_ERR"                     ,	21,	4,	317,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DED_ERR"                     ,	25,	4,	317,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BUNK_ENA"                    ,	29,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"SILO_QC"                     ,	30,	1,	317,	"R/W",	0,	1,	0ull,	0},
+	{"RESET"                       ,	31,	1,	317,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	317,	"RAZ",	1,	1,	0,	0},
+	{"TRAS"                        ,	0,	5,	318,	"R/W",	0,	0,	12ull,	12ull},
+	{"TRCD"                        ,	5,	4,	318,	"R/W",	0,	0,	4ull,	4ull},
+	{"TWTR"                        ,	9,	4,	318,	"R/W",	0,	0,	2ull,	2ull},
+	{"TRP"                         ,	13,	4,	318,	"R/W",	0,	0,	5ull,	4ull},
+	{"TRFC"                        ,	17,	5,	318,	"R/W",	0,	0,	6ull,	7ull},
+	{"TMRD"                        ,	22,	3,	318,	"R/W",	0,	0,	2ull,	2ull},
+	{"CASLAT"                      ,	25,	3,	318,	"R/W",	0,	0,	4ull,	4ull},
+	{"TRRD"                        ,	28,	3,	318,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_31_63"              ,	31,	33,	318,	"RAZ",	1,	1,	0,	0},
+	{"CS_MASK"                     ,	0,	8,	319,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	319,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_HI"                   ,	0,	32,	320,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	320,	"RAZ",	1,	1,	0,	0},
+	{"OPSCNT_LO"                   ,	0,	32,	321,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	321,	"RAZ",	1,	1,	0,	0},
+	{"EN2"                         ,	0,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"EN4"                         ,	1,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"EN6"                         ,	2,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"EN8"                         ,	3,	1,	322,	"R/W",	0,	1,	1ull,	0},
+	{"EN12"                        ,	4,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"EN16"                        ,	5,	1,	322,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	322,	"RAZ",	0,	1,	0ull,	0},
+	{"CLKR"                        ,	8,	6,	322,	"R/W",	0,	1,	0ull,	0},
+	{"CLKF"                        ,	14,	12,	322,	"R/W",	0,	1,	31ull,	0},
+	{"RESET_N"                     ,	26,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"DIV_RESET"                   ,	27,	1,	322,	"R/W",	0,	0,	1ull,	0ull},
+	{"FASTEN_N"                    ,	28,	1,	322,	"R/W",	0,	0,	0ull,	1ull},
+	{"BYPASS"                      ,	29,	1,	322,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_63"              ,	30,	34,	322,	"RAZ",	0,	1,	0ull,	0},
+	{"FBSLIP"                      ,	0,	1,	323,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	323,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_21"               ,	2,	20,	323,	"RAZ",	1,	1,	0,	0},
+	{"DDR__PCTL"                   ,	22,	5,	323,	"RO",	1,	1,	0,	0},
+	{"DDR__NCTL"                   ,	27,	5,	323,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	323,	"RAZ",	1,	1,	0,	0},
+	{"BNK"                         ,	0,	3,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	324,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COL"                         ,	4,	12,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROW"                         ,	16,	16,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"PATTERN"                     ,	32,	8,	324,	"R/W",	0,	0,	170ull,	170ull},
+	{"RANKMASK"                    ,	40,	4,	324,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_44_63"              ,	44,	20,	324,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE"                        ,	0,	4,	325,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_15"               ,	4,	12,	325,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BITMASK"                     ,	16,	16,	325,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	325,	"RAZ",	0,	0,	0ull,	0ull},
+	{"BYTE0"                       ,	0,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE1"                       ,	4,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE2"                       ,	8,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE3"                       ,	12,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE4"                       ,	16,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE5"                       ,	20,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE6"                       ,	24,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE7"                       ,	28,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"BYTE8"                       ,	32,	4,	326,	"R/W",	0,	1,	0ull,	0},
+	{"STATUS"                      ,	36,	2,	326,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_38_63"              ,	38,	26,	326,	"RAZ",	1,	0,	0,	0ull},
+	{"PCTL"                        ,	0,	5,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	327,	"RAZ",	0,	1,	0ull,	0},
+	{"NCTL"                        ,	8,	4,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_12_15"              ,	12,	4,	327,	"RAZ",	0,	1,	0ull,	0},
+	{"ENABLE"                      ,	16,	1,	327,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_17_63"              ,	17,	47,	327,	"RAZ",	0,	1,	0ull,	0},
+	{"RODT_LO0"                    ,	0,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO1"                    ,	4,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO2"                    ,	8,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_LO3"                    ,	12,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI0"                    ,	16,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI1"                    ,	20,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI2"                    ,	24,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RODT_HI3"                    ,	28,	4,	328,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_32_63"              ,	32,	32,	328,	"RAZ",	1,	1,	0,	0},
+	{"WODT_D0_R0"                  ,	0,	8,	329,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D0_R1"                  ,	8,	8,	329,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R0"                  ,	16,	8,	329,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D1_R1"                  ,	24,	8,	329,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	329,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WODT_D2_R0"                  ,	0,	8,	330,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D2_R1"                  ,	8,	8,	330,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R0"                  ,	16,	8,	330,	"R/W",	0,	0,	255ull,	255ull},
+	{"WODT_D3_R1"                  ,	24,	8,	330,	"R/W",	0,	0,	255ull,	255ull},
+	{"RESERVED_32_63"              ,	32,	32,	330,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NCBI"                        ,	0,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"LOC"                         ,	1,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA"                         ,	2,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"NCBO_0"                      ,	3,	1,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"NDF"                         ,	4,	2,	331,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	331,	"RAZ",	1,	1,	0,	0},
+	{"NCTL"                        ,	0,	5,	332,	"R/W",	1,	1,	0,	0},
+	{"PCTL"                        ,	5,	5,	332,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_10_63"              ,	10,	54,	332,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	333,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	333,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	333,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	333,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	334,	"R/W1C",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	334,	"RO",	1,	1,	0,	0},
+	{"RESERVED_2_63"               ,	2,	62,	334,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	335,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ"                       ,	1,	1,	335,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	335,	"RAZ",	1,	1,	0,	0},
+	{"DMARQ"                       ,	0,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_S"                     ,	6,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"OE_A"                        ,	12,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"OE_N"                        ,	18,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"WE_A"                        ,	24,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"WE_N"                        ,	30,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"DMACK_H"                     ,	36,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	42,	6,	336,	"R/W",	0,	1,	63ull,	0},
+	{"RESERVED_48_54"              ,	48,	7,	336,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	55,	1,	336,	"R/W",	0,	1,	0ull,	0},
+	{"DDR"                         ,	56,	1,	336,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	57,	3,	336,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	60,	2,	336,	"R/W",	0,	1,	0ull,	0},
+	{"DMARQ_PI"                    ,	62,	1,	336,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK_PI"                    ,	63,	1,	336,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_ERR"                     ,	0,	1,	337,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WAIT_ERR"                    ,	1,	1,	337,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	337,	"RAZ",	1,	1,	0,	0},
+	{"ADR_INT"                     ,	0,	1,	338,	"R/W",	0,	1,	0ull,	0},
+	{"WAIT_INT"                    ,	1,	1,	338,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	338,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	339,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	3,	5,	339,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	339,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	340,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	3,	25,	340,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_30"              ,	28,	3,	340,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	31,	1,	340,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	340,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	64,	341,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	342,	"RAZ",	1,	1,	0,	0},
+	{"NAND"                        ,	8,	1,	342,	"RO",	1,	1,	0,	0},
+	{"TERM"                        ,	9,	2,	342,	"RO",	1,	1,	0,	0},
+	{"DMACK_P0"                    ,	11,	1,	342,	"RO",	1,	1,	0,	0},
+	{"DMACK_P1"                    ,	12,	1,	342,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_13"              ,	13,	1,	342,	"RAZ",	1,	1,	0,	0},
+	{"WIDTH"                       ,	14,	1,	342,	"RO",	1,	1,	0,	0},
+	{"ALE"                         ,	15,	1,	342,	"RO",	1,	1,	0,	0},
+	{"RESERVED_16_63"              ,	16,	48,	342,	"RAZ",	1,	1,	0,	0},
+	{"BASE"                        ,	0,	16,	343,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	16,	12,	343,	"R/W",	0,	1,	0ull,	0},
+	{"WIDTH"                       ,	28,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ALE"                         ,	29,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"ORBIT"                       ,	30,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	31,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"OE_EXT"                      ,	32,	2,	343,	"R/W",	0,	1,	0ull,	0},
+	{"WE_EXT"                      ,	34,	2,	343,	"R/W",	0,	1,	0ull,	0},
+	{"SAM"                         ,	36,	1,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RD_DLY"                      ,	37,	3,	343,	"R/W",	0,	1,	0ull,	0},
+	{"TIM_MULT"                    ,	40,	2,	343,	"R/W",	0,	1,	0ull,	0},
+	{"DMACK"                       ,	42,	2,	343,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	343,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"CE"                          ,	6,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"OE"                          ,	12,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"WE"                          ,	18,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"RD_HLD"                      ,	24,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"WR_HLD"                      ,	30,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"PAUSE"                       ,	36,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"WAIT"                        ,	42,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"PAGE"                        ,	48,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"ALE"                         ,	54,	6,	344,	"R/W",	0,	1,	63ull,	0},
+	{"PAGES"                       ,	60,	2,	344,	"R/W",	0,	1,	0ull,	0},
+	{"WAITM"                       ,	62,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"PAGEM"                       ,	63,	1,	344,	"R/W",	0,	1,	0ull,	0},
+	{"FIF_THR"                     ,	0,	6,	345,	"R/W",	0,	0,	25ull,	25ull},
+	{"RESERVED_6_7"                ,	6,	2,	345,	"RAZ",	1,	1,	0,	0},
+	{"FIF_CNT"                     ,	8,	6,	345,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	345,	"RAZ",	1,	1,	0,	0},
+	{"DMA_THR"                     ,	16,	6,	345,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_63"              ,	22,	42,	345,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	64,	346,	"R/W",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	347,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	347,	"RAZ",	1,	1,	0,	0},
+	{"MAN_INFO"                    ,	0,	32,	348,	"RO",	1,	1,	0,	0},
+	{"RESERVED_32_63"              ,	32,	32,	348,	"RAZ",	1,	1,	0,	0},
+	{"PP_DIS"                      ,	0,	4,	349,	"RO",	1,	1,	0,	0},
+	{"RESERVED_4_15"               ,	4,	12,	349,	"RO",	1,	1,	0,	0},
+	{"CHIP_ID"                     ,	16,	8,	349,	"RO",	1,	1,	0,	0},
+	{"BIST_DIS"                    ,	24,	1,	349,	"RO",	1,	1,	0,	0},
+	{"RST_SHT"                     ,	25,	1,	349,	"RO",	1,	1,	0,	0},
+	{"NOCRYPTO"                    ,	26,	1,	349,	"RO",	1,	1,	0,	0},
+	{"NOMUL"                       ,	27,	1,	349,	"RO",	1,	1,	0,	0},
+	{"NODFA_CP2"                   ,	28,	1,	349,	"RO",	1,	1,	0,	0},
+	{"NOKASU"                      ,	29,	1,	349,	"RO",	1,	1,	0,	0},
+	{"RESERVED_30_31"              ,	30,	2,	349,	"RAZ",	1,	1,	0,	0},
+	{"RAID_EN"                     ,	32,	1,	349,	"RO",	1,	1,	0,	0},
+	{"FUS318"                      ,	33,	1,	349,	"RO",	1,	1,	0,	0},
+	{"RESERVED_34_63"              ,	34,	30,	349,	"RAZ",	1,	1,	0,	0},
+	{"ICACHE"                      ,	0,	24,	350,	"RO",	1,	1,	0,	0},
+	{"NODFA_DTE"                   ,	24,	1,	350,	"RO",	1,	1,	0,	0},
+	{"NOZIP"                       ,	25,	1,	350,	"RO",	1,	1,	0,	0},
+	{"EFUS_IGN"                    ,	26,	1,	350,	"RO",	1,	1,	0,	0},
+	{"EFUS_LCK"                    ,	27,	1,	350,	"RO",	1,	1,	0,	0},
+	{"BAR2_EN"                     ,	28,	1,	350,	"RO",	1,	1,	0,	0},
+	{"ZIP_CRIP"                    ,	29,	2,	350,	"RO",	1,	1,	0,	0},
+	{"RESERVED_31_63"              ,	31,	33,	350,	"RAZ",	1,	1,	0,	0},
+	{"EMA"                         ,	0,	3,	351,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	351,	"RAZ",	1,	1,	0,	0},
+	{"EFF_EMA"                     ,	4,	3,	351,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	351,	"RAZ",	1,	1,	0,	0},
+	{"PDF"                         ,	0,	64,	352,	"RO",	1,	1,	0,	0},
+	{"FBSLIP"                      ,	0,	1,	353,	"R/W1C",	0,	1,	0ull,	0},
+	{"RFSLIP"                      ,	1,	1,	353,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	353,	"RAZ",	1,	1,	0,	0},
+	{"PROG"                        ,	0,	1,	354,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_1_63"               ,	1,	63,	354,	"RAZ",	1,	1,	0,	0},
+	{"SETUP"                       ,	0,	8,	355,	"R/W",	0,	1,	3ull,	0},
+	{"SCLK_HI"                     ,	8,	12,	355,	"R/W",	0,	1,	100ull,	0},
+	{"SCLK_LO"                     ,	20,	4,	355,	"R/W",	0,	1,	2ull,	0},
+	{"OUT"                         ,	24,	8,	355,	"R/W",	0,	1,	3ull,	0},
+	{"PROG_PIN"                    ,	32,	1,	355,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_33_63"              ,	33,	31,	355,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	8,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"EFUSE"                       ,	8,	1,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	356,	"RAZ",	1,	1,	0,	0},
+	{"PEND"                        ,	12,	1,	356,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	356,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	16,	8,	356,	"RO",	1,	1,	0,	0},
+	{"RESERVED_24_63"              ,	24,	40,	356,	"RAZ",	1,	1,	0,	0},
+	{"REPAIR0"                     ,	0,	14,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR1"                     ,	14,	14,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"REPAIR2"                     ,	28,	14,	357,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	357,	"RAZ",	1,	1,	0,	0},
+	{"TOO_MANY"                    ,	0,	1,	358,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	358,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	3,	359,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_3_63"               ,	3,	61,	359,	"RAZ",	1,	1,	0,	0},
+	{"ADR"                         ,	0,	36,	360,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	36,	20,	360,	"R/W",	0,	1,	0ull,	0},
+	{"ENDIAN"                      ,	56,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP8"                       ,	57,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP16"                      ,	58,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"SWAP32"                      ,	59,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_60"              ,	60,	1,	360,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	61,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"RW"                          ,	62,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"EN"                          ,	63,	1,	360,	"R/W",	0,	1,	0ull,	0},
+	{"DONE"                        ,	0,	1,	361,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	361,	"RAZ",	1,	1,	0,	0},
+	{"DONE"                        ,	0,	1,	362,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	362,	"RAZ",	1,	1,	0,	0},
+	{"ST_INT"                      ,	0,	1,	363,	"R/W1C",	0,	1,	0ull,	0},
+	{"TS_INT"                      ,	1,	1,	363,	"R/W1C",	0,	1,	0ull,	0},
+	{"CORE_INT"                    ,	2,	1,	363,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	363,	"RAZ",	1,	1,	0,	0},
+	{"ST_EN"                       ,	4,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"TS_EN"                       ,	5,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"CORE_EN"                     ,	6,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_7"                ,	7,	1,	363,	"RAZ",	1,	1,	0,	0},
+	{"SDA_OVR"                     ,	8,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"SCL_OVR"                     ,	9,	1,	363,	"R/W",	0,	1,	0ull,	0},
+	{"SDA"                         ,	10,	1,	363,	"RO",	1,	1,	0,	0},
+	{"SCL"                         ,	11,	1,	363,	"RO",	1,	1,	0,	0},
+	{"RESERVED_12_63"              ,	12,	52,	363,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	364,	"R/W",	0,	1,	0ull,	0},
+	{"EOP_IA"                      ,	32,	3,	364,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	35,	5,	364,	"R/W",	0,	1,	0ull,	0},
+	{"A"                           ,	40,	10,	364,	"R/W",	0,	1,	0ull,	0},
+	{"SCR"                         ,	50,	2,	364,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	52,	3,	364,	"R/W",	0,	1,	0ull,	0},
+	{"SOVR"                        ,	55,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"R"                           ,	56,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"OP"                          ,	57,	4,	364,	"R/W",	0,	1,	0ull,	0},
+	{"EIA"                         ,	61,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"SLONLY"                      ,	62,	1,	364,	"R/W",	0,	1,	0ull,	0},
+	{"V"                           ,	63,	1,	364,	"RC/W",	0,	1,	0ull,	0},
+	{"D"                           ,	0,	32,	365,	"R/W",	0,	1,	0ull,	0},
+	{"IA"                          ,	32,	8,	365,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	365,	"RAZ",	1,	1,	0,	0},
+	{"D"                           ,	0,	32,	366,	"R/W",	1,	1,	0,	0},
+	{"RESERVED_32_61"              ,	32,	30,	366,	"RAZ",	1,	1,	0,	0},
+	{"V"                           ,	62,	2,	366,	"RC/W",	0,	1,	0ull,	0},
+	{"DLH"                         ,	0,	8,	367,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	367,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	368,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	368,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	369,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	369,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	370,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	370,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	370,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	370,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	370,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	370,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	370,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	371,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	371,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	372,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	372,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	372,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	372,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	372,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	372,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	372,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	373,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	373,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	373,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	373,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	374,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	374,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	374,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	374,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	374,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	374,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	374,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	374,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	375,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	375,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	375,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	375,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	375,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	375,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	375,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	375,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	375,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	376,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	376,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	377,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	377,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	377,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	377,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	377,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	377,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	377,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	377,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	377,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	378,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	378,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	379,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	379,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	380,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	380,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	380,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	380,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	381,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	381,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	382,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	382,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	383,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	383,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	384,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	384,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	384,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	384,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	385,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	385,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	386,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	386,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	387,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	387,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	388,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	388,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	389,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	389,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	390,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	390,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	391,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	391,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	391,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	391,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	391,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	391,	"RAZ",	1,	1,	0,	0},
+	{"DLH"                         ,	0,	8,	392,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	392,	"RAZ",	1,	1,	0,	0},
+	{"DLL"                         ,	0,	8,	393,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	393,	"RAZ",	1,	1,	0,	0},
+	{"FAR"                         ,	0,	1,	394,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	394,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	395,	"WO",	0,	1,	0ull,	0},
+	{"RXFR"                        ,	1,	1,	395,	"WO",	0,	1,	0ull,	0},
+	{"TXFR"                        ,	2,	1,	395,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_3"                ,	3,	1,	395,	"RAZ",	0,	1,	0ull,	0},
+	{"TXTRIG"                      ,	4,	2,	395,	"WO",	0,	1,	0ull,	0},
+	{"RXTRIG"                      ,	6,	2,	395,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	395,	"RAZ",	1,	1,	0,	0},
+	{"HTX"                         ,	0,	1,	396,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	396,	"RAZ",	1,	1,	0,	0},
+	{"ERBFI"                       ,	0,	1,	397,	"R/W",	0,	1,	0ull,	0},
+	{"ETBEI"                       ,	1,	1,	397,	"R/W",	0,	1,	0ull,	0},
+	{"ELSI"                        ,	2,	1,	397,	"R/W",	0,	1,	0ull,	0},
+	{"EDSSI"                       ,	3,	1,	397,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_6"                ,	4,	3,	397,	"RAZ",	0,	1,	0ull,	0},
+	{"PTIME"                       ,	7,	1,	397,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	397,	"RAZ",	1,	1,	0,	0},
+	{"IID"                         ,	0,	4,	398,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_4_5"                ,	4,	2,	398,	"RAZ",	0,	1,	0ull,	0},
+	{"FEN"                         ,	6,	2,	398,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	398,	"RAZ",	1,	1,	0,	0},
+	{"CLS"                         ,	0,	2,	399,	"R/W",	0,	1,	0ull,	0},
+	{"STOP"                        ,	2,	1,	399,	"R/W",	0,	1,	0ull,	0},
+	{"PEN"                         ,	3,	1,	399,	"R/W",	0,	1,	0ull,	0},
+	{"EPS"                         ,	4,	1,	399,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_5"                ,	5,	1,	399,	"RAZ",	0,	1,	0ull,	0},
+	{"BRK"                         ,	6,	1,	399,	"R/W",	0,	1,	0ull,	0},
+	{"DLAB"                        ,	7,	1,	399,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	399,	"RAZ",	1,	1,	0,	0},
+	{"DR"                          ,	0,	1,	400,	"RO",	0,	1,	0ull,	0},
+	{"OE"                          ,	1,	1,	400,	"RC",	0,	1,	0ull,	0},
+	{"PE"                          ,	2,	1,	400,	"RC",	0,	1,	0ull,	0},
+	{"FE"                          ,	3,	1,	400,	"RC",	0,	1,	0ull,	0},
+	{"BI"                          ,	4,	1,	400,	"RC",	0,	1,	0ull,	0},
+	{"THRE"                        ,	5,	1,	400,	"RO",	0,	1,	1ull,	0},
+	{"TEMT"                        ,	6,	1,	400,	"RO",	0,	1,	1ull,	0},
+	{"FERR"                        ,	7,	1,	400,	"RC",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	400,	"RAZ",	1,	1,	0,	0},
+	{"DTR"                         ,	0,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RTS"                         ,	1,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"OUT1"                        ,	2,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"OUT2"                        ,	3,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"LOOP"                        ,	4,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"AFCE"                        ,	5,	1,	401,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_63"               ,	6,	58,	401,	"RAZ",	0,	1,	0ull,	0},
+	{"DCTS"                        ,	0,	1,	402,	"RC",	0,	1,	0ull,	0},
+	{"DDSR"                        ,	1,	1,	402,	"RC",	0,	1,	0ull,	0},
+	{"TERI"                        ,	2,	1,	402,	"RC",	0,	1,	0ull,	0},
+	{"DDCD"                        ,	3,	1,	402,	"RC",	0,	1,	0ull,	0},
+	{"CTS"                         ,	4,	1,	402,	"RO",	1,	1,	0,	0},
+	{"DSR"                         ,	5,	1,	402,	"RO",	0,	1,	0ull,	0},
+	{"RI"                          ,	6,	1,	402,	"RO",	0,	1,	0ull,	0},
+	{"DCD"                         ,	7,	1,	402,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	402,	"RAZ",	1,	1,	0,	0},
+	{"RBR"                         ,	0,	8,	403,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	403,	"RAZ",	1,	1,	0,	0},
+	{"RFL"                         ,	0,	7,	404,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	404,	"RAZ",	1,	1,	0,	0},
+	{"RFWD"                        ,	0,	8,	405,	"WO",	0,	1,	0ull,	0},
+	{"RFPE"                        ,	8,	1,	405,	"WO",	0,	1,	0ull,	0},
+	{"RFFE"                        ,	9,	1,	405,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	405,	"RAZ",	1,	1,	0,	0},
+	{"SBCR"                        ,	0,	1,	406,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	406,	"RAZ",	1,	1,	0,	0},
+	{"SCR"                         ,	0,	8,	407,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	407,	"RAZ",	1,	1,	0,	0},
+	{"SFE"                         ,	0,	1,	408,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	408,	"RAZ",	1,	1,	0,	0},
+	{"USR"                         ,	0,	1,	409,	"WO",	0,	1,	0ull,	0},
+	{"SRFR"                        ,	1,	1,	409,	"WO",	0,	1,	0ull,	0},
+	{"STFR"                        ,	2,	1,	409,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_3_63"               ,	3,	61,	409,	"RAZ",	1,	1,	0,	0},
+	{"SRT"                         ,	0,	2,	410,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	410,	"RAZ",	1,	1,	0,	0},
+	{"SRTS"                        ,	0,	1,	411,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_1_63"               ,	1,	63,	411,	"RAZ",	1,	1,	0,	0},
+	{"STT"                         ,	0,	2,	412,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_2_63"               ,	2,	62,	412,	"RAZ",	1,	1,	0,	0},
+	{"TFL"                         ,	0,	7,	413,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	413,	"RAZ",	1,	1,	0,	0},
+	{"TFR"                         ,	0,	8,	414,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	414,	"RAZ",	1,	1,	0,	0},
+	{"THR"                         ,	0,	8,	415,	"WO",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	415,	"RAZ",	1,	1,	0,	0},
+	{"BUSY"                        ,	0,	1,	416,	"RO",	0,	1,	0ull,	0},
+	{"TFNF"                        ,	1,	1,	416,	"RO",	0,	1,	1ull,	0},
+	{"TFE"                         ,	2,	1,	416,	"RO",	0,	1,	1ull,	0},
+	{"RFNE"                        ,	3,	1,	416,	"RO",	0,	1,	0ull,	0},
+	{"RFF"                         ,	4,	1,	416,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_5_63"               ,	5,	59,	416,	"RAZ",	1,	1,	0,	0},
+	{"ORFDAT"                      ,	0,	1,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"IRFDAT"                      ,	1,	1,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"IPFDAT"                      ,	2,	1,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"MRQDAT"                      ,	3,	1,	417,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	417,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MRQ_HWM"                     ,	0,	2,	418,	"R/W",	0,	0,	1ull,	1ull},
+	{"NBTARB"                      ,	2,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENDIAN"                     ,	3,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	4,	1,	418,	"R/W",	0,	0,	1ull,	0ull},
+	{"EN"                          ,	5,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"BUSY"                        ,	6,	1,	418,	"RO",	0,	0,	0ull,	0ull},
+	{"CRC_STRIP"                   ,	7,	1,	418,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	418,	"RAZ",	1,	1,	0,	0},
+	{"OVFENA"                      ,	0,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IVFENA"                      ,	1,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTHENA"                      ,	2,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"ITHENA"                      ,	3,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_DRPENA"                 ,	4,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"IRUNENA"                     ,	5,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"ORUNENA"                     ,	6,	1,	419,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	419,	"RAZ",	1,	1,	0,	0},
+	{"IRCNT"                       ,	0,	20,	420,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	420,	"RAZ",	1,	1,	0,	0},
+	{"IRHWM"                       ,	0,	20,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"IBPLWM"                      ,	20,	20,	421,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	421,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	422,	"RAZ",	1,	1,	0,	0},
+	{"IBASE"                       ,	3,	33,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	422,	"RAZ",	1,	1,	0,	0},
+	{"ISIZE"                       ,	40,	20,	422,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	422,	"RAZ",	1,	1,	0,	0},
+	{"IDBELL"                      ,	0,	20,	423,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	423,	"RAZ",	1,	1,	0,	0},
+	{"ITLPTR"                      ,	32,	20,	423,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	423,	"RAZ",	1,	1,	0,	0},
+	{"ODBLOVF"                     ,	0,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IDBLOVF"                     ,	1,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORTHRESH"                    ,	2,	1,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"IRTHRESH"                    ,	3,	1,	424,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_DRP"                    ,	4,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IRUN"                        ,	5,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ORUN"                        ,	6,	1,	424,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	424,	"RAZ",	1,	1,	0,	0},
+	{"ORCNT"                       ,	0,	20,	425,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	425,	"RAZ",	1,	1,	0,	0},
+	{"ORHWM"                       ,	0,	20,	426,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	426,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_2"                ,	0,	3,	427,	"RAZ",	1,	1,	0,	0},
+	{"OBASE"                       ,	3,	33,	427,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_39"              ,	36,	4,	427,	"RAZ",	1,	1,	0,	0},
+	{"OSIZE"                       ,	40,	20,	427,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	427,	"RAZ",	1,	1,	0,	0},
+	{"ODBELL"                      ,	0,	20,	428,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_20_31"              ,	20,	12,	428,	"RAZ",	1,	1,	0,	0},
+	{"OTLPTR"                      ,	32,	20,	428,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_52_63"              ,	52,	12,	428,	"RAZ",	1,	1,	0,	0},
+	{"OREMCNT"                     ,	0,	20,	429,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	429,	"RAZ",	1,	1,	0,	0},
+	{"IREMCNT"                     ,	32,	20,	429,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_52_63"              ,	52,	12,	429,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	3,	430,	"R/W",	0,	1,	0ull,	0},
+	{"ADR_CYC"                     ,	3,	4,	430,	"R/W",	0,	1,	8ull,	0},
+	{"T_MULT"                      ,	7,	4,	430,	"R/W",	0,	1,	9ull,	0},
+	{"RESERVED_11_63"              ,	11,	53,	430,	"RAZ",	1,	1,	0,	0},
+	{"NF_CMD"                      ,	0,	64,	431,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	8,	432,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	432,	"RAZ",	1,	1,	0,	0},
+	{"ECC_ERR"                     ,	0,	8,	433,	"RO",	0,	1,	0ull,	0},
+	{"XOR_ECC"                     ,	8,	24,	433,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	433,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	434,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	434,	"RAZ",	1,	1,	0,	0},
+	{"EMPTY"                       ,	0,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"FULL"                        ,	1,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"WDOG"                        ,	2,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"SM_BAD"                      ,	3,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_1BIT"                    ,	4,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"ECC_MULT"                    ,	5,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"OVRF"                        ,	6,	1,	435,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	435,	"RAZ",	1,	1,	0,	0},
+	{"RST_FF"                      ,	0,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"EX_DIS"                      ,	1,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"BT_DIS"                      ,	2,	1,	436,	"R/W",	0,	0,	0ull,	1ull},
+	{"BT_DMA"                      ,	3,	1,	436,	"R/W",	0,	1,	0ull,	0},
+	{"RD_CMD"                      ,	4,	1,	436,	"R/W",	0,	0,	0ull,	0ull},
+	{"RD_VAL"                      ,	5,	1,	436,	"RO",	0,	1,	0ull,	0},
+	{"RD_DONE"                     ,	6,	1,	436,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FR_BYT"                      ,	7,	11,	436,	"RO",	0,	1,	0ull,	0},
+	{"WAIT_CNT"                    ,	18,	6,	436,	"R/W",	0,	1,	20ull,	0},
+	{"NBR_HWM"                     ,	24,	3,	436,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_27_63"              ,	27,	37,	436,	"RAZ",	1,	1,	0,	0},
+	{"MAIN_SM"                     ,	0,	3,	437,	"RO",	0,	1,	0ull,	0},
+	{"MAIN_BAD"                    ,	3,	1,	437,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF"                       ,	4,	2,	437,	"RO",	0,	1,	0ull,	0},
+	{"RD_FF_BAD"                   ,	6,	1,	437,	"RO",	0,	1,	0ull,	0},
+	{"BT_SM"                       ,	7,	4,	437,	"RO",	0,	1,	0ull,	0},
+	{"EXE_SM"                      ,	11,	4,	437,	"RO",	0,	1,	0ull,	0},
+	{"EXE_IDLE"                    ,	15,	1,	437,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	437,	"RAZ",	1,	1,	0,	0},
+	{"ADDR_V"                      ,	0,	1,	438,	"R/W",	0,	1,	0ull,	0},
+	{"END_SWP"                     ,	1,	2,	438,	"R/W",	0,	1,	0ull,	0},
+	{"CA"                          ,	3,	1,	438,	"R/W",	0,	0,	0ull,	0ull},
+	{"ADDR_IDX"                    ,	4,	14,	438,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_31"              ,	18,	14,	438,	"RAZ",	1,	1,	0,	0},
+	{"NCB_CMD"                     ,	0,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"MSI"                         ,	1,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF4"                        ,	2,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF3"                        ,	3,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF2"                        ,	4,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF1"                        ,	5,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"DIF0"                        ,	6,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM1"                        ,	7,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"CSM0"                        ,	8,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P1"                     ,	9,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_P0"                     ,	10,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_N"                      ,	11,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C1"                     ,	12,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_C0"                     ,	13,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P1"                     ,	14,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_P0"                     ,	15,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_N"                      ,	16,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C1"                     ,	17,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_C0"                     ,	18,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_CO"                     ,	19,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_NO"                     ,	20,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N0_PO"                     ,	21,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_CO"                     ,	22,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_NO"                     ,	23,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"P2N1_PO"                     ,	24,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P1"                      ,	25,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"CPL_P0"                      ,	26,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_O"                      ,	27,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P1_C"                      ,	28,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_O"                      ,	29,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"N2P0_C"                      ,	30,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D4_PST"                      ,	31,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_PST"                      ,	32,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_PST"                      ,	33,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_PST"                      ,	34,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_PST"                      ,	35,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_39"              ,	36,	4,	439,	"RAZ",	1,	1,	0,	0},
+	{"DS_MEM"                      ,	40,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D4_MEM"                      ,	41,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D3_MEM"                      ,	42,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D2_MEM"                      ,	43,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D1_MEM"                      ,	44,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"D0_MEM"                      ,	45,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_POP1"                    ,	46,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_POP0"                    ,	47,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_49"              ,	48,	2,	439,	"RAZ",	1,	1,	0,	0},
+	{"PKT_POF"                     ,	50,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PFM"                     ,	51,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_IMEM"                    ,	52,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_SL"                     ,	53,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_ID"                     ,	54,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_CNT"                    ,	55,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_IM"                     ,	56,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PCSR_INT"                    ,	57,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_PIF"                     ,	58,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PCR_GIM"                     ,	59,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_60_62"              ,	60,	3,	439,	"RAZ",	1,	1,	0,	0},
+	{"PKT_RDF"                     ,	63,	1,	439,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_BLK"                     ,	0,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_GL"                      ,	1,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_GD"                      ,	2,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PSC_P1"                      ,	3,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PSC_P0"                      ,	4,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PKT_RD"                      ,	5,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"NWE_WR1"                     ,	6,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"NWE_WR0"                     ,	7,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"NWE_ST"                      ,	8,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"NRD_ST"                      ,	9,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_ERR"                     ,	10,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_ST1"                     ,	11,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_ST0"                     ,	12,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"PRD_TAG"                     ,	13,	1,	440,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	440,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	441,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	441,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	441,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	441,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	441,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	441,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	441,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	441,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	441,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	441,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	441,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	441,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	441,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	441,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	441,	"RAZ",	1,	1,	0,	0},
+	{"WAIT_COM"                    ,	0,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_CAX"                    ,	1,	1,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"BAR2_ESX"                    ,	2,	2,	442,	"R/W",	0,	1,	0ull,	0},
+	{"BAR2_ENB"                    ,	4,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTLP_RO"                     ,	5,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	442,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTLP_RO"                     ,	7,	1,	442,	"R/W",	0,	0,	0ull,	1ull},
+	{"INTA_MAP"                    ,	8,	2,	442,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTB_MAP"                    ,	10,	2,	442,	"R/W",	0,	0,	1ull,	1ull},
+	{"INTC_MAP"                    ,	12,	2,	442,	"R/W",	0,	0,	2ull,	2ull},
+	{"INTD_MAP"                    ,	14,	2,	442,	"R/W",	0,	0,	3ull,	3ull},
+	{"INTA"                        ,	16,	1,	442,	"RO",	0,	0,	1ull,	1ull},
+	{"INTB"                        ,	17,	1,	442,	"RO",	0,	0,	1ull,	1ull},
+	{"INTC"                        ,	18,	1,	442,	"RO",	0,	0,	1ull,	1ull},
+	{"INTD"                        ,	19,	1,	442,	"RO",	0,	0,	1ull,	1ull},
+	{"WAITL_COM"                   ,	20,	1,	442,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_63"              ,	21,	43,	442,	"RAZ",	1,	1,	0,	0},
+	{"CHIP_REV"                    ,	0,	8,	443,	"RO",	1,	1,	0,	0},
+	{"HOST_MODE"                   ,	8,	1,	443,	"RO",	1,	1,	0,	0},
+	{"PKT_BP"                      ,	9,	4,	443,	"R/W",	0,	0,	15ull,	15ull},
+	{"ARB"                         ,	13,	1,	443,	"R/W",	0,	0,	0ull,	1ull},
+	{"LNK_RST"                     ,	14,	1,	443,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	15,	1,	443,	"R/W",	0,	0,	0ull,	0ull},
+	{"CFG_RTRY"                    ,	16,	16,	443,	"R/W",	0,	0,	0ull,	32ull},
+	{"P0_NTAGS"                    ,	32,	6,	443,	"R/W",	0,	0,	32ull,	32ull},
+	{"P1_NTAGS"                    ,	38,	6,	443,	"R/W",	0,	0,	32ull,	32ull},
+	{"RESERVED_44_63"              ,	44,	20,	443,	"RAZ",	1,	1,	0,	0},
+	{"C0_B0_D"                     ,	0,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_WI_D"                     ,	1,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_B0_D"                     ,	2,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_WI_D"                     ,	3,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"C0_B1_S"                     ,	4,	3,	444,	"R/W",	0,	0,	1ull,	1ull},
+	{"C1_B1_S"                     ,	7,	3,	444,	"R/W",	0,	0,	1ull,	1ull},
+	{"C0_W_FLT"                    ,	10,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"C1_W_FLT"                    ,	11,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRRS"                        ,	12,	3,	444,	"R/W",	0,	0,	2ull,	2ull},
+	{"MPS"                         ,	15,	1,	444,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	444,	"RAZ",	1,	1,	0,	0},
+	{"P0_FCNT"                     ,	0,	6,	445,	"RO",	0,	1,	0ull,	0},
+	{"P0_UCNT"                     ,	6,	16,	445,	"RO",	0,	1,	0ull,	0},
+	{"P1_FCNT"                     ,	22,	6,	445,	"RO",	0,	1,	0ull,	0},
+	{"P1_UCNT"                     ,	28,	16,	445,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	445,	"RAZ",	1,	1,	0,	0},
+	{"DATA"                        ,	0,	17,	446,	"RO",	0,	1,	0ull,	0},
+	{"DSEL_EXT"                    ,	17,	1,	446,	"R/W",	0,	0,	1ull,	0ull},
+	{"C_MUL"                       ,	18,	5,	446,	"RO",	1,	1,	0,	0},
+	{"QLM1_SPD"                    ,	23,	2,	446,	"RO",	1,	1,	0,	0},
+	{"QLM1_MODE"                   ,	25,	2,	446,	"RO",	1,	1,	0,	0},
+	{"QLM0_REV_LANES"              ,	27,	1,	446,	"RO",	1,	1,	0,	0},
+	{"QLM0_LINK_WIDTH"             ,	28,	1,	446,	"RO",	1,	1,	0,	0},
+	{"RESERVED_29_63"              ,	29,	35,	446,	"RAZ",	1,	1,	0,	0},
+	{"DBG_SEL"                     ,	0,	16,	447,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	447,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	32,	448,	"RO",	0,	0,	0ull,	0ull},
+	{"FCNT"                        ,	32,	7,	448,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_39_63"              ,	39,	25,	448,	"RAZ",	1,	1,	0,	0},
+	{"DBELL"                       ,	0,	16,	449,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_31"              ,	16,	16,	449,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_6"                ,	0,	7,	450,	"RAZ",	1,	1,	0,	0},
+	{"SADDR"                       ,	7,	29,	450,	"R/W",	0,	1,	0ull,	0},
+	{"IDLE"                        ,	36,	1,	450,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_37_63"              ,	37,	27,	450,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	451,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	451,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	452,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	452,	"R/W",	0,	1,	0ull,	0},
+	{"CNT"                         ,	0,	32,	453,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	32,	453,	"R/W",	0,	1,	0ull,	0},
+	{"DMA0"                        ,	0,	32,	454,	"R/W",	0,	1,	0ull,	0},
+	{"DMA1"                        ,	32,	32,	454,	"R/W",	0,	1,	0ull,	0},
+	{"CSIZE"                       ,	0,	14,	455,	"R/W",	0,	1,	0ull,	0},
+	{"O_MODE"                      ,	14,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"O_ES"                        ,	15,	2,	455,	"R/W",	0,	1,	0ull,	0},
+	{"O_NS"                        ,	17,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"O_RO"                        ,	18,	1,	455,	"R/W",	0,	1,	0ull,	0},
+	{"O_ADD1"                      ,	19,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA_QUE"                     ,	20,	3,	455,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_ICHK"                    ,	23,	9,	455,	"R/W",	0,	1,	0ull,	0},
+	{"DWB_DENB"                    ,	32,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"B0_LEND"                     ,	33,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA0_ENB"                    ,	34,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_ENB"                    ,	35,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2_ENB"                    ,	36,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3_ENB"                    ,	37,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4_ENB"                    ,	38,	1,	455,	"R/W",	0,	0,	0ull,	1ull},
+	{"P_32B_M"                     ,	39,	1,	455,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	455,	"RAZ",	1,	1,	0,	0},
+	{"DMA_CNT"                     ,	0,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA0_CNT"                    ,	8,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA1_CNT"                    ,	16,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA2_CNT"                    ,	24,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_29_31"              ,	29,	3,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA3_CNT"                    ,	32,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_37_39"              ,	37,	3,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA4_CNT"                    ,	40,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_45_47"              ,	45,	3,	456,	"RAZ",	1,	1,	0,	0},
+	{"PKT_CNT"                     ,	48,	5,	456,	"R/W",	0,	1,	16ull,	0},
+	{"RESERVED_53_62"              ,	53,	10,	456,	"RAZ",	1,	1,	0,	0},
+	{"DMA_ARB"                     ,	63,	1,	456,	"R/W",	0,	1,	1ull,	0},
+	{"D0_DWE"                      ,	0,	8,	457,	"RO",	0,	1,	1ull,	0},
+	{"D1_DWE"                      ,	8,	8,	457,	"RO",	0,	1,	1ull,	0},
+	{"D2_DWE"                      ,	16,	8,	457,	"RO",	0,	1,	1ull,	0},
+	{"D3_DWE"                      ,	24,	8,	457,	"RO",	0,	1,	1ull,	0},
+	{"D4_DWE"                      ,	32,	8,	457,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_40_63"              ,	40,	24,	457,	"RAZ",	1,	1,	0,	0},
+	{"PRD"                         ,	0,	10,	458,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_10_15"              ,	10,	6,	458,	"RAZ",	1,	1,	0,	0},
+	{"NDRE"                        ,	16,	5,	458,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	458,	"RAZ",	1,	1,	0,	0},
+	{"NDWE"                        ,	24,	4,	458,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	458,	"RAZ",	1,	1,	0,	0},
+	{"DMA0_CPL"                    ,	0,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_CPL"                    ,	1,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"PINS_ERR"                    ,	2,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"POP_ERR"                     ,	3,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDI_ERR"                     ,	4,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"PGL_ERR"                     ,	5,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RDLK"                     ,	6,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RDLK"                     ,	7,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_BP"                      ,	8,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"POUT_ERR"                    ,	9,	1,	459,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	459,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1_CPL"                    ,	1,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"PINS_ERR"                    ,	2,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"POP_ERR"                     ,	3,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"PDI_ERR"                     ,	4,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"PGL_ERR"                     ,	5,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"P0_RDLK"                     ,	6,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"P1_RDLK"                     ,	7,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIN_BP"                      ,	8,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"POUT_ERR"                    ,	9,	1,	460,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_10_63"              ,	10,	54,	460,	"RAZ",	0,	1,	0ull,	0},
+	{"DMA0_CPL"                    ,	0,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1_CPL"                    ,	1,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PINS_ERR"                    ,	2,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POP_ERR"                     ,	3,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PDI_ERR"                     ,	4,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PGL_ERR"                     ,	5,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P0_RDLK"                     ,	6,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"P1_RDLK"                     ,	7,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIN_BP"                      ,	8,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"POUT_ERR"                    ,	9,	1,	461,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	461,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4DBO"                     ,	8,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0FI"                      ,	9,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_ER"                     ,	20,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_DR"                     ,	22,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_ER"                     ,	27,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_DR"                     ,	29,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_A"                       ,	61,	1,	462,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_62_62"              ,	62,	1,	462,	"RAZ",	0,	1,	0ull,	0},
+	{"MIO_INTA"                    ,	63,	1,	462,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_RTO"                     ,	0,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"RML_WTO"                     ,	1,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"BAR0_TO"                     ,	2,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOB2BIG"                     ,	3,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0DBO"                     ,	4,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1DBO"                     ,	5,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA2DBO"                     ,	6,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA3DBO"                     ,	7,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA4DBO"                     ,	8,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA0FI"                      ,	9,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DMA1FI"                      ,	10,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT0"                       ,	11,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DCNT1"                       ,	12,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME0"                      ,	13,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"DTIME1"                      ,	14,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSLDBOF"                     ,	15,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"PIDBOF"                      ,	16,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"PCNT"                        ,	17,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTIME"                       ,	18,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_AERI"                     ,	19,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_ER"                     ,	20,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_SE"                       ,	21,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS0_DR"                     ,	22,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_WAKE"                     ,	23,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_PMEI"                     ,	24,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_HPINT"                    ,	25,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_AERI"                     ,	26,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_ER"                     ,	27,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_SE"                       ,	28,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"CRS1_DR"                     ,	29,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_WAKE"                     ,	30,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_PMEI"                     ,	31,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_HPINT"                    ,	32,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B0"                    ,	33,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B1"                    ,	34,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_B2"                    ,	35,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WI"                    ,	36,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_BX"                    ,	37,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B0"                    ,	38,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B1"                    ,	39,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_B2"                    ,	40,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WI"                    ,	41,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_BX"                    ,	42,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B0"                    ,	43,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B1"                    ,	44,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_B2"                    ,	45,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WI"                    ,	46,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_BX"                    ,	47,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B0"                    ,	48,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B1"                    ,	49,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_B2"                    ,	50,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WI"                    ,	51,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_BX"                    ,	52,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UN_WF"                    ,	53,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UN_WF"                    ,	54,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_UP_WF"                    ,	55,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_UP_WF"                    ,	56,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_EXC"                      ,	57,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_EXC"                      ,	58,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C0_LDWN"                     ,	59,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"C1_LDWN"                     ,	60,	1,	463,	"R/W",	0,	0,	0ull,	1ull},
+	{"INT_A"                       ,	61,	1,	463,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_62_63"              ,	62,	2,	463,	"RAZ",	0,	1,	0ull,	0},
+	{"PSLDBOF"                     ,	0,	6,	464,	"RO",	0,	1,	0ull,	0},
+	{"PIDBOF"                      ,	6,	6,	464,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_12_63"              ,	12,	52,	464,	"RAZ",	1,	1,	0,	0},
+	{"RML_RTO"                     ,	0,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA4DBO"                     ,	8,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA0FI"                      ,	9,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PSLDBOF"                     ,	15,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PIDBOF"                      ,	16,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PCNT"                        ,	17,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"PTIME"                       ,	18,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_ER"                     ,	20,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS0_DR"                     ,	22,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_ER"                     ,	27,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CRS1_DR"                     ,	29,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	465,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INT_A"                       ,	61,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	465,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	465,	"RO",	0,	0,	0ull,	0ull},
+	{"RML_RTO"                     ,	0,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"RML_WTO"                     ,	1,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"BAR0_TO"                     ,	2,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB2BIG"                     ,	3,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA0DBO"                     ,	4,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA1DBO"                     ,	5,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA2DBO"                     ,	6,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA3DBO"                     ,	7,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	466,	"RAZ",	1,	1,	0,	0},
+	{"DMA0FI"                      ,	9,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DMA1FI"                      ,	10,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DCNT0"                       ,	11,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DCNT1"                       ,	12,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME0"                      ,	13,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DTIME1"                      ,	14,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_18"              ,	15,	4,	466,	"RAZ",	0,	0,	0ull,	0ull},
+	{"C0_AERI"                     ,	19,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_ER"                     ,	20,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_SE"                       ,	21,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS0_DR"                     ,	22,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_WAKE"                     ,	23,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_PMEI"                     ,	24,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_HPINT"                    ,	25,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_AERI"                     ,	26,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_ER"                     ,	27,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_SE"                       ,	28,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"CRS1_DR"                     ,	29,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_WAKE"                     ,	30,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_PMEI"                     ,	31,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_HPINT"                    ,	32,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B0"                    ,	33,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B1"                    ,	34,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_B2"                    ,	35,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_WI"                    ,	36,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_BX"                    ,	37,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B0"                    ,	38,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B1"                    ,	39,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_B2"                    ,	40,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_WI"                    ,	41,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_BX"                    ,	42,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B0"                    ,	43,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B1"                    ,	44,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_B2"                    ,	45,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_WI"                    ,	46,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_BX"                    ,	47,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B0"                    ,	48,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B1"                    ,	49,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_B2"                    ,	50,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_WI"                    ,	51,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_BX"                    ,	52,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UN_WF"                    ,	53,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UN_WF"                    ,	54,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_UP_WF"                    ,	55,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_UP_WF"                    ,	56,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_EXC"                      ,	57,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_EXC"                      ,	58,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C0_LDWN"                     ,	59,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"C1_LDWN"                     ,	60,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"INT_A"                       ,	61,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_62_62"              ,	62,	1,	466,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO_INTA"                    ,	63,	1,	466,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	467,	"RO",	0,	1,	0ull,	0},
+	{"DATA"                        ,	0,	64,	468,	"RO",	0,	1,	0ull,	0},
+	{"TIMER"                       ,	0,	10,	469,	"R/W",	0,	0,	0ull,	50ull},
+	{"MAX_WORD"                    ,	10,	4,	469,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	469,	"RAZ",	1,	1,	0,	0},
+	{"BA"                          ,	0,	30,	470,	"R/W",	0,	1,	0ull,	0},
+	{"ROW"                         ,	30,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	31,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"NSW"                         ,	32,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	33,	1,	470,	"R/W",	0,	1,	0ull,	0},
+	{"ESW"                         ,	34,	2,	470,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	36,	2,	470,	"R/W",	0,	1,	0ull,	0},
+	{"NMERGE"                      ,	38,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORT"                        ,	39,	2,	470,	"R/W",	0,	1,	0ull,	0},
+	{"ZERO"                        ,	41,	1,	470,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_42_63"              ,	42,	22,	470,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	64,	471,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	472,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	473,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"ENB"                         ,	0,	64,	474,	"R/W",	0,	0,	0ull,	18446744073709551615ull},
+	{"INTR"                        ,	0,	64,	475,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	476,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	477,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTR"                        ,	0,	64,	478,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	479,	"R/W",	0,	1,	0ull,	0},
+	{"RD_INT"                      ,	8,	8,	479,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	479,	"RAZ",	1,	1,	0,	0},
+	{"CLR"                         ,	0,	64,	480,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	481,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	482,	"R/W",	0,	0,	0ull,	0ull},
+	{"CLR"                         ,	0,	64,	483,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	484,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	485,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	486,	"R/W",	0,	0,	0ull,	0ull},
+	{"SET"                         ,	0,	64,	487,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSI_INT"                     ,	0,	8,	488,	"R/W",	0,	1,	0ull,	0},
+	{"CIU_INT"                     ,	8,	8,	488,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	488,	"RAZ",	1,	1,	0,	0},
+	{"P0_PCNT"                     ,	0,	8,	489,	"R/W",	0,	0,	128ull,	128ull},
+	{"P0_NCNT"                     ,	8,	8,	489,	"R/W",	0,	0,	16ull,	16ull},
+	{"P0_CCNT"                     ,	16,	8,	489,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_PCNT"                     ,	24,	8,	489,	"R/W",	0,	0,	128ull,	128ull},
+	{"P1_NCNT"                     ,	32,	8,	489,	"R/W",	0,	0,	16ull,	16ull},
+	{"P1_CCNT"                     ,	40,	8,	489,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_48_63"              ,	48,	16,	489,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	0,	8,	490,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	490,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	491,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	8,	8,	491,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	491,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_15"               ,	0,	16,	492,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	16,	8,	492,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_24_63"              ,	24,	40,	492,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_23"               ,	0,	24,	493,	"RAZ",	1,	1,	0,	0},
+	{"INTR"                        ,	24,	8,	493,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	493,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	494,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMER"                       ,	32,	22,	494,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	494,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	495,	"R/W",	0,	0,	0ull,	0ull},
+	{"WMARK"                       ,	32,	32,	495,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_0_2"                ,	0,	3,	496,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	3,	61,	496,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	497,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	497,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	498,	"R/W",	0,	1,	0ull,	0},
+	{"FCNT"                        ,	32,	5,	498,	"RO",	0,	1,	0ull,	0},
+	{"WRP"                         ,	37,	9,	498,	"RO",	0,	1,	0ull,	0},
+	{"RRP"                         ,	46,	9,	498,	"RO",	0,	1,	0ull,	0},
+	{"MAX"                         ,	55,	9,	498,	"RO",	0,	1,	16ull,	0},
+	{"RESERVED_0_5"                ,	0,	6,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"SKP_LEN"                     ,	6,	7,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_13"              ,	13,	1,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"PAR_MODE"                    ,	14,	2,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_20"              ,	16,	5,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"USE_IHDR"                    ,	21,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_22_27"              ,	22,	6,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RSKP_LEN"                    ,	28,	7,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_35_35"              ,	35,	1,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"RPARMODE"                    ,	36,	2,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_38_42"              ,	38,	5,	499,	"RAZ",	0,	1,	0ull,	0},
+	{"PBP"                         ,	43,	1,	499,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_44_63"              ,	44,	20,	499,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	500,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	4,	60,	500,	"R/W",	0,	1,	0ull,	0},
+	{"DBELL"                       ,	0,	32,	501,	"R/W",	0,	0,	0ull,	0ull},
+	{"AOFF"                        ,	32,	32,	501,	"RO",	0,	1,	0ull,	0},
+	{"RSIZE"                       ,	0,	32,	502,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	502,	"RAZ",	0,	1,	0ull,	0},
+	{"PORT"                        ,	0,	32,	503,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	503,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	504,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	504,	"RAZ",	1,	1,	0,	0},
+	{"ES"                          ,	0,	64,	505,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	0,	32,	506,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	506,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	507,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	507,	"RAZ",	1,	1,	0,	0},
+	{"DPTR"                        ,	0,	32,	508,	"R/W",	0,	0,	0ull,	4294967295ull},
+	{"RESERVED_32_63"              ,	32,	32,	508,	"RAZ",	1,	1,	0,	0},
+	{"BP"                          ,	0,	32,	509,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	509,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	510,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	510,	"RAZ",	0,	1,	0ull,	0},
+	{"RD_CNT"                      ,	0,	32,	511,	"RO",	0,	1,	0ull,	0},
+	{"WR_CNT"                      ,	32,	32,	511,	"RO",	0,	1,	0ull,	0},
+	{"PP"                          ,	0,	64,	512,	"R/W",	0,	1,	0ull,	0},
+	{"ROR"                         ,	0,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"ESR"                         ,	1,	2,	513,	"R/W",	0,	1,	0ull,	0},
+	{"NSR"                         ,	3,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"USE_CSR"                     ,	4,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"D_ROR"                       ,	5,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"D_ESR"                       ,	6,	2,	513,	"R/W",	0,	1,	0ull,	0},
+	{"D_NSR"                       ,	8,	1,	513,	"R/W",	0,	1,	0ull,	0},
+	{"PBP_DHI"                     ,	9,	13,	513,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKT_RR"                      ,	22,	1,	513,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_23_63"              ,	23,	41,	513,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	514,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	514,	"RAZ",	1,	1,	0,	0},
+	{"RDSIZE"                      ,	0,	64,	515,	"R/W",	0,	1,	0ull,	0},
+	{"IS_64B"                      ,	0,	32,	516,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	516,	"RAZ",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	32,	517,	"R/W",	0,	1,	0ull,	0},
+	{"TIME"                        ,	32,	22,	517,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_54_63"              ,	54,	10,	517,	"RAZ",	1,	1,	0,	0},
+	{"IPTR"                        ,	0,	32,	518,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	518,	"RAZ",	1,	1,	0,	0},
+	{"BMODE"                       ,	0,	32,	519,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	519,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	32,	520,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	520,	"RAZ",	1,	1,	0,	0},
+	{"WMARK"                       ,	0,	32,	521,	"R/W",	0,	0,	0ull,	14ull},
+	{"RESERVED_32_63"              ,	32,	32,	521,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	0,	64,	522,	"R/W",	0,	1,	0ull,	0},
+	{"OUT_RST"                     ,	0,	32,	523,	"RO",	0,	1,	0ull,	0},
+	{"IN_RST"                      ,	32,	32,	523,	"RO",	0,	1,	0ull,	0},
+	{"ES"                          ,	0,	64,	524,	"R/W",	0,	1,	0ull,	0},
+	{"BSIZE"                       ,	0,	16,	525,	"R/W",	0,	1,	0ull,	0},
+	{"ISIZE"                       ,	16,	7,	525,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_23_63"              ,	23,	41,	525,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	0,	32,	526,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	526,	"RAZ",	1,	1,	0,	0},
+	{"ROR"                         ,	0,	32,	527,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	527,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	528,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	528,	"RAZ",	1,	1,	0,	0},
+	{"PORT"                        ,	0,	32,	529,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	529,	"RAZ",	1,	1,	0,	0},
+	{"MIO"                         ,	0,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX0"                        ,	1,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"GMX1"                        ,	2,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"NPEI"                        ,	3,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"KEY"                         ,	4,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"FPA"                         ,	5,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"DFA"                         ,	6,	1,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ZIP"                         ,	7,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_8"                ,	8,	1,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"IPD"                         ,	9,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	10,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"TIM"                         ,	11,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"POW"                         ,	12,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"USB"                         ,	13,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RAD"                         ,	14,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"USB1"                        ,	15,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"L2C"                         ,	16,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC0"                        ,	17,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"SPX0"                        ,	18,	1,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"SPX1"                        ,	19,	1,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	20,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_21"              ,	21,	1,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASXPCS0"                     ,	22,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"ASXPCS1"                     ,	23,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_24_27"              ,	24,	4,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"AGL"                         ,	28,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"LMC1"                        ,	29,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"IOB"                         ,	30,	1,	530,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	530,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	531,	"R/W",	0,	1,	0ull,	0},
+	{"CSR"                         ,	0,	39,	532,	"RO",	0,	1,	1ull,	0},
+	{"ARB"                         ,	39,	1,	532,	"RO",	0,	1,	0ull,	0},
+	{"CPL0"                        ,	40,	12,	532,	"RO",	0,	1,	1ull,	0},
+	{"CPL1"                        ,	52,	12,	532,	"RO",	0,	1,	1ull,	0},
+	{"NND"                         ,	0,	8,	533,	"RO",	0,	1,	1ull,	0},
+	{"NNP0"                        ,	8,	8,	533,	"RO",	0,	1,	1ull,	0},
+	{"CSM0"                        ,	16,	15,	533,	"RO",	0,	1,	1ull,	0},
+	{"CSM1"                        ,	31,	15,	533,	"RO",	0,	1,	1ull,	0},
+	{"RAC"                         ,	46,	1,	533,	"RO",	0,	1,	1ull,	0},
+	{"NPEI"                        ,	47,	1,	533,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	533,	"RAZ",	1,	1,	0,	0},
+	{"NSM0"                        ,	0,	13,	534,	"RO",	0,	1,	1ull,	0},
+	{"NSM1"                        ,	13,	13,	534,	"RO",	0,	1,	1ull,	0},
+	{"PSM0"                        ,	26,	15,	534,	"RO",	0,	1,	1ull,	0},
+	{"PSM1"                        ,	41,	15,	534,	"RO",	0,	1,	1ull,	0},
+	{"RESERVED_56_63"              ,	56,	8,	534,	"RAZ",	1,	1,	0,	0},
+	{"RD_ADDR"                     ,	0,	48,	535,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	535,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LD_CMD"                      ,	49,	2,	535,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_51_63"              ,	51,	13,	535,	"RAZ",	1,	1,	0,	0},
+	{"RD_DATA"                     ,	0,	64,	536,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_0_1"                ,	0,	2,	537,	"RAZ",	1,	1,	0,	0},
+	{"WR_ADDR"                     ,	2,	46,	537,	"R/W",	0,	1,	0ull,	0},
+	{"IOBIT"                       ,	48,	1,	537,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	537,	"RAZ",	1,	1,	0,	0},
+	{"WR_DATA"                     ,	0,	64,	538,	"R/W",	0,	1,	0ull,	0},
+	{"WR_MASK"                     ,	0,	8,	539,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	539,	"RAZ",	1,	1,	0,	0},
+	{"TIME"                        ,	0,	32,	540,	"R/W",	0,	0,	0ull,	2097152ull},
+	{"RESERVED_32_63"              ,	32,	32,	540,	"RAZ",	1,	1,	0,	0},
+	{"VENDID"                      ,	0,	16,	541,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	541,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"ISAE"                        ,	0,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	542,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	542,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	542,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	542,	"RAZ",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	542,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	542,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	543,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	543,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	543,	"RO/WRSL",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	543,	"RO/WRSL",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	544,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"MFD"                         ,	23,	1,	544,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	544,	"RO",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	545,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	545,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	545,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_13"               ,	4,	10,	545,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	14,	18,	545,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	546,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	546,	"WORSL",	0,	0,	8191ull,	8191ull},
+	{"UBAB"                        ,	0,	32,	547,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	548,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	549,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	549,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	549,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_25"               ,	4,	22,	549,	"RAZ",	1,	1,	0,	0},
+	{"LBAB"                        ,	26,	6,	549,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	550,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	550,	"WORSL",	0,	0,	33554431ull,	33554431ull},
+	{"UBAB"                        ,	0,	32,	551,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	552,	"WORSL",	0,	0,	0ull,	0ull},
+	{"MSPC"                        ,	0,	1,	553,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"TYP"                         ,	1,	2,	553,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"PF"                          ,	3,	1,	553,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_4_31"               ,	4,	28,	553,	"RAZ",	1,	1,	0,	0},
+	{"ENB"                         ,	0,	1,	554,	"WORSL",	0,	0,	1ull,	1ull},
+	{"LMASK"                       ,	1,	31,	554,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"RESERVED_0_6"                ,	0,	7,	555,	"RAZ",	1,	1,	0,	0},
+	{"UBAB"                        ,	7,	25,	555,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMASK"                       ,	0,	32,	556,	"WORSL",	0,	0,	127ull,	127ull},
+	{"CISP"                        ,	0,	32,	557,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SSVID"                       ,	0,	16,	558,	"RO/WRSL",	0,	0,	6013ull,	6013ull},
+	{"SSID"                        ,	16,	16,	558,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"ER_EN"                       ,	0,	1,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_15"               ,	1,	15,	559,	"RAZ",	1,	1,	0,	0},
+	{"ERADDR"                      ,	16,	16,	559,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENB"                         ,	0,	1,	560,	"WORSL",	0,	0,	1ull,	1ull},
+	{"MASK"                        ,	1,	31,	560,	"WORSL",	0,	0,	2147483647ull,	2147483647ull},
+	{"CP"                          ,	0,	8,	561,	"RO/WRSL",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	561,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	562,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	562,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MG"                          ,	16,	8,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"ML"                          ,	24,	8,	562,	"RO",	0,	0,	0ull,	0ull},
+	{"PMCID"                       ,	0,	8,	563,	"RO",	0,	0,	1ull,	0ull},
+	{"NCP"                         ,	8,	8,	563,	"RO/WRSL",	0,	0,	80ull,	0ull},
+	{"PMSV"                        ,	16,	3,	563,	"RO/WRSL",	0,	0,	3ull,	0ull},
+	{"PME_CLOCK"                   ,	19,	1,	563,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	563,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	563,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	563,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	563,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	563,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	563,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	564,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	564,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	564,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	564,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	564,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	564,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	564,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	565,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	565,	"RO/WRSL",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	565,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	565,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	565,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	565,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	566,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	566,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	567,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	568,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	568,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	569,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	569,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	569,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	569,	"RO",	0,	0,	0ull,	0ull},
+	{"SI"                          ,	24,	1,	569,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	569,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	569,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	570,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	570,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	570,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	570,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"EL1AL"                       ,	9,	3,	570,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"RESERVED_12_14"              ,	12,	3,	570,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	570,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	570,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	570,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	570,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	570,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	571,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	571,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	571,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	571,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	571,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	571,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	571,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	571,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	572,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	572,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	572,	"RO/WRSL",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	572,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	572,	"RO/WRSL",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	572,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"LBNC"                        ,	21,	1,	572,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	572,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	572,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	573,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"LD"                          ,	4,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	573,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_15"              ,	10,	6,	573,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	573,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	573,	"RO",	0,	0,	0ull,	8ull},
+	{"RESERVED_26_26"              ,	26,	1,	573,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	573,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"DLLA"                        ,	29,	1,	573,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	573,	"RAZ",	1,	1,	0,	0},
+	{"ABP"                         ,	0,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	574,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIC"                         ,	8,	2,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCC"                         ,	10,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	575,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	575,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	575,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"EMIS"                        ,	23,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	575,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	575,	"RAZ",	1,	1,	0,	0},
+	{"CTRS"                        ,	0,	4,	576,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	576,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	576,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	577,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	577,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	577,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	578,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	579,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	580,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	581,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	582,	"RO",	0,	0,	1ull,	0ull},
+	{"CV"                          ,	16,	4,	582,	"RO",	0,	0,	1ull,	0ull},
+	{"NCO"                         ,	20,	12,	582,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	583,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	583,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	583,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	583,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	583,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	584,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	584,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	584,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	584,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	584,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	585,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	585,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	585,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	585,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	585,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	585,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	585,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	585,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	585,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	586,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	586,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	586,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	586,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	586,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	586,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	586,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	586,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	586,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	587,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	587,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	587,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	587,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	587,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	588,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	588,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	588,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	588,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	588,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	589,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	590,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	591,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	592,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	593,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	593,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	594,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	595,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_14"               ,	8,	7,	595,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	595,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	595,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	595,	"R/W",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	596,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	596,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	596,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	596,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	596,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	596,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	597,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	597,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	597,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	597,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	597,	"R/W",	0,	0,	7ull,	7ull},
+	{"RESERVED_22_24"              ,	22,	3,	597,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	597,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	597,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	598,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	598,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	599,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	599,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	599,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	599,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	599,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	599,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	599,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	600,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	600,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	600,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	601,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	601,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	602,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	603,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	604,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	604,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	605,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	605,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	606,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	606,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	607,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	607,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	608,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	608,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	609,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	610,	"RO/WRSL",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	610,	"RO/WRSL",	0,	0,	35ull,	35ull},
+	{"RESERVED_20_20"              ,	20,	1,	610,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	610,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	610,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	610,	"RO/WRSL",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	610,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	611,	"RO/WRSL",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	611,	"RO/WRSL",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	611,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	611,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	611,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	612,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"HEADER_CREDITS"              ,	12,	8,	612,	"RO/WRSL",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	612,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	612,	"RO/WRSL",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	612,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	613,	"RO/WRSL",	0,	0,	331ull,	331ull},
+	{"RESERVED_14_15"              ,	14,	2,	613,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	613,	"RO/WRSL",	0,	0,	41ull,	41ull},
+	{"RESERVED_26_31"              ,	26,	6,	613,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	614,	"RO/WRSL",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	614,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	614,	"RO/WRSL",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	614,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	615,	"RO/WRSL",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	615,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	615,	"RO/WRSL",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	615,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	616,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	617,	"R/W",	0,	0,	0ull,	0ull},
+	{"VENDID"                      ,	0,	16,	618,	"R/W",	0,	0,	6013ull,	6013ull},
+	{"DEVID"                       ,	16,	16,	618,	"R/W",	0,	0,	128ull,	128ull},
+	{"ISAE"                        ,	0,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSAE"                        ,	1,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"ME"                          ,	2,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"SCSE"                        ,	3,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"MWICE"                       ,	4,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"VPS"                         ,	5,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"PER"                         ,	6,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDS_WCC"                     ,	7,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	8,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	9,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"I_DIS"                       ,	10,	1,	619,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_18"              ,	11,	8,	619,	"RAZ",	1,	1,	0,	0},
+	{"I_STAT"                      ,	19,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"CL"                          ,	20,	1,	619,	"RO",	0,	0,	1ull,	1ull},
+	{"M66"                         ,	21,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	619,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	619,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	619,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RID"                         ,	0,	8,	620,	"R/W",	0,	0,	8ull,	8ull},
+	{"PI"                          ,	8,	8,	620,	"R/W",	0,	0,	0ull,	0ull},
+	{"SC"                          ,	16,	8,	620,	"R/W",	0,	0,	48ull,	48ull},
+	{"BCC"                         ,	24,	8,	620,	"R/W",	0,	0,	11ull,	11ull},
+	{"CLS"                         ,	0,	8,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT"                          ,	8,	8,	621,	"RO",	0,	0,	0ull,	0ull},
+	{"CHF"                         ,	16,	7,	621,	"RO",	0,	0,	1ull,	1ull},
+	{"MFD"                         ,	23,	1,	621,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST"                        ,	24,	8,	621,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_31"               ,	0,	32,	622,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	623,	"RO",	1,	1,	0,	0},
+	{"PBNUM"                       ,	0,	8,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"SBNUM"                       ,	8,	8,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"SUBBNUM"                     ,	16,	8,	624,	"R/W",	0,	0,	0ull,	0ull},
+	{"SLT"                         ,	24,	8,	624,	"RO",	0,	0,	0ull,	0ull},
+	{"IO32A"                       ,	0,	1,	625,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	625,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_BASE"                    ,	4,	4,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"IO32B"                       ,	8,	1,	625,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_9_11"               ,	9,	3,	625,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LIO_LIMI"                    ,	12,	4,	625,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_20"              ,	16,	5,	625,	"RAZ",	1,	1,	0,	0},
+	{"M66"                         ,	21,	1,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_22"              ,	22,	1,	625,	"RO",	1,	1,	0,	0},
+	{"FBB"                         ,	23,	1,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"MDPE"                        ,	24,	1,	625,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DEVT"                        ,	25,	2,	625,	"RO",	0,	0,	0ull,	0ull},
+	{"STA"                         ,	27,	1,	625,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTA"                         ,	28,	1,	625,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RMA"                         ,	29,	1,	625,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SSE"                         ,	30,	1,	625,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPE"                         ,	31,	1,	625,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	626,	"RO",	1,	1,	0,	0},
+	{"MB_ADDR"                     ,	4,	12,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_19"              ,	16,	4,	626,	"RO",	1,	1,	0,	0},
+	{"ML_ADDR"                     ,	20,	12,	626,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64A"                      ,	0,	1,	627,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_3"                ,	1,	3,	627,	"RO",	1,	1,	0,	0},
+	{"LMEM_BASE"                   ,	4,	12,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"MEM64B"                      ,	16,	1,	627,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_17_19"              ,	17,	3,	627,	"RO",	1,	1,	0,	0},
+	{"LMEM_LIMIT"                  ,	20,	12,	627,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_BASE"                   ,	0,	32,	628,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMEM_LIMIT"                  ,	0,	32,	629,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_BASE"                    ,	0,	16,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"UIO_LIMIT"                   ,	16,	16,	630,	"R/W",	0,	0,	0ull,	0ull},
+	{"CP"                          ,	0,	8,	631,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_8_31"               ,	8,	24,	631,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	632,	"RAZ",	1,	1,	0,	0},
+	{"IL"                          ,	0,	8,	633,	"R/W",	0,	0,	255ull,	255ull},
+	{"INTA"                        ,	8,	8,	633,	"R/W",	0,	0,	1ull,	1ull},
+	{"PERE"                        ,	16,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEE"                         ,	17,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISAE"                        ,	18,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGAE"                        ,	19,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"VGA16D"                      ,	20,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAM"                         ,	21,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"SBRST"                       ,	22,	1,	633,	"R/W",	0,	0,	0ull,	0ull},
+	{"FBBE"                        ,	23,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"PDT"                         ,	24,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"SDT"                         ,	25,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"DTS"                         ,	26,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"DTSEES"                      ,	27,	1,	633,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	633,	"RO",	1,	1,	0,	0},
+	{"PMCID"                       ,	0,	8,	634,	"RO",	0,	0,	1ull,	1ull},
+	{"NCP"                         ,	8,	8,	634,	"R/W",	0,	0,	80ull,	80ull},
+	{"PMSV"                        ,	16,	3,	634,	"R/W",	0,	0,	3ull,	3ull},
+	{"PME_CLOCK"                   ,	19,	1,	634,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	634,	"RAZ",	1,	1,	0,	0},
+	{"DSI"                         ,	21,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUXC"                        ,	22,	3,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"D1S"                         ,	25,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"D2S"                         ,	26,	1,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMES"                        ,	27,	5,	634,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS"                          ,	0,	2,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	635,	"RAZ",	1,	1,	0,	0},
+	{"NSR"                         ,	3,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	635,	"RAZ",	1,	1,	0,	0},
+	{"PMEENS"                      ,	8,	1,	635,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMDS"                        ,	9,	4,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"PMEDSIA"                     ,	13,	2,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"PMESS"                       ,	15,	1,	635,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_21"              ,	16,	6,	635,	"RAZ",	1,	1,	0,	0},
+	{"BD3H"                        ,	22,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"BPCCEE"                      ,	23,	1,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"PMDIA"                       ,	24,	8,	635,	"RO",	0,	0,	0ull,	0ull},
+	{"MSICID"                      ,	0,	8,	636,	"RO",	0,	0,	5ull,	5ull},
+	{"NCP"                         ,	8,	8,	636,	"R/W",	0,	0,	112ull,	112ull},
+	{"MSIEN"                       ,	16,	1,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"MMC"                         ,	17,	3,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"MME"                         ,	20,	3,	636,	"R/W",	0,	0,	0ull,	0ull},
+	{"M64"                         ,	23,	1,	636,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_24_31"              ,	24,	8,	636,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	637,	"RAZ",	1,	1,	0,	0},
+	{"LMSI"                        ,	2,	30,	637,	"R/W",	0,	0,	0ull,	0ull},
+	{"UMSI"                        ,	0,	32,	638,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSIMD"                       ,	0,	16,	639,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	639,	"RAZ",	1,	1,	0,	0},
+	{"PCIEID"                      ,	0,	8,	640,	"RO",	0,	0,	16ull,	16ull},
+	{"NCP"                         ,	8,	8,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCIECV"                      ,	16,	4,	640,	"RO",	0,	0,	2ull,	2ull},
+	{"DPT"                         ,	20,	4,	640,	"RO",	0,	0,	4ull,	4ull},
+	{"SI"                          ,	24,	1,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"IMN"                         ,	25,	5,	640,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_30_31"              ,	30,	2,	640,	"RAZ",	1,	1,	0,	0},
+	{"MPSS"                        ,	0,	3,	641,	"R/W",	0,	0,	1ull,	1ull},
+	{"PFS"                         ,	3,	2,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETFS"                        ,	5,	1,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL0AL"                       ,	6,	3,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"EL1AL"                       ,	9,	3,	641,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_14"              ,	12,	3,	641,	"RAZ",	1,	1,	0,	0},
+	{"RBER"                        ,	15,	1,	641,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_17"              ,	16,	2,	641,	"RAZ",	1,	1,	0,	0},
+	{"CSPLV"                       ,	18,	8,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"CSPLS"                       ,	26,	2,	641,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	641,	"RAZ",	1,	1,	0,	0},
+	{"CE_EN"                       ,	0,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFE_EN"                      ,	1,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"FE_EN"                       ,	2,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"UR_EN"                       ,	3,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"RO_EN"                       ,	4,	1,	642,	"R/W",	0,	0,	1ull,	1ull},
+	{"MPS"                         ,	5,	3,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"ETF_EN"                      ,	8,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	9,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"AP_EN"                       ,	10,	1,	642,	"R/W",	0,	0,	0ull,	0ull},
+	{"NS_EN"                       ,	11,	1,	642,	"R/W",	0,	0,	1ull,	1ull},
+	{"MRRS"                        ,	12,	3,	642,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_15_15"              ,	15,	1,	642,	"RAZ",	1,	1,	0,	0},
+	{"CE_D"                        ,	16,	1,	642,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFE_D"                       ,	17,	1,	642,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FE_D"                        ,	18,	1,	642,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UR_D"                        ,	19,	1,	642,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AP_D"                        ,	20,	1,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"TP"                          ,	21,	1,	642,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	642,	"RAZ",	1,	1,	0,	0},
+	{"MLS"                         ,	0,	4,	643,	"R/W",	0,	0,	1ull,	1ull},
+	{"MLW"                         ,	4,	6,	643,	"R/W",	0,	0,	8ull,	8ull},
+	{"ASLPMS"                      ,	10,	2,	643,	"R/W",	0,	0,	3ull,	3ull},
+	{"L0EL"                        ,	12,	3,	643,	"R/W",	0,	0,	6ull,	6ull},
+	{"L1EL"                        ,	15,	3,	643,	"R/W",	0,	0,	6ull,	6ull},
+	{"CPM"                         ,	18,	1,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDERC"                       ,	19,	1,	643,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLARC"                      ,	20,	1,	643,	"RO",	0,	0,	1ull,	1ull},
+	{"LBNC"                        ,	21,	1,	643,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_22_23"              ,	22,	2,	643,	"RAZ",	1,	1,	0,	0},
+	{"PNUM"                        ,	24,	8,	643,	"R/W",	0,	0,	0ull,	0ull},
+	{"ASLPC"                       ,	0,	2,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	644,	"RAZ",	1,	1,	0,	0},
+	{"RCB"                         ,	3,	1,	644,	"R/W",	0,	0,	1ull,	1ull},
+	{"LD"                          ,	4,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"RL"                          ,	5,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCC"                         ,	6,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"ES"                          ,	7,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECPM"                        ,	8,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"HAWD"                        ,	9,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"LBM_INT_ENB"                 ,	10,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAB_INT_ENB"                 ,	11,	1,	644,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	644,	"RAZ",	1,	1,	0,	0},
+	{"LS"                          ,	16,	4,	644,	"RO",	0,	0,	1ull,	1ull},
+	{"NLW"                         ,	20,	6,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_26"              ,	26,	1,	644,	"RAZ",	1,	1,	0,	0},
+	{"LT"                          ,	27,	1,	644,	"RO",	0,	0,	0ull,	0ull},
+	{"SCC"                         ,	28,	1,	644,	"R/W",	0,	0,	1ull,	0ull},
+	{"DLLA"                        ,	29,	1,	644,	"RO",	0,	0,	0ull,	1ull},
+	{"LBM"                         ,	30,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LAB"                         ,	31,	1,	644,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ABP"                         ,	0,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"PCP"                         ,	1,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLSP"                       ,	2,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIP"                         ,	3,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"PIP"                         ,	4,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_S"                        ,	5,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"HP_C"                        ,	6,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LV"                       ,	7,	8,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"SP_LS"                       ,	15,	2,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIP"                        ,	17,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"NCCS"                        ,	18,	1,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"PS_NUM"                      ,	19,	13,	645,	"R/W",	0,	0,	0ull,	0ull},
+	{"ABP_EN"                      ,	0,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"PF_EN"                       ,	1,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRLS_EN"                     ,	2,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"PD_EN"                       ,	3,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"CCINT_EN"                    ,	4,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"HPINT_EN"                    ,	5,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"AIC"                         ,	6,	2,	646,	"R/W",	0,	0,	3ull,	3ull},
+	{"PIC"                         ,	8,	2,	646,	"R/W",	0,	0,	3ull,	3ull},
+	{"PCC"                         ,	10,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"EMIC"                        ,	11,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLLS_EN"                     ,	12,	1,	646,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	646,	"RAZ",	1,	1,	0,	0},
+	{"ABP_D"                       ,	16,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PF_D"                        ,	17,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLS_C"                      ,	18,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PD_C"                        ,	19,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CCINT_D"                     ,	20,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRLSS"                       ,	21,	1,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"PDS"                         ,	22,	1,	646,	"RO",	0,	0,	1ull,	1ull},
+	{"EMIS"                        ,	23,	1,	646,	"RO",	0,	0,	0ull,	0ull},
+	{"DLLS_C"                      ,	24,	1,	646,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	646,	"RAZ",	1,	1,	0,	0},
+	{"SECEE"                       ,	0,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"SENFEE"                      ,	1,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"SEFEE"                       ,	2,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"PMEIE"                       ,	3,	1,	647,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRSSVE"                      ,	4,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_15"               ,	5,	11,	647,	"RAZ",	1,	1,	0,	0},
+	{"CRSSV"                       ,	16,	1,	647,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	647,	"RAZ",	1,	1,	0,	0},
+	{"PME_RID"                     ,	0,	16,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"PME_STAT"                    ,	16,	1,	648,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PME_PEND"                    ,	17,	1,	648,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_31"              ,	18,	14,	648,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CTRS"                        ,	0,	4,	649,	"RO",	0,	0,	0ull,	0ull},
+	{"CTDS"                        ,	4,	1,	649,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_5_31"               ,	5,	27,	649,	"RAZ",	1,	1,	0,	0},
+	{"CTV"                         ,	0,	4,	650,	"RO",	0,	0,	0ull,	0ull},
+	{"CTD"                         ,	4,	1,	650,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	650,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	651,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	652,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	653,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_31"               ,	0,	32,	654,	"RAZ",	1,	1,	0,	0},
+	{"PCIEEC"                      ,	0,	16,	655,	"RO",	0,	0,	1ull,	1ull},
+	{"CV"                          ,	16,	4,	655,	"RO",	0,	0,	1ull,	1ull},
+	{"NCO"                         ,	20,	12,	655,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_3"                ,	0,	4,	656,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SDES"                        ,	5,	1,	656,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	656,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CTS"                         ,	14,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MTLPS"                       ,	18,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRCES"                      ,	19,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	656,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	656,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	657,	"RAZ",	1,	1,	0,	0},
+	{"DLPEM"                       ,	4,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"SDEM"                        ,	5,	1,	657,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_11"               ,	6,	6,	657,	"RAZ",	1,	1,	0,	0},
+	{"PTLPM"                       ,	12,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPEM"                       ,	13,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"CTM"                         ,	14,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	15,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCM"                         ,	16,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROM"                         ,	17,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"MTLPM"                       ,	18,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRCEM"                      ,	19,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"UREM"                        ,	20,	1,	657,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	657,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_3"                ,	0,	4,	658,	"RAZ",	1,	1,	0,	0},
+	{"DLPES"                       ,	4,	1,	658,	"R/W",	0,	0,	1ull,	1ull},
+	{"SDES"                        ,	5,	1,	658,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_11"               ,	6,	6,	658,	"RAZ",	1,	1,	0,	0},
+	{"PTLPS"                       ,	12,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPES"                       ,	13,	1,	658,	"R/W",	0,	0,	1ull,	1ull},
+	{"CTS"                         ,	14,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAS"                         ,	15,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"UCS"                         ,	16,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"ROS"                         ,	17,	1,	658,	"R/W",	0,	0,	1ull,	1ull},
+	{"MTLPS"                       ,	18,	1,	658,	"R/W",	0,	0,	1ull,	1ull},
+	{"ECRCES"                      ,	19,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"URES"                        ,	20,	1,	658,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	658,	"RAZ",	1,	1,	0,	0},
+	{"RES"                         ,	0,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	659,	"RAZ",	1,	1,	0,	0},
+	{"BTLPS"                       ,	6,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BDLLPS"                      ,	7,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNRS"                        ,	8,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	659,	"RAZ",	1,	1,	0,	0},
+	{"RTTS"                        ,	12,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ANFES"                       ,	13,	1,	659,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_31"              ,	14,	18,	659,	"RAZ",	1,	1,	0,	0},
+	{"REM"                         ,	0,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_5"                ,	1,	5,	660,	"RAZ",	1,	1,	0,	0},
+	{"BTLPM"                       ,	6,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"BDLLPM"                      ,	7,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNRM"                        ,	8,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	660,	"RAZ",	1,	1,	0,	0},
+	{"RTTM"                        ,	12,	1,	660,	"R/W",	0,	0,	0ull,	0ull},
+	{"ANFEM"                       ,	13,	1,	660,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_14_31"              ,	14,	18,	660,	"RAZ",	1,	1,	0,	0},
+	{"FEP"                         ,	0,	5,	661,	"RO",	0,	0,	0ull,	0ull},
+	{"GC"                          ,	5,	1,	661,	"RO",	0,	0,	1ull,	1ull},
+	{"GE"                          ,	6,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"CC"                          ,	7,	1,	661,	"RO",	0,	0,	1ull,	1ull},
+	{"CE"                          ,	8,	1,	661,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_31"               ,	9,	23,	661,	"RAZ",	1,	1,	0,	0},
+	{"DWORD1"                      ,	0,	32,	662,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD2"                      ,	0,	32,	663,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD3"                      ,	0,	32,	664,	"RO",	0,	0,	0ull,	0ull},
+	{"DWORD4"                      ,	0,	32,	665,	"RO",	0,	0,	0ull,	0ull},
+	{"CERE"                        ,	0,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"NFERE"                       ,	1,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"FERE"                        ,	2,	1,	666,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	666,	"RAZ",	1,	1,	0,	0},
+	{"ECR"                         ,	0,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_ECR"                   ,	1,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EFNFR"                       ,	2,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MULTI_EFNFR"                 ,	3,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FUF"                         ,	4,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NFEMR"                       ,	5,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEMR"                        ,	6,	1,	667,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_26"               ,	7,	20,	667,	"RAZ",	1,	1,	0,	0},
+	{"AEIMN"                       ,	27,	5,	667,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECSI"                        ,	0,	16,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"EFNFSI"                      ,	16,	16,	668,	"RO",	0,	0,	0ull,	0ull},
+	{"RTLTL"                       ,	0,	16,	669,	"R/W",	0,	0,	4143ull,	4143ull},
+	{"RTL"                         ,	16,	16,	669,	"R/W",	0,	0,	12429ull,	12429ull},
+	{"OMR"                         ,	0,	32,	670,	"R/W",	0,	1,	4294967295ull,	0},
+	{"LINK_NUM"                    ,	0,	8,	671,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_8_14"               ,	8,	7,	671,	"RAZ",	1,	1,	0,	0},
+	{"FORCE_LINK"                  ,	15,	1,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"LINK_STATE"                  ,	16,	6,	671,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	671,	"RAZ",	1,	1,	0,	0},
+	{"LPEC"                        ,	24,	8,	671,	"RO",	0,	0,	7ull,	7ull},
+	{"ACK_FREQ"                    ,	0,	8,	672,	"R/W",	0,	0,	0ull,	0ull},
+	{"N_FTS"                       ,	8,	8,	672,	"R/W",	0,	0,	128ull,	128ull},
+	{"N_FTS_CC"                    ,	16,	8,	672,	"R/W",	0,	0,	128ull,	128ull},
+	{"L0EL"                        ,	24,	3,	672,	"R/W",	0,	0,	3ull,	3ull},
+	{"L1EL"                        ,	27,	3,	672,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_30_31"              ,	30,	2,	672,	"RAZ",	1,	1,	0,	0},
+	{"OMR"                         ,	0,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"SD"                          ,	1,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"LE"                          ,	2,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RA"                          ,	3,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_4"                ,	4,	1,	673,	"RAZ",	1,	1,	0,	0},
+	{"DLLLE"                       ,	5,	1,	673,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_6"                ,	6,	1,	673,	"RAZ",	1,	1,	0,	0},
+	{"FLM"                         ,	7,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_15"               ,	8,	8,	673,	"RO",	0,	0,	1ull,	1ull},
+	{"LME"                         ,	16,	6,	673,	"R/W",	0,	0,	15ull,	15ull},
+	{"RESERVED_22_24"              ,	22,	3,	673,	"RAZ",	1,	1,	0,	0},
+	{"ECCRC"                       ,	25,	1,	673,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	673,	"RAZ",	1,	1,	0,	0},
+	{"ILST"                        ,	0,	24,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCD"                         ,	24,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACK_NAK"                     ,	25,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_30"              ,	26,	5,	674,	"RAZ",	1,	1,	0,	0},
+	{"DLLD"                        ,	31,	1,	674,	"R/W",	0,	0,	0ull,	0ull},
+	{"NTSS"                        ,	0,	4,	675,	"R/W",	0,	0,	10ull,	10ull},
+	{"RESERVED_4_7"                ,	4,	4,	675,	"RO",	1,	1,	0,	0},
+	{"NSKPS"                       ,	8,	3,	675,	"R/W",	0,	0,	3ull,	3ull},
+	{"RESERVED_11_13"              ,	11,	3,	675,	"RAZ",	1,	1,	0,	0},
+	{"TMRT"                        ,	14,	5,	675,	"R/W",	0,	0,	8ull,	8ull},
+	{"TMANLT"                      ,	19,	5,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"TMFCWT"                      ,	24,	5,	675,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	675,	"RO",	1,	1,	0,	0},
+	{"SKPIV"                       ,	0,	11,	676,	"R/W",	0,	0,	1280ull,	1280ull},
+	{"RESERVED_11_14"              ,	11,	4,	676,	"RAZ",	1,	1,	0,	0},
+	{"DFCWT"                       ,	15,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_FUN"                       ,	16,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_POIS_FILT"                 ,	17,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_BAR_MATCH"                 ,	18,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG1_FILT"                 ,	19,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_LK_FILT"                   ,	20,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TAG_ERR"               ,	21,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_RID_ERR"               ,	22,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_FUN_ERR"               ,	23,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_TC_ERR"                ,	24,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ATTR_ERR"              ,	25,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_LEN_ERR"               ,	26,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_ECRC_FILT"                 ,	27,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CPL_ECRC_FILT"             ,	28,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"MSG_CTRL"                    ,	29,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_IO_FILT"                   ,	30,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_CFG0_FILT"                 ,	31,	1,	676,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND0_DRP"                 ,	0,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"M_VEND1_DRP"                 ,	1,	1,	677,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_31"               ,	2,	30,	677,	"RAZ",	1,	1,	0,	0},
+	{"DBG_INFO_L32"                ,	0,	32,	678,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_INFO_U32"                ,	0,	32,	679,	"RO",	0,	0,	0ull,	0ull},
+	{"TPDFCC"                      ,	0,	12,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"TPHFCC"                      ,	12,	8,	680,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	680,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	681,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	681,	"RAZ",	1,	1,	0,	0},
+	{"TCDFCC"                      ,	0,	12,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"TCHFCC"                      ,	12,	8,	682,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	682,	"RAZ",	1,	1,	0,	0},
+	{"RTLPFCCNR"                   ,	0,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"TRBNE"                       ,	1,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"RQNE"                        ,	2,	1,	683,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	683,	"RAZ",	1,	1,	0,	0},
+	{"WRR_VC0"                     ,	0,	8,	684,	"RO",	0,	0,	15ull,	15ull},
+	{"WRR_VC1"                     ,	8,	8,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC2"                     ,	16,	8,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC3"                     ,	24,	8,	684,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC4"                     ,	0,	8,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC5"                     ,	8,	8,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC6"                     ,	16,	8,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"WRR_VC7"                     ,	24,	8,	685,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	686,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	686,	"R/W",	0,	0,	35ull,	35ull},
+	{"RESERVED_20_20"              ,	20,	1,	686,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	686,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_29"              ,	24,	6,	686,	"RAZ",	1,	1,	0,	0},
+	{"TYPE_ORDERING"               ,	30,	1,	686,	"R/W",	0,	0,	1ull,	1ull},
+	{"RX_QUEUE_ORDER"              ,	31,	1,	686,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATA_CREDITS"                ,	0,	12,	687,	"R/W",	0,	0,	4ull,	4ull},
+	{"HEADER_CREDITS"              ,	12,	8,	687,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_20_20"              ,	20,	1,	687,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	687,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	687,	"RAZ",	1,	1,	0,	0},
+	{"DATA_CREDITS"                ,	0,	12,	688,	"R/W",	0,	0,	128ull,	128ull},
+	{"HEADER_CREDITS"              ,	12,	8,	688,	"R/W",	0,	0,	64ull,	64ull},
+	{"RESERVED_20_20"              ,	20,	1,	688,	"RAZ",	1,	1,	0,	0},
+	{"QUEUE_MODE"                  ,	21,	3,	688,	"R/W",	0,	0,	2ull,	2ull},
+	{"RESERVED_24_31"              ,	24,	8,	688,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	689,	"R/W",	0,	0,	331ull,	331ull},
+	{"RESERVED_14_15"              ,	14,	2,	689,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	689,	"R/W",	0,	0,	41ull,	41ull},
+	{"RESERVED_26_31"              ,	26,	6,	689,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	690,	"R/W",	0,	0,	56ull,	56ull},
+	{"RESERVED_14_15"              ,	14,	2,	690,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	690,	"R/W",	0,	0,	14ull,	14ull},
+	{"RESERVED_26_31"              ,	26,	6,	690,	"RAZ",	1,	1,	0,	0},
+	{"DATA_DEPTH"                  ,	0,	14,	691,	"R/W",	0,	0,	360ull,	360ull},
+	{"RESERVED_14_15"              ,	14,	2,	691,	"RAZ",	1,	1,	0,	0},
+	{"HEADER_DEPTH"                ,	16,	10,	691,	"R/W",	0,	0,	70ull,	70ull},
+	{"RESERVED_26_31"              ,	26,	6,	691,	"RAZ",	1,	1,	0,	0},
+	{"PHY_STAT"                    ,	0,	32,	692,	"RO",	0,	0,	0ull,	0ull},
+	{"PHY_CTRL"                    ,	0,	32,	693,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_4"                ,	0,	5,	694,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	694,	"R/W",	0,	0,	1ull,	1ull},
+	{"HFD"                         ,	6,	1,	694,	"R/W",	0,	0,	1ull,	1ull},
+	{"PAUSE"                       ,	7,	2,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	694,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	694,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	694,	"RAZ",	0,	0,	0ull,	0ull},
+	{"NP"                          ,	15,	1,	694,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	694,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_11"               ,	0,	12,	695,	"RAZ",	0,	0,	0ull,	0ull},
+	{"THOU_THD"                    ,	12,	1,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_TFD"                    ,	13,	1,	695,	"RO",	0,	0,	0ull,	0ull},
+	{"THOU_XHD"                    ,	14,	1,	695,	"RO",	0,	0,	1ull,	1ull},
+	{"THOU_XFD"                    ,	15,	1,	695,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	695,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	696,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FD"                          ,	5,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"HFD"                         ,	6,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	7,	2,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_11"               ,	9,	3,	696,	"RAZ",	0,	0,	0ull,	0ull},
+	{"REM_FLT"                     ,	12,	2,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	14,	1,	696,	"RO",	0,	1,	0ull,	0},
+	{"NP"                          ,	15,	1,	696,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	696,	"RAZ",	1,	1,	0,	0},
+	{"LINK_OK"                     ,	0,	1,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	1,	1,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	2,	1,	697,	"RO",	0,	0,	0ull,	1ull},
+	{"SPD"                         ,	3,	2,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"PAUSE"                       ,	5,	2,	697,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	697,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD_EN"                   ,	0,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"XMIT_EN"                     ,	1,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_ERR_EN"                   ,	2,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFU_EN"                   ,	3,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXFIFO_EN"                   ,	4,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"TXBAD_EN"                    ,	5,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXERR_EN"                    ,	6,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	7,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXLOCK_EN"                   ,	8,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"AN_BAD_EN"                   ,	9,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNC_BAD_EN"                 ,	10,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"DUP"                         ,	11,	1,	698,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_12_63"              ,	12,	52,	698,	"RAZ",	1,	1,	0,	0},
+	{"LNKSPD"                      ,	0,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	1,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_ERR"                      ,	2,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFU"                      ,	3,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXFIFO"                      ,	4,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TXBAD"                       ,	5,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXERR"                       ,	6,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	7,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXLOCK"                      ,	8,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	9,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	10,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	11,	1,	699,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_63"              ,	12,	52,	699,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	16,	700,	"R/W",	0,	1,	1094ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	700,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	701,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	701,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	701,	"RAZ",	1,	1,	0,	0},
+	{"SAMP_PT"                     ,	0,	7,	702,	"R/W",	0,	1,	1ull,	0},
+	{"AN_OVRD"                     ,	7,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"MODE"                        ,	8,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAC_PHY"                     ,	9,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK2"                    ,	10,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"GMXENO"                      ,	11,	1,	702,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGMII"                       ,	12,	1,	702,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	702,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_4"                ,	0,	5,	703,	"RAZ",	1,	1,	0,	0},
+	{"UNI"                         ,	5,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDMSB"                      ,	6,	1,	703,	"R/W",	0,	0,	1ull,	1ull},
+	{"COLTST"                      ,	7,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"DUP"                         ,	8,	1,	703,	"R/W",	0,	0,	1ull,	1ull},
+	{"RST_AN"                      ,	9,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_10"              ,	10,	1,	703,	"RAZ",	1,	1,	0,	0},
+	{"PWR_DN"                      ,	11,	1,	703,	"R/W",	0,	0,	1ull,	0ull},
+	{"AN_EN"                       ,	12,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"SPDLSB"                      ,	13,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOPBCK1"                    ,	14,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	703,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	703,	"RAZ",	1,	1,	0,	0},
+	{"EXTND"                       ,	0,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	704,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LNK_ST"                      ,	2,	1,	704,	"RO",	0,	0,	0ull,	1ull},
+	{"AN_ABIL"                     ,	3,	1,	704,	"RO",	0,	0,	1ull,	1ull},
+	{"RM_FLT"                      ,	4,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_CPT"                      ,	5,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"PRB_SUP"                     ,	6,	1,	704,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_7"                ,	7,	1,	704,	"RAZ",	0,	0,	0ull,	0ull},
+	{"EXT_ST"                      ,	8,	1,	704,	"RO",	0,	0,	1ull,	1ull},
+	{"HUN_T2HD"                    ,	9,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T2FD"                    ,	10,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_HD"                      ,	11,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"TEN_FD"                      ,	12,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XHD"                     ,	13,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_XFD"                     ,	14,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"HUN_T4"                      ,	15,	1,	704,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	704,	"RAZ",	1,	1,	0,	0},
+	{"AN_ST"                       ,	0,	4,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"AN_BAD"                      ,	4,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	5,	4,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC_BAD"                    ,	9,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_ST"                       ,	10,	5,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"RX_BAD"                      ,	15,	1,	705,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	705,	"RAZ",	1,	1,	0,	0},
+	{"BIT_LOCK"                    ,	0,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"SYNC"                        ,	1,	1,	706,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	706,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	707,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	707,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	707,	"R/W",	0,	0,	2ull,	2ull},
+	{"DUP"                         ,	12,	1,	707,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_13_13"              ,	13,	1,	707,	"RAZ",	0,	1,	0ull,	0},
+	{"ACK"                         ,	14,	1,	707,	"RO",	0,	0,	0ull,	0ull},
+	{"LINK"                        ,	15,	1,	707,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	707,	"RAZ",	1,	1,	0,	0},
+	{"ONE"                         ,	0,	1,	708,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_9"                ,	1,	9,	708,	"RAZ",	0,	1,	0ull,	0},
+	{"SPEED"                       ,	10,	2,	708,	"RO",	0,	0,	0ull,	2ull},
+	{"DUP"                         ,	12,	1,	708,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_14"              ,	13,	2,	708,	"RAZ",	0,	1,	0ull,	0},
+	{"LINK"                        ,	15,	1,	708,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_16_63"              ,	16,	48,	708,	"RAZ",	1,	1,	0,	0},
+	{"ORD_ST"                      ,	0,	4,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"TX_BAD"                      ,	4,	1,	709,	"RO",	0,	0,	0ull,	0ull},
+	{"XMIT"                        ,	5,	2,	709,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_7_63"               ,	7,	57,	709,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"AUTORXPL"                    ,	2,	1,	710,	"RO",	0,	0,	0ull,	0ull},
+	{"RXOVRD"                      ,	3,	1,	710,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	710,	"RAZ",	1,	1,	0,	0},
+	{"L0SYNC"                      ,	0,	1,	711,	"RO",	0,	0,	0ull,	1ull},
+	{"L1SYNC"                      ,	1,	1,	711,	"RO",	0,	0,	0ull,	1ull},
+	{"L2SYNC"                      ,	2,	1,	711,	"RO",	0,	0,	0ull,	1ull},
+	{"L3SYNC"                      ,	3,	1,	711,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_4_10"               ,	4,	7,	711,	"RAZ",	1,	1,	0,	0},
+	{"PATTST"                      ,	11,	1,	711,	"RO",	0,	0,	0ull,	0ull},
+	{"ALIGND"                      ,	12,	1,	711,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_13_63"              ,	13,	51,	711,	"RAZ",	1,	1,	0,	0},
+	{"BIST_STATUS"                 ,	0,	1,	712,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	712,	"RAZ",	1,	1,	0,	0},
+	{"BITLCK0"                     ,	0,	1,	713,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK1"                     ,	1,	1,	713,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK2"                     ,	2,	1,	713,	"RO",	0,	1,	0ull,	0},
+	{"BITLCK3"                     ,	3,	1,	713,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	713,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	714,	"RAZ",	1,	1,	0,	0},
+	{"SPD"                         ,	2,	4,	714,	"RO",	0,	0,	0ull,	0ull},
+	{"SPDSEL0"                     ,	6,	1,	714,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_7_10"               ,	7,	4,	714,	"RAZ",	1,	1,	0,	0},
+	{"LO_PWR"                      ,	11,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_12"              ,	12,	1,	714,	"RAZ",	1,	1,	0,	0},
+	{"SPDSEL1"                     ,	13,	1,	714,	"RO",	0,	0,	1ull,	1ull},
+	{"LOOPBCK1"                    ,	14,	1,	714,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	15,	1,	714,	"R/W",	0,	0,	1ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	714,	"RAZ",	1,	1,	0,	0},
+	{"TYPE"                        ,	0,	2,	715,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	715,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT_EN"                    ,	0,	1,	716,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXBAD_EN"                    ,	1,	1,	716,	"R/W",	0,	0,	0ull,	1ull},
+	{"RXSYNBAD_EN"                 ,	2,	1,	716,	"R/W",	0,	0,	0ull,	1ull},
+	{"BITLCKLS_EN"                 ,	3,	1,	716,	"R/W",	0,	0,	0ull,	1ull},
+	{"SYNLOS_EN"                   ,	4,	1,	716,	"R/W",	0,	0,	0ull,	1ull},
+	{"ALGNLOS_EN"                  ,	5,	1,	716,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_6_63"               ,	6,	58,	716,	"RAZ",	1,	1,	0,	0},
+	{"TXFLT"                       ,	0,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXBAD"                       ,	1,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXSYNBAD"                    ,	2,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BITLCKLS"                    ,	3,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SYNLOS"                      ,	4,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ALGNLOS"                     ,	5,	1,	717,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	717,	"RAZ",	1,	1,	0,	0},
+	{"PKT_SZ"                      ,	0,	2,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"LA_EN"                       ,	2,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"LAFIFOVFL"                   ,	3,	1,	718,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DROP_LN"                     ,	4,	2,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENC_MODE"                    ,	6,	1,	718,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	718,	"RAZ",	1,	1,	0,	0},
+	{"GMXENO"                      ,	0,	1,	719,	"R/W",	0,	0,	0ull,	0ull},
+	{"XAUI"                        ,	1,	1,	719,	"RO",	1,	1,	0,	0},
+	{"RX_SWAP"                     ,	2,	1,	719,	"R/W",	0,	1,	0ull,	0},
+	{"TX_SWAP"                     ,	3,	1,	719,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_4_63"               ,	4,	60,	719,	"RAZ",	1,	1,	0,	0},
+	{"SYNC0ST"                     ,	0,	4,	720,	"RO",	0,	1,	0ull,	0},
+	{"SYNC1ST"                     ,	4,	4,	720,	"RO",	0,	1,	0ull,	0},
+	{"SYNC2ST"                     ,	8,	4,	720,	"RO",	0,	1,	0ull,	0},
+	{"SYNC3ST"                     ,	12,	4,	720,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	720,	"RAZ",	1,	1,	0,	0},
+	{"TENGB"                       ,	0,	1,	721,	"RO",	0,	0,	1ull,	1ull},
+	{"TENPASST"                    ,	1,	1,	721,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	721,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	722,	"RAZ",	1,	1,	0,	0},
+	{"LPABLE"                      ,	1,	1,	722,	"RO",	0,	0,	1ull,	1ull},
+	{"RCV_LNK"                     ,	2,	1,	722,	"RO",	0,	0,	0ull,	1ull},
+	{"RESERVED_3_6"                ,	3,	4,	722,	"RAZ",	1,	1,	0,	0},
+	{"FLT"                         ,	7,	1,	722,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	722,	"RAZ",	1,	1,	0,	0},
+	{"TENGB_R"                     ,	0,	1,	723,	"RO",	0,	0,	0ull,	0ull},
+	{"TENGB_X"                     ,	1,	1,	723,	"RO",	0,	0,	1ull,	1ull},
+	{"TENGB_W"                     ,	2,	1,	723,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_9"                ,	3,	7,	723,	"RAZ",	1,	1,	0,	0},
+	{"RCVFLT"                      ,	10,	1,	723,	"RC",	0,	0,	0ull,	0ull},
+	{"XMTFLT"                      ,	11,	1,	723,	"RC",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_13"              ,	12,	2,	723,	"RAZ",	1,	1,	0,	0},
+	{"DEV"                         ,	14,	2,	723,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_16_63"              ,	16,	48,	723,	"RAZ",	1,	1,	0,	0},
+	{"TXPLRT"                      ,	0,	1,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXPLRT"                      ,	1,	1,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_TXPLRT"                  ,	2,	4,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"XOR_RXPLRT"                  ,	6,	4,	724,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	724,	"RAZ",	1,	1,	0,	0},
+	{"TX_ST"                       ,	0,	3,	725,	"RO",	0,	1,	0ull,	0},
+	{"RX_ST"                       ,	3,	2,	725,	"RO",	0,	1,	0ull,	0},
+	{"ALGN_ST"                     ,	5,	3,	725,	"RO",	0,	1,	0ull,	0},
+	{"RXBAD"                       ,	8,	1,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN0BAD"                     ,	9,	1,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN1BAD"                     ,	10,	1,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN2BAD"                     ,	11,	1,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"SYN3BAD"                     ,	12,	1,	725,	"RO",	0,	0,	0ull,	0ull},
+	{"TERM_ERR"                    ,	13,	1,	725,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	725,	"RAZ",	1,	1,	0,	0},
+	{"SOT"                         ,	0,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR0"                      ,	1,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQHDR1"                      ,	2,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA4"                     ,	3,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA3"                     ,	4,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA2"                     ,	5,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA1"                     ,	6,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA0"                     ,	7,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RETRY"                       ,	8,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"PTLP_OR"                     ,	9,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"NTLP_OR"                     ,	10,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"CTLP_OR"                     ,	11,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RQDATA5"                     ,	12,	1,	726,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	726,	"RAZ",	1,	1,	0,	0},
+	{"PPF"                         ,	0,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TC0"                     ,	1,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TCF1"                    ,	2,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TNF"                     ,	3,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF0"                    ,	4,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PEF_TPF1"                    ,	5,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"RSL_P2E"                     ,	6,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"PEAI_P2E"                    ,	7,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"DBG_P2E"                     ,	8,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_RSL"                     ,	9,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_P"                       ,	10,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_N"                       ,	11,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"E2P_CPL"                     ,	12,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"CTO_P2E"                     ,	13,	1,	727,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_63"              ,	14,	50,	727,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	32,	728,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	728,	"R/W",	0,	1,	0ull,	0},
+	{"ADDR"                        ,	0,	32,	729,	"R/W",	0,	1,	0ull,	0},
+	{"DATA"                        ,	32,	32,	729,	"R/W",	0,	1,	0ull,	0},
+	{"TAG"                         ,	0,	32,	730,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	730,	"RAZ",	1,	1,	0,	0},
+	{"INV_LCRC"                    ,	0,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"INV_ECRC"                    ,	1,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_2"                ,	2,	1,	731,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RO_CTLP"                     ,	3,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"LNK_ENB"                     ,	4,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"DLY_ONE"                     ,	5,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"NF_ECRC"                     ,	6,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_8"                ,	7,	2,	731,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OB_P_CMD"                    ,	9,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XPME"                     ,	10,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"PM_XTOFF"                    ,	11,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"LANE_SWP"                    ,	12,	1,	731,	"R/W",	0,	0,	0ull,	0ull},
+	{"QLM_CFG"                     ,	13,	2,	731,	"RO",	1,	1,	0,	0},
+	{"PBUS"                        ,	15,	8,	731,	"RO",	1,	1,	0,	0},
+	{"DNUM"                        ,	23,	5,	731,	"RO",	1,	1,	0,	0},
+	{"RESERVED_28_63"              ,	28,	36,	731,	"RAZ",	1,	1,	0,	0},
+	{"PCIERST"                     ,	0,	1,	732,	"RO",	0,	0,	0ull,	0ull},
+	{"PCLK_RUN"                    ,	1,	1,	732,	"R/W1C",	0,	0,	0ull,	1ull},
+	{"RESERVED_2_63"               ,	2,	62,	732,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	733,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	733,	"RAZ",	1,	1,	0,	0},
+	{"SPOISON"                     ,	0,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPMAL"                     ,	1,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTLPLLE"                     ,	2,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RECRCE"                      ,	3,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPOISON"                     ,	4,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RCEMRC"                      ,	5,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNFEMRC"                     ,	6,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RFEMRC"                      ,	7,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPMERC"                      ,	8,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPTAMRC"                     ,	9,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RUMEP"                       ,	10,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RVDM"                        ,	11,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACTO"                        ,	12,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTE"                         ,	13,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"MRE"                         ,	14,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RDWDLE"                      ,	15,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RTWDLE"                      ,	16,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"DPEOOSD"                     ,	17,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCPVWT"                      ,	18,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RPE"                         ,	19,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"FCUV"                        ,	20,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQO"                         ,	21,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAUC"                        ,	22,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACUR"                       ,	23,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACCA"                       ,	24,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"CAAR"                        ,	25,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RARWDNS"                     ,	26,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAMTLP"                      ,	27,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RACPP"                       ,	28,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWWPP"                      ,	29,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"ECRC_E"                      ,	30,	1,	734,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_63"              ,	31,	33,	734,	"RAZ",	1,	1,	0,	0},
+	{"AUX_EN"                      ,	0,	1,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_EN"                       ,	1,	1,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_STAT"                     ,	2,	1,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"PM_DST"                      ,	3,	1,	735,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	735,	"RO",	1,	1,	0,	0},
+	{"RESERVED_0_13"               ,	0,	14,	736,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	14,	50,	736,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_25"               ,	0,	26,	737,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	26,	38,	737,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_38"               ,	0,	39,	738,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	39,	25,	738,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_0_11"               ,	0,	12,	739,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	739,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"RESERVED_0_11"               ,	0,	12,	740,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	12,	52,	740,	"R/W",	0,	1,	4503599627370495ull,	0},
+	{"NPEI_P"                      ,	0,	8,	741,	"R/W",	0,	0,	128ull,	128ull},
+	{"NPEI_NP"                     ,	8,	8,	741,	"R/W",	0,	0,	16ull,	16ull},
+	{"NPEI_CPL"                    ,	16,	8,	741,	"R/W",	0,	0,	128ull,	128ull},
+	{"PESC_P"                      ,	24,	8,	741,	"R/W",	0,	0,	128ull,	128ull},
+	{"PESC_NP"                     ,	32,	8,	741,	"R/W",	0,	0,	16ull,	16ull},
+	{"PESC_CPL"                    ,	40,	8,	741,	"R/W",	0,	0,	128ull,	128ull},
+	{"PEAI_PPF"                    ,	48,	8,	741,	"R/W",	0,	0,	128ull,	128ull},
+	{"RESERVED_56_63"              ,	56,	8,	741,	"RAZ",	1,	1,	0,	0},
+	{"BIST"                        ,	0,	18,	742,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	742,	"RAZ",	1,	1,	0,	0},
+	{"DPRT"                        ,	0,	16,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"UDP"                         ,	16,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP"                         ,	17,	1,	743,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_18_63"              ,	18,	46,	743,	"RAZ",	1,	1,	0,	0},
+	{"MAP0"                        ,	0,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	744,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP0"                        ,	0,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP1"                        ,	4,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP2"                        ,	8,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP3"                        ,	12,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP4"                        ,	16,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP5"                        ,	20,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP6"                        ,	24,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP7"                        ,	28,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP8"                        ,	32,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP9"                        ,	36,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP10"                       ,	40,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP11"                       ,	44,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP12"                       ,	48,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP13"                       ,	52,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP14"                       ,	56,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAP15"                       ,	60,	4,	745,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINLEN"                      ,	0,	16,	746,	"R/W",	0,	0,	64ull,	64ull},
+	{"MAXLEN"                      ,	16,	16,	746,	"R/W",	0,	0,	1536ull,	1536ull},
+	{"RESERVED_32_63"              ,	32,	32,	746,	"RAZ",	1,	1,	0,	0},
+	{"NIP_SHF"                     ,	0,	3,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	747,	"RAZ",	1,	1,	0,	0},
+	{"RAW_SHF"                     ,	8,	3,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_15"              ,	11,	5,	747,	"RAZ",	1,	1,	0,	0},
+	{"MAX_L2"                      ,	16,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_UDP"                     ,	17,	1,	747,	"R/W",	0,	0,	1ull,	1ull},
+	{"TAG_SYN"                     ,	18,	1,	747,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_63"              ,	19,	45,	747,	"RAZ",	1,	1,	0,	0},
+	{"IP_CHK"                      ,	0,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_MAL"                      ,	1,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP_HOP"                      ,	2,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP4_OPTS"                    ,	3,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"IP6_EEXT"                    ,	4,	2,	748,	"R/W",	0,	0,	1ull,	3ull},
+	{"RESERVED_6_7"                ,	6,	2,	748,	"RAZ",	1,	1,	0,	0},
+	{"L4_MAL"                      ,	8,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_PRT"                      ,	9,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_CHK"                      ,	10,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"L4_LEN"                      ,	11,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCP_FLAG"                    ,	12,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"L2_MAL"                      ,	13,	1,	748,	"R/W",	0,	0,	1ull,	1ull},
+	{"VS_QOS"                      ,	14,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"VS_WQE"                      ,	15,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNRS"                       ,	16,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_19"              ,	17,	3,	748,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RING_EN"                     ,	20,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	748,	"RAZ",	1,	1,	0,	0},
+	{"DSA_GRP_SID"                 ,	24,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_SCMD"                ,	25,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_GRP_TVID"                ,	26,	1,	748,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_63"              ,	27,	37,	748,	"RAZ",	1,	1,	0,	0},
+	{"PRI"                         ,	0,	6,	749,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_6_7"                ,	6,	2,	749,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	8,	3,	749,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_11_11"              ,	11,	1,	749,	"RAZ",	1,	1,	0,	0},
+	{"UP_QOS"                      ,	12,	1,	749,	"RAZ",	0,	1,	0ull,	0},
+	{"RESERVED_13_63"              ,	13,	51,	749,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	750,	"RAZ",	1,	1,	0,	0},
+	{"BCKPRS"                      ,	2,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	750,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	750,	"RAZ",	1,	1,	0,	0},
+	{"PKTDRP"                      ,	0,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_1"                ,	1,	1,	751,	"RAZ",	1,	1,	0,	0},
+	{"BCKPRS"                      ,	2,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTNXA"                      ,	3,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BADTAG"                      ,	4,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SKPRUNT"                     ,	5,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TODOOVR"                     ,	6,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FEPERR"                      ,	7,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BEPERR"                      ,	8,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MINERR"                      ,	9,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MAXERR"                      ,	10,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LENERR"                      ,	11,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PUNYERR"                     ,	12,	1,	751,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_63"              ,	13,	51,	751,	"RAZ",	1,	1,	0,	0},
+	{"OFFSET"                      ,	0,	3,	752,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	752,	"RAZ",	1,	1,	0,	0},
+	{"SKIP"                        ,	0,	7,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	753,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	8,	2,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"DSA_EN"                      ,	10,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"HIGIG_EN"                    ,	11,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"CRC_EN"                      ,	12,	1,	753,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	753,	"RAZ",	1,	1,	0,	0},
+	{"QOS_VLAN"                    ,	16,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_DIFF"                    ,	17,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VOD"                     ,	18,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_VSEL"                    ,	19,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS_WAT"                     ,	20,	4,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"QOS"                         ,	24,	3,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"HG_QOS"                      ,	27,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT"                     ,	28,	4,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"INST_HDR"                    ,	32,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"DYN_RS"                      ,	33,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_INC"                     ,	34,	2,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RAWDRP"                      ,	36,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_37_39"              ,	37,	3,	753,	"RAZ",	1,	1,	0,	0},
+	{"QOS_WAT_47"                  ,	40,	4,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRP_WAT_47"                  ,	44,	4,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"MINERR_EN"                   ,	48,	1,	753,	"R/W",	0,	0,	1ull,	1ull},
+	{"MAXERR_EN"                   ,	49,	1,	753,	"R/W",	0,	0,	1ull,	1ull},
+	{"LENERR_EN"                   ,	50,	1,	753,	"R/W",	0,	0,	1ull,	1ull},
+	{"VLAN_LEN"                    ,	51,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"PAD_LEN"                     ,	52,	1,	753,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_53_63"              ,	53,	11,	753,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	0,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"NON_TAG_TYPE"                ,	4,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_TAG_TYPE"                ,	6,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_TAG_TYPE"                ,	8,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP4_TAG_TYPE"               ,	10,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"TCP6_TAG_TYPE"               ,	12,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SRC_FLAG"                ,	14,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SRC_FLAG"                ,	15,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DST_FLAG"                ,	16,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DST_FLAG"                ,	17,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_PCTL_FLAG"               ,	18,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_NXTH_FLAG"               ,	19,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_SPRT_FLAG"               ,	20,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_SPRT_FLAG"               ,	21,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP4_DPRT_FLAG"               ,	22,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"IP6_DPRT_FLAG"               ,	23,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_PRT_FLAG"                ,	24,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VLAN"                    ,	25,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC_VS"                      ,	26,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"TAG_MODE"                    ,	28,	2,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG_MSKIP"                ,	30,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAG"                      ,	31,	1,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGMASK"                  ,	32,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"GRPTAGBASE"                  ,	36,	4,	754,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	754,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	755,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	755,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	0,	3,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	756,	"RAZ",	1,	1,	0,	0},
+	{"QOS1"                        ,	4,	3,	756,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	756,	"RAZ",	1,	1,	0,	0},
+	{"MATCH_VALUE"                 ,	0,	16,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"MATCH_TYPE"                  ,	16,	3,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_19"              ,	19,	1,	757,	"RAZ",	1,	1,	0,	0},
+	{"QOS"                         ,	20,	3,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	757,	"RAZ",	1,	1,	0,	0},
+	{"GRP"                         ,	24,	4,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_28_31"              ,	28,	4,	757,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	32,	16,	757,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	757,	"RAZ",	1,	1,	0,	0},
+	{"WORD"                        ,	0,	56,	758,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_56_63"              ,	56,	8,	758,	"RAZ",	1,	1,	0,	0},
+	{"RST"                         ,	0,	1,	759,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	759,	"RAZ",	1,	1,	0,	0},
+	{"DRP_OCTS"                    ,	0,	32,	760,	"R/W",	0,	1,	0ull,	0},
+	{"DRP_PKTS"                    ,	32,	32,	760,	"R/W",	0,	1,	0ull,	0},
+	{"OCTS"                        ,	0,	48,	761,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	761,	"RAZ",	1,	1,	0,	0},
+	{"RAW"                         ,	0,	32,	762,	"R/W",	0,	1,	0ull,	0},
+	{"PKTS"                        ,	32,	32,	762,	"R/W",	0,	1,	0ull,	0},
+	{"MCST"                        ,	0,	32,	763,	"R/W",	0,	1,	0ull,	0},
+	{"BCST"                        ,	32,	32,	763,	"R/W",	0,	1,	0ull,	0},
+	{"H64"                         ,	0,	32,	764,	"R/W",	0,	1,	0ull,	0},
+	{"H65TO127"                    ,	32,	32,	764,	"R/W",	0,	1,	0ull,	0},
+	{"H128TO255"                   ,	0,	32,	765,	"R/W",	0,	1,	0ull,	0},
+	{"H256TO511"                   ,	32,	32,	765,	"R/W",	0,	1,	0ull,	0},
+	{"H512TO1023"                  ,	0,	32,	766,	"R/W",	0,	1,	0ull,	0},
+	{"H1024TO1518"                 ,	32,	32,	766,	"R/W",	0,	1,	0ull,	0},
+	{"H1519"                       ,	0,	32,	767,	"R/W",	0,	1,	0ull,	0},
+	{"FCS"                         ,	32,	32,	767,	"R/W",	0,	1,	0ull,	0},
+	{"UNDERSZ"                     ,	0,	32,	768,	"R/W",	0,	1,	0ull,	0},
+	{"FRAG"                        ,	32,	32,	768,	"R/W",	0,	1,	0ull,	0},
+	{"OVERSZ"                      ,	0,	32,	769,	"R/W",	0,	1,	0ull,	0},
+	{"JABBER"                      ,	32,	32,	769,	"R/W",	0,	1,	0ull,	0},
+	{"RDCLR"                       ,	0,	1,	770,	"R/W",	0,	0,	1ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	770,	"RAZ",	1,	1,	0,	0},
+	{"ERRS"                        ,	0,	16,	771,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_16_63"              ,	16,	48,	771,	"RAZ",	1,	1,	0,	0},
+	{"OCTS"                        ,	0,	48,	772,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	772,	"RAZ",	1,	1,	0,	0},
+	{"PKTS"                        ,	0,	32,	773,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	773,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	8,	774,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_8_63"               ,	8,	56,	774,	"RAZ",	1,	1,	0,	0},
+	{"MASK"                        ,	0,	16,	775,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	775,	"RAZ",	1,	1,	0,	0},
+	{"SRC"                         ,	0,	16,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"DST"                         ,	16,	16,	776,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	776,	"RAZ",	1,	1,	0,	0},
+	{"ENTRY"                       ,	0,	62,	777,	"RO",	1,	1,	0,	0},
+	{"RESERVED_62_62"              ,	62,	1,	777,	"RAZ",	1,	1,	0,	0},
+	{"VAL"                         ,	63,	1,	777,	"RO",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	32,	778,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	778,	"RAZ",	1,	1,	0,	0},
+	{"COUNT"                       ,	0,	48,	779,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	779,	"RAZ",	1,	1,	0,	0},
+	{"SIZE"                        ,	0,	16,	780,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	780,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	780,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	780,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	781,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	781,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	781,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	781,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	781,	"RO",	1,	0,	0,	0ull},
+	{"PTRS2"                       ,	0,	17,	782,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS1"                       ,	32,	17,	782,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	782,	"RAZ",	1,	0,	0,	0ull},
+	{"MOD"                         ,	0,	3,	783,	"RO",	1,	0,	0,	0ull},
+	{"CNT"                         ,	3,	13,	783,	"RO",	1,	0,	0,	0ull},
+	{"CHK"                         ,	16,	1,	783,	"RO",	1,	0,	0,	0ull},
+	{"LEN"                         ,	17,	1,	783,	"RO",	1,	0,	0,	0ull},
+	{"SOP"                         ,	18,	1,	783,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	19,	3,	783,	"RO",	1,	0,	0,	0ull},
+	{"MAJ"                         ,	22,	1,	783,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	783,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	16,	784,	"RO",	1,	0,	0,	0ull},
+	{"SEGS"                        ,	16,	6,	784,	"RO",	1,	0,	0,	0ull},
+	{"CMD"                         ,	22,	14,	784,	"RO",	1,	0,	0,	0ull},
+	{"FAU"                         ,	36,	28,	784,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	785,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	785,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	785,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	785,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	785,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	786,	"RO",	1,	0,	0,	0ull},
+	{"PTR"                         ,	0,	40,	787,	"RO",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	40,	16,	787,	"RO",	1,	0,	0,	0ull},
+	{"POOL"                        ,	56,	3,	787,	"RO",	1,	0,	0,	0ull},
+	{"BACK"                        ,	59,	4,	787,	"RO",	1,	0,	0,	0ull},
+	{"I"                           ,	63,	1,	787,	"RO",	1,	0,	0,	0ull},
+	{"DATA"                        ,	0,	64,	788,	"RO",	1,	0,	0,	0ull},
+	{"MAJOR"                       ,	0,	3,	789,	"RO",	1,	0,	0,	0ull},
+	{"MINOR"                       ,	3,	2,	789,	"RO",	1,	0,	0,	0ull},
+	{"WAIT"                        ,	5,	1,	789,	"RO",	1,	0,	0,	0ull},
+	{"CHK_MODE"                    ,	6,	1,	789,	"RO",	1,	0,	0,	0ull},
+	{"CHK_ONCE"                    ,	7,	1,	789,	"RO",	1,	0,	0,	0ull},
+	{"INIT_DWRITE"                 ,	8,	1,	789,	"RO",	1,	0,	0,	0ull},
+	{"DREAD_SOP"                   ,	9,	1,	789,	"RO",	1,	0,	0,	0ull},
+	{"UID"                         ,	10,	2,	789,	"RO",	1,	0,	0,	0ull},
+	{"CMND_OFF"                    ,	12,	6,	789,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SIZ"                    ,	18,	16,	789,	"RO",	1,	0,	0,	0ull},
+	{"CMND_SEGS"                   ,	34,	6,	789,	"RO",	1,	0,	0,	0ull},
+	{"CURR_OFF"                    ,	40,	16,	789,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	56,	8,	789,	"RO",	1,	0,	0,	0ull},
+	{"CURR_SIZ"                    ,	0,	8,	790,	"RO",	1,	0,	0,	0ull},
+	{"CURR_PTR"                    ,	8,	40,	790,	"RO",	1,	0,	0,	0ull},
+	{"NXT_INFLT"                   ,	48,	6,	790,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_54_63"              ,	54,	10,	790,	"RAZ",	1,	0,	0,	0ull},
+	{"QID_BASE"                    ,	0,	8,	791,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFF"                     ,	8,	4,	791,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFMAX"                  ,	12,	4,	791,	"RO",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	16,	5,	791,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	21,	3,	791,	"RO",	1,	0,	0,	0ull},
+	{"STATC"                       ,	24,	1,	791,	"RO",	1,	0,	0,	0ull},
+	{"ACTIVE"                      ,	25,	1,	791,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTED"                   ,	26,	1,	791,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	27,	1,	791,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	791,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFTHS"                  ,	29,	4,	791,	"RO",	1,	0,	0,	0ull},
+	{"QID_OFFRES"                  ,	33,	4,	791,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_37_63"              ,	37,	27,	791,	"RAZ",	1,	0,	0,	0ull},
+	{"QCB_RIDX"                    ,	0,	6,	792,	"RO",	1,	0,	0,	0ull},
+	{"QCB_WIDX"                    ,	6,	6,	792,	"RO",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	12,	33,	792,	"RO",	1,	0,	0,	0ull},
+	{"BUF_SIZ"                     ,	45,	13,	792,	"RO",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	58,	1,	792,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	59,	5,	792,	"RO",	1,	0,	0,	0ull},
+	{"QOS"                         ,	0,	3,	793,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	3,	1,	793,	"RO",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	4,	1,	793,	"RO",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	5,	1,	793,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTEE"                   ,	6,	1,	793,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"DOORBELL"                    ,	8,	20,	793,	"RO",	1,	0,	0,	0ull},
+	{"PREEMPTER"                   ,	28,	1,	793,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_29_63"              ,	29,	35,	793,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS3"                       ,	0,	17,	794,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"PTRS0"                       ,	32,	17,	794,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_49_63"              ,	49,	15,	794,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	795,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	795,	"R/W",	1,	0,	0,	0ull},
+	{"BP_PORT"                     ,	10,	6,	795,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_16_52"              ,	16,	37,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	795,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	61,	1,	795,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_62_63"              ,	62,	2,	795,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	796,	"R/W",	1,	0,	0,	0ull},
+	{"EID"                         ,	6,	4,	796,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_10_52"              ,	10,	43,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	796,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	796,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	797,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_PKT"                    ,	8,	24,	797,	"R/W",	1,	0,	0,	0ull},
+	{"RATE_WORD"                   ,	32,	19,	797,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_51_63"              ,	51,	13,	797,	"RAZ",	1,	0,	0,	0ull},
+	{"PID"                         ,	0,	6,	798,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_6_7"                ,	6,	2,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"RATE_LIM"                    ,	8,	24,	798,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	798,	"RAZ",	1,	0,	0,	0ull},
+	{"QUEUE"                       ,	0,	7,	799,	"R/W",	1,	0,	0,	0ull},
+	{"PORT"                        ,	7,	6,	799,	"WR0",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	13,	3,	799,	"WR0",	1,	0,	0,	0ull},
+	{"TAIL"                        ,	16,	1,	799,	"R/W",	1,	0,	0,	0ull},
+	{"BUF_PTR"                     ,	17,	36,	799,	"R/W",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	799,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_Q"                    ,	61,	1,	799,	"R/W",	1,	0,	0,	0ull},
+	{"STATIC_P"                    ,	62,	1,	799,	"R/W",	1,	0,	0,	0ull},
+	{"S_TAIL"                      ,	63,	1,	799,	"R/W",	1,	0,	0,	0ull},
+	{"QID"                         ,	0,	7,	800,	"R/W",	1,	0,	0,	0ull},
+	{"PID"                         ,	7,	6,	800,	"WR0",	1,	0,	0,	0ull},
+	{"RESERVED_13_52"              ,	13,	40,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"QOS_MASK"                    ,	53,	8,	800,	"R/W",	1,	0,	0,	0ull},
+	{"RESERVED_61_63"              ,	61,	3,	800,	"RAZ",	1,	0,	0,	0ull},
+	{"DAT_PTR"                     ,	0,	4,	801,	"RO",	1,	0,	0,	0ull},
+	{"DAT_DAT"                     ,	4,	2,	801,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CTL"                     ,	6,	2,	801,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QSB"                     ,	8,	3,	801,	"RO",	1,	0,	0,	0ull},
+	{"PRT_QCB"                     ,	11,	2,	801,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	13,	2,	801,	"RO",	1,	0,	0,	0ull},
+	{"PRT_PSB"                     ,	15,	8,	801,	"RO",	1,	0,	0,	0ull},
+	{"PRT_NXT"                     ,	23,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"PRT_CHK"                     ,	24,	3,	801,	"RO",	1,	0,	0,	0ull},
+	{"OUT_WIF"                     ,	27,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"OUT_STA"                     ,	28,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"OUT_CTL"                     ,	29,	3,	801,	"RO",	1,	0,	0,	0ull},
+	{"OUT_DAT"                     ,	32,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"IOB"                         ,	33,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"CSR"                         ,	34,	1,	801,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_35_63"              ,	35,	29,	801,	"RAZ",	1,	0,	0,	0ull},
+	{"SIZE"                        ,	0,	13,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_19"              ,	13,	7,	802,	"RAZ",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	20,	3,	802,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_63"              ,	23,	41,	802,	"RAZ",	1,	0,	0,	0ull},
+	{"ASSERTS"                     ,	0,	64,	803,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	804,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	805,	"RO",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	64,	806,	"RO",	0,	0,	0ull,	0ull},
+	{"ENGINE0"                     ,	0,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE1"                     ,	4,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE2"                     ,	8,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE3"                     ,	12,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE4"                     ,	16,	4,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE5"                     ,	20,	4,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE6"                     ,	24,	4,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE7"                     ,	28,	4,	807,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENGINE8"                     ,	32,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
+	{"ENGINE9"                     ,	36,	4,	807,	"R/W",	0,	0,	4ull,	4ull},
+	{"RESERVED_40_63"              ,	40,	24,	807,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	10,	808,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_63"              ,	10,	54,	808,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	809,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	809,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	809,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	809,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA_PKO"                     ,	0,	1,	810,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENA_DWB"                     ,	1,	1,	810,	"R/W",	0,	0,	0ull,	0ull},
+	{"STORE_BE"                    ,	2,	1,	810,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	3,	1,	810,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	810,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE0"                       ,	0,	3,	811,	"R/W",	0,	0,	2ull,	2ull},
+	{"MODE1"                       ,	3,	3,	811,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	811,	"RAZ",	1,	0,	0,	0ull},
+	{"PARITY"                      ,	0,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	1,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURRZERO"                    ,	2,	1,	812,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	812,	"RAZ",	1,	0,	0,	0ull},
+	{"MODE"                        ,	0,	2,	813,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	813,	"RAZ",	1,	0,	0,	0ull},
+	{"QID7"                        ,	0,	1,	814,	"R/W",	0,	0,	0ull,	0ull},
+	{"IDX3"                        ,	1,	1,	814,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	814,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	815,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	815,	"RAZ",	1,	0,	0,	0ull},
+	{"ADR"                         ,	0,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"PEND"                        ,	1,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR0"                        ,	2,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"NBR1"                        ,	3,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"FIDX"                        ,	4,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	5,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT0"                        ,	6,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"NBT1"                        ,	7,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"CAM"                         ,	8,	1,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_15"               ,	9,	7,	816,	"RAZ",	1,	1,	0,	0},
+	{"PP"                          ,	16,	4,	816,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	816,	"RAZ",	1,	1,	0,	0},
+	{"DS_PC"                       ,	0,	32,	817,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	817,	"RAZ",	1,	1,	0,	0},
+	{"SBE"                         ,	0,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBE"                         ,	1,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SBE_IE"                      ,	2,	1,	818,	"R/W",	0,	1,	0ull,	0},
+	{"DBE_IE"                      ,	3,	1,	818,	"R/W",	0,	1,	0ull,	0},
+	{"SYN"                         ,	4,	5,	818,	"RO",	1,	1,	0,	0},
+	{"RESERVED_9_11"               ,	9,	3,	818,	"RAZ",	1,	1,	0,	0},
+	{"RPE"                         ,	12,	1,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RPE_IE"                      ,	13,	1,	818,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_14_15"              ,	14,	2,	818,	"RAZ",	1,	1,	0,	0},
+	{"IOP"                         ,	16,	13,	818,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_29_31"              ,	29,	3,	818,	"RAZ",	1,	1,	0,	0},
+	{"IOP_IE"                      ,	32,	13,	818,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_45_63"              ,	45,	19,	818,	"RAZ",	1,	1,	0,	0},
+	{"NBR_THR"                     ,	0,	5,	819,	"R/W",	0,	0,	2ull,	2ull},
+	{"PFR_DIS"                     ,	5,	1,	819,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	819,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	820,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	820,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	32,	821,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	821,	"RAZ",	1,	1,	0,	0},
+	{"IQ_INT"                      ,	0,	8,	822,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	822,	"RAZ",	1,	1,	0,	0},
+	{"INT_EN"                      ,	0,	8,	823,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	823,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	32,	824,	"R/W",	0,	1,	4294967295ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	824,	"RAZ",	1,	1,	0,	0},
+	{"NOS_CNT"                     ,	0,	10,	825,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_63"              ,	10,	54,	825,	"RAZ",	1,	1,	0,	0},
+	{"NW_TIM"                      ,	0,	10,	826,	"R/W",	0,	0,	0ull,	1023ull},
+	{"RESERVED_10_63"              ,	10,	54,	826,	"RAZ",	1,	1,	0,	0},
+	{"RST_MSK"                     ,	0,	8,	827,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_8_63"               ,	8,	56,	827,	"RAZ",	1,	1,	0,	0},
+	{"GRP_MSK"                     ,	0,	16,	828,	"R/W",	0,	0,	65535ull,	65535ull},
+	{"QOS0_PRI"                    ,	16,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS1_PRI"                    ,	20,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS2_PRI"                    ,	24,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS3_PRI"                    ,	28,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS4_PRI"                    ,	32,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS5_PRI"                    ,	36,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS6_PRI"                    ,	40,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"QOS7_PRI"                    ,	44,	4,	828,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_48_63"              ,	48,	16,	828,	"RAZ",	1,	1,	0,	0},
+	{"RND"                         ,	0,	8,	829,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P1"                      ,	8,	8,	829,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P2"                      ,	16,	8,	829,	"R/W",	0,	1,	255ull,	0},
+	{"RND_P3"                      ,	24,	8,	829,	"R/W",	0,	1,	255ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	829,	"RAZ",	1,	1,	0,	0},
+	{"MIN_THR"                     ,	0,	9,	830,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	830,	"RAZ",	1,	1,	0,	0},
+	{"MAX_THR"                     ,	12,	9,	830,	"R/W",	0,	1,	511ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	830,	"RAZ",	1,	1,	0,	0},
+	{"FREE_CNT"                    ,	24,	10,	830,	"RO",	0,	1,	503ull,	0},
+	{"RESERVED_34_35"              ,	34,	2,	830,	"RAZ",	1,	1,	0,	0},
+	{"BUF_CNT"                     ,	36,	10,	830,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_46_47"              ,	46,	2,	830,	"RAZ",	1,	1,	0,	0},
+	{"DES_CNT"                     ,	48,	10,	830,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	830,	"RAZ",	1,	1,	0,	0},
+	{"TS_PC"                       ,	0,	32,	831,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	831,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	832,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	832,	"RAZ",	1,	1,	0,	0},
+	{"WA_PC"                       ,	0,	32,	833,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	833,	"RAZ",	1,	1,	0,	0},
+	{"WQ_INT"                      ,	0,	16,	834,	"R/W1C",	0,	1,	0ull,	0},
+	{"IQ_DIS"                      ,	16,	16,	834,	"R/W1",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	834,	"RAZ",	1,	1,	0,	0},
+	{"IQ_CNT"                      ,	0,	10,	835,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_10_11"              ,	10,	2,	835,	"RAZ",	1,	1,	0,	0},
+	{"DS_CNT"                      ,	12,	10,	835,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_22_23"              ,	22,	2,	835,	"RAZ",	1,	1,	0,	0},
+	{"TC_CNT"                      ,	24,	4,	835,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_28_63"              ,	28,	36,	835,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_7"                ,	0,	8,	836,	"RAZ",	1,	1,	0,	0},
+	{"PC_THR"                      ,	8,	20,	836,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_28_31"              ,	28,	4,	836,	"RAZ",	1,	1,	0,	0},
+	{"PC"                          ,	32,	28,	836,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_60_63"              ,	60,	4,	836,	"RAZ",	1,	1,	0,	0},
+	{"IQ_THR"                      ,	0,	9,	837,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_9_11"               ,	9,	3,	837,	"RAZ",	1,	1,	0,	0},
+	{"DS_THR"                      ,	12,	9,	837,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_21_23"              ,	21,	3,	837,	"RAZ",	1,	1,	0,	0},
+	{"TC_THR"                      ,	24,	4,	837,	"R/W",	0,	1,	0ull,	0},
+	{"TC_EN"                       ,	28,	1,	837,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_29_63"              ,	29,	35,	837,	"RAZ",	1,	1,	0,	0},
+	{"WS_PC"                       ,	0,	32,	838,	"R/W1C",	0,	1,	0ull,	0},
+	{"RESERVED_32_63"              ,	32,	32,	838,	"RAZ",	1,	1,	0,	0},
+	{"IWORD"                       ,	0,	64,	839,	"RO",	1,	1,	0,	0},
+	{"P_DAT"                       ,	0,	64,	840,	"RO",	1,	1,	0,	0},
+	{"Q_DAT"                       ,	0,	64,	841,	"RO",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	2,	842,	"RO",	1,	0,	0,	0ull},
+	{"NCB_INB"                     ,	2,	2,	842,	"RO",	1,	0,	0,	0ull},
+	{"NCB_OUB"                     ,	4,	1,	842,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	5,	1,	842,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	842,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	33,	843,	"R/W",	0,	1,	0ull,	0},
+	{"SIZE"                        ,	33,	13,	843,	"R/W",	0,	1,	0ull,	0},
+	{"POOL"                        ,	46,	3,	843,	"R/W",	0,	1,	0ull,	0},
+	{"DWB"                         ,	49,	9,	843,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_58_63"              ,	58,	6,	843,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	0,	1,	844,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STORE_LE"                    ,	1,	1,	844,	"R/W",	0,	0,	0ull,	0ull},
+	{"MAX_READ"                    ,	2,	4,	844,	"R/W",	0,	0,	8ull,	8ull},
+	{"RESERVED_6_63"               ,	6,	58,	844,	"RAZ",	0,	0,	0ull,	0ull},
+	{"STATE"                       ,	0,	5,	845,	"RO",	1,	1,	0,	0},
+	{"COMMIT"                      ,	5,	1,	845,	"RO",	1,	1,	0,	0},
+	{"OWORDPV"                     ,	6,	1,	845,	"RO",	1,	1,	0,	0},
+	{"OWORDQV"                     ,	7,	1,	845,	"RO",	1,	1,	0,	0},
+	{"IWIDX"                       ,	8,	6,	845,	"RO",	1,	1,	0,	0},
+	{"RESERVED_14_15"              ,	14,	2,	845,	"RAZ",	1,	1,	0,	0},
+	{"IRIDX"                       ,	16,	6,	845,	"RO",	1,	1,	0,	0},
+	{"RESERVED_22_31"              ,	22,	10,	845,	"RAZ",	1,	1,	0,	0},
+	{"LOOP"                        ,	32,	25,	845,	"RO",	1,	1,	0,	0},
+	{"RESERVED_57_63"              ,	57,	7,	845,	"RAZ",	1,	1,	0,	0},
+	{"CWORD"                       ,	0,	64,	846,	"RO",	1,	1,	0,	0},
+	{"PTR"                         ,	0,	40,	847,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	847,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	847,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	848,	"RO",	1,	1,	0,	0},
+	{"SOD"                         ,	8,	1,	848,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	9,	1,	848,	"RO",	1,	1,	0,	0},
+	{"WC"                          ,	10,	1,	848,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	11,	1,	848,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	12,	1,	848,	"RO",	1,	1,	0,	0},
+	{"RESERVED_13_63"              ,	13,	51,	848,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ASSERTS"                     ,	0,	15,	849,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	849,	"RAZ",	0,	0,	0ull,	0ull},
+	{"OWORDP"                      ,	0,	64,	850,	"RO",	1,	1,	0,	0},
+	{"OWORDQ"                      ,	0,	64,	851,	"RO",	1,	1,	0,	0},
+	{"RWORD"                       ,	0,	64,	852,	"RO",	1,	1,	0,	0},
+	{"N0CREDS"                     ,	0,	4,	853,	"RO",	0,	0,	8ull,	0ull},
+	{"N1CREDS"                     ,	4,	4,	853,	"RO",	0,	0,	8ull,	0ull},
+	{"POWCREDS"                    ,	8,	2,	853,	"RO",	0,	0,	2ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	853,	"RAZ",	0,	0,	0ull,	0ull},
+	{"FPACREDS"                    ,	12,	2,	853,	"RO",	0,	0,	1ull,	0ull},
+	{"WCCREDS"                     ,	14,	2,	853,	"RO",	0,	0,	0ull,	0ull},
+	{"NIWIDX0"                     ,	16,	4,	853,	"RO",	1,	1,	0,	0},
+	{"NIRIDX0"                     ,	20,	4,	853,	"RO",	1,	1,	0,	0},
+	{"NIWIDX1"                     ,	24,	4,	853,	"RO",	1,	1,	0,	0},
+	{"NIRIDX1"                     ,	28,	4,	853,	"RO",	1,	1,	0,	0},
+	{"NIRVAL6"                     ,	32,	5,	853,	"RO",	1,	1,	0,	0},
+	{"NIRARB6"                     ,	37,	1,	853,	"RO",	1,	1,	0,	0},
+	{"NIRQUE6"                     ,	38,	2,	853,	"RO",	1,	1,	0,	0},
+	{"NIROPC6"                     ,	40,	3,	853,	"RO",	1,	1,	0,	0},
+	{"NIRVAL7"                     ,	43,	5,	853,	"RO",	1,	1,	0,	0},
+	{"NIRQUE7"                     ,	48,	2,	853,	"RO",	1,	1,	0,	0},
+	{"NIROPC7"                     ,	50,	3,	853,	"RO",	1,	1,	0,	0},
+	{"RESERVED_53_63"              ,	53,	11,	853,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	40,	854,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	854,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	56,	8,	854,	"RO",	1,	1,	0,	0},
+	{"CNT"                         ,	0,	15,	855,	"RO",	1,	1,	0,	0},
+	{"RESERVED_15_63"              ,	15,	49,	855,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PTR"                         ,	0,	40,	856,	"RO",	1,	1,	0,	0},
+	{"SIZE"                        ,	40,	16,	856,	"RO",	1,	1,	0,	0},
+	{"FLAGS"                       ,	56,	8,	856,	"RO",	1,	1,	0,	0},
+	{"INDEX"                       ,	0,	8,	857,	"RO",	1,	1,	0,	0},
+	{"MUL"                         ,	8,	8,	857,	"RO",	1,	1,	0,	0},
+	{"P"                           ,	16,	1,	857,	"RO",	1,	1,	0,	0},
+	{"Q"                           ,	17,	1,	857,	"RO",	1,	1,	0,	0},
+	{"INI"                         ,	18,	1,	857,	"RO",	1,	1,	0,	0},
+	{"EOD"                         ,	19,	1,	857,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_63"              ,	20,	44,	857,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	0,	1,	858,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	858,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DOORBELL"                    ,	0,	1,	859,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_1_63"               ,	1,	63,	859,	"RAZ",	0,	0,	0ull,	0ull},
+	{"COEFFS"                      ,	0,	8,	860,	"R/W",	0,	0,	29ull,	29ull},
+	{"RESERVED_8_63"               ,	8,	56,	860,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INDEX"                       ,	0,	16,	861,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	16,	16,	861,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_32_63"              ,	32,	32,	861,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MEM"                         ,	0,	1,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"RRC"                         ,	1,	1,	862,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_63"               ,	2,	62,	862,	"RAZ",	1,	1,	0,	0},
+	{"ENT_EN"                      ,	0,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_EN"                      ,	1,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNM_RST"                     ,	2,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RNG_RST"                     ,	3,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"EXP_ENT"                     ,	4,	1,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENT_SEL"                     ,	5,	4,	863,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_63"               ,	9,	55,	863,	"RAZ",	1,	1,	0,	0},
+	{"PHASE"                       ,	0,	8,	864,	"R/W",	0,	0,	100ull,	100ull},
+	{"SAMPLE"                      ,	8,	4,	864,	"R/W",	0,	0,	2ull,	2ull},
+	{"PREAMBLE"                    ,	12,	1,	864,	"R/W",	0,	0,	1ull,	1ull},
+	{"CLK_IDLE"                    ,	13,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_14_14"              ,	14,	1,	864,	"RAZ",	1,	1,	0,	0},
+	{"SAMPLE_MODE"                 ,	15,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"SAMPLE_HI"                   ,	16,	5,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_23"              ,	21,	3,	864,	"RAZ",	1,	1,	0,	0},
+	{"MODE"                        ,	24,	1,	864,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_63"              ,	25,	39,	864,	"RAZ",	1,	1,	0,	0},
+	{"REG_ADR"                     ,	0,	5,	865,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_5_7"                ,	5,	3,	865,	"RAZ",	1,	1,	0,	0},
+	{"PHY_ADR"                     ,	8,	5,	865,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_13_15"              ,	13,	3,	865,	"RAZ",	1,	1,	0,	0},
+	{"PHY_OP"                      ,	16,	2,	865,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	865,	"RAZ",	1,	1,	0,	0},
+	{"EN"                          ,	0,	1,	866,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_1_63"               ,	1,	63,	866,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	867,	"RO",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	867,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	867,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	867,	"RAZ",	1,	1,	0,	0},
+	{"DAT"                         ,	0,	16,	868,	"R/W",	0,	1,	0ull,	0},
+	{"VAL"                         ,	16,	1,	868,	"RO",	0,	1,	0ull,	0},
+	{"PENDING"                     ,	17,	1,	868,	"RO",	0,	1,	0ull,	0},
+	{"RESERVED_18_63"              ,	18,	46,	868,	"RAZ",	1,	1,	0,	0},
+	{"INTERVAL"                    ,	0,	22,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	869,	"RAZ",	1,	0,	0,	0ull},
+	{"COUNT"                       ,	24,	22,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_46_46"              ,	46,	1,	869,	"RAZ",	1,	0,	0,	0ull},
+	{"ENA"                         ,	47,	1,	869,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_48_63"              ,	48,	16,	869,	"RAZ",	1,	0,	0,	0ull},
+	{"BSIZE"                       ,	0,	20,	870,	"RO",	1,	0,	0,	0ull},
+	{"BASE"                        ,	20,	31,	870,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	51,	13,	870,	"RO",	1,	0,	0,	0ull},
+	{"BUCKET"                      ,	0,	7,	871,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_7_7"                ,	7,	1,	871,	"RAZ",	1,	0,	0,	0ull},
+	{"CSIZE"                       ,	8,	13,	871,	"RO",	1,	0,	0,	0ull},
+	{"CPOOL"                       ,	21,	3,	871,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_24_63"              ,	24,	40,	871,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"NUM_BUCKETS"                 ,	4,	20,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"FIRST_BUCKET"                ,	24,	31,	872,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_55_63"              ,	55,	9,	872,	"RAZ",	1,	0,	0,	0ull},
+	{"RING"                        ,	0,	4,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTERVAL"                    ,	4,	22,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"WORDS_PER_CHUNK"             ,	26,	13,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"POOL"                        ,	39,	3,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE"                      ,	42,	1,	873,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_43_63"              ,	43,	21,	873,	"RAZ",	1,	0,	0,	0ull},
+	{"CTL"                         ,	0,	1,	874,	"RO",	1,	0,	0,	0ull},
+	{"NCB"                         ,	1,	1,	874,	"RO",	1,	0,	0,	0ull},
+	{"STA"                         ,	2,	2,	874,	"RO",	1,	0,	0,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	874,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	875,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	875,	"RAZ",	1,	0,	0,	0ull},
+	{"ENABLE_TIMERS"               ,	0,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENABLE_DWB"                  ,	1,	1,	876,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESET"                       ,	2,	1,	876,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	876,	"RAZ",	1,	0,	0,	0ull},
+	{"MASK"                        ,	0,	16,	877,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	877,	"RAZ",	1,	0,	0,	0ull},
+	{"INDEX"                       ,	0,	8,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"INC"                         ,	8,	8,	878,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_63"              ,	16,	48,	878,	"RAZ",	1,	0,	0,	0ull},
+	{"TDF0"                        ,	0,	1,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"TDF1"                        ,	1,	1,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"TCF"                         ,	2,	1,	879,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_63"               ,	3,	61,	879,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ENA"                         ,	0,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"WRAP"                        ,	1,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"TRIG_CTL"                    ,	2,	2,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIME_GRN"                    ,	4,	3,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"FULL_THR"                    ,	7,	2,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	9,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	10,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	11,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	12,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"MCD0_ENA"                    ,	13,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"IGNORE_O"                    ,	14,	1,	880,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_15_63"              ,	15,	49,	880,	"RAZ",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	8,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	8,	8,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	16,	48,	881,	"RO",	0,	0,	0ull,	0ull},
+	{"WPTR"                        ,	0,	10,	882,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_11"              ,	10,	2,	882,	"RAZ",	0,	0,	0ull,	0ull},
+	{"RPTR"                        ,	12,	10,	882,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_23"              ,	22,	2,	882,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CYCLES"                      ,	24,	40,	882,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	883,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	883,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	884,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	884,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	885,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	885,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	886,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	886,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	886,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	886,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	886,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	887,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	887,	"RAZ",	0,	0,	0ull,	0ull},
+	{"CIU_TRG"                     ,	0,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CIU_THR"                     ,	1,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_TRG"                    ,	2,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"MCD0_THR"                    ,	3,	1,	888,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_63"               ,	4,	60,	888,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	64,	889,	"RO",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	890,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	890,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	891,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	891,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	892,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	892,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	893,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	893,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	893,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	893,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	893,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	894,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	894,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	895,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	895,	"RAZ",	0,	0,	0ull,	0ull},
+	{"ADR"                         ,	0,	36,	896,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_36_63"              ,	36,	28,	896,	"RAZ",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	0,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"PL2"                         ,	1,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"PSL1"                        ,	2,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDD"                         ,	3,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDI"                         ,	4,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"LDT"                         ,	5,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"STF"                         ,	6,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"STC"                         ,	7,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"STP"                         ,	8,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"STT"                         ,	9,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD8"                      ,	10,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD16"                     ,	11,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD32"                     ,	12,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBLD64"                     ,	13,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBST"                       ,	14,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"IOBDMA"                      ,	15,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"SAA"                         ,	16,	1,	897,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_17_63"              ,	17,	47,	897,	"RAZ",	0,	0,	0ull,	0ull},
+	{"MIO"                         ,	0,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL3"                    ,	1,	2,	898,	"R/W",	0,	0,	0ull,	3ull},
+	{"PCI"                         ,	3,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"KEY"                         ,	4,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"FPA"                         ,	5,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"DFA"                         ,	6,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"ZIP"                         ,	7,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"RNG"                         ,	8,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL2"                    ,	9,	3,	898,	"R/W",	0,	0,	0ull,	7ull},
+	{"POW"                         ,	12,	1,	898,	"R/W",	0,	0,	0ull,	1ull},
+	{"ILLEGAL"                     ,	13,	19,	898,	"R/W",	0,	0,	0ull,	524287ull},
+	{"RESERVED_32_63"              ,	32,	32,	898,	"RAZ",	0,	0,	0ull,	0ull},
+	{"PP"                          ,	0,	16,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKI"                         ,	16,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKO"                         ,	17,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"IOBREQ"                      ,	18,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"DWB"                         ,	19,	1,	899,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_63"              ,	20,	44,	899,	"RAZ",	0,	0,	0ull,	0ull},
+	{"INEPINT"                     ,	0,	16,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"OUTEPINT"                    ,	16,	16,	900,	"RO",	0,	0,	0ull,	0ull},
+	{"INEPMSK"                     ,	0,	16,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTEPMSK"                    ,	16,	16,	901,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVSPD"                      ,	0,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"NZSTSOUTHSHK"                ,	2,	1,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_3"                ,	3,	1,	902,	"RAZ",	1,	1,	0,	0},
+	{"DEVADDR"                     ,	4,	7,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"PERFRINT"                    ,	11,	2,	902,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_17"              ,	13,	5,	902,	"RAZ",	1,	1,	0,	0},
+	{"EPMISCNT"                    ,	18,	5,	902,	"R/W",	0,	0,	8ull,	0ull},
+	{"RESERVED_23_31"              ,	23,	9,	902,	"RAZ",	1,	1,	0,	0},
+	{"RMTWKUPSIG"                  ,	0,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"SFTDISCON"                   ,	1,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"GNPINNAKSTS"                 ,	2,	1,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKSTS"                  ,	3,	1,	903,	"RO",	0,	0,	0ull,	0ull},
+	{"TSTCTL"                      ,	4,	3,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"SGNPINNAK"                   ,	7,	1,	903,	"WO",	0,	0,	0ull,	0ull},
+	{"CGNPINNAK"                   ,	8,	1,	903,	"WO",	0,	0,	0ull,	0ull},
+	{"SGOUTNAK"                    ,	9,	1,	903,	"WO",	0,	0,	0ull,	0ull},
+	{"CGOUTNAK"                    ,	10,	1,	903,	"WO",	0,	0,	0ull,	0ull},
+	{"PWRONPRGDONE"                ,	11,	1,	903,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_31"              ,	12,	20,	903,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"NEXTEP"                      ,	11,	4,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	904,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	904,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_20"              ,	20,	1,	904,	"RAZ",	1,	1,	0,	0},
+	{"STALL"                       ,	21,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	22,	4,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"CNAK"                        ,	26,	1,	904,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	904,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	904,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	904,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	904,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"TIMEOUT"                     ,	3,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMP"                 ,	4,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INTKNEPMIS"                  ,	5,	1,	905,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFF"                  ,	6,	1,	905,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	905,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"TIMEOUTMSK"                  ,	3,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNTXFEMPMSK"              ,	4,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNEPMISMSK"               ,	5,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPNAKEFFMSK"               ,	6,	1,	906,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_31"               ,	7,	25,	906,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	907,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	907,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	907,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	907,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_14"              ,	11,	4,	908,	"RAZ",	0,	0,	0ull,	0ull},
+	{"USBACTEP"                    ,	15,	1,	908,	"R/W",	0,	0,	1ull,	0ull},
+	{"DPID"                        ,	16,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"NAKSTS"                      ,	17,	1,	908,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"SNP"                         ,	20,	1,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	21,	1,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_25"              ,	22,	4,	908,	"RAZ",	1,	1,	0,	0},
+	{"CNAK"                        ,	26,	1,	908,	"WO",	0,	0,	0ull,	0ull},
+	{"SNAK"                        ,	27,	1,	908,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD0PID"                    ,	28,	1,	908,	"WO",	0,	0,	0ull,	0ull},
+	{"SETD1PID"                    ,	29,	1,	908,	"WO",	0,	0,	0ull,	0ull},
+	{"EPDIS"                       ,	30,	1,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPENA"                       ,	31,	1,	908,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERCOMPL"                   ,	0,	1,	909,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EPDISBLD"                    ,	1,	1,	909,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	909,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SETUP"                       ,	3,	1,	909,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDIS"                 ,	4,	1,	909,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	909,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDISBLDMSK"                 ,	1,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"SETUPMSK"                    ,	3,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"OUTTKNEPDISMSK"              ,	4,	1,	910,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	910,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZE"                    ,	0,	19,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"MC"                          ,	29,	2,	911,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	911,	"RAZ",	1,	1,	0,	0},
+	{"DPTXFSTADDR"                 ,	0,	16,	912,	"RO",	0,	0,	0ull,	0ull},
+	{"DPTXFSIZE"                   ,	16,	16,	912,	"RO",	0,	0,	1896ull,	1896ull},
+	{"SUSPSTS"                     ,	0,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"ENUMSPD"                     ,	1,	2,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"ERRTICERR"                   ,	3,	1,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_4_7"                ,	4,	4,	913,	"RAZ",	1,	1,	0,	0},
+	{"SOFFN"                       ,	8,	14,	913,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_22_31"              ,	22,	10,	913,	"RAZ",	1,	1,	0,	0},
+	{"INTKNWPTR"                   ,	0,	5,	914,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_6"                ,	5,	2,	914,	"RAZ",	1,	1,	0,	0},
+	{"WRAPBIT"                     ,	7,	1,	914,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	8,	24,	914,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	915,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	916,	"RO",	0,	0,	0ull,	0ull},
+	{"EPTKN"                       ,	0,	32,	917,	"RO",	0,	0,	0ull,	0ull},
+	{"GLBLINTRMSK"                 ,	0,	1,	918,	"R/W",	0,	0,	0ull,	1ull},
+	{"HBSTLEN"                     ,	1,	4,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMAEN"                       ,	5,	1,	918,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_6"                ,	6,	1,	918,	"RAZ",	1,	1,	0,	0},
+	{"NPTXFEMPLVL"                 ,	7,	1,	918,	"R/W",	0,	0,	0ull,	1ull},
+	{"PTXFEMPLVL"                  ,	8,	1,	918,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_9_31"               ,	9,	23,	918,	"RAZ",	1,	1,	0,	0},
+	{"EPDIR"                       ,	0,	32,	919,	"RO",	0,	0,	0ull,	0ull},
+	{"OTGMODE"                     ,	0,	3,	920,	"RO",	0,	0,	2ull,	2ull},
+	{"OTGARCH"                     ,	3,	2,	920,	"RO",	0,	0,	1ull,	1ull},
+	{"SINGPNT"                     ,	5,	1,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"HSPHYTYPE"                   ,	6,	2,	920,	"RO",	0,	0,	1ull,	1ull},
+	{"FSPHYTYPE"                   ,	8,	2,	920,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVEPS"                   ,	10,	4,	920,	"RO",	0,	0,	4ull,	4ull},
+	{"NUMHSTCHNL"                  ,	14,	4,	920,	"RO",	0,	0,	7ull,	7ull},
+	{"PERIOSUPPORT"                ,	18,	1,	920,	"RO",	0,	0,	1ull,	1ull},
+	{"DYNFIFOSIZING"               ,	19,	1,	920,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_20_21"              ,	20,	2,	920,	"RAZ",	1,	1,	0,	0},
+	{"NPTXQDEPTH"                  ,	22,	2,	920,	"RO",	0,	0,	2ull,	2ull},
+	{"PTXQDEPTH"                   ,	24,	2,	920,	"RO",	0,	0,	2ull,	2ull},
+	{"TKNQDEPTH"                   ,	26,	5,	920,	"RO",	0,	0,	30ull,	30ull},
+	{"RESERVED_31_31"              ,	31,	1,	920,	"RAZ",	1,	1,	0,	0},
+	{"XFERSIZEWIDTH"               ,	0,	4,	921,	"RO",	0,	0,	8ull,	8ull},
+	{"PKTSIZEWIDTH"                ,	4,	3,	921,	"RO",	0,	0,	6ull,	6ull},
+	{"OTGEN"                       ,	7,	1,	921,	"RO",	0,	0,	1ull,	1ull},
+	{"I2C_SELECTION"               ,	8,	1,	921,	"RO",	0,	0,	0ull,	0ull},
+	{"VENDOR_CONTROL_INTERFACE_SUPPORT",	9,	1,	921,	"RO",	0,	0,	0ull,	0ull},
+	{"OPTFEATURE"                  ,	10,	1,	921,	"RO",	0,	0,	1ull,	1ull},
+	{"RSTTYPE"                     ,	11,	1,	921,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBPHYSYNC"                  ,	12,	1,	921,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_13_15"              ,	13,	3,	921,	"RAZ",	1,	1,	0,	0},
+	{"DFIFODEPTH"                  ,	16,	16,	921,	"RO",	0,	0,	1824ull,	1824ull},
+	{"NUMDEVPERIOEPS"              ,	0,	4,	922,	"RO",	0,	0,	4ull,	4ull},
+	{"ENABLEPWROPT"                ,	4,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBFREQ"                     ,	5,	1,	922,	"RO",	0,	0,	1ull,	1ull},
+	{"RESERVED_6_13"               ,	6,	8,	922,	"RAZ",	1,	1,	0,	0},
+	{"PHYDATAWIDTH"                ,	14,	2,	922,	"RO",	0,	0,	1ull,	1ull},
+	{"NUMCTLEPS"                   ,	16,	4,	922,	"RO",	0,	0,	4ull,	4ull},
+	{"IDDGFLTR"                    ,	20,	1,	922,	"RO",	0,	0,	1ull,	1ull},
+	{"VBUSVALIDFLTR"               ,	21,	1,	922,	"RO",	0,	0,	1ull,	1ull},
+	{"AVALIDFLTR"                  ,	22,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"BVALIDFLTR"                  ,	23,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"SESSENDFLTR"                 ,	24,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"ENDEDTRFIFO"                 ,	25,	1,	922,	"RO",	0,	0,	0ull,	0ull},
+	{"NUMDEVMODINEND"              ,	26,	4,	922,	"RO",	0,	0,	2ull,	2ull},
+	{"RESERVED_30_31"              ,	30,	2,	922,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_0"                ,	0,	1,	923,	"RAZ",	1,	1,	0,	0},
+	{"MODEMISMSK"                  ,	1,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGINTMSK"                   ,	2,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"SOFMSK"                      ,	3,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFLVLMSK"                   ,	4,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"NPTXFEMPMSK"                 ,	5,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"GINNAKEFFMSK"                ,	6,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFFMSK"               ,	7,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"ULPICKINTMSK"                ,	8,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"ERLYSUSPMSK"                 ,	10,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBSUSPMSK"                  ,	11,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBRSTMSK"                   ,	12,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"ENUMDONEMSK"                 ,	13,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROPMSK"               ,	14,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"EOPFMSK"                     ,	15,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	923,	"RAZ",	1,	1,	0,	0},
+	{"EPMISMSK"                    ,	17,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"INEPINTMSK"                  ,	18,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"OEPINTMSK"                   ,	19,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPISOINMSK"              ,	20,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"INCOMPLPMSK"                 ,	21,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"FETSUSPMSK"                  ,	22,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	923,	"RAZ",	1,	1,	0,	0},
+	{"PRTINTMSK"                   ,	24,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"HCHINTMSK"                   ,	25,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"PTXFEMPMSK"                  ,	26,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	923,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNGMSK"             ,	28,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"DISCONNINTMSK"               ,	29,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESSREQINTMSK"               ,	30,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"WKUPINTMSK"                  ,	31,	1,	923,	"R/W",	0,	0,	0ull,	0ull},
+	{"CURMOD"                      ,	0,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"MODEMIS"                     ,	1,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"OTGINT"                      ,	2,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"SOF"                         ,	3,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RXFLVL"                      ,	4,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXFEMP"                    ,	5,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"GINNAKEFF"                   ,	6,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"GOUTNAKEFF"                  ,	7,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"ULPICKINT"                   ,	8,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"I2CINT"                      ,	9,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ERLYSUSP"                    ,	10,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBSUSP"                     ,	11,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"USBRST"                      ,	12,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ENUMDONE"                    ,	13,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ISOOUTDROP"                  ,	14,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"EOPF"                        ,	15,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	924,	"RAZ",	1,	1,	0,	0},
+	{"EPMIS"                       ,	17,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"IEPINT"                      ,	18,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"OEPINT"                      ,	19,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"INCOMPISOIN"                 ,	20,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"INCOMPLP"                    ,	21,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FETSUSP"                     ,	22,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_23_23"              ,	23,	1,	924,	"RAZ",	1,	1,	0,	0},
+	{"PRTINT"                      ,	24,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"HCHINT"                      ,	25,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXFEMP"                     ,	26,	1,	924,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_27_27"              ,	27,	1,	924,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTSCHNG"                ,	28,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DISCONNINT"                  ,	29,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"SESSREQINT"                  ,	30,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"WKUPINT"                     ,	31,	1,	924,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NPTXFSTADDR"                 ,	0,	16,	925,	"R/W",	0,	0,	1824ull,	456ull},
+	{"NPTXFDEP"                    ,	16,	16,	925,	"R/W",	0,	0,	1824ull,	912ull},
+	{"NPTXFSPCAVAIL"               ,	0,	16,	926,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQSPCAVAIL"               ,	16,	8,	926,	"RO",	0,	0,	0ull,	0ull},
+	{"NPTXQTOP"                    ,	24,	7,	926,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_31_31"              ,	31,	1,	926,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSCS"                   ,	0,	1,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"SESREQ"                      ,	1,	1,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_2_7"                ,	2,	6,	927,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGSCS"                   ,	8,	1,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"HNPREQ"                      ,	9,	1,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSTSETHNPEN"                 ,	10,	1,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVHNPEN"                    ,	11,	1,	927,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_12_15"              ,	12,	4,	927,	"RAZ",	1,	1,	0,	0},
+	{"CONIDSTS"                    ,	16,	1,	927,	"RO",	1,	1,	0,	0},
+	{"DBNCTIME"                    ,	17,	1,	927,	"RO",	0,	0,	0ull,	0ull},
+	{"ASESVLD"                     ,	18,	1,	927,	"RO",	1,	1,	0,	0},
+	{"BSESVLD"                     ,	19,	1,	927,	"RO",	1,	1,	0,	0},
+	{"RESERVED_20_31"              ,	20,	12,	927,	"RAZ",	1,	1,	0,	0},
+	{"RESERVED_0_1"                ,	0,	2,	928,	"RAZ",	1,	1,	0,	0},
+	{"SESENDDET"                   ,	2,	1,	928,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_7"                ,	3,	5,	928,	"RAZ",	1,	1,	0,	0},
+	{"SESREQSUCSTSCHNG"            ,	8,	1,	928,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"HSTNEGSUCSTSCHNG"            ,	9,	1,	928,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_10_16"              ,	10,	7,	928,	"RAZ",	1,	1,	0,	0},
+	{"HSTNEGDET"                   ,	17,	1,	928,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ADEVTOUTCHG"                 ,	18,	1,	928,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DBNCEDONE"                   ,	19,	1,	928,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_20_31"              ,	20,	12,	928,	"RAZ",	1,	1,	0,	0},
+	{"CSFTRST"                     ,	0,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"HSFTRST"                     ,	1,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMCNTRRST"                  ,	2,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"INTKNQFLSH"                  ,	3,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"RXFFLSH"                     ,	4,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFFLSH"                     ,	5,	1,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFNUM"                      ,	6,	5,	929,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_29"              ,	11,	19,	929,	"RAZ",	1,	1,	0,	0},
+	{"DMAREQ"                      ,	30,	1,	929,	"RO",	0,	0,	0ull,	0ull},
+	{"AHBIDLE"                     ,	31,	1,	929,	"RO",	0,	0,	1ull,	1ull},
+	{"RXFDEP"                      ,	0,	16,	930,	"R/W",	0,	0,	1824ull,	456ull},
+	{"RESERVED_16_31"              ,	16,	16,	930,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	931,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	931,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	931,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	931,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	931,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	931,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	932,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	932,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	932,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	932,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	932,	"RAZ",	1,	1,	0,	0},
+	{"EPNUM"                       ,	0,	4,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"FN"                          ,	21,	4,	933,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_25_31"              ,	25,	7,	933,	"RAZ",	1,	1,	0,	0},
+	{"CHNUM"                       ,	0,	4,	934,	"RO",	0,	0,	0ull,	0ull},
+	{"BCNT"                        ,	4,	11,	934,	"RO",	0,	0,	0ull,	0ull},
+	{"DPID"                        ,	15,	2,	934,	"RO",	0,	0,	0ull,	0ull},
+	{"PKTSTS"                      ,	17,	4,	934,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_21_31"              ,	21,	11,	934,	"RAZ",	1,	1,	0,	0},
+	{"SYNOPSYSID"                  ,	0,	32,	935,	"RO",	1,	1,	0,	0},
+	{"TOUTCAL"                     ,	0,	3,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYIF"                       ,	3,	1,	936,	"RO",	0,	0,	1ull,	1ull},
+	{"ULPI_UTMI_SEL"               ,	4,	1,	936,	"RO",	0,	0,	0ull,	0ull},
+	{"FSINTF"                      ,	5,	1,	936,	"WO",	0,	0,	0ull,	0ull},
+	{"PHYSEL"                      ,	6,	1,	936,	"WO",	0,	0,	0ull,	0ull},
+	{"DDRSEL"                      ,	7,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"SRPCAP"                      ,	8,	1,	936,	"RO",	0,	0,	0ull,	0ull},
+	{"HNPCAP"                      ,	9,	1,	936,	"RO",	0,	0,	0ull,	0ull},
+	{"USBTRDTIM"                   ,	10,	4,	936,	"R/W",	0,	0,	5ull,	5ull},
+	{"RESERVED_14_14"              ,	14,	1,	936,	"RAZ",	1,	1,	0,	0},
+	{"PHYLPWRCLKSEL"               ,	15,	1,	936,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGI2CSEL"                   ,	16,	1,	936,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_31"              ,	17,	15,	936,	"RAZ",	1,	1,	0,	0},
+	{"HAINT"                       ,	0,	16,	937,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	937,	"RAZ",	1,	1,	0,	0},
+	{"HAINTMSK"                    ,	0,	16,	938,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_31"              ,	16,	16,	938,	"RAZ",	1,	1,	0,	0},
+	{"MPS"                         ,	0,	11,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPNUM"                       ,	11,	4,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPDIR"                       ,	15,	1,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	939,	"RAZ",	1,	1,	0,	0},
+	{"LSPDDEV"                     ,	17,	1,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"EPTYPE"                      ,	18,	2,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"EC"                          ,	20,	2,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"DEVADDR"                     ,	22,	7,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"ODDFRM"                      ,	29,	1,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHDIS"                       ,	30,	1,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHENA"                       ,	31,	1,	939,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSPCLKSEL"                 ,	0,	2,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSLSSUPP"                    ,	2,	1,	940,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_3_31"               ,	3,	29,	940,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPL"                   ,	0,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"CHHLTD"                      ,	1,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"AHBERR"                      ,	2,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"STALL"                       ,	3,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NAK"                         ,	4,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ACK"                         ,	5,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NYET"                        ,	6,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"XACTERR"                     ,	7,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"BBLERR"                      ,	8,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"FRMOVRUN"                    ,	9,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DATATGLERR"                  ,	10,	1,	941,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	941,	"RAZ",	1,	1,	0,	0},
+	{"XFERCOMPLMSK"                ,	0,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHHLTDMSK"                   ,	1,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"AHBERRMSK"                   ,	2,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"STALLMSK"                    ,	3,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"NAKMSK"                      ,	4,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"ACKMSK"                      ,	5,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"NYETMSK"                     ,	6,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTERRMSK"                  ,	7,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"BBLERRMSK"                   ,	8,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRMOVRUNMSK"                 ,	9,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"DATATGLERRMSK"               ,	10,	1,	942,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_11_31"              ,	11,	21,	942,	"RAZ",	1,	1,	0,	0},
+	{"PRTADDR"                     ,	0,	7,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"HUBADDR"                     ,	7,	7,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"XACTPOS"                     ,	14,	2,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"COMPSPLT"                    ,	16,	1,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_17_30"              ,	17,	14,	943,	"RAZ",	1,	1,	0,	0},
+	{"SPLTENA"                     ,	31,	1,	943,	"R/W",	0,	0,	0ull,	0ull},
+	{"XFERSIZE"                    ,	0,	19,	944,	"R/W",	0,	0,	0ull,	0ull},
+	{"PKTCNT"                      ,	19,	10,	944,	"R/W",	0,	0,	0ull,	0ull},
+	{"PID"                         ,	29,	2,	944,	"R/W",	0,	0,	0ull,	0ull},
+	{"DOPNG"                       ,	31,	1,	944,	"R/W",	0,	0,	0ull,	0ull},
+	{"FRINT"                       ,	0,	16,	945,	"R/W",	0,	0,	2959ull,	3750ull},
+	{"RESERVED_16_31"              ,	16,	16,	945,	"RAZ",	1,	1,	0,	0},
+	{"FRNUM"                       ,	0,	16,	946,	"RO",	0,	0,	16383ull,	0ull},
+	{"FRREM"                       ,	16,	16,	946,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNSTS"                  ,	0,	1,	947,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTCONNDET"                  ,	1,	1,	947,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENA"                      ,	2,	1,	947,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTENCHNG"                   ,	3,	1,	947,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRACT"               ,	4,	1,	947,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTOVRCURRCHNG"              ,	5,	1,	947,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PRTRES"                      ,	6,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSUSP"                     ,	7,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTRST"                      ,	8,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_9_9"                ,	9,	1,	947,	"RAZ",	1,	1,	0,	0},
+	{"PRTLNSTS"                    ,	10,	2,	947,	"RO",	0,	0,	0ull,	0ull},
+	{"PRTPWR"                      ,	12,	1,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTTSTCTL"                   ,	13,	4,	947,	"R/W",	0,	0,	0ull,	0ull},
+	{"PRTSPD"                      ,	17,	2,	947,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_31"              ,	19,	13,	947,	"RAZ",	1,	1,	0,	0},
+	{"PTXFSTADDR"                  ,	0,	16,	948,	"R/W",	0,	0,	3648ull,	912ull},
+	{"PTXFSIZE"                    ,	16,	16,	948,	"R/W",	0,	0,	256ull,	456ull},
+	{"PTXFSPCAVAIL"                ,	0,	16,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQSPCAVAIL"                ,	16,	8,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"PTXQTOP"                     ,	24,	8,	949,	"RO",	0,	0,	0ull,	0ull},
+	{"DATA"                        ,	0,	32,	950,	"R/W",	0,	0,	0ull,	0ull},
+	{"STOPPCLK"                    ,	0,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"GATEHCLK"                    ,	1,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"PWRCLMP"                     ,	2,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"RSTPDWNMODULE"               ,	3,	1,	951,	"R/W",	0,	0,	0ull,	0ull},
+	{"PHYSUSPENDED"                ,	4,	1,	951,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_5_31"               ,	5,	27,	951,	"RAZ",	1,	1,	0,	0},
+	{"NOF_BIS"                     ,	0,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"NIF_BIS"                     ,	1,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"USBC_BIS"                    ,	2,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"N2UF_BIS"                    ,	3,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"E2HC_BIS"                    ,	4,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NF_BIS"                    ,	5,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"U2NC_BIS"                    ,	6,	1,	952,	"RO",	0,	0,	0ull,	0ull},
+	{"RESERVED_7_63"               ,	7,	57,	952,	"RAZ",	1,	1,	0,	0},
+	{"DIVIDE"                      ,	0,	3,	953,	"R/W",	0,	0,	4ull,	0ull},
+	{"HRST"                        ,	3,	1,	953,	"R/W",	0,	0,	0ull,	1ull},
+	{"PRST"                        ,	4,	1,	953,	"R/W",	0,	0,	0ull,	1ull},
+	{"ENABLE"                      ,	5,	1,	953,	"R/W",	0,	0,	1ull,	1ull},
+	{"POR"                         ,	6,	1,	953,	"R/W",	0,	0,	1ull,	0ull},
+	{"S_BIST"                      ,	7,	1,	953,	"R/W",	0,	0,	0ull,	1ull},
+	{"SD_MODE"                     ,	8,	2,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"CDIV_BYP"                    ,	10,	1,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"P_C_SEL"                     ,	11,	2,	953,	"R/W",	0,	0,	2ull,	0ull},
+	{"P_COM_ON"                    ,	13,	1,	953,	"R/W",	0,	0,	1ull,	1ull},
+	{"P_RTYPE"                     ,	14,	2,	953,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_16_16"              ,	16,	1,	953,	"RAZ",	1,	1,	0,	0},
+	{"HCLK_RST"                    ,	17,	1,	953,	"R/W",	0,	0,	1ull,	1ull},
+	{"DIVIDE2"                     ,	18,	2,	953,	"R/W",	0,	0,	0ull,	1ull},
+	{"RESERVED_20_63"              ,	20,	44,	953,	"RAZ",	1,	1,	0,	0},
+	{"L2C_EMOD"                    ,	0,	2,	954,	"R/W",	0,	0,	1ull,	1ull},
+	{"INV_A2"                      ,	2,	1,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_TEST"                    ,	3,	1,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_STT"                     ,	4,	1,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_0PAG"                    ,	5,	1,	954,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_6_63"               ,	6,	58,	954,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	955,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	955,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	956,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	956,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	957,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	957,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	958,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	958,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	959,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	959,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	960,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	960,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	961,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	961,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	962,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	962,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	963,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	963,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	964,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	964,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	965,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	965,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	966,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	966,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	967,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	967,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	968,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	968,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	969,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	969,	"RAZ",	1,	1,	0,	0},
+	{"ADDR"                        ,	0,	36,	970,	"R/W",	0,	1,	0ull,	0},
+	{"RESERVED_36_63"              ,	36,	28,	970,	"RAZ",	1,	1,	0,	0},
+	{"BURST"                       ,	0,	4,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"CHANNEL"                     ,	4,	5,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"COUNT"                       ,	9,	11,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"F_ADDR"                      ,	20,	18,	971,	"R/W",	0,	0,	0ull,	0ull},
+	{"REQ"                         ,	38,	1,	971,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DONE"                        ,	39,	1,	971,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RESERVED_40_63"              ,	40,	24,	971,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_E"                     ,	16,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"L2_FI_F"                     ,	17,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"UOD_PF"                      ,	25,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	972,	"RAZ",	0,	0,	0ull,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	972,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	972,	"RAZ",	1,	1,	0,	0},
+	{"PR_PO_E"                     ,	0,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PR_PU_F"                     ,	1,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PO_E"                     ,	2,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NR_PU_F"                     ,	3,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PO_E"                     ,	4,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LR_PU_F"                     ,	5,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PO_E"                     ,	6,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"PT_PU_F"                     ,	7,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PO_E"                     ,	8,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"NT_PU_F"                     ,	9,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PO_E"                     ,	10,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_PU_F"                     ,	11,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_E"                     ,	12,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"DCRED_F"                     ,	13,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"L2C_S_E"                     ,	14,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"L2C_A_F"                     ,	15,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"LT_FI_E"                     ,	16,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LT_FI_F"                     ,	17,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_E"                     ,	18,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RG_FI_F"                     ,	19,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_F"                     ,	20,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q2_E"                     ,	21,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_F"                     ,	22,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"RQ_Q3_E"                     ,	23,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"UOD_PE"                      ,	24,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"UOD_PF"                      ,	25,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_26_31"              ,	26,	6,	973,	"RAZ",	1,	0,	0,	0ull},
+	{"LTL_F_PE"                    ,	32,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"LTL_F_PF"                    ,	33,	1,	973,	"R/W1C",	0,	0,	0ull,	0ull},
+	{"ND4O_RPE"                    ,	34,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_RPF"                    ,	35,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPE"                    ,	36,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"ND4O_DPF"                    ,	37,	1,	973,	"R/W1C",	1,	0,	0,	0ull},
+	{"RESERVED_38_63"              ,	38,	26,	973,	"RAZ",	1,	1,	0,	0},
+	{"ATE_RESET"                   ,	0,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_IN"                    ,	1,	8,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TADDR_IN"                    ,	9,	4,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_SEL"                   ,	13,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"BIST_ENB"                    ,	14,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"VTEST_ENB"                   ,	15,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"LOOP_ENB"                    ,	16,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_EN"                    ,	17,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TX_BS_ENH"                   ,	18,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"RESERVED_19_22"              ,	19,	4,	974,	"RAZ",	0,	0,	0ull,	0ull},
+	{"HST_MODE"                    ,	23,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"DM_PULLD"                    ,	24,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"DP_PULLD"                    ,	25,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"TCLK"                        ,	26,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"USBP_BIST"                   ,	27,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"USBC_END"                    ,	28,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"DMA_BMODE"                   ,	29,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXPREEMPHASISTUNE"           ,	30,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"SIDDQ"                       ,	31,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TDATA_OUT"                   ,	32,	4,	974,	"RO",	1,	1,	0,	0},
+	{"BIST_ERR"                    ,	36,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"BIST_DONE"                   ,	37,	1,	974,	"RO",	0,	0,	0ull,	0ull},
+	{"HSBIST"                      ,	38,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"FSBIST"                      ,	39,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"LSBIST"                      ,	40,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"DRVVBUS"                     ,	41,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"PORTRESET"                   ,	42,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"OTGDISABLE"                  ,	43,	1,	974,	"R/W",	0,	0,	1ull,	1ull},
+	{"OTGTUNE"                     ,	44,	3,	974,	"R/W",	0,	0,	2ull,	2ull},
+	{"COMPDISTUNE"                 ,	47,	3,	974,	"R/W",	0,	0,	2ull,	2ull},
+	{"SQRXTUNE"                    ,	50,	3,	974,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXHSXVTUNE"                  ,	53,	2,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{"TXFSLSTUNE"                  ,	55,	4,	974,	"R/W",	0,	0,	3ull,	3ull},
+	{"TXVREFTUNE"                  ,	59,	4,	974,	"R/W",	0,	0,	7ull,	7ull},
+	{"TXRISETUNE"                  ,	63,	1,	974,	"R/W",	0,	0,	0ull,	0ull},
+	{NULL,0,0,0,0,0,0,0,0}
+};
+
+
+const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
+	cvmx_csr_db_cn38xxp2,
+	cvmx_csr_db_cn31xx,
+	cvmx_csr_db_cn30xx,
+	cvmx_csr_db_cn38xx,
+	cvmx_csr_db_cn58xxp1,
+	cvmx_csr_db_cn58xx,
+	cvmx_csr_db_cn56xxp1,
+	cvmx_csr_db_cn56xx,
+	cvmx_csr_db_cn50xx,
+	cvmx_csr_db_cn52xxp1,
+	cvmx_csr_db_cn52xx,
+	NULL
+};
+const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
+	cvmx_csr_db_addresses_cn38xxp2,
+	cvmx_csr_db_addresses_cn31xx,
+	cvmx_csr_db_addresses_cn30xx,
+	cvmx_csr_db_addresses_cn38xx,
+	cvmx_csr_db_addresses_cn58xxp1,
+	cvmx_csr_db_addresses_cn58xx,
+	cvmx_csr_db_addresses_cn56xxp1,
+	cvmx_csr_db_addresses_cn56xx,
+	cvmx_csr_db_addresses_cn50xx,
+	cvmx_csr_db_addresses_cn52xxp1,
+	cvmx_csr_db_addresses_cn52xx,
+	NULL
+};
+const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
+	cvmx_csr_db_fields_cn38xxp2,
+	cvmx_csr_db_fields_cn31xx,
+	cvmx_csr_db_fields_cn30xx,
+	cvmx_csr_db_fields_cn38xx,
+	cvmx_csr_db_fields_cn58xxp1,
+	cvmx_csr_db_fields_cn58xx,
+	cvmx_csr_db_fields_cn56xxp1,
+	cvmx_csr_db_fields_cn56xx,
+	cvmx_csr_db_fields_cn50xx,
+	cvmx_csr_db_fields_cn52xxp1,
+	cvmx_csr_db_fields_cn52xx,
+	NULL
+};
diff --git a/cvmx-csr-db.h b/cvmx-csr-db.h
new file mode 100644
index 0000000000000..a3b0239fcda9d
--- /dev/null
+++ b/cvmx-csr-db.h
@@ -0,0 +1,179 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+#ifndef __CVMX_CSR_DB_H__
+#define __CVMX_CSR_DB_H__
+
+/**
+ * @file
+ * Interface for the Octeon CSR database.
+ *
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#include "cvmx-platform.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+   CVMX_CSR_DB_TYPE_RSL,             /**< Octeon internal address, but indirect and slow (not used for addresses) */
+   CVMX_CSR_DB_TYPE_NCB,             /**< Octeon internal address */
+   CVMX_CSR_DB_TYPE_PCI_NCB,         /**< Can be accessed through PCI BAR0, also an NCB alias (not used for addresses) */
+   CVMX_CSR_DB_TYPE_PCICONFIG,       /**< PCI Config, also an NCB alias */
+   CVMX_CSR_DB_TYPE_PCI,             /**< PCI BAR0 (only) */
+   CVMX_CSR_DB_TYPE_PEXP,            /**< PCIe BAR 0 address only */
+   CVMX_CSR_DB_TYPE_PEXP_NCB,        /**< NCB-direct and PCIe BAR0 address */
+   CVMX_CSR_DB_TYPE_PCICONFIGEP,     /**< PCIe config address (EP mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
+   CVMX_CSR_DB_TYPE_PCICONFIGRC      /**< PCICONFIGRC - PCIe config address (RC mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
+} CVMX_CSR_DB_TYPE_FIELD;
+
+/**
+ * the structure for the cvmx_csr_db_addresses[] array that
+ * holds all possible Octeon CSR addresses
+ */
+typedef struct {
+   char *   name;                   /**< CSR name at the supplied address */
+   uint64_t address;                /**< Address = octeon internal, PCI BAR0 relative, PCI CONFIG relative */
+   CVMX_CSR_DB_TYPE_FIELD type:8;   /**< the type */
+   uint8_t  widthbits;              /**< the width of the CSR in bits */
+   uint16_t csroff;                 /**< position of the CSR in cvmx_csr_db[] */
+} __attribute__ ((packed)) CVMX_CSR_DB_ADDRESS_TYPE;
+
+/**
+ * the structure for the cvmx_csr_db_fields[] array that
+ * holds all possible Octeon CSR fields
+ */
+typedef struct {
+   char *   name;                   /**< name of the field */
+   uint8_t  startbit;               /**< starting bit position of the field */
+   uint8_t  sizebits;               /**< the size of the field in bits */
+   uint16_t csroff;                 /**< position of the CSR containing the field in cvmx_csr_db[] (get alias from there) */
+   char *   type;                   /**< the type of the field R/W, R/W1C, ... */
+   uint8_t  rst_unp;                /**< set if the reset value is unknown */
+   uint8_t  typ_unp;                /**< set if the typical value is unknown */
+   uint64_t rst_val;                /**< the reset value of the field */
+   uint64_t typ_val;                /**< the typical value of the field */
+} __attribute__ ((packed)) CVMX_CSR_DB_FIELD_TYPE;
+
+/**
+ * the structure for the cvmx_csr_db[] array that holds all
+ * possible Octeon CSR forms
+ */
+typedef struct {
+   char *basename;                  /**< the base name of the CSR */
+   CVMX_CSR_DB_TYPE_FIELD type:8;   /**< the type */
+   uint8_t  widthbits;              /**< the width of the CSR in bits */
+   uint16_t addoff;                 /**< the position of the first address in cvmx_csr_db_csr_addresses[] (numblocks*indexnum is #) */
+   uint8_t  numfields;              /**< the number of fields in the CSR (and in cvmx_csr_db_csr_fields[]) */
+   uint16_t fieldoff;               /**< the position of the first field in cvmx_csr_db_csr_fields[] */
+} __attribute__ ((packed)) CVMX_CSR_DB_TYPE;
+
+
+/**
+ * This NULL terminated array contains the CVMX_CSR_DB_TYPE
+ * arrays for each chip. Each array entry is another NULL
+ * terminated array of CSRs.
+ */
+extern const CVMX_CSR_DB_TYPE *cvmx_csr_db[];
+
+/**
+ * This NULL terminated array contains the CVMX_CSR_DB_ADDRESS_TYPE
+ * arrays for each chip. Each array entry is another NULL
+ * terminated array of CSR addresses.
+ */
+extern const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[];
+
+/**
+ * This NULL terminated array contains the CVMX_CSR_DB_FIELD_TYPE
+ * arrays for each chip. Each array entry is another NULL
+ * terminated array of CSR fields.
+ */
+extern const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[];
+
+/**
+ * Figure out which database to use for this chip. The passed
+ * identifier can be a processor ID or a PCI ID.
+ *
+ * @param identifier processor ID or a PCI ID
+ *
+ * @return index into the csr db
+ */
+extern int cvmx_db_get_chipindex(int identifier);
+
+/**
+ * Get the CSR DB entry for the passed Octeon model and CSR name. The
+ * model can either be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param name       CSR name to lookup
+ *
+ * @return CSR DB entry or NULL on failure
+ */
+extern const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const char *name);
+
+/**
+ * Decode a CSR value into named bitfields. The model can either
+ * be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param address    CSR address being decoded
+ * @param value      Value to decode
+ */
+extern void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value);
+
+/**
+ * Print a list of csrs begimning with a prefix. The
+ * model can either be specified as a processor id or PCI id.
+ *
+ * @param identifier Identifer to choose the CSR DB with
+ * @param prefix     Beginning prefix to look for
+ */
+extern void cvmx_csr_db_display_list(int identifier, const char *prefix);
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif
diff --git a/cvmx-csr-enums.h b/cvmx-csr-enums.h
new file mode 100644
index 0000000000000..f6f19a2f77555
--- /dev/null
+++ b/cvmx-csr-enums.h
@@ -0,0 +1,183 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ * Definitions for enumerations used with Octeon CSRs.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#ifndef __CVMX_CSR_ENUMS_H__
+#define __CVMX_CSR_ENUMS_H__
+
+typedef enum {
+   CVMX_IPD_OPC_MODE_STT = 0LL,   /* All blocks DRAM, not cached in L2 */
+   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All bloccks into  L2 */
+   CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
+   CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
+} cvmx_ipd_mode_t;
+
+
+/**
+ * Enumeration representing the amount of packet processing
+ * and validation performed by the input hardware.
+ */
+typedef enum
+{
+    CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,  /**< Packet input doesn't perform any
+                                            processing of the input packet. */
+    CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed
+                                            with pointer starting at the L2
+                                            (ethernet MAC) header. */
+    CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP.
+                                            Results from non IP packets is
+                                            undefined. Pointers reference the
+                                            beginning of the IP header. */
+} cvmx_pip_port_parse_mode_t;
+
+
+/**
+ * This enumeration controls how a QoS watcher matches a packet.
+ *
+ * @deprecated  This enumeration was used with cvmx_pip_config_watcher which has
+ *              been deprecated.
+ */
+typedef enum
+{
+    CVMX_PIP_QOS_WATCH_DISABLE = 0ull,   /**< QoS watcher is diabled */
+    CVMX_PIP_QOS_WATCH_PROTNH = 1ull,    /**< QoS watcher will match based on the IP protocol */
+    CVMX_PIP_QOS_WATCH_TCP = 2ull,       /**< QoS watcher will match TCP packets to a specific destination port */
+    CVMX_PIP_QOS_WATCH_UDP = 3ull        /**< QoS watcher will match UDP packets to a specific destination port */
+} cvmx_pip_qos_watch_types;
+
+/**
+ * This enumeration is used in PIP tag config to control how
+ * POW tags are generated by the hardware.
+ */
+typedef enum
+{
+    CVMX_PIP_TAG_MODE_TUPLE = 0ull,         /**< Always use tuple tag algorithm. This is the only mode supported on Pass 1 */
+    CVMX_PIP_TAG_MODE_MASK = 1ull,          /**< Always use mask tag algorithm */
+    CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull,    /**< If packet is IP, use tuple else use mask */
+    CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull /**< tuple XOR mask */
+} cvmx_pip_tag_mode_t;
+
+/**
+ * Tag type definitions
+ */
+typedef enum
+{
+    CVMX_POW_TAG_TYPE_ORDERED   = 0L,   /**< Tag ordering is maintained */
+    CVMX_POW_TAG_TYPE_ATOMIC    = 1L,   /**< Tag ordering is maintained, and at most one PP has the tag */
+    CVMX_POW_TAG_TYPE_NULL      = 2L,   /**< The work queue entry from the order
+                                            - NEVER tag switch from NULL to NULL */
+    CVMX_POW_TAG_TYPE_NULL_NULL = 3L    /**< A tag switch to NULL, and there is no space reserved in POW
+                                            - NEVER tag switch to NULL_NULL
+                                            - NEVER tag switch from NULL_NULL
+                                            - NULL_NULL is entered at the beginning of time and on a deschedule.
+                                            - NULL_NULL can be exited by a new work request. A NULL_SWITCH load can also switch the state to NULL */
+} cvmx_pow_tag_type_t;
+
+
+/**
+ * LCR bits 0 and 1 control the number of bits per character. See the following table for encodings:
+ *
+ * - 00 = 5 bits (bits 0-4 sent)
+ * - 01 = 6 bits (bits 0-5 sent)
+ * - 10 = 7 bits (bits 0-6 sent)
+ * - 11 = 8 bits (all bits sent)
+ */
+typedef enum
+{
+    CVMX_UART_BITS5 = 0,
+    CVMX_UART_BITS6 = 1,
+    CVMX_UART_BITS7 = 2,
+    CVMX_UART_BITS8 = 3
+} cvmx_uart_bits_t;
+
+
+/**
+ * Interrupt   Priority   Interrupt         Interrupt                                       Interrupt
+ * ID          Level      Type              Source                                          Reset By
+ * ---------------------------------------------------------------------------------------------------------------------------------
+ * 0001        -          None              None                                            -
+ *
+ * 0110        Highest    Receiver Line     Overrun, parity, or framing errors or break     Reading the Line Status Register
+ *                        Status            interrupt
+ *
+ * 0100        Second     Received Data     Receiver data available (FIFOs disabled) or     Reading the Receiver Buffer Register
+ *                        Available         RX FIFO trigger level reached (FIFOs            (FIFOs disabled) or the FIFO drops below
+ *                                          enabled)                                        the trigger level (FIFOs enabled)
+ *
+ * 1100        Second     Character         No characters in or out of the RX FIFO          Reading the Receiver Buffer Register
+ *                        Timeout           during the last 4 character times and there
+ *                        Indication        is at least 1 character in it during this
+ *                                          time
+ *
+ * 0010        Third      Transmitter       Transmitter Holding Register Empty              Reading the Interrupt Identity Register
+ *                        Holding           (Programmable THRE Mode disabled) or TX         (if source of interrupt) or writing into
+ *                        Register          FIFO at or below threshold (Programmable        THR (FIFOs or THRE Mode disabled) or TX
+ *                        Empty             THRE Mode enabled)                              FIFO above threshold (FIFOs and THRE
+ *                                                                                          Mode enabled)
+ *
+ * 0000        Fourth     Modem Status      Clear To Send (CTS) or Data Set Ready (DSR)     Reading the Modem Status Register
+ *                        Changed           or Ring Indicator (RI) or Data Center
+ *                                          Detect (DCD) changed
+ *
+ * 0111        Fifth      Busy Detect       Software has tried to write to the Line         Reading the UART Status Register
+ *                        Indication        Control Register while the BUSY bit of the
+ *                                          UART Status Register was set
+ */
+typedef enum
+{
+    CVMX_UART_IID_NONE          = 1,
+    CVMX_UART_IID_RX_ERROR      = 6,
+    CVMX_UART_IID_RX_DATA       = 4,
+    CVMX_UART_IID_RX_TIMEOUT    = 12,
+    CVMX_UART_IID_TX_EMPTY      = 2,
+    CVMX_UART_IID_MODEM         = 0,
+    CVMX_UART_IID_BUSY          = 7
+} cvmx_uart_iid_t;
+
+#endif /* __CVMX_CSR_ENUMS_H__ */
diff --git a/cvmx-csr-typedefs.h b/cvmx-csr-typedefs.h
new file mode 100644
index 0000000000000..24d63867046ac
--- /dev/null
+++ b/cvmx-csr-typedefs.h
@@ -0,0 +1,73991 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and type definitions for
+ * Octeon. Include cvmx-csr.h instead of this file directly.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#ifndef __CVMX_CSR_TYPEDEFS_H__
+#define __CVMX_CSR_TYPEDEFS_H__
+
+
+/**
+ * cvmx_agl_gmx_bad_reg
+ *
+ * AGL_GMX_BAD_REG = A collection of things that have gone very, very wrong
+ *
+ *
+ * Notes:
+ * OUT_OVR[0], OVRFLW, TXPOP, TXPSH    will be reset when MIX0_CTL[RESET] is set to 1.
+ * OUT_OVR[1], OVRFLW1, TXPOP1, TXPSH1 will be reset when MIX1_CTL[RESET] is set to 1.
+ * LOSTSTAT, STATOVR, STATOVR will bee reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_bad_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t txpsh1                  : 1;       /**< TX FIFO overflow (MII1) */
+        uint64_t txpop1                  : 1;       /**< TX FIFO underflow (MII1) */
+        uint64_t ovrflw1                 : 1;       /**< RX FIFO overflow (MII1) */
+        uint64_t txpsh                   : 1;       /**< TX FIFO overflow */
+        uint64_t txpop                   : 1;       /**< TX FIFO underflow */
+        uint64_t ovrflw                  : 1;       /**< RX FIFO overflow */
+        uint64_t reserved_27_31          : 5;
+        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
+        uint64_t reserved_23_25          : 3;
+        uint64_t loststat                : 1;       /**< TX Statistics data was over-written
+                                                         TX Stats are corrupted */
+        uint64_t reserved_4_21           : 18;
+        uint64_t out_ovr                 : 2;       /**< Outbound data FIFO overflow */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t out_ovr                 : 2;
+        uint64_t reserved_4_21           : 18;
+        uint64_t loststat                : 1;
+        uint64_t reserved_23_25          : 3;
+        uint64_t statovr                 : 1;
+        uint64_t reserved_27_31          : 5;
+        uint64_t ovrflw                  : 1;
+        uint64_t txpop                   : 1;
+        uint64_t txpsh                   : 1;
+        uint64_t ovrflw1                 : 1;
+        uint64_t txpop1                  : 1;
+        uint64_t txpsh1                  : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_agl_gmx_bad_reg_s        cn52xx;
+    struct cvmx_agl_gmx_bad_reg_s        cn52xxp1;
+    struct cvmx_agl_gmx_bad_reg_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_35_63          : 29;
+        uint64_t txpsh                   : 1;       /**< TX FIFO overflow */
+        uint64_t txpop                   : 1;       /**< TX FIFO underflow */
+        uint64_t ovrflw                  : 1;       /**< RX FIFO overflow */
+        uint64_t reserved_27_31          : 5;
+        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
+        uint64_t reserved_23_25          : 3;
+        uint64_t loststat                : 1;       /**< TX Statistics data was over-written
+                                                         TX Stats are corrupted */
+        uint64_t reserved_3_21           : 19;
+        uint64_t out_ovr                 : 1;       /**< Outbound data FIFO overflow */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t out_ovr                 : 1;
+        uint64_t reserved_3_21           : 19;
+        uint64_t loststat                : 1;
+        uint64_t reserved_23_25          : 3;
+        uint64_t statovr                 : 1;
+        uint64_t reserved_27_31          : 5;
+        uint64_t ovrflw                  : 1;
+        uint64_t txpop                   : 1;
+        uint64_t txpsh                   : 1;
+        uint64_t reserved_35_63          : 29;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_bad_reg_cn56xx   cn56xxp1;
+} cvmx_agl_gmx_bad_reg_t;
+
+
+/**
+ * cvmx_agl_gmx_bist
+ *
+ * AGL_GMX_BIST = GMX BIST Results
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_bist_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t status                  : 10;      /**< BIST Results.
+                                                          HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.drf64x78m1_bist
+                                                         - 1: gmx#.outb.fif.drf64x71m1_bist
+                                                         - 2: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 3: 0
+                                                         - 4: 0
+                                                         - 5: 0
+                                                         - 6: gmx#.csr.drf20x80m1_bist
+                                                         - 7: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 8: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 9: 0 */
+#else
+        uint64_t status                  : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_agl_gmx_bist_s           cn52xx;
+    struct cvmx_agl_gmx_bist_s           cn52xxp1;
+    struct cvmx_agl_gmx_bist_s           cn56xx;
+    struct cvmx_agl_gmx_bist_s           cn56xxp1;
+} cvmx_agl_gmx_bist_t;
+
+
+/**
+ * cvmx_agl_gmx_drv_ctl
+ *
+ * AGL_GMX_DRV_CTL = GMX Drive Control
+ *
+ *
+ * Notes:
+ * NCTL, PCTL, BYP_EN    will be reset when MIX0_CTL[RESET] is set to 1.
+ * NCTL1, PCTL1, BYP_EN1 will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_drv_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t byp_en1                 : 1;       /**< Compensation Controller Bypass Enable (MII1) */
+        uint64_t reserved_45_47          : 3;
+        uint64_t pctl1                   : 5;       /**< AGL PCTL (MII1) */
+        uint64_t reserved_37_39          : 3;
+        uint64_t nctl1                   : 5;       /**< AGL NCTL (MII1) */
+        uint64_t reserved_17_31          : 15;
+        uint64_t byp_en                  : 1;       /**< Compensation Controller Bypass Enable */
+        uint64_t reserved_13_15          : 3;
+        uint64_t pctl                    : 5;       /**< AGL PCTL */
+        uint64_t reserved_5_7            : 3;
+        uint64_t nctl                    : 5;       /**< AGL NCTL */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t byp_en                  : 1;
+        uint64_t reserved_17_31          : 15;
+        uint64_t nctl1                   : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t pctl1                   : 5;
+        uint64_t reserved_45_47          : 3;
+        uint64_t byp_en1                 : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_agl_gmx_drv_ctl_s        cn52xx;
+    struct cvmx_agl_gmx_drv_ctl_s        cn52xxp1;
+    struct cvmx_agl_gmx_drv_ctl_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t byp_en                  : 1;       /**< Compensation Controller Bypass Enable */
+        uint64_t reserved_13_15          : 3;
+        uint64_t pctl                    : 5;       /**< AGL PCTL */
+        uint64_t reserved_5_7            : 3;
+        uint64_t nctl                    : 5;       /**< AGL NCTL */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t byp_en                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_drv_ctl_cn56xx   cn56xxp1;
+} cvmx_agl_gmx_drv_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_inf_mode
+ *
+ * AGL_GMX_INF_MODE = Interface Mode
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_inf_mode_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t en                      : 1;       /**< Interface Enable */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t en                      : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_agl_gmx_inf_mode_s       cn52xx;
+    struct cvmx_agl_gmx_inf_mode_s       cn52xxp1;
+    struct cvmx_agl_gmx_inf_mode_s       cn56xx;
+    struct cvmx_agl_gmx_inf_mode_s       cn56xxp1;
+} cvmx_agl_gmx_inf_mode_t;
+
+
+/**
+ * cvmx_agl_gmx_prt#_cfg
+ *
+ * AGL_GMX_PRT_CFG = Port description
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_prtx_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t tx_en                   : 1;       /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all MII cycles will appear as
+                                                         inter-frame cycles. */
+        uint64_t rx_en                   : 1;       /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all MII cycles will appear as
+                                                         inter-frame cycles. */
+        uint64_t slottime                : 1;       /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = Reserved */
+        uint64_t duplex                  : 1;       /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex */
+        uint64_t speed                   : 1;       /**< Link Speed
+                                                         0 = 10/100Mbs operation
+                                                         1 = Reserved */
+        uint64_t en                      : 1;       /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+        uint64_t en                      : 1;
+        uint64_t speed                   : 1;
+        uint64_t duplex                  : 1;
+        uint64_t slottime                : 1;
+        uint64_t rx_en                   : 1;
+        uint64_t tx_en                   : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_agl_gmx_prtx_cfg_s       cn52xx;
+    struct cvmx_agl_gmx_prtx_cfg_s       cn52xxp1;
+    struct cvmx_agl_gmx_prtx_cfg_s       cn56xx;
+    struct cvmx_agl_gmx_prtx_cfg_s       cn56xxp1;
+} cvmx_agl_gmx_prtx_cfg_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam0
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam0_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam0_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam1
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam1_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam1_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam2
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam2_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam2_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam3
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam3_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam3_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam4
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam4_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam4_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam5
+ *
+ * AGL_GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ *
+ * Notes:
+ * Not reset when MIX*_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to AGL_GMX_RX_ADR_CAM will not
+                                                         change the CSR when AGL_GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam5_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam5_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_cam_en
+ *
+ * AGL_GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_cam_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t en                      : 8;       /**< CAM Entry Enables */
+#else
+        uint64_t en                      : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_cam_en_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_adr_ctl
+ *
+ * AGL_GMX_RX_ADR_CTL = Address Filtering Control
+ *
+ *
+ * Notes:
+ * * ALGORITHM
+ *   Here is some pseudo code that represents the address filter behavior.
+ * 
+ *      @verbatim
+ *      bool dmac_addr_filter(uint8 prt, uint48 dmac) [
+ *        ASSERT(prt >= 0 && prt <= 3);
+ *        if (is_bcst(dmac))                               // broadcast accept
+ *          return (AGL_GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
+ *        if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
+ *          return REJECT;
+ *        if (is_mcst(dmac) & AGL_GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
+ *          return ACCEPT;
+ * 
+ *        cam_hit = 0;
+ * 
+ *        for (i=0; i<8; i++) [
+ *          if (AGL_GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
+ *            continue;
+ *          uint48 unswizzled_mac_adr = 0x0;
+ *          for (j=5; j>=0; j--) [
+ *             unswizzled_mac_adr = (unswizzled_mac_adr << 8) | AGL_GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
+ *          ]
+ *          if (unswizzled_mac_adr == dmac) [
+ *            cam_hit = 1;
+ *            break;
+ *          ]
+ *        ]
+ * 
+ *        if (cam_hit)
+ *          return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
+ *        else
+ *          return (AGL_GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
+ *      ]
+ *      @endverbatim
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_adr_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t cam_mode                : 1;       /**< Allow or deny DMAC address filter
+                                                         0 = reject the packet on DMAC address match
+                                                         1 = accept the packet on DMAC address match */
+        uint64_t mcst                    : 2;       /**< Multicast Mode
+                                                         0 = Use the Address Filter CAM
+                                                         1 = Force reject all multicast packets
+                                                         2 = Force accept all multicast packets
+                                                         3 = Reserved */
+        uint64_t bcst                    : 1;       /**< Accept All Broadcast Packets */
+#else
+        uint64_t bcst                    : 1;
+        uint64_t mcst                    : 2;
+        uint64_t cam_mode                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_adr_ctl_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_adr_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_decision
+ *
+ * AGL_GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
+ *
+ *
+ * Notes:
+ * As each byte in a packet is received by GMX, the L2 byte count is compared
+ * against the AGL_GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes
+ * from the beginning of the L2 header (DMAC).  In normal operation, the L2
+ * header begins after the PREAMBLE+SFD (AGL_GMX_RX_FRM_CTL[PRE_CHK]=1) and any
+ * optional UDD skip data (AGL_GMX_RX_UDD_SKP[LEN]).
+ * 
+ * When AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
+ * packet and would require UDD skip length to account for them.
+ * 
+ *                                                 L2 Size
+ * Port Mode             <=AGL_GMX_RX_DECISION bytes (default=24)  >AGL_GMX_RX_DECISION bytes (default=24)
+ * 
+ * MII/Full Duplex       accept packet                             apply filters
+ *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters
+ * 
+ * MII/Half Duplex       drop packet                               apply filters
+ *                       packet is unconditionally dropped         accept packet based on DMAC
+ * 
+ * where l2_size = MAX(0, total_packet_size - AGL_GMX_RX_UDD_SKP[LEN] - ((AGL_GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_decision_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t cnt                     : 5;       /**< The byte count to decide when to accept or filter
+                                                         a packet. */
+#else
+        uint64_t cnt                     : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_decision_s   cn52xx;
+    struct cvmx_agl_gmx_rxx_decision_s   cn52xxp1;
+    struct cvmx_agl_gmx_rxx_decision_s   cn56xx;
+    struct cvmx_agl_gmx_rxx_decision_s   cn56xxp1;
+} cvmx_agl_gmx_rxx_decision_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_frm_chk
+ *
+ * AGL_GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
+ *
+ *
+ * Notes:
+ * If AGL_GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_frm_chk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with MII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t reserved_1_1            : 1;
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_frm_chk_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_frm_chk_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_frm_chk_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_frm_chk_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_chk_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_frm_ctl
+ *
+ * AGL_GMX_RX_FRM_CTL = Frame Control
+ *
+ *
+ * Notes:
+ * * PRE_CHK
+ *   When set, the MII state expects a typical frame consisting of
+ *   INTER_FRAME=>PREAMBLE(x7)=>SFD(x1)=>DAT.  The state machine watches for
+ *   this exact sequence in order to recognize a valid frame and push frame
+ *   data into the Octane.  There must be exactly 7 PREAMBLE cycles followed by
+ *   the single SFD cycle for the frame to be accepted.
+ * 
+ *   When a problem does occur within the PREAMBLE seqeunce, the frame is
+ *   marked as bad and not sent into the core.  The AGL_GMX_RX_INT_REG[PCTERR]
+ *   interrupt is also raised.
+ * 
+ * * PRE_STRP
+ *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
+ *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
+ *   core as part of the packet.
+ * 
+ *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
+ *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes
+ *   are skipped when locating the start of the L2 header for DMAC and Control
+ *   frame recognition.
+ * 
+ * * CTL_BCK/CTL_DRP
+ *   These bits control how the HW handles incoming PAUSE packets.  Here are
+ *   the most common modes of operation:
+ *     CTL_BCK=1,CTL_DRP=1   - HW does it all
+ *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames
+ *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored
+ * 
+ *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
+ *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet
+ *   would constitute an exception which should be handled by the processing
+ *   cores.  PAUSE packets should not be forwarded.
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_frm_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PREAMBLE can be consumed
+                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
+                                                         PRE_STRP must be set for correct operation.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+        uint64_t pad_len                 : 1;       /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data */
+        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
+        uint64_t pre_free                : 1;       /**< When set, PREAMBLE checking is  less strict.
+                                                         0 - 254 cycles of PREAMBLE followed by SFD
+                                                         PRE_FREE must be set if PRE_ALIGN is set.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
+        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
+        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
+        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_STRP must be set if PRE_ALIGN is set.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+        uint64_t pre_chk                 : 1;
+        uint64_t pre_strp                : 1;
+        uint64_t ctl_drp                 : 1;
+        uint64_t ctl_bck                 : 1;
+        uint64_t ctl_mcst                : 1;
+        uint64_t ctl_smac                : 1;
+        uint64_t pre_free                : 1;
+        uint64_t vlan_len                : 1;
+        uint64_t pad_len                 : 1;
+        uint64_t pre_align               : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_frm_ctl_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_frm_max
+ *
+ * AGL_GMX_RX_FRM_MAX = Frame Max length
+ *
+ *
+ * Notes:
+ * When changing the LEN field, be sure that LEN does not exceed
+ * AGL_GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
+ * are within the maximum length parameter to be rejected because they exceed
+ * the AGL_GMX_RX_JABBER[CNT] limit.
+ * 
+ * Notes:
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_frm_max_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t len                     : 16;      /**< Byte count for Max-sized frame check
+                                                         Failing packets set the MAXERR interrupt and are
+                                                         optionally sent with opcode==MAXERR
+                                                         LEN <= AGL_GMX_RX_JABBER[CNT] */
+#else
+        uint64_t len                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_frm_max_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_frm_max_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_frm_max_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_frm_max_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_max_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_frm_min
+ *
+ * AGL_GMX_RX_FRM_MIN = Frame Min length
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_frm_min_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t len                     : 16;      /**< Byte count for Min-sized frame check
+                                                         Failing packets set the MINERR interrupt and are
+                                                         optionally sent with opcode==MINERR */
+#else
+        uint64_t len                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_frm_min_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_frm_min_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_frm_min_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_frm_min_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_frm_min_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_ifg
+ *
+ * AGL_GMX_RX_IFG = RX Min IFG
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_ifg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ifg                     : 4;       /**< Min IFG between packets used to determine IFGERR */
+#else
+        uint64_t ifg                     : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_ifg_s        cn52xx;
+    struct cvmx_agl_gmx_rxx_ifg_s        cn52xxp1;
+    struct cvmx_agl_gmx_rxx_ifg_s        cn56xx;
+    struct cvmx_agl_gmx_rxx_ifg_s        cn56xxp1;
+} cvmx_agl_gmx_rxx_ifg_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_int_en
+ *
+ * AGL_GMX_RX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t reserved_16_18          : 3;
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< MII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
+        uint64_t reserved_9_9            : 1;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t reserved_1_1            : 1;
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t pause_drp               : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_int_en_s     cn52xx;
+    struct cvmx_agl_gmx_rxx_int_en_s     cn52xxp1;
+    struct cvmx_agl_gmx_rxx_int_en_s     cn56xx;
+    struct cvmx_agl_gmx_rxx_int_en_s     cn56xxp1;
+} cvmx_agl_gmx_rxx_int_en_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_int_reg
+ *
+ * AGL_GMX_RX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * (1) exceptions will only be raised to the control processor if the
+ *     corresponding bit in the AGL_GMX_RX_INT_EN register is set.
+ * 
+ * (2) exception conditions 10:0 can also set the rcv/opcode in the received
+ *     packet's workQ entry.  The AGL_GMX_RX_FRM_CHK register provides a bit mask
+ *     for configuring which conditions set the error.
+ * 
+ * (3) in half duplex operation, the expectation is that collisions will appear
+ *     as MINERRs.
+ * 
+ * (4) JABBER - An RX Jabber error indicates that a packet was received which
+ *              is longer than the maximum allowed packet as defined by the
+ *              system.  GMX will truncate the packet at the JABBER count.
+ *              Failure to do so could lead to system instabilty.
+ * 
+ * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
+ *              AGL_GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
+ *              > AGL_GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
+ * 
+ * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < AGL_GMX_RX_FRM_MIN.
+ * 
+ * (8) ALNERR - Indicates that the packet received was not an integer number of
+ *              bytes.  If FCS checking is enabled, ALNERR will only assert if
+ *              the FCS is bad.  If FCS checking is disabled, ALNERR will
+ *              assert in all non-integer frame cases.
+ * 
+ * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision
+ *                  is assumed by the receiver when the received
+ *                  frame < AGL_GMX_RX_FRM_MIN - this is normally a MINERR
+ * 
+ * (A) LENERR - Length errors occur when the received packet does not match the
+ *              length field.  LENERR is only checked for packets between 64
+ *              and 1500 bytes.  For untagged frames, the length must exact
+ *              match.  For tagged frames the length or length+4 must match.
+ * 
+ * (B) PCTERR - checks that the frame transtions from PREAMBLE=>SFD=>DATA.
+ *              Does not check the number of PREAMBLE cycles.
+ * 
+ * (C) OVRERR - Not to be included in the HRM
+ * 
+ *              OVRERR is an architectural assertion check internal to GMX to
+ *              make sure no assumption was violated.  In a correctly operating
+ *              system, this interrupt can never fire.
+ * 
+ *              GMX has an internal arbiter which selects which of 4 ports to
+ *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,
+ *              then each port will typically push a tick every 8 cycles - if
+ *              the packet interface is going as fast as possible.  If there
+ *              are four ports, they push every two cycles.  So that's the
+ *              assumption.  That the inbound module will always be able to
+ *              consume the tick before another is produced.  If that doesn't
+ *              happen - that's when OVRERR will assert.
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t reserved_16_18          : 3;
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< MII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+        uint64_t reserved_9_9            : 1;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with MII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t reserved_1_1            : 1;
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t pause_drp               : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_int_reg_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_int_reg_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_int_reg_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_int_reg_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_int_reg_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_jabber
+ *
+ * AGL_GMX_RX_JABBER = The max size packet after which GMX will truncate
+ *
+ *
+ * Notes:
+ * CNT must be 8-byte aligned such that CNT[2:0] == 0
+ * 
+ *   The packet that will be sent to the packet input logic will have an
+ *   additionl 8 bytes if AGL_GMX_RX_FRM_CTL[PRE_CHK] is set and
+ *   AGL_GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
+ *   defined as...
+ * 
+ *        max_sized_packet = AGL_GMX_RX_JABBER[CNT]+((AGL_GMX_RX_FRM_CTL[PRE_CHK] & !AGL_GMX_RX_FRM_CTL[PRE_STRP])*8)
+ * 
+ *   Be sure the CNT field value is at least as large as the
+ *   AGL_GMX_RX_FRM_MAX[LEN] value. Failure to meet this constraint will cause
+ *   packets that are within the AGL_GMX_RX_FRM_MAX[LEN] length to be rejected
+ *   because they exceed the CNT limit.
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_jabber_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt                     : 16;      /**< Byte count for jabber check
+                                                         Failing packets set the JABBER interrupt and are
+                                                         optionally sent with opcode==JABBER
+                                                         GMX will truncate the packet to CNT bytes
+                                                         CNT >= AGL_GMX_RX_FRM_MAX[LEN] */
+#else
+        uint64_t cnt                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_jabber_s     cn52xx;
+    struct cvmx_agl_gmx_rxx_jabber_s     cn52xxp1;
+    struct cvmx_agl_gmx_rxx_jabber_s     cn56xx;
+    struct cvmx_agl_gmx_rxx_jabber_s     cn56xxp1;
+} cvmx_agl_gmx_rxx_jabber_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_pause_drop_time
+ *
+ * AGL_GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_pause_drop_time_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t status                  : 16;      /**< Time extracted from the dropped PAUSE packet */
+#else
+        uint64_t status                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
+    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
+    struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+} cvmx_agl_gmx_rxx_pause_drop_time_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_ctl
+ *
+ * AGL_GMX_RX_STATS_CTL = RX Stats Control register
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rd_clr                  : 1;       /**< RX Stats registers will clear on reads */
+#else
+        uint64_t rd_clr                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_ctl_s  cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_octs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of received good packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs_ctl
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of received pause packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs_dmac
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of filtered dmac packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_dmac_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_octs_drp
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_octs_drp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of dropped packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_octs_drp_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts
+ *
+ * AGL_GMX_RX_STATS_PKTS
+ * 
+ * Count of good received packets - packets that are not recognized as PAUSE
+ * packets, dropped due the DMAC filter, dropped due FIFO full status, or
+ * have any other OPCODE (FCS, Length, etc).
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_pkts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of received good packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_bad
+ *
+ * AGL_GMX_RX_STATS_PKTS_BAD
+ * 
+ * Count of all packets received with some error that were not dropped
+ * either due to the dmac filter or lack of room in the receive FIFO.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of bad packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_bad_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_ctl
+ *
+ * AGL_GMX_RX_STATS_PKTS_CTL
+ * 
+ * Count of all packets received that were recognized as Flow Control or
+ * PAUSE packets.  PAUSE packets with any kind of error are counted in
+ * AGL_GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or
+ * forwarded based on the AGL_GMX_RX_FRM_CTL[CTL_DRP] bit.  This count
+ * increments regardless of whether the packet is dropped.  Pause packets
+ * will never be counted in AGL_GMX_RX_STATS_PKTS.  Packets dropped due the dmac
+ * filter will be counted in AGL_GMX_RX_STATS_PKTS_DMAC and not here.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of received pause packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_dmac
+ *
+ * AGL_GMX_RX_STATS_PKTS_DMAC
+ * 
+ * Count of all packets received that were dropped by the dmac filter.
+ * Packets that match the DMAC will be dropped and counted here regardless
+ * of if they were bad packets.  These packets will never be counted in
+ * AGL_GMX_RX_STATS_PKTS.
+ * 
+ * Some packets that were not able to satisify the DECISION_CNT may not
+ * actually be dropped by Octeon, but they will be counted here as if they
+ * were dropped.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of filtered dmac packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_dmac_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_stats_pkts_drp
+ *
+ * AGL_GMX_RX_STATS_PKTS_DRP
+ * 
+ * Count of all packets received that were dropped due to a full receive
+ * FIFO.  This counts good and bad packets received - all packets dropped by
+ * the FIFO.  It does not count packets dropped by the dmac or pause packet
+ * filters.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of dropped packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
+    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
+    struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+} cvmx_agl_gmx_rxx_stats_pkts_drp_t;
+
+
+/**
+ * cvmx_agl_gmx_rx#_udd_skp
+ *
+ * AGL_GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
+ *
+ *
+ * Notes:
+ * (1) The skip bytes are part of the packet and will be sent down the NCB
+ *     packet interface and will be handled by PKI.
+ * 
+ * (2) The system can determine if the UDD bytes are included in the FCS check
+ *     by using the FCSSEL field - if the FCS check is enabled.
+ * 
+ * (3) Assume that the preamble/sfd is always at the start of the frame - even
+ *     before UDD bytes.  In most cases, there will be no preamble in these
+ *     cases since it will be MII to MII communication without a PHY
+ *     involved.
+ * 
+ * (4) We can still do address filtering and control packet filtering is the
+ *     user desires.
+ * 
+ * (5) UDD_SKP must be 0 in half-duplex operation unless
+ *     AGL_GMX_RX_FRM_CTL[PRE_CHK] is clear.  If AGL_GMX_RX_FRM_CTL[PRE_CHK] is set,
+ *     then UDD_SKP will normally be 8.
+ * 
+ * (6) In all cases, the UDD bytes will be sent down the packet interface as
+ *     part of the packet.  The UDD bytes are never stripped from the actual
+ *     packet.
+ * 
+ * (7) If LEN != 0, then AGL_GMX_RX_FRM_CHK[LENERR] will be disabled and AGL_GMX_RX_INT_REG[LENERR] will be zero
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rxx_udd_skp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t fcssel                  : 1;       /**< Include the skip bytes in the FCS calculation
+                                                         0 = all skip bytes are included in FCS
+                                                         1 = the skip bytes are not included in FCS */
+        uint64_t reserved_7_7            : 1;
+        uint64_t len                     : 7;       /**< Amount of User-defined data before the start of
+                                                         the L2 data.  Zero means L2 comes first.
+                                                         Max value is 64. */
+#else
+        uint64_t len                     : 7;
+        uint64_t reserved_7_7            : 1;
+        uint64_t fcssel                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rxx_udd_skp_s    cn52xx;
+    struct cvmx_agl_gmx_rxx_udd_skp_s    cn52xxp1;
+    struct cvmx_agl_gmx_rxx_udd_skp_s    cn56xx;
+    struct cvmx_agl_gmx_rxx_udd_skp_s    cn56xxp1;
+} cvmx_agl_gmx_rxx_udd_skp_t;
+
+
+/**
+ * cvmx_agl_gmx_rx_bp_drop#
+ *
+ * AGL_GMX_RX_BP_DROP = FIFO mark for packet drop
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rx_bp_dropx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t mark                    : 6;       /**< Number of 8B ticks to reserve in the RX FIFO.
+                                                         When the FIFO exceeds this count, packets will
+                                                         be dropped and not buffered.
+                                                         MARK should typically be programmed to 2.
+                                                         Failure to program correctly can lead to system
+                                                         instability. */
+#else
+        uint64_t mark                    : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rx_bp_dropx_s    cn52xx;
+    struct cvmx_agl_gmx_rx_bp_dropx_s    cn52xxp1;
+    struct cvmx_agl_gmx_rx_bp_dropx_s    cn56xx;
+    struct cvmx_agl_gmx_rx_bp_dropx_s    cn56xxp1;
+} cvmx_agl_gmx_rx_bp_dropx_t;
+
+
+/**
+ * cvmx_agl_gmx_rx_bp_off#
+ *
+ * AGL_GMX_RX_BP_OFF = Lowater mark for packet drop
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rx_bp_offx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t mark                    : 6;       /**< Water mark (8B ticks) to deassert backpressure */
+#else
+        uint64_t mark                    : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rx_bp_offx_s     cn52xx;
+    struct cvmx_agl_gmx_rx_bp_offx_s     cn52xxp1;
+    struct cvmx_agl_gmx_rx_bp_offx_s     cn56xx;
+    struct cvmx_agl_gmx_rx_bp_offx_s     cn56xxp1;
+} cvmx_agl_gmx_rx_bp_offx_t;
+
+
+/**
+ * cvmx_agl_gmx_rx_bp_on#
+ *
+ * AGL_GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rx_bp_onx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t mark                    : 9;       /**< Hiwater mark (8B ticks) for backpressure. */
+#else
+        uint64_t mark                    : 9;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rx_bp_onx_s      cn52xx;
+    struct cvmx_agl_gmx_rx_bp_onx_s      cn52xxp1;
+    struct cvmx_agl_gmx_rx_bp_onx_s      cn56xx;
+    struct cvmx_agl_gmx_rx_bp_onx_s      cn56xxp1;
+} cvmx_agl_gmx_rx_bp_onx_t;
+
+
+/**
+ * cvmx_agl_gmx_rx_prt_info
+ *
+ * AGL_GMX_RX_PRT_INFO = state information for the ports
+ *
+ *
+ * Notes:
+ * COMMIT[0], DROP[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * COMMIT[1], DROP[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rx_prt_info_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t drop                    : 2;       /**< Port indication that data was dropped */
+        uint64_t reserved_2_15           : 14;
+        uint64_t commit                  : 2;       /**< Port indication that SOP was accepted */
+#else
+        uint64_t commit                  : 2;
+        uint64_t reserved_2_15           : 14;
+        uint64_t drop                    : 2;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rx_prt_info_s    cn52xx;
+    struct cvmx_agl_gmx_rx_prt_info_s    cn52xxp1;
+    struct cvmx_agl_gmx_rx_prt_info_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t drop                    : 1;       /**< Port indication that data was dropped */
+        uint64_t reserved_1_15           : 15;
+        uint64_t commit                  : 1;       /**< Port indication that SOP was accepted */
+#else
+        uint64_t commit                  : 1;
+        uint64_t reserved_1_15           : 15;
+        uint64_t drop                    : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+} cvmx_agl_gmx_rx_prt_info_t;
+
+
+/**
+ * cvmx_agl_gmx_rx_tx_status
+ *
+ * AGL_GMX_RX_TX_STATUS = GMX RX/TX Status
+ *
+ *
+ * Notes:
+ * RX[0], TX[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * RX[1], TX[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_rx_tx_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t tx                      : 2;       /**< Transmit data since last read */
+        uint64_t reserved_2_3            : 2;
+        uint64_t rx                      : 2;       /**< Receive data since last read */
+#else
+        uint64_t rx                      : 2;
+        uint64_t reserved_2_3            : 2;
+        uint64_t tx                      : 2;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_agl_gmx_rx_tx_status_s   cn52xx;
+    struct cvmx_agl_gmx_rx_tx_status_s   cn52xxp1;
+    struct cvmx_agl_gmx_rx_tx_status_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t tx                      : 1;       /**< Transmit data since last read */
+        uint64_t reserved_1_3            : 3;
+        uint64_t rx                      : 1;       /**< Receive data since last read */
+#else
+        uint64_t rx                      : 1;
+        uint64_t reserved_1_3            : 3;
+        uint64_t tx                      : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+} cvmx_agl_gmx_rx_tx_status_t;
+
+
+/**
+ * cvmx_agl_gmx_smac#
+ *
+ * AGL_GMX_SMAC = MII SMAC
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_smacx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t smac                    : 48;      /**< The SMAC field is used for generating and
+                                                         accepting Control Pause packets */
+#else
+        uint64_t smac                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_smacx_s          cn52xx;
+    struct cvmx_agl_gmx_smacx_s          cn52xxp1;
+    struct cvmx_agl_gmx_smacx_s          cn56xx;
+    struct cvmx_agl_gmx_smacx_s          cn56xxp1;
+} cvmx_agl_gmx_smacx_t;
+
+
+/**
+ * cvmx_agl_gmx_stat_bp
+ *
+ * AGL_GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_stat_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t bp                      : 1;       /**< Current BP state */
+        uint64_t cnt                     : 16;      /**< Number of cycles that BP has been asserted
+                                                         Saturating counter */
+#else
+        uint64_t cnt                     : 16;
+        uint64_t bp                      : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_agl_gmx_stat_bp_s        cn52xx;
+    struct cvmx_agl_gmx_stat_bp_s        cn52xxp1;
+    struct cvmx_agl_gmx_stat_bp_s        cn56xx;
+    struct cvmx_agl_gmx_stat_bp_s        cn56xxp1;
+} cvmx_agl_gmx_stat_bp_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_append
+ *
+ * AGL_GMX_TX_APPEND = MII TX Append Control
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_append_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t force_fcs               : 1;       /**< Append the Ethernet FCS on each pause packet
+                                                         when FCS is clear.  Pause packets are normally
+                                                         padded to 60 bytes.  If
+                                                         AGL_GMX_TX_MIN_PKT[MIN_SIZE] exceeds 59, then
+                                                         FORCE_FCS will not be used. */
+        uint64_t fcs                     : 1;       /**< Append the Ethernet FCS on each packet */
+        uint64_t pad                     : 1;       /**< Append PAD bytes such that min sized */
+        uint64_t preamble                : 1;       /**< Prepend the Ethernet preamble on each transfer */
+#else
+        uint64_t preamble                : 1;
+        uint64_t pad                     : 1;
+        uint64_t fcs                     : 1;
+        uint64_t force_fcs               : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_append_s     cn52xx;
+    struct cvmx_agl_gmx_txx_append_s     cn52xxp1;
+    struct cvmx_agl_gmx_txx_append_s     cn56xx;
+    struct cvmx_agl_gmx_txx_append_s     cn56xxp1;
+} cvmx_agl_gmx_txx_append_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_ctl
+ *
+ * AGL_GMX_TX_CTL = TX Control register
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t xsdef_en                : 1;       /**< Enables the excessive deferral check for stats
+                                                         and interrupts */
+        uint64_t xscol_en                : 1;       /**< Enables the excessive collision check for stats
+                                                         and interrupts */
+#else
+        uint64_t xscol_en                : 1;
+        uint64_t xsdef_en                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_ctl_s        cn52xx;
+    struct cvmx_agl_gmx_txx_ctl_s        cn52xxp1;
+    struct cvmx_agl_gmx_txx_ctl_s        cn56xx;
+    struct cvmx_agl_gmx_txx_ctl_s        cn56xxp1;
+} cvmx_agl_gmx_txx_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_min_pkt
+ *
+ * AGL_GMX_TX_MIN_PKT = MII TX Min Size Packet (PAD upto min size)
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_min_pkt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t min_size                : 8;       /**< Min frame in bytes before the FCS is applied
+                                                         Padding is only appened when
+                                                         AGL_GMX_TX_APPEND[PAD] for the coresponding MII
+                                                         port is set. Packets will be padded to
+                                                         MIN_SIZE+1 The reset value will pad to 60 bytes. */
+#else
+        uint64_t min_size                : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_min_pkt_s    cn52xx;
+    struct cvmx_agl_gmx_txx_min_pkt_s    cn52xxp1;
+    struct cvmx_agl_gmx_txx_min_pkt_s    cn56xx;
+    struct cvmx_agl_gmx_txx_min_pkt_s    cn56xxp1;
+} cvmx_agl_gmx_txx_min_pkt_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_pause_pkt_interval
+ *
+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL = MII TX Pause Packet transmission interval - how often PAUSE packets will be sent
+ *
+ *
+ * Notes:
+ * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * AGL_GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ * 
+ * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ * 
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ * 
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_pause_pkt_interval_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t interval                : 16;      /**< Arbitrate for a pause packet every (INTERVAL*512)
+                                                         bit-times.
+                                                         Normally, 0 < INTERVAL < AGL_GMX_TX_PAUSE_PKT_TIME
+                                                         INTERVAL=0, will only send a single PAUSE packet
+                                                         for each backpressure event */
+#else
+        uint64_t interval                : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
+    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
+    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
+    struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_pkt_interval_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_pause_pkt_time
+ *
+ * AGL_GMX_TX_PAUSE_PKT_TIME = MII TX Pause Packet pause_time field
+ *
+ *
+ * Notes:
+ * Choosing proper values of AGL_GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * AGL_GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * AGL_GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ * 
+ * If the system chooses to not set AGL_GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ * 
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ * 
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ * 
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_pause_pkt_time_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t time                    : 16;      /**< The pause_time field placed is outbnd pause pkts
+                                                         pause_time is in 512 bit-times
+                                                         Normally, TIME > AGL_GMX_TX_PAUSE_PKT_INTERVAL */
+#else
+        uint64_t time                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
+    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
+    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
+    struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_pkt_time_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_pause_togo
+ *
+ * AGL_GMX_TX_PAUSE_TOGO = MII TX Amount of time remaining to backpressure
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_pause_togo_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t time                    : 16;      /**< Amount of time remaining to backpressure */
+#else
+        uint64_t time                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
+    struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
+    struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
+    struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_togo_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_pause_zero
+ *
+ * AGL_GMX_TX_PAUSE_ZERO = MII TX Amount of time remaining to backpressure
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_pause_zero_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t send                    : 1;       /**< When backpressure condition clear, send PAUSE
+                                                         packet with pause_time of zero to enable the
+                                                         channel */
+#else
+        uint64_t send                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
+    struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
+    struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
+    struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+} cvmx_agl_gmx_txx_pause_zero_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_soft_pause
+ *
+ * AGL_GMX_TX_SOFT_PAUSE = MII TX Software Pause
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_soft_pause_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t time                    : 16;      /**< Back off the TX bus for (TIME*512) bit-times
+                                                         for full-duplex operation only */
+#else
+        uint64_t time                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
+    struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
+    struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
+    struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+} cvmx_agl_gmx_txx_soft_pause_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat0
+ *
+ * AGL_GMX_TX_STAT0 = AGL_GMX_TX_STATS_XSDEF / AGL_GMX_TX_STATS_XSCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t xsdef                   : 32;      /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive deferal */
+        uint64_t xscol                   : 32;      /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive collision.  Defined by
+                                                         AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
+#else
+        uint64_t xscol                   : 32;
+        uint64_t xsdef                   : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat0_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat0_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat0_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat0_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat0_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat1
+ *
+ * AGL_GMX_TX_STAT1 = AGL_GMX_TX_STATS_SCOL  / AGL_GMX_TX_STATS_MCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t scol                    : 32;      /**< Number of packets sent with a single collision */
+        uint64_t mcol                    : 32;      /**< Number of packets sent with multiple collisions
+                                                         but < AGL_GMX_TX_COL_ATTEMPT[LIMIT]. */
+#else
+        uint64_t mcol                    : 32;
+        uint64_t scol                    : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat1_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat1_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat1_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat1_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat1_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat2
+ *
+ * AGL_GMX_TX_STAT2 = AGL_GMX_TX_STATS_OCTS
+ *
+ *
+ * Notes:
+ * - Octect counts are the sum of all data transmitted on the wire including
+ *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect
+ *   counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t octs                    : 48;      /**< Number of total octets sent on the interface.
+                                                         Does not count octets from frames that were
+                                                         truncated due to collisions in halfdup mode. */
+#else
+        uint64_t octs                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat2_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat2_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat2_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat2_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat2_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat3
+ *
+ * AGL_GMX_TX_STAT3 = AGL_GMX_TX_STATS_PKTS
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pkts                    : 32;      /**< Number of total frames sent on the interface.
+                                                         Does not count frames that were truncated due to
+                                                          collisions in halfdup mode. */
+#else
+        uint64_t pkts                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat3_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat3_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat3_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat3_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat3_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat4
+ *
+ * AGL_GMX_TX_STAT4 = AGL_GMX_TX_STATS_HIST1 (64) / AGL_GMX_TX_STATS_HIST0 (<64)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist1                   : 32;      /**< Number of packets sent with an octet count of 64. */
+        uint64_t hist0                   : 32;      /**< Number of packets sent with an octet count
+                                                         of < 64. */
+#else
+        uint64_t hist0                   : 32;
+        uint64_t hist1                   : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat4_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat4_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat4_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat4_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat4_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat5
+ *
+ * AGL_GMX_TX_STAT5 = AGL_GMX_TX_STATS_HIST3 (128- 255) / AGL_GMX_TX_STATS_HIST2 (65- 127)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist3                   : 32;      /**< Number of packets sent with an octet count of
+                                                         128 - 255. */
+        uint64_t hist2                   : 32;      /**< Number of packets sent with an octet count of
+                                                         65 - 127. */
+#else
+        uint64_t hist2                   : 32;
+        uint64_t hist3                   : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat5_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat5_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat5_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat5_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat5_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat6
+ *
+ * AGL_GMX_TX_STAT6 = AGL_GMX_TX_STATS_HIST5 (512-1023) / AGL_GMX_TX_STATS_HIST4 (256-511)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist5                   : 32;      /**< Number of packets sent with an octet count of
+                                                         512 - 1023. */
+        uint64_t hist4                   : 32;      /**< Number of packets sent with an octet count of
+                                                         256 - 511. */
+#else
+        uint64_t hist4                   : 32;
+        uint64_t hist5                   : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat6_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat6_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat6_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat6_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat6_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat7
+ *
+ * AGL_GMX_TX_STAT7 = AGL_GMX_TX_STATS_HIST7 (1024-1518) / AGL_GMX_TX_STATS_HIST6 (>1518)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist7                   : 32;      /**< Number of packets sent with an octet count
+                                                         of > 1518. */
+        uint64_t hist6                   : 32;      /**< Number of packets sent with an octet count of
+                                                         1024 - 1518. */
+#else
+        uint64_t hist6                   : 32;
+        uint64_t hist7                   : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat7_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat7_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat7_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat7_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat7_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat8
+ *
+ * AGL_GMX_TX_STAT8 = AGL_GMX_TX_STATS_MCST  / AGL_GMX_TX_STATS_BCST
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
+ *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet
+ *   as per the 802.3 frame definition.  If the system requires additional data
+ *   before the L2 header, then the MCST and BCST counters may not reflect
+ *   reality and should be ignored by software.
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat8_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mcst                    : 32;      /**< Number of packets sent to multicast DMAC.
+                                                         Does not include BCST packets. */
+        uint64_t bcst                    : 32;      /**< Number of packets sent to broadcast DMAC.
+                                                         Does not include MCST packets. */
+#else
+        uint64_t bcst                    : 32;
+        uint64_t mcst                    : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat8_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat8_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat8_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat8_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat8_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stat9
+ *
+ * AGL_GMX_TX_STAT9 = AGL_GMX_TX_STATS_UNDFLW / AGL_GMX_TX_STATS_CTL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when AGL_GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Not reset when MIX*_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stat9_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t undflw                  : 32;      /**< Number of underflow packets */
+        uint64_t ctl                     : 32;      /**< Number of Control packets (PAUSE flow control)
+                                                         generated by GMX.  It does not include control
+                                                         packets forwarded or generated by the PP's. */
+#else
+        uint64_t ctl                     : 32;
+        uint64_t undflw                  : 32;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stat9_s      cn52xx;
+    struct cvmx_agl_gmx_txx_stat9_s      cn52xxp1;
+    struct cvmx_agl_gmx_txx_stat9_s      cn56xx;
+    struct cvmx_agl_gmx_txx_stat9_s      cn56xxp1;
+} cvmx_agl_gmx_txx_stat9_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_stats_ctl
+ *
+ * AGL_GMX_TX_STATS_CTL = TX Stats Control register
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_stats_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rd_clr                  : 1;       /**< Stats registers will clear on reads */
+#else
+        uint64_t rd_clr                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_stats_ctl_s  cn52xx;
+    struct cvmx_agl_gmx_txx_stats_ctl_s  cn52xxp1;
+    struct cvmx_agl_gmx_txx_stats_ctl_s  cn56xx;
+    struct cvmx_agl_gmx_txx_stats_ctl_s  cn56xxp1;
+} cvmx_agl_gmx_txx_stats_ctl_t;
+
+
+/**
+ * cvmx_agl_gmx_tx#_thresh
+ *
+ * AGL_GMX_TX_THRESH = MII TX Threshold
+ *
+ *
+ * Notes:
+ * Additionally reset when MIX<prt>_CTL[RESET] is set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_txx_thresh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t cnt                     : 6;       /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                         before sending on the MII interface
+                                                         This register should be large enough to prevent
+                                                         underflow on the MII interface and must never
+                                                         be set below 4.  This register cannot exceed the
+                                                         the TX FIFO depth which is 32 16B entries. */
+#else
+        uint64_t cnt                     : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_agl_gmx_txx_thresh_s     cn52xx;
+    struct cvmx_agl_gmx_txx_thresh_s     cn52xxp1;
+    struct cvmx_agl_gmx_txx_thresh_s     cn56xx;
+    struct cvmx_agl_gmx_txx_thresh_s     cn56xxp1;
+} cvmx_agl_gmx_txx_thresh_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_bp
+ *
+ * AGL_GMX_TX_BP = MII TX BackPressure Register
+ *
+ *
+ * Notes:
+ * BP[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * BP[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t bp                      : 2;       /**< Port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+        uint64_t bp                      : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_bp_s          cn52xx;
+    struct cvmx_agl_gmx_tx_bp_s          cn52xxp1;
+    struct cvmx_agl_gmx_tx_bp_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t bp                      : 1;       /**< Port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+        uint64_t bp                      : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_tx_bp_cn56xx     cn56xxp1;
+} cvmx_agl_gmx_tx_bp_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_col_attempt
+ *
+ * AGL_GMX_TX_COL_ATTEMPT = MII TX collision attempts before dropping frame
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_col_attempt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t limit                   : 5;       /**< Collision Attempts */
+#else
+        uint64_t limit                   : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
+    struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
+    struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
+    struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+} cvmx_agl_gmx_tx_col_attempt_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_ifg
+ *
+ * Common
+ * 
+ * 
+ * AGL_GMX_TX_IFG = MII TX Interframe Gap
+ *
+ * Notes:
+ * Notes:
+ * * Programming IFG1 and IFG2.
+ * 
+ *   For half-duplex systems that require IEEE 802.3 compatibility, IFG1 must
+ *   be in the range of 1-8, IFG2 must be in the range of 4-12, and the
+ *   IFG1+IFG2 sum must be 12.
+ * 
+ *   For full-duplex systems that require IEEE 802.3 compatibility, IFG1 must
+ *   be in the range of 1-11, IFG2 must be in the range of 1-11, and the
+ *   IFG1+IFG2 sum must be 12.
+ * 
+ *   For all other systems, IFG1 and IFG2 can be any value in the range of
+ *   1-15.  Allowing for a total possible IFG sum of 2-30.
+ * 
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_ifg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ifg2                    : 4;       /**< 1/3 of the interframe gap timing
+                                                         If CRS is detected during IFG2, then the
+                                                         interFrameSpacing timer is not reset and a frame
+                                                         is transmited once the timer expires. */
+        uint64_t ifg1                    : 4;       /**< 2/3 of the interframe gap timing
+                                                         If CRS is detected during IFG1, then the
+                                                         interFrameSpacing timer is reset and a frame is
+                                                         not transmited. */
+#else
+        uint64_t ifg1                    : 4;
+        uint64_t ifg2                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_ifg_s         cn52xx;
+    struct cvmx_agl_gmx_tx_ifg_s         cn52xxp1;
+    struct cvmx_agl_gmx_tx_ifg_s         cn56xx;
+    struct cvmx_agl_gmx_tx_ifg_s         cn56xxp1;
+} cvmx_agl_gmx_tx_ifg_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_int_en
+ *
+ * AGL_GMX_TX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t late_col                : 2;       /**< TX Late Collision */
+        uint64_t reserved_14_15          : 2;
+        uint64_t xsdef                   : 2;       /**< TX Excessive deferral (MII/halfdup mode only) */
+        uint64_t reserved_10_11          : 2;
+        uint64_t xscol                   : 2;       /**< TX Excessive collisions (MII/halfdup mode only) */
+        uint64_t reserved_4_7            : 4;
+        uint64_t undflw                  : 2;       /**< TX Underflow (MII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 2;
+        uint64_t reserved_4_7            : 4;
+        uint64_t xscol                   : 2;
+        uint64_t reserved_10_11          : 2;
+        uint64_t xsdef                   : 2;
+        uint64_t reserved_14_15          : 2;
+        uint64_t late_col                : 2;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_int_en_s      cn52xx;
+    struct cvmx_agl_gmx_tx_int_en_s      cn52xxp1;
+    struct cvmx_agl_gmx_tx_int_en_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t late_col                : 1;       /**< TX Late Collision */
+        uint64_t reserved_13_15          : 3;
+        uint64_t xsdef                   : 1;       /**< TX Excessive deferral (MII/halfdup mode only) */
+        uint64_t reserved_9_11           : 3;
+        uint64_t xscol                   : 1;       /**< TX Excessive collisions (MII/halfdup mode only) */
+        uint64_t reserved_3_7            : 5;
+        uint64_t undflw                  : 1;       /**< TX Underflow (MII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 1;
+        uint64_t reserved_3_7            : 5;
+        uint64_t xscol                   : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t xsdef                   : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t late_col                : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_int_en_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_int_reg
+ *
+ * AGL_GMX_TX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * UNDFLW[0], XSCOL[0], XSDEF[0], LATE_COL[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * UNDFLW[1], XSCOL[1], XSDEF[1], LATE_COL[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ * PKO_NXA will bee reset when both MIX0/1_CTL[RESET] are set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t late_col                : 2;       /**< TX Late Collision */
+        uint64_t reserved_14_15          : 2;
+        uint64_t xsdef                   : 2;       /**< TX Excessive deferral (MII/halfdup mode only) */
+        uint64_t reserved_10_11          : 2;
+        uint64_t xscol                   : 2;       /**< TX Excessive collisions (MII/halfdup mode only) */
+        uint64_t reserved_4_7            : 4;
+        uint64_t undflw                  : 2;       /**< TX Underflow (MII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 2;
+        uint64_t reserved_4_7            : 4;
+        uint64_t xscol                   : 2;
+        uint64_t reserved_10_11          : 2;
+        uint64_t xsdef                   : 2;
+        uint64_t reserved_14_15          : 2;
+        uint64_t late_col                : 2;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_int_reg_s     cn52xx;
+    struct cvmx_agl_gmx_tx_int_reg_s     cn52xxp1;
+    struct cvmx_agl_gmx_tx_int_reg_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t late_col                : 1;       /**< TX Late Collision */
+        uint64_t reserved_13_15          : 3;
+        uint64_t xsdef                   : 1;       /**< TX Excessive deferral (MII/halfdup mode only) */
+        uint64_t reserved_9_11           : 3;
+        uint64_t xscol                   : 1;       /**< TX Excessive collisions (MII/halfdup mode only) */
+        uint64_t reserved_3_7            : 5;
+        uint64_t undflw                  : 1;       /**< TX Underflow (MII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 1;
+        uint64_t reserved_3_7            : 5;
+        uint64_t xscol                   : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t xsdef                   : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t late_col                : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_int_reg_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_jam
+ *
+ * AGL_GMX_TX_JAM = MII TX Jam Pattern
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_jam_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t jam                     : 8;       /**< Jam pattern */
+#else
+        uint64_t jam                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_jam_s         cn52xx;
+    struct cvmx_agl_gmx_tx_jam_s         cn52xxp1;
+    struct cvmx_agl_gmx_tx_jam_s         cn56xx;
+    struct cvmx_agl_gmx_tx_jam_s         cn56xxp1;
+} cvmx_agl_gmx_tx_jam_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_lfsr
+ *
+ * AGL_GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_lfsr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t lfsr                    : 16;      /**< The current state of the LFSR used to feed random
+                                                         numbers to compute truncated binary exponential
+                                                         backoff. */
+#else
+        uint64_t lfsr                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_lfsr_s        cn52xx;
+    struct cvmx_agl_gmx_tx_lfsr_s        cn52xxp1;
+    struct cvmx_agl_gmx_tx_lfsr_s        cn56xx;
+    struct cvmx_agl_gmx_tx_lfsr_s        cn56xxp1;
+} cvmx_agl_gmx_tx_lfsr_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_ovr_bp
+ *
+ * AGL_GMX_TX_OVR_BP = MII TX Override BackPressure
+ *
+ *
+ * Notes:
+ * IGN_FULL[0], BP[0], EN[0] will be reset when MIX0_CTL[RESET] is set to 1.
+ * IGN_FULL[1], BP[1], EN[1] will be reset when MIX1_CTL[RESET] is set to 1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_ovr_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t en                      : 2;       /**< Per port Enable back pressure override */
+        uint64_t reserved_6_7            : 2;
+        uint64_t bp                      : 2;       /**< Port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+        uint64_t reserved_2_3            : 2;
+        uint64_t ign_full                : 2;       /**< Ignore the RX FIFO full when computing BP */
+#else
+        uint64_t ign_full                : 2;
+        uint64_t reserved_2_3            : 2;
+        uint64_t bp                      : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t en                      : 2;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_ovr_bp_s      cn52xx;
+    struct cvmx_agl_gmx_tx_ovr_bp_s      cn52xxp1;
+    struct cvmx_agl_gmx_tx_ovr_bp_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t en                      : 1;       /**< Per port Enable back pressure override */
+        uint64_t reserved_5_7            : 3;
+        uint64_t bp                      : 1;       /**< Port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+        uint64_t reserved_1_3            : 3;
+        uint64_t ign_full                : 1;       /**< Ignore the RX FIFO full when computing BP */
+#else
+        uint64_t ign_full                : 1;
+        uint64_t reserved_1_3            : 3;
+        uint64_t bp                      : 1;
+        uint64_t reserved_5_7            : 3;
+        uint64_t en                      : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn56xx;
+    struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+} cvmx_agl_gmx_tx_ovr_bp_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_pause_pkt_dmac
+ *
+ * AGL_GMX_TX_PAUSE_PKT_DMAC = MII TX Pause Packet DMAC field
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t dmac                    : 48;      /**< The DMAC field placed is outbnd pause pkts */
+#else
+        uint64_t dmac                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
+    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
+    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
+    struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+} cvmx_agl_gmx_tx_pause_pkt_dmac_t;
+
+
+/**
+ * cvmx_agl_gmx_tx_pause_pkt_type
+ *
+ * AGL_GMX_TX_PAUSE_PKT_TYPE = MII TX Pause Packet TYPE field
+ *
+ *
+ * Notes:
+ * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_agl_gmx_tx_pause_pkt_type_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t type                    : 16;      /**< The TYPE field placed is outbnd pause pkts */
+#else
+        uint64_t type                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
+    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
+    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
+    struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+} cvmx_agl_gmx_tx_pause_pkt_type_t;
+
+
+/**
+ * cvmx_asx#_gmii_rx_clk_set
+ *
+ * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_gmii_rx_clk_set_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< Setting to place on the RXCLK (GMII receive clk)
+                                                         delay line.  The intrinsic delay can range from
+                                                         50ps to 80ps per tap. */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_gmii_rx_clk_set_s   cn30xx;
+    struct cvmx_asxx_gmii_rx_clk_set_s   cn31xx;
+    struct cvmx_asxx_gmii_rx_clk_set_s   cn50xx;
+} cvmx_asxx_gmii_rx_clk_set_t;
+
+
+/**
+ * cvmx_asx#_gmii_rx_dat_set
+ *
+ * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_gmii_rx_dat_set_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< Setting to place on the RXD (GMII receive data)
+                                                         delay lines.  The intrinsic delay can range from
+                                                         50ps to 80ps per tap. */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_gmii_rx_dat_set_s   cn30xx;
+    struct cvmx_asxx_gmii_rx_dat_set_s   cn31xx;
+    struct cvmx_asxx_gmii_rx_dat_set_s   cn50xx;
+} cvmx_asxx_gmii_rx_dat_set_t;
+
+
+/**
+ * cvmx_asx#_int_en
+ *
+ * ASX_INT_EN = Interrupt Enable
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t txpsh                   : 4;       /**< TX FIFO overflow on RMGII port */
+        uint64_t txpop                   : 4;       /**< TX FIFO underflow on RMGII port */
+        uint64_t ovrflw                  : 4;       /**< RX FIFO overflow on RMGII port */
+#else
+        uint64_t ovrflw                  : 4;
+        uint64_t txpop                   : 4;
+        uint64_t txpsh                   : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_asxx_int_en_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t txpsh                   : 3;       /**< TX FIFO overflow on RMGII port */
+        uint64_t reserved_7_7            : 1;
+        uint64_t txpop                   : 3;       /**< TX FIFO underflow on RMGII port */
+        uint64_t reserved_3_3            : 1;
+        uint64_t ovrflw                  : 3;       /**< RX FIFO overflow on RMGII port */
+#else
+        uint64_t ovrflw                  : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t txpop                   : 3;
+        uint64_t reserved_7_7            : 1;
+        uint64_t txpsh                   : 3;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_int_en_cn30xx       cn31xx;
+    struct cvmx_asxx_int_en_s            cn38xx;
+    struct cvmx_asxx_int_en_s            cn38xxp2;
+    struct cvmx_asxx_int_en_cn30xx       cn50xx;
+    struct cvmx_asxx_int_en_s            cn58xx;
+    struct cvmx_asxx_int_en_s            cn58xxp1;
+} cvmx_asxx_int_en_t;
+
+
+/**
+ * cvmx_asx#_int_reg
+ *
+ * ASX_INT_REG = Interrupt Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t txpsh                   : 4;       /**< TX FIFO overflow on RMGII port */
+        uint64_t txpop                   : 4;       /**< TX FIFO underflow on RMGII port */
+        uint64_t ovrflw                  : 4;       /**< RX FIFO overflow on RMGII port */
+#else
+        uint64_t ovrflw                  : 4;
+        uint64_t txpop                   : 4;
+        uint64_t txpsh                   : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_asxx_int_reg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t txpsh                   : 3;       /**< TX FIFO overflow on RMGII port */
+        uint64_t reserved_7_7            : 1;
+        uint64_t txpop                   : 3;       /**< TX FIFO underflow on RMGII port */
+        uint64_t reserved_3_3            : 1;
+        uint64_t ovrflw                  : 3;       /**< RX FIFO overflow on RMGII port */
+#else
+        uint64_t ovrflw                  : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t txpop                   : 3;
+        uint64_t reserved_7_7            : 1;
+        uint64_t txpsh                   : 3;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_int_reg_cn30xx      cn31xx;
+    struct cvmx_asxx_int_reg_s           cn38xx;
+    struct cvmx_asxx_int_reg_s           cn38xxp2;
+    struct cvmx_asxx_int_reg_cn30xx      cn50xx;
+    struct cvmx_asxx_int_reg_s           cn58xx;
+    struct cvmx_asxx_int_reg_s           cn58xxp1;
+} cvmx_asxx_int_reg_t;
+
+
+/**
+ * cvmx_asx#_mii_rx_dat_set
+ *
+ * ASX_MII_RX_DAT_SET = GMII Clock delay setting
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_mii_rx_dat_set_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< Setting to place on the RXD (MII receive data)
+                                                         delay lines.  The intrinsic delay can range from
+                                                         50ps to 80ps per tap. */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_mii_rx_dat_set_s    cn30xx;
+    struct cvmx_asxx_mii_rx_dat_set_s    cn50xx;
+} cvmx_asxx_mii_rx_dat_set_t;
+
+
+/**
+ * cvmx_asx#_prt_loop
+ *
+ * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_prt_loop_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ext_loop                : 4;       /**< External Loopback Enable
+                                                         0 = No Loopback (TX FIFO is filled by RMGII)
+                                                         1 = RX FIFO drives the TX FIFO
+                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
+                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
+                                                             - core clock > 250MHZ
+                                                             - rxc must not deviate from the +-50ppm
+                                                             - if txc>rxc, idle cycle may drop over time */
+        uint64_t int_loop                : 4;       /**< Internal Loopback Enable
+                                                         0 = No Loopback (RX FIFO is filled by RMGII pins)
+                                                         1 = TX FIFO drives the RX FIFO
+                                                         Note, in internal loop-back mode, the RGMII link
+                                                         status is not used (since there is no real PHY).
+                                                         Software cannot use the inband status. */
+#else
+        uint64_t int_loop                : 4;
+        uint64_t ext_loop                : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_asxx_prt_loop_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t ext_loop                : 3;       /**< External Loopback Enable
+                                                         0 = No Loopback (TX FIFO is filled by RMGII)
+                                                         1 = RX FIFO drives the TX FIFO
+                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
+                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
+                                                             - core clock > 250MHZ
+                                                             - rxc must not deviate from the +-50ppm
+                                                             - if txc>rxc, idle cycle may drop over time */
+        uint64_t reserved_3_3            : 1;
+        uint64_t int_loop                : 3;       /**< Internal Loopback Enable
+                                                         0 = No Loopback (RX FIFO is filled by RMGII pins)
+                                                         1 = TX FIFO drives the RX FIFO
+                                                             - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
+                                                             - GMX_PRT_CFG[SPEED] must be 1  (GigE speed)
+                                                             - GMX_TX_CLK[CLK_CNT] must be 1
+                                                         Note, in internal loop-back mode, the RGMII link
+                                                         status is not used (since there is no real PHY).
+                                                         Software cannot use the inband status. */
+#else
+        uint64_t int_loop                : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t ext_loop                : 3;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_prt_loop_cn30xx     cn31xx;
+    struct cvmx_asxx_prt_loop_s          cn38xx;
+    struct cvmx_asxx_prt_loop_s          cn38xxp2;
+    struct cvmx_asxx_prt_loop_cn30xx     cn50xx;
+    struct cvmx_asxx_prt_loop_s          cn58xx;
+    struct cvmx_asxx_prt_loop_s          cn58xxp1;
+} cvmx_asxx_prt_loop_t;
+
+
+/**
+ * cvmx_asx#_rld_bypass
+ *
+ * ASX_RLD_BYPASS
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_bypass_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t bypass                  : 1;       /**< When set, the rld_dll setting is bypassed with
+                                                         ASX_RLD_BYPASS_SETTING */
+#else
+        uint64_t bypass                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_asxx_rld_bypass_s        cn38xx;
+    struct cvmx_asxx_rld_bypass_s        cn38xxp2;
+    struct cvmx_asxx_rld_bypass_s        cn58xx;
+    struct cvmx_asxx_rld_bypass_s        cn58xxp1;
+} cvmx_asxx_rld_bypass_t;
+
+
+/**
+ * cvmx_asx#_rld_bypass_setting
+ *
+ * ASX_RLD_BYPASS_SETTING
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_bypass_setting_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< The rld_dll setting bypass value */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_rld_bypass_setting_s cn38xx;
+    struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
+    struct cvmx_asxx_rld_bypass_setting_s cn58xx;
+    struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
+} cvmx_asxx_rld_bypass_setting_t;
+
+
+/**
+ * cvmx_asx#_rld_comp
+ *
+ * ASX_RLD_COMP
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_comp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t pctl                    : 5;       /**< PCTL Compensation Value
+                                                         These bits reflect the computed compensation
+                                                          values from the built-in compensation circuit. */
+        uint64_t nctl                    : 4;       /**< These bits reflect the computed compensation
+                                                         values from the built-in compensation circuit. */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_asxx_rld_comp_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t pctl                    : 4;       /**< These bits reflect the computed compensation
+                                                         values from the built-in compensation circuit. */
+        uint64_t nctl                    : 4;       /**< These bits reflect the computed compensation
+                                                         values from the built-in compensation circuit. */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } cn38xx;
+    struct cvmx_asxx_rld_comp_cn38xx     cn38xxp2;
+    struct cvmx_asxx_rld_comp_s          cn58xx;
+    struct cvmx_asxx_rld_comp_s          cn58xxp1;
+} cvmx_asxx_rld_comp_t;
+
+
+/**
+ * cvmx_asx#_rld_data_drv
+ *
+ * ASX_RLD_DATA_DRV
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_data_drv_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t pctl                    : 4;       /**< These bits specify a driving strength (positive
+                                                         integer) for the RLD I/Os when the built-in
+                                                         compensation circuit is bypassed. */
+        uint64_t nctl                    : 4;       /**< These bits specify a driving strength (positive
+                                                         integer) for the RLD I/Os when the built-in
+                                                         compensation circuit is bypassed. */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_asxx_rld_data_drv_s      cn38xx;
+    struct cvmx_asxx_rld_data_drv_s      cn38xxp2;
+    struct cvmx_asxx_rld_data_drv_s      cn58xx;
+    struct cvmx_asxx_rld_data_drv_s      cn58xxp1;
+} cvmx_asxx_rld_data_drv_t;
+
+
+/**
+ * cvmx_asx#_rld_fcram_mode
+ *
+ * ASX_RLD_FCRAM_MODE
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_fcram_mode_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t mode                    : 1;       /**< Memory Mode
+                                                         - 0: RLDRAM
+                                                         - 1: FCRAM */
+#else
+        uint64_t mode                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_asxx_rld_fcram_mode_s    cn38xx;
+    struct cvmx_asxx_rld_fcram_mode_s    cn38xxp2;
+} cvmx_asxx_rld_fcram_mode_t;
+
+
+/**
+ * cvmx_asx#_rld_nctl_strong
+ *
+ * ASX_RLD_NCTL_STRONG
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_nctl_strong_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t nctl                    : 5;       /**< Duke's drive control */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_rld_nctl_strong_s   cn38xx;
+    struct cvmx_asxx_rld_nctl_strong_s   cn38xxp2;
+    struct cvmx_asxx_rld_nctl_strong_s   cn58xx;
+    struct cvmx_asxx_rld_nctl_strong_s   cn58xxp1;
+} cvmx_asxx_rld_nctl_strong_t;
+
+
+/**
+ * cvmx_asx#_rld_nctl_weak
+ *
+ * ASX_RLD_NCTL_WEAK
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_nctl_weak_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t nctl                    : 5;       /**< UNUSED (not needed for O9N) */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_rld_nctl_weak_s     cn38xx;
+    struct cvmx_asxx_rld_nctl_weak_s     cn38xxp2;
+    struct cvmx_asxx_rld_nctl_weak_s     cn58xx;
+    struct cvmx_asxx_rld_nctl_weak_s     cn58xxp1;
+} cvmx_asxx_rld_nctl_weak_t;
+
+
+/**
+ * cvmx_asx#_rld_pctl_strong
+ *
+ * ASX_RLD_PCTL_STRONG
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_pctl_strong_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t pctl                    : 5;       /**< Duke's drive control */
+#else
+        uint64_t pctl                    : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_rld_pctl_strong_s   cn38xx;
+    struct cvmx_asxx_rld_pctl_strong_s   cn38xxp2;
+    struct cvmx_asxx_rld_pctl_strong_s   cn58xx;
+    struct cvmx_asxx_rld_pctl_strong_s   cn58xxp1;
+} cvmx_asxx_rld_pctl_strong_t;
+
+
+/**
+ * cvmx_asx#_rld_pctl_weak
+ *
+ * ASX_RLD_PCTL_WEAK
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_pctl_weak_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t pctl                    : 5;       /**< UNUSED (not needed for O9N) */
+#else
+        uint64_t pctl                    : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_rld_pctl_weak_s     cn38xx;
+    struct cvmx_asxx_rld_pctl_weak_s     cn38xxp2;
+    struct cvmx_asxx_rld_pctl_weak_s     cn58xx;
+    struct cvmx_asxx_rld_pctl_weak_s     cn58xxp1;
+} cvmx_asxx_rld_pctl_weak_t;
+
+
+/**
+ * cvmx_asx#_rld_setting
+ *
+ * ASX_RLD_SETTING
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rld_setting_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t dfaset                  : 5;       /**< RLD ClkGen DLL Setting(debug)
+                                                         ** NEW O9N ** */
+        uint64_t dfalag                  : 1;       /**< RLD ClkGen DLL Lag Error(debug)
+                                                         ** NEW O9N ** */
+        uint64_t dfalead                 : 1;       /**< RLD ClkGen DLL Lead Error(debug)
+                                                         ** NEW O9N ** */
+        uint64_t dfalock                 : 1;       /**< RLD ClkGen DLL Lock acquisition(debug)
+                                                         ** NEW O9N ** */
+        uint64_t setting                 : 5;       /**< RLDCK90 DLL Setting(debug) */
+#else
+        uint64_t setting                 : 5;
+        uint64_t dfalock                 : 1;
+        uint64_t dfalead                 : 1;
+        uint64_t dfalag                  : 1;
+        uint64_t dfaset                  : 5;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_asxx_rld_setting_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< This is the read-only true rld dll_setting. */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn38xx;
+    struct cvmx_asxx_rld_setting_cn38xx  cn38xxp2;
+    struct cvmx_asxx_rld_setting_s       cn58xx;
+    struct cvmx_asxx_rld_setting_s       cn58xxp1;
+} cvmx_asxx_rld_setting_t;
+
+
+/**
+ * cvmx_asx#_rx_clk_set#
+ *
+ * ASX_RX_CLK_SET = RGMII Clock delay setting
+ *
+ *
+ * Notes:
+ * Setting to place on the open-loop RXC (RGMII receive clk)
+ * delay line, which can delay the recieved clock. This
+ * can be used if the board and/or transmitting device
+ * has not otherwise delayed the clock.
+ * 
+ * A value of SETTING=0 disables the delay line. The delay
+ * line should be disabled unless the transmitter or board
+ * does not delay the clock.
+ * 
+ * Note that this delay line provides only a coarse control
+ * over the delay. Generally, it can only reliably provide
+ * a delay in the range 1.25-2.5ns, which may not be adequate
+ * for some system applications.
+ * 
+ * The open loop delay line selects
+ * from among a series of tap positions. Each incremental
+ * tap position adds a delay of 50ps to 135ps per tap, depending
+ * on the chip, its temperature, and the voltage.
+ * To achieve from 1.25-2.5ns of delay on the recieved
+ * clock, a fixed value of SETTING=24 may work.
+ * For more precision, we recommend the following settings
+ * based on the chip voltage:
+ * 
+ *    VDD           SETTING
+ *  -----------------------------
+ *    1.0             18
+ *    1.05            19
+ *    1.1             21
+ *    1.15            22
+ *    1.2             23
+ *    1.25            24
+ *    1.3             25
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rx_clk_setx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< Setting to place on the open-loop RXC delay line */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_rx_clk_setx_s       cn30xx;
+    struct cvmx_asxx_rx_clk_setx_s       cn31xx;
+    struct cvmx_asxx_rx_clk_setx_s       cn38xx;
+    struct cvmx_asxx_rx_clk_setx_s       cn38xxp2;
+    struct cvmx_asxx_rx_clk_setx_s       cn50xx;
+    struct cvmx_asxx_rx_clk_setx_s       cn58xx;
+    struct cvmx_asxx_rx_clk_setx_s       cn58xxp1;
+} cvmx_asxx_rx_clk_setx_t;
+
+
+/**
+ * cvmx_asx#_rx_prt_en
+ *
+ * ASX_RX_PRT_EN = RGMII Port Enable
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rx_prt_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t prt_en                  : 4;       /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+        uint64_t prt_en                  : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_asxx_rx_prt_en_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t prt_en                  : 3;       /**< Port enable.  Must be set for Octane to receive
+                                                         RMGII traffic.  When this bit clear on a given
+                                                         port, then the all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+        uint64_t prt_en                  : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_rx_prt_en_cn30xx    cn31xx;
+    struct cvmx_asxx_rx_prt_en_s         cn38xx;
+    struct cvmx_asxx_rx_prt_en_s         cn38xxp2;
+    struct cvmx_asxx_rx_prt_en_cn30xx    cn50xx;
+    struct cvmx_asxx_rx_prt_en_s         cn58xx;
+    struct cvmx_asxx_rx_prt_en_s         cn58xxp1;
+} cvmx_asxx_rx_prt_en_t;
+
+
+/**
+ * cvmx_asx#_rx_wol
+ *
+ * ASX_RX_WOL = RGMII RX Wake on LAN status register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rx_wol_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t status                  : 1;       /**< Copy of PMCSR[15] - PME_status */
+        uint64_t enable                  : 1;       /**< Copy of PMCSR[8]  - PME_enable */
+#else
+        uint64_t enable                  : 1;
+        uint64_t status                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_asxx_rx_wol_s            cn38xx;
+    struct cvmx_asxx_rx_wol_s            cn38xxp2;
+} cvmx_asxx_rx_wol_t;
+
+
+/**
+ * cvmx_asx#_rx_wol_msk
+ *
+ * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rx_wol_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t msk                     : 64;      /**< Bytes to include in the CRC signature */
+#else
+        uint64_t msk                     : 64;
+#endif
+    } s;
+    struct cvmx_asxx_rx_wol_msk_s        cn38xx;
+    struct cvmx_asxx_rx_wol_msk_s        cn38xxp2;
+} cvmx_asxx_rx_wol_msk_t;
+
+
+/**
+ * cvmx_asx#_rx_wol_powok
+ *
+ * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rx_wol_powok_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t powerok                 : 1;       /**< Power OK */
+#else
+        uint64_t powerok                 : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_asxx_rx_wol_powok_s      cn38xx;
+    struct cvmx_asxx_rx_wol_powok_s      cn38xxp2;
+} cvmx_asxx_rx_wol_powok_t;
+
+
+/**
+ * cvmx_asx#_rx_wol_sig
+ *
+ * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_rx_wol_sig_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t sig                     : 32;      /**< CRC signature */
+#else
+        uint64_t sig                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_asxx_rx_wol_sig_s        cn38xx;
+    struct cvmx_asxx_rx_wol_sig_s        cn38xxp2;
+} cvmx_asxx_rx_wol_sig_t;
+
+
+/**
+ * cvmx_asx#_tx_clk_set#
+ *
+ * ASX_TX_CLK_SET = RGMII Clock delay setting
+ *
+ *
+ * Notes:
+ * Setting to place on the open-loop TXC (RGMII transmit clk)
+ * delay line, which can delay the transmited clock. This
+ * can be used if the board and/or transmitting device
+ * has not otherwise delayed the clock.
+ * 
+ * A value of SETTING=0 disables the delay line. The delay
+ * line should be disabled unless the transmitter or board
+ * does not delay the clock.
+ * 
+ * Note that this delay line provides only a coarse control
+ * over the delay. Generally, it can only reliably provide
+ * a delay in the range 1.25-2.5ns, which may not be adequate
+ * for some system applications.
+ * 
+ * The open loop delay line selects
+ * from among a series of tap positions. Each incremental
+ * tap position adds a delay of 50ps to 135ps per tap, depending
+ * on the chip, its temperature, and the voltage.
+ * To achieve from 1.25-2.5ns of delay on the recieved
+ * clock, a fixed value of SETTING=24 may work.
+ * For more precision, we recommend the following settings
+ * based on the chip voltage:
+ * 
+ *    VDD           SETTING
+ *  -----------------------------
+ *    1.0             18
+ *    1.05            19
+ *    1.1             21
+ *    1.15            22
+ *    1.2             23
+ *    1.25            24
+ *    1.3             25
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_tx_clk_setx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t setting                 : 5;       /**< Setting to place on the open-loop TXC delay line */
+#else
+        uint64_t setting                 : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_asxx_tx_clk_setx_s       cn30xx;
+    struct cvmx_asxx_tx_clk_setx_s       cn31xx;
+    struct cvmx_asxx_tx_clk_setx_s       cn38xx;
+    struct cvmx_asxx_tx_clk_setx_s       cn38xxp2;
+    struct cvmx_asxx_tx_clk_setx_s       cn50xx;
+    struct cvmx_asxx_tx_clk_setx_s       cn58xx;
+    struct cvmx_asxx_tx_clk_setx_s       cn58xxp1;
+} cvmx_asxx_tx_clk_setx_t;
+
+
+/**
+ * cvmx_asx#_tx_comp_byp
+ *
+ * ASX_TX_COMP_BYP = RGMII Clock delay setting
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_tx_comp_byp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_asxx_tx_comp_byp_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t bypass                  : 1;       /**< Compensation bypass */
+        uint64_t pctl                    : 4;       /**< PCTL Compensation Value (see Duke) */
+        uint64_t nctl                    : 4;       /**< NCTL Compensation Value (see Duke) */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 4;
+        uint64_t bypass                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_tx_comp_byp_cn30xx  cn31xx;
+    struct cvmx_asxx_tx_comp_byp_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t pctl                    : 4;       /**< PCTL Compensation Value (see Duke) */
+        uint64_t nctl                    : 4;       /**< NCTL Compensation Value (see Duke) */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } cn38xx;
+    struct cvmx_asxx_tx_comp_byp_cn38xx  cn38xxp2;
+    struct cvmx_asxx_tx_comp_byp_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t bypass                  : 1;       /**< Compensation bypass */
+        uint64_t reserved_13_15          : 3;
+        uint64_t pctl                    : 5;       /**< PCTL Compensation Value (see Duke) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t nctl                    : 5;       /**< NCTL Compensation Value (see Duke) */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t bypass                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn50xx;
+    struct cvmx_asxx_tx_comp_byp_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t pctl                    : 5;       /**< PCTL Compensation Value (see Duke) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t nctl                    : 5;       /**< NCTL Compensation Value (see Duke) */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn58xx;
+    struct cvmx_asxx_tx_comp_byp_cn58xx  cn58xxp1;
+} cvmx_asxx_tx_comp_byp_t;
+
+
+/**
+ * cvmx_asx#_tx_hi_water#
+ *
+ * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_tx_hi_waterx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t mark                    : 4;       /**< TX FIFO HiWatermark to stall GMX
+                                                         Value of 0 maps to 16
+                                                         Reset value changed from 10 in pass1
+                                                         Pass1 settings (assuming 125 tclk)
+                                                         - 325-375: 12
+                                                         - 375-437: 11
+                                                         - 437-550: 10
+                                                         - 550-687:  9 */
+#else
+        uint64_t mark                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_asxx_tx_hi_waterx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t mark                    : 3;       /**< TX FIFO HiWatermark to stall GMX
+                                                         Value 0 maps to 8. */
+#else
+        uint64_t mark                    : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
+    struct cvmx_asxx_tx_hi_waterx_s      cn38xx;
+    struct cvmx_asxx_tx_hi_waterx_s      cn38xxp2;
+    struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
+    struct cvmx_asxx_tx_hi_waterx_s      cn58xx;
+    struct cvmx_asxx_tx_hi_waterx_s      cn58xxp1;
+} cvmx_asxx_tx_hi_waterx_t;
+
+
+/**
+ * cvmx_asx#_tx_prt_en
+ *
+ * ASX_TX_PRT_EN = RGMII Port Enable
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asxx_tx_prt_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t prt_en                  : 4;       /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+        uint64_t prt_en                  : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_asxx_tx_prt_en_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t prt_en                  : 3;       /**< Port enable.  Must be set for Octane to send
+                                                         RMGII traffic.   When this bit clear on a given
+                                                         port, then all RGMII cycles will appear as
+                                                         inter-frame cycles. */
+#else
+        uint64_t prt_en                  : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_asxx_tx_prt_en_cn30xx    cn31xx;
+    struct cvmx_asxx_tx_prt_en_s         cn38xx;
+    struct cvmx_asxx_tx_prt_en_s         cn38xxp2;
+    struct cvmx_asxx_tx_prt_en_cn30xx    cn50xx;
+    struct cvmx_asxx_tx_prt_en_s         cn58xx;
+    struct cvmx_asxx_tx_prt_en_s         cn58xxp1;
+} cvmx_asxx_tx_prt_en_t;
+
+
+/**
+ * cvmx_asx0_dbg_data_drv
+ *
+ * ASX_DBG_DATA_DRV
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asx0_dbg_data_drv_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t pctl                    : 5;       /**< These bits control the driving strength of the dbg
+                                                         interface. */
+        uint64_t nctl                    : 4;       /**< These bits control the driving strength of the dbg
+                                                         interface. */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_asx0_dbg_data_drv_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t pctl                    : 4;       /**< These bits control the driving strength of the dbg
+                                                         interface. */
+        uint64_t nctl                    : 4;       /**< These bits control the driving strength of the dbg
+                                                         interface. */
+#else
+        uint64_t nctl                    : 4;
+        uint64_t pctl                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } cn38xx;
+    struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2;
+    struct cvmx_asx0_dbg_data_drv_s      cn58xx;
+    struct cvmx_asx0_dbg_data_drv_s      cn58xxp1;
+} cvmx_asx0_dbg_data_drv_t;
+
+
+/**
+ * cvmx_asx0_dbg_data_enable
+ *
+ * ASX_DBG_DATA_ENABLE
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_asx0_dbg_data_enable_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t en                      : 1;       /**< A 1->0 transistion, turns the dbg interface OFF. */
+#else
+        uint64_t en                      : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_asx0_dbg_data_enable_s   cn38xx;
+    struct cvmx_asx0_dbg_data_enable_s   cn38xxp2;
+    struct cvmx_asx0_dbg_data_enable_s   cn58xx;
+    struct cvmx_asx0_dbg_data_enable_s   cn58xxp1;
+} cvmx_asx0_dbg_data_enable_t;
+
+
+/**
+ * cvmx_ciu_bist
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_bist_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t bist                    : 4;       /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+        uint64_t bist                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_ciu_bist_s               cn30xx;
+    struct cvmx_ciu_bist_s               cn31xx;
+    struct cvmx_ciu_bist_s               cn38xx;
+    struct cvmx_ciu_bist_s               cn38xxp2;
+    struct cvmx_ciu_bist_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t bist                    : 2;       /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+        uint64_t bist                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn50xx;
+    struct cvmx_ciu_bist_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t bist                    : 3;       /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+        uint64_t bist                    : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_bist_cn52xx          cn52xxp1;
+    struct cvmx_ciu_bist_s               cn56xx;
+    struct cvmx_ciu_bist_s               cn56xxp1;
+    struct cvmx_ciu_bist_s               cn58xx;
+    struct cvmx_ciu_bist_s               cn58xxp1;
+} cvmx_ciu_bist_t;
+
+
+/**
+ * cvmx_ciu_dint
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_dint_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dint                    : 16;      /**< Send DINT pulse to PP vector */
+#else
+        uint64_t dint                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_ciu_dint_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t dint                    : 1;       /**< Send DINT pulse to PP vector */
+#else
+        uint64_t dint                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_dint_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dint                    : 2;       /**< Send DINT pulse to PP vector */
+#else
+        uint64_t dint                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_dint_s               cn38xx;
+    struct cvmx_ciu_dint_s               cn38xxp2;
+    struct cvmx_ciu_dint_cn31xx          cn50xx;
+    struct cvmx_ciu_dint_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t dint                    : 4;       /**< Send DINT pulse to PP vector */
+#else
+        uint64_t dint                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_dint_cn52xx          cn52xxp1;
+    struct cvmx_ciu_dint_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t dint                    : 12;      /**< Send DINT pulse to PP vector */
+#else
+        uint64_t dint                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_dint_cn56xx          cn56xxp1;
+    struct cvmx_ciu_dint_s               cn58xx;
+    struct cvmx_ciu_dint_s               cn58xxp1;
+} cvmx_ciu_dint_t;
+
+
+/**
+ * cvmx_ciu_fuse
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_fuse_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t fuse                    : 16;      /**< Physical PP is present */
+#else
+        uint64_t fuse                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_ciu_fuse_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t fuse                    : 1;       /**< Physical PP is present */
+#else
+        uint64_t fuse                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_fuse_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t fuse                    : 2;       /**< Physical PP is present */
+#else
+        uint64_t fuse                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_fuse_s               cn38xx;
+    struct cvmx_ciu_fuse_s               cn38xxp2;
+    struct cvmx_ciu_fuse_cn31xx          cn50xx;
+    struct cvmx_ciu_fuse_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t fuse                    : 4;       /**< Physical PP is present */
+#else
+        uint64_t fuse                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_fuse_cn52xx          cn52xxp1;
+    struct cvmx_ciu_fuse_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t fuse                    : 12;      /**< Physical PP is present */
+#else
+        uint64_t fuse                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_fuse_cn56xx          cn56xxp1;
+    struct cvmx_ciu_fuse_s               cn58xx;
+    struct cvmx_ciu_fuse_s               cn58xxp1;
+} cvmx_ciu_fuse_t;
+
+
+/**
+ * cvmx_ciu_gstop
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_gstop_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t gstop                   : 1;       /**< GSTOP bit */
+#else
+        uint64_t gstop                   : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_ciu_gstop_s              cn30xx;
+    struct cvmx_ciu_gstop_s              cn31xx;
+    struct cvmx_ciu_gstop_s              cn38xx;
+    struct cvmx_ciu_gstop_s              cn38xxp2;
+    struct cvmx_ciu_gstop_s              cn50xx;
+    struct cvmx_ciu_gstop_s              cn52xx;
+    struct cvmx_ciu_gstop_s              cn52xxp1;
+    struct cvmx_ciu_gstop_s              cn56xx;
+    struct cvmx_ciu_gstop_s              cn56xxp1;
+    struct cvmx_ciu_gstop_s              cn58xx;
+    struct cvmx_ciu_gstop_s              cn58xxp1;
+} cvmx_ciu_gstop_t;
+
+
+/**
+ * cvmx_ciu_int#_en0
+ *
+ * Notes:
+ * CIU_INT0_EN0:  PP0 /IP2
+ * CIU_INT1_EN0:  PP0 /IP3
+ * ...
+ * CIU_INT6_EN0:  PP3/IP2
+ * CIU_INT7_EN0:  PP3/IP3
+ * (hole)
+ * CIU_INT32_EN0: PCI /IP
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t reserved_47_47          : 1;
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t reserved_47_47          : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_intx_en0_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_intx_en0_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn38xx;
+    struct cvmx_ciu_intx_en0_cn38xx      cn38xxp2;
+    struct cvmx_ciu_intx_en0_cn30xx      cn50xx;
+    struct cvmx_ciu_intx_en0_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en0_cn52xx      cn52xxp1;
+    struct cvmx_ciu_intx_en0_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en0_cn56xx      cn56xxp1;
+    struct cvmx_ciu_intx_en0_cn38xx      cn58xx;
+    struct cvmx_ciu_intx_en0_cn38xx      cn58xxp1;
+} cvmx_ciu_intx_en0_t;
+
+
+/**
+ * cvmx_ciu_int#_en0_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN0 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en0_w1c_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en0_w1c_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en0_w1c_s       cn56xx;
+    struct cvmx_ciu_intx_en0_w1c_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en0_w1c_t;
+
+
+/**
+ * cvmx_ciu_int#_en0_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN0 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en0_w1s_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en0_w1s_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en0_w1s_s       cn56xx;
+    struct cvmx_ciu_intx_en0_w1s_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en0_w1s_t;
+
+
+/**
+ * cvmx_ciu_int#_en1
+ *
+ * Notes:
+ * @verbatim
+ * PPx/IP2 will be raised when...
+ * 
+ *    n = x*2
+ *    PPx/IP2 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ * 
+ * PPx/IP3 will be raised when...
+ * 
+ *    n = x*2 + 1
+ *    PPx/IP3 =  |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0])
+ * 
+ * PCI/INT will be raised when...
+ * 
+ *    PCI/INT = |([CIU_INT_SUM1, CIU_INT32_SUM0] & [CIU_INT32_EN1, CIU_INT32_EN0])
+ * @endverbatim
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en1_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t wdog                    : 1;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_intx_en1_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t wdog                    : 2;       /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_intx_en1_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_ciu_intx_en1_cn38xx      cn38xxp2;
+    struct cvmx_ciu_intx_en1_cn31xx      cn50xx;
+    struct cvmx_ciu_intx_en1_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en1_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn52xxp1;
+    struct cvmx_ciu_intx_en1_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en1_cn56xx      cn56xxp1;
+    struct cvmx_ciu_intx_en1_cn38xx      cn58xx;
+    struct cvmx_ciu_intx_en1_cn38xx      cn58xxp1;
+} cvmx_ciu_intx_en1_t;
+
+
+/**
+ * cvmx_ciu_int#_en1_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN1 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en1_w1c_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en1_w1c_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en1_w1c_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en1_w1c_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en1_w1c_t;
+
+
+/**
+ * cvmx_ciu_int#_en1_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN1 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en1_w1s_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en1_w1s_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en1_w1s_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en1_w1s_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en1_w1s_t;
+
+
+/**
+ * cvmx_ciu_int#_en4_0
+ *
+ * Notes:
+ * CIU_INT0_EN4_0:   PP0  /IP4
+ * CIU_INT1_EN4_0:   PP1  /IP4
+ * ...
+ * CIU_INT11_EN4_0:  PP11 /IP4
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en4_0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en4_0_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t reserved_47_47          : 1;
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t reserved_47_47          : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } cn50xx;
+    struct cvmx_ciu_intx_en4_0_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en4_0_cn52xx    cn52xxp1;
+    struct cvmx_ciu_intx_en4_0_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en4_0_cn56xx    cn56xxp1;
+    struct cvmx_ciu_intx_en4_0_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn58xx;
+    struct cvmx_ciu_intx_en4_0_cn58xx    cn58xxp1;
+} cvmx_ciu_intx_en4_0_t;
+
+
+/**
+ * cvmx_ciu_int#_en4_0_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN4_0 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en4_0_w1c_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en4_0_w1c_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en4_0_w1c_s     cn56xx;
+    struct cvmx_ciu_intx_en4_0_w1c_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en4_0_w1c_t;
+
+
+/**
+ * cvmx_ciu_int#_en4_0_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN4_0 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en4_0_w1s_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en4_0_w1s_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en4_0_w1s_s     cn56xx;
+    struct cvmx_ciu_intx_en4_0_w1s_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t reserved_44_44          : 1;
+        uint64_t pci_msi                 : 4;       /**< PCI MSI */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox/PCI interrupts */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t reserved_44_44          : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en4_0_w1s_t;
+
+
+/**
+ * cvmx_ciu_int#_en4_1
+ *
+ * Notes:
+ * PPx/IP4 will be raised when...
+ * PPx/IP4 = |([CIU_INT_SUM1, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en4_1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en4_1_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t wdog                    : 2;       /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn50xx;
+    struct cvmx_ciu_intx_en4_1_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en4_1_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn52xxp1;
+    struct cvmx_ciu_intx_en4_1_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en4_1_cn56xx    cn56xxp1;
+    struct cvmx_ciu_intx_en4_1_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn58xx;
+    struct cvmx_ciu_intx_en4_1_cn58xx    cn58xxp1;
+} cvmx_ciu_intx_en4_1_t;
+
+
+/**
+ * cvmx_ciu_int#_en4_1_w1c
+ *
+ * Notes:
+ * Write-1-to-clear version of the CIU_INTx_EN4_1 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en4_1_w1c_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en4_1_w1c_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en4_1_w1c_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en4_1_w1c_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en4_1_w1c_t;
+
+
+/**
+ * cvmx_ciu_int#_en4_1_w1s
+ *
+ * Notes:
+ * Write-1-to-set version of the CIU_INTx_EN4_1 register
+ * (Pass2 ONLY)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_en4_1_w1s_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_intx_en4_1_w1s_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< Watchdog summary interrupt enable vector */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_en4_1_w1s_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_en4_1_w1s_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< Watchdog summary interrupt enable vectory */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn58xx;
+} cvmx_ciu_intx_en4_1_w1s_t;
+
+
+/**
+ * cvmx_ciu_int#_sum0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_sum0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-31.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_sum0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t reserved_47_47          : 1;
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-1.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t reserved_47_47          : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_intx_sum0_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-3.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_intx_sum0_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-31.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn38xx;
+    struct cvmx_ciu_intx_sum0_cn38xx     cn38xxp2;
+    struct cvmx_ciu_intx_sum0_cn30xx     cn50xx;
+    struct cvmx_ciu_intx_sum0_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< SUM1&EN1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN is set, where x
+                                                         is the same as x in this CIU_INTx_SUM0.
+                                                         PPs use CIU_INTx_SUM0 where x=0-7.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3
+                                                         Note that WDOG_SUM only summarizes the SUM/EN1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-7
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_sum0_cn52xx     cn52xxp1;
+    struct cvmx_ciu_intx_sum0_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM0 where x=0-23.
+                                                         PCI uses the CIU_INTx_SUM0 where x=32.
+                                                         Even INTx registers report WDOG to IP2
+                                                         Odd INTx registers report WDOG to IP3 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-23
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_sum0_cn56xx     cn56xxp1;
+    struct cvmx_ciu_intx_sum0_cn38xx     cn58xx;
+    struct cvmx_ciu_intx_sum0_cn38xx     cn58xxp1;
+} cvmx_ciu_intx_sum0_t;
+
+
+/**
+ * cvmx_ciu_int#_sum4
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_intx_sum4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         These registers report WDOG to IP4 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_intx_sum4_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t mpi                     : 1;       /**< MPI/SPI interrupt */
+        uint64_t pcm                     : 1;       /**< PCM/TDM interrupt */
+        uint64_t usb                     : 1;       /**< USB interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t reserved_47_47          : 1;
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         PPs use CIU_INTx_SUM4 where x=0-1. */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t reserved_47_47          : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t pcm                     : 1;
+        uint64_t mpi                     : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } cn50xx;
+    struct cvmx_ciu_intx_sum4_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t reserved_51_51          : 1;
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t reserved_49_49          : 1;
+        uint64_t gmx_drp                 : 1;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< SUM1&EN4_1 summary bit
+                                                         This read-only bit reads as a one whenever any
+                                                         CIU_INT_SUM1 bit is set and corresponding
+                                                         enable bit in CIU_INTx_EN4_1 is set, where x
+                                                         is the same as x in this CIU_INTx_SUM4.
+                                                         PPs use CIU_INTx_SUM4 for IP4, where x=PPid.
+                                                         Note that WDOG_SUM only summarizes the SUM/EN4_1
+                                                         result and does not have a corresponding enable
+                                                         bit, so does not directly contribute to
+                                                         interrupts. */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-3
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 1;
+        uint64_t reserved_49_49          : 1;
+        uint64_t ipd_drp                 : 1;
+        uint64_t reserved_51_51          : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_intx_sum4_cn52xx     cn52xxp1;
+    struct cvmx_ciu_intx_sum4_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bootdma                 : 1;       /**< Boot bus DMA engines Interrupt */
+        uint64_t mii                     : 1;       /**< MII Interface Interrupt */
+        uint64_t ipdppthr                : 1;       /**< IPD per-port counter threshold interrupt */
+        uint64_t powiq                   : 1;       /**< POW IQ interrupt */
+        uint64_t twsi2                   : 1;       /**< 2nd TWSI Interrupt */
+        uint64_t reserved_57_58          : 2;
+        uint64_t usb                     : 1;       /**< USB Interrupt */
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         These registers report WDOG to IP4 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         Refer to "Receiving Message-Signalled
+                                                         Interrupts" in the PCIe chapter of the spec */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D
+                                                         Refer to "Receiving Emulated INTA/INTB/
+                                                         INTC/INTD" in the PCIe chapter of the spec */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-11
+                                                         [33] is the or of <31:16>
+                                                         [32] is the or of <15:0> */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t usb                     : 1;
+        uint64_t reserved_57_58          : 2;
+        uint64_t twsi2                   : 1;
+        uint64_t powiq                   : 1;
+        uint64_t ipdppthr                : 1;
+        uint64_t mii                     : 1;
+        uint64_t bootdma                 : 1;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_intx_sum4_cn56xx     cn56xxp1;
+    struct cvmx_ciu_intx_sum4_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t timer                   : 4;       /**< General timer interrupts */
+        uint64_t key_zero                : 1;       /**< Key Zeroization interrupt
+                                                         KEY_ZERO will be set when the external ZERO_KEYS
+                                                         pin is sampled high.  KEY_ZERO is cleared by SW */
+        uint64_t ipd_drp                 : 1;       /**< IPD QOS packet drop */
+        uint64_t gmx_drp                 : 2;       /**< GMX packet drop */
+        uint64_t trace                   : 1;       /**< L2C has the CMB trace buffer */
+        uint64_t rml                     : 1;       /**< RML Interrupt */
+        uint64_t twsi                    : 1;       /**< TWSI Interrupt */
+        uint64_t wdog_sum                : 1;       /**< Watchdog summary
+                                                         These registers report WDOG to IP4 */
+        uint64_t pci_msi                 : 4;       /**< PCI MSI
+                                                         [43] is the or of <63:48>
+                                                         [42] is the or of <47:32>
+                                                         [41] is the or of <31:16>
+                                                         [40] is the or of <15:0> */
+        uint64_t pci_int                 : 4;       /**< PCI INTA/B/C/D */
+        uint64_t uart                    : 2;       /**< Two UART interrupts */
+        uint64_t mbox                    : 2;       /**< Two mailbox interrupts for entries 0-31
+                                                          [33] is the or of <31:16>
+                                                          [32] is the or of <15:0>
+                                                         Two PCI internal interrupts for entry 32
+                                                          CIU_PCI_INTA */
+        uint64_t gpio                    : 16;      /**< 16 GPIO interrupts */
+        uint64_t workq                   : 16;      /**< 16 work queue interrupts
+                                                         1 bit/group. A copy of the R/W1C bit in the POW. */
+#else
+        uint64_t workq                   : 16;
+        uint64_t gpio                    : 16;
+        uint64_t mbox                    : 2;
+        uint64_t uart                    : 2;
+        uint64_t pci_int                 : 4;
+        uint64_t pci_msi                 : 4;
+        uint64_t wdog_sum                : 1;
+        uint64_t twsi                    : 1;
+        uint64_t rml                     : 1;
+        uint64_t trace                   : 1;
+        uint64_t gmx_drp                 : 2;
+        uint64_t ipd_drp                 : 1;
+        uint64_t key_zero                : 1;
+        uint64_t timer                   : 4;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn58xx;
+    struct cvmx_ciu_intx_sum4_cn58xx     cn58xxp1;
+} cvmx_ciu_intx_sum4_t;
+
+
+/**
+ * cvmx_ciu_int_sum1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_int_sum1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t wdog                    : 16;      /**< 16 watchdog interrupts */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_ciu_int_sum1_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t wdog                    : 1;       /**< 1 watchdog interrupt */
+#else
+        uint64_t wdog                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_int_sum1_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t wdog                    : 2;       /**< 2 watchdog interrupts */
+#else
+        uint64_t wdog                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_int_sum1_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t wdog                    : 16;      /**< 16 watchdog interrupts */
+#else
+        uint64_t wdog                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_ciu_int_sum1_cn38xx      cn38xxp2;
+    struct cvmx_ciu_int_sum1_cn31xx      cn50xx;
+    struct cvmx_ciu_int_sum1_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t nand                    : 1;       /**< NAND Flash Controller */
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< 4 watchdog interrupts */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t nand                    : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_int_sum1_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t mii1                    : 1;       /**< Second MII Interrupt */
+        uint64_t usb1                    : 1;       /**< Second USB Interrupt */
+        uint64_t uart2                   : 1;       /**< Third UART interrupt */
+        uint64_t reserved_4_15           : 12;
+        uint64_t wdog                    : 4;       /**< 4 watchdog interrupts */
+#else
+        uint64_t wdog                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t uart2                   : 1;
+        uint64_t usb1                    : 1;
+        uint64_t mii1                    : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn52xxp1;
+    struct cvmx_ciu_int_sum1_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t wdog                    : 12;      /**< 12 watchdog interrupts */
+#else
+        uint64_t wdog                    : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_int_sum1_cn56xx      cn56xxp1;
+    struct cvmx_ciu_int_sum1_cn38xx      cn58xx;
+    struct cvmx_ciu_int_sum1_cn38xx      cn58xxp1;
+} cvmx_ciu_int_sum1_t;
+
+
+/**
+ * cvmx_ciu_mbox_clr#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_mbox_clrx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bits                    : 32;      /**< On writes, clr corresponding bit in MBOX register
+                                                         on reads, return the MBOX register */
+#else
+        uint64_t bits                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_ciu_mbox_clrx_s          cn30xx;
+    struct cvmx_ciu_mbox_clrx_s          cn31xx;
+    struct cvmx_ciu_mbox_clrx_s          cn38xx;
+    struct cvmx_ciu_mbox_clrx_s          cn38xxp2;
+    struct cvmx_ciu_mbox_clrx_s          cn50xx;
+    struct cvmx_ciu_mbox_clrx_s          cn52xx;
+    struct cvmx_ciu_mbox_clrx_s          cn52xxp1;
+    struct cvmx_ciu_mbox_clrx_s          cn56xx;
+    struct cvmx_ciu_mbox_clrx_s          cn56xxp1;
+    struct cvmx_ciu_mbox_clrx_s          cn58xx;
+    struct cvmx_ciu_mbox_clrx_s          cn58xxp1;
+} cvmx_ciu_mbox_clrx_t;
+
+
+/**
+ * cvmx_ciu_mbox_set#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_mbox_setx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bits                    : 32;      /**< On writes, set corresponding bit in MBOX register
+                                                         on reads, return the MBOX register */
+#else
+        uint64_t bits                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_ciu_mbox_setx_s          cn30xx;
+    struct cvmx_ciu_mbox_setx_s          cn31xx;
+    struct cvmx_ciu_mbox_setx_s          cn38xx;
+    struct cvmx_ciu_mbox_setx_s          cn38xxp2;
+    struct cvmx_ciu_mbox_setx_s          cn50xx;
+    struct cvmx_ciu_mbox_setx_s          cn52xx;
+    struct cvmx_ciu_mbox_setx_s          cn52xxp1;
+    struct cvmx_ciu_mbox_setx_s          cn56xx;
+    struct cvmx_ciu_mbox_setx_s          cn56xxp1;
+    struct cvmx_ciu_mbox_setx_s          cn58xx;
+    struct cvmx_ciu_mbox_setx_s          cn58xxp1;
+} cvmx_ciu_mbox_setx_t;
+
+
+/**
+ * cvmx_ciu_nmi
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_nmi_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t nmi                     : 16;      /**< Send NMI pulse to PP vector */
+#else
+        uint64_t nmi                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_ciu_nmi_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t nmi                     : 1;       /**< Send NMI pulse to PP vector */
+#else
+        uint64_t nmi                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_nmi_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t nmi                     : 2;       /**< Send NMI pulse to PP vector */
+#else
+        uint64_t nmi                     : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_nmi_s                cn38xx;
+    struct cvmx_ciu_nmi_s                cn38xxp2;
+    struct cvmx_ciu_nmi_cn31xx           cn50xx;
+    struct cvmx_ciu_nmi_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t nmi                     : 4;       /**< Send NMI pulse to PP vector */
+#else
+        uint64_t nmi                     : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_nmi_cn52xx           cn52xxp1;
+    struct cvmx_ciu_nmi_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t nmi                     : 12;      /**< Send NMI pulse to PP vector */
+#else
+        uint64_t nmi                     : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_nmi_cn56xx           cn56xxp1;
+    struct cvmx_ciu_nmi_s                cn58xx;
+    struct cvmx_ciu_nmi_s                cn58xxp1;
+} cvmx_ciu_nmi_t;
+
+
+/**
+ * cvmx_ciu_pci_inta
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_pci_inta_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t intr                    : 2;       /**< PCI interrupt
+                                                         These bits are observed in CIU_INT32_SUM0<33:32> */
+#else
+        uint64_t intr                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_ciu_pci_inta_s           cn30xx;
+    struct cvmx_ciu_pci_inta_s           cn31xx;
+    struct cvmx_ciu_pci_inta_s           cn38xx;
+    struct cvmx_ciu_pci_inta_s           cn38xxp2;
+    struct cvmx_ciu_pci_inta_s           cn50xx;
+    struct cvmx_ciu_pci_inta_s           cn52xx;
+    struct cvmx_ciu_pci_inta_s           cn52xxp1;
+    struct cvmx_ciu_pci_inta_s           cn56xx;
+    struct cvmx_ciu_pci_inta_s           cn56xxp1;
+    struct cvmx_ciu_pci_inta_s           cn58xx;
+    struct cvmx_ciu_pci_inta_s           cn58xxp1;
+} cvmx_ciu_pci_inta_t;
+
+
+/**
+ * cvmx_ciu_pp_dbg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_pp_dbg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ppdbg                   : 16;      /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+        uint64_t ppdbg                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_ciu_pp_dbg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t ppdbg                   : 1;       /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+        uint64_t ppdbg                   : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_pp_dbg_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t ppdbg                   : 2;       /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+        uint64_t ppdbg                   : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_pp_dbg_s             cn38xx;
+    struct cvmx_ciu_pp_dbg_s             cn38xxp2;
+    struct cvmx_ciu_pp_dbg_cn31xx        cn50xx;
+    struct cvmx_ciu_pp_dbg_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ppdbg                   : 4;       /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+        uint64_t ppdbg                   : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_pp_dbg_cn52xx        cn52xxp1;
+    struct cvmx_ciu_pp_dbg_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t ppdbg                   : 12;      /**< Debug[DM] value for each PP
+                                                         whether the PP's are in debug mode or not */
+#else
+        uint64_t ppdbg                   : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_pp_dbg_cn56xx        cn56xxp1;
+    struct cvmx_ciu_pp_dbg_s             cn58xx;
+    struct cvmx_ciu_pp_dbg_s             cn58xxp1;
+} cvmx_ciu_pp_dbg_t;
+
+
+/**
+ * cvmx_ciu_pp_poke#
+ *
+ * Notes:
+ * Any write to a CIU_PP_POKE register clears any pending interrupt generated
+ * by the associated watchdog, resets the CIU_WDOG[STATE] field, and set
+ * CIU_WDOG[CNT] to be (CIU_WDOG[LEN] << 8).
+ * 
+ * Reads to this register will return the associated CIU_WDOG register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_pp_pokex_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t poke                    : 64;      /**< Reserved */
+#else
+        uint64_t poke                    : 64;
+#endif
+    } s;
+    struct cvmx_ciu_pp_pokex_s           cn30xx;
+    struct cvmx_ciu_pp_pokex_s           cn31xx;
+    struct cvmx_ciu_pp_pokex_s           cn38xx;
+    struct cvmx_ciu_pp_pokex_s           cn38xxp2;
+    struct cvmx_ciu_pp_pokex_s           cn50xx;
+    struct cvmx_ciu_pp_pokex_s           cn52xx;
+    struct cvmx_ciu_pp_pokex_s           cn52xxp1;
+    struct cvmx_ciu_pp_pokex_s           cn56xx;
+    struct cvmx_ciu_pp_pokex_s           cn56xxp1;
+    struct cvmx_ciu_pp_pokex_s           cn58xx;
+    struct cvmx_ciu_pp_pokex_s           cn58xxp1;
+} cvmx_ciu_pp_pokex_t;
+
+
+/**
+ * cvmx_ciu_pp_rst
+ *
+ * Contains the reset control for each PP.  Value of '1' will hold a PP in reset, '0' will release.
+ * Resets to 0xffff when PCI boot is enabled, 0xfffe otherwise.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_pp_rst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t rst                     : 15;      /**< PP Rst for PP's 15-1 */
+        uint64_t rst0                    : 1;       /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+        uint64_t rst0                    : 1;
+        uint64_t rst                     : 15;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_ciu_pp_rst_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rst0                    : 1;       /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+        uint64_t rst0                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn30xx;
+    struct cvmx_ciu_pp_rst_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t rst                     : 1;       /**< PP Rst for PP1 */
+        uint64_t rst0                    : 1;       /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+        uint64_t rst0                    : 1;
+        uint64_t rst                     : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_ciu_pp_rst_s             cn38xx;
+    struct cvmx_ciu_pp_rst_s             cn38xxp2;
+    struct cvmx_ciu_pp_rst_cn31xx        cn50xx;
+    struct cvmx_ciu_pp_rst_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t rst                     : 3;       /**< PP Rst for PP's 11-1 */
+        uint64_t rst0                    : 1;       /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+        uint64_t rst0                    : 1;
+        uint64_t rst                     : 3;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_pp_rst_cn52xx        cn52xxp1;
+    struct cvmx_ciu_pp_rst_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t rst                     : 11;      /**< PP Rst for PP's 11-1 */
+        uint64_t rst0                    : 1;       /**< PP Rst for PP0
+                                                         depends on standalone mode */
+#else
+        uint64_t rst0                    : 1;
+        uint64_t rst                     : 11;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xx;
+    struct cvmx_ciu_pp_rst_cn56xx        cn56xxp1;
+    struct cvmx_ciu_pp_rst_s             cn58xx;
+    struct cvmx_ciu_pp_rst_s             cn58xxp1;
+} cvmx_ciu_pp_rst_t;
+
+
+/**
+ * cvmx_ciu_qlm_dcok
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_qlm_dcok_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t qlm_dcok                : 4;       /**< Re-assert dcok for each QLM. The value in this
+                                                         field is "anded" with the pll_dcok pin and then
+                                                         sent to each QLM (0..3). */
+#else
+        uint64_t qlm_dcok                : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_ciu_qlm_dcok_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t qlm_dcok                : 2;       /**< Re-assert dcok for each QLM. The value in this
+                                                         field is "anded" with the pll_dcok pin and then
+                                                         sent to each QLM (0..3). */
+#else
+        uint64_t qlm_dcok                : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_qlm_dcok_cn52xx      cn52xxp1;
+    struct cvmx_ciu_qlm_dcok_s           cn56xx;
+    struct cvmx_ciu_qlm_dcok_s           cn56xxp1;
+} cvmx_ciu_qlm_dcok_t;
+
+
+/**
+ * cvmx_ciu_qlm_jtgc
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_qlm_jtgc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t clk_div                 : 3;       /**< Clock divider for QLM JTAG operations.  eclk is
+                                                         divided by 2^(CLK_DIV + 2) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t mux_sel                 : 2;       /**< Selects which QLM JTAG shift out is shifted into
+                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
+        uint64_t bypass                  : 4;       /**< Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+#else
+        uint64_t bypass                  : 4;
+        uint64_t mux_sel                 : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t clk_div                 : 3;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_ciu_qlm_jtgc_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t clk_div                 : 3;       /**< Clock divider for QLM JTAG operations.  eclk is
+                                                         divided by 2^(CLK_DIV + 2) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t mux_sel                 : 1;       /**< Selects which QLM JTAG shift out is shifted into
+                                                         the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
+        uint64_t reserved_2_3            : 2;
+        uint64_t bypass                  : 2;       /**< Selects which QLM JTAG shift chains are bypassed
+                                                         by the QLM JTAG data register (CIU_QLM_JTGD) (one
+                                                         bit per QLM) */
+#else
+        uint64_t bypass                  : 2;
+        uint64_t reserved_2_3            : 2;
+        uint64_t mux_sel                 : 1;
+        uint64_t reserved_5_7            : 3;
+        uint64_t clk_div                 : 3;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_qlm_jtgc_cn52xx      cn52xxp1;
+    struct cvmx_ciu_qlm_jtgc_s           cn56xx;
+    struct cvmx_ciu_qlm_jtgc_s           cn56xxp1;
+} cvmx_ciu_qlm_jtgc_t;
+
+
+/**
+ * cvmx_ciu_qlm_jtgd
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_qlm_jtgd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t capture                 : 1;       /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+        uint64_t shift                   : 1;       /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+        uint64_t update                  : 1;       /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+        uint64_t reserved_44_60          : 17;
+        uint64_t select                  : 4;       /**< Selects which QLM JTAG shift chains the JTAG
+                                                         operations are performed on */
+        uint64_t reserved_37_39          : 3;
+        uint64_t shft_cnt                : 5;       /**< QLM JTAG shift count (encoded in -1 notation) */
+        uint64_t shft_reg                : 32;      /**< QLM JTAG shift register */
+#else
+        uint64_t shft_reg                : 32;
+        uint64_t shft_cnt                : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t select                  : 4;
+        uint64_t reserved_44_60          : 17;
+        uint64_t update                  : 1;
+        uint64_t shift                   : 1;
+        uint64_t capture                 : 1;
+#endif
+    } s;
+    struct cvmx_ciu_qlm_jtgd_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t capture                 : 1;       /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+        uint64_t shift                   : 1;       /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+        uint64_t update                  : 1;       /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+        uint64_t reserved_42_60          : 19;
+        uint64_t select                  : 2;       /**< Selects which QLM JTAG shift chains the JTAG
+                                                         operations are performed on */
+        uint64_t reserved_37_39          : 3;
+        uint64_t shft_cnt                : 5;       /**< QLM JTAG shift count (encoded in -1 notation) */
+        uint64_t shft_reg                : 32;      /**< QLM JTAG shift register */
+#else
+        uint64_t shft_reg                : 32;
+        uint64_t shft_cnt                : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t select                  : 2;
+        uint64_t reserved_42_60          : 19;
+        uint64_t update                  : 1;
+        uint64_t shift                   : 1;
+        uint64_t capture                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_qlm_jtgd_cn52xx      cn52xxp1;
+    struct cvmx_ciu_qlm_jtgd_s           cn56xx;
+    struct cvmx_ciu_qlm_jtgd_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t capture                 : 1;       /**< Perform JTAG capture operation (self-clearing when
+                                                         op completes) */
+        uint64_t shift                   : 1;       /**< Perform JTAG shift operation (self-clearing when
+                                                         op completes) */
+        uint64_t update                  : 1;       /**< Perform JTAG update operation (self-clearing when
+                                                         op completes) */
+        uint64_t reserved_37_60          : 24;
+        uint64_t shft_cnt                : 5;       /**< QLM JTAG shift count (encoded in -1 notation) */
+        uint64_t shft_reg                : 32;      /**< QLM JTAG shift register */
+#else
+        uint64_t shft_reg                : 32;
+        uint64_t shft_cnt                : 5;
+        uint64_t reserved_37_60          : 24;
+        uint64_t update                  : 1;
+        uint64_t shift                   : 1;
+        uint64_t capture                 : 1;
+#endif
+    } cn56xxp1;
+} cvmx_ciu_qlm_jtgd_t;
+
+
+/**
+ * cvmx_ciu_soft_bist
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_soft_bist_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t soft_bist               : 1;       /**< Run BIST on soft reset. */
+#else
+        uint64_t soft_bist               : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_ciu_soft_bist_s          cn30xx;
+    struct cvmx_ciu_soft_bist_s          cn31xx;
+    struct cvmx_ciu_soft_bist_s          cn38xx;
+    struct cvmx_ciu_soft_bist_s          cn38xxp2;
+    struct cvmx_ciu_soft_bist_s          cn50xx;
+    struct cvmx_ciu_soft_bist_s          cn52xx;
+    struct cvmx_ciu_soft_bist_s          cn52xxp1;
+    struct cvmx_ciu_soft_bist_s          cn56xx;
+    struct cvmx_ciu_soft_bist_s          cn56xxp1;
+    struct cvmx_ciu_soft_bist_s          cn58xx;
+    struct cvmx_ciu_soft_bist_s          cn58xxp1;
+} cvmx_ciu_soft_bist_t;
+
+
+/**
+ * cvmx_ciu_soft_prst
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_soft_prst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t host64                  : 1;       /**< PCX Host Mode Device Capability (0=32b/1=64b) */
+        uint64_t npi                     : 1;       /**< When PCI soft reset is asserted, also reset the
+                                                         NPI and PNI logic */
+        uint64_t soft_prst               : 1;       /**< Reset the PCI bus.  Only works when Octane is
+                                                         configured as a HOST. When OCTEON is a PCI host
+                                                         (i.e. when PCI_HOST_MODE = 1), This controls
+                                                         PCI_RST_L. Refer to section 10.11.1. */
+#else
+        uint64_t soft_prst               : 1;
+        uint64_t npi                     : 1;
+        uint64_t host64                  : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_ciu_soft_prst_s          cn30xx;
+    struct cvmx_ciu_soft_prst_s          cn31xx;
+    struct cvmx_ciu_soft_prst_s          cn38xx;
+    struct cvmx_ciu_soft_prst_s          cn38xxp2;
+    struct cvmx_ciu_soft_prst_s          cn50xx;
+    struct cvmx_ciu_soft_prst_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t soft_prst               : 1;       /**< Reset the PCI bus.  Only works when Octane is
+                                                         configured as a HOST. When OCTEON is a PCI host
+                                                         (i.e. when PCI_HOST_MODE = 1), This controls
+                                                         PCI_RST_L. Refer to section 10.11.1. */
+#else
+        uint64_t soft_prst               : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn52xx;
+    struct cvmx_ciu_soft_prst_cn52xx     cn52xxp1;
+    struct cvmx_ciu_soft_prst_cn52xx     cn56xx;
+    struct cvmx_ciu_soft_prst_cn52xx     cn56xxp1;
+    struct cvmx_ciu_soft_prst_s          cn58xx;
+    struct cvmx_ciu_soft_prst_s          cn58xxp1;
+} cvmx_ciu_soft_prst_t;
+
+
+/**
+ * cvmx_ciu_soft_prst1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_soft_prst1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t soft_prst               : 1;       /**< Reset the PCI bus.  Only works when Octane is
+                                                         configured as a HOST. When OCTEON is a PCI host
+                                                         (i.e. when PCI_HOST_MODE = 1), This controls
+                                                         PCI_RST_L. Refer to section 10.11.1. */
+#else
+        uint64_t soft_prst               : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_ciu_soft_prst1_s         cn52xx;
+    struct cvmx_ciu_soft_prst1_s         cn52xxp1;
+    struct cvmx_ciu_soft_prst1_s         cn56xx;
+    struct cvmx_ciu_soft_prst1_s         cn56xxp1;
+} cvmx_ciu_soft_prst1_t;
+
+
+/**
+ * cvmx_ciu_soft_rst
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_soft_rst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t soft_rst                : 1;       /**< Resets Octeon
+                                                         When soft reseting Octeon from a remote PCI host,
+                                                         always read CIU_SOFT_RST (and wait for result)
+                                                         before writing SOFT_RST to '1'. */
+#else
+        uint64_t soft_rst                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_ciu_soft_rst_s           cn30xx;
+    struct cvmx_ciu_soft_rst_s           cn31xx;
+    struct cvmx_ciu_soft_rst_s           cn38xx;
+    struct cvmx_ciu_soft_rst_s           cn38xxp2;
+    struct cvmx_ciu_soft_rst_s           cn50xx;
+    struct cvmx_ciu_soft_rst_s           cn52xx;
+    struct cvmx_ciu_soft_rst_s           cn52xxp1;
+    struct cvmx_ciu_soft_rst_s           cn56xx;
+    struct cvmx_ciu_soft_rst_s           cn56xxp1;
+    struct cvmx_ciu_soft_rst_s           cn58xx;
+    struct cvmx_ciu_soft_rst_s           cn58xxp1;
+} cvmx_ciu_soft_rst_t;
+
+
+/**
+ * cvmx_ciu_tim#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_timx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t one_shot                : 1;       /**< One-shot mode */
+        uint64_t len                     : 36;      /**< Timeout length in core clock cycles
+                                                         Periodic interrupts will occur every LEN+1 core
+                                                         clock cycles when ONE_SHOT==0
+                                                         Timer disabled when LEN==0 */
+#else
+        uint64_t len                     : 36;
+        uint64_t one_shot                : 1;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } s;
+    struct cvmx_ciu_timx_s               cn30xx;
+    struct cvmx_ciu_timx_s               cn31xx;
+    struct cvmx_ciu_timx_s               cn38xx;
+    struct cvmx_ciu_timx_s               cn38xxp2;
+    struct cvmx_ciu_timx_s               cn50xx;
+    struct cvmx_ciu_timx_s               cn52xx;
+    struct cvmx_ciu_timx_s               cn52xxp1;
+    struct cvmx_ciu_timx_s               cn56xx;
+    struct cvmx_ciu_timx_s               cn56xxp1;
+    struct cvmx_ciu_timx_s               cn58xx;
+    struct cvmx_ciu_timx_s               cn58xxp1;
+} cvmx_ciu_timx_t;
+
+
+/**
+ * cvmx_ciu_wdog#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ciu_wdogx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_46_63          : 18;
+        uint64_t gstopen                 : 1;       /**< GSTOPEN */
+        uint64_t dstop                   : 1;       /**< DSTOP */
+        uint64_t cnt                     : 24;      /**< Number of 256-cycle intervals until next watchdog
+                                                         expiration.  Cleared on write to associated
+                                                         CIU_PP_POKE register. */
+        uint64_t len                     : 16;      /**< Watchdog time expiration length
+                                                         The 16 bits of LEN represent the most significant
+                                                         bits of a 24 bit decrementer that decrements
+                                                         every 256 cycles.
+                                                         LEN must be set > 0 */
+        uint64_t state                   : 2;       /**< Watchdog state
+                                                         number of watchdog time expirations since last
+                                                         PP poke.  Cleared on write to associated
+                                                         CIU_PP_POKE register. */
+        uint64_t mode                    : 2;       /**< Watchdog mode
+                                                         0 = Off
+                                                         1 = Interrupt Only
+                                                         2 = Interrupt + NMI
+                                                         3 = Interrupt + NMI + Soft-Reset */
+#else
+        uint64_t mode                    : 2;
+        uint64_t state                   : 2;
+        uint64_t len                     : 16;
+        uint64_t cnt                     : 24;
+        uint64_t dstop                   : 1;
+        uint64_t gstopen                 : 1;
+        uint64_t reserved_46_63          : 18;
+#endif
+    } s;
+    struct cvmx_ciu_wdogx_s              cn30xx;
+    struct cvmx_ciu_wdogx_s              cn31xx;
+    struct cvmx_ciu_wdogx_s              cn38xx;
+    struct cvmx_ciu_wdogx_s              cn38xxp2;
+    struct cvmx_ciu_wdogx_s              cn50xx;
+    struct cvmx_ciu_wdogx_s              cn52xx;
+    struct cvmx_ciu_wdogx_s              cn52xxp1;
+    struct cvmx_ciu_wdogx_s              cn56xx;
+    struct cvmx_ciu_wdogx_s              cn56xxp1;
+    struct cvmx_ciu_wdogx_s              cn58xx;
+    struct cvmx_ciu_wdogx_s              cn58xxp1;
+} cvmx_ciu_wdogx_t;
+
+
+/**
+ * cvmx_dbg_data
+ *
+ * DBG_DATA = Debug Data Register
+ * 
+ * Value returned on the debug-data lines from the RSLs
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dbg_data_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t c_mul                   : 5;       /**< C_MUL pins sampled at DCOK assertion */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_dbg_data_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t pll_mul                 : 3;       /**< pll_mul pins sampled at DCOK assertion */
+        uint64_t reserved_23_27          : 5;
+        uint64_t c_mul                   : 5;       /**< Core PLL multiplier sampled at DCOK assertion */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t reserved_23_27          : 5;
+        uint64_t pll_mul                 : 3;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } cn30xx;
+    struct cvmx_dbg_data_cn30xx          cn31xx;
+    struct cvmx_dbg_data_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t d_mul                   : 4;       /**< D_MUL pins sampled on DCOK assertion */
+        uint64_t dclk_mul2               : 1;       /**< Should always be set for fast DDR-II operation */
+        uint64_t cclk_div2               : 1;       /**< Should always be clear for fast core clock */
+        uint64_t c_mul                   : 5;       /**< C_MUL pins sampled at DCOK assertion */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t cclk_div2               : 1;
+        uint64_t dclk_mul2               : 1;
+        uint64_t d_mul                   : 4;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn38xx;
+    struct cvmx_dbg_data_cn38xx          cn38xxp2;
+    struct cvmx_dbg_data_cn30xx          cn50xx;
+    struct cvmx_dbg_data_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t rem                     : 6;       /**< Remaining debug_select pins sampled at DCOK */
+        uint64_t c_mul                   : 5;       /**< C_MUL pins sampled at DCOK assertion */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t rem                     : 6;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn58xx;
+    struct cvmx_dbg_data_cn58xx          cn58xxp1;
+} cvmx_dbg_data_t;
+
+
+/**
+ * cvmx_dfa_bst0
+ *
+ * DFA_BST0 = DFA Bist Status
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_bst0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rdf                     : 16;      /**< Bist Results for RDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t pdf                     : 16;      /**< Bist Results for PDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t pdf                     : 16;
+        uint64_t rdf                     : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_dfa_bst0_s               cn31xx;
+    struct cvmx_dfa_bst0_s               cn38xx;
+    struct cvmx_dfa_bst0_s               cn38xxp2;
+    struct cvmx_dfa_bst0_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t rdf                     : 4;       /**< Bist Results for RDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_4_15           : 12;
+        uint64_t pdf                     : 4;       /**< Bist Results for PDF[3:0] RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t pdf                     : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t rdf                     : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn58xx;
+    struct cvmx_dfa_bst0_cn58xx          cn58xxp1;
+} cvmx_dfa_bst0_t;
+
+
+/**
+ * cvmx_dfa_bst1
+ *
+ * DFA_BST1 = DFA Bist Status
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_bst1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t crq                     : 1;       /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ifu                     : 1;       /**< Bist Results for IFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t gfu                     : 1;       /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t drf                     : 1;       /**< Bist Results for DRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t crf                     : 1;       /**< Bist Results for CRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p0_bwb                  : 1;       /**< Bist Results for P0_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p1_bwb                  : 1;       /**< Bist Results for P1_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p0_brf                  : 8;       /**< Bist Results for P0_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p1_brf                  : 8;       /**< Bist Results for P1_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t p1_brf                  : 8;
+        uint64_t p0_brf                  : 8;
+        uint64_t p1_bwb                  : 1;
+        uint64_t p0_bwb                  : 1;
+        uint64_t crf                     : 1;
+        uint64_t drf                     : 1;
+        uint64_t gfu                     : 1;
+        uint64_t ifu                     : 1;
+        uint64_t crq                     : 1;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_dfa_bst1_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t crq                     : 1;       /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ifu                     : 1;       /**< Bist Results for IFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t gfu                     : 1;       /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t drf                     : 1;       /**< Bist Results for DRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t crf                     : 1;       /**< Bist Results for CRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_0_17           : 18;
+#else
+        uint64_t reserved_0_17           : 18;
+        uint64_t crf                     : 1;
+        uint64_t drf                     : 1;
+        uint64_t gfu                     : 1;
+        uint64_t ifu                     : 1;
+        uint64_t crq                     : 1;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } cn31xx;
+    struct cvmx_dfa_bst1_s               cn38xx;
+    struct cvmx_dfa_bst1_s               cn38xxp2;
+    struct cvmx_dfa_bst1_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t crq                     : 1;       /**< Bist Results for CRQ RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ifu                     : 1;       /**< Bist Results for IFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t gfu                     : 1;       /**< Bist Results for GFU RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_19_19          : 1;
+        uint64_t crf                     : 1;       /**< Bist Results for CRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p0_bwb                  : 1;       /**< Bist Results for P0_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p1_bwb                  : 1;       /**< Bist Results for P1_BWB RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p0_brf                  : 8;       /**< Bist Results for P0_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t p1_brf                  : 8;       /**< Bist Results for P1_BRF RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t p1_brf                  : 8;
+        uint64_t p0_brf                  : 8;
+        uint64_t p1_bwb                  : 1;
+        uint64_t p0_bwb                  : 1;
+        uint64_t crf                     : 1;
+        uint64_t reserved_19_19          : 1;
+        uint64_t gfu                     : 1;
+        uint64_t ifu                     : 1;
+        uint64_t crq                     : 1;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } cn58xx;
+    struct cvmx_dfa_bst1_cn58xx          cn58xxp1;
+} cvmx_dfa_bst1_t;
+
+
+/**
+ * cvmx_dfa_cfg
+ *
+ * Specify the RSL base addresses for the block
+ * 
+ *                  DFA_CFG = DFA Configuration
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t nrpl_ena                : 1;       /**< When set, allows the per-node replication feature to be
+                                                         enabled.
+                                                         In 36-bit mode: The IWORD0[31:30]=SNREPL field AND
+                                                         bits [21:20] of the Next Node ptr are used in generating
+                                                         the next node address (see OCTEON HRM - DFA Chapter for
+                                                         psuedo-code of DTE next node address generation).
+                                                         NOTE: When NRPL_ENA=1 and IWORD0[TY]=1(36b mode),
+                                                         (regardless of IWORD0[NRPLEN]), the Resultant Word1+
+                                                         [[47:44],[23:20]] = Next Node's [27:20] bits. This allows
+                                                         SW to use the RESERVED bits of the final node for SW
+                                                         caching. Also, if required, SW will use [22:21]=Node
+                                                         Replication to re-start the same graph walk(if graph
+                                                         walk prematurely terminated (ie: DATA_GONE).
+                                                         In 18-bit mode: The IWORD0[31:30]=SNREPL field AND
+                                                         bit [16:14] of the Next Node ptr are used in generating
+                                                         the next node address (see OCTEON HRM - DFA Chapter for
+                                                         psuedo-code of DTE next node address generation).
+                                                         If (IWORD0[NREPLEN]=1 and DFA_CFG[NRPL_ENA]=1) [
+                                                            If next node ptr[16] is set [
+                                                              next node ptr[15:14] indicates the next node repl
+                                                              next node ptr[13:0]  indicates the position of the
+                                                                 node relative to the first normal node (i.e.
+                                                                 IWORD3[Msize] must be added to get the final node)
+                                                            ]
+                                                            else If next node ptr[16] is not set [
+                                                              next node ptr[15:0] indicates the next node id
+                                                              next node repl = 0
+                                                            ]
+                                                         ]
+                                                         NOTE: For 18b node replication, MAX node space=64KB(2^16)
+                                                         is used in detecting terminal node space(see HRM for full
+                                                         description).
+                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
+                                                         aware of the "per-node" replication. */
+        uint64_t nxor_ena                : 1;       /**< When set, allows the DTE Instruction IWORD0[NXOREN]
+                                                         to be used to enable/disable the per-node address 'scramble'
+                                                         of the LLM address to lessen the effects of bank conflicts.
+                                                         If IWORD0[NXOREN] is also set, then:
+                                                         In 36-bit mode: The node_Id[7:0] 8-bit value is XORed
+                                                         against the LLM address addr[9:2].
+                                                         In 18-bit mode: The node_id[6:0] 7-bit value is XORed
+                                                         against the LLM address addr[8:2]. (note: we don't address
+                                                         scramble outside the mode's node space).
+                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
+                                                         aware of the "per-node" address scramble.
+                                                         NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
+                                                         read/write operations. */
+        uint64_t gxor_ena                : 1;       /**< When set, the DTE Instruction IWORD0[GXOR]
+                                                         field is used to 'scramble' the LLM address
+                                                         to lessen the effects of bank conflicts.
+                                                         In 36-bit mode: The GXOR[7:0] 8-bit value is XORed
+                                                         against the LLM address addr[9:2].
+                                                         In 18-bit mode: GXOR[6:0] 7-bit value is XORed against
+                                                         the LLM address addr[8:2]. (note: we don't address
+                                                         scramble outside the mode's node space)
+                                                         NOTE: The DFA graphs MUST BE built/written to DFA LLM memory
+                                                         aware of the "per-graph" address scramble.
+                                                         NOTE: The address 'scramble' ocurs for BOTH DFA LLM graph
+                                                         read/write operations. */
+        uint64_t sarb                    : 1;       /**< DFA Source Arbiter Mode
+                                                         Selects the arbitration mode used to select DFA
+                                                         requests issued from either CP2 or the DTE (NCB-CSR
+                                                         or DFA HW engine).
+                                                            - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
+                                                            - 1: Round-Robin
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+        uint64_t sarb                    : 1;
+        uint64_t gxor_ena                : 1;
+        uint64_t nxor_ena                : 1;
+        uint64_t nrpl_ena                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_dfa_cfg_s                cn38xx;
+    struct cvmx_dfa_cfg_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t sarb                    : 1;       /**< DFA Source Arbiter Mode
+                                                         Selects the arbitration mode used to select DFA
+                                                         requests issued from either CP2 or the DTE (NCB-CSR
+                                                         or DFA HW engine).
+                                                            - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
+                                                            - 1: Round-Robin
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+        uint64_t sarb                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn38xxp2;
+    struct cvmx_dfa_cfg_s                cn58xx;
+    struct cvmx_dfa_cfg_s                cn58xxp1;
+} cvmx_dfa_cfg_t;
+
+
+/**
+ * cvmx_dfa_dbell
+ *
+ * DFA_DBELL = DFA Doorbell Register
+ * 
+ * Description:
+ *  NOTE: To write to the DFA_DBELL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b00.
+ *        To read the DFA_DBELL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b00.
+ * 
+ *  NOTE: If DFA_CFG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DBELL register do not take effect.
+ *  NOTE: If FUSE[120]="DFA DTE disable" is blown, reads/writes to the DFA_DBELL register do not take effect.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_dbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t dbell                   : 20;      /**< Represents the cumulative total of pending
+                                                         DFA instructions which SW has previously written
+                                                         into the DFA Instruction FIFO (DIF) in main memory.
+                                                         Each DFA instruction contains a fixed size 32B
+                                                         instruction word which is executed by the DFA HW.
+                                                         The DBL register can hold up to 1M-1 (2^20-1)
+                                                         pending DFA instruction requests.
+                                                         During a read (by SW), the 'most recent' contents
+                                                         of the DFA_DBELL register are returned at the time
+                                                         the NCB-INB bus is driven.
+                                                         NOTE: Since DFA HW updates this register, its
+                                                         contents are unpredictable in SW. */
+#else
+        uint64_t dbell                   : 20;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_dfa_dbell_s              cn31xx;
+    struct cvmx_dfa_dbell_s              cn38xx;
+    struct cvmx_dfa_dbell_s              cn38xxp2;
+    struct cvmx_dfa_dbell_s              cn58xx;
+    struct cvmx_dfa_dbell_s              cn58xxp1;
+} cvmx_dfa_dbell_t;
+
+
+/**
+ * cvmx_dfa_ddr2_addr
+ *
+ * DFA_DDR2_ADDR = DFA DDR2  fclk-domain Memory Address Config Register
+ * 
+ * 
+ * Description: The following registers are used to compose the DFA's DDR2 address into ROW/COL/BNK
+ *              etc.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t rdimm_ena               : 1;       /**< If there is a need to insert a register chip on the
+                                                         system (the equivalent of a registered DIMM) to
+                                                         provide better setup for the command and control bits
+                                                         turn this mode on.
+                                                             RDIMM_ENA
+                                                                0           Registered Mode OFF
+                                                                1           Registered Mode ON */
+        uint64_t num_rnks                : 2;       /**< NUM_RNKS is programmed based on how many ranks there
+                                                         are in the system. This needs to be programmed correctly
+                                                         regardless of whether we are in RNK_LO mode or not.
+                                                            NUM_RNKS     \# of Ranks
+                                                              0              1
+                                                              1              2
+                                                              2              4
+                                                              3              RESERVED */
+        uint64_t rnk_lo                  : 1;       /**< When this mode is turned on, consecutive addresses
+                                                         outside the bank boundary
+                                                         are programmed to go to different ranks in order to
+                                                         minimize bank conflicts. It is useful in 4-bank DDR2
+                                                         parts based memory to extend out the \#physical banks
+                                                         available and minimize bank conflicts.
+                                                         On 8 bank ddr2 parts, this mode is not very useful
+                                                         because this mode does come with
+                                                         a penalty which is that every successive reads that
+                                                         cross rank boundary will need a 1 cycle bubble
+                                                         inserted to prevent bus turnaround conflicts.
+                                                            RNK_LO
+                                                             0      - OFF
+                                                             1      - ON */
+        uint64_t num_colrows             : 3;       /**< NUM_COLROWS    is used to set the MSB of the ROW_ADDR
+                                                         and the LSB of RANK address when not in RNK_LO mode.
+                                                         Calculate the sum of \#COL and \#ROW and program the
+                                                         controller appropriately
+                                                            RANK_LSB        \#COLs + \#ROWs
+                                                            ------------------------------
+                                                             - 000:                   22
+                                                             - 001:                   23
+                                                             - 010:                   24
+                                                             - 011:                   25
+                                                            - 100-111:             RESERVED */
+        uint64_t num_cols                : 2;       /**< The Long word address that the controller receives
+                                                         needs to be converted to Row, Col, Rank and Bank
+                                                         addresses depending on the memory part's micro arch.
+                                                         NUM_COL tells the controller how many colum bits
+                                                         there are and the controller uses this info to map
+                                                         the LSB of the row address
+                                                             - 00: num_cols = 9
+                                                             - 01: num_cols = 10
+                                                             - 10: num_cols = 11
+                                                             - 11: RESERVED */
+#else
+        uint64_t num_cols                : 2;
+        uint64_t num_colrows             : 3;
+        uint64_t rnk_lo                  : 1;
+        uint64_t num_rnks                : 2;
+        uint64_t rdimm_ena               : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_addr_s          cn31xx;
+} cvmx_dfa_ddr2_addr_t;
+
+
+/**
+ * cvmx_dfa_ddr2_bus
+ *
+ * DFA_DDR2_BUS = DFA DDR Bus Activity Counter
+ * 
+ * 
+ * Description: This counter counts \# cycles that the memory bus is doing a read/write/command
+ *              Useful to benchmark the bus utilization as a ratio of
+ *              \#Cycles of Data Transfer/\#Cycles since init or
+ *              \#Cycles of Data Transfer/\#Cycles that memory controller is active
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_bus_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_47_63          : 17;
+        uint64_t bus_cnt                 : 47;      /**< Counter counts the \# cycles of Data transfer */
+#else
+        uint64_t bus_cnt                 : 47;
+        uint64_t reserved_47_63          : 17;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_bus_s           cn31xx;
+} cvmx_dfa_ddr2_bus_t;
+
+
+/**
+ * cvmx_dfa_ddr2_cfg
+ *
+ * DFA_DDR2_CFG = DFA DDR2 fclk-domain Memory Configuration \#0 Register
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_41_63          : 23;
+        uint64_t trfc                    : 5;       /**< Establishes tRFC(from DDR2 data sheets) in \# of
+                                                         4 fclk intervals.
+                                                         General Equation:
+                                                         TRFC(csr) = ROUNDUP[tRFC(data-sheet-ns)/(4 * fclk(ns))]
+                                                         Example:
+                                                            tRFC(data-sheet-ns) = 127.5ns
+                                                            Operational Frequency: 533MHz DDR rate
+                                                                [fclk=266MHz(3.75ns)]
+                                                         Then:
+                                                            TRFC(csr) = ROUNDUP[127.5ns/(4 * 3.75ns)]
+                                                                      = 9 */
+        uint64_t mrs_pgm                 : 1;       /**< When clear, the HW initialization sequence fixes
+                                                         some of the *MRS register bit definitions.
+                                                            EMRS:
+                                                              A[14:13] = 0 RESERVED
+                                                              A[12] = 0    Output Buffers Enabled (FIXED)
+                                                              A[11] = 0    RDQS Disabled (FIXED)
+                                                              A[10] = 0    DQSn Enabled (FIXED)
+                                                              A[9:7] = 0   OCD Not supported (FIXED)
+                                                              A[6] = 0     RTT Disabled (FIXED)
+                                                              A[5:3]=DFA_DDR2_TMG[ADDLAT] (if DFA_DDR2_TMG[POCAS]=1)
+                                                                            Additive LATENCY (Programmable)
+                                                              A[2]=0       RTT Disabled (FIXED)
+                                                              A[1]=DFA_DDR2_TMG[DIC] (Programmable)
+                                                              A[0] = 0     DLL Enabled (FIXED)
+                                                            MRS:
+                                                              A[14:13] = 0 RESERVED
+                                                              A[12] = 0    Fast Active Power Down Mode (FIXED)
+                                                              A[11:9] = DFA_DDR2_TMG[TWR](Programmable)
+                                                              A[8] = 1     DLL Reset (FIXED)
+                                                              A[7] = 0     Test Mode (FIXED)
+                                                              A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (Programmable)
+                                                              A[3] = 0     Burst Type(must be 0:Sequential) (FIXED)
+                                                              A[2:0] = 2   Burst Length=4 (must be 0:Sequential) (FIXED)
+                                                         When set, the HW initialization sequence sources
+                                                         the DFA_DDR2_MRS, DFA_DDR2_EMRS registers which are
+                                                         driven onto the DFA_A[] pins. (this allows the MRS/EMRS
+                                                         fields to be completely programmable - however care
+                                                         must be taken by software).
+                                                         This mode is useful for customers who wish to:
+                                                            1) override the FIXED definitions(above), or
+                                                            2) Use a "clamshell mode" of operation where the
+                                                               address bits(per rank) are swizzled on the
+                                                               board to reduce stub lengths for optimal
+                                                               frequency operation.
+                                                         Use this in combination with DFA_DDR2_CFG[RNK_MSK]
+                                                         to specify the INIT sequence for each of the 4
+                                                         supported ranks. */
+        uint64_t fpip                    : 3;       /**< Early Fill Programmable Pipe [\#fclks]
+                                                         This field dictates the \#fclks prior to the arrival
+                                                         of fill data(in fclk domain), to start the 'early' fill
+                                                         command pipe (in the eclk domain) so as to minimize the
+                                                         overall fill latency.
+                                                         The programmable early fill command signal is synchronized
+                                                         into the eclk domain, where it is used to pull data out of
+                                                         asynchronous RAM as fast as possible.
+                                                         NOTE: A value of FPIP=0 is the 'safest' setting and will
+                                                         result in the early fill command pipe starting in the
+                                                         same cycle as the fill data.
+                                                         General Equation: (for FPIP)
+                                                             FPIP <= MIN[6, (ROUND_DOWN[6/EF_RATIO] + 1)]
+                                                         where:
+                                                           EF_RATIO = ECLK/FCLK Ratio [eclk(MHz)/fclk(MHz)]
+                                                         Example: FCLK=200MHz/ECLK=600MHz
+                                                            FPIP = MIN[6, (ROUND_DOWN[6/(600/200))] + 1)]
+                                                            FPIP <= 3 */
+        uint64_t reserved_29_31          : 3;
+        uint64_t ref_int                 : 13;      /**< Refresh Interval (represented in \#of fclk
+                                                         increments).
+                                                         Each refresh interval will generate a single
+                                                         auto-refresh command sequence which implicitly targets
+                                                         all banks within the device:
+                                                         Example: For fclk=200MHz(5ns)/400MHz(DDR):
+                                                           trefint(ns) = [tREFI(max)=3.9us = 3900ns [datasheet]
+                                                           REF_INT = ROUND_DOWN[(trefint/fclk)]
+                                                                   = ROUND_DOWN[(3900ns/5ns)]
+                                                                   = 780 fclks (0x30c)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t reserved_14_15          : 2;
+        uint64_t tskw                    : 2;       /**< Board Skew (represented in \#fclks)
+                                                         Represents additional board skew of DQ/DQS.
+                                                             - 00: board-skew = 0 fclk
+                                                             - 01: board-skew = 1 fclk
+                                                             - 10: board-skew = 2 fclk
+                                                             - 11: board-skew = 3 fclk
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t rnk_msk                 : 4;       /**< Controls the CS_N[3:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_DDR2_CFG[INIT]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the RNK_MSK[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per rank(or clam). In a clamshell configuration,
+                                                         the N3K DFA_A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         separate HW init sequences each unique rank address
+                                                         mapping. Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_DDR2_MRS/EMRS registers with
+                                                         the data that will be driven onto the A[14:0] wires
+                                                         during the EMRS/MRS mode register write(s).
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the RNK_MSK[3:0] field = 3'b1111 (so that CS_N[3:0]
+                                                         is driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t silo_qc                 : 1;       /**< Enables Quarter Cycle move of the Rd sampling window */
+        uint64_t silo_hc                 : 1;       /**< A combination of SILO_HC, SILO_QC and TSKW
+                                                         specifies the positioning of the sampling strobe
+                                                         when receiving read data back from DDR2. This is
+                                                         done to offset any board trace induced delay on
+                                                         the DQ and DQS which inherently makes these
+                                                         asynchronous with respect to the internal clk of
+                                                         controller. TSKW moves this sampling window by
+                                                         integer cycles. SILO_QC and HC move this quarter
+                                                         and half a cycle respectively. */
+        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#fclks): On reads, determines how many
+                                                         additional fclks to wait (on top of CASLAT+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t bprch                   : 1;       /**< Tristate Enable (back porch) (\#fclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t fprch                   : 1;       /**< Tristate Enable (front porch) (\#fclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t init                    : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for the LLM Memory Port is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port
+                                                               a) PRTENA=1
+                                                           2) Wait 200us (to ensure a stable clock
+                                                              to the DDR2) - as per DDR2 spec.
+                                                           3) Write a '1' to the INIT which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_DDR2* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t prtena                  : 1;       /**< Enable DFA Memory
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for DFA-LLM memory port. */
+#else
+        uint64_t prtena                  : 1;
+        uint64_t init                    : 1;
+        uint64_t fprch                   : 1;
+        uint64_t bprch                   : 1;
+        uint64_t sil_lat                 : 2;
+        uint64_t silo_hc                 : 1;
+        uint64_t silo_qc                 : 1;
+        uint64_t rnk_msk                 : 4;
+        uint64_t tskw                    : 2;
+        uint64_t reserved_14_15          : 2;
+        uint64_t ref_int                 : 13;
+        uint64_t reserved_29_31          : 3;
+        uint64_t fpip                    : 3;
+        uint64_t mrs_pgm                 : 1;
+        uint64_t trfc                    : 5;
+        uint64_t reserved_41_63          : 23;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_cfg_s           cn31xx;
+} cvmx_dfa_ddr2_cfg_t;
+
+
+/**
+ * cvmx_dfa_ddr2_comp
+ *
+ * DFA_DDR2_COMP = DFA DDR2 I/O PVT Compensation Configuration
+ * 
+ * 
+ * Description: The following are registers to program the DDR2 PLL and DLL
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_comp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dfa__pctl               : 4;       /**< DFA DDR pctl from compensation circuit
+                                                         Internal DBG only */
+        uint64_t dfa__nctl               : 4;       /**< DFA DDR nctl from compensation circuit
+                                                         Internal DBG only */
+        uint64_t reserved_9_55           : 47;
+        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t comp_bypass             : 1;       /**< Compensation Bypass */
+#else
+        uint64_t comp_bypass             : 1;
+        uint64_t nctl_csr                : 4;
+        uint64_t pctl_csr                : 4;
+        uint64_t reserved_9_55           : 47;
+        uint64_t dfa__nctl               : 4;
+        uint64_t dfa__pctl               : 4;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_comp_s          cn31xx;
+} cvmx_dfa_ddr2_comp_t;
+
+
+/**
+ * cvmx_dfa_ddr2_emrs
+ *
+ * DFA_DDR2_EMRS = DDR2 EMRS Register(s) EMRS1[14:0], EMRS1_OCD[14:0]
+ * Description: This register contains the data driven onto the Address[14:0] lines during  DDR INIT
+ * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
+ * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
+ * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
+ * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
+ *
+ * Notes:
+ * For DDR-II please consult your device's data sheet for further details:
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_emrs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t emrs1_ocd               : 15;      /**< Memory Address[14:0] during "EMRS1 (OCD Calibration)"
+                                                         step \#12a "EMRS OCD Default Command" A[9:7]=111
+                                                         of DDR2 HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2):
+                                                         Power Up and initialization sequence).
+                                                            A[14:13] = 0, RESERVED
+                                                            A[12] = 0, Output Buffers Enabled
+                                                            A[11] = 0, RDQS Disabled (we do not support RDQS)
+                                                            A[10] = 0, DQSn Enabled
+                                                            A[9:7] = 7, OCD Calibration Mode Default
+                                                            A[6] = 0, ODT Disabled
+                                                            A[5:3]=DFA_DDR2_TMG[ADDLAT]  Additive LATENCY (Default 0)
+                                                            A[2]=0    Termination Res RTT (ODT off Default)
+                                                            [A6,A2] = 0 -> ODT Disabled
+                                                                      1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
+                                                            A[1]=0  Normal Output Driver Imp mode
+                                                                    (1 - weak ie., 60% of normal drive strength)
+                                                            A[0] = 0 DLL Enabled */
+        uint64_t reserved_15_15          : 1;
+        uint64_t emrs1                   : 15;      /**< Memory Address[14:0] during:
+                                                           a) Step \#7 "EMRS1 to enable DLL (A[0]=0)"
+                                                           b) Step \#12b "EMRS OCD Calibration Mode Exit"
+                                                         steps of DDR2 HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up and
+                                                         initialization sequence).
+                                                           A[14:13] = 0, RESERVED
+                                                           A[12] = 0, Output Buffers Enabled
+                                                           A[11] = 0, RDQS Disabled (we do not support RDQS)
+                                                           A[10] = 0, DQSn Enabled
+                                                           A[9:7] = 0, OCD Calibration Mode exit/maintain
+                                                           A[6] = 0, ODT Disabled
+                                                           A[5:3]=DFA_DDR2_TMG[ADDLAT]  Additive LATENCY (Default 0)
+                                                           A[2]=0    Termination Res RTT (ODT off Default)
+                                                           [A6,A2] = 0 -> ODT Disabled
+                                                                     1 -> 75 ohm; 2 -> 150 ohm; 3 - Reserved
+                                                           A[1]=0  Normal Output Driver Imp mode
+                                                                   (1 - weak ie., 60% of normal drive strength)
+                                                           A[0] = 0 DLL Enabled */
+#else
+        uint64_t emrs1                   : 15;
+        uint64_t reserved_15_15          : 1;
+        uint64_t emrs1_ocd               : 15;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_emrs_s          cn31xx;
+} cvmx_dfa_ddr2_emrs_t;
+
+
+/**
+ * cvmx_dfa_ddr2_fcnt
+ *
+ * DFA_DDR2_FCNT = DFA FCLK Counter
+ * 
+ * 
+ * Description: This FCLK cycle counter gets going after memory has been initialized
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_fcnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_47_63          : 17;
+        uint64_t fcyc_cnt                : 47;      /**< Counter counts FCLK cycles or \# cycles that the memory
+                                                         controller has requests queued up depending on FCNT_MODE
+                                                         If FCNT_MODE = 0, this counter counts the \# FCLK cycles
+                                                         If FCNT_MODE = 1, this counter counts the \# cycles the
+                                                         controller is active with memory requests. */
+#else
+        uint64_t fcyc_cnt                : 47;
+        uint64_t reserved_47_63          : 17;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_fcnt_s          cn31xx;
+} cvmx_dfa_ddr2_fcnt_t;
+
+
+/**
+ * cvmx_dfa_ddr2_mrs
+ *
+ * DFA_DDR2_MRS = DDR2 MRS Register(s) MRS_DLL[14:0], MRS[14:0]
+ * Description: This register contains the data driven onto the Address[14:0] lines during DDR INIT
+ * To support Clamshelling (where N3K DFA_A[] pins are not 1:1 mapped to each clam(or rank), a HW init
+ * sequence is allowed on a "per-rank" basis. Care must be taken in the values programmed into these
+ * registers during the HW initialization sequence (see N3K specific restrictions in notes below).
+ * DFA_DDR2_CFG[MRS_PGM] must be 1 to support this feature.
+ *
+ * Notes:
+ * For DDR-II please consult your device's data sheet for further details:
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_mrs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t mrs                     : 15;      /**< Memory Address[14:0] during "MRS without resetting
+                                                         DLL A[8]=0" step of HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up
+                                                         and initialization sequence - Step \#11).
+                                                           A[14:13] = 0, RESERVED
+                                                           A[12] = 0, Fast Active Power Down Mode
+                                                           A[11:9] = DFA_DDR2_TMG[TWR]
+                                                           A[8] = 0, for DLL Reset
+                                                           A[7] =0  Test Mode (must be 0 for normal operation)
+                                                           A[6:4]=DFA_DDR2_TMG[CASLAT] CAS LATENCY (default 4)
+                                                           A[3]=0    Burst Type(must be 0:Sequential)
+                                                           A[2:0]=2  Burst Length=4(default) */
+        uint64_t reserved_15_15          : 1;
+        uint64_t mrs_dll                 : 15;      /**< Memory Address[14:0] during "MRS for DLL_RESET A[8]=1"
+                                                         step of HW initialization sequence.
+                                                         (See JEDEC DDR2 specification (JESD79-2): Power Up
+                                                         and initialization sequence - Step \#8).
+                                                           A[14:13] = 0, RESERVED
+                                                           A[12] = 0, Fast Active Power Down Mode
+                                                           A[11:9] = DFA_DDR2_TMG[TWR]
+                                                           A[8] = 1, for DLL Reset
+                                                           A[7] = 0  Test Mode (must be 0 for normal operation)
+                                                           A[6:4]=DFA_DDR2_TMG[CASLAT]    CAS LATENCY (default 4)
+                                                           A[3] = 0    Burst Type(must be 0:Sequential)
+                                                           A[2:0] = 2  Burst Length=4(default) */
+#else
+        uint64_t mrs_dll                 : 15;
+        uint64_t reserved_15_15          : 1;
+        uint64_t mrs                     : 15;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_mrs_s           cn31xx;
+} cvmx_dfa_ddr2_mrs_t;
+
+
+/**
+ * cvmx_dfa_ddr2_opt
+ *
+ * DFA_DDR2_OPT = DFA DDR2 Optimization Registers
+ * 
+ * 
+ * Description: The following are registers to tweak certain parameters to boost performance
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_opt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t max_read_batch          : 5;       /**< Maximum number of consecutive read to service before
+                                                         allowing write to interrupt. */
+        uint64_t max_write_batch         : 5;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+#else
+        uint64_t max_write_batch         : 5;
+        uint64_t max_read_batch          : 5;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_opt_s           cn31xx;
+} cvmx_dfa_ddr2_opt_t;
+
+
+/**
+ * cvmx_dfa_ddr2_pll
+ *
+ * DFA_DDR2_PLL = DFA DDR2 PLL and DLL Configuration
+ * 
+ * 
+ * Description: The following are registers to program the DDR2 PLL and DLL
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_pll_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pll_setting             : 17;      /**< Internal Debug Use Only */
+        uint64_t reserved_32_46          : 15;
+        uint64_t setting90               : 5;       /**< Contains the setting of DDR DLL; Internal DBG only */
+        uint64_t reserved_21_26          : 6;
+        uint64_t dll_setting             : 5;       /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+        uint64_t dll_byp                 : 1;       /**< DLL Bypass. When set, the DDR90 DLL is bypassed and
+                                                         the DLL behaves in Open Loop giving a fixed delay
+                                                         set by DLL_SETTING */
+        uint64_t qdll_ena                : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         erst deassertion will reset the DDR 90 DLL. Allow
+                                                         200 micro seconds for Lock before DDR Init. */
+        uint64_t bw_ctl                  : 4;       /**< Internal Use Only - for Debug */
+        uint64_t bw_upd                  : 1;       /**< Internal Use Only - for Debug */
+        uint64_t pll_div2                : 1;       /**< PLL Output is further divided by 2. Useful for slow
+                                                         fclk frequencies where the PLL may be out of range. */
+        uint64_t reserved_7_7            : 1;
+        uint64_t pll_ratio               : 5;       /**< Bits <6:2> sets the clk multiplication ratio
+                                                         If the fclk frequency desired is less than 260MHz
+                                                         (lower end saturation point of the pll), write 2x
+                                                         the ratio desired in this register and set PLL_DIV2 */
+        uint64_t pll_bypass              : 1;       /**< PLL Bypass. Uses the ref_clk without multiplication. */
+        uint64_t pll_init                : 1;       /**< Need a 0 to 1 pulse on this CSR to get the DFA
+                                                         Clk Generator Started. Write this register before
+                                                         starting anything. Allow 200 uS for PLL Lock before
+                                                         doing anything. */
+#else
+        uint64_t pll_init                : 1;
+        uint64_t pll_bypass              : 1;
+        uint64_t pll_ratio               : 5;
+        uint64_t reserved_7_7            : 1;
+        uint64_t pll_div2                : 1;
+        uint64_t bw_upd                  : 1;
+        uint64_t bw_ctl                  : 4;
+        uint64_t qdll_ena                : 1;
+        uint64_t dll_byp                 : 1;
+        uint64_t dll_setting             : 5;
+        uint64_t reserved_21_26          : 6;
+        uint64_t setting90               : 5;
+        uint64_t reserved_32_46          : 15;
+        uint64_t pll_setting             : 17;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_pll_s           cn31xx;
+} cvmx_dfa_ddr2_pll_t;
+
+
+/**
+ * cvmx_dfa_ddr2_tmg
+ *
+ * DFA_DDR2_TMG = DFA DDR2 Memory Timing Config Register
+ * 
+ * 
+ * Description: The following are registers to program the DDR2 memory timing parameters.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ddr2_tmg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_47_63          : 17;
+        uint64_t fcnt_mode               : 1;       /**< If FCNT_MODE = 0, this counter counts the \# FCLK cycles
+                                                         If FCNT_MODE = 1, this counter counts the \# cycles the
+                                                         controller is active with memory requests. */
+        uint64_t cnt_clr                 : 1;       /**< Clears the FCLK Cyc & Bus Util counter */
+        uint64_t cavmipo                 : 1;       /**< RESERVED */
+        uint64_t ctr_rst                 : 1;       /**< Reset oneshot pulse for refresh counter & Perf counters
+                                                         SW should first write this field to a one to clear
+                                                         & then write to a zero for normal operation */
+        uint64_t odt_rtt                 : 2;       /**< DDR2 Termination Resistor Setting
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                              00 = ODT Disabled
+                                                              01 = 75 ohm Termination
+                                                              10 = 150 ohm Termination
+                                                              11 = 50 ohm Termination */
+        uint64_t dqsn_ena                : 1;       /**< For DDR-II Mode, DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                              0 - DQSN Enable
+                                                              1 - DQSN Disable */
+        uint64_t dic                     : 1;       /**< Drive Strength Control:
+                                                         For DDR-I/II Mode, DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization. (see DDR-I data sheet EMRS
+                                                         description)
+                                                              0 = Normal
+                                                              1 = Reduced */
+        uint64_t r2r_slot                : 1;       /**< A 1 on this register will force the controller to
+                                                         slot a bubble between every reads */
+        uint64_t tfaw                    : 5;       /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                         Four Access Window time. Relevant only in
+                                                         8-bank parts.
+                                                              TFAW = 5'b0 for DDR2-4bank
+                                                              TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
+        uint64_t twtr                    : 4;       /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
+                                                         Last Wr Data to Rd Command time.
+                                                         (Represented in fclk cycles)
+                                                         TYP=15ns
+                                                              - 0000: RESERVED
+                                                              - 0001: 1
+                                                              - ...
+                                                              - 0111: 7
+                                                              - 1000-1111: RESERVED */
+        uint64_t twr                     : 3;       /**< DDR Write Recovery time (tWR). Last Wr Brst to Prech
+                                                         This is not a direct encoding of the value. Its
+                                                         programmed as below per DDR2 spec. The decimal number
+                                                         on the right is RNDUP(tWR(ns) / clkFreq)
+                                                         TYP=15ns
+                                                              - 000: RESERVED
+                                                              - 001: 2
+                                                              - 010: 3
+                                                              - 011: 4
+                                                              - 100: 5
+                                                              - 101: 6
+                                                              - 110-111: RESERVED */
+        uint64_t trp                     : 4;       /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
+                                                         (Represented in fclk cycles)
+                                                         TYP=15ns
+                                                              - 0000: RESERVED
+                                                              - 0001: 1
+                                                              - ...
+                                                              - 0111: 7
+                                                              - 1000-1111: RESERVED
+                                                         When using parts with 8 banks (DFA_CFG->MAX_BNK
+                                                         is 1), load tRP cycles + 1 into this register. */
+        uint64_t tras                    : 5;       /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
+                                                         (Represented in fclk cycles)
+                                                         TYP=45ns
+                                                              - 00000-0001: RESERVED
+                                                              - 00010: 2
+                                                              - ...
+                                                              - 10100: 20
+                                                              - 10101-11111: RESERVED */
+        uint64_t trrd                    : 3;       /**< tRRD cycles: ACT-ACT timing parameter for different
+                                                         banks. (Represented in fclk cycles)
+                                                         For DDR2, TYP=7.5ns
+                                                             - 000: RESERVED
+                                                             - 001: 1 tCYC
+                                                             - 010: 2 tCYC
+                                                             - 011: 3 tCYC
+                                                             - 100: 4 tCYC
+                                                             - 101: 5 tCYC
+                                                             - 110-111: RESERVED */
+        uint64_t trcd                    : 4;       /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
+                                                         (Represented in fclk cycles)
+                                                         TYP=15ns
+                                                              - 0000: RESERVED
+                                                              - 0001: 2 (2 is the smallest value allowed)
+                                                              - 0002: 2
+                                                              - ...
+                                                              - 0111: 7
+                                                              - 1110-1111: RESERVED */
+        uint64_t addlat                  : 3;       /**< When in Posted CAS mode ADDLAT needs to be programmed
+                                                         to tRCD-1
+                                                               ADDLAT         \#additional latency cycles
+                                                                000              0
+                                                                001              1 (tRCD = 2 fclk's)
+                                                                010              2 (tRCD = 3 fclk's)
+                                                                011              3 (tRCD = 4 fclk's)
+                                                                100              4 (tRCD = 5 fclk's)
+                                                                101              5 (tRCD = 6 fclk's)
+                                                                110              6 (tRCD = 7 fclk's)
+                                                                111              7 (tRCD = 8 fclk's) */
+        uint64_t pocas                   : 1;       /**< Posted CAS mode. When 1, we use DDR2's Posted CAS
+                                                         feature. When using this mode, ADDLAT needs to be
+                                                         programmed as well */
+        uint64_t caslat                  : 3;       /**< CAS Latency in \# fclk Cycles
+                                                         CASLAT           \#  CAS latency cycles
+                                                          000 - 010           RESERVED
+                                                          011                    3
+                                                          100                    4
+                                                          101                    5
+                                                          110                    6
+                                                          111                    7 */
+        uint64_t tmrd                    : 2;       /**< tMRD Cycles
+                                                         (Represented in fclk tCYC)
+                                                         For DDR2, its TYP 2*tCYC)
+                                                             - 000: RESERVED
+                                                             - 001: 1
+                                                             - 010: 2
+                                                             - 011: 3 */
+        uint64_t ddr2t                   : 1;       /**< When 2T mode is turned on, command signals are
+                                                         setup a cycle ahead of when the CS is enabled
+                                                         and kept for a total of 2 cycles. This mode is
+                                                         enabled in higher speeds when there is difficulty
+                                                         meeting setup. Performance could
+                                                         be negatively affected in 2T mode */
+#else
+        uint64_t ddr2t                   : 1;
+        uint64_t tmrd                    : 2;
+        uint64_t caslat                  : 3;
+        uint64_t pocas                   : 1;
+        uint64_t addlat                  : 3;
+        uint64_t trcd                    : 4;
+        uint64_t trrd                    : 3;
+        uint64_t tras                    : 5;
+        uint64_t trp                     : 4;
+        uint64_t twr                     : 3;
+        uint64_t twtr                    : 4;
+        uint64_t tfaw                    : 5;
+        uint64_t r2r_slot                : 1;
+        uint64_t dic                     : 1;
+        uint64_t dqsn_ena                : 1;
+        uint64_t odt_rtt                 : 2;
+        uint64_t ctr_rst                 : 1;
+        uint64_t cavmipo                 : 1;
+        uint64_t cnt_clr                 : 1;
+        uint64_t fcnt_mode               : 1;
+        uint64_t reserved_47_63          : 17;
+#endif
+    } s;
+    struct cvmx_dfa_ddr2_tmg_s           cn31xx;
+} cvmx_dfa_ddr2_tmg_t;
+
+
+/**
+ * cvmx_dfa_difctl
+ *
+ * DFA_DIFCTL = DFA Instruction FIFO (DIF) Control Register
+ * 
+ * Description:
+ *  NOTE: To write to the DFA_DIFCTL register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b11.
+ *        To read the DFA_DIFCTL register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b11.
+ * 
+ *  NOTE: This register is intended to ONLY be written once (at power-up). Any future writes could
+ *  cause the DFA and FPA HW to become unpredictable.
+ * 
+ *  NOTE: If DFA_CFG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFCTL register do not take effect.
+ *  NOTE: If FUSE[120]="DFA DTE disable" is blown, reads/writes to the DFA_DIFCTL register do not take effect.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_difctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t dwbcnt                  : 8;       /**< Represents the \# of cache lines in the instruction
+                                                         buffer that may be dirty and should not be
+                                                         written-back to memory when the instruction
+                                                         chunk is returned to the Free Page list.
+                                                         NOTE: Typically SW will want to mark all DFA
+                                                         Instruction memory returned to the Free Page list
+                                                         as DWB (Don't WriteBack), therefore SW should
+                                                         seed this register as:
+                                                           DFA_DIFCTL[DWBCNT] = (DFA_DIFCTL[SIZE] + 4)/4 */
+        uint64_t pool                    : 3;       /**< Represents the 3bit buffer pool-id  used by DFA HW
+                                                         when the DFA instruction chunk is recycled back
+                                                         to the Free Page List maintained by the FPA HW
+                                                         (once the DFA instruction has been issued). */
+        uint64_t size                    : 9;       /**< Represents the \# of 32B instructions contained
+                                                         within each DFA instruction chunk. At Power-on,
+                                                         SW will seed the SIZE register with a fixed
+                                                         chunk-size. (Must be at least 3)
+                                                         DFA HW uses this field to determine the size
+                                                         of each DFA instruction chunk, in order to:
+                                                            a) determine when to read the next DFA
+                                                               instruction chunk pointer which is
+                                                               written by SW at the end of the current
+                                                               DFA instruction chunk (see DFA description
+                                                               of next chunk buffer Ptr for format).
+                                                            b) determine when a DFA instruction chunk
+                                                               can be returned to the Free Page List
+                                                               maintained by the FPA HW. */
+#else
+        uint64_t size                    : 9;
+        uint64_t pool                    : 3;
+        uint64_t dwbcnt                  : 8;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_dfa_difctl_s             cn31xx;
+    struct cvmx_dfa_difctl_s             cn38xx;
+    struct cvmx_dfa_difctl_s             cn38xxp2;
+    struct cvmx_dfa_difctl_s             cn58xx;
+    struct cvmx_dfa_difctl_s             cn58xxp1;
+} cvmx_dfa_difctl_t;
+
+
+/**
+ * cvmx_dfa_difrdptr
+ *
+ * DFA_DIFRDPTR = DFA Instruction FIFO (DIF) RDPTR Register
+ * 
+ * Description:
+ *  NOTE: To write to the DFA_DIFRDPTR register, a device would issue an IOBST directed at the DFA with addr[34:33]=2'b01.
+ *        To read the DFA_DIFRDPTR register, a device would issue an IOBLD64 directed at the DFA with addr[34:33]=2'b01.
+ * 
+ *  NOTE: If DFA_CFG[DTECLKDIS]=1 (DFA-DTE clocks disabled), reads/writes to the DFA_DIFRDPTR register do not take effect.
+ *  NOTE: If FUSE[120]="DFA DTE disable" is blown, reads/writes to the DFA_DIFRDPTR register do not take effect.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_difrdptr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t rdptr                   : 31;      /**< Represents the 32B-aligned address of the current
+                                                         instruction in the DFA Instruction FIFO in main
+                                                         memory. The RDPTR must be seeded by software at
+                                                         boot time, and is then maintained thereafter
+                                                         by DFA HW.
+                                                         During the seed write (by SW), RDPTR[6:5]=0,
+                                                         since DFA instruction chunks must be 128B aligned.
+                                                         During a read (by SW), the 'most recent' contents
+                                                         of the RDPTR register are returned at the time
+                                                         the NCB-INB bus is driven.
+                                                         NOTE: Since DFA HW updates this register, its
+                                                         contents are unpredictable in SW (unless
+                                                         its guaranteed that no new DoorBell register
+                                                         writes have occurred and the DoorBell register is
+                                                         read as zero). */
+        uint64_t reserved_0_4            : 5;
+#else
+        uint64_t reserved_0_4            : 5;
+        uint64_t rdptr                   : 31;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_dfa_difrdptr_s           cn31xx;
+    struct cvmx_dfa_difrdptr_s           cn38xx;
+    struct cvmx_dfa_difrdptr_s           cn38xxp2;
+    struct cvmx_dfa_difrdptr_s           cn58xx;
+    struct cvmx_dfa_difrdptr_s           cn58xxp1;
+} cvmx_dfa_difrdptr_t;
+
+
+/**
+ * cvmx_dfa_eclkcfg
+ *
+ * Specify the RSL base addresses for the block
+ * 
+ *                  DFA_ECLKCFG = DFA eclk-domain Configuration Registers
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_eclkcfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t sbdnum                  : 3;       /**< SBD Debug Entry#
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         Selects which one of 8 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+        uint64_t reserved_15_15          : 1;
+        uint64_t sbdlck                  : 1;       /**< DFA Scoreboard LOCK Strobe
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+        uint64_t dcmode                  : 1;       /**< DRF-CRQ/DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t dtmode                  : 1;       /**< DRF-DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t pmode                   : 1;       /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t qmode                   : 1;       /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t imode                   : 1;       /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t sarb                    : 1;       /**< DFA Source Arbiter Mode
+                                                         Selects the arbitration mode used to select DFA requests
+                                                         issued from either CP2 or the DTE (NCB-CSR or DFA HW engine).
+                                                          - 0: Fixed Priority [Highest=CP2, Lowest=DTE]
+                                                          - 1: Round-Robin
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t reserved_3_7            : 5;
+        uint64_t dteclkdis               : 1;       /**< DFA DTE Clock Disable
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled.
+                                                         NOTE: When SET, SW MUST NEVER issue ANY operations to
+                                                         the DFA via the NCB Bus. All DFA Operations must be
+                                                         issued solely through the CP2 interface. */
+        uint64_t maxbnk                  : 1;       /**< Maximum Banks per-device (used by the address mapper
+                                                         when extracting address bits for the memory bank#.
+                                                                 - 0: 4 banks/device
+                                                                 - 1: 8 banks/device */
+        uint64_t dfa_frstn               : 1;       /**< Hold this 0 until the DFA DDR PLL and DLL lock
+                                                         and then write a 1. A 1 on this register deasserts
+                                                         the internal frst_n. Refer to DFA_DDR2_PLL registers for more
+                                                         startup information.
+                                                         Startup sequence if DFA interface needs to be ON:
+                                                          After valid power up,
+                                                          Write DFA_DDR2_PLL-> PLL_RATIO & PLL_DIV2 & PLL_BYPASS
+                                                          to the appropriate values
+                                                          Wait a few cycles
+                                                          Write a 1 DFA_DDR2_PLL -> PLL_INIT
+                                                          Wait 100 microseconds
+                                                          Write a 1 to DFA_DDR2_PLL -> QDLL_ENA
+                                                          Wait 10 microseconds
+                                                          Write a 1 to this register DFA_FRSTN to pull DFA out of
+                                                          reset
+                                                          Now the DFA block is ready to be initialized (follow the
+                                                          DDR init sequence). */
+#else
+        uint64_t dfa_frstn               : 1;
+        uint64_t maxbnk                  : 1;
+        uint64_t dteclkdis               : 1;
+        uint64_t reserved_3_7            : 5;
+        uint64_t sarb                    : 1;
+        uint64_t imode                   : 1;
+        uint64_t qmode                   : 1;
+        uint64_t pmode                   : 1;
+        uint64_t dtmode                  : 1;
+        uint64_t dcmode                  : 1;
+        uint64_t sbdlck                  : 1;
+        uint64_t reserved_15_15          : 1;
+        uint64_t sbdnum                  : 3;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } s;
+    struct cvmx_dfa_eclkcfg_s            cn31xx;
+} cvmx_dfa_eclkcfg_t;
+
+
+/**
+ * cvmx_dfa_err
+ *
+ * DFA_ERR = DFA ERROR Register
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_err_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_33_63          : 31;
+        uint64_t dblina                  : 1;       /**< Doorbell Overflow Interrupt Enable bit.
+                                                         When set, doorbell overflow conditions are reported. */
+        uint64_t dblovf                  : 1;       /**< Doorbell Overflow detected - Status bit
+                                                         When set, the 20b accumulated doorbell register
+                                                         had overflowed (SW wrote too many doorbell requests).
+                                                         If the DBLINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         NOTE: Detection of a Doorbell Register overflow
+                                                         is a catastrophic error which may leave the DFA
+                                                         HW in an unrecoverable state. */
+        uint64_t cp2pina                 : 1;       /**< CP2 LW Mode Parity Error Interrupt Enable bit.
+                                                         When set, all PP-generated LW Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 36b of data) are reported. */
+        uint64_t cp2perr                 : 1;       /**< PP-CP2 Parity Error Detected - Status bit
+                                                         When set, a parity error had been detected for a
+                                                         PP-generated LW Mode read transaction.
+                                                         If the CP2PINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure. */
+        uint64_t cp2parena               : 1;       /**< CP2 LW Mode Parity Error Enable
+                                                         When set, all PP-generated LW Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 36b of data) are reported.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no PP-CP2 transactions
+                                                         (preferrably during power-on software initialization). */
+        uint64_t dtepina                 : 1;       /**< DTE Parity Error Interrupt Enable bit
+                                                         (for 18b SIMPLE mode ONLY).
+                                                         When set, all DTE-generated 18b SIMPLE Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 17b of data) are reported. */
+        uint64_t dteperr                 : 1;       /**< DTE Parity Error Detected (for 18b SIMPLE mode ONLY)
+                                                         When set, all DTE-generated 18b SIMPLE Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 17b of data) are reported. */
+        uint64_t dteparena               : 1;       /**< DTE Parity Error Enable (for 18b SIMPLE mode ONLY)
+                                                         When set, all DTE-generated 18b SIMPLE Mode read
+                                                         transactions which encounter a parity error (across
+                                                         the 17b of data) are reported.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no DFA thread engines active
+                                                         (preferrably during power-on). */
+        uint64_t dtesyn                  : 7;       /**< DTE 29b ECC Failing 6bit Syndrome
+                                                         When DTESBE or DTEDBE are set, this field contains
+                                                         the failing 7b ECC syndrome. */
+        uint64_t dtedbina                : 1;       /**< DTE 29b Double Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any DTE-generated
+                                                         36b SIMPLE Mode read which encounters a double bit
+                                                         error. */
+        uint64_t dtesbina                : 1;       /**< DTE 29b Single Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any DTE-generated
+                                                         36b SIMPLE Mode read which encounters a single bit
+                                                         error (which is also corrected). */
+        uint64_t dtedbe                  : 1;       /**< DTE 29b Double Bit Error Detected - Status bit
+                                                         When set, a double bit error had been detected
+                                                         for a DTE-generated 36b SIMPLE Mode read transaction.
+                                                         The DTESYN contains the failing syndrome.
+                                                         If the DTEDBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure.
+                                                         NOTE: DTE-generated 18b SIMPLE Mode Read transactions
+                                                         do not participate in ECC check/correct). */
+        uint64_t dtesbe                  : 1;       /**< DTE 29b Single Bit Error Corrected - Status bit
+                                                         When set, a single bit error had been detected and
+                                                         corrected for a DTE-generated 36b SIMPLE Mode read
+                                                         transaction.
+                                                         If the DTEDBE=0, then the DTESYN contains the
+                                                         failing syndrome (used during correction).
+                                                         NOTE: DTE-generated 18b SIMPLE Mode Read
+                                                         transactions do not participate in ECC check/correct).
+                                                         If the DTESBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure. */
+        uint64_t dteeccena               : 1;       /**< DTE 29b ECC Enable (for 36b SIMPLE mode ONLY)
+                                                         When set, 29b ECC is enabled on all DTE-generated
+                                                         36b SIMPLE Mode read transactions.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no DFA thread engines active
+                                                         (preferrably during power-on software initialization). */
+        uint64_t cp2syn                  : 8;       /**< PP-CP2 QW ECC Failing 8bit Syndrome
+                                                         When CP2SBE or CP2DBE are set, this field contains
+                                                         the failing ECC 8b syndrome.
+                                                         Refer to CP2ECCENA. */
+        uint64_t cp2dbina                : 1;       /**< PP-CP2 Double Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any PP-generated
+                                                         QW Mode read which encounters a double bit error.
+                                                         Refer to CP2DBE. */
+        uint64_t cp2sbina                : 1;       /**< PP-CP2 Single Bit Error Interrupt Enable bit
+                                                         When set, an interrupt is posted for any PP-generated
+                                                         QW Mode read which encounters a single bit error
+                                                         (which is also corrected).
+                                                         Refer to CP2SBE. */
+        uint64_t cp2dbe                  : 1;       /**< PP-CP2 Double Bit Error Detected - Status bit
+                                                         When set, a double bit error had been detected
+                                                         for a PP-generated QW Mode read transaction.
+                                                         The CP2SYN contains the failing syndrome.
+                                                          NOTE: PP-generated LW Mode Read transactions
+                                                         do not participate in ECC check/correct).
+                                                         Refer to CP2ECCENA.
+                                                         If the CP2DBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure. */
+        uint64_t cp2sbe                  : 1;       /**< PP-CP2 Single Bit Error Corrected - Status bit
+                                                         When set, a single bit error had been detected and
+                                                         corrected for a PP-generated QW Mode read
+                                                         transaction.
+                                                         If the CP2DBE=0, then the CP2SYN contains the
+                                                         failing syndrome (used during correction).
+                                                         Refer to CP2ECCENA.
+                                                         If the CP2SBINA had previously been enabled(set),
+                                                         an interrupt will be posted. Software can clear
+                                                         the interrupt by writing a 1 to this register bit.
+                                                         See also: DFA_MEMFADR CSR which contains more data
+                                                         about the memory address/control to help isolate
+                                                         the failure.
+                                                         NOTE: PP-generated LW Mode Read transactions
+                                                         do not participate in ECC check/correct). */
+        uint64_t cp2eccena               : 1;       /**< PP-CP2 QW ECC Enable (for QW Mode transactions)
+                                                         When set, 8bit QW ECC is enabled on all PP-generated
+                                                         QW Mode read transactions, CP2SBE and
+                                                         CP2DBE may be set, and CP2SYN may be filled.
+                                                         NOTE: This signal must only be written to a different
+                                                         value when there are no PP-CP2 transactions
+                                                         (preferrably during power-on software initialization).
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store. */
+#else
+        uint64_t cp2eccena               : 1;
+        uint64_t cp2sbe                  : 1;
+        uint64_t cp2dbe                  : 1;
+        uint64_t cp2sbina                : 1;
+        uint64_t cp2dbina                : 1;
+        uint64_t cp2syn                  : 8;
+        uint64_t dteeccena               : 1;
+        uint64_t dtesbe                  : 1;
+        uint64_t dtedbe                  : 1;
+        uint64_t dtesbina                : 1;
+        uint64_t dtedbina                : 1;
+        uint64_t dtesyn                  : 7;
+        uint64_t dteparena               : 1;
+        uint64_t dteperr                 : 1;
+        uint64_t dtepina                 : 1;
+        uint64_t cp2parena               : 1;
+        uint64_t cp2perr                 : 1;
+        uint64_t cp2pina                 : 1;
+        uint64_t dblovf                  : 1;
+        uint64_t dblina                  : 1;
+        uint64_t reserved_33_63          : 31;
+#endif
+    } s;
+    struct cvmx_dfa_err_s                cn31xx;
+    struct cvmx_dfa_err_s                cn38xx;
+    struct cvmx_dfa_err_s                cn38xxp2;
+    struct cvmx_dfa_err_s                cn58xx;
+    struct cvmx_dfa_err_s                cn58xxp1;
+} cvmx_dfa_err_t;
+
+
+/**
+ * cvmx_dfa_memcfg0
+ *
+ * DFA_MEMCFG0 = DFA Memory Configuration
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_memcfg0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rldqck90_rst            : 1;       /**< RLDCK90 and RLDQK90 DLL SW Reset
+                                                         When written with a '1' the RLDCK90 and RLDQK90 DLL are
+                                                         in soft-reset. */
+        uint64_t rldck_rst               : 1;       /**< RLDCK Zero Delay DLL(Clock Generator) SW Reset
+                                                         When written with a '1' the RLDCK zero delay DLL is in
+                                                         soft-reset. */
+        uint64_t clkdiv                  : 2;       /**< RLDCLK Divisor Select
+                                                           - 0: RLDx_CK_H/L = Core Clock /2
+                                                           - 1: RESERVED (must not be used)
+                                                           - 2: RLDx_CK_H/L = Core Clock /3
+                                                           - 3: RLDx_CK_H/L = Core Clock /4
+                                                         The DFA LLM interface(s) are tied to the core clock
+                                                         frequency through this programmable clock divisor.
+                                                         Examples:
+                                                            Core Clock(MHz) | DFA-LLM Clock(MHz) | CLKDIV
+                                                           -----------------+--------------------+--------
+                                                                 800        |    400/(800-DDR)   |  /2
+                                                                1000        |    333/(666-DDR)   |  /3
+                                                                 800        |    200/(400-DDR)   |  /4
+                                                         NOTE: This value MUST BE programmed BEFORE doing a
+                                                         Hardware init sequence (see: DFA_MEMCFG0[INIT_Px] bits).
+                                                         *** NOTE: O9N PASS1 Addition */
+        uint64_t lpp_ena                 : 1;       /**< PP Linear Port Addressing Mode Enable
+                                                         When enabled, PP-core LLM accesses to the lower-512MB
+                                                         LLM address space are sent to the single DFA port
+                                                         which is enabled. NOTE: If LPP_ENA=1, only
+                                                         one DFA RLDRAM port may be enabled for RLDRAM accesses
+                                                         (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
+                                                         PP-core LLM accesses to the upper-512MB LLM address
+                                                         space are sent to the other 'disabled' DFA port.
+                                                         SW RESTRICTION: If LPP_ENA=1, then only one DFA port
+                                                         may be enabled for RLDRAM accesses (ie: ENA_P0 and
+                                                         ENA_P1 CAN NEVER BOTH be set).
+                                                         NOTE: This bit is used to allow PP-Core LLM accesses to a
+                                                         disabled port, such that each port can be sequentially
+                                                         addressed (ie: disable LW address interleaving).
+                                                         Enabling this bit allows BOTH PORTs to be active and
+                                                         sequentially addressable. The single port that is
+                                                         enabled(ENA_Px) will respond to the low-512MB LLM address
+                                                         space, and the other 'disabled' port will respond to the
+                                                         high-512MB LLM address space.
+                                                         Example usage:
+                                                            - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
+                                                            - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
+                                                         USAGE NOTE:
+                                                         If LPP_ENA=1 and SW DOES NOT initialize the disabled port
+                                                         (ie: INIT_Px=0->1), then refreshes and the HW init
+                                                         sequence WILL NOT occur for the disabled port.
+                                                         If LPP_ENA=1 and SW does initialize the disabled port
+                                                         (INIT_Px=0->1 with ENA_Px=0), then refreshes and
+                                                         the HW init sequence WILL occur to the disabled port. */
+        uint64_t bunk_init               : 2;       /**< Controls the CS_N[1:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per bunk(or clam). In a clamshell configuration,
+                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         two separate HW init sequences for the two bunks
+                                                         (or clams) . Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_MEMRLD[22:0] with the data
+                                                         that will be driven onto the A[22:0] wires during
+                                                         an MRS mode register write.
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
+                                                         driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t init_p0                 : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#0 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
+                                                              RLDRAM operation.
+                                                                [legal values 0: DIV2 2: DIV3 3: DIV4]
+                                                           2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
+                                                              and DFA_MEM_CFG0[RLDQCK90_RST] field at
+                                                              the SAME TIME. This step puts all three DLLs in
+                                                              SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
+                                                           3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
+                                                              This step takes the RLDCK DLL out of soft-reset so
+                                                              that the DLL can generate the RLDx_CK_H/L clock pins.
+                                                           4) Wait 1ms (for RLDCK DLL to achieve lock)
+                                                           5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
+                                                              This step takes the RLDCK90 DLL AND RLDQK90 DLL out
+                                                              of soft-reset.
+                                                           6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
+                                                           7) Enable memory port(s):  ENA_P0=1/ENA_P1=1
+                                                           8) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                           9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
+                                                              intended to be initialized.
+                                                          10) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence to that'specific' port.
+                                                          11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
+                                                              [to ensure the HW init sequence has completed
+                                                              before writing to ANY of the DFA_MEM* registers]
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                          12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
+                                                              refreshes to BOTH bunks.
+                                                         NOTE: In some cases (where the address wires are routed
+                                                         differently between the front and back 'bunks'),
+                                                         SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
+                                                         control the Hardware initialization sequence for a
+                                                         'specific bunk'. In these cases, SW would setup the
+                                                         BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+        uint64_t init_p1                 : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#1 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Set up the DFA_MEMCFG0[CLKDIV] ratio for intended
+                                                              RLDRAM operation.
+                                                                [legal values 0: DIV2 2: DIV3 3: DIV4]
+                                                           2) Write a '1' into BOTH the DFA_MEM_CFG0[RLDCK_RST]
+                                                              and DFA_MEM_CFG0[RLDQCK90_RST] field at
+                                                              the SAME TIME. This step puts all three DLLs in
+                                                              SW reset (RLDCK, RLDCK90, RLDQK90 DLLs).
+                                                           3) Write a '0' into the DFA_MEM_CFG0[RLDCK_RST] field.
+                                                              This step takes the RLDCK DLL out of soft-reset so
+                                                              that the DLL can generate the RLDx_CK_H/L clock pins.
+                                                           4) Wait 1ms (for RLDCK DLL to achieve lock)
+                                                           5) Write a '0' into DFA_MEM_CFG0[RLDQCK90_RST] field.
+                                                              This step takes the RLDCK90 DLL AND RLDQK90 DLL out
+                                                              of soft-reset.
+                                                           6) Wait 1ms (for RLDCK90/RLDQK90 DLLs to achieve lock)
+                                                           7) Enable memory port(s) ENA_P0=1/ENA_P1=1
+                                                           8) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                           9) Setup the DFA_MEMCFG0[BUNK_INIT] for the bunk(s)
+                                                              intended to be initialized.
+                                                          10) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence to that'specific' port.
+                                                          11) Wait (DFA_MEMCFG0[CLKDIV] * 32K) eclk cycles.
+                                                              [to ensure the HW init sequence has completed
+                                                              before writing to ANY of the DFA_MEM* registers]
+                                                           - - - - - Hardware Initialization Sequence - - - - -
+                                                          12) Write the DFA_MEMCFG0[BUNK_INIT]=3 to enable
+                                                              refreshes to BOTH bunks.
+                                                         NOTE: In some cases (where the address wires are routed
+                                                         differently between the front and back 'bunks'),
+                                                         SW will need to use DFA_MEMCFG0[BUNK_INIT] bits to
+                                                         control the Hardware initialization sequence for a
+                                                         'specific bunk'. In these cases, SW would setup the
+                                                         BUNK_INIT and repeat Steps \#9-11 for each bunk/port.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+        uint64_t r2r_pbunk               : 1;       /**< When enabled, an additional command bubble is inserted
+                                                         if back to back reads are issued to different physical
+                                                         bunks. This is to avoid DQ data bus collisions when
+                                                         references cross between physical bunks.
+                                                         [NOTE: the physical bunk address boundary is determined
+                                                         by the PBUNK bit].
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t pbunk                   : 3;       /**< Physical Bunk address bit pointer.
+                                                         Specifies which address bit within the Longword
+                                                         Memory address MA[23:0] is used to determine the
+                                                         chip selects.
+                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
+                                                         RLD_CS1_N corresponds to physical bunk \#1].
+                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
+                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
+                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
+                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
+                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
+                                                           - 101-111: CS0_N = 0 /CS1_N = 1
+                                                         Example(s):
+                                                         To build out a 128MB DFA memory, 4x 32Mx9
+                                                         parts could be used to fill out TWO physical
+                                                         bunks (clamshell configuration). Each (of the
+                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
+                                                         Each RLDRAM device also contains 8 internal banks,
+                                                         therefore the memory Address is 16M/8banks = 2M
+                                                         addresses/bunk (2^21). In this case, MA[21] would
+                                                         select the physical bunk.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         be used to determine the Chip Select(s). */
+        uint64_t blen                    : 1;       /**< Device Burst Length  (0=2-burst/1=4-burst)
+                                                         NOTE: RLDRAM-II MUST USE BLEN=0(2-burst) */
+        uint64_t bprch                   : 2;       /**< Tristate Enable (back porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t fprch                   : 2;       /**< Tristate Enable (front porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t wr_dly                  : 4;       /**< Write->Read CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from write to read. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
+                                                         on W->R transitions is not pronounced. */
+        uint64_t rw_dly                  : 4;       /**< Read->Write CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from read to write. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
+                                                         on R->W transitions is not pronounced. */
+        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#dclks): On reads, determines how many
+                                                         additional dclks to wait (on top of tRL+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t mtype                   : 1;       /**< FCRAM-II Memory Type
+                                                         *** O9N UNSUPPORTED *** */
+        uint64_t reserved_2_2            : 1;
+        uint64_t ena_p0                  : 1;       /**< Enable DFA RLDRAM Port#0
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#0.
+                                                         NOTE: a customer is at
+                                                         liberty to enable either Port#0 or Port#1 or both.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+        uint64_t ena_p1                  : 1;       /**< Enable DFA RLDRAM Port#1
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#1.
+                                                         NOTE: a customer is at
+                                                         liberty to enable either Port#0 or Port#1 or both.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+#else
+        uint64_t ena_p1                  : 1;
+        uint64_t ena_p0                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t mtype                   : 1;
+        uint64_t sil_lat                 : 2;
+        uint64_t rw_dly                  : 4;
+        uint64_t wr_dly                  : 4;
+        uint64_t fprch                   : 2;
+        uint64_t bprch                   : 2;
+        uint64_t blen                    : 1;
+        uint64_t pbunk                   : 3;
+        uint64_t r2r_pbunk               : 1;
+        uint64_t init_p1                 : 1;
+        uint64_t init_p0                 : 1;
+        uint64_t bunk_init               : 2;
+        uint64_t lpp_ena                 : 1;
+        uint64_t clkdiv                  : 2;
+        uint64_t rldck_rst               : 1;
+        uint64_t rldqck90_rst            : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_dfa_memcfg0_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t lpp_ena                 : 1;       /**< PP Linear Port Addressing Mode Enable
+                                                         When enabled, PP-core LLM accesses to the lower-512MB
+                                                         LLM address space are sent to the single DFA port
+                                                         which is enabled. NOTE: If LPP_ENA=1, only
+                                                         one DFA RLDRAM port may be enabled for RLDRAM accesses
+                                                         (ie: ENA_P0 and ENA_P1 CAN NEVER BOTH be set).
+                                                         PP-core LLM accesses to the upper-512MB LLM address
+                                                         space are sent to the other 'disabled' DFA port.
+                                                         SW RESTRICTION: If LPP_ENA=1, then only one DFA port
+                                                         may be enabled for RLDRAM accesses (ie: ENA_P0 and
+                                                         ENA_P1 CAN NEVER BOTH be set).
+                                                         NOTE: This bit is used to allow PP-Core LLM accesses to a
+                                                         disabled port, such that each port can be sequentially
+                                                         addressed (ie: disable LW address interleaving).
+                                                         Enabling this bit allows BOTH PORTs to be active and
+                                                         sequentially addressable. The single port that is
+                                                         enabled(ENA_Px) will respond to the low-512MB LLM address
+                                                         space, and the other 'disabled' port will respond to the
+                                                         high-512MB LLM address space.
+                                                         Example usage:
+                                                            - DFA RLD0 pins used for TCAM-FPGA(CP2 accesses)
+                                                            - DFA RLD1 pins used for RLDRAM (DTE/CP2 accesses).
+                                                         USAGE NOTE:
+                                                         If LPP_ENA=1 and SW DOES NOT initialize the disabled port
+                                                         (ie: INIT_Px=0->1), then refreshes and the HW init
+                                                         sequence WILL NOT occur for the disabled port.
+                                                         If LPP_ENA=1 and SW does initialize the disabled port
+                                                         (INIT_Px=0->1 with ENA_Px=0), then refreshes and
+                                                         the HW init sequence WILL occur to the disabled port. */
+        uint64_t bunk_init               : 2;       /**< Controls the CS_N[1:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per bunk(or clam). In a clamshell configuration,
+                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         two separate HW init sequences for the two bunks
+                                                         (or clams) . Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_MEMRLD[22:0] with the data
+                                                         that will be driven onto the A[22:0] wires during
+                                                         an MRS mode register write.
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
+                                                         driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
+                                                         initialized independently. In other words, a HW init
+                                                         must be done for Bunk#0, and then another HW init
+                                                         must be done for Bunk#1 at power-on. */
+        uint64_t init_p0                 : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#0 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+        uint64_t init_p1                 : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#1 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+        uint64_t r2r_pbunk               : 1;       /**< When enabled, an additional command bubble is inserted
+                                                         if back to back reads are issued to different physical
+                                                         bunks. This is to avoid DQ data bus collisions when
+                                                         references cross between physical bunks.
+                                                         [NOTE: the physical bunk address boundary is determined
+                                                         by the PBUNK bit].
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
+                                                         ZERO(for optimal performance). However, if electrically,
+                                                         DQ-sharing becomes a power/heat issue, then R2R_PBUNK
+                                                         should be set (but at a cost to performance (1/2 BW). */
+        uint64_t pbunk                   : 3;       /**< Physical Bunk address bit pointer.
+                                                         Specifies which address bit within the Longword
+                                                         Memory address MA[23:0] is used to determine the
+                                                         chip selects.
+                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
+                                                         RLD_CS1_N corresponds to physical bunk \#1].
+                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
+                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
+                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
+                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
+                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
+                                                           - 101-111: CS0_N = 0 /CS1_N = 1
+                                                         Example(s):
+                                                         To build out a 128MB DFA memory, 4x 32Mx9
+                                                         parts could be used to fill out TWO physical
+                                                         bunks (clamshell configuration). Each (of the
+                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
+                                                         Each RLDRAM device also contains 8 internal banks,
+                                                         therefore the memory Address is 16M/8banks = 2M
+                                                         addresses/bunk (2^21). In this case, MA[21] would
+                                                         select the physical bunk.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         be used to determine the Chip Select(s).
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
+                                                         "Redundant Bunk" scheme is employed to provide the
+                                                         highest overall performance (1 Req/ MCLK cycle).
+                                                         In this mode, it's imperative that SW set the PBUNK
+                                                         field +1 'above' the highest address bit. (such that
+                                                         the PBUNK extracted from the address will always be
+                                                         zero). In this mode, the CS_N[1:0] pins are driven
+                                                         to each redundant bunk based on a TDM scheme:
+                                                         [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
+        uint64_t blen                    : 1;       /**< Device Burst Length  (0=2-burst/1=4-burst)
+                                                         When BLEN=0(BL2), all QW reads/writes from CP2 are
+                                                         decomposed into 2 separate BL2(LW) requests to the
+                                                         Low-Latency memory.
+                                                         When BLEN=1(BL4), a LW request (from CP2 or NCB) is
+                                                         treated as 1 BL4(QW) request to the low latency memory.
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization before the DFA LLM
+                                                         (low latency memory) is used.
+                                                         NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
+                                                         NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
+                                                         multi-bunk(clam) board design.
+                                                         NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
+                                                         SW SHOULD use CP2 QW read/write requests (for
+                                                         optimal low-latency bus performance).
+                                                         [LW length read/write requests(in BL4 mode) use 50%
+                                                         of the available bus bandwidth]
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
+                                                         be used with FCRAM-II devices which support BL2 mode
+                                                         (see: Toshiba FCRAM-II, where DQ tristate after 2 data
+                                                         transfers).
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
+                                                         write requests (FCRAM-II+ device specification has removed
+                                                         the variable write mask function from the devices).
+                                                         As such, if this mode is used, SW must be careful to
+                                                         issue only PP-CP2 QW write requests. */
+        uint64_t bprch                   : 2;       /**< Tristate Enable (back porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t fprch                   : 2;       /**< Tristate Enable (front porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t wr_dly                  : 4;       /**< Write->Read CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from write to read. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
+                                                         For FCRAM-II (BL2 grepl>=2x): (TBL=3)
+                                                            NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
+                                                            grepl>=2x, writes require redundant bunk writes
+                                                            which require an additional 2 cycles before slotting
+                                                            the next read.
+                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
+                                                         on W->R transitions is not pronounced. */
+        uint64_t rw_dly                  : 4;       /**< Read->Write CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from read to write. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
+                                                         on R->W transitions is not pronounced. */
+        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#dclks): On reads, determines how many
+                                                         additional dclks to wait (on top of tRL+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t mtype                   : 1;       /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
+                                                         NOTE: N3K-P1 only supports RLDRAM-II
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
+                                                         "unidirectional DS/QS" mode is supported. (see FCRAM
+                                                         data sheet EMRS[A6:A5]=SS(Strobe Select) register
+                                                         definition. [in FCRAM 2-burst mode, we use FCRAM
+                                                         in a clamshell configuration such that clam0 is
+                                                         addressed independently of clam1, and DQ is shared
+                                                         for optimal performance. As such it's imperative that
+                                                         the QS are conditionally received (and are NOT
+                                                         free-running), as the N3K receive data capture silos
+                                                         OR the clam0/1 QS strobes.
+                                                         NOTE: If this bit is SET, the ASX0/1
+                                                         ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
+                                                         in order for the RLD0/1-PHY(s) to support FCRAM devices. */
+        uint64_t reserved_2_2            : 1;
+        uint64_t ena_p0                  : 1;       /**< Enable DFA RLDRAM Port#0
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#0.
+                                                         NOTE: For N3K-P1, to enable Port#0(2nd port),
+                                                         Port#1 MUST ALSO be enabled.
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+        uint64_t ena_p1                  : 1;       /**< Enable DFA RLDRAM Port#1
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#1.
+                                                         NOTE: For N3K-P1, If the customer wishes to use a
+                                                         single port, s/he must enable Port#1 (and not Port#0).
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+#else
+        uint64_t ena_p1                  : 1;
+        uint64_t ena_p0                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t mtype                   : 1;
+        uint64_t sil_lat                 : 2;
+        uint64_t rw_dly                  : 4;
+        uint64_t wr_dly                  : 4;
+        uint64_t fprch                   : 2;
+        uint64_t bprch                   : 2;
+        uint64_t blen                    : 1;
+        uint64_t pbunk                   : 3;
+        uint64_t r2r_pbunk               : 1;
+        uint64_t init_p1                 : 1;
+        uint64_t init_p0                 : 1;
+        uint64_t bunk_init               : 2;
+        uint64_t lpp_ena                 : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn38xx;
+    struct cvmx_dfa_memcfg0_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t bunk_init               : 2;       /**< Controls the CS_N[1:0] during a) a HW Initialization
+                                                         sequence (triggered by DFA_MEMCFG0[INIT_Px]) or
+                                                         b) during a normal refresh sequence. If
+                                                         the BNK_INIT[x]=1, the corresponding CS_N[x] is driven.
+                                                         NOTE: This is required for DRAM used in a
+                                                         clamshell configuration, since the address lines
+                                                         carry Mode Register write data that is unique
+                                                         per bunk(or clam). In a clamshell configuration,
+                                                         The N3K A[x] pin may be tied into Clam#0's A[x]
+                                                         and also into Clam#1's 'mirrored' address bit A[y]
+                                                         (eg: Clam0 sees A[5] and Clam1 sees A[15]).
+                                                         To support clamshell designs, SW must initiate
+                                                         two separate HW init sequences for the two bunks
+                                                         (or clams) . Before each HW init sequence is triggered,
+                                                         SW must preload the DFA_MEMRLD[22:0] with the data
+                                                         that will be driven onto the A[22:0] wires during
+                                                         an MRS mode register write.
+                                                         NOTE: After the final HW initialization sequence has
+                                                         been triggered, SW must wait 64K eclks before writing
+                                                         the BUNK_INIT[1:0] field = 3'b11 (so that CS_N[1:0] is
+                                                         driven during refresh sequences in normal operation.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For MTYPE=1(FCRAM) Mode, each bunk MUST BE
+                                                         initialized independently. In other words, a HW init
+                                                         must be done for Bunk#0, and then another HW init
+                                                         must be done for Bunk#1 at power-on. */
+        uint64_t init_p0                 : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#0 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+        uint64_t init_p1                 : 1;       /**< When a '1' is written (and the previous value was '0'),
+                                                         the HW init sequence(s) for Memory Port \#1 is
+                                                         initiated.
+                                                         NOTE: To initialize memory, SW must:
+                                                           1) Enable memory port(s):
+                                                               a) ENA_P1=1 (single port in pass 1) OR
+                                                               b) ENA_P0=1/ENA_P1=1 (dual ports or single when not pass 1)
+                                                           2) Wait 100us (to ensure a stable clock
+                                                              to the RLDRAMs) - as per RLDRAM spec.
+                                                           3) Write a '1' to the corresponding INIT_Px which
+                                                              will initiate a hardware initialization
+                                                              sequence.
+                                                         NOTE: After writing a '1', SW must wait 64K eclk
+                                                         cycles to ensure the HW init sequence has completed
+                                                         before writing to ANY of the DFA_MEM* registers.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+        uint64_t r2r_pbunk               : 1;       /**< When enabled, an additional command bubble is inserted
+                                                         if back to back reads are issued to different physical
+                                                         bunks. This is to avoid DQ data bus collisions when
+                                                         references cross between physical bunks.
+                                                         [NOTE: the physical bunk address boundary is determined
+                                                         by the PBUNK bit].
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         When MTYPE=1(FCRAM)/BLEN=0(2-burst), R2R_PBUNK SHOULD BE
+                                                         ZERO(for optimal performance). However, if electrically,
+                                                         DQ-sharing becomes a power/heat issue, then R2R_PBUNK
+                                                         should be set (but at a cost to performance (1/2 BW). */
+        uint64_t pbunk                   : 3;       /**< Physical Bunk address bit pointer.
+                                                         Specifies which address bit within the Longword
+                                                         Memory address MA[23:0] is used to determine the
+                                                         chip selects.
+                                                         [RLD_CS0_N corresponds to physical bunk \#0, and
+                                                         RLD_CS1_N corresponds to physical bunk \#1].
+                                                           - 000: CS0_N = MA[19]/CS1_N = !MA[19]
+                                                           - 001: CS0_N = MA[20]/CS1_N = !MA[20]
+                                                           - 010: CS0_N = MA[21]/CS1_N = !MA[21]
+                                                           - 011: CS0_N = MA[22]/CS1_N = !MA[22]
+                                                           - 100: CS0_N = MA[23]/CS1_N = !MA[23]
+                                                           - 101-111: CS0_N = 0 /CS1_N = 1
+                                                         Example(s):
+                                                         To build out a 128MB DFA memory, 4x 32Mx9
+                                                         parts could be used to fill out TWO physical
+                                                         bunks (clamshell configuration). Each (of the
+                                                         two) physical bunks contains 2x 32Mx9 = 16Mx36.
+                                                         Each RLDRAM device also contains 8 internal banks,
+                                                         therefore the memory Address is 16M/8banks = 2M
+                                                         addresses/bunk (2^21). In this case, MA[21] would
+                                                         select the physical bunk.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         be used to determine the Chip Select(s).
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), a
+                                                         "Redundant Bunk" scheme is employed to provide the
+                                                         highest overall performance (1 Req/ MCLK cycle).
+                                                         In this mode, it's imperative that SW set the PBUNK
+                                                         field +1 'above' the highest address bit. (such that
+                                                         the PBUNK extracted from the address will always be
+                                                         zero). In this mode, the CS_N[1:0] pins are driven
+                                                         to each redundant bunk based on a TDM scheme:
+                                                         [MCLK-EVEN=Bunk#0/MCLK-ODD=Bunk#1]. */
+        uint64_t blen                    : 1;       /**< Device Burst Length  (0=2-burst/1=4-burst)
+                                                         When BLEN=0(BL2), all QW reads/writes from CP2 are
+                                                         decomposed into 2 separate BL2(LW) requests to the
+                                                         Low-Latency memory.
+                                                         When BLEN=1(BL4), a LW request (from CP2 or NCB) is
+                                                         treated as 1 BL4(QW) request to the low latency memory.
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization before the DFA LLM
+                                                         (low latency memory) is used.
+                                                         NOTE: MTYPE=0(RLDRAM-II) MUST USE BLEN=0(2-burst)
+                                                         NOTE: MTYPE=1(FCRAM)/BLEN=0(BL2) requires a
+                                                         multi-bunk(clam) board design.
+                                                         NOTE: If MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=1(BL4),
+                                                         SW SHOULD use CP2 QW read/write requests (for
+                                                         optimal low-latency bus performance).
+                                                         [LW length read/write requests(in BL4 mode) use 50%
+                                                         of the available bus bandwidth]
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=0(II)/BLEN=0(BL2) can only
+                                                         be used with FCRAM-II devices which support BL2 mode
+                                                         (see: Toshiba FCRAM-II, where DQ tristate after 2 data
+                                                         transfers).
+                                                         NOTE: MTYPE=1(FCRAM)/FCRAM2P=1(II+) does not support LW
+                                                         write requests (FCRAM-II+ device specification has removed
+                                                         the variable write mask function from the devices).
+                                                         As such, if this mode is used, SW must be careful to
+                                                         issue only PP-CP2 QW write requests. */
+        uint64_t bprch                   : 2;       /**< Tristate Enable (back porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable back porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t fprch                   : 2;       /**< Tristate Enable (front porch) (\#dclks)
+                                                         On reads, allows user to control the shape of the
+                                                         tristate disable front porch for the DQ data bus.
+                                                         This parameter is also very dependent on the
+                                                         RW_DLY and WR_DLY parameters and care must be
+                                                         taken when programming these parameters to avoid
+                                                         data bus contention. Valid range [0..2]
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t wr_dly                  : 4;       /**< Write->Read CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from write to read. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II(BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         For FCRAM-II (BL2 grepl=1x ONLY): (TBL=1)
+                                                         For FCRAM-II (BL2 grepl>=2x): (TBL=3)
+                                                            NOTE: When MTYTPE=1(FCRAM-II) BLEN=0(BL2 Mode),
+                                                            grepl>=2x, writes require redundant bunk writes
+                                                            which require an additional 2 cycles before slotting
+                                                            the next read.
+                                                         WR_DLY = ROUND_UP[((TWL+TBL)*2 - TSKW + FPRCH) / 2] - TRL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the WR_DLY 'may' be tuned down(-1) if bus fight
+                                                         on W->R transitions is not pronounced. */
+        uint64_t rw_dly                  : 4;       /**< Read->Write CMD Delay (\#mclks):
+                                                         Determines \#mclk cycles to insert when controller
+                                                         switches from read to write. This allows programmer
+                                                         to control the data bus contention.
+                                                         For RLDRAM-II/FCRAM-II (BL2): (TBL=1)
+                                                         For FCRAM-II (BL4): (TBL=2)
+                                                         RW_DLY = ROUND_UP[((TRL+TBL)*2 + TSKW + BPRCH+2)/2] - TWL + 1
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: For aggressive(performance optimal) designs,
+                                                         the RW_DLY 'may' be tuned down(-1) if bus fight
+                                                         on R->W transitions is not pronounced. */
+        uint64_t sil_lat                 : 2;       /**< Silo Latency (\#dclks): On reads, determines how many
+                                                         additional dclks to wait (on top of tRL+1) before
+                                                         pulling data out of the padring silos used for time
+                                                         domain boundary crossing.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t mtype                   : 1;       /**< Memory Type (0=RLDRAM-II/1=Network DRAM-II/FCRAM)
+                                                         NOTE: N3K-P1 only supports RLDRAM-II
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: When MTYPE=1(FCRAM)/BLEN=0(2-burst), only the
+                                                         "unidirectional DS/QS" mode is supported. (see FCRAM
+                                                         data sheet EMRS[A6:A5]=SS(Strobe Select) register
+                                                         definition. [in FCRAM 2-burst mode, we use FCRAM
+                                                         in a clamshell configuration such that clam0 is
+                                                         addressed independently of clam1, and DQ is shared
+                                                         for optimal performance. As such it's imperative that
+                                                         the QS are conditionally received (and are NOT
+                                                         free-running), as the N3K receive data capture silos
+                                                         OR the clam0/1 QS strobes.
+                                                         NOTE: If this bit is SET, the ASX0/1
+                                                         ASX_RLD_FCRAM_MODE[MODE] bit(s) should also be SET
+                                                         in order for the RLD0/1-PHY(s) to support FCRAM devices. */
+        uint64_t reserved_2_2            : 1;
+        uint64_t ena_p0                  : 1;       /**< Enable DFA RLDRAM Port#0
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#0.
+                                                         NOTE: For N3K-P1, to enable Port#0(2nd port),
+                                                         Port#1 MUST ALSO be enabled.
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#0 corresponds to the Octeon
+                                                         RLD0_* pins. */
+        uint64_t ena_p1                  : 1;       /**< Enable DFA RLDRAM Port#1
+                                                         When enabled, this bit lets N3K be the default
+                                                         driver for memory port \#1.
+                                                         NOTE: For N3K-P1, If the customer wishes to use a
+                                                         single port, s/he must enable Port#1 (and not Port#0).
+                                                         NOTE: For N3K-P2, single port mode, a customer is at
+                                                         liberty to enable either Port#0 or Port#1.
+                                                         NOTE: Once a port has been disabled, it MUST NEVER
+                                                         be re-enabled. [the only way to enable a port is
+                                                         through a chip reset].
+                                                         NOTE: DFA Memory Port#1 corresponds to the Octeon
+                                                         RLD1_* pins. */
+#else
+        uint64_t ena_p1                  : 1;
+        uint64_t ena_p0                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t mtype                   : 1;
+        uint64_t sil_lat                 : 2;
+        uint64_t rw_dly                  : 4;
+        uint64_t wr_dly                  : 4;
+        uint64_t fprch                   : 2;
+        uint64_t bprch                   : 2;
+        uint64_t blen                    : 1;
+        uint64_t pbunk                   : 3;
+        uint64_t r2r_pbunk               : 1;
+        uint64_t init_p1                 : 1;
+        uint64_t init_p0                 : 1;
+        uint64_t bunk_init               : 2;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn38xxp2;
+    struct cvmx_dfa_memcfg0_s            cn58xx;
+    struct cvmx_dfa_memcfg0_s            cn58xxp1;
+} cvmx_dfa_memcfg0_t;
+
+
+/**
+ * cvmx_dfa_memcfg1
+ *
+ * DFA_MEMCFG1 = RLDRAM Memory Timing Configuration
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_memcfg1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ref_intlo               : 9;       /**< Burst Refresh Interval[8:0] (\#dclks)
+                                                         For finer refresh interval granularity control.
+                                                         This field provides an additional level of granularity
+                                                         for the refresh interval. It specifies the additional
+                                                         \#dclks [0...511] to be added to the REF_INT[3:0] field.
+                                                         For RLDRAM-II: For dclk(400MHz=2.5ns):
+                                                         Example: 64K AREF cycles required within tREF=32ms
+                                                             trefint = tREF(ms)/(64K cycles/8banks)
+                                                                         = 32ms/8K = 3.9us = 3900ns
+                                                             REF_INT[3:0] = ROUND_DOWN[(trefint/dclk)/512]
+                                                                          = ROUND_DOWN[(3900/2.5)/512]
+                                                                          = 3
+                                                             REF_INTLO[8:0] = MOD[(trefint/dclk)/512]
+                                                                            = MOD[(3900/2.5)/512]
+                                                                            = 24
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t aref_ena                : 1;       /**< Auto Refresh Cycle Enable
+                                                         INTERNAL USE ONLY:
+                                                         NOTE: This mode bit is ONLY intended to be used by
+                                                         low-level power-on initialization routines in the
+                                                         event that the hardware initialization routine
+                                                         does not work. It allows SW to create AREF
+                                                         commands on the RLDRAM bus directly.
+                                                         When this bit is set, ALL RLDRAM writes (issued by
+                                                         a PP through the NCB or CP2) are converted to AREF
+                                                         commands on the RLDRAM bus. The write-address is
+                                                         presented on the A[20:0]/BA[2:0] pins (for which
+                                                         the RLDRAM only interprets BA[2:0]).
+                                                         When this bit is set, only writes are allowed
+                                                         and MUST use grepl=0 (1x).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: MRS_ENA and AREF_ENA are mutually exclusive
+                                                         (SW can set one or the other, but never both!)
+                                                         NOTE: AREF commands generated using this method target
+                                                         the 'addressed' bunk. */
+        uint64_t mrs_ena                 : 1;       /**< Mode Register Set Cycle Enable
+                                                         INTERNAL USE ONLY:
+                                                         NOTE: This mode bit is ONLY intended to be used by
+                                                         low-level power-on initialization routines in the
+                                                         event that the hardware initialization routine
+                                                         does not work. It allows SW to create MRS
+                                                         commands on the RLDRAM bus directly.
+                                                         When this bit is set, ALL RLDRAM writes (issued by
+                                                         a PP through the NCB or CP2) are converted to MRS
+                                                         commands on the RLDRAM bus. The write-address is
+                                                         presented on the A[20:0]/BA[2:0] pins (for which
+                                                         the RLDRAM only interprets A[17:0]).
+                                                         When this bit is set, only writes are allowed
+                                                         and MUST use grepl=0 (1x).
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization.
+                                                         NOTE: MRS_ENA and AREF_ENA are mutually exclusive
+                                                         (SW can set one or the other, but never both!)
+                                                         NOTE: MRS commands generated using this method target
+                                                         the 'addressed' bunk. */
+        uint64_t tmrsc                   : 3;       /**< Mode Register Set Cycle Time (represented in \#mclks)
+                                                              - 000-001: RESERVED
+                                                              - 010: tMRSC = 2 mclks
+                                                              - 011: tMRSC = 3 mclks
+                                                              - ...
+                                                              - 111: tMRSC = 7 mclks
+                                                         NOTE: The device tMRSC parameter is a function of CL
+                                                         (which during HW initialization is not known. Its
+                                                         recommended to load tMRSC(MAX) value to avoid timing
+                                                         violations.
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t trc                     : 4;       /**< Row Cycle Time (represented in \#mclks)
+                                                         see also: DFA_MEMRLD[RLCFG] field which must
+                                                         correspond with tRL/tWL parameter(s).
+                                                              - 0000-0010: RESERVED
+                                                              - 0011: tRC = 3 mclks
+                                                              - 0100: tRC = 4 mclks
+                                                              - 0101: tRC = 5 mclks
+                                                              - 0110: tRC = 6 mclks
+                                                              - 0111: tRC = 7 mclks
+                                                              - 1000: tRC = 8 mclks
+                                                              - 1001: tRC = 9 mclks
+                                                              - 1010-1111: RESERVED
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t twl                     : 4;       /**< Write Latency (represented in \#mclks)
+                                                         see also: DFA_MEMRLD[RLCFG] field which must
+                                                         correspond with tRL/tWL parameter(s).
+                                                              - 0000-0001: RESERVED
+                                                              - 0010: Write Latency (WL=2.0 mclk)
+                                                              - 0011: Write Latency (WL=3.0 mclks)
+                                                              - 0100: Write Latency (WL=4.0 mclks)
+                                                              - 0101: Write Latency (WL=5.0 mclks)
+                                                              - 0110: Write Latency (WL=6.0 mclks)
+                                                              - 0111: Write Latency (WL=7.0 mclks)
+                                                              - 1000: Write Latency (WL=8.0 mclks)
+                                                              - 1001: Write Latency (WL=9.0 mclks)
+                                                              - 1010: Write Latency (WL=10.0 mclks)
+                                                              - 1011-1111: RESERVED
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t trl                     : 4;       /**< Read Latency (represented in \#mclks)
+                                                         see also: DFA_MEMRLD[RLCFG] field which must
+                                                         correspond with tRL/tWL parameter(s).
+                                                              - 0000-0010: RESERVED
+                                                              - 0011: Read Latency = 3 mclks
+                                                              - 0100: Read Latency = 4 mclks
+                                                              - 0101: Read Latency = 5 mclks
+                                                              - 0110: Read Latency = 6 mclks
+                                                              - 0111: Read Latency = 7 mclks
+                                                              - 1000: Read Latency = 8 mclks
+                                                              - 1001: Read Latency = 9 mclks
+                                                              - 1010: Read Latency = 10 mclks
+                                                              - 1011-1111: RESERVED
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t reserved_6_7            : 2;
+        uint64_t tskw                    : 2;       /**< Board Skew (represented in \#dclks)
+                                                         Represents additional board skew of DQ/DQS.
+                                                             - 00: board-skew = 0 dclk
+                                                             - 01: board-skew = 1 dclk
+                                                             - 10: board-skew = 2 dclk
+                                                             - 11: board-skew = 3 dclk
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t ref_int                 : 4;       /**< Refresh Interval (represented in \#of 512 dclk
+                                                         increments).
+                                                              - 0000: RESERVED
+                                                              - 0001: 1 * 512  = 512 dclks
+                                                              - ...
+                                                              - 1111: 15 * 512 = 7680 dclks
+                                                         NOTE: For finer level of granularity, refer to
+                                                         REF_INTLO[8:0] field.
+                                                         For RLDRAM-II, each refresh interval will
+                                                         generate a burst of 8 AREF commands, one to each of
+                                                         8 explicit banks (referenced using the RLD_BA[2:0]
+                                                         pins.
+                                                         Example: For mclk=200MHz/dclk(400MHz=2.5ns):
+                                                           64K AREF cycles required within tREF=32ms
+                                                             trefint = tREF(ms)/(64K cycles/8banks)
+                                                                     = 32ms/8K = 3.9us = 3900ns
+                                                             REF_INT = ROUND_DOWN[(trefint/dclk)/512]
+                                                                     = ROUND_DOWN[(3900/2.5)/512]
+                                                                     = 3
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+        uint64_t ref_int                 : 4;
+        uint64_t tskw                    : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t trl                     : 4;
+        uint64_t twl                     : 4;
+        uint64_t trc                     : 4;
+        uint64_t tmrsc                   : 3;
+        uint64_t mrs_ena                 : 1;
+        uint64_t aref_ena                : 1;
+        uint64_t ref_intlo               : 9;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_dfa_memcfg1_s            cn38xx;
+    struct cvmx_dfa_memcfg1_s            cn38xxp2;
+    struct cvmx_dfa_memcfg1_s            cn58xx;
+    struct cvmx_dfa_memcfg1_s            cn58xxp1;
+} cvmx_dfa_memcfg1_t;
+
+
+/**
+ * cvmx_dfa_memcfg2
+ *
+ * DFA_MEMCFG2 = DFA Memory Config Register \#2
+ * *** NOTE: Pass2 Addition
+ * 
+ * Description: Additional Memory Configuration CSRs to support FCRAM-II/II+ and Network DRAM-II
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_memcfg2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t dteclkdis               : 1;       /**< DFA DTE Clock Disable
+                                                         When SET, the DFA clocks for DTE(thread engine)
+                                                         operation are disabled.
+                                                         NOTE: When SET, SW MUST NEVER issue ANY operations to
+                                                         the DFA via the NCB Bus. All DFA Operations must be
+                                                         issued solely through the CP2 interface.
+                                                         *** NOTE: PASS2 Addition
+                                                         NOTE: When DTECLKDIS=1, if CP2 Errors are encountered
+                                                         (ie: CP2SBE, CP2DBE, CP2PERR), the DFA_MEMFADR CSR
+                                                         does not reflect the failing address/ctl information. */
+        uint64_t silrst                  : 1;       /**< LLM-PHY Silo Reset
+                                                         When a '1' is written (when the previous
+                                                         value was a '0') causes the the LLM-PHY Silo read/write
+                                                         pointers to be reset.
+                                                         NOTE: SW MUST WAIT 400 dclks after the LAST HW Init
+                                                         sequence was launched (ie: INIT_START 0->1 CSR write),
+                                                         before the SILRST can be triggered (0->1). */
+        uint64_t trfc                    : 5;       /**< FCRAM-II Refresh Interval
+                                                         *** O9N UNSUPPORTED *** */
+        uint64_t refshort                : 1;       /**< FCRAM Short Refresh Mode
+                                                         *** O9N UNSUPPORTED *** */
+        uint64_t ua_start                : 2;       /**< FCRAM-II Upper Addres Start
+                                                         *** O9N UNSUPPORTED *** */
+        uint64_t maxbnk                  : 1;       /**< Maximum Banks per-device (used by the address mapper
+                                                         when extracting address bits for the memory bank#.
+                                                           - 0: 4 banks/device
+                                                           - 1: 8 banks/device
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t fcram2p                 : 1;       /**< FCRAM-II+ Mode Enable
+                                                         *** O9N UNSUPPORTED *** */
+#else
+        uint64_t fcram2p                 : 1;
+        uint64_t maxbnk                  : 1;
+        uint64_t ua_start                : 2;
+        uint64_t refshort                : 1;
+        uint64_t trfc                    : 5;
+        uint64_t silrst                  : 1;
+        uint64_t dteclkdis               : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_dfa_memcfg2_s            cn38xx;
+    struct cvmx_dfa_memcfg2_s            cn38xxp2;
+    struct cvmx_dfa_memcfg2_s            cn58xx;
+    struct cvmx_dfa_memcfg2_s            cn58xxp1;
+} cvmx_dfa_memcfg2_t;
+
+
+/**
+ * cvmx_dfa_memfadr
+ *
+ * DFA_MEMFADR = RLDRAM Failing Address/Control Register
+ * 
+ * Description: DFA Memory Failing Address/Control Error Capture information
+ * This register contains useful information to help in isolating an RLDRAM memory failure.
+ * NOTE: The first detected SEC/DED/PERR failure is captured in DFA_MEMFADR, however, a DED or PERR (which is
+ * more severe) will always overwrite a SEC error. The user can 'infer' the source of the interrupt
+ * via the FSRC field.
+ * NOTE: If DFA_MEMCFG2[DTECLKDIS]=1, the contents of this register are UNDEFINED.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_memfadr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t maddr                   : 24;      /**< Memory Address */
+#else
+        uint64_t maddr                   : 24;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_dfa_memfadr_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t fdst                    : 9;       /**< Fill-Destination
+                                                            FSRC[1:0]    | FDST[8:0]
+                                                            -------------+-------------------------------------
+                                                             0(NCB-DTE)  | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
+                                                             1(NCB-CSR)  | [ncbSRC[8:0]]
+                                                             3(CP2-PP)   | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
+                                                           where:
+                                                               DTE: DFA Thread Engine ID#
+                                                               PP: Packet Processor ID#
+                                                               FID: Fill-ID# (unique per PP)
+                                                               WIDX:  16b SIMPLE Mode (index)
+                                                               DMODE: (0=16b SIMPLE/1=32b SIMPLE)
+                                                               SIZE: (0=LW Mode access/1=QW Mode Access)
+                                                               INDEX: (0=Low LW/1=High LW)
+                                                         NOTE: QW refers to a 56/64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 32-bit load/store. */
+        uint64_t fsrc                    : 2;       /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
+        uint64_t pnum                    : 1;       /**< Memory Port
+                                                         NOTE: For O2P, this bit will always return zero. */
+        uint64_t bnum                    : 3;       /**< Memory Bank
+                                                         When DFA_DDR2_ADDR[RNK_LO]=1, BNUM[2]=RANK[0].
+                                                         (RANK[1] can be inferred from MADDR[24:0]) */
+        uint64_t maddr                   : 25;      /**< Memory Address */
+#else
+        uint64_t maddr                   : 25;
+        uint64_t bnum                    : 3;
+        uint64_t pnum                    : 1;
+        uint64_t fsrc                    : 2;
+        uint64_t fdst                    : 9;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } cn31xx;
+    struct cvmx_dfa_memfadr_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t fdst                    : 9;       /**< Fill-Destination
+                                                            FSRC[1:0]    | FDST[8:0]
+                                                            -------------+-------------------------------------
+                                                             0(NCB-DTE)  | [fillstart,2'b0,WIDX(1),DMODE(1),DTE(4)]
+                                                             1(NCB-CSR)  | [ncbSRC[8:0]]
+                                                             3(CP2-PP)   | [2'b0,SIZE(1),INDEX(1),PP(4),FID(1)]
+                                                           where:
+                                                               DTE: DFA Thread Engine ID#
+                                                               PP: Packet Processor ID#
+                                                               FID: Fill-ID# (unique per PP)
+                                                               WIDX:  18b SIMPLE Mode (index)
+                                                               DMODE: (0=18b SIMPLE/1=36b SIMPLE)
+                                                               SIZE: (0=LW Mode access/1=QW Mode Access)
+                                                               INDEX: (0=Low LW/1=High LW)
+                                                         NOTE: QW refers to a 64-bit LLM Load/Store (intiated
+                                                         by a processor core). LW refers to a 36-bit load/store. */
+        uint64_t fsrc                    : 2;       /**< Fill-Source (0=NCB-DTE/1=NCB-CSR/2=RESERVED/3=PP-CP2) */
+        uint64_t pnum                    : 1;       /**< Memory Port
+                                                         NOTE: the port id's are reversed
+                                                            PNUM==0 => port#1
+                                                            PNUM==1 => port#0 */
+        uint64_t bnum                    : 3;       /**< Memory Bank */
+        uint64_t maddr                   : 24;      /**< Memory Address */
+#else
+        uint64_t maddr                   : 24;
+        uint64_t bnum                    : 3;
+        uint64_t pnum                    : 1;
+        uint64_t fsrc                    : 2;
+        uint64_t fdst                    : 9;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } cn38xx;
+    struct cvmx_dfa_memfadr_cn38xx       cn38xxp2;
+    struct cvmx_dfa_memfadr_cn38xx       cn58xx;
+    struct cvmx_dfa_memfadr_cn38xx       cn58xxp1;
+} cvmx_dfa_memfadr_t;
+
+
+/**
+ * cvmx_dfa_memfcr
+ *
+ * DFA_MEMFCR = FCRAM MRS Register(s) EMRS2[14:0], EMRS1[14:0], MRS[14:0]
+ * *** O9N UNSUPPORTED ***
+ *
+ * Notes:
+ * For FCRAM-II please consult your device's data sheet for further details:
+ * MRS Definition:
+ *    A[13:8]=0   RESERVED
+ *    A[7]=0      TEST MODE     (N3K requires test mode 0:"disabled")
+ *    A[6:4]      CAS LATENCY   (fully programmable - SW must ensure that the value programmed
+ *                               into DFA_MEM_CFG0[TRL] corresponds with this value).
+ *    A[3]=0      BURST TYPE    (N3K requires 0:"Sequential" Burst Type)
+ *    A[2:0]      BURST LENGTH  Burst Length [1:BL2/2:BL4] (N3K only supports BL=2,4)
+ * 
+ *                                  In BL2 mode(for highest performance), only 1/2 the phsyical
+ *                                  memory is unique (ie: each bunk stores the same information).
+ *                                  In BL4 mode(highest capacity), all of the physical memory
+ *                                  is unique (ie: each bunk is uniquely addressable).
+ * EMRS Definition:
+ *    A[13:12]    REFRESH MODE  (N3K Supports only 0:"Conventional" and 1:"Short" auto-refresh modes)
+ * 
+ *                              (SW must ensure that the value programmed into DFA_MEMCFG2[REFSHORT]
+ *                              is also reflected in the Refresh Mode encoding).
+ *    A[11:7]=0   RESERVED
+ *    A[6:5]=2    STROBE SELECT (N3K supports only 2:"Unidirectional DS/QS" mode - the read capture
+ *                              silos rely on a conditional QS strobe)
+ *    A[4:3]      DIC(QS)       QS Drive Strength: fully programmable (consult your FCRAM-II data sheet)
+ *                                [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
+ *    A[2:1]      DIC(DQ)       DQ Drive Strength: fully programmable (consult your FCRAM-II data sheet)
+ *                                [0: Normal Output Drive/1: Strong Output Drive/2: Weak output Drive]
+ *    A[0]        DLL           DLL Enable: Programmable [0:DLL Enable/1: DLL Disable]
+ * 
+ * EMRS2 Definition: (for FCRAM-II+)
+ *    A[13:11]=0                RESERVED
+ *    A[10:8]     ODTDS         On Die Termination (DS+/-)
+ *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
+ *    A[7:6]=0    MBW           Multi-Bank Write: (N3K requires use of 0:"single bank" mode only)
+ *    A[5:3]      ODTin         On Die Termination (input pin)
+ *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
+ *    A[2:0]      ODTDQ         On Die Termination (DQ)
+ *                                 [0: ODT Disable /1: 15ohm termination /(2-7): RESERVED]
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_memfcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_47_63          : 17;
+        uint64_t emrs2                   : 15;      /**< Memory Address[14:0] during EMRS2(for FCRAM-II+)
+                                                         *** O9N UNSUPPORTED *** */
+        uint64_t reserved_31_31          : 1;
+        uint64_t emrs                    : 15;      /**< Memory Address[14:0] during EMRS
+                                                         *** O9N UNSUPPORTED ***
+                                                           A[0]=1: DLL Enabled) */
+        uint64_t reserved_15_15          : 1;
+        uint64_t mrs                     : 15;      /**< FCRAM Memory Address[14:0] during MRS
+                                                         *** O9N UNSUPPORTED ***
+                                                           A[6:4]=4  CAS LATENCY=4(default)
+                                                           A[3]=0    Burst Type(must be 0:Sequential)
+                                                           A[2:0]=2  Burst Length=4(default) */
+#else
+        uint64_t mrs                     : 15;
+        uint64_t reserved_15_15          : 1;
+        uint64_t emrs                    : 15;
+        uint64_t reserved_31_31          : 1;
+        uint64_t emrs2                   : 15;
+        uint64_t reserved_47_63          : 17;
+#endif
+    } s;
+    struct cvmx_dfa_memfcr_s             cn38xx;
+    struct cvmx_dfa_memfcr_s             cn38xxp2;
+    struct cvmx_dfa_memfcr_s             cn58xx;
+    struct cvmx_dfa_memfcr_s             cn58xxp1;
+} cvmx_dfa_memfcr_t;
+
+
+/**
+ * cvmx_dfa_memrld
+ *
+ * DFA_MEMRLD = DFA RLDRAM MRS Register Values
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_memrld_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t mrsdat                  : 23;      /**< This field represents the data driven onto the
+                                                         A[22:0] address lines during MRS(Mode Register Set)
+                                                         commands (during a HW init sequence). This field
+                                                         corresponds with the Mode Register Bit Map from
+                                                         your RLDRAM-II device specific data sheet.
+                                                            A[17:10]: RESERVED
+                                                            A[9]:     ODT (on die termination)
+                                                            A[8]:     Impedance Matching
+                                                            A[7]:     DLL Reset
+                                                            A[6]:     UNUSED
+                                                            A[5]:     Address Mux  (for N3K: MUST BE ZERO)
+                                                            A[4:3]:   Burst Length (for N3K: MUST BE ZERO)
+                                                            A[2:0]:   Configuration (see data sheet for
+                                                                      specific RLDRAM-II device).
+                                                               - 000-001: CFG=1 [tRC=4/tRL=4/tWL=5]
+                                                               - 010:     CFG=2 [tRC=6/tRL=6/tWL=7]
+                                                               - 011:     CFG=3 [tRC=8/tRL=8/tWL=9]
+                                                               - 100-111: RESERVED
+                                                          NOTE: For additional density, the RLDRAM-II parts
+                                                          can be 'clamshelled' (ie: two devices mounted on
+                                                          different sides of the PCB board), since the BGA
+                                                          pinout supports 'mirroring'.
+                                                          To support a clamshell design, SW must preload
+                                                          the MRSDAT[22:0] with the proper A[22:0] pin mapping
+                                                          which is dependent on the 'selected' bunk/clam
+                                                          (see also: DFA_MEMCFG0[BUNK_INIT] field).
+                                                          NOTE: Care MUST BE TAKEN NOT to write to this register
+                                                          within 64K eclk cycles of a HW INIT (see: INIT_P0/INIT_P1).
+                                                          NOTE: This should only be written to a different value
+                                                          during power-on SW initialization. */
+#else
+        uint64_t mrsdat                  : 23;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_dfa_memrld_s             cn38xx;
+    struct cvmx_dfa_memrld_s             cn38xxp2;
+    struct cvmx_dfa_memrld_s             cn58xx;
+    struct cvmx_dfa_memrld_s             cn58xxp1;
+} cvmx_dfa_memrld_t;
+
+
+/**
+ * cvmx_dfa_ncbctl
+ *
+ * DFA_NCBCTL = DFA NCB CTL Register
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_ncbctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t sbdnum                  : 5;       /**< SBD Debug Entry#
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         Selects which one of 32 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+        uint64_t sbdlck                  : 1;       /**< DFA Scoreboard LOCK Strobe
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+        uint64_t dcmode                  : 1;       /**< DRF-CRQ/DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t dtmode                  : 1;       /**< DRF-DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t pmode                   : 1;       /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t qmode                   : 1;       /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t imode                   : 1;       /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+        uint64_t imode                   : 1;
+        uint64_t qmode                   : 1;
+        uint64_t pmode                   : 1;
+        uint64_t dtmode                  : 1;
+        uint64_t dcmode                  : 1;
+        uint64_t sbdlck                  : 1;
+        uint64_t sbdnum                  : 5;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_dfa_ncbctl_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t sbdnum                  : 4;       /**< SBD Debug Entry#
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         Selects which one of 16 DFA Scoreboard entries is
+                                                         latched into the DFA_SBD_DBG[0-3] registers. */
+        uint64_t sbdlck                  : 1;       /**< DFA Scoreboard LOCK Strobe
+                                                         For internal use only. (DFA Scoreboard debug)
+                                                         When written with a '1', the DFA Scoreboard Debug
+                                                         registers (DFA_SBD_DBG[0-3]) are all locked down.
+                                                         This allows SW to lock down the contents of the entire
+                                                         SBD for a single instant in time. All subsequent reads
+                                                         of the DFA scoreboard registers will return the data
+                                                         from that instant in time. */
+        uint64_t dcmode                  : 1;       /**< DRF-CRQ/DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=CRQ/HP=DTE],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t dtmode                  : 1;       /**< DRF-DTE Arbiter Mode
+                                                         DTE-DRF Arbiter (0=FP [LP=DTE[15],...,HP=DTE[0]],1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t pmode                   : 1;       /**< NCB-NRP Arbiter Mode
+                                                         (0=Fixed Priority [LP=WQF,DFF,HP=RGF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t qmode                   : 1;       /**< NCB-NRQ Arbiter Mode
+                                                         (0=Fixed Priority [LP=IRF,RWF,PRF,HP=GRF]/1=RR
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+        uint64_t imode                   : 1;       /**< NCB-Inbound Arbiter
+                                                         (0=FP [LP=NRQ,HP=NRP], 1=RR)
+                                                         NOTE: This should only be written to a different value
+                                                         during power-on SW initialization. */
+#else
+        uint64_t imode                   : 1;
+        uint64_t qmode                   : 1;
+        uint64_t pmode                   : 1;
+        uint64_t dtmode                  : 1;
+        uint64_t dcmode                  : 1;
+        uint64_t sbdlck                  : 1;
+        uint64_t sbdnum                  : 4;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn38xx;
+    struct cvmx_dfa_ncbctl_cn38xx        cn38xxp2;
+    struct cvmx_dfa_ncbctl_s             cn58xx;
+    struct cvmx_dfa_ncbctl_s             cn58xxp1;
+} cvmx_dfa_ncbctl_t;
+
+
+/**
+ * cvmx_dfa_rodt_comp_ctl
+ *
+ * DFA_RODT_COMP_CTL = DFA RLD Compensation control (For read "on die termination")
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_rodt_comp_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t enable                  : 1;       /**< Read On Die Termination Enable
+                                                         (0=disable, 1=enable) */
+        uint64_t reserved_12_15          : 4;
+        uint64_t nctl                    : 4;       /**< Compensation control bits */
+        uint64_t reserved_5_7            : 3;
+        uint64_t pctl                    : 5;       /**< Compensation control bits */
+#else
+        uint64_t pctl                    : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t nctl                    : 4;
+        uint64_t reserved_12_15          : 4;
+        uint64_t enable                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_dfa_rodt_comp_ctl_s      cn58xx;
+    struct cvmx_dfa_rodt_comp_ctl_s      cn58xxp1;
+} cvmx_dfa_rodt_comp_ctl_t;
+
+
+/**
+ * cvmx_dfa_sbd_dbg0
+ *
+ * DFA_SBD_DBG0 = DFA Scoreboard Debug \#0 Register
+ * 
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_sbd_dbg0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t sbd0                    : 64;      /**< DFA ScoreBoard \#0 Data
+                                                         For internal use only! (DFA Scoreboard Debug)
+                                                         [63:40] rptr[26:3]: Result Base Pointer
+                                                         [39:24] rwcnt[15:0] Cumulative Result Write Counter
+                                                         [23]    lastgrdrsp: Last Gather-Rd Response
+                                                         [22]    wtgrdrsp: Waiting Gather-Rd Response
+                                                         [21]    wtgrdreq: Waiting for Gather-Rd Issue
+                                                         [20]    glvld: GLPTR/GLCNT Valid
+                                                         [19]    cmpmark: Completion Marked Node Detected
+                                                         [18:17] cmpcode[1:0]: Completion Code
+                                                                       [0=PDGONE/1=PERR/2=RFULL/3=TERM]
+                                                         [16]    cmpdet: Completion Detected
+                                                         [15]    wthdrwrcmtrsp: Waiting for HDR RWrCmtRsp
+                                                         [14]    wtlastwrcmtrsp: Waiting for LAST RESULT
+                                                                       RWrCmtRsp
+                                                         [13]    hdrwrreq: Waiting for HDR RWrReq
+                                                         [12]    wtrwrreq: Waiting for RWrReq
+                                                         [11]    wtwqwrreq: Waiting for WQWrReq issue
+                                                         [10]    lastprdrspeot: Last Packet-Rd Response
+                                                         [9]     lastprdrsp: Last Packet-Rd Response
+                                                         [8]     wtprdrsp:  Waiting for PRdRsp EOT
+                                                         [7]     wtprdreq: Waiting for PRdReq Issue
+                                                         [6]     lastpdvld: PDPTR/PDLEN Valid
+                                                         [5]     pdvld: Packet Data Valid
+                                                         [4]     wqvld: WQVLD
+                                                         [3]     wqdone: WorkQueue Done condition
+                                                                       a) WQWrReq issued(for WQPTR<>0) OR
+                                                                       b) HDR RWrCmtRsp completed)
+                                                         [2]     rwstf: Resultant write STF/P Mode
+                                                         [1]     pdldt: Packet-Data LDT mode
+                                                         [0]     gmode: Gather-Mode */
+#else
+        uint64_t sbd0                    : 64;
+#endif
+    } s;
+    struct cvmx_dfa_sbd_dbg0_s           cn31xx;
+    struct cvmx_dfa_sbd_dbg0_s           cn38xx;
+    struct cvmx_dfa_sbd_dbg0_s           cn38xxp2;
+    struct cvmx_dfa_sbd_dbg0_s           cn58xx;
+    struct cvmx_dfa_sbd_dbg0_s           cn58xxp1;
+} cvmx_dfa_sbd_dbg0_t;
+
+
+/**
+ * cvmx_dfa_sbd_dbg1
+ *
+ * DFA_SBD_DBG1 = DFA Scoreboard Debug \#1 Register
+ * 
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_sbd_dbg1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t sbd1                    : 64;      /**< DFA ScoreBoard \#1 Data
+                                                         For internal use only! (DFA Scoreboard Debug)
+                                                         [63:61] wqptr[35:33]: Work Queue Pointer
+                                                         [60:52] rptr[35:27]: Result Base Pointer
+                                                         [51:16] pdptr[35:0]: Packet Data Pointer
+                                                         [15:0]  pdcnt[15:0]: Packet Data Counter */
+#else
+        uint64_t sbd1                    : 64;
+#endif
+    } s;
+    struct cvmx_dfa_sbd_dbg1_s           cn31xx;
+    struct cvmx_dfa_sbd_dbg1_s           cn38xx;
+    struct cvmx_dfa_sbd_dbg1_s           cn38xxp2;
+    struct cvmx_dfa_sbd_dbg1_s           cn58xx;
+    struct cvmx_dfa_sbd_dbg1_s           cn58xxp1;
+} cvmx_dfa_sbd_dbg1_t;
+
+
+/**
+ * cvmx_dfa_sbd_dbg2
+ *
+ * DFA_SBD_DBG2 = DFA Scoreboard Debug \#2 Register
+ * 
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_sbd_dbg2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t sbd2                    : 64;      /**< DFA ScoreBoard \#2 Data
+                                                         [63:49] wqptr[17:3]: Work Queue Pointer
+                                                         [48:16] rwptr[35:3]: Result Write Pointer
+                                                         [15:0]  prwcnt[15:0]: Pending Result Write Counter */
+#else
+        uint64_t sbd2                    : 64;
+#endif
+    } s;
+    struct cvmx_dfa_sbd_dbg2_s           cn31xx;
+    struct cvmx_dfa_sbd_dbg2_s           cn38xx;
+    struct cvmx_dfa_sbd_dbg2_s           cn38xxp2;
+    struct cvmx_dfa_sbd_dbg2_s           cn58xx;
+    struct cvmx_dfa_sbd_dbg2_s           cn58xxp1;
+} cvmx_dfa_sbd_dbg2_t;
+
+
+/**
+ * cvmx_dfa_sbd_dbg3
+ *
+ * DFA_SBD_DBG3 = DFA Scoreboard Debug \#3 Register
+ * 
+ * Description: When the DFA_NCBCTL[SBDLCK] bit is written '1', the contents of this register are locked down.
+ * Otherwise, the contents of this register are the 'active' contents of the DFA Scoreboard at the time of the
+ * CSR read.
+ * VERIFICATION NOTE: Read data is unsafe. X's(undefined data) can propagate (in the behavioral model)
+ * on the reads unless the DTE Engine specified by DFA_NCBCTL[SBDNUM] has previously been assigned an
+ * instruction.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_dfa_sbd_dbg3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t sbd3                    : 64;      /**< DFA ScoreBoard \#3 Data
+                                                         [63:49] wqptr[32:18]: Work Queue Pointer
+                                                         [48:16] glptr[35:3]: Gather List Pointer
+                                                         [15:0]  glcnt[15:0]: Gather List Counter */
+#else
+        uint64_t sbd3                    : 64;
+#endif
+    } s;
+    struct cvmx_dfa_sbd_dbg3_s           cn31xx;
+    struct cvmx_dfa_sbd_dbg3_s           cn38xx;
+    struct cvmx_dfa_sbd_dbg3_s           cn38xxp2;
+    struct cvmx_dfa_sbd_dbg3_s           cn58xx;
+    struct cvmx_dfa_sbd_dbg3_s           cn58xxp1;
+} cvmx_dfa_sbd_dbg3_t;
+
+
+/**
+ * cvmx_fpa_bist_status
+ *
+ * FPA_BIST_STATUS = BIST Status of FPA Memories
+ * 
+ * The result of the BIST run on the FPA memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t frd                     : 1;       /**< fpa_frd  memory bist status. */
+        uint64_t fpf0                    : 1;       /**< fpa_fpf0 memory bist status. */
+        uint64_t fpf1                    : 1;       /**< fpa_fpf1 memory bist status. */
+        uint64_t ffr                     : 1;       /**< fpa_ffr  memory bist status. */
+        uint64_t fdr                     : 1;       /**< fpa_fdr  memory bist status. */
+#else
+        uint64_t fdr                     : 1;
+        uint64_t ffr                     : 1;
+        uint64_t fpf1                    : 1;
+        uint64_t fpf0                    : 1;
+        uint64_t frd                     : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_fpa_bist_status_s        cn30xx;
+    struct cvmx_fpa_bist_status_s        cn31xx;
+    struct cvmx_fpa_bist_status_s        cn38xx;
+    struct cvmx_fpa_bist_status_s        cn38xxp2;
+    struct cvmx_fpa_bist_status_s        cn50xx;
+    struct cvmx_fpa_bist_status_s        cn52xx;
+    struct cvmx_fpa_bist_status_s        cn52xxp1;
+    struct cvmx_fpa_bist_status_s        cn56xx;
+    struct cvmx_fpa_bist_status_s        cn56xxp1;
+    struct cvmx_fpa_bist_status_s        cn58xx;
+    struct cvmx_fpa_bist_status_s        cn58xxp1;
+} cvmx_fpa_bist_status_t;
+
+
+/**
+ * cvmx_fpa_ctl_status
+ *
+ * FPA_CTL_STATUS = FPA's Control/Status Register
+ * 
+ * The FPA's interrupt enable register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t reset                   : 1;       /**< When set causes a reset of the FPA with the
+                                                         exception of the RSL. */
+        uint64_t use_ldt                 : 1;       /**< When clear '0' the FPA will use LDT to load
+                                                         pointers from the L2C. */
+        uint64_t use_stt                 : 1;       /**< When clear '0' the FPA will use STT to store
+                                                         pointers to the L2C. */
+        uint64_t enb                     : 1;       /**< Must be set to 1 AFTER writing all config registers
+                                                         and 10 cycles have past. If any of the config
+                                                         register are written after writing this bit the
+                                                         FPA may begin to operate incorrectly. */
+        uint64_t mem1_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 1. */
+        uint64_t mem0_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 0. */
+#else
+        uint64_t mem0_err                : 7;
+        uint64_t mem1_err                : 7;
+        uint64_t enb                     : 1;
+        uint64_t use_stt                 : 1;
+        uint64_t use_ldt                 : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_fpa_ctl_status_s         cn30xx;
+    struct cvmx_fpa_ctl_status_s         cn31xx;
+    struct cvmx_fpa_ctl_status_s         cn38xx;
+    struct cvmx_fpa_ctl_status_s         cn38xxp2;
+    struct cvmx_fpa_ctl_status_s         cn50xx;
+    struct cvmx_fpa_ctl_status_s         cn52xx;
+    struct cvmx_fpa_ctl_status_s         cn52xxp1;
+    struct cvmx_fpa_ctl_status_s         cn56xx;
+    struct cvmx_fpa_ctl_status_s         cn56xxp1;
+    struct cvmx_fpa_ctl_status_s         cn58xx;
+    struct cvmx_fpa_ctl_status_s         cn58xxp1;
+} cvmx_fpa_ctl_status_t;
+
+
+/**
+ * cvmx_fpa_fpf#_marks
+ *
+ * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks
+ * 
+ * The high and low watermark register that determines when we write and read free pages from L2C
+ * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 diffrence. Recommend value
+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_fpfx_marks_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_22_63          : 42;
+        uint64_t fpf_wr                  : 11;      /**< When the number of free-page-pointers in a
+                                                          queue exceeds this value the FPA will write
+                                                          32-page-pointers of that queue to DRAM.
+                                                         The MAX value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-2. */
+        uint64_t fpf_rd                  : 11;      /**< When the number of free-page-pointers in a
+                                                          queue drops below this value amd there are
+                                                          free-page-pointers in DRAM, the FPA will
+                                                          read one page (32 pointers) from DRAM.
+                                                         This maximum value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-34. The min number
+                                                         for this would be 16. */
+#else
+        uint64_t fpf_rd                  : 11;
+        uint64_t fpf_wr                  : 11;
+        uint64_t reserved_22_63          : 42;
+#endif
+    } s;
+    struct cvmx_fpa_fpfx_marks_s         cn38xx;
+    struct cvmx_fpa_fpfx_marks_s         cn38xxp2;
+    struct cvmx_fpa_fpfx_marks_s         cn56xx;
+    struct cvmx_fpa_fpfx_marks_s         cn56xxp1;
+    struct cvmx_fpa_fpfx_marks_s         cn58xx;
+    struct cvmx_fpa_fpfx_marks_s         cn58xxp1;
+} cvmx_fpa_fpfx_marks_t;
+
+
+/**
+ * cvmx_fpa_fpf#_size
+ *
+ * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size
+ * 
+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
+ * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_fpfx_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t fpf_siz                 : 11;      /**< The number of entries assigned in the FPA FIFO
+                                                         (used to hold page-pointers) for this Queue.
+                                                         The value of this register must divisable by 2,
+                                                         and the FPA will ignore bit [0] of this register.
+                                                         The total of the FPF_SIZ field of the 8 (0-7)
+                                                         FPA_FPF#_SIZE registers must not exceed 2048.
+                                                         After writing this field the FPA will need 10
+                                                         core clock cycles to be ready for operation. The
+                                                         assignment of location in the FPA FIFO must
+                                                         start with Queue 0, then 1, 2, etc.
+                                                         The number of useable entries will be FPF_SIZ-2. */
+#else
+        uint64_t fpf_siz                 : 11;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_fpa_fpfx_size_s          cn38xx;
+    struct cvmx_fpa_fpfx_size_s          cn38xxp2;
+    struct cvmx_fpa_fpfx_size_s          cn56xx;
+    struct cvmx_fpa_fpfx_size_s          cn56xxp1;
+    struct cvmx_fpa_fpfx_size_s          cn58xx;
+    struct cvmx_fpa_fpfx_size_s          cn58xxp1;
+} cvmx_fpa_fpfx_size_t;
+
+
+/**
+ * cvmx_fpa_fpf0_marks
+ *
+ * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks
+ * 
+ * The high and low watermark register that determines when we write and read free pages from L2C
+ * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 diffrence. Recommend value
+ * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_fpf0_marks_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t fpf_wr                  : 12;      /**< When the number of free-page-pointers in a
+                                                          queue exceeds this value the FPA will write
+                                                          32-page-pointers of that queue to DRAM.
+                                                         The MAX value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-2. */
+        uint64_t fpf_rd                  : 12;      /**< When the number of free-page-pointers in a
+                                                         queue drops below this value amd there are
+                                                         free-page-pointers in DRAM, the FPA will
+                                                         read one page (32 pointers) from DRAM.
+                                                         This maximum value for this field should be
+                                                         FPA_FPF0_SIZE[FPF_SIZ]-34. The min number
+                                                         for this would be 16. */
+#else
+        uint64_t fpf_rd                  : 12;
+        uint64_t fpf_wr                  : 12;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_fpa_fpf0_marks_s         cn38xx;
+    struct cvmx_fpa_fpf0_marks_s         cn38xxp2;
+    struct cvmx_fpa_fpf0_marks_s         cn56xx;
+    struct cvmx_fpa_fpf0_marks_s         cn56xxp1;
+    struct cvmx_fpa_fpf0_marks_s         cn58xx;
+    struct cvmx_fpa_fpf0_marks_s         cn58xxp1;
+} cvmx_fpa_fpf0_marks_t;
+
+
+/**
+ * cvmx_fpa_fpf0_size
+ *
+ * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size
+ * 
+ * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are
+ * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used.
+ * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_fpf0_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t fpf_siz                 : 12;      /**< The number of entries assigned in the FPA FIFO
+                                                         (used to hold page-pointers) for this Queue.
+                                                         The value of this register must divisable by 2,
+                                                         and the FPA will ignore bit [0] of this register.
+                                                         The total of the FPF_SIZ field of the 8 (0-7)
+                                                         FPA_FPF#_SIZE registers must not exceed 2048.
+                                                         After writing this field the FPA will need 10
+                                                         core clock cycles to be ready for operation. The
+                                                         assignment of location in the FPA FIFO must
+                                                         start with Queue 0, then 1, 2, etc.
+                                                         The number of useable entries will be FPF_SIZ-2. */
+#else
+        uint64_t fpf_siz                 : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_fpa_fpf0_size_s          cn38xx;
+    struct cvmx_fpa_fpf0_size_s          cn38xxp2;
+    struct cvmx_fpa_fpf0_size_s          cn56xx;
+    struct cvmx_fpa_fpf0_size_s          cn56xxp1;
+    struct cvmx_fpa_fpf0_size_s          cn58xx;
+    struct cvmx_fpa_fpf0_size_s          cn58xxp1;
+} cvmx_fpa_fpf0_size_t;
+
+
+/**
+ * cvmx_fpa_int_enb
+ *
+ * FPA_INT_ENB = FPA's Interrupt Enable
+ * 
+ * The FPA's interrupt enable register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t q7_perr                 : 1;       /**< When set (1) and bit 27 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q7_coff                 : 1;       /**< When set (1) and bit 26 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q7_und                  : 1;       /**< When set (1) and bit 25 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q6_perr                 : 1;       /**< When set (1) and bit 24 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q6_coff                 : 1;       /**< When set (1) and bit 23 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q6_und                  : 1;       /**< When set (1) and bit 22 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q5_perr                 : 1;       /**< When set (1) and bit 21 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q5_coff                 : 1;       /**< When set (1) and bit 20 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q5_und                  : 1;       /**< When set (1) and bit 19 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q4_perr                 : 1;       /**< When set (1) and bit 18 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q4_coff                 : 1;       /**< When set (1) and bit 17 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q4_und                  : 1;       /**< When set (1) and bit 16 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q3_perr                 : 1;       /**< When set (1) and bit 15 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q3_coff                 : 1;       /**< When set (1) and bit 14 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q3_und                  : 1;       /**< When set (1) and bit 13 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q2_perr                 : 1;       /**< When set (1) and bit 12 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q2_coff                 : 1;       /**< When set (1) and bit 11 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q2_und                  : 1;       /**< When set (1) and bit 10 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q1_perr                 : 1;       /**< When set (1) and bit 9 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q1_coff                 : 1;       /**< When set (1) and bit 8 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q1_und                  : 1;       /**< When set (1) and bit 7 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q0_perr                 : 1;       /**< When set (1) and bit 6 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q0_coff                 : 1;       /**< When set (1) and bit 5 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t q0_und                  : 1;       /**< When set (1) and bit 4 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t fed1_dbe                : 1;       /**< When set (1) and bit 3 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t fed1_sbe                : 1;       /**< When set (1) and bit 2 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t fed0_dbe                : 1;       /**< When set (1) and bit 1 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+        uint64_t fed0_sbe                : 1;       /**< When set (1) and bit 0 of the FPA_INT_SUM
+                                                         register is asserted the FPA will assert an
+                                                         interrupt. */
+#else
+        uint64_t fed0_sbe                : 1;
+        uint64_t fed0_dbe                : 1;
+        uint64_t fed1_sbe                : 1;
+        uint64_t fed1_dbe                : 1;
+        uint64_t q0_und                  : 1;
+        uint64_t q0_coff                 : 1;
+        uint64_t q0_perr                 : 1;
+        uint64_t q1_und                  : 1;
+        uint64_t q1_coff                 : 1;
+        uint64_t q1_perr                 : 1;
+        uint64_t q2_und                  : 1;
+        uint64_t q2_coff                 : 1;
+        uint64_t q2_perr                 : 1;
+        uint64_t q3_und                  : 1;
+        uint64_t q3_coff                 : 1;
+        uint64_t q3_perr                 : 1;
+        uint64_t q4_und                  : 1;
+        uint64_t q4_coff                 : 1;
+        uint64_t q4_perr                 : 1;
+        uint64_t q5_und                  : 1;
+        uint64_t q5_coff                 : 1;
+        uint64_t q5_perr                 : 1;
+        uint64_t q6_und                  : 1;
+        uint64_t q6_coff                 : 1;
+        uint64_t q6_perr                 : 1;
+        uint64_t q7_und                  : 1;
+        uint64_t q7_coff                 : 1;
+        uint64_t q7_perr                 : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_fpa_int_enb_s            cn30xx;
+    struct cvmx_fpa_int_enb_s            cn31xx;
+    struct cvmx_fpa_int_enb_s            cn38xx;
+    struct cvmx_fpa_int_enb_s            cn38xxp2;
+    struct cvmx_fpa_int_enb_s            cn50xx;
+    struct cvmx_fpa_int_enb_s            cn52xx;
+    struct cvmx_fpa_int_enb_s            cn52xxp1;
+    struct cvmx_fpa_int_enb_s            cn56xx;
+    struct cvmx_fpa_int_enb_s            cn56xxp1;
+    struct cvmx_fpa_int_enb_s            cn58xx;
+    struct cvmx_fpa_int_enb_s            cn58xxp1;
+} cvmx_fpa_int_enb_t;
+
+
+/**
+ * cvmx_fpa_int_sum
+ *
+ * FPA_INT_SUM = FPA's Interrupt Summary Register
+ * 
+ * Contains the diffrent interrupt summary bits of the FPA.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t q7_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q7_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+        uint64_t q7_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q6_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q6_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+        uint64_t q6_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q5_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q5_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+        uint64_t q5_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q4_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q4_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+        uint64_t q4_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q3_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q3_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+        uint64_t q3_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q2_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q2_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than than pointers
+                                                         present in the FPA. */
+        uint64_t q2_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q1_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q1_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+        uint64_t q1_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t q0_perr                 : 1;       /**< Set when a Queue0 pointer read from the stack in
+                                                         the L2C does not have the FPA owner ship bit set. */
+        uint64_t q0_coff                 : 1;       /**< Set when a Queue0 stack end tag is present and
+                                                         the count available is greater than pointers
+                                                         present in the FPA. */
+        uint64_t q0_und                  : 1;       /**< Set when a Queue0 page count available goes
+                                                         negative. */
+        uint64_t fed1_dbe                : 1;       /**< Set when a Double Bit Error is detected in FPF1. */
+        uint64_t fed1_sbe                : 1;       /**< Set when a Single Bit Error is detected in FPF1. */
+        uint64_t fed0_dbe                : 1;       /**< Set when a Double Bit Error is detected in FPF0. */
+        uint64_t fed0_sbe                : 1;       /**< Set when a Single Bit Error is detected in FPF0. */
+#else
+        uint64_t fed0_sbe                : 1;
+        uint64_t fed0_dbe                : 1;
+        uint64_t fed1_sbe                : 1;
+        uint64_t fed1_dbe                : 1;
+        uint64_t q0_und                  : 1;
+        uint64_t q0_coff                 : 1;
+        uint64_t q0_perr                 : 1;
+        uint64_t q1_und                  : 1;
+        uint64_t q1_coff                 : 1;
+        uint64_t q1_perr                 : 1;
+        uint64_t q2_und                  : 1;
+        uint64_t q2_coff                 : 1;
+        uint64_t q2_perr                 : 1;
+        uint64_t q3_und                  : 1;
+        uint64_t q3_coff                 : 1;
+        uint64_t q3_perr                 : 1;
+        uint64_t q4_und                  : 1;
+        uint64_t q4_coff                 : 1;
+        uint64_t q4_perr                 : 1;
+        uint64_t q5_und                  : 1;
+        uint64_t q5_coff                 : 1;
+        uint64_t q5_perr                 : 1;
+        uint64_t q6_und                  : 1;
+        uint64_t q6_coff                 : 1;
+        uint64_t q6_perr                 : 1;
+        uint64_t q7_und                  : 1;
+        uint64_t q7_coff                 : 1;
+        uint64_t q7_perr                 : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_fpa_int_sum_s            cn30xx;
+    struct cvmx_fpa_int_sum_s            cn31xx;
+    struct cvmx_fpa_int_sum_s            cn38xx;
+    struct cvmx_fpa_int_sum_s            cn38xxp2;
+    struct cvmx_fpa_int_sum_s            cn50xx;
+    struct cvmx_fpa_int_sum_s            cn52xx;
+    struct cvmx_fpa_int_sum_s            cn52xxp1;
+    struct cvmx_fpa_int_sum_s            cn56xx;
+    struct cvmx_fpa_int_sum_s            cn56xxp1;
+    struct cvmx_fpa_int_sum_s            cn58xx;
+    struct cvmx_fpa_int_sum_s            cn58xxp1;
+} cvmx_fpa_int_sum_t;
+
+
+/**
+ * cvmx_fpa_que#_available
+ *
+ * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register
+ * 
+ * The number of page pointers that are available in the FPA and local DRAM.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_quex_available_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t que_siz                 : 29;      /**< The number of free pages available in this Queue. */
+#else
+        uint64_t que_siz                 : 29;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_fpa_quex_available_s     cn30xx;
+    struct cvmx_fpa_quex_available_s     cn31xx;
+    struct cvmx_fpa_quex_available_s     cn38xx;
+    struct cvmx_fpa_quex_available_s     cn38xxp2;
+    struct cvmx_fpa_quex_available_s     cn50xx;
+    struct cvmx_fpa_quex_available_s     cn52xx;
+    struct cvmx_fpa_quex_available_s     cn52xxp1;
+    struct cvmx_fpa_quex_available_s     cn56xx;
+    struct cvmx_fpa_quex_available_s     cn56xxp1;
+    struct cvmx_fpa_quex_available_s     cn58xx;
+    struct cvmx_fpa_quex_available_s     cn58xxp1;
+} cvmx_fpa_quex_available_t;
+
+
+/**
+ * cvmx_fpa_que#_page_index
+ *
+ * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index
+ * 
+ * The present index page for queue 0 of the FPA.
+ * This numbr reflests the number of pages of pointers that have been written to memory
+ * for this queue.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_quex_page_index_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_25_63          : 39;
+        uint64_t pg_num                  : 25;      /**< Page number. */
+#else
+        uint64_t pg_num                  : 25;
+        uint64_t reserved_25_63          : 39;
+#endif
+    } s;
+    struct cvmx_fpa_quex_page_index_s    cn30xx;
+    struct cvmx_fpa_quex_page_index_s    cn31xx;
+    struct cvmx_fpa_quex_page_index_s    cn38xx;
+    struct cvmx_fpa_quex_page_index_s    cn38xxp2;
+    struct cvmx_fpa_quex_page_index_s    cn50xx;
+    struct cvmx_fpa_quex_page_index_s    cn52xx;
+    struct cvmx_fpa_quex_page_index_s    cn52xxp1;
+    struct cvmx_fpa_quex_page_index_s    cn56xx;
+    struct cvmx_fpa_quex_page_index_s    cn56xxp1;
+    struct cvmx_fpa_quex_page_index_s    cn58xx;
+    struct cvmx_fpa_quex_page_index_s    cn58xxp1;
+} cvmx_fpa_quex_page_index_t;
+
+
+/**
+ * cvmx_fpa_que_act
+ *
+ * FPA_QUE_ACT = FPA's Queue# Actual Page Index
+ * 
+ * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C.
+ * This is latched on the first error and will not latch again unitl all errors are cleared.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_que_act_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t act_que                 : 3;       /**< FPA-queue-number read from memory. */
+        uint64_t act_indx                : 26;      /**< Page number read from memory. */
+#else
+        uint64_t act_indx                : 26;
+        uint64_t act_que                 : 3;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_fpa_que_act_s            cn30xx;
+    struct cvmx_fpa_que_act_s            cn31xx;
+    struct cvmx_fpa_que_act_s            cn38xx;
+    struct cvmx_fpa_que_act_s            cn38xxp2;
+    struct cvmx_fpa_que_act_s            cn50xx;
+    struct cvmx_fpa_que_act_s            cn52xx;
+    struct cvmx_fpa_que_act_s            cn52xxp1;
+    struct cvmx_fpa_que_act_s            cn56xx;
+    struct cvmx_fpa_que_act_s            cn56xxp1;
+    struct cvmx_fpa_que_act_s            cn58xx;
+    struct cvmx_fpa_que_act_s            cn58xxp1;
+} cvmx_fpa_que_act_t;
+
+
+/**
+ * cvmx_fpa_que_exp
+ *
+ * FPA_QUE_EXP = FPA's Queue# Expected Page Index
+ * 
+ * When a INT_SUM[PERR#] occurs this will be latched with the expected value.
+ * This is latched on the first error and will not latch again unitl all errors are cleared.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_que_exp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t exp_que                 : 3;       /**< Expected fpa-queue-number read from memory. */
+        uint64_t exp_indx                : 26;      /**< Expected page number read from memory. */
+#else
+        uint64_t exp_indx                : 26;
+        uint64_t exp_que                 : 3;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_fpa_que_exp_s            cn30xx;
+    struct cvmx_fpa_que_exp_s            cn31xx;
+    struct cvmx_fpa_que_exp_s            cn38xx;
+    struct cvmx_fpa_que_exp_s            cn38xxp2;
+    struct cvmx_fpa_que_exp_s            cn50xx;
+    struct cvmx_fpa_que_exp_s            cn52xx;
+    struct cvmx_fpa_que_exp_s            cn52xxp1;
+    struct cvmx_fpa_que_exp_s            cn56xx;
+    struct cvmx_fpa_que_exp_s            cn56xxp1;
+    struct cvmx_fpa_que_exp_s            cn58xx;
+    struct cvmx_fpa_que_exp_s            cn58xxp1;
+} cvmx_fpa_que_exp_t;
+
+
+/**
+ * cvmx_fpa_wart_ctl
+ *
+ * FPA_WART_CTL = FPA's WART Control
+ * 
+ * Control and status for the WART block.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_wart_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ctl                     : 16;      /**< Control information. */
+#else
+        uint64_t ctl                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_fpa_wart_ctl_s           cn30xx;
+    struct cvmx_fpa_wart_ctl_s           cn31xx;
+    struct cvmx_fpa_wart_ctl_s           cn38xx;
+    struct cvmx_fpa_wart_ctl_s           cn38xxp2;
+    struct cvmx_fpa_wart_ctl_s           cn50xx;
+    struct cvmx_fpa_wart_ctl_s           cn52xx;
+    struct cvmx_fpa_wart_ctl_s           cn52xxp1;
+    struct cvmx_fpa_wart_ctl_s           cn56xx;
+    struct cvmx_fpa_wart_ctl_s           cn56xxp1;
+    struct cvmx_fpa_wart_ctl_s           cn58xx;
+    struct cvmx_fpa_wart_ctl_s           cn58xxp1;
+} cvmx_fpa_wart_ctl_t;
+
+
+/**
+ * cvmx_fpa_wart_status
+ *
+ * FPA_WART_STATUS = FPA's WART Status
+ * 
+ * Control and status for the WART block.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_fpa_wart_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t status                  : 32;      /**< Status information. */
+#else
+        uint64_t status                  : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_fpa_wart_status_s        cn30xx;
+    struct cvmx_fpa_wart_status_s        cn31xx;
+    struct cvmx_fpa_wart_status_s        cn38xx;
+    struct cvmx_fpa_wart_status_s        cn38xxp2;
+    struct cvmx_fpa_wart_status_s        cn50xx;
+    struct cvmx_fpa_wart_status_s        cn52xx;
+    struct cvmx_fpa_wart_status_s        cn52xxp1;
+    struct cvmx_fpa_wart_status_s        cn56xx;
+    struct cvmx_fpa_wart_status_s        cn56xxp1;
+    struct cvmx_fpa_wart_status_s        cn58xx;
+    struct cvmx_fpa_wart_status_s        cn58xxp1;
+} cvmx_fpa_wart_status_t;
+
+
+/**
+ * cvmx_gmx#_bad_reg
+ *
+ * GMX_BAD_REG = A collection of things that have gone very, very wrong
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_bad_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t inb_nxa                 : 4;       /**< Inbound port > GMX_RX_PRTS */
+        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
+        uint64_t loststat                : 4;       /**< TX Statistics data was over-written (per RGM port)
+                                                         TX Stats are corrupted */
+        uint64_t reserved_18_21          : 4;
+        uint64_t out_ovr                 : 16;      /**< Outbound data FIFO overflow (per port) */
+        uint64_t ncb_ovr                 : 1;       /**< Outbound NCB FIFO Overflow */
+        uint64_t out_col                 : 1;       /**< Outbound collision occured between PKO and NCB */
+#else
+        uint64_t out_col                 : 1;
+        uint64_t ncb_ovr                 : 1;
+        uint64_t out_ovr                 : 16;
+        uint64_t reserved_18_21          : 4;
+        uint64_t loststat                : 4;
+        uint64_t statovr                 : 1;
+        uint64_t inb_nxa                 : 4;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_gmxx_bad_reg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t inb_nxa                 : 4;       /**< Inbound port > GMX_RX_PRTS */
+        uint64_t statovr                 : 1;       /**< TX Statistics overflow */
+        uint64_t reserved_25_25          : 1;
+        uint64_t loststat                : 3;       /**< TX Statistics data was over-written (per RGM port)
+                                                         TX Stats are corrupted */
+        uint64_t reserved_5_21           : 17;
+        uint64_t out_ovr                 : 3;       /**< Outbound data FIFO overflow (per port) */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t out_ovr                 : 3;
+        uint64_t reserved_5_21           : 17;
+        uint64_t loststat                : 3;
+        uint64_t reserved_25_25          : 1;
+        uint64_t statovr                 : 1;
+        uint64_t inb_nxa                 : 4;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_bad_reg_cn30xx      cn31xx;
+    struct cvmx_gmxx_bad_reg_s           cn38xx;
+    struct cvmx_gmxx_bad_reg_s           cn38xxp2;
+    struct cvmx_gmxx_bad_reg_cn30xx      cn50xx;
+    struct cvmx_gmxx_bad_reg_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t inb_nxa                 : 4;       /**< Inbound port > GMX_RX_PRTS */
+        uint64_t statovr                 : 1;       /**< TX Statistics overflow
+                                                         The common FIFO to SGMII and XAUI had an overflow
+                                                         TX Stats are corrupted */
+        uint64_t loststat                : 4;       /**< TX Statistics data was over-written
+                                                         In SGMII, one bit per port
+                                                         In XAUI, only port0 is used
+                                                         TX Stats are corrupted */
+        uint64_t reserved_6_21           : 16;
+        uint64_t out_ovr                 : 4;       /**< Outbound data FIFO overflow (per port) */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t out_ovr                 : 4;
+        uint64_t reserved_6_21           : 16;
+        uint64_t loststat                : 4;
+        uint64_t statovr                 : 1;
+        uint64_t inb_nxa                 : 4;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_bad_reg_cn52xx      cn52xxp1;
+    struct cvmx_gmxx_bad_reg_cn52xx      cn56xx;
+    struct cvmx_gmxx_bad_reg_cn52xx      cn56xxp1;
+    struct cvmx_gmxx_bad_reg_s           cn58xx;
+    struct cvmx_gmxx_bad_reg_s           cn58xxp1;
+} cvmx_gmxx_bad_reg_t;
+
+
+/**
+ * cvmx_gmx#_bist
+ *
+ * GMX_BIST = GMX BIST Results
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_bist_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t status                  : 17;      /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.fif_bnk0
+                                                         - 1: gmx#.inb.fif_bnk1
+                                                         - 2: gmx#.inb.fif_bnk2
+                                                         - 3: gmx#.inb.fif_bnk3
+                                                         - 4: gmx#.outb.fif.fif_bnk0
+                                                         - 5: gmx#.outb.fif.fif_bnk1
+                                                         - 6: gmx#.outb.fif.fif_bnk2
+                                                         - 7: gmx#.outb.fif.fif_bnk3
+                                                         - 8: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 9: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 10: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 11: gmx#.csr.gmi3.srf8x64m1_bist
+                                                         - 12: gmx#.csr.drf20x80m1_bist
+                                                         - 13: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 14: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 15: gmx#.outb.ncb.drf16x76m1_bist
+                                                         - 16: gmx#.outb.fif.srf32x16m2_bist */
+#else
+        uint64_t status                  : 17;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_gmxx_bist_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t status                  : 10;      /**< BIST Results.
+                                                          HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.dpr512x78m4_bist
+                                                         - 1: gmx#.outb.fif.dpr512x71m4_bist
+                                                         - 2: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 3: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 4: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 5: 0
+                                                         - 6: gmx#.csr.drf20x80m1_bist
+                                                         - 7: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 8: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 9: 0 */
+#else
+        uint64_t status                  : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_bist_cn30xx         cn31xx;
+    struct cvmx_gmxx_bist_cn30xx         cn38xx;
+    struct cvmx_gmxx_bist_cn30xx         cn38xxp2;
+    struct cvmx_gmxx_bist_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t status                  : 12;      /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails */
+#else
+        uint64_t status                  : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn50xx;
+    struct cvmx_gmxx_bist_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t status                  : 16;      /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         - 0: gmx#.inb.fif_bnk0
+                                                         - 1: gmx#.inb.fif_bnk1
+                                                         - 2: gmx#.inb.fif_bnk2
+                                                         - 3: gmx#.inb.fif_bnk3
+                                                         - 4: gmx#.outb.fif.fif_bnk0
+                                                         - 5: gmx#.outb.fif.fif_bnk1
+                                                         - 6: gmx#.outb.fif.fif_bnk2
+                                                         - 7: gmx#.outb.fif.fif_bnk3
+                                                         - 8: gmx#.csr.gmi0.srf8x64m1_bist
+                                                         - 9: gmx#.csr.gmi1.srf8x64m1_bist
+                                                         - 10: gmx#.csr.gmi2.srf8x64m1_bist
+                                                         - 11: gmx#.csr.gmi3.srf8x64m1_bist
+                                                         - 12: gmx#.csr.drf20x80m1_bist
+                                                         - 13: gmx#.outb.stat.drf16x27m1_bist
+                                                         - 14: gmx#.outb.stat.drf40x64m1_bist
+                                                         - 15: xgmii.tx.drf16x38m1_async_bist */
+#else
+        uint64_t status                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_bist_cn52xx         cn52xxp1;
+    struct cvmx_gmxx_bist_cn52xx         cn56xx;
+    struct cvmx_gmxx_bist_cn52xx         cn56xxp1;
+    struct cvmx_gmxx_bist_s              cn58xx;
+    struct cvmx_gmxx_bist_s              cn58xxp1;
+} cvmx_gmxx_bist_t;
+
+
+/**
+ * cvmx_gmx#_clk_en
+ *
+ * DO NOT DOCUMENT THIS REGISTER - IT IS NOT OFFICIAL
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_clk_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t clk_en                  : 1;       /**< Force the clock enables on */
+#else
+        uint64_t clk_en                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_gmxx_clk_en_s            cn52xx;
+    struct cvmx_gmxx_clk_en_s            cn52xxp1;
+    struct cvmx_gmxx_clk_en_s            cn56xx;
+    struct cvmx_gmxx_clk_en_s            cn56xxp1;
+} cvmx_gmxx_clk_en_t;
+
+
+/**
+ * cvmx_gmx#_hg2_control
+ *
+ * Notes:
+ * The HiGig2 TX and RX enable would normally be both set together for HiGig2 messaging. However
+ * setting just the TX or RX bit will result in only the HG2 message transmit or the receive
+ * capability.
+ * PHYS_EN and LOGL_EN bits when 1, allow link pause or back pressure to PKO as per received
+ * HiGig2 message. When 0, link pause and back pressure to PKO in response to received messages
+ * are disabled.
+ * 
+ * GMX*_TX_XAUI_CTL[HG_EN] must be set to one(to enable HiGig) whenever either HG2TX_EN or HG2RX_EN
+ * are set.
+ * 
+ * GMX*_RX0_UDD_SKP[LEN] must be set to 16 (to select HiGig2) whenever either HG2TX_EN or HG2RX_EN
+ * are set.
+ * 
+ * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
+ * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol when
+ * GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by GMX*_TX_XAUI_CTL[HG_EN]=1
+ * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages
+ * (optionally, when HG2TX_EN=1) with the HiGig2 protocol.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_hg2_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t hg2tx_en                : 1;       /**< Enable Transmission of HG2 phys and logl messages
+                                                         When set, also disables HW auto-generated (802.3
+                                                         and CBFC) pause frames. (OCTEON cannot generate
+                                                         proper 802.3 or CBFC pause frames in HiGig2 mode.) */
+        uint64_t hg2rx_en                : 1;       /**< Enable extraction and processing of HG2 message
+                                                         packet from RX flow. Physical logical pause info
+                                                         is used to pause physical link, back pressure PKO
+                                                         HG2RX_EN must be set when HiGig2 messages are
+                                                         present in the receive stream. */
+        uint64_t phys_en                 : 1;       /**< 1 bit physical link pause enable for recevied
+                                                         HiGig2 physical pause message */
+        uint64_t logl_en                 : 16;      /**< 16 bit xof enables for recevied HiGig2 messages
+                                                         or CBFC packets */
+#else
+        uint64_t logl_en                 : 16;
+        uint64_t phys_en                 : 1;
+        uint64_t hg2rx_en                : 1;
+        uint64_t hg2tx_en                : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } s;
+    struct cvmx_gmxx_hg2_control_s       cn52xx;
+    struct cvmx_gmxx_hg2_control_s       cn52xxp1;
+    struct cvmx_gmxx_hg2_control_s       cn56xx;
+} cvmx_gmxx_hg2_control_t;
+
+
+/**
+ * cvmx_gmx#_inf_mode
+ *
+ * GMX_INF_MODE = Interface Mode
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_inf_mode_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t speed                   : 2;       /**< Interface Speed
+                                                         - 0: 1.250GHz
+                                                         - 1: 2.500GHz
+                                                         - 2: 3.125GHz
+                                                         - 3: 3.750GHz */
+        uint64_t reserved_6_7            : 2;
+        uint64_t mode                    : 2;       /**< Interface Electrical Operating Mode
+                                                         - 0: Disabled (PCIe)
+                                                         - 1: XAUI (IEEE 802.3-2005)
+                                                         - 2: SGMII (v1.8)
+                                                         - 3: PICMG3.1 */
+        uint64_t reserved_3_3            : 1;
+        uint64_t p0mii                   : 1;       /**< Port 0 Interface Mode
+                                                         - 0: Port 0 is RGMII
+                                                         - 1: Port 0 is MII */
+        uint64_t en                      : 1;       /**< Interface Enable */
+        uint64_t type                    : 1;       /**< Interface Mode
+                                                         - 0: RGMII Mode
+                                                         - 1: Spi4 Mode */
+#else
+        uint64_t type                    : 1;
+        uint64_t en                      : 1;
+        uint64_t p0mii                   : 1;
+        uint64_t reserved_3_3            : 1;
+        uint64_t mode                    : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t speed                   : 2;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_gmxx_inf_mode_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t p0mii                   : 1;       /**< Port 0 Interface Mode
+                                                         - 0: Port 0 is RGMII
+                                                         - 1: Port 0 is MII */
+        uint64_t en                      : 1;       /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+        uint64_t type                    : 1;       /**< Port 1/2 Interface Mode
+                                                         - 0: Ports 1 and 2 are RGMII
+                                                         - 1: Port  1 is GMII/MII, Port 2 is unused
+                                                             GMII/MII is selected by GMX_PRT1_CFG[SPEED] */
+#else
+        uint64_t type                    : 1;
+        uint64_t en                      : 1;
+        uint64_t p0mii                   : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_inf_mode_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t en                      : 1;       /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+        uint64_t type                    : 1;       /**< Interface Mode
+                                                         - 0: All three ports are RGMII ports
+                                                         - 1: prt0 is RGMII, prt1 is GMII, and prt2 is unused */
+#else
+        uint64_t type                    : 1;
+        uint64_t en                      : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn31xx;
+    struct cvmx_gmxx_inf_mode_cn31xx     cn38xx;
+    struct cvmx_gmxx_inf_mode_cn31xx     cn38xxp2;
+    struct cvmx_gmxx_inf_mode_cn30xx     cn50xx;
+    struct cvmx_gmxx_inf_mode_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t speed                   : 2;       /**< Interface Speed
+                                                         - 0: 1.250GHz
+                                                         - 1: 2.500GHz
+                                                         - 2: 3.125GHz
+                                                         - 3: 3.750GHz */
+        uint64_t reserved_6_7            : 2;
+        uint64_t mode                    : 2;       /**< Interface Electrical Operating Mode
+                                                         - 0: Disabled (PCIe)
+                                                         - 1: XAUI (IEEE 802.3-2005)
+                                                         - 2: SGMII (v1.8)
+                                                         - 3: PICMG3.1 */
+        uint64_t reserved_2_3            : 2;
+        uint64_t en                      : 1;       /**< Interface Enable
+                                                         Must be set to enable the packet interface.
+                                                         Should be enabled before any other requests to
+                                                         GMX including enabling port back pressure with
+                                                         IPD_CTL_STATUS[PBP_EN] */
+        uint64_t type                    : 1;       /**< Interface Protocol Type
+                                                         - 0: SGMII/1000Base-X
+                                                         - 1: XAUI */
+#else
+        uint64_t type                    : 1;
+        uint64_t en                      : 1;
+        uint64_t reserved_2_3            : 2;
+        uint64_t mode                    : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t speed                   : 2;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_inf_mode_cn52xx     cn52xxp1;
+    struct cvmx_gmxx_inf_mode_cn52xx     cn56xx;
+    struct cvmx_gmxx_inf_mode_cn52xx     cn56xxp1;
+    struct cvmx_gmxx_inf_mode_cn31xx     cn58xx;
+    struct cvmx_gmxx_inf_mode_cn31xx     cn58xxp1;
+} cvmx_gmxx_inf_mode_t;
+
+
+/**
+ * cvmx_gmx#_nxa_adr
+ *
+ * GMX_NXA_ADR = NXA Port Address
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_nxa_adr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t prt                     : 6;       /**< Logged address for NXA exceptions
+                                                         The logged address will be from the first
+                                                         exception that caused the problem.  NCB has
+                                                         higher priority than PKO and will win. */
+#else
+        uint64_t prt                     : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_gmxx_nxa_adr_s           cn30xx;
+    struct cvmx_gmxx_nxa_adr_s           cn31xx;
+    struct cvmx_gmxx_nxa_adr_s           cn38xx;
+    struct cvmx_gmxx_nxa_adr_s           cn38xxp2;
+    struct cvmx_gmxx_nxa_adr_s           cn50xx;
+    struct cvmx_gmxx_nxa_adr_s           cn52xx;
+    struct cvmx_gmxx_nxa_adr_s           cn52xxp1;
+    struct cvmx_gmxx_nxa_adr_s           cn56xx;
+    struct cvmx_gmxx_nxa_adr_s           cn56xxp1;
+    struct cvmx_gmxx_nxa_adr_s           cn58xx;
+    struct cvmx_gmxx_nxa_adr_s           cn58xxp1;
+} cvmx_gmxx_nxa_adr_t;
+
+
+/**
+ * cvmx_gmx#_prt#_cbfc_ctl
+ *
+ * ** HG2 message CSRs end
+ *
+ *
+ * Notes:
+ * XOFF for a specific port is XOFF<prt> = (PHYS_EN<prt> & PHYS_BP) | (LOGL_EN<prt> & LOGL_BP<prt>)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_prtx_cbfc_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t phys_en                 : 16;      /**< Determines which ports will have physical
+                                                         backpressure pause packets.
+                                                         The value pplaced in the Class Enable Vector
+                                                         field of the CBFC pause packet will be
+                                                         PHYS_EN | LOGL_EN */
+        uint64_t logl_en                 : 16;      /**< Determines which ports will have logical
+                                                         backpressure pause packets.
+                                                         The value pplaced in the Class Enable Vector
+                                                         field of the CBFC pause packet will be
+                                                         PHYS_EN | LOGL_EN */
+        uint64_t phys_bp                 : 16;      /**< When RX_EN is set and the HW is backpressuring any
+                                                         ports (from either CBFC pause packets or the
+                                                         GMX_TX_OVR_BP[TX_PRT_BP] register) and all ports
+                                                         indiciated by PHYS_BP are backpressured, simulate
+                                                         physical backpressure by defering all packets on
+                                                         the transmitter. */
+        uint64_t reserved_4_15           : 12;
+        uint64_t bck_en                  : 1;       /**< Forward CBFC Pause information to BP block */
+        uint64_t drp_en                  : 1;       /**< Drop Control CBFC Pause Frames */
+        uint64_t tx_en                   : 1;       /**< When set, allow for CBFC Pause Packets
+                                                         Must be clear in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+        uint64_t rx_en                   : 1;       /**< When set, allow for CBFC Pause Packets
+                                                         Must be clear in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+        uint64_t rx_en                   : 1;
+        uint64_t tx_en                   : 1;
+        uint64_t drp_en                  : 1;
+        uint64_t bck_en                  : 1;
+        uint64_t reserved_4_15           : 12;
+        uint64_t phys_bp                 : 16;
+        uint64_t logl_en                 : 16;
+        uint64_t phys_en                 : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_prtx_cbfc_ctl_s     cn52xx;
+    struct cvmx_gmxx_prtx_cbfc_ctl_s     cn56xx;
+} cvmx_gmxx_prtx_cbfc_ctl_t;
+
+
+/**
+ * cvmx_gmx#_prt#_cfg
+ *
+ * GMX_PRT_CFG = Port description
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_prtx_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t tx_idle                 : 1;       /**< TX Machine is idle */
+        uint64_t rx_idle                 : 1;       /**< RX Machine is idle */
+        uint64_t reserved_9_11           : 3;
+        uint64_t speed_msb               : 1;       /**< Link Speed MSB [SPEED_MSB:SPEED]
+                                                         10 = 10Mbs operation
+                                                         00 = 100Mbs operation
+                                                         01 = 1000Mbs operation
+                                                         11 = Reserved
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_4_7            : 4;
+        uint64_t slottime                : 1;       /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = 4096 bitimes (1000Mbs operation) */
+        uint64_t duplex                  : 1;       /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex */
+        uint64_t speed                   : 1;       /**< Link Speed
+                                                         0 = 10/100Mbs operation
+                                                             (GMX_TX_CLK[CLK_CNT] > 1)
+                                                         1 = 1000Mbs operation */
+        uint64_t en                      : 1;       /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+        uint64_t en                      : 1;
+        uint64_t speed                   : 1;
+        uint64_t duplex                  : 1;
+        uint64_t slottime                : 1;
+        uint64_t reserved_4_7            : 4;
+        uint64_t speed_msb               : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t rx_idle                 : 1;
+        uint64_t tx_idle                 : 1;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_gmxx_prtx_cfg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t slottime                : 1;       /**< Slot Time for Half-Duplex operation
+                                                         0 = 512 bitimes (10/100Mbs operation)
+                                                         1 = 4096 bitimes (1000Mbs operation) */
+        uint64_t duplex                  : 1;       /**< Duplex
+                                                         0 = Half Duplex (collisions/extentions/bursts)
+                                                         1 = Full Duplex */
+        uint64_t speed                   : 1;       /**< Link Speed
+                                                         0 = 10/100Mbs operation
+                                                             (in RGMII mode, GMX_TX_CLK[CLK_CNT] >  1)
+                                                             (in MII   mode, GMX_TX_CLK[CLK_CNT] == 1)
+                                                         1 = 1000Mbs operation */
+        uint64_t en                      : 1;       /**< Link Enable
+                                                         When EN is clear, packets will not be received
+                                                         or transmitted (including PAUSE and JAM packets).
+                                                         If EN is cleared while a packet is currently
+                                                         being received or transmitted, the packet will
+                                                         be allowed to complete before the bus is idled.
+                                                         On the RX side, subsequent packets in a burst
+                                                         will be ignored. */
+#else
+        uint64_t en                      : 1;
+        uint64_t speed                   : 1;
+        uint64_t duplex                  : 1;
+        uint64_t slottime                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_prtx_cfg_cn30xx     cn31xx;
+    struct cvmx_gmxx_prtx_cfg_cn30xx     cn38xx;
+    struct cvmx_gmxx_prtx_cfg_cn30xx     cn38xxp2;
+    struct cvmx_gmxx_prtx_cfg_cn30xx     cn50xx;
+    struct cvmx_gmxx_prtx_cfg_s          cn52xx;
+    struct cvmx_gmxx_prtx_cfg_s          cn52xxp1;
+    struct cvmx_gmxx_prtx_cfg_s          cn56xx;
+    struct cvmx_gmxx_prtx_cfg_s          cn56xxp1;
+    struct cvmx_gmxx_prtx_cfg_cn30xx     cn58xx;
+    struct cvmx_gmxx_prtx_cfg_cn30xx     cn58xxp1;
+} cvmx_gmxx_prtx_cfg_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam0
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam0_s      cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam0_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam1
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam1_s      cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam1_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam2
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam2_s      cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam2_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam3
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam3_s      cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam3_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam4
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam4_s      cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam4_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam5
+ *
+ * GMX_RX_ADR_CAM = Address Filtering Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t adr                     : 64;      /**< The DMAC address to match on
+                                                         Each entry contributes 8bits to one of 8 matchers
+                                                         Write transactions to GMX_RX_ADR_CAM will not
+                                                         change the CSR when GMX_PRT_CFG[EN] is enabled
+                                                         The CAM matches against unicst or multicst DMAC
+                                                         addresses. */
+#else
+        uint64_t adr                     : 64;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam5_s      cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam5_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_cam_en
+ *
+ * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_cam_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t en                      : 8;       /**< CAM Entry Enables */
+#else
+        uint64_t en                      : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn30xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn31xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn38xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn50xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn52xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn56xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn58xx;
+    struct cvmx_gmxx_rxx_adr_cam_en_s    cn58xxp1;
+} cvmx_gmxx_rxx_adr_cam_en_t;
+
+
+/**
+ * cvmx_gmx#_rx#_adr_ctl
+ *
+ * GMX_RX_ADR_CTL = Address Filtering Control
+ *
+ *
+ * Notes:
+ * * ALGORITHM
+ * Here is some pseudo code that represents the address filter behavior.
+ * 
+ *    @verbatim
+ *    bool dmac_addr_filter(uint8 prt, uint48 dmac) [
+ *      ASSERT(prt >= 0 && prt <= 3);
+ *      if (is_bcst(dmac))                               // broadcast accept
+ *        return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
+ *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1)   // multicast reject
+ *        return REJECT;
+ *      if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2)   // multicast accept
+ *        return ACCEPT;
+ * 
+ *      cam_hit = 0;
+ * 
+ *      for (i=0; i<8; i++) [
+ *        if (GMX_RX[prt]_ADR_CAM_EN[EN<i>] == 0)
+ *          continue;
+ *        uint48 unswizzled_mac_adr = 0x0;
+ *        for (j=5; j>=0; j--) [
+ *           unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[prt]_ADR_CAM[j][ADR<i*8+7:i*8>];
+ *        ]
+ *        if (unswizzled_mac_adr == dmac) [
+ *          cam_hit = 1;
+ *          break;
+ *        ]
+ *      ]
+ * 
+ *      if (cam_hit)
+ *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
+ *      else
+ *        return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
+ *    ]
+ *    @endverbatim
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_adr_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t cam_mode                : 1;       /**< Allow or deny DMAC address filter
+                                                         0 = reject the packet on DMAC address match
+                                                         1 = accept the packet on DMAC address match */
+        uint64_t mcst                    : 2;       /**< Multicast Mode
+                                                         0 = Use the Address Filter CAM
+                                                         1 = Force reject all multicast packets
+                                                         2 = Force accept all multicast packets
+                                                         3 = Reserved */
+        uint64_t bcst                    : 1;       /**< Accept All Broadcast Packets */
+#else
+        uint64_t bcst                    : 1;
+        uint64_t mcst                    : 2;
+        uint64_t cam_mode                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn30xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn31xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn38xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn38xxp2;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn50xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn52xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn52xxp1;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn56xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn56xxp1;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn58xx;
+    struct cvmx_gmxx_rxx_adr_ctl_s       cn58xxp1;
+} cvmx_gmxx_rxx_adr_ctl_t;
+
+
+/**
+ * cvmx_gmx#_rx#_decision
+ *
+ * GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
+ *
+ *
+ * Notes:
+ * As each byte in a packet is received by GMX, the L2 byte count is compared
+ * against the GMX_RX_DECISION[CNT].  The L2 byte count is the number of bytes
+ * from the beginning of the L2 header (DMAC).  In normal operation, the L2
+ * header begins after the PREAMBLE+SFD (GMX_RX_FRM_CTL[PRE_CHK]=1) and any
+ * optional UDD skip data (GMX_RX_UDD_SKP[LEN]).
+ * 
+ * When GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
+ * packet and would require UDD skip length to account for them.
+ * 
+ *                                                 L2 Size
+ * Port Mode             <GMX_RX_DECISION bytes (default=24)       >=GMX_RX_DECISION bytes (default=24)
+ * 
+ * Full Duplex           accept packet                             apply filters
+ *                       no filtering is applied                   accept packet based on DMAC and PAUSE packet filters
+ * 
+ * Half Duplex           drop packet                               apply filters
+ *                       packet is unconditionally dropped         accept packet based on DMAC
+ * 
+ * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_decision_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t cnt                     : 5;       /**< The byte count to decide when to accept or filter
+                                                         a packet. */
+#else
+        uint64_t cnt                     : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_decision_s      cn30xx;
+    struct cvmx_gmxx_rxx_decision_s      cn31xx;
+    struct cvmx_gmxx_rxx_decision_s      cn38xx;
+    struct cvmx_gmxx_rxx_decision_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_decision_s      cn50xx;
+    struct cvmx_gmxx_rxx_decision_s      cn52xx;
+    struct cvmx_gmxx_rxx_decision_s      cn52xxp1;
+    struct cvmx_gmxx_rxx_decision_s      cn56xx;
+    struct cvmx_gmxx_rxx_decision_s      cn56xxp1;
+    struct cvmx_gmxx_rxx_decision_s      cn58xx;
+    struct cvmx_gmxx_rxx_decision_s      cn58xxp1;
+} cvmx_gmxx_rxx_decision_t;
+
+
+/**
+ * cvmx_gmx#_rx#_frm_chk
+ *
+ * GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
+ *
+ *
+ * Notes:
+ * If GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
+ * 
+ * In XAUI mode prt0 is used for checking.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_frm_chk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_frm_chk_s       cn30xx;
+    struct cvmx_gmxx_rxx_frm_chk_s       cn31xx;
+    struct cvmx_gmxx_rxx_frm_chk_s       cn38xx;
+    struct cvmx_gmxx_rxx_frm_chk_s       cn38xxp2;
+    struct cvmx_gmxx_rxx_frm_chk_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t reserved_6_6            : 1;
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t reserved_6_6            : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn50xx;
+    struct cvmx_gmxx_rxx_frm_chk_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
+        uint64_t reserved_5_6            : 2;
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_rxx_frm_chk_cn52xx  cn52xxp1;
+    struct cvmx_gmxx_rxx_frm_chk_cn52xx  cn56xx;
+    struct cvmx_gmxx_rxx_frm_chk_cn52xx  cn56xxp1;
+    struct cvmx_gmxx_rxx_frm_chk_s       cn58xx;
+    struct cvmx_gmxx_rxx_frm_chk_s       cn58xxp1;
+} cvmx_gmxx_rxx_frm_chk_t;
+
+
+/**
+ * cvmx_gmx#_rx#_frm_ctl
+ *
+ * GMX_RX_FRM_CTL = Frame Control
+ *
+ *
+ * Notes:
+ * * PRE_CHK
+ *   When set, the RX state expects a typical frame consisting of
+ *   INTER_FRAME=>PREAMBLE(x7)=>SFD(x1)=>DAT.  The state machine watches for
+ *   this exact sequence in order to recognize a valid frame and push frame
+ *   data into the Octane.  There must be exactly 7 PREAMBLE cycles followed by
+ *   the single SFD cycle for the frame to be accepted.
+ * 
+ *   When a problem does occur within the PREAMBLE seqeunce, the frame is
+ *   marked as bad and not sent into the core.  The GMX_RX_INT_REG[PCTERR]
+ *   interrupt is also raised.
+ * 
+ * * PRE_STRP
+ *   When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
+ *   determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
+ *   core as part of the packet.
+ * 
+ *   In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
+ *   size when checking against the MIN and MAX bounds.  Furthermore, the bytes
+ *   are skipped when locating the start of the L2 header for DMAC and Control
+ *   frame recognition.
+ * 
+ * * CTL_BCK/CTL_DRP
+ *   These bits control how the HW handles incoming PAUSE packets.  Here are
+ *   the most common modes of operation:
+ *     CTL_BCK=1,CTL_DRP=1   - HW does it all
+ *     CTL_BCK=0,CTL_DRP=0   - SW sees all pause frames
+ *     CTL_BCK=0,CTL_DRP=1   - all pause frames are completely ignored
+ * 
+ *   These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
+ *   Since PAUSE packets only apply to fulldup operation, any PAUSE packet
+ *   would constitute an exception which should be handled by the processing
+ *   cores.  PAUSE packets should not be forwarded.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_frm_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t null_dis                : 1;       /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets
+                                                         In spi4 mode, all ports use prt0 for checking. */
+        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PREAMBLE can be consumed
+                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
+                                                         PRE_STRP must be set for correct operation.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+        uint64_t pad_len                 : 1;       /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data
+                                                         (PASS3 Only) */
+        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts
+                                                         (PASS2 only) */
+        uint64_t pre_free                : 1;       /**< When set, PREAMBLE checking is  less strict.
+                                                         0 - 254 cycles of PREAMBLE followed by SFD */
+        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
+        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
+        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
+        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+        uint64_t pre_chk                 : 1;
+        uint64_t pre_strp                : 1;
+        uint64_t ctl_drp                 : 1;
+        uint64_t ctl_bck                 : 1;
+        uint64_t ctl_mcst                : 1;
+        uint64_t ctl_smac                : 1;
+        uint64_t pre_free                : 1;
+        uint64_t vlan_len                : 1;
+        uint64_t pad_len                 : 1;
+        uint64_t pre_align               : 1;
+        uint64_t null_dis                : 1;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_frm_ctl_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t pad_len                 : 1;       /**< When set, disables the length check for non-min
+                                                         sized pkts with padding in the client data */
+        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
+        uint64_t pre_free                : 1;       /**< Allows for less strict PREAMBLE checking.
+                                                         0-7 cycles of PREAMBLE followed by SFD (pass 1.0)
+                                                         0-254 cycles of PREAMBLE followed by SFD (else) */
+        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
+        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
+        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
+        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+        uint64_t pre_chk                 : 1;
+        uint64_t pre_strp                : 1;
+        uint64_t ctl_drp                 : 1;
+        uint64_t ctl_bck                 : 1;
+        uint64_t ctl_mcst                : 1;
+        uint64_t ctl_smac                : 1;
+        uint64_t pre_free                : 1;
+        uint64_t vlan_len                : 1;
+        uint64_t pad_len                 : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
+        uint64_t pre_free                : 1;       /**< Allows for less strict PREAMBLE checking.
+                                                         0 - 7 cycles of PREAMBLE followed by SFD (pass1.0)
+                                                         0 - 254 cycles of PREAMBLE followed by SFD (else) */
+        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
+        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
+        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
+        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+        uint64_t pre_chk                 : 1;
+        uint64_t pre_strp                : 1;
+        uint64_t ctl_drp                 : 1;
+        uint64_t ctl_bck                 : 1;
+        uint64_t ctl_mcst                : 1;
+        uint64_t ctl_smac                : 1;
+        uint64_t pre_free                : 1;
+        uint64_t vlan_len                : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } cn31xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn30xx  cn38xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn31xx  cn38xxp2;
+    struct cvmx_gmxx_rxx_frm_ctl_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t null_dis                : 1;       /**< When set, do not modify the MOD bits on NULL ticks
+                                                         due to PARITAL packets */
+        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PREAMBLE can be consumed
+                                                         by the HW so when PRE_ALIGN is set, PRE_FREE,
+                                                         PRE_STRP must be set for correct operation.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+        uint64_t reserved_7_8            : 2;
+        uint64_t pre_free                : 1;       /**< Allows for less strict PREAMBLE checking.
+                                                         0-254 cycles of PREAMBLE followed by SFD */
+        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
+        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
+        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
+        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped */
+        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly */
+#else
+        uint64_t pre_chk                 : 1;
+        uint64_t pre_strp                : 1;
+        uint64_t ctl_drp                 : 1;
+        uint64_t ctl_bck                 : 1;
+        uint64_t ctl_mcst                : 1;
+        uint64_t ctl_smac                : 1;
+        uint64_t pre_free                : 1;
+        uint64_t reserved_7_8            : 2;
+        uint64_t pre_align               : 1;
+        uint64_t null_dis                : 1;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn50xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn50xx  cn52xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn50xx  cn52xxp1;
+    struct cvmx_gmxx_rxx_frm_ctl_cn50xx  cn56xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pre_align               : 1;       /**< When set, PREAMBLE parser aligns the the SFD byte
+                                                         regardless of the number of previous PREAMBLE
+                                                         nibbles.  In this mode, PRE_STRP should be set to
+                                                         account for the variable nature of the PREAMBLE.
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII at 10/100Mbs only) */
+        uint64_t reserved_7_8            : 2;
+        uint64_t pre_free                : 1;       /**< When set, PREAMBLE checking is  less strict.
+                                                         0 - 254 cycles of PREAMBLE followed by SFD
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features.
+                                                         (SGMII/1000Base-X only) */
+        uint64_t ctl_smac                : 1;       /**< Control Pause Frames can match station SMAC */
+        uint64_t ctl_mcst                : 1;       /**< Control Pause Frames can match globally assign
+                                                         Multicast address */
+        uint64_t ctl_bck                 : 1;       /**< Forward pause information to TX block */
+        uint64_t ctl_drp                 : 1;       /**< Drop Control Pause Frames */
+        uint64_t pre_strp                : 1;       /**< Strip off the preamble (when present)
+                                                         0=PREAMBLE+SFD is sent to core as part of frame
+                                                         1=PREAMBLE+SFD is dropped
+                                                         PRE_CHK must be set to enable this and all
+                                                         PREAMBLE features. */
+        uint64_t pre_chk                 : 1;       /**< This port is configured to send PREAMBLE+SFD
+                                                         to begin every frame.  GMX checks that the
+                                                         PREAMBLE is sent correctly.
+                                                         When GMX_TX_XAUI_CTL[HG_EN] is set, PRE_CHK
+                                                         must be zero. */
+#else
+        uint64_t pre_chk                 : 1;
+        uint64_t pre_strp                : 1;
+        uint64_t ctl_drp                 : 1;
+        uint64_t ctl_bck                 : 1;
+        uint64_t ctl_mcst                : 1;
+        uint64_t ctl_smac                : 1;
+        uint64_t pre_free                : 1;
+        uint64_t reserved_7_8            : 2;
+        uint64_t pre_align               : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn56xxp1;
+    struct cvmx_gmxx_rxx_frm_ctl_s       cn58xx;
+    struct cvmx_gmxx_rxx_frm_ctl_cn30xx  cn58xxp1;
+} cvmx_gmxx_rxx_frm_ctl_t;
+
+
+/**
+ * cvmx_gmx#_rx#_frm_max
+ *
+ * GMX_RX_FRM_MAX = Frame Max length
+ *
+ *
+ * Notes:
+ * In spi4 mode, all spi4 ports use prt0 for checking.
+ * 
+ * When changing the LEN field, be sure that LEN does not exceed
+ * GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
+ * are within the maximum length parameter to be rejected because they exceed
+ * the GMX_RX_JABBER[CNT] limit.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_frm_max_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t len                     : 16;      /**< Byte count for Max-sized frame check
+                                                         Failing packets set the MAXERR interrupt and are
+                                                         optionally sent with opcode==MAXERR
+                                                         LEN =< GMX_RX_JABBER[CNT] */
+#else
+        uint64_t len                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_frm_max_s       cn30xx;
+    struct cvmx_gmxx_rxx_frm_max_s       cn31xx;
+    struct cvmx_gmxx_rxx_frm_max_s       cn38xx;
+    struct cvmx_gmxx_rxx_frm_max_s       cn38xxp2;
+    struct cvmx_gmxx_rxx_frm_max_s       cn58xx;
+    struct cvmx_gmxx_rxx_frm_max_s       cn58xxp1;
+} cvmx_gmxx_rxx_frm_max_t;
+
+
+/**
+ * cvmx_gmx#_rx#_frm_min
+ *
+ * GMX_RX_FRM_MIN = Frame Min length
+ *
+ *
+ * Notes:
+ * In spi4 mode, all spi4 ports use prt0 for checking.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_frm_min_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t len                     : 16;      /**< Byte count for Min-sized frame check
+                                                         Failing packets set the MINERR interrupt and are
+                                                         optionally sent with opcode==MINERR */
+#else
+        uint64_t len                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_frm_min_s       cn30xx;
+    struct cvmx_gmxx_rxx_frm_min_s       cn31xx;
+    struct cvmx_gmxx_rxx_frm_min_s       cn38xx;
+    struct cvmx_gmxx_rxx_frm_min_s       cn38xxp2;
+    struct cvmx_gmxx_rxx_frm_min_s       cn58xx;
+    struct cvmx_gmxx_rxx_frm_min_s       cn58xxp1;
+} cvmx_gmxx_rxx_frm_min_t;
+
+
+/**
+ * cvmx_gmx#_rx#_ifg
+ *
+ * GMX_RX_IFG = RX Min IFG
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_ifg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ifg                     : 4;       /**< Min IFG between packets used to determine IFGERR
+                                                         1000Mbs, IFG==0.096us or 12 clks
+                                                         100Mbs,  IFG==0.96us or 24 clks
+                                                         10Mbs,   IFG==9.6us or 24 clks
+                                                         In order to simplify the programming model,
+                                                         IFG is doubled internally when
+                                                         GMX_PRT_CFG[SPEED]==0. */
+#else
+        uint64_t ifg                     : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_ifg_s           cn30xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn31xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn38xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn38xxp2;
+    struct cvmx_gmxx_rxx_ifg_s           cn50xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn52xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn52xxp1;
+    struct cvmx_gmxx_rxx_ifg_s           cn56xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn56xxp1;
+    struct cvmx_gmxx_rxx_ifg_s           cn58xx;
+    struct cvmx_gmxx_rxx_ifg_s           cn58xxp1;
+} cvmx_gmxx_rxx_ifg_t;
+
+
+/**
+ * cvmx_gmx#_rx#_int_en
+ *
+ * GMX_RX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * In XAUI mode prt0 is used for checking.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t hg2cc                   : 1;       /**< HiGig2 CRC8 or Control char error interrupt enable */
+        uint64_t hg2fld                  : 1;       /**< HiGig2 Bad field error interrupt enable */
+        uint64_t undat                   : 1;       /**< Unexpected Data
+                                                         (XAUI Mode only) */
+        uint64_t uneop                   : 1;       /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+        uint64_t unsop                   : 1;       /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t pause_drp               : 1;
+        uint64_t loc_fault               : 1;
+        uint64_t rem_fault               : 1;
+        uint64_t bad_seq                 : 1;
+        uint64_t bad_term                : 1;
+        uint64_t unsop                   : 1;
+        uint64_t uneop                   : 1;
+        uint64_t undat                   : 1;
+        uint64_t hg2fld                  : 1;
+        uint64_t hg2cc                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_int_en_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_rxx_int_en_cn30xx   cn31xx;
+    struct cvmx_gmxx_rxx_int_en_cn30xx   cn38xx;
+    struct cvmx_gmxx_rxx_int_en_cn30xx   cn38xxp2;
+    struct cvmx_gmxx_rxx_int_en_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t reserved_6_6            : 1;
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t reserved_6_6            : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t pause_drp               : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn50xx;
+    struct cvmx_gmxx_rxx_int_en_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t hg2cc                   : 1;       /**< HiGig2 CRC8 or Control char error interrupt enable */
+        uint64_t hg2fld                  : 1;       /**< HiGig2 Bad field error interrupt enable */
+        uint64_t undat                   : 1;       /**< Unexpected Data
+                                                         (XAUI Mode only) */
+        uint64_t uneop                   : 1;       /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+        uint64_t unsop                   : 1;       /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t reserved_16_18          : 3;
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         (SGMII/1000Base-X only) */
+        uint64_t coldet                  : 1;       /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_9_9            : 1;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
+        uint64_t reserved_5_6            : 2;
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t pause_drp               : 1;
+        uint64_t loc_fault               : 1;
+        uint64_t rem_fault               : 1;
+        uint64_t bad_seq                 : 1;
+        uint64_t bad_term                : 1;
+        uint64_t unsop                   : 1;
+        uint64_t uneop                   : 1;
+        uint64_t undat                   : 1;
+        uint64_t hg2fld                  : 1;
+        uint64_t hg2cc                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_rxx_int_en_cn52xx   cn52xxp1;
+    struct cvmx_gmxx_rxx_int_en_cn52xx   cn56xx;
+    struct cvmx_gmxx_rxx_int_en_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t undat                   : 1;       /**< Unexpected Data
+                                                         (XAUI Mode only) */
+        uint64_t uneop                   : 1;       /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+        uint64_t unsop                   : 1;       /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t reserved_16_18          : 3;
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         (SGMII/1000Base-X only) */
+        uint64_t coldet                  : 1;       /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_9_9            : 1;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
+        uint64_t reserved_5_6            : 2;
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t pause_drp               : 1;
+        uint64_t loc_fault               : 1;
+        uint64_t rem_fault               : 1;
+        uint64_t bad_seq                 : 1;
+        uint64_t bad_term                : 1;
+        uint64_t unsop                   : 1;
+        uint64_t uneop                   : 1;
+        uint64_t undat                   : 1;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn56xxp1;
+    struct cvmx_gmxx_rxx_int_en_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t pause_drp               : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn58xx;
+    struct cvmx_gmxx_rxx_int_en_cn58xx   cn58xxp1;
+} cvmx_gmxx_rxx_int_en_t;
+
+
+/**
+ * cvmx_gmx#_rx#_int_reg
+ *
+ * GMX_RX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * (1) exceptions will only be raised to the control processor if the
+ *     corresponding bit in the GMX_RX_INT_EN register is set.
+ * 
+ * (2) exception conditions 10:0 can also set the rcv/opcode in the received
+ *     packet's workQ entry.  The GMX_RX_FRM_CHK register provides a bit mask
+ *     for configuring which conditions set the error.
+ * 
+ * (3) in half duplex operation, the expectation is that collisions will appear
+ *     as either MINERR o r CAREXT errors.
+ * 
+ * (4) JABBER - An RX Jabber error indicates that a packet was received which
+ *              is longer than the maximum allowed packet as defined by the
+ *              system.  GMX will truncate the packet at the JABBER count.
+ *              Failure to do so could lead to system instabilty.
+ * 
+ * (5) NIBERR - This error is illegal at 1000Mbs speeds
+ *              (GMX_RX_PRT_CFG[SPEED]==0) and will never assert.
+ * 
+ * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
+ *              GMX_RX_FRM_MAX.  For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
+ *              > GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
+ * 
+ * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < GMX_RX_FRM_MIN.
+ * 
+ * (8) ALNERR - Indicates that the packet received was not an integer number of
+ *              bytes.  If FCS checking is enabled, ALNERR will only assert if
+ *              the FCS is bad.  If FCS checking is disabled, ALNERR will
+ *              assert in all non-integer frame cases.
+ * 
+ * (9) Collisions - Collisions can only occur in half-duplex mode.  A collision
+ *                  is assumed by the receiver when the slottime
+ *                  (GMX_PRT_CFG[SLOTTIME]) is not satisfied.  In 10/100 mode,
+ *                  this will result in a frame < SLOTTIME.  In 1000 mode, it
+ *                  could result either in frame < SLOTTIME or a carrier extend
+ *                  error with the SLOTTIME.  These conditions are visible by...
+ * 
+ *                  . transfer ended before slottime - COLDET
+ *                  . carrier extend error           - CAREXT
+ * 
+ * (A) LENERR - Length errors occur when the received packet does not match the
+ *              length field.  LENERR is only checked for packets between 64
+ *              and 1500 bytes.  For untagged frames, the length must exact
+ *              match.  For tagged frames the length or length+4 must match.
+ * 
+ * (B) PCTERR - checks that the frame transtions from PREAMBLE=>SFD=>DATA.
+ *              Does not check the number of PREAMBLE cycles.
+ * 
+ * (C) OVRERR - Not to be included in the HRM
+ * 
+ *              OVRERR is an architectural assertion check internal to GMX to
+ *              make sure no assumption was violated.  In a correctly operating
+ *              system, this interrupt can never fire.
+ * 
+ *              GMX has an internal arbiter which selects which of 4 ports to
+ *              buffer in the main RX FIFO.  If we normally buffer 8 bytes,
+ *              then each port will typically push a tick every 8 cycles - if
+ *              the packet interface is going as fast as possible.  If there
+ *              are four ports, they push every two cycles.  So that's the
+ *              assumption.  That the inbound module will always be able to
+ *              consume the tick before another is produced.  If that doesn't
+ *              happen - that's when OVRERR will assert.
+ * 
+ * (D) In XAUI mode prt0 is used for interrupt logging.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t hg2cc                   : 1;       /**< HiGig2 received message CRC or Control char  error
+                                                         Set when either CRC8 error detected or when
+                                                         a Control Character is found in the message
+                                                         bytes after the K.SOM
+                                                         NOTE: HG2CC has higher priority than HG2FLD
+                                                               i.e. a HiGig2 message that results in HG2CC
+                                                               getting set, will never set HG2FLD. */
+        uint64_t hg2fld                  : 1;       /**< HiGig2 received message field error, as below
+                                                         1) MSG_TYPE field not 6'b00_0000
+                                                            i.e. it is not a FLOW CONTROL message, which
+                                                            is the only defined type for HiGig2
+                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
+                                                            which is the only defined type for HiGig2
+                                                         3) FC_OBJECT field is neither 4'b0000 for
+                                                            Physical Link nor 4'b0010 for Logical Link.
+                                                            Those are the only two defined types in HiGig2 */
+        uint64_t undat                   : 1;       /**< Unexpected Data
+                                                         (XAUI Mode only) */
+        uint64_t uneop                   : 1;       /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+        uint64_t unsop                   : 1;       /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t pause_drp               : 1;
+        uint64_t loc_fault               : 1;
+        uint64_t rem_fault               : 1;
+        uint64_t bad_seq                 : 1;
+        uint64_t bad_term                : 1;
+        uint64_t unsop                   : 1;
+        uint64_t uneop                   : 1;
+        uint64_t undat                   : 1;
+        uint64_t hg2fld                  : 1;
+        uint64_t hg2cc                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_int_reg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_rxx_int_reg_cn30xx  cn31xx;
+    struct cvmx_gmxx_rxx_int_reg_cn30xx  cn38xx;
+    struct cvmx_gmxx_rxx_int_reg_cn30xx  cn38xxp2;
+    struct cvmx_gmxx_rxx_int_reg_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t reserved_6_6            : 1;
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t reserved_6_6            : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t pause_drp               : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn50xx;
+    struct cvmx_gmxx_rxx_int_reg_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t hg2cc                   : 1;       /**< HiGig2 received message CRC or Control char  error
+                                                         Set when either CRC8 error detected or when
+                                                         a Control Character is found in the message
+                                                         bytes after the K.SOM
+                                                         NOTE: HG2CC has higher priority than HG2FLD
+                                                               i.e. a HiGig2 message that results in HG2CC
+                                                               getting set, will never set HG2FLD. */
+        uint64_t hg2fld                  : 1;       /**< HiGig2 received message field error, as below
+                                                         1) MSG_TYPE field not 6'b00_0000
+                                                            i.e. it is not a FLOW CONTROL message, which
+                                                            is the only defined type for HiGig2
+                                                         2) FWD_TYPE field not 2'b00 i.e. Link Level msg
+                                                            which is the only defined type for HiGig2
+                                                         3) FC_OBJECT field is neither 4'b0000 for
+                                                            Physical Link nor 4'b0010 for Logical Link.
+                                                            Those are the only two defined types in HiGig2 */
+        uint64_t undat                   : 1;       /**< Unexpected Data
+                                                         (XAUI Mode only) */
+        uint64_t uneop                   : 1;       /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+        uint64_t unsop                   : 1;       /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t reserved_16_18          : 3;
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure
+                                                         (SGMII/1000Base-X only) */
+        uint64_t coldet                  : 1;       /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol
+                                                         In XAUI mode, the column of data that was bad
+                                                         will be logged in GMX_RX_XAUI_BAD_COL */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_9_9            : 1;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
+        uint64_t reserved_5_6            : 2;
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t pause_drp               : 1;
+        uint64_t loc_fault               : 1;
+        uint64_t rem_fault               : 1;
+        uint64_t bad_seq                 : 1;
+        uint64_t bad_term                : 1;
+        uint64_t unsop                   : 1;
+        uint64_t uneop                   : 1;
+        uint64_t undat                   : 1;
+        uint64_t hg2fld                  : 1;
+        uint64_t hg2cc                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_rxx_int_reg_cn52xx  cn52xxp1;
+    struct cvmx_gmxx_rxx_int_reg_cn52xx  cn56xx;
+    struct cvmx_gmxx_rxx_int_reg_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t undat                   : 1;       /**< Unexpected Data
+                                                         (XAUI Mode only) */
+        uint64_t uneop                   : 1;       /**< Unexpected EOP
+                                                         (XAUI Mode only) */
+        uint64_t unsop                   : 1;       /**< Unexpected SOP
+                                                         (XAUI Mode only) */
+        uint64_t bad_term                : 1;       /**< Frame is terminated by control character other
+                                                         than /T/.  The error propagation control
+                                                         character /E/ will be included as part of the
+                                                         frame and does not cause a frame termination.
+                                                         (XAUI Mode only) */
+        uint64_t bad_seq                 : 1;       /**< Reserved Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t rem_fault               : 1;       /**< Remote Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t loc_fault               : 1;       /**< Local Fault Sequence Deteted
+                                                         (XAUI Mode only) */
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t reserved_16_18          : 3;
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure
+                                                         (SGMII/1000Base-X only) */
+        uint64_t coldet                  : 1;       /**< Collision Detection
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime
+                                                         (SGMII/1000Base-X only) */
+        uint64_t rsverr                  : 1;       /**< Reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol
+                                                         In XAUI mode, the column of data that was bad
+                                                         will be logged in GMX_RX_XAUI_BAD_COL */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_9_9            : 1;
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with Data reception error */
+        uint64_t reserved_5_6            : 2;
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t reserved_2_2            : 1;
+        uint64_t carext                  : 1;       /**< Carrier extend error
+                                                         (SGMII/1000Base-X only) */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t carext                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t pause_drp               : 1;
+        uint64_t loc_fault               : 1;
+        uint64_t rem_fault               : 1;
+        uint64_t bad_seq                 : 1;
+        uint64_t bad_term                : 1;
+        uint64_t unsop                   : 1;
+        uint64_t uneop                   : 1;
+        uint64_t undat                   : 1;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn56xxp1;
+    struct cvmx_gmxx_rxx_int_reg_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pause_drp               : 1;       /**< Pause packet was dropped due to full GMX RX FIFO */
+        uint64_t phy_dupx                : 1;       /**< Change in the RMGII inbound LinkDuplex */
+        uint64_t phy_spd                 : 1;       /**< Change in the RMGII inbound LinkSpeed */
+        uint64_t phy_link                : 1;       /**< Change in the RMGII inbound LinkStatus */
+        uint64_t ifgerr                  : 1;       /**< Interframe Gap Violation
+                                                         Does not necessarily indicate a failure */
+        uint64_t coldet                  : 1;       /**< Collision Detection */
+        uint64_t falerr                  : 1;       /**< False carrier error or extend error after slottime */
+        uint64_t rsverr                  : 1;       /**< RGMII reserved opcodes */
+        uint64_t pcterr                  : 1;       /**< Bad Preamble / Protocol */
+        uint64_t ovrerr                  : 1;       /**< Internal Data Aggregation Overflow
+                                                         This interrupt should never assert */
+        uint64_t niberr                  : 1;       /**< Nibble error (hi_nibble != lo_nibble) */
+        uint64_t skperr                  : 1;       /**< Skipper error */
+        uint64_t rcverr                  : 1;       /**< Frame was received with RMGII Data reception error */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t alnerr                  : 1;       /**< Frame was received with an alignment error */
+        uint64_t fcserr                  : 1;       /**< Frame was received with FCS/CRC error */
+        uint64_t jabber                  : 1;       /**< Frame was received with length > sys_length */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t carext                  : 1;       /**< RGMII carrier extend error */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+#else
+        uint64_t minerr                  : 1;
+        uint64_t carext                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t jabber                  : 1;
+        uint64_t fcserr                  : 1;
+        uint64_t alnerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t rcverr                  : 1;
+        uint64_t skperr                  : 1;
+        uint64_t niberr                  : 1;
+        uint64_t ovrerr                  : 1;
+        uint64_t pcterr                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t falerr                  : 1;
+        uint64_t coldet                  : 1;
+        uint64_t ifgerr                  : 1;
+        uint64_t phy_link                : 1;
+        uint64_t phy_spd                 : 1;
+        uint64_t phy_dupx                : 1;
+        uint64_t pause_drp               : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn58xx;
+    struct cvmx_gmxx_rxx_int_reg_cn58xx  cn58xxp1;
+} cvmx_gmxx_rxx_int_reg_t;
+
+
+/**
+ * cvmx_gmx#_rx#_jabber
+ *
+ * GMX_RX_JABBER = The max size packet after which GMX will truncate
+ *
+ *
+ * Notes:
+ * CNT must be 8-byte aligned such that CNT[2:0] == 0
+ * 
+ * The packet that will be sent to the packet input logic will have an
+ * additionl 8 bytes if GMX_RX_FRM_CTL[PRE_CHK] is set and
+ * GMX_RX_FRM_CTL[PRE_STRP] is clear.  The max packet that will be sent is
+ * defined as...
+ * 
+ *      max_sized_packet = GMX_RX_JABBER[CNT]+((GMX_RX_FRM_CTL[PRE_CHK] & !GMX_RX_FRM_CTL[PRE_STRP])*8)
+ * 
+ * In XAUI mode prt0 is used for checking.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_jabber_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt                     : 16;      /**< Byte count for jabber check
+                                                         Failing packets set the JABBER interrupt and are
+                                                         optionally sent with opcode==JABBER
+                                                         GMX will truncate the packet to CNT bytes
+                                                         CNT >= GMX_RX_FRM_MAX[LEN] */
+#else
+        uint64_t cnt                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_jabber_s        cn30xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn31xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn38xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn38xxp2;
+    struct cvmx_gmxx_rxx_jabber_s        cn50xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn52xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn52xxp1;
+    struct cvmx_gmxx_rxx_jabber_s        cn56xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn56xxp1;
+    struct cvmx_gmxx_rxx_jabber_s        cn58xx;
+    struct cvmx_gmxx_rxx_jabber_s        cn58xxp1;
+} cvmx_gmxx_rxx_jabber_t;
+
+
+/**
+ * cvmx_gmx#_rx#_pause_drop_time
+ *
+ * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_pause_drop_time_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t status                  : 16;      /**< Time extracted from the dropped PAUSE packet */
+#else
+        uint64_t status                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
+    struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
+} cvmx_gmxx_rxx_pause_drop_time_t;
+
+
+/**
+ * cvmx_gmx#_rx#_rx_inbnd
+ *
+ * GMX_RX_INBND = RGMII InBand Link Status
+ *
+ *
+ * Notes:
+ * These fields are only valid if the attached PHY is operating in RGMII mode
+ * and supports the optional in-band status (see section 3.4.1 of the RGMII
+ * specification, version 1.3 for more information).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_rx_inbnd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t duplex                  : 1;       /**< RGMII Inbound LinkDuplex
+                                                         0=half-duplex
+                                                         1=full-duplex */
+        uint64_t speed                   : 2;       /**< RGMII Inbound LinkSpeed
+                                                         00=2.5MHz
+                                                         01=25MHz
+                                                         10=125MHz
+                                                         11=Reserved */
+        uint64_t status                  : 1;       /**< RGMII Inbound LinkStatus
+                                                         0=down
+                                                         1=up */
+#else
+        uint64_t status                  : 1;
+        uint64_t speed                   : 2;
+        uint64_t duplex                  : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn30xx;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn31xx;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn38xx;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn38xxp2;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn50xx;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn58xx;
+    struct cvmx_gmxx_rxx_rx_inbnd_s      cn58xxp1;
+} cvmx_gmxx_rxx_rx_inbnd_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_ctl
+ *
+ * GMX_RX_STATS_CTL = RX Stats Control register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rd_clr                  : 1;       /**< RX Stats registers will clear on reads */
+#else
+        uint64_t rd_clr                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn30xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn31xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn38xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn50xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn52xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn56xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn58xx;
+    struct cvmx_gmxx_rxx_stats_ctl_s     cn58xxp1;
+} cvmx_gmxx_rxx_stats_ctl_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_octs
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_octs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of received good packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn30xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn31xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn38xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn50xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn52xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn56xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn58xx;
+    struct cvmx_gmxx_rxx_stats_octs_s    cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_octs_ctl
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of received pause packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_ctl_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_octs_dmac
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of filtered dmac packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_dmac_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_octs_drp
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t cnt                     : 48;      /**< Octet count of dropped packets */
+#else
+        uint64_t cnt                     : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_octs_drp_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts
+ *
+ * GMX_RX_STATS_PKTS
+ * 
+ * Count of good received packets - packets that are not recognized as PAUSE
+ * packets, dropped due the DMAC filter, dropped due FIFO full status, or
+ * have any other OPCODE (FCS, Length, etc).
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_pkts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of received good packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn30xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn31xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn38xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn50xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn52xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn56xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn58xx;
+    struct cvmx_gmxx_rxx_stats_pkts_s    cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_bad
+ *
+ * GMX_RX_STATS_PKTS_BAD
+ * 
+ * Count of all packets received with some error that were not dropped
+ * either due to the dmac filter or lack of room in the receive FIFO.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of bad packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_bad_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_ctl
+ *
+ * GMX_RX_STATS_PKTS_CTL
+ * 
+ * Count of all packets received that were recognized as Flow Control or
+ * PAUSE packets.  PAUSE packets with any kind of error are counted in
+ * GMX_RX_STATS_PKTS_BAD.  Pause packets can be optionally dropped or
+ * forwarded based on the GMX_RX_FRM_CTL[CTL_DRP] bit.  This count
+ * increments regardless of whether the packet is dropped.  Pause packets
+ * will never be counted in GMX_RX_STATS_PKTS.  Packets dropped due the dmac
+ * filter will be counted in GMX_RX_STATS_PKTS_DMAC and not here.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of received pause packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_ctl_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_dmac
+ *
+ * GMX_RX_STATS_PKTS_DMAC
+ * 
+ * Count of all packets received that were dropped by the dmac filter.
+ * Packets that match the DMAC will be dropped and counted here regardless
+ * of if they were bad packets.  These packets will never be counted in
+ * GMX_RX_STATS_PKTS.
+ * 
+ * Some packets that were not able to satisify the DECISION_CNT may not
+ * actually be dropped by Octeon, but they will be counted here as if they
+ * were dropped.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of filtered dmac packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_dmac_t;
+
+
+/**
+ * cvmx_gmx#_rx#_stats_pkts_drp
+ *
+ * GMX_RX_STATS_PKTS_DRP
+ * 
+ * Count of all packets received that were dropped due to a full receive
+ * FIFO.  This counts good and bad packets received - all packets dropped by
+ * the FIFO.  It does not count packets dropped by the dmac or pause packet
+ * filters.
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Count of dropped packets */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
+    struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
+} cvmx_gmxx_rxx_stats_pkts_drp_t;
+
+
+/**
+ * cvmx_gmx#_rx#_udd_skp
+ *
+ * GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
+ *
+ *
+ * Notes:
+ * (1) The skip bytes are part of the packet and will be sent down the NCB
+ *     packet interface and will be handled by PKI.
+ * 
+ * (2) The system can determine if the UDD bytes are included in the FCS check
+ *     by using the FCSSEL field - if the FCS check is enabled.
+ * 
+ * (3) Assume that the preamble/sfd is always at the start of the frame - even
+ *     before UDD bytes.  In most cases, there will be no preamble in these
+ *     cases since it will be packet interface in direct communication to
+ *     another packet interface (MAC to MAC) without a PHY involved.
+ * 
+ * (4) We can still do address filtering and control packet filtering is the
+ *     user desires.
+ * 
+ * (5) UDD_SKP must be 0 in half-duplex operation unless
+ *     GMX_RX_FRM_CTL[PRE_CHK] is clear.  If GMX_RX_FRM_CTL[PRE_CHK] is clear,
+ *     then UDD_SKP will normally be 8.
+ * 
+ * (6) In all cases, the UDD bytes will be sent down the packet interface as
+ *     part of the packet.  The UDD bytes are never stripped from the actual
+ *     packet.
+ * 
+ * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rxx_udd_skp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t fcssel                  : 1;       /**< Include the skip bytes in the FCS calculation
+                                                         0 = all skip bytes are included in FCS
+                                                         1 = the skip bytes are not included in FCS */
+        uint64_t reserved_7_7            : 1;
+        uint64_t len                     : 7;       /**< Amount of User-defined data before the start of
+                                                         the L2 data.  Zero means L2 comes first.
+                                                         Max value is 64. */
+#else
+        uint64_t len                     : 7;
+        uint64_t reserved_7_7            : 1;
+        uint64_t fcssel                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn30xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn31xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn38xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn38xxp2;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn50xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn52xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn52xxp1;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn56xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn56xxp1;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn58xx;
+    struct cvmx_gmxx_rxx_udd_skp_s       cn58xxp1;
+} cvmx_gmxx_rxx_udd_skp_t;
+
+
+/**
+ * cvmx_gmx#_rx_bp_drop#
+ *
+ * GMX_RX_BP_DROP = FIFO mark for packet drop
+ *
+ *
+ * Notes:
+ * The actual watermark is dynamic with respect to the GMX_RX_PRTS
+ * register.  The GMX_RX_PRTS controls the depth of the port's
+ * FIFO so as ports are added or removed, the drop point may change.
+ * 
+ * In XAUI mode prt0 is used for checking.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_bp_dropx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t mark                    : 6;       /**< Number of 8B ticks to reserve in the RX FIFO.
+                                                         When the FIFO exceeds this count, packets will
+                                                         be dropped and not buffered.
+                                                         MARK should typically be programmed to ports+1.
+                                                         Failure to program correctly can lead to system
+                                                         instability.
+                                                         Reset value for RGMII mode = 2
+                                                         Reset value for Spi4 mode  = 17 */
+#else
+        uint64_t mark                    : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn30xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn31xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn38xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn38xxp2;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn50xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn52xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn52xxp1;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn56xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn56xxp1;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn58xx;
+    struct cvmx_gmxx_rx_bp_dropx_s       cn58xxp1;
+} cvmx_gmxx_rx_bp_dropx_t;
+
+
+/**
+ * cvmx_gmx#_rx_bp_off#
+ *
+ * GMX_RX_BP_OFF = Lowater mark for packet drop
+ *
+ *
+ * Notes:
+ * In XAUI mode, prt0 is used for checking.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_bp_offx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t mark                    : 6;       /**< Water mark (8B ticks) to deassert backpressure */
+#else
+        uint64_t mark                    : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_bp_offx_s        cn30xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn31xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn38xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn38xxp2;
+    struct cvmx_gmxx_rx_bp_offx_s        cn50xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn52xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn52xxp1;
+    struct cvmx_gmxx_rx_bp_offx_s        cn56xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn56xxp1;
+    struct cvmx_gmxx_rx_bp_offx_s        cn58xx;
+    struct cvmx_gmxx_rx_bp_offx_s        cn58xxp1;
+} cvmx_gmxx_rx_bp_offx_t;
+
+
+/**
+ * cvmx_gmx#_rx_bp_on#
+ *
+ * GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
+ *
+ *
+ * Notes:
+ * In XAUI mode, prt0 is used for checking.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_bp_onx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t mark                    : 9;       /**< Hiwater mark (8B ticks) for backpressure.
+                                                         In RGMII mode, the backpressure is given per
+                                                         port.  In Spi4 mode, the backpressure is for the
+                                                         entire interface.  GMX_RX_BP_ON must satisfy
+                                                         BP_OFF <= BP_ON < (FIFO_SIZE - BP_DROP)
+                                                         The reset value is half the FIFO.
+                                                         Reset value RGMII mode = 0x40  (512bytes)
+                                                         Reset value Spi4 mode  = 0x100 (2048bytes)
+                                                         A value of zero will immediately assert back
+                                                         pressure. */
+#else
+        uint64_t mark                    : 9;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_bp_onx_s         cn30xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn31xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn38xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn38xxp2;
+    struct cvmx_gmxx_rx_bp_onx_s         cn50xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn52xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn52xxp1;
+    struct cvmx_gmxx_rx_bp_onx_s         cn56xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn56xxp1;
+    struct cvmx_gmxx_rx_bp_onx_s         cn58xx;
+    struct cvmx_gmxx_rx_bp_onx_s         cn58xxp1;
+} cvmx_gmxx_rx_bp_onx_t;
+
+
+/**
+ * cvmx_gmx#_rx_hg2_status
+ *
+ * ** HG2 message CSRs
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_hg2_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t phtim2go                : 16;      /**< Physical time to go for removal of physical link
+                                                         pause. Initial value from received HiGig2 msg pkt
+                                                         Non-zero only when physical back pressure active */
+        uint64_t xof                     : 16;      /**< 16 bit xof back pressure vector from HiGig2 msg pkt
+                                                         or from CBFC packets.
+                                                         Non-zero only when logical back pressure is active
+                                                         All bits will be 0 when LGTIM2GO=0 */
+        uint64_t lgtim2go                : 16;      /**< Logical packet flow back pressure time remaining
+                                                         Initial value set from xof time field of HiGig2
+                                                         message packet received or a function of the
+                                                         enabled and current timers for CBFC packets.
+                                                         Non-zero only when logical back pressure is active */
+#else
+        uint64_t lgtim2go                : 16;
+        uint64_t xof                     : 16;
+        uint64_t phtim2go                : 16;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_hg2_status_s     cn52xx;
+    struct cvmx_gmxx_rx_hg2_status_s     cn52xxp1;
+    struct cvmx_gmxx_rx_hg2_status_s     cn56xx;
+} cvmx_gmxx_rx_hg2_status_t;
+
+
+/**
+ * cvmx_gmx#_rx_pass_en
+ *
+ * GMX_RX_PASS_EN = Packet pass through mode enable
+ * 
+ * When both Octane ports are running in Spi4 mode, packets can be directly
+ * passed from one SPX interface to the other without being processed by the
+ * core or PP's.  The register has one bit for each port to enable the pass
+ * through feature.
+ *
+ * Notes:
+ * (1) Can only be used in dual Spi4 configs
+ * 
+ * (2) The mapped pass through output port cannot be the destination port for
+ *     any Octane core traffic.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_pass_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t en                      : 16;      /**< Which ports to configure in pass through mode */
+#else
+        uint64_t en                      : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_pass_en_s        cn38xx;
+    struct cvmx_gmxx_rx_pass_en_s        cn38xxp2;
+    struct cvmx_gmxx_rx_pass_en_s        cn58xx;
+    struct cvmx_gmxx_rx_pass_en_s        cn58xxp1;
+} cvmx_gmxx_rx_pass_en_t;
+
+
+/**
+ * cvmx_gmx#_rx_pass_map#
+ *
+ * GMX_RX_PASS_MAP = Packet pass through port map
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_pass_mapx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t dprt                    : 4;       /**< Destination port to map Spi pass through traffic */
+#else
+        uint64_t dprt                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_pass_mapx_s      cn38xx;
+    struct cvmx_gmxx_rx_pass_mapx_s      cn38xxp2;
+    struct cvmx_gmxx_rx_pass_mapx_s      cn58xx;
+    struct cvmx_gmxx_rx_pass_mapx_s      cn58xxp1;
+} cvmx_gmxx_rx_pass_mapx_t;
+
+
+/**
+ * cvmx_gmx#_rx_prt_info
+ *
+ * GMX_RX_PRT_INFO = Report the RX status for port
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_prt_info_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t drop                    : 16;      /**< Per port indication that data was dropped
+                                                         (PASS3 only) */
+        uint64_t commit                  : 16;      /**< Per port indication that SOP was accepted
+                                                         (PASS3 only) */
+#else
+        uint64_t commit                  : 16;
+        uint64_t drop                    : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_prt_info_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t drop                    : 3;       /**< Per port indication that data was dropped */
+        uint64_t reserved_3_15           : 13;
+        uint64_t commit                  : 3;       /**< Per port indication that SOP was accepted */
+#else
+        uint64_t commit                  : 3;
+        uint64_t reserved_3_15           : 13;
+        uint64_t drop                    : 3;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_rx_prt_info_cn30xx  cn31xx;
+    struct cvmx_gmxx_rx_prt_info_s       cn38xx;
+    struct cvmx_gmxx_rx_prt_info_cn30xx  cn50xx;
+    struct cvmx_gmxx_rx_prt_info_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t drop                    : 4;       /**< Per port indication that data was dropped */
+        uint64_t reserved_4_15           : 12;
+        uint64_t commit                  : 4;       /**< Per port indication that SOP was accepted */
+#else
+        uint64_t commit                  : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t drop                    : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_rx_prt_info_cn52xx  cn52xxp1;
+    struct cvmx_gmxx_rx_prt_info_cn52xx  cn56xx;
+    struct cvmx_gmxx_rx_prt_info_cn52xx  cn56xxp1;
+    struct cvmx_gmxx_rx_prt_info_s       cn58xx;
+    struct cvmx_gmxx_rx_prt_info_s       cn58xxp1;
+} cvmx_gmxx_rx_prt_info_t;
+
+
+/**
+ * cvmx_gmx#_rx_prts
+ *
+ * GMX_RX_PRTS = Number of FIFOs to carve the RX buffer into
+ *
+ *
+ * Notes:
+ * GMX_RX_PRTS is unused in XAUI mode since the RX buffer is always unified.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_prts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t prts                    : 3;       /**< In RGMII mode, the RX buffer can be carved into
+                                                         several logical buffers depending on the number
+                                                         or implemented ports.
+                                                         0 or 1 port  = 512ticks / 4096bytes
+                                                         2 ports      = 256ticks / 2048bytes
+                                                         3 or 4 ports = 128ticks / 1024bytes */
+#else
+        uint64_t prts                    : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_prts_s           cn30xx;
+    struct cvmx_gmxx_rx_prts_s           cn31xx;
+    struct cvmx_gmxx_rx_prts_s           cn38xx;
+    struct cvmx_gmxx_rx_prts_s           cn38xxp2;
+    struct cvmx_gmxx_rx_prts_s           cn50xx;
+    struct cvmx_gmxx_rx_prts_s           cn52xx;
+    struct cvmx_gmxx_rx_prts_s           cn52xxp1;
+    struct cvmx_gmxx_rx_prts_s           cn56xx;
+    struct cvmx_gmxx_rx_prts_s           cn56xxp1;
+    struct cvmx_gmxx_rx_prts_s           cn58xx;
+    struct cvmx_gmxx_rx_prts_s           cn58xxp1;
+} cvmx_gmxx_rx_prts_t;
+
+
+/**
+ * cvmx_gmx#_rx_tx_status
+ *
+ * GMX_RX_TX_STATUS = GMX RX/TX Status
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_tx_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t tx                      : 3;       /**< Transmit data since last read */
+        uint64_t reserved_3_3            : 1;
+        uint64_t rx                      : 3;       /**< Receive data since last read */
+#else
+        uint64_t rx                      : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t tx                      : 3;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_tx_status_s      cn30xx;
+    struct cvmx_gmxx_rx_tx_status_s      cn31xx;
+    struct cvmx_gmxx_rx_tx_status_s      cn50xx;
+} cvmx_gmxx_rx_tx_status_t;
+
+
+/**
+ * cvmx_gmx#_rx_xaui_bad_col
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_xaui_bad_col_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t val                     : 1;       /**< Set when GMX_RX_INT_REG[PCTERR] is set.
+                                                         (XAUI mode only) */
+        uint64_t state                   : 3;       /**< When GMX_RX_INT_REG[PCTERR] is set, STATE will
+                                                         conatin the receive state at the time of the
+                                                         error.
+                                                         (XAUI mode only) */
+        uint64_t lane_rxc                : 4;       /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXC will
+                                                         conatin the XAUI column at the time of the error.
+                                                         (XAUI mode only) */
+        uint64_t lane_rxd                : 32;      /**< When GMX_RX_INT_REG[PCTERR] is set, LANE_RXD will
+                                                         conatin the XAUI column at the time of the error.
+                                                         (XAUI mode only) */
+#else
+        uint64_t lane_rxd                : 32;
+        uint64_t lane_rxc                : 4;
+        uint64_t state                   : 3;
+        uint64_t val                     : 1;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_xaui_bad_col_s   cn52xx;
+    struct cvmx_gmxx_rx_xaui_bad_col_s   cn52xxp1;
+    struct cvmx_gmxx_rx_xaui_bad_col_s   cn56xx;
+    struct cvmx_gmxx_rx_xaui_bad_col_s   cn56xxp1;
+} cvmx_gmxx_rx_xaui_bad_col_t;
+
+
+/**
+ * cvmx_gmx#_rx_xaui_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_rx_xaui_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t status                  : 2;       /**< Link Status
+                                                         0=Link OK
+                                                         1=Local Fault
+                                                         2=Remote Fault
+                                                         3=Reserved
+                                                         (XAUI mode only) */
+#else
+        uint64_t status                  : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_gmxx_rx_xaui_ctl_s       cn52xx;
+    struct cvmx_gmxx_rx_xaui_ctl_s       cn52xxp1;
+    struct cvmx_gmxx_rx_xaui_ctl_s       cn56xx;
+    struct cvmx_gmxx_rx_xaui_ctl_s       cn56xxp1;
+} cvmx_gmxx_rx_xaui_ctl_t;
+
+
+/**
+ * cvmx_gmx#_smac#
+ *
+ * GMX_SMAC = Packet SMAC
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_smacx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t smac                    : 48;      /**< The SMAC field is used for generating and
+                                                         accepting Control Pause packets */
+#else
+        uint64_t smac                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_smacx_s             cn30xx;
+    struct cvmx_gmxx_smacx_s             cn31xx;
+    struct cvmx_gmxx_smacx_s             cn38xx;
+    struct cvmx_gmxx_smacx_s             cn38xxp2;
+    struct cvmx_gmxx_smacx_s             cn50xx;
+    struct cvmx_gmxx_smacx_s             cn52xx;
+    struct cvmx_gmxx_smacx_s             cn52xxp1;
+    struct cvmx_gmxx_smacx_s             cn56xx;
+    struct cvmx_gmxx_smacx_s             cn56xxp1;
+    struct cvmx_gmxx_smacx_s             cn58xx;
+    struct cvmx_gmxx_smacx_s             cn58xxp1;
+} cvmx_gmxx_smacx_t;
+
+
+/**
+ * cvmx_gmx#_stat_bp
+ *
+ * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_stat_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t bp                      : 1;       /**< Current BP state */
+        uint64_t cnt                     : 16;      /**< Number of cycles that BP has been asserted
+                                                         Saturating counter */
+#else
+        uint64_t cnt                     : 16;
+        uint64_t bp                      : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_gmxx_stat_bp_s           cn30xx;
+    struct cvmx_gmxx_stat_bp_s           cn31xx;
+    struct cvmx_gmxx_stat_bp_s           cn38xx;
+    struct cvmx_gmxx_stat_bp_s           cn38xxp2;
+    struct cvmx_gmxx_stat_bp_s           cn50xx;
+    struct cvmx_gmxx_stat_bp_s           cn52xx;
+    struct cvmx_gmxx_stat_bp_s           cn52xxp1;
+    struct cvmx_gmxx_stat_bp_s           cn56xx;
+    struct cvmx_gmxx_stat_bp_s           cn56xxp1;
+    struct cvmx_gmxx_stat_bp_s           cn58xx;
+    struct cvmx_gmxx_stat_bp_s           cn58xxp1;
+} cvmx_gmxx_stat_bp_t;
+
+
+/**
+ * cvmx_gmx#_tx#_append
+ *
+ * GMX_TX_APPEND = Packet TX Append Control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_append_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t force_fcs               : 1;       /**< Append the Ethernet FCS on each pause packet
+                                                         When FCS is clear
+                                                         This implies that FCS==0 and PAD==0
+                                                         (PASS2 only) */
+        uint64_t fcs                     : 1;       /**< Append the Ethernet FCS on each packet */
+        uint64_t pad                     : 1;       /**< Append PAD bytes such that min sized */
+        uint64_t preamble                : 1;       /**< Prepend the Ethernet preamble on each transfer */
+#else
+        uint64_t preamble                : 1;
+        uint64_t pad                     : 1;
+        uint64_t fcs                     : 1;
+        uint64_t force_fcs               : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_append_s        cn30xx;
+    struct cvmx_gmxx_txx_append_s        cn31xx;
+    struct cvmx_gmxx_txx_append_s        cn38xx;
+    struct cvmx_gmxx_txx_append_s        cn38xxp2;
+    struct cvmx_gmxx_txx_append_s        cn50xx;
+    struct cvmx_gmxx_txx_append_s        cn52xx;
+    struct cvmx_gmxx_txx_append_s        cn52xxp1;
+    struct cvmx_gmxx_txx_append_s        cn56xx;
+    struct cvmx_gmxx_txx_append_s        cn56xxp1;
+    struct cvmx_gmxx_txx_append_s        cn58xx;
+    struct cvmx_gmxx_txx_append_s        cn58xxp1;
+} cvmx_gmxx_txx_append_t;
+
+
+/**
+ * cvmx_gmx#_tx#_burst
+ *
+ * GMX_TX_BURST = Packet TX Burst Counter
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_burst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t burst                   : 16;      /**< Burst (refer to 802.3 to set correctly)
+                                                         10/100Mbs: 0x0
+                                                         1000Mbs:   0x2000 */
+#else
+        uint64_t burst                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_burst_s         cn30xx;
+    struct cvmx_gmxx_txx_burst_s         cn31xx;
+    struct cvmx_gmxx_txx_burst_s         cn38xx;
+    struct cvmx_gmxx_txx_burst_s         cn38xxp2;
+    struct cvmx_gmxx_txx_burst_s         cn50xx;
+    struct cvmx_gmxx_txx_burst_s         cn52xx;
+    struct cvmx_gmxx_txx_burst_s         cn52xxp1;
+    struct cvmx_gmxx_txx_burst_s         cn56xx;
+    struct cvmx_gmxx_txx_burst_s         cn56xxp1;
+    struct cvmx_gmxx_txx_burst_s         cn58xx;
+    struct cvmx_gmxx_txx_burst_s         cn58xxp1;
+} cvmx_gmxx_txx_burst_t;
+
+
+/**
+ * cvmx_gmx#_tx#_cbfc_xoff
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_cbfc_xoff_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t xoff                    : 16;      /**< Which ports to backpressure
+                                                         Do not write in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+        uint64_t xoff                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_cbfc_xoff_s     cn52xx;
+    struct cvmx_gmxx_txx_cbfc_xoff_s     cn56xx;
+} cvmx_gmxx_txx_cbfc_xoff_t;
+
+
+/**
+ * cvmx_gmx#_tx#_cbfc_xon
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_cbfc_xon_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t xon                     : 16;      /**< Which ports to stop backpressure
+                                                         Do not write in HiGig2 mode i.e. when
+                                                         GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                         GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+        uint64_t xon                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_cbfc_xon_s      cn52xx;
+    struct cvmx_gmxx_txx_cbfc_xon_s      cn56xx;
+} cvmx_gmxx_txx_cbfc_xon_t;
+
+
+/**
+ * cvmx_gmx#_tx#_clk
+ *
+ * Per Port
+ * 
+ * 
+ * GMX_TX_CLK = RGMII TX Clock Generation Register
+ *
+ * Notes:
+ * Programming Restrictions:
+ *  (1) In RGMII mode, if GMX_PRT_CFG[SPEED]==0, then CLK_CNT must be > 1.
+ *  (2) In MII mode, CLK_CNT == 1
+ *  (3) In RGMII or GMII mode, if CLK_CNT==0, Octeon will not generate a tx clock.
+ * 
+ * RGMII Example:
+ *  Given a 125MHz PLL reference clock...
+ *   CLK_CNT ==  1 ==> 125.0MHz TXC clock period (8ns* 1)
+ *   CLK_CNT ==  5 ==>  25.0MHz TXC clock period (8ns* 5)
+ *   CLK_CNT == 50 ==>   2.5MHz TXC clock period (8ns*50)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_clk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t clk_cnt                 : 6;       /**< Controls the RGMII TXC frequency
+                                                         When PLL is used, TXC(phase) =
+                                                          spi4_tx_pll_ref_clk(period)/2*CLK_CNT
+                                                         When PLL bypass is used, TXC(phase) =
+                                                          spi4_tx_pll_ref_clk(period)*2*CLK_CNT
+                                                         NOTE: CLK_CNT==0 will not generate any clock
+                                                         if CLK_CNT > 1 if GMX_PRT_CFG[SPEED]==0 */
+#else
+        uint64_t clk_cnt                 : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_clk_s           cn30xx;
+    struct cvmx_gmxx_txx_clk_s           cn31xx;
+    struct cvmx_gmxx_txx_clk_s           cn38xx;
+    struct cvmx_gmxx_txx_clk_s           cn38xxp2;
+    struct cvmx_gmxx_txx_clk_s           cn50xx;
+    struct cvmx_gmxx_txx_clk_s           cn58xx;
+    struct cvmx_gmxx_txx_clk_s           cn58xxp1;
+} cvmx_gmxx_txx_clk_t;
+
+
+/**
+ * cvmx_gmx#_tx#_ctl
+ *
+ * GMX_TX_CTL = TX Control register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t xsdef_en                : 1;       /**< Enables the excessive deferral check for stats
+                                                         and interrupts
+                                                         (PASS2 only) */
+        uint64_t xscol_en                : 1;       /**< Enables the excessive collision check for stats
+                                                         and interrupts
+                                                         (PASS2 only) */
+#else
+        uint64_t xscol_en                : 1;
+        uint64_t xsdef_en                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_ctl_s           cn30xx;
+    struct cvmx_gmxx_txx_ctl_s           cn31xx;
+    struct cvmx_gmxx_txx_ctl_s           cn38xx;
+    struct cvmx_gmxx_txx_ctl_s           cn38xxp2;
+    struct cvmx_gmxx_txx_ctl_s           cn50xx;
+    struct cvmx_gmxx_txx_ctl_s           cn52xx;
+    struct cvmx_gmxx_txx_ctl_s           cn52xxp1;
+    struct cvmx_gmxx_txx_ctl_s           cn56xx;
+    struct cvmx_gmxx_txx_ctl_s           cn56xxp1;
+    struct cvmx_gmxx_txx_ctl_s           cn58xx;
+    struct cvmx_gmxx_txx_ctl_s           cn58xxp1;
+} cvmx_gmxx_txx_ctl_t;
+
+
+/**
+ * cvmx_gmx#_tx#_min_pkt
+ *
+ * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_min_pkt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t min_size                : 8;       /**< Min frame in bytes before the FCS is applied
+                                                         Padding is only appened when GMX_TX_APPEND[PAD]
+                                                         for the coresponding RGMII port is set. */
+#else
+        uint64_t min_size                : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_min_pkt_s       cn30xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn31xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn38xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn38xxp2;
+    struct cvmx_gmxx_txx_min_pkt_s       cn50xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn52xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn52xxp1;
+    struct cvmx_gmxx_txx_min_pkt_s       cn56xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn56xxp1;
+    struct cvmx_gmxx_txx_min_pkt_s       cn58xx;
+    struct cvmx_gmxx_txx_min_pkt_s       cn58xxp1;
+} cvmx_gmxx_txx_min_pkt_t;
+
+
+/**
+ * cvmx_gmx#_tx#_pause_pkt_interval
+ *
+ * GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent
+ *
+ *
+ * Notes:
+ * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ * 
+ * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ * 
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ * 
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t interval                : 16;      /**< Arbitrate for a pause packet every (INTERVAL*512)
+                                                         bit-times.
+                                                         Normally, 0 < INTERVAL < GMX_TX_PAUSE_PKT_TIME
+                                                         INTERVAL=0, will only send a single PAUSE packet
+                                                         for each backpressure event */
+#else
+        uint64_t interval                : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
+    struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
+} cvmx_gmxx_txx_pause_pkt_interval_t;
+
+
+/**
+ * cvmx_gmx#_tx#_pause_pkt_time
+ *
+ * GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field
+ *
+ *
+ * Notes:
+ * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
+ * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
+ * designer.  It is suggested that TIME be much greater than INTERVAL and
+ * GMX_TX_PAUSE_ZERO[SEND] be set.  This allows a periodic refresh of the PAUSE
+ * count and then when the backpressure condition is lifted, a PAUSE packet
+ * with TIME==0 will be sent indicating that Octane is ready for additional
+ * data.
+ * 
+ * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
+ * suggested that TIME and INTERVAL are programmed such that they satisify the
+ * following rule...
+ * 
+ *    INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
+ * 
+ * where largest_pkt_size is that largest packet that the system can send
+ * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
+ * of the PAUSE packet (normally 64B).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_pause_pkt_time_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t time                    : 16;      /**< The pause_time field placed is outbnd pause pkts
+                                                         pause_time is in 512 bit-times
+                                                         Normally, TIME > GMX_TX_PAUSE_PKT_INTERVAL */
+#else
+        uint64_t time                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
+    struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
+} cvmx_gmxx_txx_pause_pkt_time_t;
+
+
+/**
+ * cvmx_gmx#_tx#_pause_togo
+ *
+ * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_pause_togo_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t msg_time                : 16;      /**< Amount of time remaining to backpressure
+                                                         From the higig2 physical message pause timer
+                                                         (only valid on port0) */
+        uint64_t time                    : 16;      /**< Amount of time remaining to backpressure */
+#else
+        uint64_t time                    : 16;
+        uint64_t msg_time                : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t time                    : 16;      /**< Amount of time remaining to backpressure */
+#else
+        uint64_t time                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
+    struct cvmx_gmxx_txx_pause_togo_s    cn52xx;
+    struct cvmx_gmxx_txx_pause_togo_s    cn52xxp1;
+    struct cvmx_gmxx_txx_pause_togo_s    cn56xx;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
+    struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
+} cvmx_gmxx_txx_pause_togo_t;
+
+
+/**
+ * cvmx_gmx#_tx#_pause_zero
+ *
+ * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_pause_zero_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t send                    : 1;       /**< When backpressure condition clear, send PAUSE
+                                                         packet with pause_time of zero to enable the
+                                                         channel */
+#else
+        uint64_t send                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_pause_zero_s    cn30xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn31xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn38xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn38xxp2;
+    struct cvmx_gmxx_txx_pause_zero_s    cn50xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn52xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn52xxp1;
+    struct cvmx_gmxx_txx_pause_zero_s    cn56xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn56xxp1;
+    struct cvmx_gmxx_txx_pause_zero_s    cn58xx;
+    struct cvmx_gmxx_txx_pause_zero_s    cn58xxp1;
+} cvmx_gmxx_txx_pause_zero_t;
+
+
+/**
+ * cvmx_gmx#_tx#_sgmii_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_sgmii_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t align                   : 1;       /**< Align the transmission to even cycles
+                                                         0 = Data can be sent on any cycle
+                                                             Possible to for the TX PCS machine to drop
+                                                             first byte of preamble
+                                                         1 = Data will only be sent on even cycles
+                                                             There will be no loss of data
+                                                         (SGMII/1000Base-X only) */
+#else
+        uint64_t align                   : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_sgmii_ctl_s     cn52xx;
+    struct cvmx_gmxx_txx_sgmii_ctl_s     cn52xxp1;
+    struct cvmx_gmxx_txx_sgmii_ctl_s     cn56xx;
+    struct cvmx_gmxx_txx_sgmii_ctl_s     cn56xxp1;
+} cvmx_gmxx_txx_sgmii_ctl_t;
+
+
+/**
+ * cvmx_gmx#_tx#_slot
+ *
+ * GMX_TX_SLOT = Packet TX Slottime Counter
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_slot_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t slot                    : 10;      /**< Slottime (refer to 802.3 to set correctly)
+                                                         10/100Mbs: 0x40
+                                                         1000Mbs:   0x200 */
+#else
+        uint64_t slot                    : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_slot_s          cn30xx;
+    struct cvmx_gmxx_txx_slot_s          cn31xx;
+    struct cvmx_gmxx_txx_slot_s          cn38xx;
+    struct cvmx_gmxx_txx_slot_s          cn38xxp2;
+    struct cvmx_gmxx_txx_slot_s          cn50xx;
+    struct cvmx_gmxx_txx_slot_s          cn52xx;
+    struct cvmx_gmxx_txx_slot_s          cn52xxp1;
+    struct cvmx_gmxx_txx_slot_s          cn56xx;
+    struct cvmx_gmxx_txx_slot_s          cn56xxp1;
+    struct cvmx_gmxx_txx_slot_s          cn58xx;
+    struct cvmx_gmxx_txx_slot_s          cn58xxp1;
+} cvmx_gmxx_txx_slot_t;
+
+
+/**
+ * cvmx_gmx#_tx#_soft_pause
+ *
+ * GMX_TX_SOFT_PAUSE = Packet TX Software Pause
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_soft_pause_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t time                    : 16;      /**< Back off the TX bus for (TIME*512) bit-times */
+#else
+        uint64_t time                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_soft_pause_s    cn30xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn31xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn38xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn38xxp2;
+    struct cvmx_gmxx_txx_soft_pause_s    cn50xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn52xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn52xxp1;
+    struct cvmx_gmxx_txx_soft_pause_s    cn56xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn56xxp1;
+    struct cvmx_gmxx_txx_soft_pause_s    cn58xx;
+    struct cvmx_gmxx_txx_soft_pause_s    cn58xxp1;
+} cvmx_gmxx_txx_soft_pause_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat0
+ *
+ * GMX_TX_STAT0 = GMX_TX_STATS_XSDEF / GMX_TX_STATS_XSCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t xsdef                   : 32;      /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive deferal */
+        uint64_t xscol                   : 32;      /**< Number of packets dropped (never successfully
+                                                         sent) due to excessive collision.  Defined by
+                                                         GMX_TX_COL_ATTEMPT[LIMIT]. */
+#else
+        uint64_t xscol                   : 32;
+        uint64_t xsdef                   : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat0_s         cn30xx;
+    struct cvmx_gmxx_txx_stat0_s         cn31xx;
+    struct cvmx_gmxx_txx_stat0_s         cn38xx;
+    struct cvmx_gmxx_txx_stat0_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat0_s         cn50xx;
+    struct cvmx_gmxx_txx_stat0_s         cn52xx;
+    struct cvmx_gmxx_txx_stat0_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat0_s         cn56xx;
+    struct cvmx_gmxx_txx_stat0_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat0_s         cn58xx;
+    struct cvmx_gmxx_txx_stat0_s         cn58xxp1;
+} cvmx_gmxx_txx_stat0_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat1
+ *
+ * GMX_TX_STAT1 = GMX_TX_STATS_SCOL  / GMX_TX_STATS_MCOL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t scol                    : 32;      /**< Number of packets sent with a single collision */
+        uint64_t mcol                    : 32;      /**< Number of packets sent with multiple collisions
+                                                         but < GMX_TX_COL_ATTEMPT[LIMIT]. */
+#else
+        uint64_t mcol                    : 32;
+        uint64_t scol                    : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat1_s         cn30xx;
+    struct cvmx_gmxx_txx_stat1_s         cn31xx;
+    struct cvmx_gmxx_txx_stat1_s         cn38xx;
+    struct cvmx_gmxx_txx_stat1_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat1_s         cn50xx;
+    struct cvmx_gmxx_txx_stat1_s         cn52xx;
+    struct cvmx_gmxx_txx_stat1_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat1_s         cn56xx;
+    struct cvmx_gmxx_txx_stat1_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat1_s         cn58xx;
+    struct cvmx_gmxx_txx_stat1_s         cn58xxp1;
+} cvmx_gmxx_txx_stat1_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat2
+ *
+ * GMX_TX_STAT2 = GMX_TX_STATS_OCTS
+ *
+ *
+ * Notes:
+ * - Octect counts are the sum of all data transmitted on the wire including
+ *   packet data, pad bytes, fcs bytes, pause bytes, and jam bytes.  The octect
+ *   counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t octs                    : 48;      /**< Number of total octets sent on the interface.
+                                                         Does not count octets from frames that were
+                                                         truncated due to collisions in halfdup mode. */
+#else
+        uint64_t octs                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat2_s         cn30xx;
+    struct cvmx_gmxx_txx_stat2_s         cn31xx;
+    struct cvmx_gmxx_txx_stat2_s         cn38xx;
+    struct cvmx_gmxx_txx_stat2_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat2_s         cn50xx;
+    struct cvmx_gmxx_txx_stat2_s         cn52xx;
+    struct cvmx_gmxx_txx_stat2_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat2_s         cn56xx;
+    struct cvmx_gmxx_txx_stat2_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat2_s         cn58xx;
+    struct cvmx_gmxx_txx_stat2_s         cn58xxp1;
+} cvmx_gmxx_txx_stat2_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat3
+ *
+ * GMX_TX_STAT3 = GMX_TX_STATS_PKTS
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pkts                    : 32;      /**< Number of total frames sent on the interface.
+                                                         Does not count frames that were truncated due to
+                                                          collisions in halfdup mode. */
+#else
+        uint64_t pkts                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat3_s         cn30xx;
+    struct cvmx_gmxx_txx_stat3_s         cn31xx;
+    struct cvmx_gmxx_txx_stat3_s         cn38xx;
+    struct cvmx_gmxx_txx_stat3_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat3_s         cn50xx;
+    struct cvmx_gmxx_txx_stat3_s         cn52xx;
+    struct cvmx_gmxx_txx_stat3_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat3_s         cn56xx;
+    struct cvmx_gmxx_txx_stat3_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat3_s         cn58xx;
+    struct cvmx_gmxx_txx_stat3_s         cn58xxp1;
+} cvmx_gmxx_txx_stat3_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat4
+ *
+ * GMX_TX_STAT4 = GMX_TX_STATS_HIST1 (64) / GMX_TX_STATS_HIST0 (<64)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist1                   : 32;      /**< Number of packets sent with an octet count of 64. */
+        uint64_t hist0                   : 32;      /**< Number of packets sent with an octet count
+                                                         of < 64. */
+#else
+        uint64_t hist0                   : 32;
+        uint64_t hist1                   : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat4_s         cn30xx;
+    struct cvmx_gmxx_txx_stat4_s         cn31xx;
+    struct cvmx_gmxx_txx_stat4_s         cn38xx;
+    struct cvmx_gmxx_txx_stat4_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat4_s         cn50xx;
+    struct cvmx_gmxx_txx_stat4_s         cn52xx;
+    struct cvmx_gmxx_txx_stat4_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat4_s         cn56xx;
+    struct cvmx_gmxx_txx_stat4_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat4_s         cn58xx;
+    struct cvmx_gmxx_txx_stat4_s         cn58xxp1;
+} cvmx_gmxx_txx_stat4_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat5
+ *
+ * GMX_TX_STAT5 = GMX_TX_STATS_HIST3 (128- 255) / GMX_TX_STATS_HIST2 (65- 127)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist3                   : 32;      /**< Number of packets sent with an octet count of
+                                                         128 - 255. */
+        uint64_t hist2                   : 32;      /**< Number of packets sent with an octet count of
+                                                         65 - 127. */
+#else
+        uint64_t hist2                   : 32;
+        uint64_t hist3                   : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat5_s         cn30xx;
+    struct cvmx_gmxx_txx_stat5_s         cn31xx;
+    struct cvmx_gmxx_txx_stat5_s         cn38xx;
+    struct cvmx_gmxx_txx_stat5_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat5_s         cn50xx;
+    struct cvmx_gmxx_txx_stat5_s         cn52xx;
+    struct cvmx_gmxx_txx_stat5_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat5_s         cn56xx;
+    struct cvmx_gmxx_txx_stat5_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat5_s         cn58xx;
+    struct cvmx_gmxx_txx_stat5_s         cn58xxp1;
+} cvmx_gmxx_txx_stat5_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat6
+ *
+ * GMX_TX_STAT6 = GMX_TX_STATS_HIST5 (512-1023) / GMX_TX_STATS_HIST4 (256-511)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist5                   : 32;      /**< Number of packets sent with an octet count of
+                                                         512 - 1023. */
+        uint64_t hist4                   : 32;      /**< Number of packets sent with an octet count of
+                                                         256 - 511. */
+#else
+        uint64_t hist4                   : 32;
+        uint64_t hist5                   : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat6_s         cn30xx;
+    struct cvmx_gmxx_txx_stat6_s         cn31xx;
+    struct cvmx_gmxx_txx_stat6_s         cn38xx;
+    struct cvmx_gmxx_txx_stat6_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat6_s         cn50xx;
+    struct cvmx_gmxx_txx_stat6_s         cn52xx;
+    struct cvmx_gmxx_txx_stat6_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat6_s         cn56xx;
+    struct cvmx_gmxx_txx_stat6_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat6_s         cn58xx;
+    struct cvmx_gmxx_txx_stat6_s         cn58xxp1;
+} cvmx_gmxx_txx_stat6_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat7
+ *
+ * GMX_TX_STAT7 = GMX_TX_STATS_HIST7 (1024-1518) / GMX_TX_STATS_HIST6 (>1518)
+ *
+ *
+ * Notes:
+ * - Packet length is the sum of all data transmitted on the wire for the given
+ *   packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
+ *   bytes.  The octect counts do not include PREAMBLE byte or EXTEND cycles.
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t hist7                   : 32;      /**< Number of packets sent with an octet count
+                                                         of > 1518. */
+        uint64_t hist6                   : 32;      /**< Number of packets sent with an octet count of
+                                                         1024 - 1518. */
+#else
+        uint64_t hist6                   : 32;
+        uint64_t hist7                   : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat7_s         cn30xx;
+    struct cvmx_gmxx_txx_stat7_s         cn31xx;
+    struct cvmx_gmxx_txx_stat7_s         cn38xx;
+    struct cvmx_gmxx_txx_stat7_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat7_s         cn50xx;
+    struct cvmx_gmxx_txx_stat7_s         cn52xx;
+    struct cvmx_gmxx_txx_stat7_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat7_s         cn56xx;
+    struct cvmx_gmxx_txx_stat7_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat7_s         cn58xx;
+    struct cvmx_gmxx_txx_stat7_s         cn58xxp1;
+} cvmx_gmxx_txx_stat7_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat8
+ *
+ * GMX_TX_STAT8 = GMX_TX_STATS_MCST  / GMX_TX_STATS_BCST
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
+ *   packet.  GMX assumes that the DMAC lies in the first 6 bytes of the packet
+ *   as per the 802.3 frame definition.  If the system requires additional data
+ *   before the L2 header, then the MCST and BCST counters may not reflect
+ *   reality and should be ignored by software.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat8_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mcst                    : 32;      /**< Number of packets sent to multicast DMAC.
+                                                         Does not include BCST packets. */
+        uint64_t bcst                    : 32;      /**< Number of packets sent to broadcast DMAC.
+                                                         Does not include MCST packets. */
+#else
+        uint64_t bcst                    : 32;
+        uint64_t mcst                    : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat8_s         cn30xx;
+    struct cvmx_gmxx_txx_stat8_s         cn31xx;
+    struct cvmx_gmxx_txx_stat8_s         cn38xx;
+    struct cvmx_gmxx_txx_stat8_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat8_s         cn50xx;
+    struct cvmx_gmxx_txx_stat8_s         cn52xx;
+    struct cvmx_gmxx_txx_stat8_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat8_s         cn56xx;
+    struct cvmx_gmxx_txx_stat8_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat8_s         cn58xx;
+    struct cvmx_gmxx_txx_stat8_s         cn58xxp1;
+} cvmx_gmxx_txx_stat8_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stat9
+ *
+ * GMX_TX_STAT9 = GMX_TX_STATS_UNDFLW / GMX_TX_STATS_CTL
+ *
+ *
+ * Notes:
+ * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
+ * - Counters will wrap
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stat9_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t undflw                  : 32;      /**< Number of underflow packets */
+        uint64_t ctl                     : 32;      /**< Number of Control packets (PAUSE flow control)
+                                                         generated by GMX.  It does not include control
+                                                         packets forwarded or generated by the PP's. */
+#else
+        uint64_t ctl                     : 32;
+        uint64_t undflw                  : 32;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stat9_s         cn30xx;
+    struct cvmx_gmxx_txx_stat9_s         cn31xx;
+    struct cvmx_gmxx_txx_stat9_s         cn38xx;
+    struct cvmx_gmxx_txx_stat9_s         cn38xxp2;
+    struct cvmx_gmxx_txx_stat9_s         cn50xx;
+    struct cvmx_gmxx_txx_stat9_s         cn52xx;
+    struct cvmx_gmxx_txx_stat9_s         cn52xxp1;
+    struct cvmx_gmxx_txx_stat9_s         cn56xx;
+    struct cvmx_gmxx_txx_stat9_s         cn56xxp1;
+    struct cvmx_gmxx_txx_stat9_s         cn58xx;
+    struct cvmx_gmxx_txx_stat9_s         cn58xxp1;
+} cvmx_gmxx_txx_stat9_t;
+
+
+/**
+ * cvmx_gmx#_tx#_stats_ctl
+ *
+ * GMX_TX_STATS_CTL = TX Stats Control register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_stats_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rd_clr                  : 1;       /**< Stats registers will clear on reads */
+#else
+        uint64_t rd_clr                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn30xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn31xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn38xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn38xxp2;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn50xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn52xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn52xxp1;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn56xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn56xxp1;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn58xx;
+    struct cvmx_gmxx_txx_stats_ctl_s     cn58xxp1;
+} cvmx_gmxx_txx_stats_ctl_t;
+
+
+/**
+ * cvmx_gmx#_tx#_thresh
+ *
+ * Per Port
+ * 
+ * 
+ * GMX_TX_THRESH = Packet TX Threshold
+ *
+ * Notes:
+ * In XAUI mode, prt0 is used for checking.  Since XAUI mode uses a single TX FIFO and is higher data rate, recommended value is 0x80.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_txx_thresh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t cnt                     : 9;       /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                         before sending on the RGMII interface
+                                                         This register should be large enough to prevent
+                                                         underflow on the RGMII interface and must never
+                                                         be set to zero.  This register cannot exceed the
+                                                         the TX FIFO depth which is...
+                                                          GMX_TX_PRTS==0,1:  CNT MAX = 0x100
+                                                          GMX_TX_PRTS==2  :  CNT MAX = 0x080
+                                                          GMX_TX_PRTS==3,4:  CNT MAX = 0x040 */
+#else
+        uint64_t cnt                     : 9;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_gmxx_txx_thresh_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t cnt                     : 7;       /**< Number of 16B ticks to accumulate in the TX FIFO
+                                                         before sending on the RGMII interface
+                                                         This register should be large enough to prevent
+                                                         underflow on the RGMII interface and must never
+                                                         be set below 4.  This register cannot exceed the
+                                                         the TX FIFO depth which is 64 16B entries. */
+#else
+        uint64_t cnt                     : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_txx_thresh_cn30xx   cn31xx;
+    struct cvmx_gmxx_txx_thresh_s        cn38xx;
+    struct cvmx_gmxx_txx_thresh_s        cn38xxp2;
+    struct cvmx_gmxx_txx_thresh_cn30xx   cn50xx;
+    struct cvmx_gmxx_txx_thresh_s        cn52xx;
+    struct cvmx_gmxx_txx_thresh_s        cn52xxp1;
+    struct cvmx_gmxx_txx_thresh_s        cn56xx;
+    struct cvmx_gmxx_txx_thresh_s        cn56xxp1;
+    struct cvmx_gmxx_txx_thresh_s        cn58xx;
+    struct cvmx_gmxx_txx_thresh_s        cn58xxp1;
+} cvmx_gmxx_txx_thresh_t;
+
+
+/**
+ * cvmx_gmx#_tx_bp
+ *
+ * GMX_TX_BP = Packet Interface TX BackPressure Register
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of BP is used.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t bp                      : 4;       /**< Per port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+        uint64_t bp                      : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_bp_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t bp                      : 3;       /**< Per port BackPressure status
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+#else
+        uint64_t bp                      : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_tx_bp_cn30xx        cn31xx;
+    struct cvmx_gmxx_tx_bp_s             cn38xx;
+    struct cvmx_gmxx_tx_bp_s             cn38xxp2;
+    struct cvmx_gmxx_tx_bp_cn30xx        cn50xx;
+    struct cvmx_gmxx_tx_bp_s             cn52xx;
+    struct cvmx_gmxx_tx_bp_s             cn52xxp1;
+    struct cvmx_gmxx_tx_bp_s             cn56xx;
+    struct cvmx_gmxx_tx_bp_s             cn56xxp1;
+    struct cvmx_gmxx_tx_bp_s             cn58xx;
+    struct cvmx_gmxx_tx_bp_s             cn58xxp1;
+} cvmx_gmxx_tx_bp_t;
+
+
+/**
+ * cvmx_gmx#_tx_clk_msk#
+ *
+ * GMX_TX_CLK_MSK = GMX Clock Select
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_clk_mskx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t msk                     : 1;       /**< Write this bit to a 1 when switching clks */
+#else
+        uint64_t msk                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_clk_mskx_s       cn30xx;
+    struct cvmx_gmxx_tx_clk_mskx_s       cn50xx;
+} cvmx_gmxx_tx_clk_mskx_t;
+
+
+/**
+ * cvmx_gmx#_tx_col_attempt
+ *
+ * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_col_attempt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t limit                   : 5;       /**< Collision Attempts */
+#else
+        uint64_t limit                   : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_col_attempt_s    cn30xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn31xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn38xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn38xxp2;
+    struct cvmx_gmxx_tx_col_attempt_s    cn50xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn52xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn52xxp1;
+    struct cvmx_gmxx_tx_col_attempt_s    cn56xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn56xxp1;
+    struct cvmx_gmxx_tx_col_attempt_s    cn58xx;
+    struct cvmx_gmxx_tx_col_attempt_s    cn58xxp1;
+} cvmx_gmxx_tx_col_attempt_t;
+
+
+/**
+ * cvmx_gmx#_tx_corrupt
+ *
+ * GMX_TX_CORRUPT = TX - Corrupt TX packets with the ERR bit set
+ *
+ *
+ * Notes:
+ * Packets sent from PKO with the ERR wire asserted will be corrupted by
+ * the transmitter if CORRUPT[prt] is set (XAUI uses prt==0).
+ * 
+ * Corruption means that GMX will send a bad FCS value.  If GMX_TX_APPEND[FCS]
+ * is clear then no FCS is sent and the GMX cannot corrupt it.  The corrupt FCS
+ * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error
+ * propagation code in XAUI mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_corrupt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t corrupt                 : 4;       /**< Per port error propagation
+                                                         0=Never corrupt packets
+                                                         1=Corrupt packets with ERR */
+#else
+        uint64_t corrupt                 : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_corrupt_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t corrupt                 : 3;       /**< Per port error propagation
+                                                         0=Never corrupt packets
+                                                         1=Corrupt packets with ERR */
+#else
+        uint64_t corrupt                 : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_tx_corrupt_cn30xx   cn31xx;
+    struct cvmx_gmxx_tx_corrupt_s        cn38xx;
+    struct cvmx_gmxx_tx_corrupt_s        cn38xxp2;
+    struct cvmx_gmxx_tx_corrupt_cn30xx   cn50xx;
+    struct cvmx_gmxx_tx_corrupt_s        cn52xx;
+    struct cvmx_gmxx_tx_corrupt_s        cn52xxp1;
+    struct cvmx_gmxx_tx_corrupt_s        cn56xx;
+    struct cvmx_gmxx_tx_corrupt_s        cn56xxp1;
+    struct cvmx_gmxx_tx_corrupt_s        cn58xx;
+    struct cvmx_gmxx_tx_corrupt_s        cn58xxp1;
+} cvmx_gmxx_tx_corrupt_t;
+
+
+/**
+ * cvmx_gmx#_tx_hg2_reg1
+ *
+ * Notes:
+ * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
+ * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of
+ * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
+ * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
+ * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_hg2_reg1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t tx_xof                  : 16;      /**< TX HiGig2 message for logical link pause when any
+                                                         bit value changes
+                                                          Only write in HiGig2 mode i.e. when
+                                                          GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                          GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+        uint64_t tx_xof                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_hg2_reg1_s       cn52xx;
+    struct cvmx_gmxx_tx_hg2_reg1_s       cn52xxp1;
+    struct cvmx_gmxx_tx_hg2_reg1_s       cn56xx;
+} cvmx_gmxx_tx_hg2_reg1_t;
+
+
+/**
+ * cvmx_gmx#_tx_hg2_reg2
+ *
+ * Notes:
+ * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
+ * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address  of
+ * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
+ * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
+ * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_hg2_reg2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t tx_xon                  : 16;      /**< TX HiGig2 message for logical link pause when any
+                                                         bit value changes
+                                                          Only write in HiGig2 mode i.e. when
+                                                          GMX_TX_XAUI_CTL[HG_EN]=1 and
+                                                          GMX_RX_UDD_SKP[SKIP]=16. */
+#else
+        uint64_t tx_xon                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_hg2_reg2_s       cn52xx;
+    struct cvmx_gmxx_tx_hg2_reg2_s       cn52xxp1;
+    struct cvmx_gmxx_tx_hg2_reg2_s       cn56xx;
+} cvmx_gmxx_tx_hg2_reg2_t;
+
+
+/**
+ * cvmx_gmx#_tx_ifg
+ *
+ * GMX_TX_IFG = Packet TX Interframe Gap
+ *
+ *
+ * Notes:
+ * * Programming IFG1 and IFG2.
+ * 
+ * For 10/100/1000Mbs half-duplex systems that require IEEE 802.3
+ * compatibility, IFG1 must be in the range of 1-8, IFG2 must be in the range
+ * of 4-12, and the IFG1+IFG2 sum must be 12.
+ * 
+ * For 10/100/1000Mbs full-duplex systems that require IEEE 802.3
+ * compatibility, IFG1 must be in the range of 1-11, IFG2 must be in the range
+ * of 1-11, and the IFG1+IFG2 sum must be 12.
+ * 
+ * For XAUI/10Gbs systems that require IEEE 802.3 compatibility, the
+ * IFG1+IFG2 sum must be 12.  IFG1[1:0] and IFG2[1:0] must be zero.
+ * 
+ * For all other systems, IFG1 and IFG2 can be any value in the range of
+ * 1-15.  Allowing for a total possible IFG sum of 2-30.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_ifg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ifg2                    : 4;       /**< 1/3 of the interframe gap timing (in IFG2*8 bits)
+                                                         If CRS is detected during IFG2, then the
+                                                         interFrameSpacing timer is not reset and a frame
+                                                         is transmited once the timer expires. */
+        uint64_t ifg1                    : 4;       /**< 2/3 of the interframe gap timing (in IFG1*8 bits)
+                                                         If CRS is detected during IFG1, then the
+                                                         interFrameSpacing timer is reset and a frame is
+                                                         not transmited. */
+#else
+        uint64_t ifg1                    : 4;
+        uint64_t ifg2                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_ifg_s            cn30xx;
+    struct cvmx_gmxx_tx_ifg_s            cn31xx;
+    struct cvmx_gmxx_tx_ifg_s            cn38xx;
+    struct cvmx_gmxx_tx_ifg_s            cn38xxp2;
+    struct cvmx_gmxx_tx_ifg_s            cn50xx;
+    struct cvmx_gmxx_tx_ifg_s            cn52xx;
+    struct cvmx_gmxx_tx_ifg_s            cn52xxp1;
+    struct cvmx_gmxx_tx_ifg_s            cn56xx;
+    struct cvmx_gmxx_tx_ifg_s            cn56xxp1;
+    struct cvmx_gmxx_tx_ifg_s            cn58xx;
+    struct cvmx_gmxx_tx_ifg_s            cn58xxp1;
+} cvmx_gmxx_tx_ifg_t;
+
+
+/**
+ * cvmx_gmx#_tx_int_en
+ *
+ * GMX_TX_INT_EN = Interrupt Enable
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t late_col                : 4;       /**< TX Late Collision
+                                                         (PASS3 only) */
+        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
+        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t ncb_nxa                 : 1;
+        uint64_t undflw                  : 4;
+        uint64_t reserved_6_7            : 2;
+        uint64_t xscol                   : 4;
+        uint64_t xsdef                   : 4;
+        uint64_t late_col                : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_int_en_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t late_col                : 3;       /**< TX Late Collision */
+        uint64_t reserved_15_15          : 1;
+        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
+        uint64_t reserved_11_11          : 1;
+        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 3;
+        uint64_t reserved_5_7            : 3;
+        uint64_t xscol                   : 3;
+        uint64_t reserved_11_11          : 1;
+        uint64_t xsdef                   : 3;
+        uint64_t reserved_15_15          : 1;
+        uint64_t late_col                : 3;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_tx_int_en_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
+        uint64_t reserved_11_11          : 1;
+        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 3;
+        uint64_t reserved_5_7            : 3;
+        uint64_t xscol                   : 3;
+        uint64_t reserved_11_11          : 1;
+        uint64_t xsdef                   : 3;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } cn31xx;
+    struct cvmx_gmxx_tx_int_en_s         cn38xx;
+    struct cvmx_gmxx_tx_int_en_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
+        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t ncb_nxa                 : 1;
+        uint64_t undflw                  : 4;
+        uint64_t reserved_6_7            : 2;
+        uint64_t xscol                   : 4;
+        uint64_t xsdef                   : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xxp2;
+    struct cvmx_gmxx_tx_int_en_cn30xx    cn50xx;
+    struct cvmx_gmxx_tx_int_en_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t late_col                : 4;       /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t xsdef                   : 4;       /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t xscol                   : 4;       /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t undflw                  : 4;       /**< TX Underflow */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 4;
+        uint64_t reserved_6_7            : 2;
+        uint64_t xscol                   : 4;
+        uint64_t xsdef                   : 4;
+        uint64_t late_col                : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_tx_int_en_cn52xx    cn52xxp1;
+    struct cvmx_gmxx_tx_int_en_cn52xx    cn56xx;
+    struct cvmx_gmxx_tx_int_en_cn52xx    cn56xxp1;
+    struct cvmx_gmxx_tx_int_en_s         cn58xx;
+    struct cvmx_gmxx_tx_int_en_s         cn58xxp1;
+} cvmx_gmxx_tx_int_en_t;
+
+
+/**
+ * cvmx_gmx#_tx_int_reg
+ *
+ * GMX_TX_INT_REG = Interrupt Register
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t late_col                : 4;       /**< TX Late Collision
+                                                         (PASS3 only) */
+        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
+        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t ncb_nxa                 : 1;
+        uint64_t undflw                  : 4;
+        uint64_t reserved_6_7            : 2;
+        uint64_t xscol                   : 4;
+        uint64_t xsdef                   : 4;
+        uint64_t late_col                : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_int_reg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t late_col                : 3;       /**< TX Late Collision */
+        uint64_t reserved_15_15          : 1;
+        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
+        uint64_t reserved_11_11          : 1;
+        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 3;
+        uint64_t reserved_5_7            : 3;
+        uint64_t xscol                   : 3;
+        uint64_t reserved_11_11          : 1;
+        uint64_t xsdef                   : 3;
+        uint64_t reserved_15_15          : 1;
+        uint64_t late_col                : 3;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_tx_int_reg_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t xsdef                   : 3;       /**< TX Excessive deferral (RGMII/halfdup mode only) */
+        uint64_t reserved_11_11          : 1;
+        uint64_t xscol                   : 3;       /**< TX Excessive collisions (RGMII/halfdup mode only) */
+        uint64_t reserved_5_7            : 3;
+        uint64_t undflw                  : 3;       /**< TX Underflow (RGMII mode only) */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 3;
+        uint64_t reserved_5_7            : 3;
+        uint64_t xscol                   : 3;
+        uint64_t reserved_11_11          : 1;
+        uint64_t xsdef                   : 3;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } cn31xx;
+    struct cvmx_gmxx_tx_int_reg_s        cn38xx;
+    struct cvmx_gmxx_tx_int_reg_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t xsdef                   : 4;       /**< TX Excessive deferral (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t xscol                   : 4;       /**< TX Excessive collisions (RGMII/halfdup mode only)
+                                                         (PASS2 only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t undflw                  : 4;       /**< TX Underflow (RGMII mode only) */
+        uint64_t ncb_nxa                 : 1;       /**< Port address out-of-range from NCB Interface */
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t ncb_nxa                 : 1;
+        uint64_t undflw                  : 4;
+        uint64_t reserved_6_7            : 2;
+        uint64_t xscol                   : 4;
+        uint64_t xsdef                   : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xxp2;
+    struct cvmx_gmxx_tx_int_reg_cn30xx   cn50xx;
+    struct cvmx_gmxx_tx_int_reg_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t late_col                : 4;       /**< TX Late Collision
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t xsdef                   : 4;       /**< TX Excessive deferral
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t xscol                   : 4;       /**< TX Excessive collisions
+                                                         (SGMII/1000Base-X half-duplex only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t undflw                  : 4;       /**< TX Underflow */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pko_nxa                 : 1;       /**< Port address out-of-range from PKO Interface */
+#else
+        uint64_t pko_nxa                 : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t undflw                  : 4;
+        uint64_t reserved_6_7            : 2;
+        uint64_t xscol                   : 4;
+        uint64_t xsdef                   : 4;
+        uint64_t late_col                : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_gmxx_tx_int_reg_cn52xx   cn52xxp1;
+    struct cvmx_gmxx_tx_int_reg_cn52xx   cn56xx;
+    struct cvmx_gmxx_tx_int_reg_cn52xx   cn56xxp1;
+    struct cvmx_gmxx_tx_int_reg_s        cn58xx;
+    struct cvmx_gmxx_tx_int_reg_s        cn58xxp1;
+} cvmx_gmxx_tx_int_reg_t;
+
+
+/**
+ * cvmx_gmx#_tx_jam
+ *
+ * GMX_TX_JAM = Packet TX Jam Pattern
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_jam_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t jam                     : 8;       /**< Jam pattern */
+#else
+        uint64_t jam                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_jam_s            cn30xx;
+    struct cvmx_gmxx_tx_jam_s            cn31xx;
+    struct cvmx_gmxx_tx_jam_s            cn38xx;
+    struct cvmx_gmxx_tx_jam_s            cn38xxp2;
+    struct cvmx_gmxx_tx_jam_s            cn50xx;
+    struct cvmx_gmxx_tx_jam_s            cn52xx;
+    struct cvmx_gmxx_tx_jam_s            cn52xxp1;
+    struct cvmx_gmxx_tx_jam_s            cn56xx;
+    struct cvmx_gmxx_tx_jam_s            cn56xxp1;
+    struct cvmx_gmxx_tx_jam_s            cn58xx;
+    struct cvmx_gmxx_tx_jam_s            cn58xxp1;
+} cvmx_gmxx_tx_jam_t;
+
+
+/**
+ * cvmx_gmx#_tx_lfsr
+ *
+ * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_lfsr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t lfsr                    : 16;      /**< The current state of the LFSR used to feed random
+                                                         numbers to compute truncated binary exponential
+                                                         backoff. */
+#else
+        uint64_t lfsr                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_lfsr_s           cn30xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn31xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn38xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn38xxp2;
+    struct cvmx_gmxx_tx_lfsr_s           cn50xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn52xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn52xxp1;
+    struct cvmx_gmxx_tx_lfsr_s           cn56xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn56xxp1;
+    struct cvmx_gmxx_tx_lfsr_s           cn58xx;
+    struct cvmx_gmxx_tx_lfsr_s           cn58xxp1;
+} cvmx_gmxx_tx_lfsr_t;
+
+
+/**
+ * cvmx_gmx#_tx_ovr_bp
+ *
+ * GMX_TX_OVR_BP = Packet Interface TX Override BackPressure
+ *
+ *
+ * Notes:
+ * In XAUI mode, only the lsb (corresponding to port0) of EN, BP, and IGN_FULL are used.
+ * 
+ * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
+ * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol
+ * when GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by
+ * GMX*_TX_XAUI_CTL[HG_EN]=1 and GMX*_RX0_UDD_SKP[LEN]=16.) HW can only auto-generate backpressure
+ * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2
+ * protocol.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_ovr_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t tx_prt_bp               : 16;      /**< Per port BP sent to PKO
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+        uint64_t reserved_12_31          : 20;
+        uint64_t en                      : 4;       /**< Per port Enable back pressure override */
+        uint64_t bp                      : 4;       /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+        uint64_t ign_full                : 4;       /**< Ignore the RX FIFO full when computing BP */
+#else
+        uint64_t ign_full                : 4;
+        uint64_t bp                      : 4;
+        uint64_t en                      : 4;
+        uint64_t reserved_12_31          : 20;
+        uint64_t tx_prt_bp               : 16;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_ovr_bp_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t en                      : 3;       /**< Per port Enable back pressure override */
+        uint64_t reserved_7_7            : 1;
+        uint64_t bp                      : 3;       /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+        uint64_t reserved_3_3            : 1;
+        uint64_t ign_full                : 3;       /**< Ignore the RX FIFO full when computing BP */
+#else
+        uint64_t ign_full                : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t bp                      : 3;
+        uint64_t reserved_7_7            : 1;
+        uint64_t en                      : 3;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn30xx;
+    struct cvmx_gmxx_tx_ovr_bp_cn30xx    cn31xx;
+    struct cvmx_gmxx_tx_ovr_bp_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t en                      : 4;       /**< Per port Enable back pressure override */
+        uint64_t bp                      : 4;       /**< Per port BackPressure status to use
+                                                         0=Port is available
+                                                         1=Port should be back pressured */
+        uint64_t ign_full                : 4;       /**< Ignore the RX FIFO full when computing BP */
+#else
+        uint64_t ign_full                : 4;
+        uint64_t bp                      : 4;
+        uint64_t en                      : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn38xx;
+    struct cvmx_gmxx_tx_ovr_bp_cn38xx    cn38xxp2;
+    struct cvmx_gmxx_tx_ovr_bp_cn30xx    cn50xx;
+    struct cvmx_gmxx_tx_ovr_bp_s         cn52xx;
+    struct cvmx_gmxx_tx_ovr_bp_s         cn52xxp1;
+    struct cvmx_gmxx_tx_ovr_bp_s         cn56xx;
+    struct cvmx_gmxx_tx_ovr_bp_s         cn56xxp1;
+    struct cvmx_gmxx_tx_ovr_bp_cn38xx    cn58xx;
+    struct cvmx_gmxx_tx_ovr_bp_cn38xx    cn58xxp1;
+} cvmx_gmxx_tx_ovr_bp_t;
+
+
+/**
+ * cvmx_gmx#_tx_pause_pkt_dmac
+ *
+ * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t dmac                    : 48;      /**< The DMAC field placed is outbnd pause pkts */
+#else
+        uint64_t dmac                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
+    struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
+} cvmx_gmxx_tx_pause_pkt_dmac_t;
+
+
+/**
+ * cvmx_gmx#_tx_pause_pkt_type
+ *
+ * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_pause_pkt_type_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t type                    : 16;      /**< The TYPE field placed is outbnd pause pkts */
+#else
+        uint64_t type                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
+    struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
+} cvmx_gmxx_tx_pause_pkt_type_t;
+
+
+/**
+ * cvmx_gmx#_tx_prts
+ *
+ * Common
+ * 
+ * 
+ * GMX_TX_PRTS = TX Ports
+ *
+ * Notes:
+ * * The value programmed for PRTS is the number of the highest architected
+ * port number on the interface, plus 1.  For example, if port 2 is the
+ * highest architected port, then the programmed value should be 3 since
+ * there are 3 ports in the system - 0, 1, and 2.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_prts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t prts                    : 5;       /**< Number of ports allowed on the interface */
+#else
+        uint64_t prts                    : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_prts_s           cn30xx;
+    struct cvmx_gmxx_tx_prts_s           cn31xx;
+    struct cvmx_gmxx_tx_prts_s           cn38xx;
+    struct cvmx_gmxx_tx_prts_s           cn38xxp2;
+    struct cvmx_gmxx_tx_prts_s           cn50xx;
+    struct cvmx_gmxx_tx_prts_s           cn52xx;
+    struct cvmx_gmxx_tx_prts_s           cn52xxp1;
+    struct cvmx_gmxx_tx_prts_s           cn56xx;
+    struct cvmx_gmxx_tx_prts_s           cn56xxp1;
+    struct cvmx_gmxx_tx_prts_s           cn58xx;
+    struct cvmx_gmxx_tx_prts_s           cn58xxp1;
+} cvmx_gmxx_tx_prts_t;
+
+
+/**
+ * cvmx_gmx#_tx_spi_ctl
+ *
+ * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_spi_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t tpa_clr                 : 1;       /**< TPA Clear Mode
+                                                         Clear credit counter when satisifed status */
+        uint64_t cont_pkt                : 1;       /**< Contiguous Packet Mode
+                                                         Finish one packet before switching to another
+                                                         Cannot be set in Spi4 pass-through mode */
+#else
+        uint64_t cont_pkt                : 1;
+        uint64_t tpa_clr                 : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_spi_ctl_s        cn38xx;
+    struct cvmx_gmxx_tx_spi_ctl_s        cn38xxp2;
+    struct cvmx_gmxx_tx_spi_ctl_s        cn58xx;
+    struct cvmx_gmxx_tx_spi_ctl_s        cn58xxp1;
+} cvmx_gmxx_tx_spi_ctl_t;
+
+
+/**
+ * cvmx_gmx#_tx_spi_drain
+ *
+ * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_spi_drain_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t drain                   : 16;      /**< Per port drain control
+                                                         0=Normal operation
+                                                         1=GMX TX will be popped, but no valid data will
+                                                           be sent to SPX.  Credits are correctly returned
+                                                           to PKO.  STX_IGN_CAL should be set to ignore
+                                                           TPA and not stall due to back-pressure.
+                                                         (PASS3 only) */
+#else
+        uint64_t drain                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_spi_drain_s      cn38xx;
+    struct cvmx_gmxx_tx_spi_drain_s      cn58xx;
+    struct cvmx_gmxx_tx_spi_drain_s      cn58xxp1;
+} cvmx_gmxx_tx_spi_drain_t;
+
+
+/**
+ * cvmx_gmx#_tx_spi_max
+ *
+ * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_spi_max_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t slice                   : 7;       /**< Number of 16B blocks to transmit in a burst before
+                                                         switching to the next port. SLICE does not always
+                                                         limit the burst length transmitted by OCTEON.
+                                                         Depending on the traffic pattern and
+                                                         GMX_TX_SPI_ROUND programming, the next port could
+                                                         be the same as the current port. In this case,
+                                                         OCTEON may merge multiple sub-SLICE bursts into
+                                                         one contiguous burst that is longer than SLICE
+                                                         (as long as the burst does not cross a packet
+                                                         boundary).
+                                                         SLICE must be programmed to be >=
+                                                           GMX_TX_SPI_THRESH[THRESH]
+                                                         If SLICE==0, then the transmitter will tend to
+                                                         send the complete packet. The port will only
+                                                         switch if credits are exhausted or PKO cannot
+                                                         keep up.
+                                                         (90nm ONLY) */
+        uint64_t max2                    : 8;       /**< MAX2 (per Spi4.2 spec) */
+        uint64_t max1                    : 8;       /**< MAX1 (per Spi4.2 spec)
+                                                         MAX1 >= GMX_TX_SPI_THRESH[THRESH] */
+#else
+        uint64_t max1                    : 8;
+        uint64_t max2                    : 8;
+        uint64_t slice                   : 7;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_spi_max_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t max2                    : 8;       /**< MAX2 (per Spi4.2 spec) */
+        uint64_t max1                    : 8;       /**< MAX1 (per Spi4.2 spec)
+                                                         MAX1 >= GMX_TX_SPI_THRESH[THRESH] */
+#else
+        uint64_t max1                    : 8;
+        uint64_t max2                    : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_gmxx_tx_spi_max_cn38xx   cn38xxp2;
+    struct cvmx_gmxx_tx_spi_max_s        cn58xx;
+    struct cvmx_gmxx_tx_spi_max_s        cn58xxp1;
+} cvmx_gmxx_tx_spi_max_t;
+
+
+/**
+ * cvmx_gmx#_tx_spi_round#
+ *
+ * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_spi_roundx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t round                   : 16;      /**< Which Spi ports participate in each arbitration
+                                                          round.  Each bit corresponds to a spi port
+                                                         - 0: this port will arb in this round
+                                                         - 1: this port will not arb in this round
+                                                          (90nm ONLY) */
+#else
+        uint64_t round                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_spi_roundx_s     cn58xx;
+    struct cvmx_gmxx_tx_spi_roundx_s     cn58xxp1;
+} cvmx_gmxx_tx_spi_roundx_t;
+
+
+/**
+ * cvmx_gmx#_tx_spi_thresh
+ *
+ * GMX_TX_SPI_THRESH = RGMII TX Spi4 Transmit Threshold
+ *
+ *
+ * Notes:
+ * Note: zero will map to 0x20
+ * 
+ * This will normally creates Spi4 traffic bursts at least THRESH in length.
+ * If dclk > eclk, then this rule may not always hold and Octeon may split
+ * transfers into smaller bursts - some of which could be as short as 16B.
+ * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is
+ * not a multiple of 16B.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_spi_thresh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t thresh                  : 6;       /**< Transmit threshold in 16B blocks - cannot be zero
+                                                         THRESH <= TX_FIFO size   (in non-passthrough mode)
+                                                         THRESH <= TX_FIFO size-2 (in passthrough mode)
+                                                         THRESH <= GMX_TX_SPI_MAX[MAX1]
+                                                         THRESH <= GMX_TX_SPI_MAX[MAX2], if not then is it
+                                                          possible for Octeon to send a Spi4 data burst of
+                                                          MAX2 <= burst <= THRESH 16B ticks
+                                                         GMX_TX_SPI_MAX[SLICE] must be programmed to be >=
+                                                           THRESH */
+#else
+        uint64_t thresh                  : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_spi_thresh_s     cn38xx;
+    struct cvmx_gmxx_tx_spi_thresh_s     cn38xxp2;
+    struct cvmx_gmxx_tx_spi_thresh_s     cn58xx;
+    struct cvmx_gmxx_tx_spi_thresh_s     cn58xxp1;
+} cvmx_gmxx_tx_spi_thresh_t;
+
+
+/**
+ * cvmx_gmx#_tx_xaui_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_tx_xaui_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t hg_pause_hgi            : 2;       /**< HGI Field for HW generated HiGig pause packets
+                                                         (XAUI mode only) */
+        uint64_t hg_en                   : 1;       /**< Enable HiGig Mode
+                                                         When HG_EN is set, the following must be set:
+                                                          GMX_RX_FRM_CTL[PRE_CHK] == 0
+                                                          GMX_RX_UDD_SKP[FCSSEL] == 0
+                                                          GMX_RX_UDD_SKP[SKIP] == 12 or 16
+                                                          GMX_TX_APPEND[PREAMBLE] == 0
+                                                           (depending on the HiGig header size)
+                                                         (XAUI mode only) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t ls_byp                  : 1;       /**< Bypass the link status as determined by the XGMII
+                                                         receiver and set the link status of the
+                                                         transmitter to LS.
+                                                         (XAUI mode only) */
+        uint64_t ls                      : 2;       /**< Link Status
+                                                         0 = Link Ok
+                                                             Link runs normally. RS passes MAC data to PCS
+                                                         1 = Local Fault
+                                                             RS layer sends continuous remote fault
+                                                              sequences.
+                                                         2 = Remote Fault
+                                                             RS layer sends continuous idles sequences
+                                                         (XAUI mode only) */
+        uint64_t reserved_2_3            : 2;
+        uint64_t uni_en                  : 1;       /**< Enable Unidirectional Mode (IEEE Clause 66)
+                                                         (XAUI mode only) */
+        uint64_t dic_en                  : 1;       /**< Enable the deficit idle counter for IFG averaging
+                                                         (XAUI mode only) */
+#else
+        uint64_t dic_en                  : 1;
+        uint64_t uni_en                  : 1;
+        uint64_t reserved_2_3            : 2;
+        uint64_t ls                      : 2;
+        uint64_t ls_byp                  : 1;
+        uint64_t reserved_7_7            : 1;
+        uint64_t hg_en                   : 1;
+        uint64_t hg_pause_hgi            : 2;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_gmxx_tx_xaui_ctl_s       cn52xx;
+    struct cvmx_gmxx_tx_xaui_ctl_s       cn52xxp1;
+    struct cvmx_gmxx_tx_xaui_ctl_s       cn56xx;
+    struct cvmx_gmxx_tx_xaui_ctl_s       cn56xxp1;
+} cvmx_gmxx_tx_xaui_ctl_t;
+
+
+/**
+ * cvmx_gmx#_xaui_ext_loopback
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gmxx_xaui_ext_loopback_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t en                      : 1;       /**< Loopback enable
+                                                         Puts the packet interface in external loopback
+                                                         mode on the XAUI bus in which the RX lines are
+                                                         reflected on the TX lines.
+                                                         (XAUI mode only) */
+        uint64_t thresh                  : 4;       /**< Threshhold on the TX FIFO
+                                                         SW must only write the typical value.  Any other
+                                                         value will cause loopback mode not to function
+                                                         correctly.
+                                                         (XAUI mode only) */
+#else
+        uint64_t thresh                  : 4;
+        uint64_t en                      : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
+    struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
+    struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
+    struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
+} cvmx_gmxx_xaui_ext_loopback_t;
+
+
+/**
+ * cvmx_gpio_bit_cfg#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_bit_cfgx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t clk_gen                 : 1;       /**< When TX_OE is set, GPIO pin becomes a clock */
+        uint64_t clk_sel                 : 2;       /**< Selects which of the 4 GPIO clock generators */
+        uint64_t fil_sel                 : 4;       /**< Global counter bit-select (controls sample rate) */
+        uint64_t fil_cnt                 : 4;       /**< Number of consecutive samples to change state */
+        uint64_t int_type                : 1;       /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+        uint64_t int_en                  : 1;       /**< Bit mask to indicate which bits to raise interrupt */
+        uint64_t rx_xor                  : 1;       /**< Invert the GPIO pin */
+        uint64_t tx_oe                   : 1;       /**< Drive the GPIO pin as an output pin */
+#else
+        uint64_t tx_oe                   : 1;
+        uint64_t rx_xor                  : 1;
+        uint64_t int_en                  : 1;
+        uint64_t int_type                : 1;
+        uint64_t fil_cnt                 : 4;
+        uint64_t fil_sel                 : 4;
+        uint64_t clk_sel                 : 2;
+        uint64_t clk_gen                 : 1;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_gpio_bit_cfgx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t fil_sel                 : 4;       /**< Global counter bit-select (controls sample rate) */
+        uint64_t fil_cnt                 : 4;       /**< Number of consecutive samples to change state */
+        uint64_t int_type                : 1;       /**< Type of interrupt
+                                                         0 = level (default)
+                                                         1 = rising edge */
+        uint64_t int_en                  : 1;       /**< Bit mask to indicate which bits to raise interrupt */
+        uint64_t rx_xor                  : 1;       /**< Invert the GPIO pin */
+        uint64_t tx_oe                   : 1;       /**< Drive the GPIO pin as an output pin */
+#else
+        uint64_t tx_oe                   : 1;
+        uint64_t rx_xor                  : 1;
+        uint64_t int_en                  : 1;
+        uint64_t int_type                : 1;
+        uint64_t fil_cnt                 : 4;
+        uint64_t fil_sel                 : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn30xx;
+    struct cvmx_gpio_bit_cfgx_cn30xx     cn31xx;
+    struct cvmx_gpio_bit_cfgx_cn30xx     cn38xx;
+    struct cvmx_gpio_bit_cfgx_cn30xx     cn38xxp2;
+    struct cvmx_gpio_bit_cfgx_cn30xx     cn50xx;
+    struct cvmx_gpio_bit_cfgx_s          cn52xx;
+    struct cvmx_gpio_bit_cfgx_s          cn52xxp1;
+    struct cvmx_gpio_bit_cfgx_s          cn56xx;
+    struct cvmx_gpio_bit_cfgx_s          cn56xxp1;
+    struct cvmx_gpio_bit_cfgx_cn30xx     cn58xx;
+    struct cvmx_gpio_bit_cfgx_cn30xx     cn58xxp1;
+} cvmx_gpio_bit_cfgx_t;
+
+
+/**
+ * cvmx_gpio_boot_ena
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_boot_ena_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t boot_ena                : 4;       /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t boot_ena                : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_gpio_boot_ena_s          cn30xx;
+    struct cvmx_gpio_boot_ena_s          cn31xx;
+    struct cvmx_gpio_boot_ena_s          cn50xx;
+} cvmx_gpio_boot_ena_t;
+
+
+/**
+ * cvmx_gpio_clk_gen#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_clk_genx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t n                       : 32;      /**< Determines the frequency of the GPIO clk generator
+                                                         NOTE: Fgpio_clk = Feclk * N / 2^32
+                                                               N = (Fgpio_clk / Feclk) * 2^32
+                                                         NOTE: writing N == 0 stops the clock generator
+                                                         N  should be <= 2^31-1. */
+#else
+        uint64_t n                       : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_gpio_clk_genx_s          cn52xx;
+    struct cvmx_gpio_clk_genx_s          cn52xxp1;
+    struct cvmx_gpio_clk_genx_s          cn56xx;
+    struct cvmx_gpio_clk_genx_s          cn56xxp1;
+} cvmx_gpio_clk_genx_t;
+
+
+/**
+ * cvmx_gpio_dbg_ena
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_dbg_ena_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t dbg_ena                 : 21;      /**< Enable the debug port to be driven on the gpio */
+#else
+        uint64_t dbg_ena                 : 21;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } s;
+    struct cvmx_gpio_dbg_ena_s           cn30xx;
+    struct cvmx_gpio_dbg_ena_s           cn31xx;
+    struct cvmx_gpio_dbg_ena_s           cn50xx;
+} cvmx_gpio_dbg_ena_t;
+
+
+/**
+ * cvmx_gpio_int_clr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_int_clr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t type                    : 16;      /**< Clear the interrupt rising edge detector */
+#else
+        uint64_t type                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_gpio_int_clr_s           cn30xx;
+    struct cvmx_gpio_int_clr_s           cn31xx;
+    struct cvmx_gpio_int_clr_s           cn38xx;
+    struct cvmx_gpio_int_clr_s           cn38xxp2;
+    struct cvmx_gpio_int_clr_s           cn50xx;
+    struct cvmx_gpio_int_clr_s           cn52xx;
+    struct cvmx_gpio_int_clr_s           cn52xxp1;
+    struct cvmx_gpio_int_clr_s           cn56xx;
+    struct cvmx_gpio_int_clr_s           cn56xxp1;
+    struct cvmx_gpio_int_clr_s           cn58xx;
+    struct cvmx_gpio_int_clr_s           cn58xxp1;
+} cvmx_gpio_int_clr_t;
+
+
+/**
+ * cvmx_gpio_rx_dat
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_rx_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t dat                     : 24;      /**< GPIO Read Data */
+#else
+        uint64_t dat                     : 24;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_gpio_rx_dat_s            cn30xx;
+    struct cvmx_gpio_rx_dat_s            cn31xx;
+    struct cvmx_gpio_rx_dat_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dat                     : 16;      /**< GPIO Read Data */
+#else
+        uint64_t dat                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_gpio_rx_dat_cn38xx       cn38xxp2;
+    struct cvmx_gpio_rx_dat_s            cn50xx;
+    struct cvmx_gpio_rx_dat_cn38xx       cn52xx;
+    struct cvmx_gpio_rx_dat_cn38xx       cn52xxp1;
+    struct cvmx_gpio_rx_dat_cn38xx       cn56xx;
+    struct cvmx_gpio_rx_dat_cn38xx       cn56xxp1;
+    struct cvmx_gpio_rx_dat_cn38xx       cn58xx;
+    struct cvmx_gpio_rx_dat_cn38xx       cn58xxp1;
+} cvmx_gpio_rx_dat_t;
+
+
+/**
+ * cvmx_gpio_tx_clr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_tx_clr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t clr                     : 24;      /**< Bit mask to indicate which bits to drive to '0'. */
+#else
+        uint64_t clr                     : 24;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_gpio_tx_clr_s            cn30xx;
+    struct cvmx_gpio_tx_clr_s            cn31xx;
+    struct cvmx_gpio_tx_clr_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t clr                     : 16;      /**< Bit mask to indicate which bits to drive to '0'. */
+#else
+        uint64_t clr                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_gpio_tx_clr_cn38xx       cn38xxp2;
+    struct cvmx_gpio_tx_clr_s            cn50xx;
+    struct cvmx_gpio_tx_clr_cn38xx       cn52xx;
+    struct cvmx_gpio_tx_clr_cn38xx       cn52xxp1;
+    struct cvmx_gpio_tx_clr_cn38xx       cn56xx;
+    struct cvmx_gpio_tx_clr_cn38xx       cn56xxp1;
+    struct cvmx_gpio_tx_clr_cn38xx       cn58xx;
+    struct cvmx_gpio_tx_clr_cn38xx       cn58xxp1;
+} cvmx_gpio_tx_clr_t;
+
+
+/**
+ * cvmx_gpio_tx_set
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_tx_set_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t set                     : 24;      /**< Bit mask to indicate which bits to drive to '1'. */
+#else
+        uint64_t set                     : 24;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_gpio_tx_set_s            cn30xx;
+    struct cvmx_gpio_tx_set_s            cn31xx;
+    struct cvmx_gpio_tx_set_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t set                     : 16;      /**< Bit mask to indicate which bits to drive to '1'. */
+#else
+        uint64_t set                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_gpio_tx_set_cn38xx       cn38xxp2;
+    struct cvmx_gpio_tx_set_s            cn50xx;
+    struct cvmx_gpio_tx_set_cn38xx       cn52xx;
+    struct cvmx_gpio_tx_set_cn38xx       cn52xxp1;
+    struct cvmx_gpio_tx_set_cn38xx       cn56xx;
+    struct cvmx_gpio_tx_set_cn38xx       cn56xxp1;
+    struct cvmx_gpio_tx_set_cn38xx       cn58xx;
+    struct cvmx_gpio_tx_set_cn38xx       cn58xxp1;
+} cvmx_gpio_tx_set_t;
+
+
+/**
+ * cvmx_gpio_xbit_cfg#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_gpio_xbit_cfgx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t fil_sel                 : 4;       /**< Global counter bit-select (controls sample rate) */
+        uint64_t fil_cnt                 : 4;       /**< Number of consecutive samples to change state */
+        uint64_t reserved_2_3            : 2;
+        uint64_t rx_xor                  : 1;       /**< Invert the GPIO pin */
+        uint64_t tx_oe                   : 1;       /**< Drive the GPIO pin as an output pin */
+#else
+        uint64_t tx_oe                   : 1;
+        uint64_t rx_xor                  : 1;
+        uint64_t reserved_2_3            : 2;
+        uint64_t fil_cnt                 : 4;
+        uint64_t fil_sel                 : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_gpio_xbit_cfgx_s         cn30xx;
+    struct cvmx_gpio_xbit_cfgx_s         cn31xx;
+    struct cvmx_gpio_xbit_cfgx_s         cn50xx;
+} cvmx_gpio_xbit_cfgx_t;
+
+
+/**
+ * cvmx_iob_bist_status
+ *
+ * IOB_BIST_STATUS = BIST Status of IOB Memories
+ * 
+ * The result of the BIST run on the IOB memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t icnrcb                  : 1;       /**< icnr_cb_reg_fifo_bist_status */
+        uint64_t icr0                    : 1;       /**< icr_bist_req_fifo0_status */
+        uint64_t icr1                    : 1;       /**< icr_bist_req_fifo1_status */
+        uint64_t icnr1                   : 1;       /**< icnr_reg_mem1_bist_status */
+        uint64_t icnr0                   : 1;       /**< icnr_reg_mem0_bist_status */
+        uint64_t ibdr0                   : 1;       /**< ibdr_bist_req_fifo0_status */
+        uint64_t ibdr1                   : 1;       /**< ibdr_bist_req_fifo1_status */
+        uint64_t ibr0                    : 1;       /**< ibr_bist_rsp_fifo0_status */
+        uint64_t ibr1                    : 1;       /**< ibr_bist_rsp_fifo1_status */
+        uint64_t icnrt                   : 1;       /**< icnr_tag_cb_reg_fifo_bist_status */
+        uint64_t ibrq0                   : 1;       /**< ibrq_bist_req_fifo0_status */
+        uint64_t ibrq1                   : 1;       /**< ibrq_bist_req_fifo1_status */
+        uint64_t icrn0                   : 1;       /**< icr_ncb_bist_mem0_status */
+        uint64_t icrn1                   : 1;       /**< icr_ncb_bist_mem1_status */
+        uint64_t icrp0                   : 1;       /**< icr_pko_bist_mem0_status */
+        uint64_t icrp1                   : 1;       /**< icr_pko_bist_mem1_status */
+        uint64_t ibd                     : 1;       /**< ibd_bist_mem0_status */
+        uint64_t icd                     : 1;       /**< icd_ncb_fifo_bist_status */
+#else
+        uint64_t icd                     : 1;
+        uint64_t ibd                     : 1;
+        uint64_t icrp1                   : 1;
+        uint64_t icrp0                   : 1;
+        uint64_t icrn1                   : 1;
+        uint64_t icrn0                   : 1;
+        uint64_t ibrq1                   : 1;
+        uint64_t ibrq0                   : 1;
+        uint64_t icnrt                   : 1;
+        uint64_t ibr1                    : 1;
+        uint64_t ibr0                    : 1;
+        uint64_t ibdr1                   : 1;
+        uint64_t ibdr0                   : 1;
+        uint64_t icnr0                   : 1;
+        uint64_t icnr1                   : 1;
+        uint64_t icr1                    : 1;
+        uint64_t icr0                    : 1;
+        uint64_t icnrcb                  : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_iob_bist_status_s        cn30xx;
+    struct cvmx_iob_bist_status_s        cn31xx;
+    struct cvmx_iob_bist_status_s        cn38xx;
+    struct cvmx_iob_bist_status_s        cn38xxp2;
+    struct cvmx_iob_bist_status_s        cn50xx;
+    struct cvmx_iob_bist_status_s        cn52xx;
+    struct cvmx_iob_bist_status_s        cn52xxp1;
+    struct cvmx_iob_bist_status_s        cn56xx;
+    struct cvmx_iob_bist_status_s        cn56xxp1;
+    struct cvmx_iob_bist_status_s        cn58xx;
+    struct cvmx_iob_bist_status_s        cn58xxp1;
+} cvmx_iob_bist_status_t;
+
+
+/**
+ * cvmx_iob_ctl_status
+ *
+ * IOB Control Status = IOB Control and Status Register
+ * 
+ * Provides control for IOB functions.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t rr_mode                 : 1;       /**< When set to '1' will enable Round-Robin mode of next
+                                                         transaction that could arbitrate for the XMB. */
+        uint64_t outb_mat                : 1;       /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+        uint64_t inb_mat                 : 1;       /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. PASS2 FIELD. */
+        uint64_t pko_enb                 : 1;       /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+        uint64_t dwb_enb                 : 1;       /**< Enables the DWB function of the IOB. */
+        uint64_t fau_end                 : 1;       /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+        uint64_t fau_end                 : 1;
+        uint64_t dwb_enb                 : 1;
+        uint64_t pko_enb                 : 1;
+        uint64_t inb_mat                 : 1;
+        uint64_t outb_mat                : 1;
+        uint64_t rr_mode                 : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_iob_ctl_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t outb_mat                : 1;       /**< Was a match on the outbound bus to the inb pattern
+                                                         matchers. */
+        uint64_t inb_mat                 : 1;       /**< Was a match on the inbound bus to the inb pattern
+                                                         matchers. */
+        uint64_t pko_enb                 : 1;       /**< Toggles the endian style of the FAU for the PKO.
+                                                         '0' is for big-endian and '1' is for little-endian. */
+        uint64_t dwb_enb                 : 1;       /**< Enables the DWB function of the IOB. */
+        uint64_t fau_end                 : 1;       /**< Toggles the endian style of the FAU. '0' is for
+                                                         big-endian and '1' is for little-endian. */
+#else
+        uint64_t fau_end                 : 1;
+        uint64_t dwb_enb                 : 1;
+        uint64_t pko_enb                 : 1;
+        uint64_t inb_mat                 : 1;
+        uint64_t outb_mat                : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn30xx;
+    struct cvmx_iob_ctl_status_cn30xx    cn31xx;
+    struct cvmx_iob_ctl_status_cn30xx    cn38xx;
+    struct cvmx_iob_ctl_status_cn30xx    cn38xxp2;
+    struct cvmx_iob_ctl_status_cn30xx    cn50xx;
+    struct cvmx_iob_ctl_status_s         cn52xx;
+    struct cvmx_iob_ctl_status_cn30xx    cn52xxp1;
+    struct cvmx_iob_ctl_status_cn30xx    cn56xx;
+    struct cvmx_iob_ctl_status_cn30xx    cn56xxp1;
+    struct cvmx_iob_ctl_status_cn30xx    cn58xx;
+    struct cvmx_iob_ctl_status_cn30xx    cn58xxp1;
+} cvmx_iob_ctl_status_t;
+
+
+/**
+ * cvmx_iob_dwb_pri_cnt
+ *
+ * DWB To CMB Priority Counter = Don't Write Back to CMB Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_dwb_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_dwb_pri_cnt_s        cn38xx;
+    struct cvmx_iob_dwb_pri_cnt_s        cn38xxp2;
+    struct cvmx_iob_dwb_pri_cnt_s        cn52xx;
+    struct cvmx_iob_dwb_pri_cnt_s        cn52xxp1;
+    struct cvmx_iob_dwb_pri_cnt_s        cn56xx;
+    struct cvmx_iob_dwb_pri_cnt_s        cn56xxp1;
+    struct cvmx_iob_dwb_pri_cnt_s        cn58xx;
+    struct cvmx_iob_dwb_pri_cnt_s        cn58xxp1;
+} cvmx_iob_dwb_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_fau_timeout
+ *
+ * FAU Timeout = Fetch and Add Unit Tag-Switch Timeout
+ * 
+ * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out.
+ * for Queue 0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_fau_timeout_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t tout_enb                : 1;       /**< The enable for the FAU timeout feature.
+                                                         '1' will enable the timeout, '0' will disable. */
+        uint64_t tout_val                : 12;      /**< When a tag request arrives from the PP a timer is
+                                                         started associate with that PP. The timer which
+                                                         increments every 256 eclks is compared to TOUT_VAL.
+                                                         When the two are equal the IOB will flag the tag
+                                                         request to complete as a time-out tag operation.
+                                                         The 256 count timer used to increment the PP
+                                                         associated timer is always running so the first
+                                                         increment of the PP associated timer may occur any
+                                                         where within the first 256 eclks.  Note that '0'
+                                                         is an illegal value. */
+#else
+        uint64_t tout_val                : 12;
+        uint64_t tout_enb                : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_iob_fau_timeout_s        cn30xx;
+    struct cvmx_iob_fau_timeout_s        cn31xx;
+    struct cvmx_iob_fau_timeout_s        cn38xx;
+    struct cvmx_iob_fau_timeout_s        cn38xxp2;
+    struct cvmx_iob_fau_timeout_s        cn50xx;
+    struct cvmx_iob_fau_timeout_s        cn52xx;
+    struct cvmx_iob_fau_timeout_s        cn52xxp1;
+    struct cvmx_iob_fau_timeout_s        cn56xx;
+    struct cvmx_iob_fau_timeout_s        cn56xxp1;
+    struct cvmx_iob_fau_timeout_s        cn58xx;
+    struct cvmx_iob_fau_timeout_s        cn58xxp1;
+} cvmx_iob_fau_timeout_t;
+
+
+/**
+ * cvmx_iob_i2c_pri_cnt
+ *
+ * IPD To CMB Store Priority Counter = IPD to CMB Store Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_i2c_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_i2c_pri_cnt_s        cn38xx;
+    struct cvmx_iob_i2c_pri_cnt_s        cn38xxp2;
+    struct cvmx_iob_i2c_pri_cnt_s        cn52xx;
+    struct cvmx_iob_i2c_pri_cnt_s        cn52xxp1;
+    struct cvmx_iob_i2c_pri_cnt_s        cn56xx;
+    struct cvmx_iob_i2c_pri_cnt_s        cn56xxp1;
+    struct cvmx_iob_i2c_pri_cnt_s        cn58xx;
+    struct cvmx_iob_i2c_pri_cnt_s        cn58xxp1;
+} cvmx_iob_i2c_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_inb_control_match
+ *
+ * IOB_INB_CONTROL_MATCH = IOB Inbound Control Match
+ * 
+ * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_inb_control_match_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t mask                    : 8;       /**< Pattern to match on the inbound NCB. */
+        uint64_t opc                     : 4;       /**< Pattern to match on the inbound NCB. */
+        uint64_t dst                     : 9;       /**< Pattern to match on the inbound NCB. */
+        uint64_t src                     : 8;       /**< Pattern to match on the inbound NCB. */
+#else
+        uint64_t src                     : 8;
+        uint64_t dst                     : 9;
+        uint64_t opc                     : 4;
+        uint64_t mask                    : 8;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_iob_inb_control_match_s  cn30xx;
+    struct cvmx_iob_inb_control_match_s  cn31xx;
+    struct cvmx_iob_inb_control_match_s  cn38xx;
+    struct cvmx_iob_inb_control_match_s  cn38xxp2;
+    struct cvmx_iob_inb_control_match_s  cn50xx;
+    struct cvmx_iob_inb_control_match_s  cn52xx;
+    struct cvmx_iob_inb_control_match_s  cn52xxp1;
+    struct cvmx_iob_inb_control_match_s  cn56xx;
+    struct cvmx_iob_inb_control_match_s  cn56xxp1;
+    struct cvmx_iob_inb_control_match_s  cn58xx;
+    struct cvmx_iob_inb_control_match_s  cn58xxp1;
+} cvmx_iob_inb_control_match_t;
+
+
+/**
+ * cvmx_iob_inb_control_match_enb
+ *
+ * IOB_INB_CONTROL_MATCH_ENB = IOB Inbound Control Match Enable
+ * 
+ * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_inb_control_match_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t mask                    : 8;       /**< Pattern to match on the inbound NCB. */
+        uint64_t opc                     : 4;       /**< Pattern to match on the inbound NCB. */
+        uint64_t dst                     : 9;       /**< Pattern to match on the inbound NCB. */
+        uint64_t src                     : 8;       /**< Pattern to match on the inbound NCB. */
+#else
+        uint64_t src                     : 8;
+        uint64_t dst                     : 9;
+        uint64_t opc                     : 4;
+        uint64_t mask                    : 8;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_iob_inb_control_match_enb_s cn30xx;
+    struct cvmx_iob_inb_control_match_enb_s cn31xx;
+    struct cvmx_iob_inb_control_match_enb_s cn38xx;
+    struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
+    struct cvmx_iob_inb_control_match_enb_s cn50xx;
+    struct cvmx_iob_inb_control_match_enb_s cn52xx;
+    struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
+    struct cvmx_iob_inb_control_match_enb_s cn56xx;
+    struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
+    struct cvmx_iob_inb_control_match_enb_s cn58xx;
+    struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+} cvmx_iob_inb_control_match_enb_t;
+
+
+/**
+ * cvmx_iob_inb_data_match
+ *
+ * IOB_INB_DATA_MATCH = IOB Inbound Data Match
+ * 
+ * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_inb_data_match_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Pattern to match on the inbound NCB. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_iob_inb_data_match_s     cn30xx;
+    struct cvmx_iob_inb_data_match_s     cn31xx;
+    struct cvmx_iob_inb_data_match_s     cn38xx;
+    struct cvmx_iob_inb_data_match_s     cn38xxp2;
+    struct cvmx_iob_inb_data_match_s     cn50xx;
+    struct cvmx_iob_inb_data_match_s     cn52xx;
+    struct cvmx_iob_inb_data_match_s     cn52xxp1;
+    struct cvmx_iob_inb_data_match_s     cn56xx;
+    struct cvmx_iob_inb_data_match_s     cn56xxp1;
+    struct cvmx_iob_inb_data_match_s     cn58xx;
+    struct cvmx_iob_inb_data_match_s     cn58xxp1;
+} cvmx_iob_inb_data_match_t;
+
+
+/**
+ * cvmx_iob_inb_data_match_enb
+ *
+ * IOB_INB_DATA_MATCH_ENB = IOB Inbound Data Match Enable
+ * 
+ * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_inb_data_match_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Bit to enable match of. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_iob_inb_data_match_enb_s cn30xx;
+    struct cvmx_iob_inb_data_match_enb_s cn31xx;
+    struct cvmx_iob_inb_data_match_enb_s cn38xx;
+    struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
+    struct cvmx_iob_inb_data_match_enb_s cn50xx;
+    struct cvmx_iob_inb_data_match_enb_s cn52xx;
+    struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
+    struct cvmx_iob_inb_data_match_enb_s cn56xx;
+    struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
+    struct cvmx_iob_inb_data_match_enb_s cn58xx;
+    struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
+} cvmx_iob_inb_data_match_enb_t;
+
+
+/**
+ * cvmx_iob_int_enb
+ *
+ * IOB_INT_ENB = IOB's Interrupt Enable
+ * 
+ * The IOB's interrupt enable register. This is a PASS-2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t p_dat                   : 1;       /**< When set (1) and bit 5 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t np_dat                  : 1;       /**< When set (1) and bit 4 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t p_eop                   : 1;       /**< When set (1) and bit 3 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t p_sop                   : 1;       /**< When set (1) and bit 2 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t np_eop                  : 1;       /**< When set (1) and bit 1 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t np_sop                  : 1;       /**< When set (1) and bit 0 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+#else
+        uint64_t np_sop                  : 1;
+        uint64_t np_eop                  : 1;
+        uint64_t p_sop                   : 1;
+        uint64_t p_eop                   : 1;
+        uint64_t np_dat                  : 1;
+        uint64_t p_dat                   : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_iob_int_enb_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t p_eop                   : 1;       /**< When set (1) and bit 3 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t p_sop                   : 1;       /**< When set (1) and bit 2 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t np_eop                  : 1;       /**< When set (1) and bit 1 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+        uint64_t np_sop                  : 1;       /**< When set (1) and bit 0 of the IOB_INT_SUM
+                                                         register is asserted the IOB will assert an
+                                                         interrupt. */
+#else
+        uint64_t np_sop                  : 1;
+        uint64_t np_eop                  : 1;
+        uint64_t p_sop                   : 1;
+        uint64_t p_eop                   : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_iob_int_enb_cn30xx       cn31xx;
+    struct cvmx_iob_int_enb_cn30xx       cn38xx;
+    struct cvmx_iob_int_enb_cn30xx       cn38xxp2;
+    struct cvmx_iob_int_enb_s            cn50xx;
+    struct cvmx_iob_int_enb_s            cn52xx;
+    struct cvmx_iob_int_enb_s            cn52xxp1;
+    struct cvmx_iob_int_enb_s            cn56xx;
+    struct cvmx_iob_int_enb_s            cn56xxp1;
+    struct cvmx_iob_int_enb_s            cn58xx;
+    struct cvmx_iob_int_enb_s            cn58xxp1;
+} cvmx_iob_int_enb_t;
+
+
+/**
+ * cvmx_iob_int_sum
+ *
+ * IOB_INT_SUM = IOB's Interrupt Summary Register
+ * 
+ * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t p_dat                   : 1;       /**< Set when a data arrives before a SOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t np_dat                  : 1;       /**< Set when a data arrives before a SOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t p_eop                   : 1;       /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t p_sop                   : 1;       /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t np_eop                  : 1;       /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t np_sop                  : 1;       /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [5:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+#else
+        uint64_t np_sop                  : 1;
+        uint64_t np_eop                  : 1;
+        uint64_t p_sop                   : 1;
+        uint64_t p_eop                   : 1;
+        uint64_t np_dat                  : 1;
+        uint64_t p_dat                   : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_iob_int_sum_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t p_eop                   : 1;       /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t p_sop                   : 1;       /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t np_eop                  : 1;       /**< Set when a EOP is followed by an EOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+        uint64_t np_sop                  : 1;       /**< Set when a SOP is followed by an SOP for the same
+                                                         port for a non-passthrough packet.
+                                                         The first detected error associated with bits [3:0]
+                                                         of this register will only be set here. A new bit
+                                                         can be set when the previous reported bit is cleared. */
+#else
+        uint64_t np_sop                  : 1;
+        uint64_t np_eop                  : 1;
+        uint64_t p_sop                   : 1;
+        uint64_t p_eop                   : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_iob_int_sum_cn30xx       cn31xx;
+    struct cvmx_iob_int_sum_cn30xx       cn38xx;
+    struct cvmx_iob_int_sum_cn30xx       cn38xxp2;
+    struct cvmx_iob_int_sum_s            cn50xx;
+    struct cvmx_iob_int_sum_s            cn52xx;
+    struct cvmx_iob_int_sum_s            cn52xxp1;
+    struct cvmx_iob_int_sum_s            cn56xx;
+    struct cvmx_iob_int_sum_s            cn56xxp1;
+    struct cvmx_iob_int_sum_s            cn58xx;
+    struct cvmx_iob_int_sum_s            cn58xxp1;
+} cvmx_iob_int_sum_t;
+
+
+/**
+ * cvmx_iob_n2c_l2c_pri_cnt
+ *
+ * NCB To CMB L2C Priority Counter = NCB to CMB L2C Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn38xx;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn38xxp2;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn52xx;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn52xxp1;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn56xx;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn56xxp1;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn58xx;
+    struct cvmx_iob_n2c_l2c_pri_cnt_s    cn58xxp1;
+} cvmx_iob_n2c_l2c_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_n2c_rsp_pri_cnt
+ *
+ * NCB To CMB Response Priority Counter = NCB to CMB Response Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn38xx;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn38xxp2;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn52xx;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn52xxp1;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn56xx;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn56xxp1;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn58xx;
+    struct cvmx_iob_n2c_rsp_pri_cnt_s    cn58xxp1;
+} cvmx_iob_n2c_rsp_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_outb_com_pri_cnt
+ *
+ * Commit To NCB Priority Counter = Commit to NCB Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_com_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of NCB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to NCB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn38xx;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn38xxp2;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn52xx;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn52xxp1;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn56xx;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn56xxp1;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn58xx;
+    struct cvmx_iob_outb_com_pri_cnt_s   cn58xxp1;
+} cvmx_iob_outb_com_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_outb_control_match
+ *
+ * IOB_OUTB_CONTROL_MATCH = IOB Outbound Control Match
+ * 
+ * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_control_match_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_26_63          : 38;
+        uint64_t mask                    : 8;       /**< Pattern to match on the outbound NCB. */
+        uint64_t eot                     : 1;       /**< Pattern to match on the outbound NCB. */
+        uint64_t dst                     : 8;       /**< Pattern to match on the outbound NCB. */
+        uint64_t src                     : 9;       /**< Pattern to match on the outbound NCB. */
+#else
+        uint64_t src                     : 9;
+        uint64_t dst                     : 8;
+        uint64_t eot                     : 1;
+        uint64_t mask                    : 8;
+        uint64_t reserved_26_63          : 38;
+#endif
+    } s;
+    struct cvmx_iob_outb_control_match_s cn30xx;
+    struct cvmx_iob_outb_control_match_s cn31xx;
+    struct cvmx_iob_outb_control_match_s cn38xx;
+    struct cvmx_iob_outb_control_match_s cn38xxp2;
+    struct cvmx_iob_outb_control_match_s cn50xx;
+    struct cvmx_iob_outb_control_match_s cn52xx;
+    struct cvmx_iob_outb_control_match_s cn52xxp1;
+    struct cvmx_iob_outb_control_match_s cn56xx;
+    struct cvmx_iob_outb_control_match_s cn56xxp1;
+    struct cvmx_iob_outb_control_match_s cn58xx;
+    struct cvmx_iob_outb_control_match_s cn58xxp1;
+} cvmx_iob_outb_control_match_t;
+
+
+/**
+ * cvmx_iob_outb_control_match_enb
+ *
+ * IOB_OUTB_CONTROL_MATCH_ENB = IOB Outbound Control Match Enable
+ * 
+ * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_control_match_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_26_63          : 38;
+        uint64_t mask                    : 8;       /**< Pattern to match on the outbound NCB. */
+        uint64_t eot                     : 1;       /**< Pattern to match on the outbound NCB. */
+        uint64_t dst                     : 8;       /**< Pattern to match on the outbound NCB. */
+        uint64_t src                     : 9;       /**< Pattern to match on the outbound NCB. */
+#else
+        uint64_t src                     : 9;
+        uint64_t dst                     : 8;
+        uint64_t eot                     : 1;
+        uint64_t mask                    : 8;
+        uint64_t reserved_26_63          : 38;
+#endif
+    } s;
+    struct cvmx_iob_outb_control_match_enb_s cn30xx;
+    struct cvmx_iob_outb_control_match_enb_s cn31xx;
+    struct cvmx_iob_outb_control_match_enb_s cn38xx;
+    struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
+    struct cvmx_iob_outb_control_match_enb_s cn50xx;
+    struct cvmx_iob_outb_control_match_enb_s cn52xx;
+    struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
+    struct cvmx_iob_outb_control_match_enb_s cn56xx;
+    struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
+    struct cvmx_iob_outb_control_match_enb_s cn58xx;
+    struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+} cvmx_iob_outb_control_match_enb_t;
+
+
+/**
+ * cvmx_iob_outb_data_match
+ *
+ * IOB_OUTB_DATA_MATCH = IOB Outbound Data Match
+ * 
+ * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_data_match_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Pattern to match on the outbound NCB. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_iob_outb_data_match_s    cn30xx;
+    struct cvmx_iob_outb_data_match_s    cn31xx;
+    struct cvmx_iob_outb_data_match_s    cn38xx;
+    struct cvmx_iob_outb_data_match_s    cn38xxp2;
+    struct cvmx_iob_outb_data_match_s    cn50xx;
+    struct cvmx_iob_outb_data_match_s    cn52xx;
+    struct cvmx_iob_outb_data_match_s    cn52xxp1;
+    struct cvmx_iob_outb_data_match_s    cn56xx;
+    struct cvmx_iob_outb_data_match_s    cn56xxp1;
+    struct cvmx_iob_outb_data_match_s    cn58xx;
+    struct cvmx_iob_outb_data_match_s    cn58xxp1;
+} cvmx_iob_outb_data_match_t;
+
+
+/**
+ * cvmx_iob_outb_data_match_enb
+ *
+ * IOB_OUTB_DATA_MATCH_ENB = IOB Outbound Data Match Enable
+ * 
+ * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_data_match_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Bit to enable match of. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_iob_outb_data_match_enb_s cn30xx;
+    struct cvmx_iob_outb_data_match_enb_s cn31xx;
+    struct cvmx_iob_outb_data_match_enb_s cn38xx;
+    struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
+    struct cvmx_iob_outb_data_match_enb_s cn50xx;
+    struct cvmx_iob_outb_data_match_enb_s cn52xx;
+    struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
+    struct cvmx_iob_outb_data_match_enb_s cn56xx;
+    struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
+    struct cvmx_iob_outb_data_match_enb_s cn58xx;
+    struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+} cvmx_iob_outb_data_match_enb_t;
+
+
+/**
+ * cvmx_iob_outb_fpa_pri_cnt
+ *
+ * FPA To NCB Priority Counter = FPA Returns to NCB Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_fpa_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of NCB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to NCB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn38xx;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn38xxp2;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn52xx;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn52xxp1;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn56xx;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn56xxp1;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn58xx;
+    struct cvmx_iob_outb_fpa_pri_cnt_s   cn58xxp1;
+} cvmx_iob_outb_fpa_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_outb_req_pri_cnt
+ *
+ * Request To NCB Priority Counter = Request to NCB Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_outb_req_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of NCB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to NCB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn38xx;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn38xxp2;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn52xx;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn52xxp1;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn56xx;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn56xxp1;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn58xx;
+    struct cvmx_iob_outb_req_pri_cnt_s   cn58xxp1;
+} cvmx_iob_outb_req_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_p2c_req_pri_cnt
+ *
+ * PKO To CMB Response Priority Counter = PKO to CMB Response Priority Counter Enable and Timer Value
+ * 
+ * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_p2c_req_pri_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt_enb                 : 1;       /**< Enables the raising of CMB access priority
+                                                         when CNT_VAL is reached. */
+        uint64_t cnt_val                 : 15;      /**< Number of core clocks to wait before raising
+                                                         the priority for access to CMB. */
+#else
+        uint64_t cnt_val                 : 15;
+        uint64_t cnt_enb                 : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn38xx;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn38xxp2;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn52xx;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn52xxp1;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn56xx;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn56xxp1;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn58xx;
+    struct cvmx_iob_p2c_req_pri_cnt_s    cn58xxp1;
+} cvmx_iob_p2c_req_pri_cnt_t;
+
+
+/**
+ * cvmx_iob_pkt_err
+ *
+ * IOB_PKT_ERR = IOB Packet Error Register
+ * 
+ * Provides status about the failing packet recevie error. This is a PASS-2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_pkt_err_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t port                    : 6;       /**< When IOB_INT_SUM[3:0] bit is set, this field
+                                                         latches the failing port associate with the
+                                                         IOB_INT_SUM[3:0] bit set. */
+#else
+        uint64_t port                    : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_iob_pkt_err_s            cn30xx;
+    struct cvmx_iob_pkt_err_s            cn31xx;
+    struct cvmx_iob_pkt_err_s            cn38xx;
+    struct cvmx_iob_pkt_err_s            cn38xxp2;
+    struct cvmx_iob_pkt_err_s            cn50xx;
+    struct cvmx_iob_pkt_err_s            cn52xx;
+    struct cvmx_iob_pkt_err_s            cn52xxp1;
+    struct cvmx_iob_pkt_err_s            cn56xx;
+    struct cvmx_iob_pkt_err_s            cn56xxp1;
+    struct cvmx_iob_pkt_err_s            cn58xx;
+    struct cvmx_iob_pkt_err_s            cn58xxp1;
+} cvmx_iob_pkt_err_t;
+
+
+/**
+ * cvmx_iob_to_cmb_credits
+ *
+ * IOB_TO_CMB_CREDITS = IOB To CMB Credits
+ * 
+ * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_iob_to_cmb_credits_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t pko_rd                  : 3;       /**< Number of PKO reads that can be out to L2C where
+                                                         0 == 8-credits. */
+        uint64_t ncb_rd                  : 3;       /**< Number of NCB reads that can be out to L2C where
+                                                         0 == 8-credits. */
+        uint64_t ncb_wr                  : 3;       /**< Number of NCB/PKI writes that can be out to L2C
+                                                         where 0 == 8-credits. */
+#else
+        uint64_t ncb_wr                  : 3;
+        uint64_t ncb_rd                  : 3;
+        uint64_t pko_rd                  : 3;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_iob_to_cmb_credits_s     cn52xx;
+} cvmx_iob_to_cmb_credits_t;
+
+
+/**
+ * cvmx_ipd_1st_mbuff_skip
+ *
+ * IPD_1ST_MBUFF_SKIP = IPD First MBUFF Word Skip Size
+ * 
+ * The number of words that the IPD will skip when writing the first MBUFF.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_1st_mbuff_skip_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t skip_sz                 : 6;       /**< The number of 8-byte words from the top of the
+                                                         1st MBUFF that the IPD will store the next-pointer.
+                                                         Legal values are 0 to 32, where the MAX value
+                                                         is also limited to:
+                                                         IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 18. */
+#else
+        uint64_t skip_sz                 : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn30xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn31xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn38xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn38xxp2;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn50xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn52xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn52xxp1;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn56xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn56xxp1;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn58xx;
+    struct cvmx_ipd_1st_mbuff_skip_s     cn58xxp1;
+} cvmx_ipd_1st_mbuff_skip_t;
+
+
+/**
+ * cvmx_ipd_1st_next_ptr_back
+ *
+ * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values
+ * 
+ * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_1st_next_ptr_back_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t back                    : 4;       /**< Used to find head of buffer from the nxt-hdr-ptr. */
+#else
+        uint64_t back                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn30xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn31xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn38xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn38xxp2;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn50xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn52xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn52xxp1;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn56xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn56xxp1;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn58xx;
+    struct cvmx_ipd_1st_next_ptr_back_s  cn58xxp1;
+} cvmx_ipd_1st_next_ptr_back_t;
+
+
+/**
+ * cvmx_ipd_2nd_next_ptr_back
+ *
+ * IPD_2nd_NEXT_PTR_BACK = IPD Second Next Pointer Back Value
+ * 
+ * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_2nd_next_ptr_back_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t back                    : 4;       /**< Used to find head of buffer from the nxt-hdr-ptr. */
+#else
+        uint64_t back                    : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn30xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn31xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn38xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn38xxp2;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn50xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn52xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn52xxp1;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn56xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn56xxp1;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn58xx;
+    struct cvmx_ipd_2nd_next_ptr_back_s  cn58xxp1;
+} cvmx_ipd_2nd_next_ptr_back_t;
+
+
+/**
+ * cvmx_ipd_bist_status
+ *
+ * IPD_BIST_STATUS = IPD BIST STATUS
+ * 
+ * BIST Status for IPD's Memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t csr_mem                 : 1;       /**< CSR Register Memory Bist Status. */
+        uint64_t csr_ncmd                : 1;       /**< CSR NCB Commands Memory Bist Status. */
+        uint64_t pwq_wqed                : 1;       /**< PWQ PIP WQE DONE Memory Bist Status. */
+        uint64_t pwq_wp1                 : 1;       /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
+        uint64_t pwq_pow                 : 1;       /**< PWQ POW MEM Memory Bist Status. */
+        uint64_t ipq_pbe1                : 1;       /**< IPQ PBE1 Memory Bist Status. */
+        uint64_t ipq_pbe0                : 1;       /**< IPQ PBE0 Memory Bist Status. */
+        uint64_t pbm3                    : 1;       /**< PBM3 Memory Bist Status. */
+        uint64_t pbm2                    : 1;       /**< PBM2 Memory Bist Status. */
+        uint64_t pbm1                    : 1;       /**< PBM1 Memory Bist Status. */
+        uint64_t pbm0                    : 1;       /**< PBM0 Memory Bist Status. */
+        uint64_t pbm_word                : 1;       /**< PBM_WORD Memory Bist Status. */
+        uint64_t pwq1                    : 1;       /**< PWQ1 Memory Bist Status. */
+        uint64_t pwq0                    : 1;       /**< PWQ0 Memory Bist Status. */
+        uint64_t prc_off                 : 1;       /**< PRC_OFF Memory Bist Status. */
+        uint64_t ipd_old                 : 1;       /**< IPD_OLD Memory Bist Status. */
+        uint64_t ipd_new                 : 1;       /**< IPD_NEW Memory Bist Status. */
+        uint64_t pwp                     : 1;       /**< PWP Memory Bist Status. */
+#else
+        uint64_t pwp                     : 1;
+        uint64_t ipd_new                 : 1;
+        uint64_t ipd_old                 : 1;
+        uint64_t prc_off                 : 1;
+        uint64_t pwq0                    : 1;
+        uint64_t pwq1                    : 1;
+        uint64_t pbm_word                : 1;
+        uint64_t pbm0                    : 1;
+        uint64_t pbm1                    : 1;
+        uint64_t pbm2                    : 1;
+        uint64_t pbm3                    : 1;
+        uint64_t ipq_pbe0                : 1;
+        uint64_t ipq_pbe1                : 1;
+        uint64_t pwq_pow                 : 1;
+        uint64_t pwq_wp1                 : 1;
+        uint64_t pwq_wqed                : 1;
+        uint64_t csr_ncmd                : 1;
+        uint64_t csr_mem                 : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_ipd_bist_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t pwq_wqed                : 1;       /**< PWQ PIP WQE DONE Memory Bist Status. */
+        uint64_t pwq_wp1                 : 1;       /**< PWQ WQE PAGE1 PTR Memory Bist Status. */
+        uint64_t pwq_pow                 : 1;       /**< PWQ POW MEM Memory Bist Status. */
+        uint64_t ipq_pbe1                : 1;       /**< IPQ PBE1 Memory Bist Status. */
+        uint64_t ipq_pbe0                : 1;       /**< IPQ PBE0 Memory Bist Status. */
+        uint64_t pbm3                    : 1;       /**< PBM3 Memory Bist Status. */
+        uint64_t pbm2                    : 1;       /**< PBM2 Memory Bist Status. */
+        uint64_t pbm1                    : 1;       /**< PBM1 Memory Bist Status. */
+        uint64_t pbm0                    : 1;       /**< PBM0 Memory Bist Status. */
+        uint64_t pbm_word                : 1;       /**< PBM_WORD Memory Bist Status. */
+        uint64_t pwq1                    : 1;       /**< PWQ1 Memory Bist Status. */
+        uint64_t pwq0                    : 1;       /**< PWQ0 Memory Bist Status. */
+        uint64_t prc_off                 : 1;       /**< PRC_OFF Memory Bist Status. */
+        uint64_t ipd_old                 : 1;       /**< IPD_OLD Memory Bist Status. */
+        uint64_t ipd_new                 : 1;       /**< IPD_NEW Memory Bist Status. */
+        uint64_t pwp                     : 1;       /**< PWP Memory Bist Status. */
+#else
+        uint64_t pwp                     : 1;
+        uint64_t ipd_new                 : 1;
+        uint64_t ipd_old                 : 1;
+        uint64_t prc_off                 : 1;
+        uint64_t pwq0                    : 1;
+        uint64_t pwq1                    : 1;
+        uint64_t pbm_word                : 1;
+        uint64_t pbm0                    : 1;
+        uint64_t pbm1                    : 1;
+        uint64_t pbm2                    : 1;
+        uint64_t pbm3                    : 1;
+        uint64_t ipq_pbe0                : 1;
+        uint64_t ipq_pbe1                : 1;
+        uint64_t pwq_pow                 : 1;
+        uint64_t pwq_wp1                 : 1;
+        uint64_t pwq_wqed                : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn30xx;
+    struct cvmx_ipd_bist_status_cn30xx   cn31xx;
+    struct cvmx_ipd_bist_status_cn30xx   cn38xx;
+    struct cvmx_ipd_bist_status_cn30xx   cn38xxp2;
+    struct cvmx_ipd_bist_status_cn30xx   cn50xx;
+    struct cvmx_ipd_bist_status_s        cn52xx;
+    struct cvmx_ipd_bist_status_s        cn52xxp1;
+    struct cvmx_ipd_bist_status_s        cn56xx;
+    struct cvmx_ipd_bist_status_s        cn56xxp1;
+    struct cvmx_ipd_bist_status_cn30xx   cn58xx;
+    struct cvmx_ipd_bist_status_cn30xx   cn58xxp1;
+} cvmx_ipd_bist_status_t;
+
+
+/**
+ * cvmx_ipd_bp_prt_red_end
+ *
+ * IPD_BP_PRT_RED_END = IPD Backpressure Port RED Enable
+ * 
+ * When IPD applies backpressure to a PORT and the corresponding bit in this register is set,
+ * the RED Unit will drop packets for that port.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_bp_prt_red_end_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t prt_enb                 : 40;      /**< The port corresponding to the bit position in this
+                                                         field, will allow RED to drop back when port level
+                                                         backpressure is applied to the port. The applying
+                                                         of port-level backpressure for this RED dropping
+                                                         does not take into consideration the value of
+                                                         IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */
+#else
+        uint64_t prt_enb                 : 40;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t prt_enb                 : 36;      /**< The port corresponding to the bit position in this
+                                                         field, will allow RED to drop back when port level
+                                                         backpressure is applied to the port. The applying
+                                                         of port-level backpressure for this RED dropping
+                                                         does not take into consideration the value of
+                                                         IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */
+#else
+        uint64_t prt_enb                 : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } cn30xx;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
+    struct cvmx_ipd_bp_prt_red_end_s     cn52xx;
+    struct cvmx_ipd_bp_prt_red_end_s     cn52xxp1;
+    struct cvmx_ipd_bp_prt_red_end_s     cn56xx;
+    struct cvmx_ipd_bp_prt_red_end_s     cn56xxp1;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
+    struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+} cvmx_ipd_bp_prt_red_end_t;
+
+
+/**
+ * cvmx_ipd_clk_count
+ *
+ * IPD_CLK_COUNT = IPD Clock Count
+ * 
+ * Counts the number of core clocks periods since the de-asserition of reset.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_clk_count_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t clk_cnt                 : 64;      /**< This counter will be zeroed when reset is applied
+                                                         and will increment every rising edgge of the
+                                                         core-clock. PASS2 FIELD. */
+#else
+        uint64_t clk_cnt                 : 64;
+#endif
+    } s;
+    struct cvmx_ipd_clk_count_s          cn30xx;
+    struct cvmx_ipd_clk_count_s          cn31xx;
+    struct cvmx_ipd_clk_count_s          cn38xx;
+    struct cvmx_ipd_clk_count_s          cn38xxp2;
+    struct cvmx_ipd_clk_count_s          cn50xx;
+    struct cvmx_ipd_clk_count_s          cn52xx;
+    struct cvmx_ipd_clk_count_s          cn52xxp1;
+    struct cvmx_ipd_clk_count_s          cn56xx;
+    struct cvmx_ipd_clk_count_s          cn56xxp1;
+    struct cvmx_ipd_clk_count_s          cn58xx;
+    struct cvmx_ipd_clk_count_s          cn58xxp1;
+} cvmx_ipd_clk_count_t;
+
+
+/**
+ * cvmx_ipd_ctl_status
+ *
+ * IPD_CTL_STATUS = IPS'd Control Status Register
+ * 
+ * The number of words in a MBUFF used for packet data store.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t no_wptr                 : 1;       /**< When set '1' the WQE pointers will not be used and
+                                                         the WQE will be located at the front of the packet. */
+        uint64_t pq_apkt                 : 1;       /**< When set IPD_PORT_QOS_X_CNT WILL be incremented
+                                                         by one for every work queue entry that is sent to
+                                                         POW. */
+        uint64_t pq_nabuf                : 1;       /**< When set IPD_PORT_QOS_X_CNT WILL NOT be
+                                                         incremented when IPD allocates a buffer for a
+                                                         packet. */
+        uint64_t ipd_full                : 1;       /**< When clear '0' the IPD acts normaly.
+                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
+                                                         the IOB-arbiter, telling it to not give grants to
+                                                         NCB devices sending packet data. */
+        uint64_t pkt_off                 : 1;       /**< When clear '0' the IPD working normaly,
+                                                         buffering the received packet data. When set '1'
+                                                         the IPD will not buffer the received packet data. */
+        uint64_t len_m8                  : 1;       /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written wo the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN PASS2 generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW.
+                                                         PASS-2 Field. */
+        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port.
+                                                         PASS-2 Field. */
+        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
+        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
+        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit. */
+        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD.
+                                                         When clear '0', the IPD will appear to the
+                                                         IOB-arbiter to be applying backpressure, this
+                                                         causes the IOB-Arbiter to not send grants to NCB
+                                                         devices requesting to send packet data to the IPD. */
+#else
+        uint64_t ipd_en                  : 1;
+        cvmx_ipd_mode_t opc_mode         : 2;
+        uint64_t pbp_en                  : 1;
+        uint64_t wqe_lend                : 1;
+        uint64_t pkt_lend                : 1;
+        uint64_t naddbuf                 : 1;
+        uint64_t addpkt                  : 1;
+        uint64_t reset                   : 1;
+        uint64_t len_m8                  : 1;
+        uint64_t pkt_off                 : 1;
+        uint64_t ipd_full                : 1;
+        uint64_t pq_nabuf                : 1;
+        uint64_t pq_apkt                 : 1;
+        uint64_t no_wptr                 : 1;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_ipd_ctl_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t len_m8                  : 1;       /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written wo the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW. */
+        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port. */
+        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
+        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
+        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit.
+                                                         GMXX_INF_MODE[EN] must be set to '1' for each
+                                                         packet interface which requires port back pressure
+                                                         prior to setting PBP_EN to '1'. */
+        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD. */
+#else
+        uint64_t ipd_en                  : 1;
+        cvmx_ipd_mode_t opc_mode         : 2;
+        uint64_t pbp_en                  : 1;
+        uint64_t wqe_lend                : 1;
+        uint64_t pkt_lend                : 1;
+        uint64_t naddbuf                 : 1;
+        uint64_t addpkt                  : 1;
+        uint64_t reset                   : 1;
+        uint64_t len_m8                  : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn30xx;
+    struct cvmx_ipd_ctl_status_cn30xx    cn31xx;
+    struct cvmx_ipd_ctl_status_cn30xx    cn38xx;
+    struct cvmx_ipd_ctl_status_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW.
+                                                         PASS-2 Field. */
+        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port.
+                                                         PASS-2 Field. */
+        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
+        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
+        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit. */
+        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD. */
+#else
+        uint64_t ipd_en                  : 1;
+        cvmx_ipd_mode_t opc_mode         : 2;
+        uint64_t pbp_en                  : 1;
+        uint64_t wqe_lend                : 1;
+        uint64_t pkt_lend                : 1;
+        uint64_t naddbuf                 : 1;
+        uint64_t addpkt                  : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn38xxp2;
+    struct cvmx_ipd_ctl_status_s         cn50xx;
+    struct cvmx_ipd_ctl_status_s         cn52xx;
+    struct cvmx_ipd_ctl_status_s         cn52xxp1;
+    struct cvmx_ipd_ctl_status_s         cn56xx;
+    struct cvmx_ipd_ctl_status_s         cn56xxp1;
+    struct cvmx_ipd_ctl_status_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t ipd_full                : 1;       /**< When clear '0' the IPD acts normaly.
+                                                         When set '1' the IPD drive the IPD_BUFF_FULL line to
+                                                         the IOB-arbiter, telling it to not give grants to
+                                                         NCB devices sending packet data. */
+        uint64_t pkt_off                 : 1;       /**< When clear '0' the IPD working normaly,
+                                                         buffering the received packet data. When set '1'
+                                                         the IPD will not buffer the received packet data. */
+        uint64_t len_m8                  : 1;       /**< Setting of this bit will subtract 8 from the
+                                                         data-length field in the header written wo the
+                                                         POW and the top of a MBUFF.
+                                                         OCTEAN PASS2 generates a length that includes the
+                                                         length of the data + 8 for the header-field. By
+                                                         setting this bit the 8 for the instr-field will
+                                                         not be included in the length field of the header.
+                                                         NOTE: IPD is compliant with the spec when this
+                                                         field is '1'. */
+        uint64_t reset                   : 1;       /**< When set '1' causes a reset of the IPD, except
+                                                         RSL. */
+        uint64_t addpkt                  : 1;       /**< When IPD_CTL_STATUS[ADDPKT] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL be incremented by one for every work
+                                                         queue entry that is sent to POW.
+                                                         PASS-2 Field. */
+        uint64_t naddbuf                 : 1;       /**< When IPD_CTL_STATUS[NADDBUF] is set,
+                                                         IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL]
+                                                         WILL NOT be incremented when IPD allocates a
+                                                         buffer for a packet on the port.
+                                                         PASS-2 Field. */
+        uint64_t pkt_lend                : 1;       /**< Changes PKT to little endian writes to L2C */
+        uint64_t wqe_lend                : 1;       /**< Changes WQE to little endian writes to L2C */
+        uint64_t pbp_en                  : 1;       /**< Port back pressure enable. When set '1' enables
+                                                         the sending of port level backpressure to the
+                                                         Octane input-ports. Once enabled the sending of
+                                                         port-level-backpressure can not be disabled by
+                                                         changing the value of this bit. */
+        cvmx_ipd_mode_t opc_mode         : 2;       /**< 0 ==> All packet data (and next buffer pointers)
+                                                         is written through to memory.
+                                                         1 ==> All packet data (and next buffer pointers) is
+                                                         written into the cache.
+                                                         2 ==> The first aligned cache block holding the
+                                                         packet data (and initial next buffer pointer) is
+                                                         written to the L2 cache, all remaining cache blocks
+                                                         are not written to the L2 cache.
+                                                         3 ==> The first two aligned cache blocks holding
+                                                         the packet data (and initial next buffer pointer)
+                                                         are written to the L2 cache, all remaining cache
+                                                         blocks are not written to the L2 cache. */
+        uint64_t ipd_en                  : 1;       /**< When set '1' enable the operation of the IPD.
+                                                         When clear '0', the IPD will appear to the
+                                                         IOB-arbiter to be applying backpressure, this
+                                                         causes the IOB-Arbiter to not send grants to NCB
+                                                         devices requesting to send packet data to the IPD. */
+#else
+        uint64_t ipd_en                  : 1;
+        cvmx_ipd_mode_t opc_mode         : 2;
+        uint64_t pbp_en                  : 1;
+        uint64_t wqe_lend                : 1;
+        uint64_t pkt_lend                : 1;
+        uint64_t naddbuf                 : 1;
+        uint64_t addpkt                  : 1;
+        uint64_t reset                   : 1;
+        uint64_t len_m8                  : 1;
+        uint64_t pkt_off                 : 1;
+        uint64_t ipd_full                : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn58xx;
+    struct cvmx_ipd_ctl_status_cn58xx    cn58xxp1;
+} cvmx_ipd_ctl_status_t;
+
+
+/**
+ * cvmx_ipd_int_enb
+ *
+ * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register
+ * 
+ * Used to enable the various interrupting conditions of IPD
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t pq_sub                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+        uint64_t pq_add                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set. */
+        uint64_t bc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t d_coll                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t c_coll                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t cc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t dc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t bp_sub                  : 1;       /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+        uint64_t prc_par3                : 1;       /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+        uint64_t prc_par2                : 1;       /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+        uint64_t prc_par1                : 1;       /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+        uint64_t prc_par0                : 1;       /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+        uint64_t prc_par0                : 1;
+        uint64_t prc_par1                : 1;
+        uint64_t prc_par2                : 1;
+        uint64_t prc_par3                : 1;
+        uint64_t bp_sub                  : 1;
+        uint64_t dc_ovr                  : 1;
+        uint64_t cc_ovr                  : 1;
+        uint64_t c_coll                  : 1;
+        uint64_t d_coll                  : 1;
+        uint64_t bc_ovr                  : 1;
+        uint64_t pq_add                  : 1;
+        uint64_t pq_sub                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_ipd_int_enb_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t bp_sub                  : 1;       /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+        uint64_t prc_par3                : 1;       /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+        uint64_t prc_par2                : 1;       /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+        uint64_t prc_par1                : 1;       /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+        uint64_t prc_par0                : 1;       /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+        uint64_t prc_par0                : 1;
+        uint64_t prc_par1                : 1;
+        uint64_t prc_par2                : 1;
+        uint64_t prc_par3                : 1;
+        uint64_t bp_sub                  : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn30xx;
+    struct cvmx_ipd_int_enb_cn30xx       cn31xx;
+    struct cvmx_ipd_int_enb_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t bc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t d_coll                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t c_coll                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t cc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t dc_ovr                  : 1;       /**< Allows an interrupt to be sent when the
+                                                         corresponding bit in the IPD_INT_SUM is set.
+                                                         This is a PASS-3 Field. */
+        uint64_t bp_sub                  : 1;       /**< Enables interrupts when a backpressure subtract
+                                                         has an illegal value. */
+        uint64_t prc_par3                : 1;       /**< Enable parity error interrupts for bits
+                                                         [127:96] of the PBM memory. */
+        uint64_t prc_par2                : 1;       /**< Enable parity error interrupts for bits
+                                                         [95:64] of the PBM memory. */
+        uint64_t prc_par1                : 1;       /**< Enable parity error interrupts for bits
+                                                         [63:32] of the PBM memory. */
+        uint64_t prc_par0                : 1;       /**< Enable parity error interrupts for bits
+                                                         [31:0] of the PBM memory. */
+#else
+        uint64_t prc_par0                : 1;
+        uint64_t prc_par1                : 1;
+        uint64_t prc_par2                : 1;
+        uint64_t prc_par3                : 1;
+        uint64_t bp_sub                  : 1;
+        uint64_t dc_ovr                  : 1;
+        uint64_t cc_ovr                  : 1;
+        uint64_t c_coll                  : 1;
+        uint64_t d_coll                  : 1;
+        uint64_t bc_ovr                  : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn38xx;
+    struct cvmx_ipd_int_enb_cn30xx       cn38xxp2;
+    struct cvmx_ipd_int_enb_cn38xx       cn50xx;
+    struct cvmx_ipd_int_enb_s            cn52xx;
+    struct cvmx_ipd_int_enb_s            cn52xxp1;
+    struct cvmx_ipd_int_enb_s            cn56xx;
+    struct cvmx_ipd_int_enb_s            cn56xxp1;
+    struct cvmx_ipd_int_enb_cn38xx       cn58xx;
+    struct cvmx_ipd_int_enb_cn38xx       cn58xxp1;
+} cvmx_ipd_int_enb_t;
+
+
+/**
+ * cvmx_ipd_int_sum
+ *
+ * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register
+ * 
+ * Set when an interrupt condition occurs, write '1' to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t pq_sub                  : 1;       /**< Set when a port-qos does an sub to the count
+                                                         that causes the counter to wrap. */
+        uint64_t pq_add                  : 1;       /**< Set when a port-qos does an add to the count
+                                                         that causes the counter to wrap. */
+        uint64_t bc_ovr                  : 1;       /**< Set when the byte-count to send to IOB overflows.
+                                                         This is a PASS-3 Field. */
+        uint64_t d_coll                  : 1;       /**< Set when the packet/WQE data to be sent to IOB
+                                                         collides.
+                                                         This is a PASS-3 Field. */
+        uint64_t c_coll                  : 1;       /**< Set when the packet/WQE commands to be sent to IOB
+                                                         collides.
+                                                         This is a PASS-3 Field. */
+        uint64_t cc_ovr                  : 1;       /**< Set when the command credits to the IOB overflow.
+                                                         This is a PASS-3 Field. */
+        uint64_t dc_ovr                  : 1;       /**< Set when the data credits to the IOB overflow.
+                                                         This is a PASS-3 Field. */
+        uint64_t bp_sub                  : 1;       /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+        uint64_t prc_par3                : 1;       /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+        uint64_t prc_par2                : 1;       /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+        uint64_t prc_par1                : 1;       /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+        uint64_t prc_par0                : 1;       /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+        uint64_t prc_par0                : 1;
+        uint64_t prc_par1                : 1;
+        uint64_t prc_par2                : 1;
+        uint64_t prc_par3                : 1;
+        uint64_t bp_sub                  : 1;
+        uint64_t dc_ovr                  : 1;
+        uint64_t cc_ovr                  : 1;
+        uint64_t c_coll                  : 1;
+        uint64_t d_coll                  : 1;
+        uint64_t bc_ovr                  : 1;
+        uint64_t pq_add                  : 1;
+        uint64_t pq_sub                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_ipd_int_sum_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t bp_sub                  : 1;       /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+        uint64_t prc_par3                : 1;       /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+        uint64_t prc_par2                : 1;       /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+        uint64_t prc_par1                : 1;       /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+        uint64_t prc_par0                : 1;       /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+        uint64_t prc_par0                : 1;
+        uint64_t prc_par1                : 1;
+        uint64_t prc_par2                : 1;
+        uint64_t prc_par3                : 1;
+        uint64_t bp_sub                  : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn30xx;
+    struct cvmx_ipd_int_sum_cn30xx       cn31xx;
+    struct cvmx_ipd_int_sum_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t bc_ovr                  : 1;       /**< Set when the byte-count to send to IOB overflows.
+                                                         This is a PASS-3 Field. */
+        uint64_t d_coll                  : 1;       /**< Set when the packet/WQE data to be sent to IOB
+                                                         collides.
+                                                         This is a PASS-3 Field. */
+        uint64_t c_coll                  : 1;       /**< Set when the packet/WQE commands to be sent to IOB
+                                                         collides.
+                                                         This is a PASS-3 Field. */
+        uint64_t cc_ovr                  : 1;       /**< Set when the command credits to the IOB overflow.
+                                                         This is a PASS-3 Field. */
+        uint64_t dc_ovr                  : 1;       /**< Set when the data credits to the IOB overflow.
+                                                         This is a PASS-3 Field. */
+        uint64_t bp_sub                  : 1;       /**< Set when a backpressure subtract is done with a
+                                                         supplied illegal value. */
+        uint64_t prc_par3                : 1;       /**< Set when a parity error is dected for bits
+                                                         [127:96] of the PBM memory. */
+        uint64_t prc_par2                : 1;       /**< Set when a parity error is dected for bits
+                                                         [95:64] of the PBM memory. */
+        uint64_t prc_par1                : 1;       /**< Set when a parity error is dected for bits
+                                                         [63:32] of the PBM memory. */
+        uint64_t prc_par0                : 1;       /**< Set when a parity error is dected for bits
+                                                         [31:0] of the PBM memory. */
+#else
+        uint64_t prc_par0                : 1;
+        uint64_t prc_par1                : 1;
+        uint64_t prc_par2                : 1;
+        uint64_t prc_par3                : 1;
+        uint64_t bp_sub                  : 1;
+        uint64_t dc_ovr                  : 1;
+        uint64_t cc_ovr                  : 1;
+        uint64_t c_coll                  : 1;
+        uint64_t d_coll                  : 1;
+        uint64_t bc_ovr                  : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn38xx;
+    struct cvmx_ipd_int_sum_cn30xx       cn38xxp2;
+    struct cvmx_ipd_int_sum_cn38xx       cn50xx;
+    struct cvmx_ipd_int_sum_s            cn52xx;
+    struct cvmx_ipd_int_sum_s            cn52xxp1;
+    struct cvmx_ipd_int_sum_s            cn56xx;
+    struct cvmx_ipd_int_sum_s            cn56xxp1;
+    struct cvmx_ipd_int_sum_cn38xx       cn58xx;
+    struct cvmx_ipd_int_sum_cn38xx       cn58xxp1;
+} cvmx_ipd_int_sum_t;
+
+
+/**
+ * cvmx_ipd_not_1st_mbuff_skip
+ *
+ * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size
+ * 
+ * The number of words that the IPD will skip when writing any MBUFF that is not the first.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_not_1st_mbuff_skip_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t skip_sz                 : 6;       /**< The number of 8-byte words from the top of any
+                                                         MBUFF, that is not the 1st MBUFF, that the IPD
+                                                         will write the next-pointer.
+                                                         Legal values are 0 to 32, where the MAX value
+                                                         is also limited to:
+                                                         IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 16. */
+#else
+        uint64_t skip_sz                 : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
+    struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
+} cvmx_ipd_not_1st_mbuff_skip_t;
+
+
+/**
+ * cvmx_ipd_packet_mbuff_size
+ *
+ * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words
+ * 
+ * The number of words in a MBUFF used for packet data store.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_packet_mbuff_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t mb_size                 : 12;      /**< The number of 8-byte words in a MBUF.
+                                                         This must be a number in the range of 32 to
+                                                         2048.
+                                                         This is also the size of the FPA's
+                                                         Queue-0 Free-Page. */
+#else
+        uint64_t mb_size                 : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_ipd_packet_mbuff_size_s  cn30xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn31xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn38xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn38xxp2;
+    struct cvmx_ipd_packet_mbuff_size_s  cn50xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn52xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn52xxp1;
+    struct cvmx_ipd_packet_mbuff_size_s  cn56xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn56xxp1;
+    struct cvmx_ipd_packet_mbuff_size_s  cn58xx;
+    struct cvmx_ipd_packet_mbuff_size_s  cn58xxp1;
+} cvmx_ipd_packet_mbuff_size_t;
+
+
+/**
+ * cvmx_ipd_pkt_ptr_valid
+ *
+ * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid
+ * 
+ * The value of the packet-pointer fetched and in the valid register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_pkt_ptr_valid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t ptr                     : 29;      /**< Pointer value. */
+#else
+        uint64_t ptr                     : 29;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn30xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn31xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn38xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn50xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn52xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn52xxp1;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn56xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn56xxp1;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn58xx;
+    struct cvmx_ipd_pkt_ptr_valid_s      cn58xxp1;
+} cvmx_ipd_pkt_ptr_valid_t;
+
+
+/**
+ * cvmx_ipd_port#_bp_page_cnt
+ *
+ * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count
+ * 
+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_portx_bp_page_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t bp_enb                  : 1;       /**< When set '1' BP will be applied, if '0' BP will
+                                                         not be applied to port. */
+        uint64_t page_cnt                : 17;      /**< The number of page pointers assigned to
+                                                         the port, that when exceeded will cause
+                                                         back-pressure to be applied to the port.
+                                                         This value is in 256 page-pointer increments,
+                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
+#else
+        uint64_t page_cnt                : 17;
+        uint64_t bp_enb                  : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn30xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn31xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn38xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn38xxp2;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn50xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn52xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn52xxp1;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn56xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn56xxp1;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn58xx;
+    struct cvmx_ipd_portx_bp_page_cnt_s  cn58xxp1;
+} cvmx_ipd_portx_bp_page_cnt_t;
+
+
+/**
+ * cvmx_ipd_port#_bp_page_cnt2
+ *
+ * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count
+ * 
+ * The number of pages in use by the port that when exceeded, backpressure will be applied to the port.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_portx_bp_page_cnt2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t bp_enb                  : 1;       /**< When set '1' BP will be applied, if '0' BP will
+                                                         not be applied to port. */
+        uint64_t page_cnt                : 17;      /**< The number of page pointers assigned to
+                                                         the port, that when exceeded will cause
+                                                         back-pressure to be applied to the port.
+                                                         This value is in 256 page-pointer increments,
+                                                         (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */
+#else
+        uint64_t page_cnt                : 17;
+        uint64_t bp_enb                  : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
+    struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
+    struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
+    struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
+} cvmx_ipd_portx_bp_page_cnt2_t;
+
+
+/**
+ * cvmx_ipd_port_bp_counters2_pair#
+ *
+ * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_port_bp_counters2_pairx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_25_63          : 39;
+        uint64_t cnt_val                 : 25;      /**< Number of MBUFs being used by data on this port. */
+#else
+        uint64_t cnt_val                 : 25;
+        uint64_t reserved_25_63          : 39;
+#endif
+    } s;
+    struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
+    struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
+    struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
+    struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+} cvmx_ipd_port_bp_counters2_pairx_t;
+
+
+/**
+ * cvmx_ipd_port_bp_counters_pair#
+ *
+ * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_port_bp_counters_pairx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_25_63          : 39;
+        uint64_t cnt_val                 : 25;      /**< Number of MBUFs being used by data on this port. */
+#else
+        uint64_t cnt_val                 : 25;
+        uint64_t reserved_25_63          : 39;
+#endif
+    } s;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
+    struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+} cvmx_ipd_port_bp_counters_pairx_t;
+
+
+/**
+ * cvmx_ipd_port_qos_#_cnt
+ *
+ * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count
+ * 
+ * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7) belong to Port-0
+ * QOS 0-7 respectively followed by port 1 at (8-15), etc
+ * Ports 0-3, 36-39
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_port_qos_x_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t wmark                   : 32;      /**< When the field CNT after being modified is equal to
+                                                         or crosses this value (i.e. value was greater than
+                                                         then becomes less then, or value was less than and
+                                                         becomes greater than) the cooresponding bit in
+                                                         IPD_PORT_QOS_INTX is set. */
+        uint64_t cnt                     : 32;      /**< The packet related count that is incremented as
+                                                         specified by IPD_SUB_PORT_QOS_CNT. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t wmark                   : 32;
+#endif
+    } s;
+    struct cvmx_ipd_port_qos_x_cnt_s     cn52xx;
+    struct cvmx_ipd_port_qos_x_cnt_s     cn52xxp1;
+    struct cvmx_ipd_port_qos_x_cnt_s     cn56xx;
+    struct cvmx_ipd_port_qos_x_cnt_s     cn56xxp1;
+} cvmx_ipd_port_qos_x_cnt_t;
+
+
+/**
+ * cvmx_ipd_port_qos_int#
+ *
+ * IPD_PORT_QOS_INTX = IPD PORT-QOS Interrupt
+ * 
+ * See the description for IPD_PORT_QOS_X_CNT
+ * 
+ * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63
+ * Only ports used are: P0-3, and P32-39. Therefore only IPD_PORT_QOS_INT0[31:0] and IPD_PORT_QOS_INT4[63:0] exist.
+ * Unused registers and register fields are reserved.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_port_qos_intx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t intr                    : 64;      /**< Interrupt bits. */
+#else
+        uint64_t intr                    : 64;
+#endif
+    } s;
+    struct cvmx_ipd_port_qos_intx_s      cn52xx;
+    struct cvmx_ipd_port_qos_intx_s      cn52xxp1;
+    struct cvmx_ipd_port_qos_intx_s      cn56xx;
+    struct cvmx_ipd_port_qos_intx_s      cn56xxp1;
+} cvmx_ipd_port_qos_intx_t;
+
+
+/**
+ * cvmx_ipd_port_qos_int_enb#
+ *
+ * IPD_PORT_QOS_INT_ENBX = IPD PORT-QOS Interrupt Enable
+ * 
+ * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_port_qos_int_enbx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t enb                     : 64;      /**< Enable bits. */
+#else
+        uint64_t enb                     : 64;
+#endif
+    } s;
+    struct cvmx_ipd_port_qos_int_enbx_s  cn52xx;
+    struct cvmx_ipd_port_qos_int_enbx_s  cn52xxp1;
+    struct cvmx_ipd_port_qos_int_enbx_s  cn56xx;
+    struct cvmx_ipd_port_qos_int_enbx_s  cn56xxp1;
+} cvmx_ipd_port_qos_int_enbx_t;
+
+
+/**
+ * cvmx_ipd_prc_hold_ptr_fifo_ctl
+ *
+ * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control
+ * 
+ * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t max_pkt                 : 3;       /**< Maximum number of Packet-Pointers that COULD be
+                                                         in the FIFO. */
+        uint64_t praddr                  : 3;       /**< Present Packet-Pointer read address. */
+        uint64_t ptr                     : 29;      /**< The output of the prc-holding-fifo. */
+        uint64_t cena                    : 1;       /**< Active low Chip Enable that controls the
+                                                         MUX-select that steers [RADDR] to the fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+        uint64_t raddr                   : 3;       /**< Sets the address to read from in the holding.
+                                                         fifo in the PRC. This FIFO holds Packet-Pointers
+                                                         to be used for packet data storage. */
+#else
+        uint64_t raddr                   : 3;
+        uint64_t cena                    : 1;
+        uint64_t ptr                     : 29;
+        uint64_t praddr                  : 3;
+        uint64_t max_pkt                 : 3;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } s;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
+    struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+} cvmx_ipd_prc_hold_ptr_fifo_ctl_t;
+
+
+/**
+ * cvmx_ipd_prc_port_ptr_fifo_ctl
+ *
+ * IPD_PRC_PORT_PTR_FIFO_CTL = IPD's PRC PORT Pointer FIFO Control
+ * 
+ * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t max_pkt                 : 7;       /**< Maximum number of Packet-Pointers that are in
+                                                         in the FIFO. */
+        uint64_t ptr                     : 29;      /**< The output of the prc-port-ptr-fifo. */
+        uint64_t cena                    : 1;       /**< Active low Chip Enable to the read port of the
+                                                         pwp_fifo. This bit also controls the MUX-select
+                                                         that steers [RADDR] to the pwp_fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+        uint64_t raddr                   : 7;       /**< Sets the address to read from in the port
+                                                         fifo in the PRC. This FIFO holds Packet-Pointers
+                                                         to be used for packet data storage. */
+#else
+        uint64_t raddr                   : 7;
+        uint64_t cena                    : 1;
+        uint64_t ptr                     : 29;
+        uint64_t max_pkt                 : 7;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
+    struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+} cvmx_ipd_prc_port_ptr_fifo_ctl_t;
+
+
+/**
+ * cvmx_ipd_ptr_count
+ *
+ * IPD_PTR_COUNT = IPD Page Pointer Count
+ * 
+ * Shows the number of WQE and Packet Page Pointers stored in the IPD.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_ptr_count_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t pktv_cnt                : 1;       /**< PKT Ptr Valid. PASS2 Field */
+        uint64_t wqev_cnt                : 1;       /**< WQE Ptr Valid. This value is '1' when a WQE
+                                                         is being for use by the IPD. The value of this
+                                                         field shoould be added to tha value of the
+                                                         WQE_PCNT field, of this register, for a total
+                                                         count of the WQE Page Pointers being held by IPD.
+                                                         PASS2 Field. */
+        uint64_t pfif_cnt                : 3;       /**< See PKT_PCNT. */
+        uint64_t pkt_pcnt                : 7;       /**< This value plus PFIF_CNT plus 36 is the number
+                                                         of PKT Page Pointers in IPD. */
+        uint64_t wqe_pcnt                : 7;       /**< Number of page pointers for WQE storage that are
+                                                         buffered in the IPD. The total count is the value
+                                                         of this buffer plus the field [WQEV_CNT]. For
+                                                         PASS-1 (which does not have the WQEV_CNT field)
+                                                         when the value of this register is '0' there still
+                                                         may be 1 pointer being help by IPD. */
+#else
+        uint64_t wqe_pcnt                : 7;
+        uint64_t pkt_pcnt                : 7;
+        uint64_t pfif_cnt                : 3;
+        uint64_t wqev_cnt                : 1;
+        uint64_t pktv_cnt                : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } s;
+    struct cvmx_ipd_ptr_count_s          cn30xx;
+    struct cvmx_ipd_ptr_count_s          cn31xx;
+    struct cvmx_ipd_ptr_count_s          cn38xx;
+    struct cvmx_ipd_ptr_count_s          cn38xxp2;
+    struct cvmx_ipd_ptr_count_s          cn50xx;
+    struct cvmx_ipd_ptr_count_s          cn52xx;
+    struct cvmx_ipd_ptr_count_s          cn52xxp1;
+    struct cvmx_ipd_ptr_count_s          cn56xx;
+    struct cvmx_ipd_ptr_count_s          cn56xxp1;
+    struct cvmx_ipd_ptr_count_s          cn58xx;
+    struct cvmx_ipd_ptr_count_s          cn58xxp1;
+} cvmx_ipd_ptr_count_t;
+
+
+/**
+ * cvmx_ipd_pwp_ptr_fifo_ctl
+ *
+ * IPD_PWP_PTR_FIFO_CTL = IPD's PWP Pointer FIFO Control
+ * 
+ * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_61_63          : 3;
+        uint64_t max_cnts                : 7;       /**< Maximum number of Packet-Pointers or WQE-Pointers
+                                                         that COULD be in the FIFO. */
+        uint64_t wraddr                  : 8;       /**< Present FIFO WQE Read address. */
+        uint64_t praddr                  : 8;       /**< Present FIFO Packet Read address. */
+        uint64_t ptr                     : 29;      /**< The output of the pwp_fifo. */
+        uint64_t cena                    : 1;       /**< Active low Chip Enable to the read port of the
+                                                         pwp_fifo. This bit also controls the MUX-select
+                                                         that steers [RADDR] to the pwp_fifo.
+                                                         *WARNING - Setting this field to '0' will allow
+                                                         reading of the memories thorugh the PTR field,
+                                                         but will cause unpredictable operation of the IPD
+                                                         under normal operation. */
+        uint64_t raddr                   : 8;       /**< Sets the address to read from in the pwp_fifo.
+                                                         Addresses 0 through 7 contain Packet-Pointers and
+                                                         addresses 8 through 15 contain WQE-Pointers. */
+#else
+        uint64_t raddr                   : 8;
+        uint64_t cena                    : 1;
+        uint64_t ptr                     : 29;
+        uint64_t praddr                  : 8;
+        uint64_t wraddr                  : 8;
+        uint64_t max_cnts                : 7;
+        uint64_t reserved_61_63          : 3;
+#endif
+    } s;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn30xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn31xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn38xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn50xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn52xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn52xxp1;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn56xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn56xxp1;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn58xx;
+    struct cvmx_ipd_pwp_ptr_fifo_ctl_s   cn58xxp1;
+} cvmx_ipd_pwp_ptr_fifo_ctl_t;
+
+
+/**
+ * cvmx_ipd_qos#_red_marks
+ *
+ * IPD_QOS0_RED_MARKS = IPD QOS 0 Marks Red High Low
+ * 
+ * Set the pass-drop marks for qos level.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_qosx_red_marks_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t drop                    : 32;      /**< Packets will be dropped when the average value of
+                                                         IPD_QUE0_FREE_PAGE_CNT is equal to or less than
+                                                         this value. */
+        uint64_t pass                    : 32;      /**< Packets will be passed when the average value of
+                                                         IPD_QUE0_FREE_PAGE_CNT is larger than this value. */
+#else
+        uint64_t pass                    : 32;
+        uint64_t drop                    : 32;
+#endif
+    } s;
+    struct cvmx_ipd_qosx_red_marks_s     cn30xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn31xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn38xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn38xxp2;
+    struct cvmx_ipd_qosx_red_marks_s     cn50xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn52xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn52xxp1;
+    struct cvmx_ipd_qosx_red_marks_s     cn56xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn56xxp1;
+    struct cvmx_ipd_qosx_red_marks_s     cn58xx;
+    struct cvmx_ipd_qosx_red_marks_s     cn58xxp1;
+} cvmx_ipd_qosx_red_marks_t;
+
+
+/**
+ * cvmx_ipd_que0_free_page_cnt
+ *
+ * IPD_QUE0_FREE_PAGE_CNT = IPD Queue0 Free Page Count
+ * 
+ * Number of Free-Page Pointer that are available for use in the FPA for Queue-0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_que0_free_page_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t q0_pcnt                 : 32;      /**< Number of Queue-0 Page Pointers Available. */
+#else
+        uint64_t q0_pcnt                 : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
+    struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
+    struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
+    struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
+    struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
+} cvmx_ipd_que0_free_page_cnt_t;
+
+
+/**
+ * cvmx_ipd_red_port_enable
+ *
+ * IPD_RED_PORT_ENABLE = IPD RED Port Enable
+ * 
+ * Set the pass-drop marks for qos level.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_red_port_enable_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t prb_dly                 : 14;      /**< Number (core clocks periods + 68) * 8 to wait
+                                                         before caluclating the new packet drop
+                                                         probability for each QOS level. */
+        uint64_t avg_dly                 : 14;      /**< Number (core clocks periods + 10) * 8 to wait
+                                                         before caluclating the moving average for wach
+                                                         QOS level.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+        uint64_t prt_enb                 : 36;      /**< The bit position will enable the corresponding
+                                                         Ports ability to have packets dropped by RED
+                                                         probability. */
+#else
+        uint64_t prt_enb                 : 36;
+        uint64_t avg_dly                 : 14;
+        uint64_t prb_dly                 : 14;
+#endif
+    } s;
+    struct cvmx_ipd_red_port_enable_s    cn30xx;
+    struct cvmx_ipd_red_port_enable_s    cn31xx;
+    struct cvmx_ipd_red_port_enable_s    cn38xx;
+    struct cvmx_ipd_red_port_enable_s    cn38xxp2;
+    struct cvmx_ipd_red_port_enable_s    cn50xx;
+    struct cvmx_ipd_red_port_enable_s    cn52xx;
+    struct cvmx_ipd_red_port_enable_s    cn52xxp1;
+    struct cvmx_ipd_red_port_enable_s    cn56xx;
+    struct cvmx_ipd_red_port_enable_s    cn56xxp1;
+    struct cvmx_ipd_red_port_enable_s    cn58xx;
+    struct cvmx_ipd_red_port_enable_s    cn58xxp1;
+} cvmx_ipd_red_port_enable_t;
+
+
+/**
+ * cvmx_ipd_red_port_enable2
+ *
+ * IPD_RED_PORT_ENABLE2 = IPD RED Port Enable2
+ * 
+ * Set the pass-drop marks for qos level.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_red_port_enable2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t prt_enb                 : 4;       /**< Bits 3-0 cooresponds to ports 39-36. These bits
+                                                         have the same meaning as the PRT_ENB field of
+                                                         IPD_RED_PORT_ENABLE. */
+#else
+        uint64_t prt_enb                 : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_ipd_red_port_enable2_s   cn52xx;
+    struct cvmx_ipd_red_port_enable2_s   cn52xxp1;
+    struct cvmx_ipd_red_port_enable2_s   cn56xx;
+    struct cvmx_ipd_red_port_enable2_s   cn56xxp1;
+} cvmx_ipd_red_port_enable2_t;
+
+
+/**
+ * cvmx_ipd_red_que#_param
+ *
+ * IPD_RED_QUE0_PARAM = IPD RED Queue-0 Parameters
+ * 
+ * Value control the Passing and Dropping of packets by the red engine for QOS Level-0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_red_quex_param_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t use_pcnt                : 1;       /**< When set '1' red will use the actual Packet-Page
+                                                         Count in place of the Average for RED calculations. */
+        uint64_t new_con                 : 8;       /**< This value is used control how much of the present
+                                                         Actual Queue Size is used to calculate the new
+                                                         Average Queue Size. The value is a number from 0
+                                                         256, which represents NEW_CON/256 of the Actual
+                                                         Queue Size that will be used in the calculation.
+                                                         The number in this field plus the value of
+                                                         AVG_CON must be equal to 256.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+        uint64_t avg_con                 : 8;       /**< This value is used control how much of the present
+                                                         Average Queue Size is used to calculate the new
+                                                         Average Queue Size. The value is a number from 0
+                                                         256, which represents AVG_CON/256 of the Average
+                                                         Queue Size that will be used in the calculation.
+                                                         The number in this field plus the value of
+                                                         NEW_CON must be equal to 256.
+                                                         Larger AVG_DLY values cause the moving averages
+                                                         of ALL QOS levels to track changes in the actual
+                                                         free space more slowly. Smaller NEW_CON (and
+                                                         larger AVG_CON) values can have a similar effect,
+                                                         but only affect an individual QOS level, rather
+                                                         than all. */
+        uint64_t prb_con                 : 32;      /**< Used in computing the probability of a packet being
+                                                         passed or drop by the WRED engine. The field is
+                                                         calculated to be (255 * 2^24)/(PASS-DROP). Where
+                                                         PASS and DROP are the field from the
+                                                         IPD_QOS0_RED_MARKS CSR. */
+#else
+        uint64_t prb_con                 : 32;
+        uint64_t avg_con                 : 8;
+        uint64_t new_con                 : 8;
+        uint64_t use_pcnt                : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_ipd_red_quex_param_s     cn30xx;
+    struct cvmx_ipd_red_quex_param_s     cn31xx;
+    struct cvmx_ipd_red_quex_param_s     cn38xx;
+    struct cvmx_ipd_red_quex_param_s     cn38xxp2;
+    struct cvmx_ipd_red_quex_param_s     cn50xx;
+    struct cvmx_ipd_red_quex_param_s     cn52xx;
+    struct cvmx_ipd_red_quex_param_s     cn52xxp1;
+    struct cvmx_ipd_red_quex_param_s     cn56xx;
+    struct cvmx_ipd_red_quex_param_s     cn56xxp1;
+    struct cvmx_ipd_red_quex_param_s     cn58xx;
+    struct cvmx_ipd_red_quex_param_s     cn58xxp1;
+} cvmx_ipd_red_quex_param_t;
+
+
+/**
+ * cvmx_ipd_sub_port_bp_page_cnt
+ *
+ * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count
+ * 
+ * Will add the value to the indicated port count register, the number of pages supplied. The value added should
+ * be the 2's complement of the vallue that needs to be subtracted. Users would add 2's compliment values to the
+ * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid port-level
+ * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a port exceeds the
+ * value in the IPD_PORTX_BP_PAGE_CNT.
+ * 
+ * This register can't be written from the PCI via a window write.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t port                    : 6;       /**< The port to add the PAGE_CNT field to. */
+        uint64_t page_cnt                : 25;      /**< The number of page pointers to add to
+                                                         the port counter pointed to by the
+                                                         PORT Field. */
+#else
+        uint64_t page_cnt                : 25;
+        uint64_t port                    : 6;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
+    struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+} cvmx_ipd_sub_port_bp_page_cnt_t;
+
+
+/**
+ * cvmx_ipd_sub_port_fcs
+ *
+ * IPD_SUB_PORT_FCS = IPD Subtract Ports FCS Register
+ * 
+ * When set '1' the port corresponding to the but set will subtract 4 bytes from the end of
+ * the packet.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_sub_port_fcs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t port_bit2               : 4;       /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+        uint64_t reserved_32_35          : 4;
+        uint64_t port_bit                : 32;      /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+#else
+        uint64_t port_bit                : 32;
+        uint64_t reserved_32_35          : 4;
+        uint64_t port_bit2               : 4;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_ipd_sub_port_fcs_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t port_bit                : 3;       /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+#else
+        uint64_t port_bit                : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_ipd_sub_port_fcs_cn30xx  cn31xx;
+    struct cvmx_ipd_sub_port_fcs_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t port_bit                : 32;      /**< When set '1', the port corresponding to the bit
+                                                         position set, will subtract the FCS for packets
+                                                         on that port. */
+#else
+        uint64_t port_bit                : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn38xx;
+    struct cvmx_ipd_sub_port_fcs_cn38xx  cn38xxp2;
+    struct cvmx_ipd_sub_port_fcs_cn30xx  cn50xx;
+    struct cvmx_ipd_sub_port_fcs_s       cn52xx;
+    struct cvmx_ipd_sub_port_fcs_s       cn52xxp1;
+    struct cvmx_ipd_sub_port_fcs_s       cn56xx;
+    struct cvmx_ipd_sub_port_fcs_s       cn56xxp1;
+    struct cvmx_ipd_sub_port_fcs_cn38xx  cn58xx;
+    struct cvmx_ipd_sub_port_fcs_cn38xx  cn58xxp1;
+} cvmx_ipd_sub_port_fcs_t;
+
+
+/**
+ * cvmx_ipd_sub_port_qos_cnt
+ *
+ * IPD_SUB_PORT_QOS_CNT = IPD Subtract Port QOS Count
+ * 
+ * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be
+ * be the 2's complement of the value that needs to be subtracted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_sub_port_qos_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_41_63          : 23;
+        uint64_t port_qos                : 9;       /**< The port to add the CNT field to. */
+        uint64_t cnt                     : 32;      /**< The value to be added to the register selected
+                                                         in the PORT_QOS field. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t port_qos                : 9;
+        uint64_t reserved_41_63          : 23;
+#endif
+    } s;
+    struct cvmx_ipd_sub_port_qos_cnt_s   cn52xx;
+    struct cvmx_ipd_sub_port_qos_cnt_s   cn52xxp1;
+    struct cvmx_ipd_sub_port_qos_cnt_s   cn56xx;
+    struct cvmx_ipd_sub_port_qos_cnt_s   cn56xxp1;
+} cvmx_ipd_sub_port_qos_cnt_t;
+
+
+/**
+ * cvmx_ipd_wqe_fpa_queue
+ *
+ * IPD_WQE_FPA_QUEUE = IPD Work-Queue-Entry FPA Page Size
+ * 
+ * Which FPA Queue (0-7) to fetch page-pointers from for WQE's
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_wqe_fpa_queue_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t wqe_pool                : 3;       /**< Which FPA Queue to fetch page-pointers
+                                                         from for WQE's. */
+#else
+        uint64_t wqe_pool                : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn30xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn31xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn38xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn38xxp2;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn50xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn52xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn52xxp1;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn56xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn56xxp1;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn58xx;
+    struct cvmx_ipd_wqe_fpa_queue_s      cn58xxp1;
+} cvmx_ipd_wqe_fpa_queue_t;
+
+
+/**
+ * cvmx_ipd_wqe_ptr_valid
+ *
+ * IPD_WQE_PTR_VALID = IPD's WQE Pointer Valid
+ * 
+ * The value of the WQE-pointer fetched and in the valid register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ipd_wqe_ptr_valid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t ptr                     : 29;      /**< Pointer value. */
+#else
+        uint64_t ptr                     : 29;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn30xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn31xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn38xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn50xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn52xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn52xxp1;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn56xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn56xxp1;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn58xx;
+    struct cvmx_ipd_wqe_ptr_valid_s      cn58xxp1;
+} cvmx_ipd_wqe_ptr_valid_t;
+
+
+/**
+ * cvmx_key_bist_reg
+ *
+ * KEY_BIST_REG = KEY's BIST Status Register
+ * 
+ * The KEY's BIST status for memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_key_bist_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t rrc                     : 1;       /**< RRC bist status. */
+        uint64_t mem1                    : 1;       /**< MEM - 1 bist status. */
+        uint64_t mem0                    : 1;       /**< MEM - 0 bist status. */
+#else
+        uint64_t mem0                    : 1;
+        uint64_t mem1                    : 1;
+        uint64_t rrc                     : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_key_bist_reg_s           cn38xx;
+    struct cvmx_key_bist_reg_s           cn38xxp2;
+    struct cvmx_key_bist_reg_s           cn56xx;
+    struct cvmx_key_bist_reg_s           cn56xxp1;
+    struct cvmx_key_bist_reg_s           cn58xx;
+    struct cvmx_key_bist_reg_s           cn58xxp1;
+} cvmx_key_bist_reg_t;
+
+
+/**
+ * cvmx_key_ctl_status
+ *
+ * KEY_CTL_STATUS = KEY's Control/Status Register
+ * 
+ * The KEY's interrupt enable register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_key_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t mem1_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 13:7 of this field, for FPF
+                                                         FIFO 1. */
+        uint64_t mem0_err                : 7;       /**< Causes a flip of the ECC bit associated 38:32
+                                                         respective to bit 6:0 of this field, for FPF
+                                                         FIFO 0. */
+#else
+        uint64_t mem0_err                : 7;
+        uint64_t mem1_err                : 7;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_key_ctl_status_s         cn38xx;
+    struct cvmx_key_ctl_status_s         cn38xxp2;
+    struct cvmx_key_ctl_status_s         cn56xx;
+    struct cvmx_key_ctl_status_s         cn56xxp1;
+    struct cvmx_key_ctl_status_s         cn58xx;
+    struct cvmx_key_ctl_status_s         cn58xxp1;
+} cvmx_key_ctl_status_t;
+
+
+/**
+ * cvmx_key_int_enb
+ *
+ * KEY_INT_ENB = KEY's Interrupt Enable
+ * 
+ * The KEY's interrupt enable register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_key_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ked1_dbe                : 1;       /**< When set (1) and bit 3 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+        uint64_t ked1_sbe                : 1;       /**< When set (1) and bit 2 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+        uint64_t ked0_dbe                : 1;       /**< When set (1) and bit 1 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+        uint64_t ked0_sbe                : 1;       /**< When set (1) and bit 0 of the KEY_INT_SUM
+                                                         register is asserted the KEY will assert an
+                                                         interrupt. */
+#else
+        uint64_t ked0_sbe                : 1;
+        uint64_t ked0_dbe                : 1;
+        uint64_t ked1_sbe                : 1;
+        uint64_t ked1_dbe                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_key_int_enb_s            cn38xx;
+    struct cvmx_key_int_enb_s            cn38xxp2;
+    struct cvmx_key_int_enb_s            cn56xx;
+    struct cvmx_key_int_enb_s            cn56xxp1;
+    struct cvmx_key_int_enb_s            cn58xx;
+    struct cvmx_key_int_enb_s            cn58xxp1;
+} cvmx_key_int_enb_t;
+
+
+/**
+ * cvmx_key_int_sum
+ *
+ * KEY_INT_SUM = KEY's Interrupt Summary Register
+ * 
+ * Contains the diffrent interrupt summary bits of the KEY.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_key_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ked1_dbe                : 1;
+        uint64_t ked1_sbe                : 1;
+        uint64_t ked0_dbe                : 1;
+        uint64_t ked0_sbe                : 1;
+#else
+        uint64_t ked0_sbe                : 1;
+        uint64_t ked0_dbe                : 1;
+        uint64_t ked1_sbe                : 1;
+        uint64_t ked1_dbe                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_key_int_sum_s            cn38xx;
+    struct cvmx_key_int_sum_s            cn38xxp2;
+    struct cvmx_key_int_sum_s            cn56xx;
+    struct cvmx_key_int_sum_s            cn56xxp1;
+    struct cvmx_key_int_sum_s            cn58xx;
+    struct cvmx_key_int_sum_s            cn58xxp1;
+} cvmx_key_int_sum_t;
+
+
+/**
+ * cvmx_l2c_bst0
+ *
+ * L2C_BST0 = L2C BIST 0 CTL/STAT
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_bst0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t dtbnk                   : 1;       /**< DuTag Bank#
+                                                         When DT=1(BAD), this field provides additional information
+                                                         about which DuTag Bank (0/1) failed.
+                                                         *** NOTE: O9N PASS1 Addition */
+        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t dtcnt                   : 13;      /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [12]:    i (0=FORWARD/1=REVERSE pass)
+                                                         [11:10]: j (Pattern# 1 of 4)
+                                                         [9:4]:   k (DT Index 1 of 64)
+                                                         [3:0]:   l (DT# 1 of 16 DTs) */
+        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t wlb_dat                 : 4;
+        uint64_t stin_msk                : 1;
+        uint64_t dt                      : 1;
+        uint64_t dtcnt                   : 13;
+        uint64_t wlb_msk                 : 4;
+        uint64_t dtbnk                   : 1;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_l2c_bst0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_15_18          : 4;
+        uint64_t dtcnt                   : 9;       /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [8]:   i (0=FORWARD/1=REVERSE pass)
+                                                         [7:6]: j (Pattern# 1 of 4)
+                                                         [5:0]: k (DT Index 1 of 64) */
+        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_4_4            : 1;
+        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t wlb_dat                 : 4;
+        uint64_t reserved_4_4            : 1;
+        uint64_t dt                      : 1;
+        uint64_t dtcnt                   : 9;
+        uint64_t reserved_15_18          : 4;
+        uint64_t wlb_msk                 : 4;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_bst0_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_16_18          : 3;
+        uint64_t dtcnt                   : 10;      /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [9]:   i (0=FORWARD/1=REVERSE pass)
+                                                         [8:7]: j (Pattern# 1 of 4)
+                                                         [6:1]: k (DT Index 1 of 64)
+                                                         [0]:   l (DT# 1 of 2 DTs) */
+        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t wlb_dat                 : 4;
+        uint64_t stin_msk                : 1;
+        uint64_t dt                      : 1;
+        uint64_t dtcnt                   : 10;
+        uint64_t reserved_16_18          : 3;
+        uint64_t wlb_msk                 : 4;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } cn31xx;
+    struct cvmx_l2c_bst0_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t dtcnt                   : 13;      /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [12]:    i (0=FORWARD/1=REVERSE pass)
+                                                         [11:10]: j (Pattern# 1 of 4)
+                                                         [9:4]:   k (DT Index 1 of 64)
+                                                         [3:0]:   l (DT# 1 of 16 DTs) */
+        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t wlb_dat                 : 4;
+        uint64_t stin_msk                : 1;
+        uint64_t dt                      : 1;
+        uint64_t dtcnt                   : 13;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn38xx;
+    struct cvmx_l2c_bst0_cn38xx          cn38xxp2;
+    struct cvmx_l2c_bst0_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t dtbnk                   : 1;       /**< DuTag Bank#
+                                                         When DT=1(BAD), this field provides additional information
+                                                         about which DuTag Bank (0/1) failed. */
+        uint64_t wlb_msk                 : 4;       /**< Bist Results for WLB-MSK RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_16_18          : 3;
+        uint64_t dtcnt                   : 10;      /**< DuTag BiST Counter (used to help isolate the failure)
+                                                         [9]:   i (0=FORWARD/1=REVERSE pass)
+                                                         [8:7]: j (Pattern# 1 of 4)
+                                                         [6:1]: k (DT Index 1 of 64)
+                                                         [0]:   l (DT# 1 of 2 DTs) */
+        uint64_t dt                      : 1;       /**< Bist Results for DuTAG RAM(s)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t stin_msk                : 1;       /**< Bist Results for STIN-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t wlb_dat                 : 4;       /**< Bist Results for WLB-DAT RAM [DP0-3]
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t wlb_dat                 : 4;
+        uint64_t stin_msk                : 1;
+        uint64_t dt                      : 1;
+        uint64_t dtcnt                   : 10;
+        uint64_t reserved_16_18          : 3;
+        uint64_t wlb_msk                 : 4;
+        uint64_t dtbnk                   : 1;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } cn50xx;
+    struct cvmx_l2c_bst0_cn50xx          cn52xx;
+    struct cvmx_l2c_bst0_cn50xx          cn52xxp1;
+    struct cvmx_l2c_bst0_s               cn56xx;
+    struct cvmx_l2c_bst0_s               cn56xxp1;
+    struct cvmx_l2c_bst0_s               cn58xx;
+    struct cvmx_l2c_bst0_s               cn58xxp1;
+} cvmx_l2c_bst0_t;
+
+
+/**
+ * cvmx_l2c_bst1
+ *
+ * L2C_BST1 = L2C BIST 1 CTL/STAT
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_bst1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t l2t                     : 9;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_l2c_bst1_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t vwdf                    : 4;       /**< Bist Results for VWDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t lrf                     : 2;       /**< Bist Results for LRF RAMs (PLC+ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vab_vwcf                : 1;       /**< Bist Results for VAB VWCF_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_5_8            : 4;
+        uint64_t l2t                     : 5;       /**< Bist Results for L2T (USE+4SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t l2t                     : 5;
+        uint64_t reserved_5_8            : 4;
+        uint64_t vab_vwcf                : 1;
+        uint64_t lrf                     : 2;
+        uint64_t vwdf                    : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_bst1_cn30xx          cn31xx;
+    struct cvmx_l2c_bst1_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t vwdf                    : 4;       /**< Bist Results for VWDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t lrf                     : 2;       /**< Bist Results for LRF RAMs (PLC+ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vab_vwcf                : 1;       /**< Bist Results for VAB VWCF_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t l2t                     : 9;
+        uint64_t vab_vwcf                : 1;
+        uint64_t lrf                     : 2;
+        uint64_t vwdf                    : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_l2c_bst1_cn38xx          cn38xxp2;
+    struct cvmx_l2c_bst1_cn38xx          cn50xx;
+    struct cvmx_l2c_bst1_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t plc2                    : 1;       /**< Bist Results for PLC2 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t plc1                    : 1;       /**< Bist Results for PLC1 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t plc0                    : 1;       /**< Bist Results for PLC0 RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vwdf                    : 4;       /**< Bist Results for VWDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_11_11          : 1;
+        uint64_t ilc                     : 1;       /**< Bist Results for ILC RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vab_vwcf                : 1;       /**< Bist Results for VAB VWCF_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t l2t                     : 9;
+        uint64_t vab_vwcf                : 1;
+        uint64_t ilc                     : 1;
+        uint64_t reserved_11_11          : 1;
+        uint64_t vwdf                    : 4;
+        uint64_t plc0                    : 1;
+        uint64_t plc1                    : 1;
+        uint64_t plc2                    : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } cn52xx;
+    struct cvmx_l2c_bst1_cn52xx          cn52xxp1;
+    struct cvmx_l2c_bst1_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t plc2                    : 1;       /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t plc1                    : 1;       /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t plc0                    : 1;       /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ilc                     : 1;       /**< Bist Results for LRF RAMs (ILC)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vwdf1                   : 4;       /**< Bist Results for VWDF1 RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vwdf0                   : 4;       /**< Bist Results for VWDF0 RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t vab_vwcf1               : 1;       /**< Bist Results for VAB VWCF1_MEM */
+        uint64_t reserved_10_10          : 1;
+        uint64_t vab_vwcf0               : 1;       /**< Bist Results for VAB VWCF0_MEM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t l2t                     : 9;       /**< Bist Results for L2T (USE+8SET RAMs)
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t l2t                     : 9;
+        uint64_t vab_vwcf0               : 1;
+        uint64_t reserved_10_10          : 1;
+        uint64_t vab_vwcf1               : 1;
+        uint64_t vwdf0                   : 4;
+        uint64_t vwdf1                   : 4;
+        uint64_t ilc                     : 1;
+        uint64_t plc0                    : 1;
+        uint64_t plc1                    : 1;
+        uint64_t plc2                    : 1;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } cn56xx;
+    struct cvmx_l2c_bst1_cn56xx          cn56xxp1;
+    struct cvmx_l2c_bst1_cn38xx          cn58xx;
+    struct cvmx_l2c_bst1_cn38xx          cn58xxp1;
+} cvmx_l2c_bst1_t;
+
+
+/**
+ * cvmx_l2c_bst2
+ *
+ * L2C_BST2 = L2C BIST 2 CTL/STAT
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_bst2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_4_11           : 8;
+        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
+                                                         - 1: BAD */
+        uint64_t picbst                  : 1;       /**< Bist Results for RFB PIC RAM
+                                                         - 1: BAD */
+        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t xrddat                  : 1;
+        uint64_t xrdmsk                  : 1;
+        uint64_t picbst                  : 1;
+        uint64_t ipcbst                  : 1;
+        uint64_t reserved_4_11           : 8;
+        uint64_t mrb                     : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_l2c_bst2_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t rmdf                    : 4;       /**< Bist Results for RMDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_4_7            : 4;
+        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t reserved_2_2            : 1;
+        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t xrddat                  : 1;
+        uint64_t xrdmsk                  : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t ipcbst                  : 1;
+        uint64_t reserved_4_7            : 4;
+        uint64_t rmdf                    : 4;
+        uint64_t mrb                     : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_bst2_cn30xx          cn31xx;
+    struct cvmx_l2c_bst2_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t rmdf                    : 4;       /**< Bist Results for RMDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t rhdf                    : 4;       /**< Bist Results for RHDF RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
+                                                         - 1: BAD */
+        uint64_t picbst                  : 1;       /**< Bist Results for RFB PIC RAM
+                                                         - 1: BAD */
+        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t xrddat                  : 1;
+        uint64_t xrdmsk                  : 1;
+        uint64_t picbst                  : 1;
+        uint64_t ipcbst                  : 1;
+        uint64_t rhdf                    : 4;
+        uint64_t rmdf                    : 4;
+        uint64_t mrb                     : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_l2c_bst2_cn38xx          cn38xxp2;
+    struct cvmx_l2c_bst2_cn30xx          cn50xx;
+    struct cvmx_l2c_bst2_cn30xx          cn52xx;
+    struct cvmx_l2c_bst2_cn30xx          cn52xxp1;
+    struct cvmx_l2c_bst2_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mrb                     : 4;       /**< Bist Results for MRB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t rmdb                    : 4;       /**< Bist Results for RMDB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t rhdb                    : 4;       /**< Bist Results for RHDB RAMs
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ipcbst                  : 1;       /**< Bist Results for RFB IPC RAM
+                                                         - 1: BAD */
+        uint64_t picbst                  : 1;       /**< Bist Results for RFB PIC RAM
+                                                         - 1: BAD */
+        uint64_t xrdmsk                  : 1;       /**< Bist Results for RFB XRD-MSK RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t xrddat                  : 1;       /**< Bist Results for RFB XRD-DAT RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t xrddat                  : 1;
+        uint64_t xrdmsk                  : 1;
+        uint64_t picbst                  : 1;
+        uint64_t ipcbst                  : 1;
+        uint64_t rhdb                    : 4;
+        uint64_t rmdb                    : 4;
+        uint64_t mrb                     : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn56xx;
+    struct cvmx_l2c_bst2_cn56xx          cn56xxp1;
+    struct cvmx_l2c_bst2_cn56xx          cn58xx;
+    struct cvmx_l2c_bst2_cn56xx          cn58xxp1;
+} cvmx_l2c_bst2_t;
+
+
+/**
+ * cvmx_l2c_cfg
+ *
+ * Specify the RSL base addresses for the block
+ * 
+ *                  L2C_CFG = L2C Configuration
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t bstrun                  : 1;       /**< L2 Data Store Bist Running
+                                                         Indicates when the L2C HW Bist sequence(short or long) is
+                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state]
+                                                         *** NOTE: O9N PASS2 Addition */
+        uint64_t lbist                   : 1;       /**< L2C Data Store Long Bist Sequence
+                                                         When the previous state was '0' and SW writes a '1',
+                                                         the long bist sequence (enhanced 13N March) is performed.
+                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
+                                                         that the long bist sequence is running. When BSTRUN-=0,
+                                                         the state of the L2D_BST[0-3] registers contain information
+                                                         which reflects the status of the recent long bist sequence.
+                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
+                                                         (ie: when BSTRUN=1 never write LBIST=0).
+                                                         NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS
+                                                         Fuse is blown.
+                                                         *** NOTE: O9N PASS2 Addition */
+        uint64_t xor_bank                : 1;       /**< L2C XOR Bank Bit
+                                                         When both LMC's are enabled(DPRES1=1/DPRES0=1), this
+                                                         bit determines how addresses are assigned to
+                                                         LMC port(s).
+                                                            XOR_BANK|  LMC#
+                                                          ----------+---------------------------------
+                                                              0     |   byte address[7]
+                                                              1     |   byte address[7] XOR byte address[12]
+                                                         Example: If both LMC ports are enabled (DPRES1=1/DPRES0=1)
+                                                         and XOR_BANK=1, then addr[7] XOR addr[12] is used to determine
+                                                         which LMC Port# a reference is directed to.
+                                                         *** NOTE: O56 PASS1 Addition */
+        uint64_t dpres1                  : 1;       /**< DDR1 Present/LMC1 Enable
+                                                         When DPRES1 is set, LMC#1 is enabled(DDR1 pins at
+                                                         the BOTTOM of the chip are active).
+                                                         NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1),
+                                                         see XOR_BANK bit to determine how a reference is
+                                                         assigned to a DDR/LMC port. (Also, in dual-LMC configuration,
+                                                         the address sent to the targeted LMC port is the
+                                                         address shifted right by one).
+                                                         NOTE: For power-savings, the DPRES1 is also used to
+                                                         disable DDR1/LMC1 clocks.
+                                                         SW Constraint: When dual LMC is enabled
+                                                         (L2C_CFG[DPRES0/1]=1), the LMCx_DDR2_CTL[DDR_EOF]
+                                                         must be increased by +1 to account for an additional
+                                                         cycle of uncertainty.
+                                                         *** NOTE: O56 PASS1 Addition */
+        uint64_t dpres0                  : 1;       /**< DDR0 Present/LMC0 Enable
+                                                         When DPRES0 is set, LMC#0 is enabled(DDR0 pins at
+                                                         the BOTTOM of the chip are active).
+                                                         NOTE: When both LMC ports are enabled(DPRES1=1/DPRES0=1),
+                                                         see XOR_BANK bit to determine how a reference is
+                                                         assigned to a DDR/LMC port. (Also, in dual-LMC configuration,
+                                                         the address sent to the targeted LMC port is the
+                                                         address shifted right by one).
+                                                         NOTE: For power-savings, the DPRES0 is also used to
+                                                         disable DDR0/LMC0 clocks.
+                                                         SW Constraint: When dual LMC is enabled
+                                                         (L2C_CFG[DPRES0/1]=1), the LMCx_DDR2_CTL[DDR_EOF]
+                                                         must be increased by +1 to account for an additional
+                                                         cycle of uncertainty.
+                                                         *** NOTE: O56 PASS1 Addition */
+        uint64_t dfill_dis               : 1;       /**< L2C Dual Fill Disable
+                                                         When set, the L2C dual-fill performance feature is
+                                                         disabled.
+                                                         NOTE: This bit is only intended to evaluate the
+                                                         effectiveness of the dual-fill feature. For OPTIMAL
+                                                         performance, this bit should ALWAYS be zero.
+                                                         *** NOTE: O9N PASS1 Addition */
+        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 11-bit
+                                                         index with the low order 11-bits of the tag.
+                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+        uint64_t lrf_arb_mode            : 1;
+        uint64_t rfb_arb_mode            : 1;
+        uint64_t rsp_arb_mode            : 1;
+        uint64_t mwf_crd                 : 4;
+        uint64_t idxalias                : 1;
+        uint64_t fpen                    : 1;
+        uint64_t fpempty                 : 1;
+        uint64_t fpexp                   : 4;
+        uint64_t dfill_dis               : 1;
+        uint64_t dpres0                  : 1;
+        uint64_t dpres1                  : 1;
+        uint64_t xor_bank                : 1;
+        uint64_t lbist                   : 1;
+        uint64_t bstrun                  : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_l2c_cfg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 8-bit
+                                                         index with the low order 8-bits of the tag.
+                                                            index[14:7] =  (tag[22:15] ^ index[14:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+        uint64_t lrf_arb_mode            : 1;
+        uint64_t rfb_arb_mode            : 1;
+        uint64_t rsp_arb_mode            : 1;
+        uint64_t mwf_crd                 : 4;
+        uint64_t idxalias                : 1;
+        uint64_t fpen                    : 1;
+        uint64_t fpempty                 : 1;
+        uint64_t fpexp                   : 4;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_cfg_cn30xx           cn31xx;
+    struct cvmx_l2c_cfg_cn30xx           cn38xx;
+    struct cvmx_l2c_cfg_cn30xx           cn38xxp2;
+    struct cvmx_l2c_cfg_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t bstrun                  : 1;       /**< L2 Data Store Bist Running
+                                                         Indicates when the L2C HW Bist sequence(short or long) is
+                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state]
+                                                         *** NOTE: O56 PASS1 Addition */
+        uint64_t lbist                   : 1;       /**< L2C Data Store Long Bist Sequence
+                                                         When the previous state was '0' and SW writes a '1',
+                                                         the long bist sequence (enhanced 13N March) is performed.
+                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
+                                                         that the long bist sequence is running. When BSTRUN-=0,
+                                                         the state of the L2D_BST[0-3] registers contain information
+                                                         which reflects the status of the recent long bist sequence.
+                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
+                                                         (ie: when BSTRUN=1 never write LBIST=0). */
+        uint64_t reserved_14_17          : 4;
+        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 7-bit
+                                                         index with the low order 7-bits of the tag.
+                                                            index[13:7] =  (tag[20:14] ^ index[13:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+        uint64_t lrf_arb_mode            : 1;
+        uint64_t rfb_arb_mode            : 1;
+        uint64_t rsp_arb_mode            : 1;
+        uint64_t mwf_crd                 : 4;
+        uint64_t idxalias                : 1;
+        uint64_t fpen                    : 1;
+        uint64_t fpempty                 : 1;
+        uint64_t fpexp                   : 4;
+        uint64_t reserved_14_17          : 4;
+        uint64_t lbist                   : 1;
+        uint64_t bstrun                  : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn50xx;
+    struct cvmx_l2c_cfg_cn50xx           cn52xx;
+    struct cvmx_l2c_cfg_cn50xx           cn52xxp1;
+    struct cvmx_l2c_cfg_s                cn56xx;
+    struct cvmx_l2c_cfg_s                cn56xxp1;
+    struct cvmx_l2c_cfg_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t bstrun                  : 1;       /**< L2 Data Store Bist Running
+                                                         Indicates when the L2C HW Bist sequence(short or long) is
+                                                         running. [L2C ECC Bist FSM is not in the RESET/DONE state]
+                                                         *** NOTE: O9N PASS2 Addition */
+        uint64_t lbist                   : 1;       /**< L2C Data Store Long Bist Sequence
+                                                         When the previous state was '0' and SW writes a '1',
+                                                         the long bist sequence (enhanced 13N March) is performed.
+                                                         SW can then read the L2C_CFG[BSTRUN] which will indicate
+                                                         that the long bist sequence is running. When BSTRUN-=0,
+                                                         the state of the L2D_BST[0-3] registers contain information
+                                                         which reflects the status of the recent long bist sequence.
+                                                         NOTE: SW must never write LBIST=0 while Long Bist is running
+                                                         (ie: when BSTRUN=1 never write LBIST=0).
+                                                         NOTE: LBIST is disabled if the MIO_FUS_DAT2.BIST_DIS
+                                                         Fuse is blown.
+                                                         *** NOTE: O9N PASS2 Addition */
+        uint64_t reserved_15_17          : 3;
+        uint64_t dfill_dis               : 1;       /**< L2C Dual Fill Disable
+                                                         When set, the L2C dual-fill performance feature is
+                                                         disabled.
+                                                         NOTE: This bit is only intended to evaluate the
+                                                         effectiveness of the dual-fill feature. For OPTIMAL
+                                                         performance, this bit should ALWAYS be zero.
+                                                         *** NOTE: O9N PASS1 Addition */
+        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 11-bit
+                                                         index with the low order 11-bits of the tag.
+                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+        uint64_t lrf_arb_mode            : 1;
+        uint64_t rfb_arb_mode            : 1;
+        uint64_t rsp_arb_mode            : 1;
+        uint64_t mwf_crd                 : 4;
+        uint64_t idxalias                : 1;
+        uint64_t fpen                    : 1;
+        uint64_t fpempty                 : 1;
+        uint64_t fpexp                   : 4;
+        uint64_t dfill_dis               : 1;
+        uint64_t reserved_15_17          : 3;
+        uint64_t lbist                   : 1;
+        uint64_t bstrun                  : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn58xx;
+    struct cvmx_l2c_cfg_cn58xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t dfill_dis               : 1;       /**< L2C Dual Fill Disable
+                                                         When set, the L2C dual-fill performance feature is
+                                                         disabled.
+                                                         NOTE: This bit is only intended to evaluate the
+                                                         effectiveness of the dual-fill feature. For OPTIMAL
+                                                         performance, this bit should ALWAYS be zero.
+                                                         *** NOTE: O9N PASS1 Addition */
+        uint64_t fpexp                   : 4;       /**< [CYA] Forward Progress Counter Exponent
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When FPEN is enabled and the LFB is empty, the
+                                                         forward progress counter (FPCNT) is initialized to:
+                                                            FPCNT[24:0] = 2^(9+FPEXP)
+                                                         When the LFB is non-empty the FPCNT is decremented
+                                                         (every eclk interval). If the FPCNT reaches zero,
+                                                         the LFB no longer accepts new requests until either
+                                                            a) all of the current LFB entries have completed
+                                                               (to ensure forward progress).
+                                                            b) FPEMPTY=0 and another forward progress count
+                                                               interval timeout expires.
+                                                         EXAMPLE USE: If FPEXP=2, the FPCNT = 2048 eclks.
+                                                         (For eclk=500MHz(2ns), this would be ~4us). */
+        uint64_t fpempty                 : 1;       /**< [CYA] Forward Progress Counter Empty
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL all current LFB
+                                                         entries have completed.
+                                                         When clear, if the forward progress counter expires,
+                                                         all new LFB-NQs are stopped UNTIL either
+                                                           a) all current LFB entries have completed.
+                                                           b) another forward progress interval expires
+                                                         NOTE: We may want to FREEZE/HANG the system when
+                                                         we encounter an LFB entry cannot complete, and there
+                                                         may be times when we want to allow further LFB-NQs
+                                                         to be permitted to help in further analyzing the
+                                                         source */
+        uint64_t fpen                    : 1;       /**< [CYA] Forward Progress Counter Enable
+                                                         NOTE: Should NOT be exposed to customer! [FOR DEBUG ONLY]
+                                                         When set, enables the Forward Progress Counter to
+                                                         prevent new LFB entries from enqueueing until ALL
+                                                         current LFB entries have completed. */
+        uint64_t idxalias                : 1;       /**< L2C Index Alias Enable
+                                                         When set, the L2 Tag/Data Store will alias the 11-bit
+                                                         index with the low order 11-bits of the tag.
+                                                            index[17:7] =  (tag[28:18] ^ index[17:7])
+                                                         NOTE: This bit must only be modified at boot time,
+                                                         when it can be guaranteed that no blocks have been
+                                                         loaded into the L2 Cache.
+                                                         The index aliasing is a performance enhancement feature
+                                                         which reduces the L2 cache thrashing experienced for
+                                                         regular stride references.
+                                                         NOTE: The index alias is stored in the LFB and VAB, and
+                                                         its effects are reversed for memory references (Victims,
+                                                         STT-Misses and Read-Misses) */
+        uint64_t mwf_crd                 : 4;       /**< MWF Credit Threshold: When the remaining MWF credits
+                                                         become less than or equal to the MWF_CRD, the L2C will
+                                                         assert l2c__lmi_mwd_hiwater_a to signal the LMC to give
+                                                         writes (victims) higher priority. */
+        uint64_t rsp_arb_mode            : 1;       /**< RSP Arbitration Mode:
+                                                         - 0: Fixed Priority [HP=RFB, RMCF, RHCF, STRSP, LP=STRSC]
+                                                         - 1: Round Robin: [RFB(reflected I/O), RMCF(RdMiss),
+                                                             RHCF(RdHit), STRSP(ST RSP w/ invalidate),
+                                                             STRSC(ST RSP no invalidate)] */
+        uint64_t rfb_arb_mode            : 1;       /**< RFB Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB->PP requests are higher priority than
+                                                             PP->IOB requests
+                                                         - 1: Round Robin -
+                                                             I/O requests from PP and IOB are serviced in
+                                                             round robin */
+        uint64_t lrf_arb_mode            : 1;       /**< RF Arbitration Mode:
+                                                         - 0: Fixed Priority -
+                                                             IOB memory requests are higher priority than PP
+                                                             memory requests.
+                                                         - 1: Round Robin -
+                                                             Memory requests from PP and IOB are serviced in
+                                                             round robin. */
+#else
+        uint64_t lrf_arb_mode            : 1;
+        uint64_t rfb_arb_mode            : 1;
+        uint64_t rsp_arb_mode            : 1;
+        uint64_t mwf_crd                 : 4;
+        uint64_t idxalias                : 1;
+        uint64_t fpen                    : 1;
+        uint64_t fpempty                 : 1;
+        uint64_t fpexp                   : 4;
+        uint64_t dfill_dis               : 1;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } cn58xxp1;
+} cvmx_l2c_cfg_t;
+
+
+/**
+ * cvmx_l2c_dbg
+ *
+ * L2C_DBG = L2C DEBUG Register
+ * 
+ * Description: L2C Tag/Data Store Debug Register
+ *
+ * Notes:
+ * (1) When using the L2T, L2D or FINV Debug probe feature, the LDD command WILL NOT update the DuTags.
+ * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one set)
+ * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back
+ *     dirty data to memory to maintain coherency.
+ * (4) L2 Cache Lock Down feature MUST BE disabled (L2C_LCKBASE[LCK_ENA]=0) if ANY of the L2C debug
+ *     features (L2T, L2D, FINV) are enabled.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_dbg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t lfb_enum                : 4;       /**< Specifies the LFB Entry# which is to be captured. */
+        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM[3:0] are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+        uint64_t ppnum                   : 4;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which one-of-16
+                                                         PPs is selected as the diagnostic PP. */
+        uint64_t set                     : 3;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+        uint64_t finv                    : 1;       /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[17:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[17:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[17:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:18]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[17:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: N3K-Pass2 modification. (This bit's functionality
+                                                         has changed since Pass1-in the following way).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
+#else
+        uint64_t l2t                     : 1;
+        uint64_t l2d                     : 1;
+        uint64_t finv                    : 1;
+        uint64_t set                     : 3;
+        uint64_t ppnum                   : 4;
+        uint64_t lfb_dmp                 : 1;
+        uint64_t lfb_enum                : 4;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_l2c_dbg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t lfb_enum                : 2;       /**< Specifies the LFB Entry# which is to be captured. */
+        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+        uint64_t reserved_7_9            : 3;
+        uint64_t ppnum                   : 1;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which
+                                                         PP is selected as the diagnostic PP.
+                                                         NOTE: For O1P single core PPNUM=0 (MBZ) */
+        uint64_t reserved_5_5            : 1;
+        uint64_t set                     : 2;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+        uint64_t finv                    : 1;       /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the PP will invalidate
+                                                         the specified set(L2C_DBG[SET]) at the index specified
+                                                         in the STF address[14:7]. If a dirty block is detected(D=1),
+                                                         it is written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[14:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The PP can generate STF(L1 store-miss)
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss)
+                                                         command is issued from the PP.
+                                                         The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[14:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:15]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from the PP.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[14:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD(L1 load-miss) is detected. */
+#else
+        uint64_t l2t                     : 1;
+        uint64_t l2d                     : 1;
+        uint64_t finv                    : 1;
+        uint64_t set                     : 2;
+        uint64_t reserved_5_5            : 1;
+        uint64_t ppnum                   : 1;
+        uint64_t reserved_7_9            : 3;
+        uint64_t lfb_dmp                 : 1;
+        uint64_t lfb_enum                : 2;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_dbg_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t lfb_enum                : 3;       /**< Specifies the LFB Entry# which is to be captured. */
+        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+        uint64_t reserved_7_9            : 3;
+        uint64_t ppnum                   : 1;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which
+                                                         PP is selected as the diagnostic PP. */
+        uint64_t reserved_5_5            : 1;
+        uint64_t set                     : 2;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+        uint64_t finv                    : 1;       /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[15:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[15:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF(L1 store-miss)
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss)
+                                                         command is issued from a PP determined by the
+                                                         L2C_DBG[PPNUM] field. The selected set# is determined
+                                                         by the L2C_DBG[SET] field, and the index is determined
+                                                         from the address[15:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[15:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD(L1 load-miss) is detected from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]). */
+#else
+        uint64_t l2t                     : 1;
+        uint64_t l2d                     : 1;
+        uint64_t finv                    : 1;
+        uint64_t set                     : 2;
+        uint64_t reserved_5_5            : 1;
+        uint64_t ppnum                   : 1;
+        uint64_t reserved_7_9            : 3;
+        uint64_t lfb_dmp                 : 1;
+        uint64_t lfb_enum                : 3;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn31xx;
+    struct cvmx_l2c_dbg_s                cn38xx;
+    struct cvmx_l2c_dbg_s                cn38xxp2;
+    struct cvmx_l2c_dbg_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t lfb_enum                : 3;       /**< Specifies the LFB Entry# which is to be captured. */
+        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM[2:0] are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+        uint64_t reserved_7_9            : 3;
+        uint64_t ppnum                   : 1;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which 1-of-2
+                                                         PPs is selected as the diagnostic PP. */
+        uint64_t set                     : 3;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+        uint64_t finv                    : 1;       /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[13:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[13:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[13:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:14]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[13:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
+#else
+        uint64_t l2t                     : 1;
+        uint64_t l2d                     : 1;
+        uint64_t finv                    : 1;
+        uint64_t set                     : 3;
+        uint64_t ppnum                   : 1;
+        uint64_t reserved_7_9            : 3;
+        uint64_t lfb_dmp                 : 1;
+        uint64_t lfb_enum                : 3;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn50xx;
+    struct cvmx_l2c_dbg_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t lfb_enum                : 3;       /**< Specifies the LFB Entry# which is to be captured. */
+        uint64_t lfb_dmp                 : 1;       /**< LFB Dump Enable: When written(=1), the contents of
+                                                         the LFB specified by LFB_ENUM[2:0] are captured
+                                                         into the L2C_LFB(0/1/2) registers.
+                                                         NOTE: Some fields of the LFB entry are unpredictable
+                                                         and dependent on usage. This is only intended to be
+                                                         used for HW debug. */
+        uint64_t reserved_8_9            : 2;
+        uint64_t ppnum                   : 2;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines which 1-of-4
+                                                         PPs is selected as the diagnostic PP. */
+        uint64_t set                     : 3;       /**< When L2C_DBG[L2T] or L2C_DBG[L2D] or L2C_DBG[FINV]
+                                                         is enabled, this field determines 1-of-n targeted
+                                                         sets to act upon.
+                                                         NOTE: L2C_DBG[SET] must never equal a crippled or
+                                                         unusable set (see UMSK* registers and Cripple mode
+                                                         fuses). */
+        uint64_t finv                    : 1;       /**< Flush-Invalidate.
+                                                         When flush-invalidate is enable (FINV=1), all STF
+                                                         (L1 store-miss) commands generated from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will invalidate the specified set
+                                                         (L2C_DBG[SET]) at the index specified in the STF
+                                                         address[15:7]. If a dirty block is detected (D=1), it is
+                                                         written back to memory. The contents of the invalid
+                                                         L2 Cache line is also 'scrubbed' with the STF write data.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the index specified in
+                                                         STF address[15:7] refers to the 'aliased' address.
+                                                         NOTE: An STF command with write data=ZEROES can be
+                                                         generated by SW using the Prefetch instruction with
+                                                         Hint=30d "prepare for Store", followed by a SYNCW.
+                                                         What is seen at the L2C as an STF w/wrdcnt=0 with all
+                                                         of its mask bits clear (indicates zero-fill data).
+                                                         A flush-invalidate will 'force-hit' the L2 cache at
+                                                         [index,set] and invalidate the entry (V=0/D=0/L=0/U=0).
+                                                         If the cache block is dirty, it is also written back
+                                                         to memory. The DuTag state is probed/updated as normal
+                                                         for an STF request.
+                                                         TYPICAL APPLICATIONS:
+                                                            1) L2 Tag/Data ECC SW Recovery
+                                                            2) Cache Unlocking
+                                                         NOTE: If the cacheline had been previously LOCKED(L=1),
+                                                         a flush-invalidate operation will explicitly UNLOCK
+                                                         (L=0) the set/index specified.
+                                                         NOTE: The diagnostic PP cores can generate STF
+                                                         commands to the L2 Cache whenever all 128 bytes in a
+                                                         block are written. SW must take this into consideration
+                                                         to avoid 'errant' Flush-Invalidates. */
+        uint64_t l2d                     : 1;       /**< When enabled (and L2C_DBG[L2T]=0), fill data is
+                                                         returned directly from the L2 Data Store
+                                                         (regardless of hit/miss) when an LDD(L1 load-miss) command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[15:7] associated with the LDD
+                                                         command.
+                                                         This 'force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state. */
+        uint64_t l2t                     : 1;       /**< When enabled, L2 Tag information [V,D,L,U,phys_addr[33:16]]
+                                                         is returned on the data bus starting at +32(and +96) bytes
+                                                         offset from the beginning of cacheline when an LDD
+                                                         (L1 load-miss) command is issued from a PP determined by
+                                                         the L2C_DBG[PPNUM] field.
+                                                         The selected L2 set# is determined by the L2C_DBG[SET]
+                                                         field, and the L2 index is determined from the
+                                                         phys_addr[15:7] associated with the LDD command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: The diagnostic PP should issue a d-stream load
+                                                         to an aligned cacheline+0x20(+0x60) in order to have the
+                                                         return VDLUTAG information (in OW2/OW6) written directly
+                                                         into the proper PP register. The diagnostic PP should also
+                                                         flush it's local L1 cache after use(to ensure data
+                                                         coherency).
+                                                         NOTE: The position of the VDLUTAG data in the destination
+                                                         register is dependent on the endian mode(big/little).
+                                                         NOTE: (For L2C BitMap testing of L2 Data Store OW ECC):
+                                                         If L2D_ERR[ECC_ENA]=0, the OW ECC from the selected
+                                                         half cacheline (see: L2D_ERR[BMHCLSEL] is also
+                                                         conditionally latched into the L2D_FSYN0/1 CSRs if an
+                                                         LDD command is detected from the diagnostic PP(L2C_DBG[PPNUM]). */
+#else
+        uint64_t l2t                     : 1;
+        uint64_t l2d                     : 1;
+        uint64_t finv                    : 1;
+        uint64_t set                     : 3;
+        uint64_t ppnum                   : 2;
+        uint64_t reserved_8_9            : 2;
+        uint64_t lfb_dmp                 : 1;
+        uint64_t lfb_enum                : 3;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn52xx;
+    struct cvmx_l2c_dbg_cn52xx           cn52xxp1;
+    struct cvmx_l2c_dbg_s                cn56xx;
+    struct cvmx_l2c_dbg_s                cn56xxp1;
+    struct cvmx_l2c_dbg_s                cn58xx;
+    struct cvmx_l2c_dbg_s                cn58xxp1;
+} cvmx_l2c_dbg_t;
+
+
+/**
+ * cvmx_l2c_dut
+ *
+ * L2C_DUT = L2C DUTAG Register
+ * 
+ * Description: L2C Duplicate Tag State Register
+ *
+ * Notes:
+ * (1) When using the L2T, L2D or FINV Debug probe feature, an LDD command issued by the diagnostic PP
+ *     WILL NOT update the DuTags.
+ * (2) L2T, L2D, FINV MUST BE mutually exclusive (only one enabled at a time).
+ * (3) Force Invalidate is intended as a means for SW to invalidate the L2 Cache while also writing back
+ *     dirty data to memory to maintain coherency. (A side effect of FINV is that an LDD L2 fill is
+ *     launched which fills data into the L2 DS).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_dut_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t dtena                   : 1;       /**< DuTag Diagnostic read enable.
+                                                         When L2C_DUT[DTENA]=1, all LDD(L1 load-miss)
+                                                         commands issued from the diagnostic PP
+                                                         (L2C_DBG[PPNUM]) will capture the DuTag state (V|L1TAG)
+                                                         of the PP#(specified in the LDD address[29:26] into
+                                                         the L2C_DUT CSR register. This allows the diagPP to
+                                                         read ALL DuTags (from any PP).
+                                                         The DuTag Set# to capture is extracted from the LDD
+                                                         address[25:20]. The diagnostic PP would issue the
+                                                         LDD then read the L2C_DUT register (one at a time).
+                                                         This LDD 'L2 force-hit' will NOT alter the current L2
+                                                         Tag State OR the DuTag state.
+                                                         NOTE: For O9N the DuTag SIZE has doubled (to 16KB)
+                                                         where each DuTag is organized as 2x 64-way entries.
+                                                         The LDD address[7] determines which 1(of-2) internal
+                                                         64-ways to select.
+                                                         The fill data is returned directly from the L2 Data
+                                                         Store(regardless of hit/miss) when an LDD command
+                                                         is issued from a PP determined by the L2C_DBG[PPNUM]
+                                                         field. The selected L2 Set# is determined by the
+                                                         L2C_DBG[SET] field, and the index is determined
+                                                         from the address[17:7] associated with the LDD
+                                                         command.
+                                                         This 'L2 force-hit' will NOT alter the current L2 Tag
+                                                         state OR the DuTag state.
+                                                         NOTE: In order for the DiagPP to generate an LDD command
+                                                         to the L2C, it must first force an L1 Dcache flush. */
+        uint64_t reserved_30_30          : 1;
+        uint64_t dt_vld                  : 1;       /**< Duplicate L1 Tag Valid bit latched in for previous
+                                                         LDD(L1 load-miss) command sourced by diagnostic PP. */
+        uint64_t dt_tag                  : 29;      /**< Duplicate L1 Tag[35:7] latched in for previous
+                                                         LDD(L1 load-miss) command sourced by diagnostic PP. */
+#else
+        uint64_t dt_tag                  : 29;
+        uint64_t dt_vld                  : 1;
+        uint64_t reserved_30_30          : 1;
+        uint64_t dtena                   : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_l2c_dut_s                cn30xx;
+    struct cvmx_l2c_dut_s                cn31xx;
+    struct cvmx_l2c_dut_s                cn38xx;
+    struct cvmx_l2c_dut_s                cn38xxp2;
+    struct cvmx_l2c_dut_s                cn50xx;
+    struct cvmx_l2c_dut_s                cn52xx;
+    struct cvmx_l2c_dut_s                cn52xxp1;
+    struct cvmx_l2c_dut_s                cn56xx;
+    struct cvmx_l2c_dut_s                cn56xxp1;
+    struct cvmx_l2c_dut_s                cn58xx;
+    struct cvmx_l2c_dut_s                cn58xxp1;
+} cvmx_l2c_dut_t;
+
+
+/**
+ * cvmx_l2c_grpwrr0
+ *
+ * L2C_GRPWRR0 = L2C PP Weighted Round \#0 Register
+ * 
+ * Description: Defines Weighted rounds(32) for Group PLC0,PLC1
+ *
+ * Notes:
+ * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
+ * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_grpwrr0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t plc1rmsk                : 32;      /**< PLC1 Group#1 Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for Group \#1's participation. When a 'round' bit is
+                                                         set, Group#1 is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, Group#1 WILL
+                                                         participate in the arbitration for this round. */
+        uint64_t plc0rmsk                : 32;      /**< PLC Group#0 Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for Group \#0's participation. When a 'round' bit is
+                                                         set, Group#0 is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, Group#0 WILL
+                                                         participate in the arbitration for this round. */
+#else
+        uint64_t plc0rmsk                : 32;
+        uint64_t plc1rmsk                : 32;
+#endif
+    } s;
+    struct cvmx_l2c_grpwrr0_s            cn52xx;
+    struct cvmx_l2c_grpwrr0_s            cn52xxp1;
+    struct cvmx_l2c_grpwrr0_s            cn56xx;
+    struct cvmx_l2c_grpwrr0_s            cn56xxp1;
+} cvmx_l2c_grpwrr0_t;
+
+
+/**
+ * cvmx_l2c_grpwrr1
+ *
+ * L2C_GRPWRR1 = L2C PP Weighted Round \#1 Register
+ * 
+ * Description: Defines Weighted Rounds(32) for Group PLC2,ILC
+ *
+ * Notes:
+ * - Starvation of a group 'could' occur, unless SW takes the precaution to ensure that each GROUP
+ * participates in at least 1(of 32) rounds (ie: At least 1 bit(of 32) should be clear).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_grpwrr1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t ilcrmsk                 : 32;      /**< ILC (IOB) Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for IOB participation. When a 'round' bit is
+                                                         set, IOB is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, IOB WILL
+                                                         participate in the arbitration for this round. */
+        uint64_t plc2rmsk                : 32;      /**< PLC Group#2 Weighted Round Mask
+                                                         Each bit represents 1 of 32 rounds
+                                                         for Group \#2's participation. When a 'round' bit is
+                                                         set, Group#2 is 'masked' and DOES NOT participate.
+                                                         When a 'round' bit is clear, Group#2 WILL
+                                                         participate in the arbitration for this round. */
+#else
+        uint64_t plc2rmsk                : 32;
+        uint64_t ilcrmsk                 : 32;
+#endif
+    } s;
+    struct cvmx_l2c_grpwrr1_s            cn52xx;
+    struct cvmx_l2c_grpwrr1_s            cn52xxp1;
+    struct cvmx_l2c_grpwrr1_s            cn56xx;
+    struct cvmx_l2c_grpwrr1_s            cn56xxp1;
+} cvmx_l2c_grpwrr1_t;
+
+
+/**
+ * cvmx_l2c_int_en
+ *
+ * L2C_INT_EN = L2C Global Interrupt Enable Register
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t lck2ena                 : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA2] */
+        uint64_t lckena                  : 1;       /**< L2 Tag Lock Error Interrupt Enable bit
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCK_INTENA] */
+        uint64_t l2ddeden                : 1;       /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on double bit
+                                                         (uncorrectable) errors from the L2 Data Arrays.
+                                                         NOTE: This is the 'same' bit as L2D_ERR[DED_INTENA] */
+        uint64_t l2dsecen                : 1;       /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on single bit
+                                                         (correctable) errors from the L2 Data Arrays.
+                                                         NOTE: This is the 'same' bit as L2D_ERR[SEC_INTENA] */
+        uint64_t l2tdeden                : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         NOTE: This is the 'same' bit as L2T_ERR[DED_INTENA] */
+        uint64_t l2tsecen                : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays.
+                                                         NOTE: This is the 'same' bit as L2T_ERR[SEC_INTENA] */
+        uint64_t oob3en                  : 1;       /**< DMA Out of Bounds Interrupt Enable Range#3 */
+        uint64_t oob2en                  : 1;       /**< DMA Out of Bounds Interrupt Enable Range#2 */
+        uint64_t oob1en                  : 1;       /**< DMA Out of Bounds Interrupt Enable Range#1 */
+#else
+        uint64_t oob1en                  : 1;
+        uint64_t oob2en                  : 1;
+        uint64_t oob3en                  : 1;
+        uint64_t l2tsecen                : 1;
+        uint64_t l2tdeden                : 1;
+        uint64_t l2dsecen                : 1;
+        uint64_t l2ddeden                : 1;
+        uint64_t lckena                  : 1;
+        uint64_t lck2ena                 : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_l2c_int_en_s             cn52xx;
+    struct cvmx_l2c_int_en_s             cn52xxp1;
+    struct cvmx_l2c_int_en_s             cn56xx;
+    struct cvmx_l2c_int_en_s             cn56xxp1;
+} cvmx_l2c_int_en_t;
+
+
+/**
+ * cvmx_l2c_int_stat
+ *
+ * L2C_INT_STAT = L2C Global Interrupt Status Register
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_int_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t lck2                    : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked.
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCKERR2] */
+        uint64_t lck                     : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs).
+                                                         NOTE: This is the 'same' bit as L2T_ERR[LCKERR] */
+        uint64_t l2dded                  : 1;       /**< L2D Double Error detected (DED)
+                                                         NOTE: This is the 'same' bit as L2D_ERR[DED_ERR] */
+        uint64_t l2dsec                  : 1;       /**< L2D Single Error corrected (SEC)
+                                                         NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR] */
+        uint64_t l2tded                  : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled).
+                                                         NOTE: This is the 'same' bit as L2T_ERR[DED_ERR] */
+        uint64_t l2tsec                  : 1;       /**< L2T Single Bit Error corrected (SEC) status
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled).
+                                                         NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR] */
+        uint64_t oob3                    : 1;       /**< DMA Out of Bounds Interrupt Status Range#3 */
+        uint64_t oob2                    : 1;       /**< DMA Out of Bounds Interrupt Status Range#2 */
+        uint64_t oob1                    : 1;       /**< DMA Out of Bounds Interrupt Status Range#1 */
+#else
+        uint64_t oob1                    : 1;
+        uint64_t oob2                    : 1;
+        uint64_t oob3                    : 1;
+        uint64_t l2tsec                  : 1;
+        uint64_t l2tded                  : 1;
+        uint64_t l2dsec                  : 1;
+        uint64_t l2dded                  : 1;
+        uint64_t lck                     : 1;
+        uint64_t lck2                    : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_l2c_int_stat_s           cn52xx;
+    struct cvmx_l2c_int_stat_s           cn52xxp1;
+    struct cvmx_l2c_int_stat_s           cn56xx;
+    struct cvmx_l2c_int_stat_s           cn56xxp1;
+} cvmx_l2c_int_stat_t;
+
+
+/**
+ * cvmx_l2c_lckbase
+ *
+ * L2C_LCKBASE = L2C LockDown Base Register
+ * 
+ * Description: L2C LockDown Base Register
+ *
+ * Notes:
+ * (1) SW RESTRICTION \#1: SW must manage the L2 Data Store lockdown space such that at least 1
+ *     set per cache line remains in the 'unlocked' (normal) state to allow general caching operations.
+ *     If SW violates this restriction, a status bit is set (LCK_ERR) and an interrupt is posted.
+ *     [this limits the total lockdown space to 7/8ths of the total L2 data store = 896KB]
+ * (2) IOB initiated LDI commands are ignored (only PP initiated LDI/LDD commands are considered
+ *     for lockdown).
+ * (3) To 'unlock' a locked cache line, SW can use the FLUSH-INVAL CSR mechanism (see L2C_DBG[FINV]).
+ * (4) LCK_ENA MUST only be activated when debug modes are disabled (L2C_DBG[L2T], L2C_DBG[L2D], L2C_DBG[FINV]).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_lckbase_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t lck_base                : 27;      /**< Base Memory block address[33:7]. Specifies the
+                                                         starting address of the lockdown region. */
+        uint64_t reserved_1_3            : 3;
+        uint64_t lck_ena                 : 1;       /**< L2 Cache Lock Enable
+                                                         When the LCK_ENA=1, all LDI(I-stream Load) or
+                                                         LDD(L1 load-miss) commands issued from the
+                                                         diagnostic PP (specified by the L2C_DBG[PPNUM]),
+                                                         which fall within a predefined lockdown address
+                                                         range (specified by: [lck_base:lck_base+lck_offset])
+                                                         are LOCKED in the L2 cache. The LOCKED state is
+                                                         denoted using an explicit L2 Tag bit (L=1).
+                                                         If the LOCK request L2-Hits (on ANY SET), then data is
+                                                         returned from the L2 and the hit set is updated to the
+                                                         LOCKED state. NOTE: If the Hit Set# is outside the
+                                                         available sets for a given PP (see UMSK'x'), the
+                                                         the LOCK bit is still SET. If the programmer's intent
+                                                         is to explicitly LOCK addresses into 'available' sets,
+                                                         care must be taken to flush-invalidate the cache first
+                                                         (to avoid such situations). Not following this procedure
+                                                         can lead to LCKERR2 interrupts.
+                                                         If the LOCK request L2-Misses, a replacment set is
+                                                         chosen(from the available sets (UMSK'x').
+                                                         If the replacement set contains a dirty-victim it is
+                                                         written back to memory. Memory read data is then written
+                                                         into the replacement set, and the replacment SET is
+                                                         updated to the LOCKED state(L=1).
+                                                         NOTE: SETs that contain LOCKED addresses are
+                                                         excluded from the replacement set selection algorithm.
+                                                         NOTE: The LDD command will allocate the DuTag as normal.
+                                                         NOTE: If L2C_CFG[IDXALIAS]=1, the address is 'aliased' first
+                                                         before being checked against the lockdown address
+                                                         range. To ensure an 'aliased' address is properly locked,
+                                                         it is recommmended that SW preload the 'aliased' locked adddress
+                                                         into the L2C_LCKBASE[LCK_BASE] register (while keeping
+                                                         L2C_LCKOFF[LCK_OFFSET]=0).
+                                                         NOTE: The OCTEON(N3) implementation only supports 16GB(MAX) of
+                                                         physical memory. Therefore, only byte address[33:0] are used
+                                                         (ie: address[35:34] are ignored). */
+#else
+        uint64_t lck_ena                 : 1;
+        uint64_t reserved_1_3            : 3;
+        uint64_t lck_base                : 27;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_l2c_lckbase_s            cn30xx;
+    struct cvmx_l2c_lckbase_s            cn31xx;
+    struct cvmx_l2c_lckbase_s            cn38xx;
+    struct cvmx_l2c_lckbase_s            cn38xxp2;
+    struct cvmx_l2c_lckbase_s            cn50xx;
+    struct cvmx_l2c_lckbase_s            cn52xx;
+    struct cvmx_l2c_lckbase_s            cn52xxp1;
+    struct cvmx_l2c_lckbase_s            cn56xx;
+    struct cvmx_l2c_lckbase_s            cn56xxp1;
+    struct cvmx_l2c_lckbase_s            cn58xx;
+    struct cvmx_l2c_lckbase_s            cn58xxp1;
+} cvmx_l2c_lckbase_t;
+
+
+/**
+ * cvmx_l2c_lckoff
+ *
+ * L2C_LCKOFF = L2C LockDown OFFSET Register
+ * 
+ * Description: L2C LockDown OFFSET Register
+ *
+ * Notes:
+ * (1) The generation of the end lockdown block address will 'wrap'.
+ * (2) The minimum granularity for lockdown is 1 cache line (= 128B block)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_lckoff_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t lck_offset              : 10;      /**< LockDown block Offset. Used in determining
+                                                         the ending block address of the lockdown
+                                                         region:
+                                                         End Lockdown block Address[33:7] =
+                                                         LCK_BASE[33:7]+LCK_OFFSET[9:0] */
+#else
+        uint64_t lck_offset              : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_l2c_lckoff_s             cn30xx;
+    struct cvmx_l2c_lckoff_s             cn31xx;
+    struct cvmx_l2c_lckoff_s             cn38xx;
+    struct cvmx_l2c_lckoff_s             cn38xxp2;
+    struct cvmx_l2c_lckoff_s             cn50xx;
+    struct cvmx_l2c_lckoff_s             cn52xx;
+    struct cvmx_l2c_lckoff_s             cn52xxp1;
+    struct cvmx_l2c_lckoff_s             cn56xx;
+    struct cvmx_l2c_lckoff_s             cn56xxp1;
+    struct cvmx_l2c_lckoff_s             cn58xx;
+    struct cvmx_l2c_lckoff_s             cn58xxp1;
+} cvmx_l2c_lckoff_t;
+
+
+/**
+ * cvmx_l2c_lfb0
+ *
+ * L2C_LFB0 = L2C LFB DEBUG 0 Register
+ * 
+ * Description: L2C LFB Contents (Status Bits)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_lfb0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
+        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
+        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
+        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
+        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
+        uint64_t inxt                    : 4;       /**< Next LFB Pointer(invalid if ITL=1) */
+        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
+        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
+        uint64_t set                     : 3;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
+        uint64_t vabnum                  : 4;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+        uint64_t sid                     : 9;       /**< LFB Source ID */
+        uint64_t cmd                     : 4;       /**< LFB Command */
+        uint64_t vld                     : 1;       /**< LFB Valid */
+#else
+        uint64_t vld                     : 1;
+        uint64_t cmd                     : 4;
+        uint64_t sid                     : 9;
+        uint64_t vabnum                  : 4;
+        uint64_t set                     : 3;
+        uint64_t ihd                     : 1;
+        uint64_t itl                     : 1;
+        uint64_t inxt                    : 4;
+        uint64_t vam                     : 1;
+        uint64_t stcfl                   : 1;
+        uint64_t stinv                   : 1;
+        uint64_t stpnd                   : 1;
+        uint64_t stcpnd                  : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_l2c_lfb0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
+        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
+        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
+        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
+        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
+        uint64_t reserved_25_26          : 2;
+        uint64_t inxt                    : 2;       /**< Next LFB Pointer(invalid if ITL=1) */
+        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
+        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
+        uint64_t reserved_20_20          : 1;
+        uint64_t set                     : 2;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
+        uint64_t reserved_16_17          : 2;
+        uint64_t vabnum                  : 2;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+        uint64_t sid                     : 9;       /**< LFB Source ID */
+        uint64_t cmd                     : 4;       /**< LFB Command */
+        uint64_t vld                     : 1;       /**< LFB Valid */
+#else
+        uint64_t vld                     : 1;
+        uint64_t cmd                     : 4;
+        uint64_t sid                     : 9;
+        uint64_t vabnum                  : 2;
+        uint64_t reserved_16_17          : 2;
+        uint64_t set                     : 2;
+        uint64_t reserved_20_20          : 1;
+        uint64_t ihd                     : 1;
+        uint64_t itl                     : 1;
+        uint64_t inxt                    : 2;
+        uint64_t reserved_25_26          : 2;
+        uint64_t vam                     : 1;
+        uint64_t stcfl                   : 1;
+        uint64_t stinv                   : 1;
+        uint64_t stpnd                   : 1;
+        uint64_t stcpnd                  : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_lfb0_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
+        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
+        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
+        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
+        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
+        uint64_t reserved_26_26          : 1;
+        uint64_t inxt                    : 3;       /**< Next LFB Pointer(invalid if ITL=1) */
+        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
+        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
+        uint64_t reserved_20_20          : 1;
+        uint64_t set                     : 2;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
+        uint64_t reserved_17_17          : 1;
+        uint64_t vabnum                  : 3;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+        uint64_t sid                     : 9;       /**< LFB Source ID */
+        uint64_t cmd                     : 4;       /**< LFB Command */
+        uint64_t vld                     : 1;       /**< LFB Valid */
+#else
+        uint64_t vld                     : 1;
+        uint64_t cmd                     : 4;
+        uint64_t sid                     : 9;
+        uint64_t vabnum                  : 3;
+        uint64_t reserved_17_17          : 1;
+        uint64_t set                     : 2;
+        uint64_t reserved_20_20          : 1;
+        uint64_t ihd                     : 1;
+        uint64_t itl                     : 1;
+        uint64_t inxt                    : 3;
+        uint64_t reserved_26_26          : 1;
+        uint64_t vam                     : 1;
+        uint64_t stcfl                   : 1;
+        uint64_t stinv                   : 1;
+        uint64_t stpnd                   : 1;
+        uint64_t stcpnd                  : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn31xx;
+    struct cvmx_l2c_lfb0_s               cn38xx;
+    struct cvmx_l2c_lfb0_s               cn38xxp2;
+    struct cvmx_l2c_lfb0_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t stcpnd                  : 1;       /**< LFB STC Pending Status */
+        uint64_t stpnd                   : 1;       /**< LFB ST* Pending Status */
+        uint64_t stinv                   : 1;       /**< LFB ST* Invalidate Status */
+        uint64_t stcfl                   : 1;       /**< LFB STC=FAIL Status */
+        uint64_t vam                     : 1;       /**< Valid Full Address Match Status */
+        uint64_t reserved_26_26          : 1;
+        uint64_t inxt                    : 3;       /**< Next LFB Pointer(invalid if ITL=1) */
+        uint64_t itl                     : 1;       /**< LFB Tail of List Indicator */
+        uint64_t ihd                     : 1;       /**< LFB Head of List Indicator */
+        uint64_t set                     : 3;       /**< SET# used for DS-OP (hit=hset/miss=rset) */
+        uint64_t reserved_17_17          : 1;
+        uint64_t vabnum                  : 3;       /**< VAB# used for LMC Miss Launch(valid only if VAM=1) */
+        uint64_t sid                     : 9;       /**< LFB Source ID */
+        uint64_t cmd                     : 4;       /**< LFB Command */
+        uint64_t vld                     : 1;       /**< LFB Valid */
+#else
+        uint64_t vld                     : 1;
+        uint64_t cmd                     : 4;
+        uint64_t sid                     : 9;
+        uint64_t vabnum                  : 3;
+        uint64_t reserved_17_17          : 1;
+        uint64_t set                     : 3;
+        uint64_t ihd                     : 1;
+        uint64_t itl                     : 1;
+        uint64_t inxt                    : 3;
+        uint64_t reserved_26_26          : 1;
+        uint64_t vam                     : 1;
+        uint64_t stcfl                   : 1;
+        uint64_t stinv                   : 1;
+        uint64_t stpnd                   : 1;
+        uint64_t stcpnd                  : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn50xx;
+    struct cvmx_l2c_lfb0_cn50xx          cn52xx;
+    struct cvmx_l2c_lfb0_cn50xx          cn52xxp1;
+    struct cvmx_l2c_lfb0_s               cn56xx;
+    struct cvmx_l2c_lfb0_s               cn56xxp1;
+    struct cvmx_l2c_lfb0_s               cn58xx;
+    struct cvmx_l2c_lfb0_s               cn58xxp1;
+} cvmx_l2c_lfb0_t;
+
+
+/**
+ * cvmx_l2c_lfb1
+ *
+ * L2C_LFB1 = L2C LFB DEBUG 1 Register
+ * 
+ * Description: L2C LFB Contents (Wait Bits)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_lfb1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t dsgoing                 : 1;       /**< LFB DS Going (in flight) */
+        uint64_t bid                     : 2;       /**< LFB DS Bid# */
+        uint64_t wtrsp                   : 1;       /**< LFB Waiting for RSC Response [FILL,STRSP] completion */
+        uint64_t wtdw                    : 1;       /**< LFB Waiting for DS-WR completion */
+        uint64_t wtdq                    : 1;       /**< LFB Waiting for LFB-DQ */
+        uint64_t wtwhp                   : 1;       /**< LFB Waiting for Write-Hit Partial L2 DS-WR completion */
+        uint64_t wtwhf                   : 1;       /**< LFB Waiting for Write-Hit Full L2 DS-WR completion */
+        uint64_t wtwrm                   : 1;       /**< LFB Waiting for Write-Miss L2 DS-WR completion */
+        uint64_t wtstm                   : 1;       /**< LFB Waiting for Write-Miss L2 DS-WR completion */
+        uint64_t wtrda                   : 1;       /**< LFB Waiting for Read-Miss L2 DS-WR completion */
+        uint64_t wtstdt                  : 1;       /**< LFB Waiting for all ST write Data to arrive on XMD bus */
+        uint64_t wtstrsp                 : 1;       /**< LFB Waiting for ST RSC/RSD to be issued on RSP
+                                                         (with invalidates) */
+        uint64_t wtstrsc                 : 1;       /**< LFB Waiting for ST RSC-Only to be issued on RSP
+                                                         (no-invalidates) */
+        uint64_t wtvtm                   : 1;       /**< LFB Waiting for Victim Read L2 DS-RD completion */
+        uint64_t wtmfl                   : 1;       /**< LFB Waiting for Memory Fill completion to MRB */
+        uint64_t prbrty                  : 1;       /**< Probe-Retry Detected - waiting for probe completion */
+        uint64_t wtprb                   : 1;       /**< LFB Waiting for Probe */
+        uint64_t vld                     : 1;       /**< LFB Valid */
+#else
+        uint64_t vld                     : 1;
+        uint64_t wtprb                   : 1;
+        uint64_t prbrty                  : 1;
+        uint64_t wtmfl                   : 1;
+        uint64_t wtvtm                   : 1;
+        uint64_t wtstrsc                 : 1;
+        uint64_t wtstrsp                 : 1;
+        uint64_t wtstdt                  : 1;
+        uint64_t wtrda                   : 1;
+        uint64_t wtstm                   : 1;
+        uint64_t wtwrm                   : 1;
+        uint64_t wtwhf                   : 1;
+        uint64_t wtwhp                   : 1;
+        uint64_t wtdq                    : 1;
+        uint64_t wtdw                    : 1;
+        uint64_t wtrsp                   : 1;
+        uint64_t bid                     : 2;
+        uint64_t dsgoing                 : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } s;
+    struct cvmx_l2c_lfb1_s               cn30xx;
+    struct cvmx_l2c_lfb1_s               cn31xx;
+    struct cvmx_l2c_lfb1_s               cn38xx;
+    struct cvmx_l2c_lfb1_s               cn38xxp2;
+    struct cvmx_l2c_lfb1_s               cn50xx;
+    struct cvmx_l2c_lfb1_s               cn52xx;
+    struct cvmx_l2c_lfb1_s               cn52xxp1;
+    struct cvmx_l2c_lfb1_s               cn56xx;
+    struct cvmx_l2c_lfb1_s               cn56xxp1;
+    struct cvmx_l2c_lfb1_s               cn58xx;
+    struct cvmx_l2c_lfb1_s               cn58xxp1;
+} cvmx_l2c_lfb1_t;
+
+
+/**
+ * cvmx_l2c_lfb2
+ *
+ * L2C_LFB2 = L2C LFB DEBUG 2 Register
+ * 
+ * Description: L2C LFB Contents Tag/Index
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_lfb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_l2c_lfb2_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t lfb_tag                 : 19;      /**< LFB TAG[33:15] */
+        uint64_t lfb_idx                 : 8;       /**< LFB IDX[14:7] */
+#else
+        uint64_t lfb_idx                 : 8;
+        uint64_t lfb_tag                 : 19;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_lfb2_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t lfb_tag                 : 17;      /**< LFB TAG[33:16] */
+        uint64_t lfb_idx                 : 10;      /**< LFB IDX[15:7] */
+#else
+        uint64_t lfb_idx                 : 10;
+        uint64_t lfb_tag                 : 17;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn31xx;
+    struct cvmx_l2c_lfb2_cn31xx          cn38xx;
+    struct cvmx_l2c_lfb2_cn31xx          cn38xxp2;
+    struct cvmx_l2c_lfb2_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t lfb_tag                 : 20;      /**< LFB TAG[33:14] */
+        uint64_t lfb_idx                 : 7;       /**< LFB IDX[13:7] */
+#else
+        uint64_t lfb_idx                 : 7;
+        uint64_t lfb_tag                 : 20;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn50xx;
+    struct cvmx_l2c_lfb2_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t lfb_tag                 : 18;      /**< LFB TAG[33:16] */
+        uint64_t lfb_idx                 : 9;       /**< LFB IDX[15:7] */
+#else
+        uint64_t lfb_idx                 : 9;
+        uint64_t lfb_tag                 : 18;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn52xx;
+    struct cvmx_l2c_lfb2_cn52xx          cn52xxp1;
+    struct cvmx_l2c_lfb2_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t lfb_tag                 : 16;      /**< LFB TAG[33:18] */
+        uint64_t lfb_idx                 : 11;      /**< LFB IDX[17:7] */
+#else
+        uint64_t lfb_idx                 : 11;
+        uint64_t lfb_tag                 : 16;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn56xx;
+    struct cvmx_l2c_lfb2_cn56xx          cn56xxp1;
+    struct cvmx_l2c_lfb2_cn56xx          cn58xx;
+    struct cvmx_l2c_lfb2_cn56xx          cn58xxp1;
+} cvmx_l2c_lfb2_t;
+
+
+/**
+ * cvmx_l2c_lfb3
+ *
+ * L2C_LFB3 = L2C LFB DEBUG 3 Register
+ * 
+ * Description: LFB High Water Mark Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_lfb3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t stpartdis               : 1;       /**< STP/C Performance Enhancement Disable
+                                                         When clear, all STP/C(store partials) will take 2 cycles
+                                                         to complete (power-on default).
+                                                         When set, all STP/C(store partials) will take 4 cycles
+                                                         to complete.
+                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t lfb_hwm                 : 4;       /**< LFB High Water Mark
+                                                         Determines \#of LFB Entries in use before backpressure
+                                                         is asserted.
+                                                            HWM=0:   1 LFB Entry available
+                                                                       - ...
+                                                            HWM=15: 16 LFB Entries available
+                                                         *** NOTE: PASS2 Addition */
+#else
+        uint64_t lfb_hwm                 : 4;
+        uint64_t stpartdis               : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_l2c_lfb3_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t stpartdis               : 1;       /**< STP/C Performance Enhancement Disable
+                                                         When clear, all STP/C(store partials) will take 2 cycles
+                                                         to complete (power-on default).
+                                                         When set, all STP/C(store partials) will take 4 cycles
+                                                         to complete.
+                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
+        uint64_t reserved_2_3            : 2;
+        uint64_t lfb_hwm                 : 2;       /**< LFB High Water Mark
+                                                         Determines \#of LFB Entries in use before backpressure
+                                                         is asserted.
+                                                            HWM=0:   1 LFB Entry available
+                                                                       - ...
+                                                            HWM=3:   4 LFB Entries available */
+#else
+        uint64_t lfb_hwm                 : 2;
+        uint64_t reserved_2_3            : 2;
+        uint64_t stpartdis               : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_lfb3_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t stpartdis               : 1;       /**< STP/C Performance Enhancement Disable
+                                                         When clear, all STP/C(store partials) will take 2 cycles
+                                                         to complete (power-on default).
+                                                         When set, all STP/C(store partials) will take 4 cycles
+                                                         to complete.
+                                                         NOTE: It is recommended to keep this bit ALWAYS ZERO. */
+        uint64_t reserved_3_3            : 1;
+        uint64_t lfb_hwm                 : 3;       /**< LFB High Water Mark
+                                                         Determines \#of LFB Entries in use before backpressure
+                                                         is asserted.
+                                                            HWM=0:   1 LFB Entry available
+                                                                       - ...
+                                                            HWM=7:   8 LFB Entries available */
+#else
+        uint64_t lfb_hwm                 : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t stpartdis               : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn31xx;
+    struct cvmx_l2c_lfb3_s               cn38xx;
+    struct cvmx_l2c_lfb3_s               cn38xxp2;
+    struct cvmx_l2c_lfb3_cn31xx          cn50xx;
+    struct cvmx_l2c_lfb3_cn31xx          cn52xx;
+    struct cvmx_l2c_lfb3_cn31xx          cn52xxp1;
+    struct cvmx_l2c_lfb3_s               cn56xx;
+    struct cvmx_l2c_lfb3_s               cn56xxp1;
+    struct cvmx_l2c_lfb3_s               cn58xx;
+    struct cvmx_l2c_lfb3_s               cn58xxp1;
+} cvmx_l2c_lfb3_t;
+
+
+/**
+ * cvmx_l2c_oob
+ *
+ * L2C_OOB = L2C Out of Bounds Global Enables
+ * 
+ * Description: Defines DMA "Out of Bounds" global enables.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_oob_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dwbena                  : 1;       /**< DMA Out of Bounds Range Checker for DMA DWB
+                                                         commands (Don't WriteBack).
+                                                         When enabled, any DMA DWB commands which hit 1-of-3
+                                                         out of bounds regions will be logged into
+                                                         L2C_INT_STAT[OOB*] CSRs and the DMA store WILL
+                                                         NOT occur. If the corresponding L2C_INT_EN[OOB*]
+                                                         is enabled, an interrupt will also be reported. */
+        uint64_t stena                   : 1;       /**< DMA Out of Bounds Range Checker for DMA store
+                                                         commands (STF/P/T).
+                                                         When enabled, any DMA store commands (STF/P/T) which
+                                                         hit 1-of-3 out of bounds regions will be logged into
+                                                         L2C_INT_STAT[OOB*] CSRs and the DMA store WILL
+                                                         NOT occur. If the corresponding L2C_INT_EN[OOB*]
+                                                         is enabled, an interrupt will also be reported. */
+#else
+        uint64_t stena                   : 1;
+        uint64_t dwbena                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_l2c_oob_s                cn52xx;
+    struct cvmx_l2c_oob_s                cn52xxp1;
+    struct cvmx_l2c_oob_s                cn56xx;
+    struct cvmx_l2c_oob_s                cn56xxp1;
+} cvmx_l2c_oob_t;
+
+
+/**
+ * cvmx_l2c_oob1
+ *
+ * L2C_OOB1 = L2C Out of Bounds Range Checker
+ * 
+ * Description: Defines DMA "Out of Bounds" region \#1. If a DMA initiated write transaction generates an address
+ * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_oob1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fadr                    : 27;      /**< DMA initated Memory Range Checker Failing Address
+                                                         When L2C_INT_STAT[OOB1]=1, this field indicates the
+                                                         DMA cacheline address.
+                                                         (addr[33:7] = full cacheline address captured)
+                                                         NOTE: FADR is locked down until L2C_INT_STAT[OOB1]
+                                                         is cleared. */
+        uint64_t fsrc                    : 1;       /**< DMA Out of Bounds Failing Source Command
+                                                         When L2C_INT_STAT[OOB1]=1, this field indicates the
+                                                         type of DMA command.
+                                                          - 0: ST* (STF/P/T)
+                                                          - 1: DWB (Don't WriteBack)
+                                                         NOTE: FSRC is locked down until L2C_INT_STAT[OOB1]
+                                                         is cleared. */
+        uint64_t reserved_34_35          : 2;
+        uint64_t sadr                    : 14;      /**< DMA initated Memory Range Checker Starting Address
+                                                         (1MB granularity) */
+        uint64_t reserved_14_19          : 6;
+        uint64_t size                    : 14;      /**< DMA Out of Bounds Range Checker Size
+                                                         (1MB granularity)
+                                                         Example: 0: 0MB / 1: 1MB
+                                                         The range check is for:
+                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
+                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
+                                                         the 34bit ending bounds address. */
+#else
+        uint64_t size                    : 14;
+        uint64_t reserved_14_19          : 6;
+        uint64_t sadr                    : 14;
+        uint64_t reserved_34_35          : 2;
+        uint64_t fsrc                    : 1;
+        uint64_t fadr                    : 27;
+#endif
+    } s;
+    struct cvmx_l2c_oob1_s               cn52xx;
+    struct cvmx_l2c_oob1_s               cn52xxp1;
+    struct cvmx_l2c_oob1_s               cn56xx;
+    struct cvmx_l2c_oob1_s               cn56xxp1;
+} cvmx_l2c_oob1_t;
+
+
+/**
+ * cvmx_l2c_oob2
+ *
+ * L2C_OOB2 = L2C Out of Bounds Range Checker
+ * 
+ * Description: Defines DMA "Out of Bounds" region \#2. If a DMA initiated write transaction generates an address
+ * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_oob2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fadr                    : 27;      /**< DMA initated Memory Range Checker Failing Address
+                                                         When L2C_INT_STAT[OOB2]=1, this field indicates the
+                                                         DMA cacheline address.
+                                                         (addr[33:7] = full cacheline address captured)
+                                                         NOTE: FADR is locked down until L2C_INT_STAT[OOB2]
+                                                         is cleared. */
+        uint64_t fsrc                    : 1;       /**< DMA Out of Bounds Failing Source Command
+                                                         When L2C_INT_STAT[OOB2]=1, this field indicates the
+                                                         type of DMA command.
+                                                          - 0: ST* (STF/P/T)
+                                                          - 1: DWB (Don't WriteBack)
+                                                         NOTE: FSRC is locked down until L2C_INT_STAT[OOB2]
+                                                         is cleared. */
+        uint64_t reserved_34_35          : 2;
+        uint64_t sadr                    : 14;      /**< DMA initated Memory Range Checker Starting Address
+                                                         (1MB granularity) */
+        uint64_t reserved_14_19          : 6;
+        uint64_t size                    : 14;      /**< DMA Out of Bounds Range Checker Size
+                                                         (1MB granularity)
+                                                         Example: 0: 0MB / 1: 1MB
+                                                         The range check is for:
+                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
+                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
+                                                         the 34bit ending bounds address. */
+#else
+        uint64_t size                    : 14;
+        uint64_t reserved_14_19          : 6;
+        uint64_t sadr                    : 14;
+        uint64_t reserved_34_35          : 2;
+        uint64_t fsrc                    : 1;
+        uint64_t fadr                    : 27;
+#endif
+    } s;
+    struct cvmx_l2c_oob2_s               cn52xx;
+    struct cvmx_l2c_oob2_s               cn52xxp1;
+    struct cvmx_l2c_oob2_s               cn56xx;
+    struct cvmx_l2c_oob2_s               cn56xxp1;
+} cvmx_l2c_oob2_t;
+
+
+/**
+ * cvmx_l2c_oob3
+ *
+ * L2C_OOB3 = L2C Out of Bounds Range Checker
+ * 
+ * Description: Defines DMA "Out of Bounds" region \#3. If a DMA initiated write transaction generates an address
+ * within the specified region, the write is 'ignored' and an interrupt is generated to alert software.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_oob3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fadr                    : 27;      /**< DMA initated Memory Range Checker Failing Address
+                                                         When L2C_INT_STAT[OOB3]=1, this field indicates the
+                                                         DMA cacheline address.
+                                                         (addr[33:7] = full cacheline address captured)
+                                                         NOTE: FADR is locked down until L2C_INT_STAT[00B3]
+                                                         is cleared. */
+        uint64_t fsrc                    : 1;       /**< DMA Out of Bounds Failing Source Command
+                                                         When L2C_INT_STAT[OOB3]=1, this field indicates the
+                                                         type of DMA command.
+                                                          - 0: ST* (STF/P/T)
+                                                          - 1: DWB (Don't WriteBack)
+                                                         NOTE: FSRC is locked down until L2C_INT_STAT[00B3]
+                                                         is cleared. */
+        uint64_t reserved_34_35          : 2;
+        uint64_t sadr                    : 14;      /**< DMA initated Memory Range Checker Starting Address
+                                                         (1MB granularity) */
+        uint64_t reserved_14_19          : 6;
+        uint64_t size                    : 14;      /**< DMA Out of Bounds Range Checker Size
+                                                         (1MB granularity)
+                                                         Example: 0: 0MB / 1: 1MB
+                                                         The range check is for:
+                                                             (SADR<<20) <= addr[33:0] < (((SADR+SIZE) & 0x3FFF)<<20)
+                                                         SW NOTE: SADR+SIZE could be setup to potentially wrap
+                                                         the 34bit ending bounds address. */
+#else
+        uint64_t size                    : 14;
+        uint64_t reserved_14_19          : 6;
+        uint64_t sadr                    : 14;
+        uint64_t reserved_34_35          : 2;
+        uint64_t fsrc                    : 1;
+        uint64_t fadr                    : 27;
+#endif
+    } s;
+    struct cvmx_l2c_oob3_s               cn52xx;
+    struct cvmx_l2c_oob3_s               cn52xxp1;
+    struct cvmx_l2c_oob3_s               cn56xx;
+    struct cvmx_l2c_oob3_s               cn56xxp1;
+} cvmx_l2c_oob3_t;
+
+
+/**
+ * cvmx_l2c_pfc#
+ *
+ * L2C_PFC0 = L2 Performance Counter \#0
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_pfcx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t pfcnt0                  : 36;      /**< Performance Counter \#0 */
+#else
+        uint64_t pfcnt0                  : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_l2c_pfcx_s               cn30xx;
+    struct cvmx_l2c_pfcx_s               cn31xx;
+    struct cvmx_l2c_pfcx_s               cn38xx;
+    struct cvmx_l2c_pfcx_s               cn38xxp2;
+    struct cvmx_l2c_pfcx_s               cn50xx;
+    struct cvmx_l2c_pfcx_s               cn52xx;
+    struct cvmx_l2c_pfcx_s               cn52xxp1;
+    struct cvmx_l2c_pfcx_s               cn56xx;
+    struct cvmx_l2c_pfcx_s               cn56xxp1;
+    struct cvmx_l2c_pfcx_s               cn58xx;
+    struct cvmx_l2c_pfcx_s               cn58xxp1;
+} cvmx_l2c_pfcx_t;
+
+
+/**
+ * cvmx_l2c_pfctl
+ *
+ * L2C_PFCTL = L2 Performance Counter Control Register
+ * 
+ * Description: Controls the actions of the 4 Performance Counters
+ *
+ * Notes:
+ * - There are four 36b performance counter registers which can simultaneously count events.
+ * Each Counter's event is programmably selected via the corresponding CNTxSEL field:
+ *       CNTxSEL[5:0]    Event
+ *    -----------------+-----------------------
+ *             0       | Cycles
+ *             1       | L2 Instruction Miss
+ *             2       | L2 Instruction Hit
+ *             3       | L2 Data Miss
+ *             4       | L2 Data Hit
+ *             5       | L2 Miss (I/D)
+ *             6       | L2 Hit (I/D)
+ *             7       | L2 Victim Buffer Hit (Retry Probe)
+ *             8       | LFB-NQ Index Conflict
+ *             9       | L2 Tag Probe (issued - could be VB-Retried)
+ *            10       | L2 Tag Update (completed - note: some CMD types do not update)
+ *            11       | L2 Tag Probe Completed (beyond VB-RTY window)
+ *            12       | L2 Tag Dirty Victim
+ *            13       | L2 Data Store NOP
+ *            14       | L2 Data Store READ
+ *            15       | L2 Data Store WRITE
+ *            16       | Memory Fill Data valid (1 strobe/32B)
+ *            17       | Memory Write Request
+ *            18       | Memory Read Request
+ *            19       | Memory Write Data valid (1 strobe/32B)
+ *            20       | XMC NOP (XMC Bus Idle)
+ *            21       | XMC LDT (Load-Through Request)
+ *            22       | XMC LDI (L2 Load I-Stream Request)
+ *            23       | XMC LDD (L2 Load D-stream Request)
+ *            24       | XMC STF (L2 Store Full cacheline Request)
+ *            25       | XMC STT (L2 Store Through Request)
+ *            26       | XMC STP (L2 Store Partial Request)
+ *            27       | XMC STC (L2 Store Conditional Request)
+ *            28       | XMC DWB (L2 Don't WriteBack Request)
+ *            29       | XMC PL2 (L2 Prefetch Request)
+ *            30       | XMC PSL1 (L1 Prefetch Request)
+ *            31       | XMC IOBLD
+ *            32       | XMC IOBST
+ *            33       | XMC IOBDMA
+ *            34       | XMC IOBRSP
+ *            35       | XMD Bus valid (all)
+ *            36       | XMD Bus valid (DST=L2C) Memory Data
+ *            37       | XMD Bus valid (DST=IOB) REFL Data
+ *            38       | XMD Bus valid (DST=PP) IOBRSP Data
+ *            39       | RSC NOP
+ *            40       | RSC STDN
+ *            41       | RSC FILL
+ *            42       | RSC REFL
+ *            43       | RSC STIN
+ *            44       | RSC SCIN
+ *            45       | RSC SCFL
+ *            46       | RSC SCDN
+ *            47       | RSD Data Valid
+ *            48       | RSD Data Valid (FILL)
+ *            49       | RSD Data Valid (STRSP)
+ *            50       | RSD Data Valid (REFL)
+ *            51       | LRF-REQ (LFB-NQ)
+ *            52       | DT RD-ALLOC (LDD/PSL1 Commands)
+ *            53       | DT WR-INVAL (ST* Commands)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_pfctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t cnt3rdclr               : 1;       /**< Performance Counter 3 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC3
+                                                         register will auto-clear the counter. This allows
+                                                         SW to maintain 'cumulative' counters in SW.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t cnt2rdclr               : 1;       /**< Performance Counter 2 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC2
+                                                         register will auto-clear the counter. This allows
+                                                         SW to maintain 'cumulative' counters in SW.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t cnt1rdclr               : 1;       /**< Performance Counter 1 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC1
+                                                         register will auto-clear the counter. This allows
+                                                         SW to maintain 'cumulative' counters in SW.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t cnt0rdclr               : 1;       /**< Performance Counter 0 Read Clear
+                                                         When set, all CSR reads of the L2C_PFC0
+                                                         register will 'auto-clear' the counter. This allows
+                                                         SW to maintain accurate 'cumulative' counters.
+                                                         NOTE: If the CSR read occurs in the same cycle as
+                                                         the 'event' to be counted, the counter will
+                                                         properly reflect the event.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t cnt3ena                 : 1;       /**< Performance Counter 3 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+        uint64_t cnt3clr                 : 1;       /**< Performance Counter 3 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+        uint64_t cnt3sel                 : 6;       /**< Performance Counter 3 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+        uint64_t cnt2ena                 : 1;       /**< Performance Counter 2 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+        uint64_t cnt2clr                 : 1;       /**< Performance Counter 2 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+        uint64_t cnt2sel                 : 6;       /**< Performance Counter 2 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+        uint64_t cnt1ena                 : 1;       /**< Performance Counter 1 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+        uint64_t cnt1clr                 : 1;       /**< Performance Counter 1 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+        uint64_t cnt1sel                 : 6;       /**< Performance Counter 1 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+        uint64_t cnt0ena                 : 1;       /**< Performance Counter 0 Enable
+                                                         When this bit is set, the performance counter
+                                                         is enabled. */
+        uint64_t cnt0clr                 : 1;       /**< Performance Counter 0 Clear
+                                                         When the CSR write occurs, if this bit is set,
+                                                         the performance counter is cleared. Otherwise,
+                                                         it will resume counting from its current value. */
+        uint64_t cnt0sel                 : 6;       /**< Performance Counter 0 Event Selector
+                                                         (see list of selectable events to count in NOTES) */
+#else
+        uint64_t cnt0sel                 : 6;
+        uint64_t cnt0clr                 : 1;
+        uint64_t cnt0ena                 : 1;
+        uint64_t cnt1sel                 : 6;
+        uint64_t cnt1clr                 : 1;
+        uint64_t cnt1ena                 : 1;
+        uint64_t cnt2sel                 : 6;
+        uint64_t cnt2clr                 : 1;
+        uint64_t cnt2ena                 : 1;
+        uint64_t cnt3sel                 : 6;
+        uint64_t cnt3clr                 : 1;
+        uint64_t cnt3ena                 : 1;
+        uint64_t cnt0rdclr               : 1;
+        uint64_t cnt1rdclr               : 1;
+        uint64_t cnt2rdclr               : 1;
+        uint64_t cnt3rdclr               : 1;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_l2c_pfctl_s              cn30xx;
+    struct cvmx_l2c_pfctl_s              cn31xx;
+    struct cvmx_l2c_pfctl_s              cn38xx;
+    struct cvmx_l2c_pfctl_s              cn38xxp2;
+    struct cvmx_l2c_pfctl_s              cn50xx;
+    struct cvmx_l2c_pfctl_s              cn52xx;
+    struct cvmx_l2c_pfctl_s              cn52xxp1;
+    struct cvmx_l2c_pfctl_s              cn56xx;
+    struct cvmx_l2c_pfctl_s              cn56xxp1;
+    struct cvmx_l2c_pfctl_s              cn58xx;
+    struct cvmx_l2c_pfctl_s              cn58xxp1;
+} cvmx_l2c_pfctl_t;
+
+
+/**
+ * cvmx_l2c_ppgrp
+ *
+ * L2C_PPGRP = L2C PP Group Number
+ * 
+ * Description: Defines the PP(Packet Processor) PLC Group \# (0,1,2)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_ppgrp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t pp11grp                 : 2;       /**< PP11 PLC Group# (0,1,2) */
+        uint64_t pp10grp                 : 2;       /**< PP10 PLC Group# (0,1,2) */
+        uint64_t pp9grp                  : 2;       /**< PP9 PLC Group# (0,1,2) */
+        uint64_t pp8grp                  : 2;       /**< PP8 PLC Group# (0,1,2) */
+        uint64_t pp7grp                  : 2;       /**< PP7 PLC Group# (0,1,2) */
+        uint64_t pp6grp                  : 2;       /**< PP6 PLC Group# (0,1,2) */
+        uint64_t pp5grp                  : 2;       /**< PP5 PLC Group# (0,1,2) */
+        uint64_t pp4grp                  : 2;       /**< PP4 PLC Group# (0,1,2) */
+        uint64_t pp3grp                  : 2;       /**< PP3 PLC Group# (0,1,2) */
+        uint64_t pp2grp                  : 2;       /**< PP2 PLC Group# (0,1,2) */
+        uint64_t pp1grp                  : 2;       /**< PP1 PLC Group# (0,1,2) */
+        uint64_t pp0grp                  : 2;       /**< PP0 PLC Group# (0,1,2) */
+#else
+        uint64_t pp0grp                  : 2;
+        uint64_t pp1grp                  : 2;
+        uint64_t pp2grp                  : 2;
+        uint64_t pp3grp                  : 2;
+        uint64_t pp4grp                  : 2;
+        uint64_t pp5grp                  : 2;
+        uint64_t pp6grp                  : 2;
+        uint64_t pp7grp                  : 2;
+        uint64_t pp8grp                  : 2;
+        uint64_t pp9grp                  : 2;
+        uint64_t pp10grp                 : 2;
+        uint64_t pp11grp                 : 2;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_l2c_ppgrp_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t pp3grp                  : 2;       /**< PP3 PLC Group# (0,1,2) */
+        uint64_t pp2grp                  : 2;       /**< PP2 PLC Group# (0,1,2) */
+        uint64_t pp1grp                  : 2;       /**< PP1 PLC Group# (0,1,2) */
+        uint64_t pp0grp                  : 2;       /**< PP0 PLC Group# (0,1,2) */
+#else
+        uint64_t pp0grp                  : 2;
+        uint64_t pp1grp                  : 2;
+        uint64_t pp2grp                  : 2;
+        uint64_t pp3grp                  : 2;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } cn52xx;
+    struct cvmx_l2c_ppgrp_cn52xx         cn52xxp1;
+    struct cvmx_l2c_ppgrp_s              cn56xx;
+    struct cvmx_l2c_ppgrp_s              cn56xxp1;
+} cvmx_l2c_ppgrp_t;
+
+
+/**
+ * cvmx_l2c_spar0
+ *
+ * L2C_SPAR0 = L2 Set Partitioning Register (PP0-3)
+ * 
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There MUST ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_spar0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t umsk3                   : 8;       /**< PP[3] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk2                   : 8;       /**< PP[2] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk1                   : 8;       /**< PP[1] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk0                   : 8;       /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk0                   : 8;
+        uint64_t umsk1                   : 8;
+        uint64_t umsk2                   : 8;
+        uint64_t umsk3                   : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_l2c_spar0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t umsk0                   : 4;       /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk0                   : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_spar0_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t umsk1                   : 4;       /**< PP[1] L2 'DO NOT USE' set partition mask */
+        uint64_t reserved_4_7            : 4;
+        uint64_t umsk0                   : 4;       /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk0                   : 4;
+        uint64_t reserved_4_7            : 4;
+        uint64_t umsk1                   : 4;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn31xx;
+    struct cvmx_l2c_spar0_s              cn38xx;
+    struct cvmx_l2c_spar0_s              cn38xxp2;
+    struct cvmx_l2c_spar0_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t umsk1                   : 8;       /**< PP[1] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk0                   : 8;       /**< PP[0] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk0                   : 8;
+        uint64_t umsk1                   : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn50xx;
+    struct cvmx_l2c_spar0_s              cn52xx;
+    struct cvmx_l2c_spar0_s              cn52xxp1;
+    struct cvmx_l2c_spar0_s              cn56xx;
+    struct cvmx_l2c_spar0_s              cn56xxp1;
+    struct cvmx_l2c_spar0_s              cn58xx;
+    struct cvmx_l2c_spar0_s              cn58xxp1;
+} cvmx_l2c_spar0_t;
+
+
+/**
+ * cvmx_l2c_spar1
+ *
+ * L2C_SPAR1 = L2 Set Partitioning Register (PP4-7)
+ * 
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_spar1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t umsk7                   : 8;       /**< PP[7] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk6                   : 8;       /**< PP[6] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk5                   : 8;       /**< PP[5] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk4                   : 8;       /**< PP[4] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk4                   : 8;
+        uint64_t umsk5                   : 8;
+        uint64_t umsk6                   : 8;
+        uint64_t umsk7                   : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_l2c_spar1_s              cn38xx;
+    struct cvmx_l2c_spar1_s              cn38xxp2;
+    struct cvmx_l2c_spar1_s              cn56xx;
+    struct cvmx_l2c_spar1_s              cn56xxp1;
+    struct cvmx_l2c_spar1_s              cn58xx;
+    struct cvmx_l2c_spar1_s              cn58xxp1;
+} cvmx_l2c_spar1_t;
+
+
+/**
+ * cvmx_l2c_spar2
+ *
+ * L2C_SPAR2 = L2 Set Partitioning Register (PP8-11)
+ * 
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_spar2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t umsk11                  : 8;       /**< PP[11] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk10                  : 8;       /**< PP[10] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk9                   : 8;       /**< PP[9] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk8                   : 8;       /**< PP[8] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk8                   : 8;
+        uint64_t umsk9                   : 8;
+        uint64_t umsk10                  : 8;
+        uint64_t umsk11                  : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_l2c_spar2_s              cn38xx;
+    struct cvmx_l2c_spar2_s              cn38xxp2;
+    struct cvmx_l2c_spar2_s              cn56xx;
+    struct cvmx_l2c_spar2_s              cn56xxp1;
+    struct cvmx_l2c_spar2_s              cn58xx;
+    struct cvmx_l2c_spar2_s              cn58xxp1;
+} cvmx_l2c_spar2_t;
+
+
+/**
+ * cvmx_l2c_spar3
+ *
+ * L2C_SPAR3 = L2 Set Partitioning Register (PP12-15)
+ * 
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_1024K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_512K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_spar3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t umsk15                  : 8;       /**< PP[15] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk14                  : 8;       /**< PP[14] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk13                  : 8;       /**< PP[13] L2 'DO NOT USE' set partition mask */
+        uint64_t umsk12                  : 8;       /**< PP[12] L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umsk12                  : 8;
+        uint64_t umsk13                  : 8;
+        uint64_t umsk14                  : 8;
+        uint64_t umsk15                  : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_l2c_spar3_s              cn38xx;
+    struct cvmx_l2c_spar3_s              cn38xxp2;
+    struct cvmx_l2c_spar3_s              cn58xx;
+    struct cvmx_l2c_spar3_s              cn58xxp1;
+} cvmx_l2c_spar3_t;
+
+
+/**
+ * cvmx_l2c_spar4
+ *
+ * L2C_SPAR4 = L2 Set Partitioning Register (IOB)
+ * 
+ * Description: L2 Set Partitioning Register
+ *
+ * Notes:
+ * - When a bit is set in the UMSK'x' register, a memory command issued from PP='x' will NOT select that
+ *   set for replacement.
+ * - There should ALWAYS BE at least 1 bit clear in each UMSK'x' register for proper L2 cache operation
+ * - NOTES: When L2C FUSE[136] is blown(CRIP_256K), then SETS#7-4 are SET in all UMSK'x' registers
+ *          When L2C FUSE[137] is blown(CRIP_128K), then SETS#7-2 are SET in all UMSK'x' registers
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2c_spar4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t umskiob                 : 8;       /**< IOB L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umskiob                 : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_l2c_spar4_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t umskiob                 : 4;       /**< IOB L2 'DO NOT USE' set partition mask */
+#else
+        uint64_t umskiob                 : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_l2c_spar4_cn30xx         cn31xx;
+    struct cvmx_l2c_spar4_s              cn38xx;
+    struct cvmx_l2c_spar4_s              cn38xxp2;
+    struct cvmx_l2c_spar4_s              cn50xx;
+    struct cvmx_l2c_spar4_s              cn52xx;
+    struct cvmx_l2c_spar4_s              cn52xxp1;
+    struct cvmx_l2c_spar4_s              cn56xx;
+    struct cvmx_l2c_spar4_s              cn56xxp1;
+    struct cvmx_l2c_spar4_s              cn58xx;
+    struct cvmx_l2c_spar4_s              cn58xxp1;
+} cvmx_l2c_spar4_t;
+
+
+/**
+ * cvmx_l2d_bst0
+ *
+ * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_bst0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_35_63          : 29;
+        uint64_t ftl                     : 1;       /**< L2C Data Store Fatal Defect(across all QUADs)
+                                                         2 or more columns were detected bad across all
+                                                         QUADs[0-3]. Please refer to individual quad failures
+                                                         for bad column = 0x7e to determine which QUAD was in
+                                                         error. */
+        uint64_t q0stat                  : 34;      /**< Bist Results for QUAD0
+                                                         Failure \#1 Status
+                                                           [16:14] bad bank
+                                                           [13:7] bad high column
+                                                           [6:0] bad low column
+                                                         Failure \#2 Status
+                                                           [33:31] bad bank
+                                                           [30:24] bad high column
+                                                           [23:17] bad low column
+                                                         NOTES: For bad high/low column reporting:
+                                                            0x7f:   No failure
+                                                            0x7e:   Fatal Defect: 2 or more bad columns
+                                                            0-0x45: Bad column
+                                                         NOTE: If there are less than 2 failures then the
+                                                            bad bank will be 0x7. */
+#else
+        uint64_t q0stat                  : 34;
+        uint64_t ftl                     : 1;
+        uint64_t reserved_35_63          : 29;
+#endif
+    } s;
+    struct cvmx_l2d_bst0_s               cn30xx;
+    struct cvmx_l2d_bst0_s               cn31xx;
+    struct cvmx_l2d_bst0_s               cn38xx;
+    struct cvmx_l2d_bst0_s               cn38xxp2;
+    struct cvmx_l2d_bst0_s               cn50xx;
+    struct cvmx_l2d_bst0_s               cn52xx;
+    struct cvmx_l2d_bst0_s               cn52xxp1;
+    struct cvmx_l2d_bst0_s               cn56xx;
+    struct cvmx_l2d_bst0_s               cn56xxp1;
+    struct cvmx_l2d_bst0_s               cn58xx;
+    struct cvmx_l2d_bst0_s               cn58xxp1;
+} cvmx_l2d_bst0_t;
+
+
+/**
+ * cvmx_l2d_bst1
+ *
+ * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_bst1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t q1stat                  : 34;      /**< Bist Results for QUAD1
+                                                         Failure \#1 Status
+                                                            [16:14] bad bank
+                                                            [13:7] bad high column
+                                                            [6:0] bad low column
+                                                          Failure \#2 Status
+                                                            [33:31] bad bank
+                                                            [30:24] bad high column
+                                                            [23:17] bad low column
+                                                          NOTES: For bad high/low column reporting:
+                                                             0x7f:   No failure
+                                                             0x7e:   Fatal Defect: 2 or more bad columns
+                                                             0-0x45: Bad column
+                                                          NOTE: If there are less than 2 failures then the
+                                                             bad bank will be 0x7. */
+#else
+        uint64_t q1stat                  : 34;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_l2d_bst1_s               cn30xx;
+    struct cvmx_l2d_bst1_s               cn31xx;
+    struct cvmx_l2d_bst1_s               cn38xx;
+    struct cvmx_l2d_bst1_s               cn38xxp2;
+    struct cvmx_l2d_bst1_s               cn50xx;
+    struct cvmx_l2d_bst1_s               cn52xx;
+    struct cvmx_l2d_bst1_s               cn52xxp1;
+    struct cvmx_l2d_bst1_s               cn56xx;
+    struct cvmx_l2d_bst1_s               cn56xxp1;
+    struct cvmx_l2d_bst1_s               cn58xx;
+    struct cvmx_l2d_bst1_s               cn58xxp1;
+} cvmx_l2d_bst1_t;
+
+
+/**
+ * cvmx_l2d_bst2
+ *
+ * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_bst2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t q2stat                  : 34;      /**< Bist Results for QUAD2
+                                                         Failure \#1 Status
+                                                            [16:14] bad bank
+                                                            [13:7] bad high column
+                                                            [6:0] bad low column
+                                                          Failure \#2 Status
+                                                            [33:31] bad bank
+                                                            [30:24] bad high column
+                                                            [23:17] bad low column
+                                                          NOTES: For bad high/low column reporting:
+                                                             0x7f:   No failure
+                                                             0x7e:   Fatal Defect: 2 or more bad columns
+                                                             0-0x45: Bad column
+                                                          NOTE: If there are less than 2 failures then the
+                                                             bad bank will be 0x7. */
+#else
+        uint64_t q2stat                  : 34;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_l2d_bst2_s               cn30xx;
+    struct cvmx_l2d_bst2_s               cn31xx;
+    struct cvmx_l2d_bst2_s               cn38xx;
+    struct cvmx_l2d_bst2_s               cn38xxp2;
+    struct cvmx_l2d_bst2_s               cn50xx;
+    struct cvmx_l2d_bst2_s               cn52xx;
+    struct cvmx_l2d_bst2_s               cn52xxp1;
+    struct cvmx_l2d_bst2_s               cn56xx;
+    struct cvmx_l2d_bst2_s               cn56xxp1;
+    struct cvmx_l2d_bst2_s               cn58xx;
+    struct cvmx_l2d_bst2_s               cn58xxp1;
+} cvmx_l2d_bst2_t;
+
+
+/**
+ * cvmx_l2d_bst3
+ *
+ * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_bst3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t q3stat                  : 34;      /**< Bist Results for QUAD3
+                                                         Failure \#1 Status
+                                                            [16:14] bad bank
+                                                            [13:7] bad high column
+                                                            [6:0] bad low column
+                                                          Failure \#2 Status
+                                                            [33:31] bad bank
+                                                            [30:24] bad high column
+                                                            [23:17] bad low column
+                                                          NOTES: For bad high/low column reporting:
+                                                             0x7f:   No failure
+                                                             0x7e:   Fatal Defect: 2 or more bad columns
+                                                             0-0x45: Bad column
+                                                          NOTE: If there are less than 2 failures then the
+                                                             bad bank will be 0x7. */
+#else
+        uint64_t q3stat                  : 34;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_l2d_bst3_s               cn30xx;
+    struct cvmx_l2d_bst3_s               cn31xx;
+    struct cvmx_l2d_bst3_s               cn38xx;
+    struct cvmx_l2d_bst3_s               cn38xxp2;
+    struct cvmx_l2d_bst3_s               cn50xx;
+    struct cvmx_l2d_bst3_s               cn52xx;
+    struct cvmx_l2d_bst3_s               cn52xxp1;
+    struct cvmx_l2d_bst3_s               cn56xx;
+    struct cvmx_l2d_bst3_s               cn56xxp1;
+    struct cvmx_l2d_bst3_s               cn58xx;
+    struct cvmx_l2d_bst3_s               cn58xxp1;
+} cvmx_l2d_bst3_t;
+
+
+/**
+ * cvmx_l2d_err
+ *
+ * L2D_ERR = L2 Data Errors
+ * 
+ * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_err_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t bmhclsel                : 1;       /**< L2 Bit Map Half CacheLine ECC Selector
+                                                          *** NOTE: PASS2 Addition
+                                                          When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
+                                                          which half cacheline to conditionally latch into
+                                                          the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
+                                                          is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
+                                                         - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
+                                                             be conditionally latched into the L2D_FSYN0/1 CSRs.
+                                                         - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
+                                                             be conditionally latched into
+                                                             the L2D_FSYN0/1 CSRs. */
+        uint64_t ded_err                 : 1;       /**< L2D Double Error detected (DED) */
+        uint64_t sec_err                 : 1;       /**< L2D Single Error corrected (SEC) */
+        uint64_t ded_intena              : 1;       /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on double bit
+                                                         (uncorrectable) errors from the L2 Data Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, allows interrupts to be reported on single bit
+                                                         (correctable) errors from the L2 Data Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Data ECC Enable
+                                                         When set, enables 10-bit SEC/DED codeword for 128bit L2
+                                                         Data Arrays. */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t bmhclsel                : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_l2d_err_s                cn30xx;
+    struct cvmx_l2d_err_s                cn31xx;
+    struct cvmx_l2d_err_s                cn38xx;
+    struct cvmx_l2d_err_s                cn38xxp2;
+    struct cvmx_l2d_err_s                cn50xx;
+    struct cvmx_l2d_err_s                cn52xx;
+    struct cvmx_l2d_err_s                cn52xxp1;
+    struct cvmx_l2d_err_s                cn56xx;
+    struct cvmx_l2d_err_s                cn56xxp1;
+    struct cvmx_l2d_err_s                cn58xx;
+    struct cvmx_l2d_err_s                cn58xxp1;
+} cvmx_l2d_err_t;
+
+
+/**
+ * cvmx_l2d_fadr
+ *
+ * L2D_FADR = L2 Failing Address
+ * 
+ * Description: L2 Data ECC SEC/DED Failing Address
+ *
+ * Notes:
+ * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
+ * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fadr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t fadru                   : 1;       /**< Failing L2 Data Store Upper Index bit(MSB) */
+        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+        uint64_t fset                    : 3;       /**< Failing SET# */
+        uint64_t fadr                    : 11;      /**< Failing L2 Data Store Lower Index bits
+                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
+                                                            [FADRU, FADR[10:1]]: cacheline index[17:7]
+                                                            FADR[0]: 1/2 cacheline index
+                                                         NOTE: FADR[1] is used to select between upper/lower 1MB
+                                                         physical L2 Data Store banks. */
+#else
+        uint64_t fadr                    : 11;
+        uint64_t fset                    : 3;
+        uint64_t fowmsk                  : 4;
+        uint64_t fadru                   : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } s;
+    struct cvmx_l2d_fadr_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+        uint64_t reserved_13_13          : 1;
+        uint64_t fset                    : 2;       /**< Failing SET# */
+        uint64_t reserved_9_10           : 2;
+        uint64_t fadr                    : 9;       /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
+#else
+        uint64_t fadr                    : 9;
+        uint64_t reserved_9_10           : 2;
+        uint64_t fset                    : 2;
+        uint64_t reserved_13_13          : 1;
+        uint64_t fowmsk                  : 4;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn30xx;
+    struct cvmx_l2d_fadr_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+        uint64_t reserved_13_13          : 1;
+        uint64_t fset                    : 2;       /**< Failing SET# */
+        uint64_t reserved_10_10          : 1;
+        uint64_t fadr                    : 10;      /**< Failing L2 Data Store Index
+                                                         (1 of 1024 = half cacheline indices) */
+#else
+        uint64_t fadr                    : 10;
+        uint64_t reserved_10_10          : 1;
+        uint64_t fset                    : 2;
+        uint64_t reserved_13_13          : 1;
+        uint64_t fowmsk                  : 4;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn31xx;
+    struct cvmx_l2d_fadr_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+        uint64_t fset                    : 3;       /**< Failing SET# */
+        uint64_t fadr                    : 11;      /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
+#else
+        uint64_t fadr                    : 11;
+        uint64_t fset                    : 3;
+        uint64_t fowmsk                  : 4;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn38xx;
+    struct cvmx_l2d_fadr_cn38xx          cn38xxp2;
+    struct cvmx_l2d_fadr_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+        uint64_t fset                    : 3;       /**< Failing SET# */
+        uint64_t reserved_8_10           : 3;
+        uint64_t fadr                    : 8;       /**< Failing L2 Data Store Lower Index bits
+                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
+                                                            FADR[7:1]: cacheline index[13:7]
+                                                            FADR[0]: 1/2 cacheline index */
+#else
+        uint64_t fadr                    : 8;
+        uint64_t reserved_8_10           : 3;
+        uint64_t fset                    : 3;
+        uint64_t fowmsk                  : 4;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn50xx;
+    struct cvmx_l2d_fadr_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t fowmsk                  : 4;       /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
+                                                         error) */
+        uint64_t fset                    : 3;       /**< Failing SET# */
+        uint64_t reserved_10_10          : 1;
+        uint64_t fadr                    : 10;      /**< Failing L2 Data Store Lower Index bits
+                                                         (NOTE: L2 Data Store Index is for each 1/2 cacheline)
+                                                            FADR[9:1]: cacheline index[15:7]
+                                                            FADR[0]: 1/2 cacheline index */
+#else
+        uint64_t fadr                    : 10;
+        uint64_t reserved_10_10          : 1;
+        uint64_t fset                    : 3;
+        uint64_t fowmsk                  : 4;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn52xx;
+    struct cvmx_l2d_fadr_cn52xx          cn52xxp1;
+    struct cvmx_l2d_fadr_s               cn56xx;
+    struct cvmx_l2d_fadr_s               cn56xxp1;
+    struct cvmx_l2d_fadr_s               cn58xx;
+    struct cvmx_l2d_fadr_s               cn58xxp1;
+} cvmx_l2d_fadr_t;
+
+
+/**
+ * cvmx_l2d_fsyn0
+ *
+ * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
+ * 
+ * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
+ *
+ * Notes:
+ * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
+ * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fsyn0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t fsyn_ow1                : 10;      /**< Failing L2 Data Store SYNDROME OW[1,5]
+                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
+                                                         or L2D_ERR[DED_ERR] are set, this field represents
+                                                         the failing OWECC syndrome for the half cacheline
+                                                         indexed by L2D_FADR[FADR].
+                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
+                                                         OW lane(1of4) detected the error.
+                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
+                                                         command from the diagnostic PP will conditionally latch
+                                                         the raw OWECC for the selected half cacheline.
+                                                         (see: L2D_ERR[BMHCLSEL] */
+        uint64_t fsyn_ow0                : 10;      /**< Failing L2 Data Store SYNDROME OW[0,4]
+                                                         When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
+                                                         or L2D_ERR[DED_ERR] are set, this field represents
+                                                         the failing OWECC syndrome for the half cacheline
+                                                         indexed by L2D_FADR[FADR].
+                                                         NOTE: The L2D_FADR[FOWMSK] further qualifies which
+                                                         OW lane(1of4) detected the error.
+                                                         When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
+                                                         (L1 load-miss) from the diagnostic PP will conditionally
+                                                         latch the raw OWECC for the selected half cacheline.
+                                                         (see: L2D_ERR[BMHCLSEL] */
+#else
+        uint64_t fsyn_ow0                : 10;
+        uint64_t fsyn_ow1                : 10;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_l2d_fsyn0_s              cn30xx;
+    struct cvmx_l2d_fsyn0_s              cn31xx;
+    struct cvmx_l2d_fsyn0_s              cn38xx;
+    struct cvmx_l2d_fsyn0_s              cn38xxp2;
+    struct cvmx_l2d_fsyn0_s              cn50xx;
+    struct cvmx_l2d_fsyn0_s              cn52xx;
+    struct cvmx_l2d_fsyn0_s              cn52xxp1;
+    struct cvmx_l2d_fsyn0_s              cn56xx;
+    struct cvmx_l2d_fsyn0_s              cn56xxp1;
+    struct cvmx_l2d_fsyn0_s              cn58xx;
+    struct cvmx_l2d_fsyn0_s              cn58xxp1;
+} cvmx_l2d_fsyn0_t;
+
+
+/**
+ * cvmx_l2d_fsyn1
+ *
+ * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
+ * 
+ * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
+ *
+ * Notes:
+ * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
+ * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fsyn1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t fsyn_ow3                : 10;      /**< Failing L2 Data Store SYNDROME OW[3,7] */
+        uint64_t fsyn_ow2                : 10;      /**< Failing L2 Data Store SYNDROME OW[2,5] */
+#else
+        uint64_t fsyn_ow2                : 10;
+        uint64_t fsyn_ow3                : 10;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_l2d_fsyn1_s              cn30xx;
+    struct cvmx_l2d_fsyn1_s              cn31xx;
+    struct cvmx_l2d_fsyn1_s              cn38xx;
+    struct cvmx_l2d_fsyn1_s              cn38xxp2;
+    struct cvmx_l2d_fsyn1_s              cn50xx;
+    struct cvmx_l2d_fsyn1_s              cn52xx;
+    struct cvmx_l2d_fsyn1_s              cn52xxp1;
+    struct cvmx_l2d_fsyn1_s              cn56xx;
+    struct cvmx_l2d_fsyn1_s              cn56xxp1;
+    struct cvmx_l2d_fsyn1_s              cn58xx;
+    struct cvmx_l2d_fsyn1_s              cn58xxp1;
+} cvmx_l2d_fsyn1_t;
+
+
+/**
+ * cvmx_l2d_fus0
+ *
+ * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fus0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t q0fus                   : 34;      /**< Fuse Register for QUAD0
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuse are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q0fus                   : 34;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_l2d_fus0_s               cn30xx;
+    struct cvmx_l2d_fus0_s               cn31xx;
+    struct cvmx_l2d_fus0_s               cn38xx;
+    struct cvmx_l2d_fus0_s               cn38xxp2;
+    struct cvmx_l2d_fus0_s               cn50xx;
+    struct cvmx_l2d_fus0_s               cn52xx;
+    struct cvmx_l2d_fus0_s               cn52xxp1;
+    struct cvmx_l2d_fus0_s               cn56xx;
+    struct cvmx_l2d_fus0_s               cn56xxp1;
+    struct cvmx_l2d_fus0_s               cn58xx;
+    struct cvmx_l2d_fus0_s               cn58xxp1;
+} cvmx_l2d_fus0_t;
+
+
+/**
+ * cvmx_l2d_fus1
+ *
+ * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fus1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t q1fus                   : 34;      /**< Fuse Register for QUAD1
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuse are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q1fus                   : 34;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_l2d_fus1_s               cn30xx;
+    struct cvmx_l2d_fus1_s               cn31xx;
+    struct cvmx_l2d_fus1_s               cn38xx;
+    struct cvmx_l2d_fus1_s               cn38xxp2;
+    struct cvmx_l2d_fus1_s               cn50xx;
+    struct cvmx_l2d_fus1_s               cn52xx;
+    struct cvmx_l2d_fus1_s               cn52xxp1;
+    struct cvmx_l2d_fus1_s               cn56xx;
+    struct cvmx_l2d_fus1_s               cn56xxp1;
+    struct cvmx_l2d_fus1_s               cn58xx;
+    struct cvmx_l2d_fus1_s               cn58xxp1;
+} cvmx_l2d_fus1_t;
+
+
+/**
+ * cvmx_l2d_fus2
+ *
+ * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fus2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t q2fus                   : 34;      /**< Fuse Register for QUAD2
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuse are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q2fus                   : 34;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_l2d_fus2_s               cn30xx;
+    struct cvmx_l2d_fus2_s               cn31xx;
+    struct cvmx_l2d_fus2_s               cn38xx;
+    struct cvmx_l2d_fus2_s               cn38xxp2;
+    struct cvmx_l2d_fus2_s               cn50xx;
+    struct cvmx_l2d_fus2_s               cn52xx;
+    struct cvmx_l2d_fus2_s               cn52xxp1;
+    struct cvmx_l2d_fus2_s               cn56xx;
+    struct cvmx_l2d_fus2_s               cn56xxp1;
+    struct cvmx_l2d_fus2_s               cn58xx;
+    struct cvmx_l2d_fus2_s               cn58xxp1;
+} cvmx_l2d_fus2_t;
+
+
+/**
+ * cvmx_l2d_fus3
+ *
+ * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2d_fus3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[1:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok).
+                                                         NOTE: O9N Addition */
+        uint64_t reserved_34_36          : 3;
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t reserved_34_36          : 3;
+        uint64_t ema_ctl                 : 3;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_l2d_fus3_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_35_63          : 29;
+        uint64_t crip_64k                : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:15] UNUSED
+                                                             [14]    bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:32] UNUSED
+                                                             [31]    bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_64k                : 1;
+        uint64_t reserved_35_63          : 29;
+#endif
+    } cn30xx;
+    struct cvmx_l2d_fus3_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_35_63          : 29;
+        uint64_t crip_128k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:15] UNUSED
+                                                             [14]    bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:32] UNUSED
+                                                             [31]    bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_128k               : 1;
+        uint64_t reserved_35_63          : 29;
+#endif
+    } cn31xx;
+    struct cvmx_l2d_fus3_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t crip_256k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+        uint64_t crip_512k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_512k               : 1;
+        uint64_t crip_256k               : 1;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } cn38xx;
+    struct cvmx_l2d_fus3_cn38xx          cn38xxp2;
+    struct cvmx_l2d_fus3_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[2:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+        uint64_t reserved_36_36          : 1;
+        uint64_t crip_32k                : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+        uint64_t crip_64k                : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_64k                : 1;
+        uint64_t crip_32k                : 1;
+        uint64_t reserved_36_36          : 1;
+        uint64_t ema_ctl                 : 3;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } cn50xx;
+    struct cvmx_l2d_fus3_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[2:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok). */
+        uint64_t reserved_36_36          : 1;
+        uint64_t crip_128k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+        uint64_t crip_256k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1. */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] UNUSED (5020 uses single physical bank per quad)
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] UNUSED (5020 uses single physical bank per quad)
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_256k               : 1;
+        uint64_t crip_128k               : 1;
+        uint64_t reserved_36_36          : 1;
+        uint64_t ema_ctl                 : 3;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } cn52xx;
+    struct cvmx_l2d_fus3_cn52xx          cn52xxp1;
+    struct cvmx_l2d_fus3_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t ema_ctl                 : 3;       /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[2:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok).
+                                                         NOTE: O9N Addition */
+        uint64_t reserved_36_36          : 1;
+        uint64_t crip_512k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+        uint64_t crip_1024k              : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_1024k              : 1;
+        uint64_t crip_512k               : 1;
+        uint64_t reserved_36_36          : 1;
+        uint64_t ema_ctl                 : 3;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } cn56xx;
+    struct cvmx_l2d_fus3_cn56xx          cn56xxp1;
+    struct cvmx_l2d_fus3_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t ema_ctl                 : 2;       /**< L2 Data Store EMA Control
+                                                         These bits are used to 'observe' the EMA[1:0] inputs
+                                                         for the L2 Data Store RAMs which are controlled by
+                                                         either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
+                                                         From poweron (dc_ok), the EMA_CTL are driven from
+                                                         FUSE[141:140]. However after the 1st CSR write to the
+                                                         MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
+                                                         from the MIO_FUSE_EMA[EMA] register permanently
+                                                         (until dc_ok).
+                                                         NOTE: O9N Addition */
+        uint64_t reserved_36_36          : 1;
+        uint64_t crip_512k               : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+        uint64_t crip_1024k              : 1;       /**< This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         If the FUSE is not-blown, then this bit should read
+                                                         as 0. If the FUSE is blown, then this bit should read
+                                                         as 1.
+                                                         *** NOTE: Pass2 Addition */
+        uint64_t q3fus                   : 34;      /**< Fuse Register for QUAD3
+                                                         This is purely for debug and not needed in the general
+                                                         manufacturing flow.
+                                                         Note that the fuses are complementary (Assigning a
+                                                         fuse to 1 will read as a zero). This means the case
+                                                         where no fuses are blown result in these csr's showing
+                                                         all ones.
+                                                          Failure \#1 Fuse Mapping
+                                                             [16:14] bad bank
+                                                             [13:7] bad high column
+                                                             [6:0] bad low column
+                                                           Failure \#2 Fuse Mapping
+                                                             [33:31] bad bank
+                                                             [30:24] bad high column
+                                                             [23:17] bad low column */
+#else
+        uint64_t q3fus                   : 34;
+        uint64_t crip_1024k              : 1;
+        uint64_t crip_512k               : 1;
+        uint64_t reserved_36_36          : 1;
+        uint64_t ema_ctl                 : 2;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } cn58xx;
+    struct cvmx_l2d_fus3_cn58xx          cn58xxp1;
+} cvmx_l2d_fus3_t;
+
+
+/**
+ * cvmx_l2t_err
+ *
+ * L2T_ERR = L2 Tag Errors
+ * 
+ * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_l2t_err_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t fadru                   : 1;       /**< Failing L2 Tag Upper Address Bit (Index[10])
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADRU contains the upper(MSB bit) cacheline index
+                                                         into the L2 Tag Store. */
+        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
+        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+        uint64_t fadr                    : 10;      /**< Failing L2 Tag Address (10-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the lower 10bit cacheline index
+                                                         into the L2 Tag Store. */
+        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 19-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:18]] */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t fsyn                    : 6;
+        uint64_t fadr                    : 10;
+        uint64_t fset                    : 3;
+        uint64_t lckerr                  : 1;
+        uint64_t lck_intena              : 1;
+        uint64_t lckerr2                 : 1;
+        uint64_t lck_intena2             : 1;
+        uint64_t fadru                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_l2t_err_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
+        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
+        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is
+                                                         completed successfully, however the address is NOT
+                                                         locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+        uint64_t reserved_23_23          : 1;
+        uint64_t fset                    : 2;       /**< Failing L2 Tag Hit Set# (1-of-4)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+        uint64_t reserved_19_20          : 2;
+        uint64_t fadr                    : 8;       /**< Failing L2 Tag Store Index (8-bit)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the 8bit cacheline index into the
+                                                         L2 Tag Store. */
+        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 22-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:15]] */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t fsyn                    : 6;
+        uint64_t fadr                    : 8;
+        uint64_t reserved_19_20          : 2;
+        uint64_t fset                    : 2;
+        uint64_t reserved_23_23          : 1;
+        uint64_t lckerr                  : 1;
+        uint64_t lck_intena              : 1;
+        uint64_t lckerr2                 : 1;
+        uint64_t lck_intena2             : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn30xx;
+    struct cvmx_l2t_err_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
+        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
+        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+        uint64_t reserved_23_23          : 1;
+        uint64_t fset                    : 2;       /**< Failing L2 Tag Hit Set# (1-of-4)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+        uint64_t reserved_20_20          : 1;
+        uint64_t fadr                    : 9;       /**< Failing L2 Tag Address (9-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the 9-bit cacheline index into the
+                                                         L2 Tag Store. */
+        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 21-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:16]] */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t fsyn                    : 6;
+        uint64_t fadr                    : 9;
+        uint64_t reserved_20_20          : 1;
+        uint64_t fset                    : 2;
+        uint64_t reserved_23_23          : 1;
+        uint64_t lckerr                  : 1;
+        uint64_t lck_intena              : 1;
+        uint64_t lckerr2                 : 1;
+        uint64_t lck_intena2             : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn31xx;
+    struct cvmx_l2t_err_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked.
+                                                         *** NOTE: PASS2 Addition */
+        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
+        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+        uint64_t fadr                    : 10;      /**< Failing L2 Tag Address (10-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the 10bit cacheline index into the
+                                                         L2 Tag Store. */
+        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 20-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:17]] */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t fsyn                    : 6;
+        uint64_t fadr                    : 10;
+        uint64_t fset                    : 3;
+        uint64_t lckerr                  : 1;
+        uint64_t lck_intena              : 1;
+        uint64_t lckerr2                 : 1;
+        uint64_t lck_intena2             : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn38xx;
+    struct cvmx_l2t_err_cn38xx           cn38xxp2;
+    struct cvmx_l2t_err_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
+        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
+        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+        uint64_t reserved_18_20          : 3;
+        uint64_t fadr                    : 7;       /**< Failing L2 Tag Address (7-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the lower 7bit cacheline index
+                                                         into the L2 Tag Store. */
+        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 23-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:14]] */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t fsyn                    : 6;
+        uint64_t fadr                    : 7;
+        uint64_t reserved_18_20          : 3;
+        uint64_t fset                    : 3;
+        uint64_t lckerr                  : 1;
+        uint64_t lck_intena              : 1;
+        uint64_t lckerr2                 : 1;
+        uint64_t lck_intena2             : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn50xx;
+    struct cvmx_l2t_err_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t lck_intena2             : 1;       /**< L2 Tag Lock Error2 Interrupt Enable bit */
+        uint64_t lckerr2                 : 1;       /**< HW detected a case where a Rd/Wr Miss from PP#n
+                                                         could not find an available/unlocked set (for
+                                                         replacement).
+                                                         Most likely, this is a result of SW mixing SET
+                                                         PARTITIONING with ADDRESS LOCKING. If SW allows
+                                                         another PP to LOCKDOWN all SETs available to PP#n,
+                                                         then a Rd/Wr Miss from PP#n will be unable
+                                                         to determine a 'valid' replacement set (since LOCKED
+                                                         addresses should NEVER be replaced).
+                                                         If such an event occurs, the HW will select the smallest
+                                                         available SET(specified by UMSK'x)' as the replacement
+                                                         set, and the address is unlocked. */
+        uint64_t lck_intena              : 1;       /**< L2 Tag Lock Error Interrupt Enable bit */
+        uint64_t lckerr                  : 1;       /**< SW attempted to LOCK DOWN the last available set of
+                                                         the INDEX (which is ignored by HW - but reported to SW).
+                                                         The LDD(L1 load-miss) for the LOCK operation is completed
+                                                         successfully, however the address is NOT locked.
+                                                         NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]
+                                                         into account. For example, if diagnostic PPx has
+                                                         UMSKx defined to only use SETs [1:0], and SET1 had
+                                                         been previously LOCKED, then an attempt to LOCK the
+                                                         last available SET0 would result in a LCKERR. (This
+                                                         is to ensure that at least 1 SET at each INDEX is
+                                                         not LOCKED for general use by other PPs). */
+        uint64_t fset                    : 3;       /**< Failing L2 Tag Hit Set# (1-of-8)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and
+                                                         (FSYN != 0), the FSET specifies the failing hit-set.
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set
+                                                         is specified by the L2C_DBG[SET]. */
+        uint64_t reserved_20_20          : 1;
+        uint64_t fadr                    : 9;       /**< Failing L2 Tag Address (9-bit Index)
+                                                         When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the FADR contains the lower 9bit cacheline index
+                                                         into the L2 Tag Store. */
+        uint64_t fsyn                    : 6;       /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set,
+                                                         the contents of this register contain the 6-bit
+                                                         syndrome for the hit set only.
+                                                         If (FSYN = 0), the SBE or DBE reported was for one of
+                                                         the "non-hit" sets at the failing index(FADR).
+                                                         NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set
+                                                         is specified by the L2C_DBG[SET].
+                                                         If (FSYN != 0), the SBE or DBE reported was for the
+                                                         hit set at the failing index(FADR) and failing
+                                                         set(FSET).
+                                                         SW NOTE: To determine which "non-hit" set was in error,
+                                                         SW can use the L2C_DBG[L2T] debug feature to explicitly
+                                                         read the other sets at the failing index(FADR). When
+                                                         (FSYN !=0), then the FSET contains the failing hit-set.
+                                                         NOTE: A DED Error will always overwrite a SEC Error
+                                                         SYNDROME and FADR). */
+        uint64_t ded_err                 : 1;       /**< L2T Double Bit Error detected (DED)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for double bit errors(DBEs).
+                                                         This bit is set if ANY of the 8 sets contains a DBE.
+                                                         DBEs also generated an interrupt(if enabled). */
+        uint64_t sec_err                 : 1;       /**< L2T Single Bit Error corrected (SEC)
+                                                         During every L2 Tag Probe, all 8 sets Tag's (at a
+                                                         given index) are checked for single bit errors(SBEs).
+                                                         This bit is set if ANY of the 8 sets contains an SBE.
+                                                         SBEs are auto corrected in HW and generate an
+                                                         interrupt(if enabled). */
+        uint64_t ded_intena              : 1;       /**< L2 Tag ECC Double Error Detect(DED) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on double bit (uncorrectable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t sec_intena              : 1;       /**< L2 Tag ECC Single Error Correct(SEC) Interrupt
+                                                         Enable bit. When set, allows interrupts to be
+                                                         reported on single bit (correctable) errors from
+                                                         the L2 Tag Arrays. */
+        uint64_t ecc_ena                 : 1;       /**< L2 Tag ECC Enable
+                                                         When set, enables 6-bit SEC/DED codeword for 21-bit
+                                                         L2 Tag Arrays [V,D,L,TAG[33:16]] */
+#else
+        uint64_t ecc_ena                 : 1;
+        uint64_t sec_intena              : 1;
+        uint64_t ded_intena              : 1;
+        uint64_t sec_err                 : 1;
+        uint64_t ded_err                 : 1;
+        uint64_t fsyn                    : 6;
+        uint64_t fadr                    : 9;
+        uint64_t reserved_20_20          : 1;
+        uint64_t fset                    : 3;
+        uint64_t lckerr                  : 1;
+        uint64_t lck_intena              : 1;
+        uint64_t lckerr2                 : 1;
+        uint64_t lck_intena2             : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn52xx;
+    struct cvmx_l2t_err_cn52xx           cn52xxp1;
+    struct cvmx_l2t_err_s                cn56xx;
+    struct cvmx_l2t_err_s                cn56xxp1;
+    struct cvmx_l2t_err_s                cn58xx;
+    struct cvmx_l2t_err_s                cn58xxp1;
+} cvmx_l2t_err_t;
+
+
+/**
+ * cvmx_led_blink
+ *
+ * LED_BLINK = LED Blink Rate (in led_clks)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_blink_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rate                    : 8;       /**< LED Blink rate in led_latch clks
+                                                         RATE must be > 0 */
+#else
+        uint64_t rate                    : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_led_blink_s              cn38xx;
+    struct cvmx_led_blink_s              cn38xxp2;
+    struct cvmx_led_blink_s              cn56xx;
+    struct cvmx_led_blink_s              cn56xxp1;
+    struct cvmx_led_blink_s              cn58xx;
+    struct cvmx_led_blink_s              cn58xxp1;
+} cvmx_led_blink_t;
+
+
+/**
+ * cvmx_led_clk_phase
+ *
+ * LED_CLK_PHASE = LED Clock Phase (in 64 eclks)
+ *
+ *
+ * Notes:
+ * Example:
+ * Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each
+ * led_clk phase is 64 eclks, or 128ns.  The led_clk period is 2*phase,
+ * or 256ns which is 3.9MHz.  The default value of 4, yields an led_clk
+ * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_clk_phase_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t phase                   : 7;       /**< Number of 64 eclks in order to create the led_clk */
+#else
+        uint64_t phase                   : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_led_clk_phase_s          cn38xx;
+    struct cvmx_led_clk_phase_s          cn38xxp2;
+    struct cvmx_led_clk_phase_s          cn56xx;
+    struct cvmx_led_clk_phase_s          cn56xxp1;
+    struct cvmx_led_clk_phase_s          cn58xx;
+    struct cvmx_led_clk_phase_s          cn58xxp1;
+} cvmx_led_clk_phase_t;
+
+
+/**
+ * cvmx_led_cylon
+ *
+ * LED_CYLON = LED CYLON Effect (should remain undocumented)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_cylon_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t rate                    : 16;      /**< LED Cylon Effect when RATE!=0
+                                                         Changes at RATE*LATCH period */
+#else
+        uint64_t rate                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_led_cylon_s              cn38xx;
+    struct cvmx_led_cylon_s              cn38xxp2;
+    struct cvmx_led_cylon_s              cn56xx;
+    struct cvmx_led_cylon_s              cn56xxp1;
+    struct cvmx_led_cylon_s              cn58xx;
+    struct cvmx_led_cylon_s              cn58xxp1;
+} cvmx_led_cylon_t;
+
+
+/**
+ * cvmx_led_dbg
+ *
+ * LED_DBG = LED Debug Port information
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_dbg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t dbg_en                  : 1;       /**< Add Debug Port Data to the LED shift chain
+                                                         Debug Data is shifted out LSB to MSB */
+#else
+        uint64_t dbg_en                  : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_led_dbg_s                cn38xx;
+    struct cvmx_led_dbg_s                cn38xxp2;
+    struct cvmx_led_dbg_s                cn56xx;
+    struct cvmx_led_dbg_s                cn56xxp1;
+    struct cvmx_led_dbg_s                cn58xx;
+    struct cvmx_led_dbg_s                cn58xxp1;
+} cvmx_led_dbg_t;
+
+
+/**
+ * cvmx_led_en
+ *
+ * LED_EN = LED Interface Enable
+ *
+ *
+ * Notes:
+ * The LED interface is comprised of a shift chain with a parallel latch.  LED
+ * data is shifted out on each fallingg edge of led_clk and then captured by
+ * led_lat.
+ * 
+ * The LED shift chain is comprised of the following...
+ * 
+ *      32  - UDD header
+ *      6x8 - per port status
+ *      17  - debug port
+ *      32  - UDD trailer
+ * 
+ * for a total of 129 bits.
+ * 
+ * UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out
+ * LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1],
+ * ... LED_UDD_DAT0[LED_UDD_CNT0].
+ * 
+ * The per port status is also variable.  Systems can control which ports send
+ * data (LED_PRT) as well as the status content (LED_PRT_FMT and
+ * LED_PRT_STATUS*).  When multiple ports are enabled, they come out in lowest
+ * port to highest port (prt0, prt1, ...).
+ * 
+ * The debug port data can also be added to the LED chain (LED_DBG).  When
+ * enabled, the debug data shifts out LSB to MSB.
+ * 
+ * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1
+ * and LED_UDD_DAT1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t en                      : 1;       /**< Enable the LED interface shift-chain */
+#else
+        uint64_t en                      : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_led_en_s                 cn38xx;
+    struct cvmx_led_en_s                 cn38xxp2;
+    struct cvmx_led_en_s                 cn56xx;
+    struct cvmx_led_en_s                 cn56xxp1;
+    struct cvmx_led_en_s                 cn58xx;
+    struct cvmx_led_en_s                 cn58xxp1;
+} cvmx_led_en_t;
+
+
+/**
+ * cvmx_led_polarity
+ *
+ * LED_POLARITY = LED Polarity
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_polarity_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t polarity                : 1;       /**< LED active polarity
+                                                         0 = active HIGH LED
+                                                         1 = active LOW LED (invert led_dat) */
+#else
+        uint64_t polarity                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_led_polarity_s           cn38xx;
+    struct cvmx_led_polarity_s           cn38xxp2;
+    struct cvmx_led_polarity_s           cn56xx;
+    struct cvmx_led_polarity_s           cn56xxp1;
+    struct cvmx_led_polarity_s           cn58xx;
+    struct cvmx_led_polarity_s           cn58xxp1;
+} cvmx_led_polarity_t;
+
+
+/**
+ * cvmx_led_prt
+ *
+ * LED_PRT = LED Port status information
+ *
+ *
+ * Notes:
+ * Note:
+ * the PRT vector enables information of the 8 RGMII ports connected to
+ * Octane.  It does not reflect the actual programmed PHY addresses.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_prt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t prt_en                  : 8;       /**< Which ports are enabled to display status
+                                                         PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0
+                                                         PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1
+                                                         Only applies when interface is in RGMII mode
+                                                         The status format is defined by LED_PRT_FMT */
+#else
+        uint64_t prt_en                  : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_led_prt_s                cn38xx;
+    struct cvmx_led_prt_s                cn38xxp2;
+    struct cvmx_led_prt_s                cn56xx;
+    struct cvmx_led_prt_s                cn56xxp1;
+    struct cvmx_led_prt_s                cn58xx;
+    struct cvmx_led_prt_s                cn58xxp1;
+} cvmx_led_prt_t;
+
+
+/**
+ * cvmx_led_prt_fmt
+ *
+ * LED_PRT_FMT = LED Port Status Infomation Format
+ *
+ *
+ * Notes:
+ * TX: RGMII TX block is sending packet data or extends on the port
+ * RX: RGMII RX block has received non-idle cycle
+ * 
+ * For short transfers, LEDs will remain on for at least one blink cycle
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_prt_fmt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t format                  : 4;       /**< Port Status Information for each enabled port in
+                                                         LED_PRT.  The formats are below
+                                                         0x0: [ LED_PRT_STATUS[0]            ]
+                                                         0x1: [ LED_PRT_STATUS[1:0]          ]
+                                                         0x2: [ LED_PRT_STATUS[3:0]          ]
+                                                         0x3: [ LED_PRT_STATUS[5:0]          ]
+                                                         0x4: [ (RX|TX), LED_PRT_STATUS[0]   ]
+                                                         0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ]
+                                                         0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ]
+                                                         0x8: [ Tx, Rx, LED_PRT_STATUS[0]    ]
+                                                         0x9: [ Tx, Rx, LED_PRT_STATUS[1:0]  ]
+                                                         0xa: [ Tx, Rx, LED_PRT_STATUS[3:0]  ] */
+#else
+        uint64_t format                  : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_led_prt_fmt_s            cn38xx;
+    struct cvmx_led_prt_fmt_s            cn38xxp2;
+    struct cvmx_led_prt_fmt_s            cn56xx;
+    struct cvmx_led_prt_fmt_s            cn56xxp1;
+    struct cvmx_led_prt_fmt_s            cn58xx;
+    struct cvmx_led_prt_fmt_s            cn58xxp1;
+} cvmx_led_prt_fmt_t;
+
+
+/**
+ * cvmx_led_prt_status#
+ *
+ * LED_PRT_STATUS = LED Port Status information
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_prt_statusx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t status                  : 6;       /**< Bits that software can set to be added to the
+                                                         LED shift chain - depending on LED_PRT_FMT
+                                                         LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0
+                                                          on interface0
+                                                         LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4
+                                                          on interface1
+                                                         Only applies when interface is in RGMII mode */
+#else
+        uint64_t status                  : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_led_prt_statusx_s        cn38xx;
+    struct cvmx_led_prt_statusx_s        cn38xxp2;
+    struct cvmx_led_prt_statusx_s        cn56xx;
+    struct cvmx_led_prt_statusx_s        cn56xxp1;
+    struct cvmx_led_prt_statusx_s        cn58xx;
+    struct cvmx_led_prt_statusx_s        cn58xxp1;
+} cvmx_led_prt_statusx_t;
+
+
+/**
+ * cvmx_led_udd_cnt#
+ *
+ * LED_UDD_CNT = LED UDD Counts
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_udd_cntx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t cnt                     : 6;       /**< Number of bits of user-defined data to include in
+                                                         the LED shift chain.  Legal values: 0-32. */
+#else
+        uint64_t cnt                     : 6;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_led_udd_cntx_s           cn38xx;
+    struct cvmx_led_udd_cntx_s           cn38xxp2;
+    struct cvmx_led_udd_cntx_s           cn56xx;
+    struct cvmx_led_udd_cntx_s           cn56xxp1;
+    struct cvmx_led_udd_cntx_s           cn58xx;
+    struct cvmx_led_udd_cntx_s           cn58xxp1;
+} cvmx_led_udd_cntx_t;
+
+
+/**
+ * cvmx_led_udd_dat#
+ *
+ * LED_UDD_DAT = User defined data (header or trailer)
+ *
+ *
+ * Notes:
+ * Bits come out LSB to MSB on the shift chain.  If LED_UDD_CNT is set to 4
+ * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2],
+ * LED_UDD_DAT[3].
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_udd_datx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t dat                     : 32;      /**< Header or trailer UDD data to be displayed on
+                                                         the LED shift chain.  Number of bits to include
+                                                         is controled by LED_UDD_CNT */
+#else
+        uint64_t dat                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_led_udd_datx_s           cn38xx;
+    struct cvmx_led_udd_datx_s           cn38xxp2;
+    struct cvmx_led_udd_datx_s           cn56xx;
+    struct cvmx_led_udd_datx_s           cn56xxp1;
+    struct cvmx_led_udd_datx_s           cn58xx;
+    struct cvmx_led_udd_datx_s           cn58xxp1;
+} cvmx_led_udd_datx_t;
+
+
+/**
+ * cvmx_led_udd_dat_clr#
+ *
+ * LED_UDD_DAT_CLR = User defined data (header or trailer)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_udd_dat_clrx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t clr                     : 32;      /**< Bitwise clear for the Header or trailer UDD data to
+                                                         be displayed on the LED shift chain. */
+#else
+        uint64_t clr                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_led_udd_dat_clrx_s       cn38xx;
+    struct cvmx_led_udd_dat_clrx_s       cn38xxp2;
+    struct cvmx_led_udd_dat_clrx_s       cn56xx;
+    struct cvmx_led_udd_dat_clrx_s       cn56xxp1;
+    struct cvmx_led_udd_dat_clrx_s       cn58xx;
+    struct cvmx_led_udd_dat_clrx_s       cn58xxp1;
+} cvmx_led_udd_dat_clrx_t;
+
+
+/**
+ * cvmx_led_udd_dat_set#
+ *
+ * LED_UDD_DAT_SET = User defined data (header or trailer)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_led_udd_dat_setx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t set                     : 32;      /**< Bitwise set for the Header or trailer UDD data to
+                                                         be displayed on the LED shift chain. */
+#else
+        uint64_t set                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_led_udd_dat_setx_s       cn38xx;
+    struct cvmx_led_udd_dat_setx_s       cn38xxp2;
+    struct cvmx_led_udd_dat_setx_s       cn56xx;
+    struct cvmx_led_udd_dat_setx_s       cn56xxp1;
+    struct cvmx_led_udd_dat_setx_s       cn58xx;
+    struct cvmx_led_udd_dat_setx_s       cn58xxp1;
+} cvmx_led_udd_dat_setx_t;
+
+
+/**
+ * cvmx_lmc#_bist_ctl
+ *
+ * Notes:
+ * This controls BiST only for the memories that operate on DCLK.  The normal, chip-wide BiST flow
+ * controls BiST for the memories that operate on ECLK.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_bist_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t start                   : 1;       /**< A 0->1 transition causes BiST to run. */
+#else
+        uint64_t start                   : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_lmcx_bist_ctl_s          cn50xx;
+    struct cvmx_lmcx_bist_ctl_s          cn52xx;
+    struct cvmx_lmcx_bist_ctl_s          cn52xxp1;
+    struct cvmx_lmcx_bist_ctl_s          cn56xx;
+    struct cvmx_lmcx_bist_ctl_s          cn56xxp1;
+} cvmx_lmcx_bist_ctl_t;
+
+
+/**
+ * cvmx_lmc#_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_bist_result_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t csrd2e                  : 1;       /**< BiST result of CSRD2E memory (0=pass, !0=fail) */
+        uint64_t csre2d                  : 1;       /**< BiST result of CSRE2D memory (0=pass, !0=fail) */
+        uint64_t mwf                     : 1;       /**< BiST result of MWF memories (0=pass, !0=fail) */
+        uint64_t mwd                     : 3;       /**< BiST result of MWD memories (0=pass, !0=fail) */
+        uint64_t mwc                     : 1;       /**< BiST result of MWC memories (0=pass, !0=fail) */
+        uint64_t mrf                     : 1;       /**< BiST result of MRF memories (0=pass, !0=fail) */
+        uint64_t mrd                     : 3;       /**< BiST result of MRD memories (0=pass, !0=fail) */
+#else
+        uint64_t mrd                     : 3;
+        uint64_t mrf                     : 1;
+        uint64_t mwc                     : 1;
+        uint64_t mwd                     : 3;
+        uint64_t mwf                     : 1;
+        uint64_t csre2d                  : 1;
+        uint64_t csrd2e                  : 1;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_lmcx_bist_result_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t mwf                     : 1;       /**< BiST result of MWF memories (0=pass, !0=fail) */
+        uint64_t mwd                     : 3;       /**< BiST result of MWD memories (0=pass, !0=fail) */
+        uint64_t mwc                     : 1;       /**< BiST result of MWC memories (0=pass, !0=fail) */
+        uint64_t mrf                     : 1;       /**< BiST result of MRF memories (0=pass, !0=fail) */
+        uint64_t mrd                     : 3;       /**< BiST result of MRD memories (0=pass, !0=fail) */
+#else
+        uint64_t mrd                     : 3;
+        uint64_t mrf                     : 1;
+        uint64_t mwc                     : 1;
+        uint64_t mwd                     : 3;
+        uint64_t mwf                     : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn50xx;
+    struct cvmx_lmcx_bist_result_s       cn52xx;
+    struct cvmx_lmcx_bist_result_s       cn52xxp1;
+    struct cvmx_lmcx_bist_result_s       cn56xx;
+    struct cvmx_lmcx_bist_result_s       cn56xxp1;
+} cvmx_lmcx_bist_result_t;
+
+
+/**
+ * cvmx_lmc#_comp_ctl
+ *
+ * LMC_COMP_CTL = LMC Compensation control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_comp_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t nctl_clk                : 4;       /**< Compensation control bits */
+        uint64_t nctl_cmd                : 4;       /**< Compensation control bits */
+        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
+        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t pctl_clk                : 4;       /**< Compensation control bits */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t pctl_clk                : 4;
+        uint64_t pctl_csr                : 4;
+        uint64_t nctl_dat                : 4;
+        uint64_t nctl_cmd                : 4;
+        uint64_t nctl_clk                : 4;
+        uint64_t nctl_csr                : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_comp_ctl_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t nctl_clk                : 4;       /**< Compensation control bits */
+        uint64_t nctl_cmd                : 4;       /**< Compensation control bits */
+        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
+        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t pctl_clk                : 4;       /**< Compensation control bits */
+        uint64_t pctl_cmd                : 4;       /**< Compensation control bits */
+        uint64_t pctl_dat                : 4;       /**< Compensation control bits */
+#else
+        uint64_t pctl_dat                : 4;
+        uint64_t pctl_cmd                : 4;
+        uint64_t pctl_clk                : 4;
+        uint64_t pctl_csr                : 4;
+        uint64_t nctl_dat                : 4;
+        uint64_t nctl_cmd                : 4;
+        uint64_t nctl_clk                : 4;
+        uint64_t nctl_csr                : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_lmcx_comp_ctl_cn30xx     cn31xx;
+    struct cvmx_lmcx_comp_ctl_cn30xx     cn38xx;
+    struct cvmx_lmcx_comp_ctl_cn30xx     cn38xxp2;
+    struct cvmx_lmcx_comp_ctl_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t reserved_20_27          : 8;
+        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
+        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t reserved_5_11           : 7;
+        uint64_t pctl_dat                : 5;       /**< Compensation control bits */
+#else
+        uint64_t pctl_dat                : 5;
+        uint64_t reserved_5_11           : 7;
+        uint64_t pctl_csr                : 4;
+        uint64_t nctl_dat                : 4;
+        uint64_t reserved_20_27          : 8;
+        uint64_t nctl_csr                : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn50xx;
+    struct cvmx_lmcx_comp_ctl_cn50xx     cn52xx;
+    struct cvmx_lmcx_comp_ctl_cn50xx     cn52xxp1;
+    struct cvmx_lmcx_comp_ctl_cn50xx     cn56xx;
+    struct cvmx_lmcx_comp_ctl_cn50xx     cn56xxp1;
+    struct cvmx_lmcx_comp_ctl_cn50xx     cn58xx;
+    struct cvmx_lmcx_comp_ctl_cn58xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t nctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t reserved_20_27          : 8;
+        uint64_t nctl_dat                : 4;       /**< Compensation control bits */
+        uint64_t pctl_csr                : 4;       /**< Compensation control bits */
+        uint64_t reserved_4_11           : 8;
+        uint64_t pctl_dat                : 4;       /**< Compensation control bits */
+#else
+        uint64_t pctl_dat                : 4;
+        uint64_t reserved_4_11           : 8;
+        uint64_t pctl_csr                : 4;
+        uint64_t nctl_dat                : 4;
+        uint64_t reserved_20_27          : 8;
+        uint64_t nctl_csr                : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn58xxp1;
+} cvmx_lmcx_comp_ctl_t;
+
+
+/**
+ * cvmx_lmc#_ctl
+ *
+ * LMC_CTL = LMC Control
+ * This register is an assortment of various control fields needed by the memory controller
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+        uint64_t slow_scf                : 1;       /**< Should be cleared to zero */
+        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+        uint64_t pll_div2                : 1;       /**< PLL Div2. */
+        uint64_t pll_bypass              : 1;       /**< PLL Bypass. */
+        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
+        uint64_t inorder_mrf             : 1;       /**< Always clear to zero */
+        uint64_t reserved_10_11          : 2;
+        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
+                                                         A non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+        uint64_t dic                     : 2;       /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+        uint64_t dic                     : 2;
+        uint64_t qs_dic                  : 2;
+        uint64_t tskw                    : 2;
+        uint64_t sil_lat                 : 2;
+        uint64_t bprch                   : 1;
+        uint64_t fprch2                  : 1;
+        uint64_t reserved_10_11          : 2;
+        uint64_t inorder_mrf             : 1;
+        uint64_t inorder_mwf             : 1;
+        uint64_t r2r_slot                : 1;
+        uint64_t rdimm_ena               : 1;
+        uint64_t pll_bypass              : 1;
+        uint64_t pll_div2                : 1;
+        uint64_t max_write_batch         : 4;
+        uint64_t xor_bank                : 1;
+        uint64_t slow_scf                : 1;
+        uint64_t ddr__pctl               : 4;
+        uint64_t ddr__nctl               : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ctl_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+        uint64_t slow_scf                : 1;       /**< 1=SCF has pass1 latency, 0=SCF has 1 cycle lower latency
+                                                         when compared to pass1 */
+        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+        uint64_t pll_div2                : 1;       /**< PLL Div2. */
+        uint64_t pll_bypass              : 1;       /**< PLL Bypass. */
+        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
+        uint64_t inorder_mrf             : 1;       /**< Always set to zero */
+        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+        uint64_t mode32b                 : 1;       /**< 32b data Path Mode
+                                                         Set to 1 if we use only 32 DQ pins
+                                                         0 for 16b DQ mode. */
+        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+        uint64_t qs_dic                  : 2;       /**< QS Drive Strength Control (DDR1):
+                                                         & DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 8 ODT
+                                                         pins based on what the masks (LMC_WODT_CTL1 & 2)
+                                                         are programmed to. LMC_DDR2_CTL->ODT_ENA
+                                                         enables Octeon to drive ODT pins for READS.
+                                                         LMC_RODT_CTL needs to be programmed based on
+                                                         the system's needs for ODT. */
+        uint64_t dic                     : 2;       /**< Drive Strength Control:
+                                                         For DDR-I/II Mode, DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization. (see DDR-I data sheet EMRS
+                                                         description)
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         For DDR-II Mode, DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+        uint64_t dic                     : 2;
+        uint64_t qs_dic                  : 2;
+        uint64_t tskw                    : 2;
+        uint64_t sil_lat                 : 2;
+        uint64_t bprch                   : 1;
+        uint64_t fprch2                  : 1;
+        uint64_t mode32b                 : 1;
+        uint64_t dreset                  : 1;
+        uint64_t inorder_mrf             : 1;
+        uint64_t inorder_mwf             : 1;
+        uint64_t r2r_slot                : 1;
+        uint64_t rdimm_ena               : 1;
+        uint64_t pll_bypass              : 1;
+        uint64_t pll_div2                : 1;
+        uint64_t max_write_batch         : 4;
+        uint64_t xor_bank                : 1;
+        uint64_t slow_scf                : 1;
+        uint64_t ddr__pctl               : 4;
+        uint64_t ddr__nctl               : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_lmcx_ctl_cn30xx          cn31xx;
+    struct cvmx_lmcx_ctl_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+        uint64_t slow_scf                : 1;       /**< 1=SCF has pass1 latency, 0=SCF has 1 cycle lower latency
+                                                         when compared to pass1
+                                                         NOTE - This bit has NO effect in PASS1 */
+        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+        uint64_t reserved_16_17          : 2;
+        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+        uint64_t inorder_mwf             : 1;       /**< When set, forces LMC_MWF (writes) into strict, in-order
+                                                         mode.  When clear, writes may be serviced out of order
+                                                         (optimized to keep multiple banks active).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use.
+                                                         NOTE: For PASS1, set as follows:
+                                                             DDR-I -> 1
+                                                             DDR-II -> 0
+                                                         For Pass2, this bit is RA0, write ignore (this feature
+                                                         is permanently disabled) */
+        uint64_t inorder_mrf             : 1;       /**< When set, forces LMC_MRF (reads) into strict, in-order
+                                                         mode.  When clear, reads may be serviced out of order
+                                                         (optimized to keep multiple banks active).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use.
+                                                         NOTE: For PASS1, set as follows:
+                                                             DDR-I -> 1
+                                                             DDR-II -> 0
+                                                         For Pass2, this bit should be written ZERO for
+                                                         DDR I & II */
+        uint64_t set_zero                : 1;       /**< Reserved. Always Set this Bit to Zero */
+        uint64_t mode128b                : 1;       /**< 128b data Path Mode
+                                                         Set to 1 if we use all 128 DQ pins
+                                                         0 for 64b DQ mode. */
+        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+        uint64_t qs_dic                  : 2;       /**< QS Drive Strength Control (DDR1):
+                                                         & DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+        uint64_t dic                     : 2;       /**< Drive Strength Control:
+                                                         For DDR-I/II Mode, DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization. (see DDR-I data sheet EMRS
+                                                         description)
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         For DDR-II Mode, DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+        uint64_t dic                     : 2;
+        uint64_t qs_dic                  : 2;
+        uint64_t tskw                    : 2;
+        uint64_t sil_lat                 : 2;
+        uint64_t bprch                   : 1;
+        uint64_t fprch2                  : 1;
+        uint64_t mode128b                : 1;
+        uint64_t set_zero                : 1;
+        uint64_t inorder_mrf             : 1;
+        uint64_t inorder_mwf             : 1;
+        uint64_t r2r_slot                : 1;
+        uint64_t rdimm_ena               : 1;
+        uint64_t reserved_16_17          : 2;
+        uint64_t max_write_batch         : 4;
+        uint64_t xor_bank                : 1;
+        uint64_t slow_scf                : 1;
+        uint64_t ddr__pctl               : 4;
+        uint64_t ddr__nctl               : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn38xx;
+    struct cvmx_lmcx_ctl_cn38xx          cn38xxp2;
+    struct cvmx_lmcx_ctl_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+        uint64_t slow_scf                : 1;       /**< Should be cleared to zero */
+        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+        uint64_t reserved_17_17          : 1;
+        uint64_t pll_bypass              : 1;       /**< PLL Bypass. */
+        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
+        uint64_t inorder_mrf             : 1;       /**< Always clear to zero */
+        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+        uint64_t mode32b                 : 1;       /**< 32b data Path Mode
+                                                         Set to 1 if we use 32 DQ pins
+                                                         0 for 16b DQ mode. */
+        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the ODT
+                                                         pins based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+        uint64_t dic                     : 2;       /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+        uint64_t dic                     : 2;
+        uint64_t qs_dic                  : 2;
+        uint64_t tskw                    : 2;
+        uint64_t sil_lat                 : 2;
+        uint64_t bprch                   : 1;
+        uint64_t fprch2                  : 1;
+        uint64_t mode32b                 : 1;
+        uint64_t dreset                  : 1;
+        uint64_t inorder_mrf             : 1;
+        uint64_t inorder_mwf             : 1;
+        uint64_t r2r_slot                : 1;
+        uint64_t rdimm_ena               : 1;
+        uint64_t pll_bypass              : 1;
+        uint64_t reserved_17_17          : 1;
+        uint64_t max_write_batch         : 4;
+        uint64_t xor_bank                : 1;
+        uint64_t slow_scf                : 1;
+        uint64_t ddr__pctl               : 4;
+        uint64_t ddr__nctl               : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn50xx;
+    struct cvmx_lmcx_ctl_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+        uint64_t slow_scf                : 1;       /**< Always clear to zero */
+        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+        uint64_t reserved_16_17          : 2;
+        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
+        uint64_t inorder_mrf             : 1;       /**< Always set to zero */
+        uint64_t dreset                  : 1;       /**< MBZ
+                                                         THIS IS OBSOLETE.  Use LMC_DLL_CTL[DRESET] instead. */
+        uint64_t mode32b                 : 1;       /**< 32b data Path Mode
+                                                         Set to 1 if we use only 32 DQ pins
+                                                         0 for 64b DQ mode. */
+        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1.
+                                                         THIS IS OBSOLETE.  Use READ_LEVEL_RANK instead. */
+        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks
+                                                         THIS IS OBSOLETE.  Use READ_LEVEL_RANK instead. */
+        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
+                                                         When in DDR2, a non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL0 & 1) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+        uint64_t dic                     : 2;       /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+        uint64_t dic                     : 2;
+        uint64_t qs_dic                  : 2;
+        uint64_t tskw                    : 2;
+        uint64_t sil_lat                 : 2;
+        uint64_t bprch                   : 1;
+        uint64_t fprch2                  : 1;
+        uint64_t mode32b                 : 1;
+        uint64_t dreset                  : 1;
+        uint64_t inorder_mrf             : 1;
+        uint64_t inorder_mwf             : 1;
+        uint64_t r2r_slot                : 1;
+        uint64_t rdimm_ena               : 1;
+        uint64_t reserved_16_17          : 2;
+        uint64_t max_write_batch         : 4;
+        uint64_t xor_bank                : 1;
+        uint64_t slow_scf                : 1;
+        uint64_t ddr__pctl               : 4;
+        uint64_t ddr__nctl               : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn52xx;
+    struct cvmx_lmcx_ctl_cn52xx          cn52xxp1;
+    struct cvmx_lmcx_ctl_cn52xx          cn56xx;
+    struct cvmx_lmcx_ctl_cn52xx          cn56xxp1;
+    struct cvmx_lmcx_ctl_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 4;       /**< DDR nctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pulldns. */
+        uint64_t ddr__pctl               : 4;       /**< DDR pctl from compensation circuit
+                                                         The encoded value on this will adjust the drive strength
+                                                         of the DDR DQ pullup. */
+        uint64_t slow_scf                : 1;       /**< Should be cleared to zero */
+        uint64_t xor_bank                : 1;       /**< If (XOR_BANK == 1), then
+                                                           bank[n:0]=address[n+7:7] ^ address[n+7+5:7+5]
+                                                         else
+                                                           bank[n:0]=address[n+7:7]
+                                                         where n=1 for a 4 bank part and n=2 for an 8 bank part */
+        uint64_t max_write_batch         : 4;       /**< Maximum number of consecutive writes to service before
+                                                         allowing reads to interrupt. */
+        uint64_t reserved_16_17          : 2;
+        uint64_t rdimm_ena               : 1;       /**< Registered DIMM Enable - When set allows the use
+                                                         of JEDEC Registered DIMMs which require Write
+                                                         data to be registered in the controller. */
+        uint64_t r2r_slot                : 1;       /**< R2R Slot Enable: When set, all read-to-read trans
+                                                         will slot an additional 1 cycle data bus bubble to
+                                                         avoid DQ/DQS bus contention. This is only a CYA bit,
+                                                         in case the "built-in" DIMM and RANK crossing logic
+                                                         which should auto-detect and perfectly slot
+                                                         read-to-reads to the same DIMM/RANK. */
+        uint64_t inorder_mwf             : 1;       /**< Reads as zero */
+        uint64_t inorder_mrf             : 1;       /**< Always clear to zero */
+        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+        uint64_t mode128b                : 1;       /**< 128b data Path Mode
+                                                         Set to 1 if we use all 128 DQ pins
+                                                         0 for 64b DQ mode. */
+        uint64_t fprch2                  : 1;       /**< Front Porch Enable: When set, the turn-off
+                                                         time for the DDR_DQ/DQS drivers is 1 dclk earlier.
+                                                         This bit should typically be set. */
+        uint64_t bprch                   : 1;       /**< Back Porch Enable: When set, the turn-on time for
+                                                         the DDR_DQ/DQS drivers is delayed an additional DCLK
+                                                         cycle. This should be set to one whenever both SILO_HC
+                                                         and SILO_QC are set. */
+        uint64_t sil_lat                 : 2;       /**< SILO Latency: On reads, determines how many additional
+                                                         dclks to wait (on top of TCL+1+TSKW) before pulling
+                                                         data out of the pad silos.
+                                                             - 00: illegal
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: illegal
+                                                         This should always be set to 1. */
+        uint64_t tskw                    : 2;       /**< This component is a representation of total BOARD
+                                                         DELAY on DQ (used in the controller to determine the
+                                                         R->W spacing to avoid DQS/DQ bus conflicts). Enter
+                                                         the largest of the per byte Board delay
+                                                             - 00: 0 dclk
+                                                             - 01: 1 dclks
+                                                             - 10: 2 dclks
+                                                             - 11: 3 dclks */
+        uint64_t qs_dic                  : 2;       /**< DDR2 Termination Resistor Setting
+                                                         A non Zero value in this register
+                                                         enables the On Die Termination (ODT) in DDR parts.
+                                                         These two bits are loaded into the RTT
+                                                         portion of the EMRS register bits A6 & A2. If DDR2's
+                                                         termination (for the memory's DQ/DQS/DM pads) is not
+                                                         desired, set it to 00. If it is, chose between
+                                                         01 for 75 ohm and 10 for 150 ohm termination.
+                                                             00 = ODT Disabled
+                                                             01 = 75 ohm Termination
+                                                             10 = 150 ohm Termination
+                                                             11 = 50 ohm Termination
+                                                         Octeon, on writes, by default, drives the 4/8 ODT
+                                                         pins (64/128b mode) based on what the masks
+                                                         (LMC_WODT_CTL) are programmed to.
+                                                         LMC_DDR2_CTL->ODT_ENA enables Octeon to drive ODT pins
+                                                         for READS. LMC_RODT_CTL needs to be programmed based
+                                                         on the system's needs for ODT. */
+        uint64_t dic                     : 2;       /**< Drive Strength Control:
+                                                         DIC[0] is
+                                                         loaded into the Extended Mode Register (EMRS) A1 bit
+                                                         during initialization.
+                                                             0 = Normal
+                                                             1 = Reduced
+                                                         DIC[1] is used to load into EMRS
+                                                         bit 10 - DQSN Enable/Disable field. By default, we
+                                                         program the DDR's to drive the DQSN also. Set it to
+                                                         1 if DQSN should be Hi-Z.
+                                                             0 - DQSN Enable
+                                                             1 - DQSN Disable */
+#else
+        uint64_t dic                     : 2;
+        uint64_t qs_dic                  : 2;
+        uint64_t tskw                    : 2;
+        uint64_t sil_lat                 : 2;
+        uint64_t bprch                   : 1;
+        uint64_t fprch2                  : 1;
+        uint64_t mode128b                : 1;
+        uint64_t dreset                  : 1;
+        uint64_t inorder_mrf             : 1;
+        uint64_t inorder_mwf             : 1;
+        uint64_t r2r_slot                : 1;
+        uint64_t rdimm_ena               : 1;
+        uint64_t reserved_16_17          : 2;
+        uint64_t max_write_batch         : 4;
+        uint64_t xor_bank                : 1;
+        uint64_t slow_scf                : 1;
+        uint64_t ddr__pctl               : 4;
+        uint64_t ddr__nctl               : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn58xx;
+    struct cvmx_lmcx_ctl_cn58xx          cn58xxp1;
+} cvmx_lmcx_ctl_t;
+
+
+/**
+ * cvmx_lmc#_ctl1
+ *
+ * LMC_CTL1 = LMC Control1
+ * This register is an assortment of various control fields needed by the memory controller
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ctl1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t ecc_adr                 : 1;       /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+        uint64_t forcewrite              : 4;       /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
+        uint64_t idlepower               : 3;       /**< Enter power-down mode after the memory controller has
+                                                         been idle for 2^(2+IDLEPOWER) cycles.  0=disabled. */
+        uint64_t sequence                : 3;       /**< Instruction sequence that is run after a 0->1 transition
+                                                         on LMC_MEM_CFG0[INIT_START].
+                                                         0=DDR2 power-up/init, 1=read-leveling
+                                                         2=self-refresh entry, 3=self-refresh exit,
+                                                         4=power-down entry, 5=power-down exit, 6=7=illegal */
+        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
+        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+        uint64_t reserved_2_7            : 6;
+        uint64_t data_layout             : 2;       /**< Logical data layout per DQ byte lane:
+                                                         In 32b mode, this setting has no effect and the data
+                                                         layout DQ[35:0] is the following:
+                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
+                                                         In 16b mode, the DQ[35:0] layouts are the following:
+                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
+                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
+                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
+                                                         where E means ecc, D means data, and 0 means unused
+                                                         (ignored on reads and written as 0 on writes) */
+#else
+        uint64_t data_layout             : 2;
+        uint64_t reserved_2_7            : 6;
+        uint64_t dcc_enable              : 1;
+        uint64_t sil_mode                : 1;
+        uint64_t sequence                : 3;
+        uint64_t idlepower               : 3;
+        uint64_t forcewrite              : 4;
+        uint64_t ecc_adr                 : 1;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } s;
+    struct cvmx_lmcx_ctl1_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t data_layout             : 2;       /**< Logical data layout per DQ byte lane:
+                                                         In 32b mode, this setting has no effect and the data
+                                                         layout DQ[35:0] is the following:
+                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
+                                                         In 16b mode, the DQ[35:0] layouts are the following:
+                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
+                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
+                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
+                                                         where E means ecc, D means data, and 0 means unused
+                                                         (ignored on reads and written as 0 on writes) */
+#else
+        uint64_t data_layout             : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn30xx;
+    struct cvmx_lmcx_ctl1_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
+        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+        uint64_t reserved_2_7            : 6;
+        uint64_t data_layout             : 2;       /**< Logical data layout per DQ byte lane:
+                                                         In 32b mode, this setting has no effect and the data
+                                                         layout DQ[35:0] is the following:
+                                                             [E[3:0], D[31:24], D[23:16], D[15:8], D[7:0]]
+                                                         In 16b mode, the DQ[35:0] layouts are the following:
+                                                         0 - [0[3:0], 0[7:0], [0[7:2], E[1:0]], D[15:8], D[7:0]]
+                                                         1 - [0[3:0], [0[7:2], E[1:0]], D[15:8], D[7:0], 0[7:0]]
+                                                         2 - [[0[1:0], E[1:0]], D[15:8], D[7:0], 0[7:0], 0[7:0]]
+                                                         where E means ecc, D means data, and 0 means unused
+                                                         (ignored on reads and written as 0 on writes) */
+#else
+        uint64_t data_layout             : 2;
+        uint64_t reserved_2_7            : 6;
+        uint64_t dcc_enable              : 1;
+        uint64_t sil_mode                : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn50xx;
+    struct cvmx_lmcx_ctl1_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t ecc_adr                 : 1;       /**< Include memory reference address in the ECC calculation
+                                                         0=disabled, 1=enabled */
+        uint64_t forcewrite              : 4;       /**< Force the oldest outstanding write to complete after
+                                                         having waited for 2^FORCEWRITE cycles.  0=disabled. */
+        uint64_t idlepower               : 3;       /**< Enter power-down mode after the memory controller has
+                                                         been idle for 2^(2+IDLEPOWER) cycles.  0=disabled. */
+        uint64_t sequence                : 3;       /**< Instruction sequence that is run after a 0->1 transition
+                                                         on LMC_MEM_CFG0[INIT_START].
+                                                         0=DDR2 power-up/init, 1=read-leveling
+                                                         2=self-refresh entry, 3=self-refresh exit,
+                                                         4=power-down entry, 5=power-down exit, 6=7=illegal */
+        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
+        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t dcc_enable              : 1;
+        uint64_t sil_mode                : 1;
+        uint64_t sequence                : 3;
+        uint64_t idlepower               : 3;
+        uint64_t forcewrite              : 4;
+        uint64_t ecc_adr                 : 1;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } cn52xx;
+    struct cvmx_lmcx_ctl1_cn52xx         cn52xxp1;
+    struct cvmx_lmcx_ctl1_cn52xx         cn56xx;
+    struct cvmx_lmcx_ctl1_cn52xx         cn56xxp1;
+    struct cvmx_lmcx_ctl1_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t sil_mode                : 1;       /**< Read Silo mode.  0=envelope, 1=self-timed. */
+        uint64_t dcc_enable              : 1;       /**< Duty Cycle Corrector Enable.
+                                                         0=disable, 1=enable
+                                                         If the memory part does not support DCC, then this bit
+                                                         must be set to 0. */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t dcc_enable              : 1;
+        uint64_t sil_mode                : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn58xx;
+    struct cvmx_lmcx_ctl1_cn58xx         cn58xxp1;
+} cvmx_lmcx_ctl1_t;
+
+
+/**
+ * cvmx_lmc#_dclk_cnt_hi
+ *
+ * LMC_DCLK_CNT_HI  = Performance Counters
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_dclk_cnt_hi_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t dclkcnt_hi              : 32;      /**< Performance Counter that counts dclks
+                                                         Upper 32-bits of a 64-bit counter. */
+#else
+        uint64_t dclkcnt_hi              : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn30xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn31xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn38xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn38xxp2;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn50xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn52xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn52xxp1;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn56xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn56xxp1;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn58xx;
+    struct cvmx_lmcx_dclk_cnt_hi_s       cn58xxp1;
+} cvmx_lmcx_dclk_cnt_hi_t;
+
+
+/**
+ * cvmx_lmc#_dclk_cnt_lo
+ *
+ * LMC_DCLK_CNT_LO  = Performance Counters
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_dclk_cnt_lo_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t dclkcnt_lo              : 32;      /**< Performance Counter that counts dclks
+                                                         Lower 32-bits of a 64-bit counter. */
+#else
+        uint64_t dclkcnt_lo              : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn30xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn31xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn38xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn38xxp2;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn50xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn52xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn52xxp1;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn56xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn56xxp1;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn58xx;
+    struct cvmx_lmcx_dclk_cnt_lo_s       cn58xxp1;
+} cvmx_lmcx_dclk_cnt_lo_t;
+
+
+/**
+ * cvmx_lmc#_dclk_ctl
+ *
+ * LMC_DCLK_CTL = LMC DCLK generation control
+ *
+ *
+ * Notes:
+ * This CSR is only relevant for LMC1. LMC0_DCLK_CTL is not used.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_dclk_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t off90_ena               : 1;       /**< 0=use global DCLK (i.e. the PLL) directly for LMC1
+                                                         1=use the 90 degree DCLK DLL to offset LMC1 DCLK */
+        uint64_t dclk90_byp              : 1;       /**< 0=90 degree DCLK DLL uses sampled delay from LMC0
+                                                         1=90 degree DCLK DLL uses DCLK90_VLU
+                                                         See DCLK90_VLU. */
+        uint64_t dclk90_ld               : 1;       /**< The 90 degree DCLK DLL samples the delay setting
+                                                         from LMC0's DLL when this field transitions 0->1 */
+        uint64_t dclk90_vlu              : 5;       /**< Manual open-loop delay setting.
+                                                         The LMC1 90 degree DCLK DLL uses DCLK90_VLU rather
+                                                         than the delay setting sampled from LMC0 when
+                                                         DCLK90_BYP=1. */
+#else
+        uint64_t dclk90_vlu              : 5;
+        uint64_t dclk90_ld               : 1;
+        uint64_t dclk90_byp              : 1;
+        uint64_t off90_ena               : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_lmcx_dclk_ctl_s          cn56xx;
+    struct cvmx_lmcx_dclk_ctl_s          cn56xxp1;
+} cvmx_lmcx_dclk_ctl_t;
+
+
+/**
+ * cvmx_lmc#_ddr2_ctl
+ *
+ * LMC_DDR2_CTL = LMC DDR2 & DLL Control Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ddr2_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bank8                   : 1;       /**< For 8 bank DDR2 parts
+                                                         1 - DDR2 parts have 8 internal banks (BA is 3 bits
+                                                         wide).
+                                                         0 - DDR2 parts have 4 internal banks (BA is 2 bits
+                                                         wide). */
+        uint64_t burst8                  : 1;       /**< 8-burst mode.
+                                                         1 - DDR data transfer happens in burst of 8
+                                                         0 - DDR data transfer happens in burst of 4
+                                                         BURST8 should be set when DDR2T is set
+                                                         to minimize the command bandwidth loss. */
+        uint64_t addlat                  : 3;       /**< Additional Latency for posted CAS
+                                                         When Posted CAS is on, this configures the additional
+                                                         latency. This should be set to
+                                                                1 .. LMC_MEM_CFG1[TRCD]-2
+                                                         (Note the implication that posted CAS should not
+                                                         be used when tRCD is two.) */
+        uint64_t pocas                   : 1;       /**< Enable the Posted CAS feature of DDR2. */
+        uint64_t bwcnt                   : 1;       /**< Bus utilization counter Clear.
+                                                         Clears the LMC_OPS_CNT_*, LMC_IFB_CNT_*, and
+                                                         LMC_DCLK_CNT_* registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+        uint64_t twr                     : 3;       /**< DDR Write Recovery time (tWR). Last Wr Brst to Pre delay
+                                                         This is not a direct encoding of the value. Its
+                                                         programmed as below per DDR2 spec. The decimal number
+                                                         on the right is RNDUP(tWR(ns) / tCYC(ns))
+                                                          TYP=15ns
+                                                             - 000: RESERVED
+                                                             - 001: 2
+                                                             - 010: 3
+                                                             - 011: 4
+                                                             - 100: 5
+                                                             - 101: 6
+                                                             - 110: 7
+                                                             - 111: 8 */
+        uint64_t silo_hc                 : 1;       /**< Delays the read sample window by a Half Cycle. */
+        uint64_t ddr_eof                 : 4;       /**< Early Fill Counter Init.
+                                                         L2 needs to know a few cycle before a fill completes so
+                                                         it can get its Control pipe started (for better overall
+                                                         performance). This counter contains  an init value which
+                                                         is a function of Eclk/Dclk ratio to account for the
+                                                         asynchronous boundary between L2 cache and the DRAM
+                                                         controller. This init value will
+                                                         determine when to safely let the L2 know that a fill
+                                                         termination is coming up.
+                                                         Set DDR_EOF according to the following rule:
+                                                         eclkFreq/dclkFreq = dclkPeriod/eclkPeriod = RATIO
+                                                                RATIO < 6/6  -> illegal
+                                                         6/6 <= RATIO < 6/5  -> DDR_EOF=3
+                                                         6/5 <= RATIO < 6/4  -> DDR_EOF=3
+                                                         6/4 <= RATIO < 6/3  -> DDR_EOF=2
+                                                         6/3 <= RATIO < 6/2  -> DDR_EOF=1
+                                                         6/2 <= RATIO < 6/1  -> DDR_EOF=0
+                                                         6/1 <= RATIO        -> DDR_EOF=0 */
+        uint64_t tfaw                    : 5;       /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                         Four Access Window time. Relevant only in DDR2 AND in
+                                                         8-bank parts.
+                                                             tFAW = 5'b0 in DDR2-4bank
+                                                             tFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                                      in DDR2-8bank */
+        uint64_t crip_mode               : 1;       /**< Cripple Mode - When set, the LMC allows only
+                                                         1 inflight transaction (.vs. 8 in normal mode).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use. */
+        uint64_t ddr2t                   : 1;       /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details.
+                                                         BURST8 should be set when DDR2T is set to minimize
+                                                         add/cmd loss. */
+        uint64_t odt_ena                 : 1;       /**< Enable Obsolete ODT on Reads
+                                                         Obsolete Read ODT wiggles DDR_ODT_* pins on reads.
+                                                         Should normally be cleared to zero.
+                                                         When this is on, the following fields must also be
+                                                         programmed:
+                                                             LMC_CTL->QS_DIC - programs the termination value
+                                                             LMC_RODT_CTL - programs the ODT I/O mask for Reads */
+        uint64_t qdll_ena                : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         DCLK init sequence will reset the DDR 90 DLL. Should
+                                                         happen at startup before any activity in DDR.
+                                                         DRESET should be asserted before and for 10 usec
+                                                         following the 0->1 transition on QDLL_ENA. */
+        uint64_t dll90_vlu               : 5;       /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+        uint64_t dll90_byp               : 1;       /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
+                                                         bypassed and the setting is defined by DLL90_VLU */
+        uint64_t rdqs                    : 1;       /**< DDR2 RDQS mode. When set, configures memory subsystem to
+                                                         use unidirectional DQS pins. RDQS/DM - Rcv & DQS - Xmit */
+        uint64_t ddr2                    : 1;       /**< Should be set */
+#else
+        uint64_t ddr2                    : 1;
+        uint64_t rdqs                    : 1;
+        uint64_t dll90_byp               : 1;
+        uint64_t dll90_vlu               : 5;
+        uint64_t qdll_ena                : 1;
+        uint64_t odt_ena                 : 1;
+        uint64_t ddr2t                   : 1;
+        uint64_t crip_mode               : 1;
+        uint64_t tfaw                    : 5;
+        uint64_t ddr_eof                 : 4;
+        uint64_t silo_hc                 : 1;
+        uint64_t twr                     : 3;
+        uint64_t bwcnt                   : 1;
+        uint64_t pocas                   : 1;
+        uint64_t addlat                  : 3;
+        uint64_t burst8                  : 1;
+        uint64_t bank8                   : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ddr2_ctl_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bank8                   : 1;       /**< For 8 bank DDR2 parts
+                                                         1 - DDR2 parts have 8 internal banks (BA is 3 bits
+                                                         wide).
+                                                         0 - DDR2 parts have 4 internal banks (BA is 2 bits
+                                                         wide). */
+        uint64_t burst8                  : 1;       /**< 8-burst mode.
+                                                         1 - DDR data transfer happens in burst of 8
+                                                         0 - DDR data transfer happens in burst of 4
+                                                         BURST8 should be set when DDR2T is set to minimize
+                                                         add/cmd bandwidth loss. */
+        uint64_t addlat                  : 3;       /**< Additional Latency for posted CAS
+                                                         When Posted CAS is on, this configures the additional
+                                                         latency. This should be set to
+                                                                1 .. LMC_MEM_CFG1[TRCD]-2
+                                                         (Note the implication that posted CAS should not
+                                                         be used when tRCD is two.) */
+        uint64_t pocas                   : 1;       /**< Enable the Posted CAS feature of DDR2. */
+        uint64_t bwcnt                   : 1;       /**< Bus utilization counter Clear.
+                                                         Clears the LMC_OPS_CNT_*, LMC_IFB_CNT_*, and
+                                                         LMC_DCLK_CNT_* registers. SW should first write this
+                                                         field to a one, then write this field to a zero to
+                                                         clear the CSR's. */
+        uint64_t twr                     : 3;       /**< DDR Write Recovery time (tWR). Last Wr Brst to Pre delay
+                                                         This is not a direct encoding of the value. Its
+                                                         programmed as below per DDR2 spec. The decimal number
+                                                         on the right is RNDUP(tWR(ns) / tCYC(ns))
+                                                          TYP=15ns
+                                                             - 000: RESERVED
+                                                             - 001: 2
+                                                             - 010: 3
+                                                             - 011: 4
+                                                             - 100: 5
+                                                             - 101: 6
+                                                             - 110-111: RESERVED */
+        uint64_t silo_hc                 : 1;       /**< Delays the read sample window by a Half Cycle. */
+        uint64_t ddr_eof                 : 4;       /**< Early Fill Counter Init.
+                                                         L2 needs to know a few cycle before a fill completes so
+                                                         it can get its Control pipe started (for better overall
+                                                         performance). This counter contains  an init value which
+                                                         is a function of Eclk/Dclk ratio to account for the
+                                                         asynchronous boundary between L2 cache and the DRAM
+                                                         controller. This init value will
+                                                         determine when to safely let the L2 know that a fill
+                                                         termination is coming up.
+                                                         DDR_EOF = RNDUP (DCLK period/Eclk Period). If the ratio
+                                                         is above 3, set DDR_EOF to 3.
+                                                             DCLK/ECLK period         DDR_EOF
+                                                                Less than 1            1
+                                                                Less than 2            2
+                                                                More than 2            3 */
+        uint64_t tfaw                    : 5;       /**< tFAW - Cycles = RNDUP[tFAW(ns)/tcyc(ns)] - 1
+                                                         Four Access Window time. Relevant only in
+                                                         8-bank parts.
+                                                             TFAW = 5'b0 for DDR2-4bank
+                                                             TFAW = RNDUP[tFAW(ns)/tcyc(ns)] - 1 in DDR2-8bank */
+        uint64_t crip_mode               : 1;       /**< Cripple Mode - When set, the LMC allows only
+                                                         1 inflight transaction (.vs. 8 in normal mode).
+                                                         This bit is ONLY to be set at power-on and
+                                                         should not be set for normal use. */
+        uint64_t ddr2t                   : 1;       /**< Turn on the DDR 2T mode. 2 cycle window for CMD and
+                                                         address. This mode helps relieve setup time pressure
+                                                         on the Address and command bus which nominally have
+                                                         a very large fanout. Please refer to Micron's tech
+                                                         note tn_47_01 titled "DDR2-533 Memory Design Guide
+                                                         for Two Dimm Unbuffered Systems" for physical details.
+                                                         BURST8 should be used when DDR2T is set to minimize
+                                                         add/cmd bandwidth loss. */
+        uint64_t odt_ena                 : 1;       /**< Enable ODT for DDR2 on Reads
+                                                         When this is on, the following fields must also be
+                                                         programmed:
+                                                             LMC_CTL->QS_DIC - programs the termination value
+                                                             LMC_RODT_CTL - programs the ODT I/O mask for writes
+                                                         Program as 0 for DDR1 mode and ODT needs to be off
+                                                         on Octeon Reads */
+        uint64_t qdll_ena                : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         erst deassertion will reset the DDR 90 DLL. Should
+                                                         happen at startup before any activity in DDR. */
+        uint64_t dll90_vlu               : 5;       /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+        uint64_t dll90_byp               : 1;       /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
+                                                         bypassed and the setting is defined by DLL90_VLU */
+        uint64_t reserved_1_1            : 1;
+        uint64_t ddr2                    : 1;       /**< DDR2 Enable: When set, configures memory subsystem for
+                                                         DDR-II SDRAMs. */
+#else
+        uint64_t ddr2                    : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t dll90_byp               : 1;
+        uint64_t dll90_vlu               : 5;
+        uint64_t qdll_ena                : 1;
+        uint64_t odt_ena                 : 1;
+        uint64_t ddr2t                   : 1;
+        uint64_t crip_mode               : 1;
+        uint64_t tfaw                    : 5;
+        uint64_t ddr_eof                 : 4;
+        uint64_t silo_hc                 : 1;
+        uint64_t twr                     : 3;
+        uint64_t bwcnt                   : 1;
+        uint64_t pocas                   : 1;
+        uint64_t addlat                  : 3;
+        uint64_t burst8                  : 1;
+        uint64_t bank8                   : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_lmcx_ddr2_ctl_cn30xx     cn31xx;
+    struct cvmx_lmcx_ddr2_ctl_s          cn38xx;
+    struct cvmx_lmcx_ddr2_ctl_s          cn38xxp2;
+    struct cvmx_lmcx_ddr2_ctl_s          cn50xx;
+    struct cvmx_lmcx_ddr2_ctl_s          cn52xx;
+    struct cvmx_lmcx_ddr2_ctl_s          cn52xxp1;
+    struct cvmx_lmcx_ddr2_ctl_s          cn56xx;
+    struct cvmx_lmcx_ddr2_ctl_s          cn56xxp1;
+    struct cvmx_lmcx_ddr2_ctl_s          cn58xx;
+    struct cvmx_lmcx_ddr2_ctl_s          cn58xxp1;
+} cvmx_lmcx_ddr2_ctl_t;
+
+
+/**
+ * cvmx_lmc#_delay_cfg
+ *
+ * LMC_DELAY_CFG = Open-loop delay line settings
+ *
+ *
+ * Notes:
+ * The DQ bits add OUTGOING delay only to dq, dqs_[p,n], cb, cbs_[p,n], dqm.  Delay is approximately
+ * 50-80ps per setting depending on process/voltage.  There is no need to add incoming delay since by
+ * default all strobe bits are delayed internally by 90 degrees (as was always the case in previous
+ * passes and past chips.
+ * 
+ * The CMD add delay to all command bits DDR_RAS, DDR_CAS, DDR_A<15:0>, DDR_BA<2:0>, DDR_n_CS<1:0>_L,
+ * DDR_WE, DDR_CKE and DDR_ODT_<7:0>. Again, delay is 50-80ps per tap.
+ * 
+ * The CLK bits add delay to all clock signals DDR_CK_<5:0>_P and DDR_CK_<5:0>_N.  Again, delay is
+ * 50-80ps per tap.
+ * 
+ * The usage scenario is the following: There is too much delay on command signals and setup on command
+ * is not met. The user can then delay the clock until setup is met.
+ * 
+ * At the same time though, dq/dqs should be delayed because there is also a DDR spec tying dqs with
+ * clock. If clock is too much delayed with respect to dqs, writes will start to fail.
+ * 
+ * This scheme should eliminate the board need of adding routing delay to clock signals to make high
+ * frequencies work.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_delay_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t dq                      : 5;       /**< Setting for DQ  delay line */
+        uint64_t cmd                     : 5;       /**< Setting for CMD delay line */
+        uint64_t clk                     : 5;       /**< Setting for CLK delay line */
+#else
+        uint64_t clk                     : 5;
+        uint64_t cmd                     : 5;
+        uint64_t dq                      : 5;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_lmcx_delay_cfg_s         cn30xx;
+    struct cvmx_lmcx_delay_cfg_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t dq                      : 4;       /**< Setting for DQ  delay line */
+        uint64_t reserved_9_9            : 1;
+        uint64_t cmd                     : 4;       /**< Setting for CMD delay line */
+        uint64_t reserved_4_4            : 1;
+        uint64_t clk                     : 4;       /**< Setting for CLK delay line */
+#else
+        uint64_t clk                     : 4;
+        uint64_t reserved_4_4            : 1;
+        uint64_t cmd                     : 4;
+        uint64_t reserved_9_9            : 1;
+        uint64_t dq                      : 4;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn38xx;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn50xx;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn52xx;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn52xxp1;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn56xx;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn56xxp1;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn58xx;
+    struct cvmx_lmcx_delay_cfg_cn38xx    cn58xxp1;
+} cvmx_lmcx_delay_cfg_t;
+
+
+/**
+ * cvmx_lmc#_dll_ctl
+ *
+ * LMC_DLL_CTL = LMC DLL control and DCLK reset
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_dll_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dreset                  : 1;       /**< Dclk domain reset.  The reset signal that is used by the
+                                                         Dclk domain is (DRESET || ECLK_RESET). */
+        uint64_t dll90_byp               : 1;       /**< DDR DLL90 Bypass: When set, the DDR90 DLL is to be
+                                                         bypassed and the setting is defined by DLL90_VLU */
+        uint64_t dll90_ena               : 1;       /**< DDR Quad DLL Enable: A 0->1 transition on this bit after
+                                                         DCLK init sequence resets the DDR 90 DLL. Should
+                                                         happen at startup before any activity in DDR. QDLL_ENA
+                                                         must not transition 1->0 outside of a DRESET sequence
+                                                         (i.e. it must remain 1 until the next DRESET).
+                                                         DRESET should be asserted before and for 10 usec
+                                                         following the 0->1 transition on QDLL_ENA. */
+        uint64_t dll90_vlu               : 5;       /**< Contains the open loop setting value for the DDR90 delay
+                                                         line. */
+#else
+        uint64_t dll90_vlu               : 5;
+        uint64_t dll90_ena               : 1;
+        uint64_t dll90_byp               : 1;
+        uint64_t dreset                  : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_lmcx_dll_ctl_s           cn52xx;
+    struct cvmx_lmcx_dll_ctl_s           cn52xxp1;
+    struct cvmx_lmcx_dll_ctl_s           cn56xx;
+    struct cvmx_lmcx_dll_ctl_s           cn56xxp1;
+} cvmx_lmcx_dll_ctl_t;
+
+
+/**
+ * cvmx_lmc#_dual_memcfg
+ *
+ * LMC_DUAL_MEMCFG = LMC Dual Memory Configuration Register
+ * 
+ * This register controls certain parameters of Dual Memory Configuration
+ *
+ * Notes:
+ * This register enables the design to have two, separate memory configurations, selected dynamically
+ * by the reference address.  Note however, that both configurations share LMC_CTL[MODE128b],
+ * LMC_CTL[XOR_BANK], LMC_MEM_CFG0[PBANK_LSB], LMC_MEM_CFG0[BUNK_ENA], and all timing parameters.
+ * In this description, "config0" refers to the normal memory configuration that is defined by the
+ * LMC_MEM_CFG0[ROW_LSB] andLMC_DDR2_CTL[BANK8] parameters and "config1" refers to the dual (or second)
+ * memory configuration that is defined by this register.
+ * 
+ * Memory config0 must be programmed for the part with the most strict timing requirements.  If a mix of
+ * 4 bank and 8 bank parts is used, then config0 must be used for the 8 bank part (because the timing
+ * requirements of tFAW and tRP are more strict for 8 bank parts than they are for 4 bank parts).
+ * 
+ * Enable mask to chip select mapping is shown below:
+ *   CS_MASK[7] -> DDR_3_CS_<1>
+ *   CS_MASK[6] -> DDR_3_CS_<0>
+ * 
+ *   CS_MASK[5] -> DDR_2_CS_<1>
+ *   CS_MASK[4] -> DDR_2_CS_<0>
+ * 
+ *   CS_MASK[3] -> DDR_1_CS_<1>
+ *   CS_MASK[2] -> DDR_1_CS_<0>
+ * 
+ *   CS_MASK[1] -> DDR_0_CS_<1>
+ *   CS_MASK[0] -> DDR_0_CS_<0>
+ * 
+ * the DIMMS are arranged in one of the following arrangements:
+ *   LMC_CTL[MODE128b] == 1                                    LMC_CTL[MODE128b] == 0
+ * 
+ *   DIMM3_RANK1  | DIMM1_RANK1  highest address               DIMM3_RANK1  highest addres
+ *   DIMM3_RANK0  | DIMM1_RANK0                                DIMM3_RANK0
+ * 
+ *   DIMM2_RANK1  | DIMM0_RANK1                                DIMM2_RANK1
+ *   DIMM2_RANK0  | DIMM0_RANK0  lowest address                DIMM2_RANK0
+ * 
+ *   data[127:64] | data_[63:0]                                DIMM1_RANK1
+ *                                                             DIMM1_RANK0
+ * 
+ *                                                             DIMM0_RANK1
+ *                                                             DIMM0_RANK0  lowest address
+ * 
+ *                                                             data_[63:0]
+ * 
+ *  DIMM n uses the pair of chip selects DDR_n_CS_<1:0>.  When LMC_CTL[BUNK_ENA] == 1, each
+ *  chip select in the pair asserts independently.  When LMC_CTL[BUNK_ENA] == 0, both chip
+ *  selects in the pair assert together.
+ * 
+ *  Programming restrictions for CS_MASK:
+ *    when LMC_CTL[BUNK_ENA] == 0, CS_MASK[2n + 1] = CS_MASK[2n], where 0 <= n <= 3
+ *    when LMC_CTL[MODE128b] == 1, CS_MASK[ n + 4] = CS_MASK[ n], where 0 <= n <= 3
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_dual_memcfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t bank8                   : 1;       /**< See LMC_DDR2_CTL[BANK8] */
+        uint64_t row_lsb                 : 3;       /**< See LMC_MEM_CFG0[ROW_LSB] */
+        uint64_t reserved_8_15           : 8;
+        uint64_t cs_mask                 : 8;       /**< Chip select mask.
+                                                         This mask corresponds to the 8 chip selects for a memory
+                                                         configuration.  Each reference address will assert one of
+                                                         the chip selects.  If that chip select has its
+                                                         corresponding CS_MASK bit set, then the "config1"
+                                                         parameters are used, otherwise the "config0" parameters
+                                                         are used.  See additional notes below. */
+#else
+        uint64_t cs_mask                 : 8;
+        uint64_t reserved_8_15           : 8;
+        uint64_t row_lsb                 : 3;
+        uint64_t bank8                   : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_lmcx_dual_memcfg_s       cn50xx;
+    struct cvmx_lmcx_dual_memcfg_s       cn52xx;
+    struct cvmx_lmcx_dual_memcfg_s       cn52xxp1;
+    struct cvmx_lmcx_dual_memcfg_s       cn56xx;
+    struct cvmx_lmcx_dual_memcfg_s       cn56xxp1;
+    struct cvmx_lmcx_dual_memcfg_s       cn58xx;
+    struct cvmx_lmcx_dual_memcfg_s       cn58xxp1;
+} cvmx_lmcx_dual_memcfg_t;
+
+
+/**
+ * cvmx_lmc#_ecc_synd
+ *
+ * LMC_ECC_SYND = MRD ECC Syndromes
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ecc_synd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t mrdsyn3                 : 8;       /**< MRD ECC Syndrome Quad3
+                                                         128b mode -  corresponds to DQ[127:64], Phase1
+                                                         64b mode  -  corresponds to DQ[127:64], Phase1, cycle1 */
+        uint64_t mrdsyn2                 : 8;       /**< MRD ECC Syndrome Quad2
+                                                         128b mode -  corresponds to DQ[63:0], Phase1
+                                                         64b mode  -  corresponds to DQ[63:0], Phase1, cycle0 */
+        uint64_t mrdsyn1                 : 8;       /**< MRD ECC Syndrome Quad1
+                                                         128b mode -  corresponds to DQ[127:64], Phase0
+                                                         64b mode  -  corresponds to DQ[127:64], Phase0, cycle1 */
+        uint64_t mrdsyn0                 : 8;       /**< MRD ECC Syndrome Quad0
+                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
+                                                         SYND0 corresponds to DQ[63:0], Phase0
+                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
+                                                         SYND0 corresponds to DQ[63:0], Phase0, cycle0 */
+#else
+        uint64_t mrdsyn0                 : 8;
+        uint64_t mrdsyn1                 : 8;
+        uint64_t mrdsyn2                 : 8;
+        uint64_t mrdsyn3                 : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ecc_synd_s          cn30xx;
+    struct cvmx_lmcx_ecc_synd_s          cn31xx;
+    struct cvmx_lmcx_ecc_synd_s          cn38xx;
+    struct cvmx_lmcx_ecc_synd_s          cn38xxp2;
+    struct cvmx_lmcx_ecc_synd_s          cn50xx;
+    struct cvmx_lmcx_ecc_synd_s          cn52xx;
+    struct cvmx_lmcx_ecc_synd_s          cn52xxp1;
+    struct cvmx_lmcx_ecc_synd_s          cn56xx;
+    struct cvmx_lmcx_ecc_synd_s          cn56xxp1;
+    struct cvmx_lmcx_ecc_synd_s          cn58xx;
+    struct cvmx_lmcx_ecc_synd_s          cn58xxp1;
+} cvmx_lmcx_ecc_synd_t;
+
+
+/**
+ * cvmx_lmc#_fadr
+ *
+ * LMC_FADR = LMC Failing Address Register (SEC/DED)
+ * 
+ * This register only captures the first transaction with ecc errors. A DBE error can
+ * over-write this register with its failing addresses. If you write
+ * LMC_MEM_CFG0->SEC_ERR/DED_ERR then it will clear the error bits and capture the
+ * next failing address.
+ * The phy mapping is a function of the num Col bits & \# row bits
+ * 
+ * If failing dimm is 2 that means the error is in the higher bits dimm.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_fadr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t fdimm                   : 2;       /**< Failing DIMM# */
+        uint64_t fbunk                   : 1;       /**< Failing Rank */
+        uint64_t fbank                   : 3;       /**< Failing Bank[2:0] */
+        uint64_t frow                    : 14;      /**< Failing Row Address[13:0] */
+        uint64_t fcol                    : 12;      /**< Failing Column Start Address[11:0]
+                                                         Represents the Failing read's starting column address
+                                                         (and not the exact column address in which the SEC/DED
+                                                         was detected) */
+#else
+        uint64_t fcol                    : 12;
+        uint64_t frow                    : 14;
+        uint64_t fbank                   : 3;
+        uint64_t fbunk                   : 1;
+        uint64_t fdimm                   : 2;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_fadr_s              cn30xx;
+    struct cvmx_lmcx_fadr_s              cn31xx;
+    struct cvmx_lmcx_fadr_s              cn38xx;
+    struct cvmx_lmcx_fadr_s              cn38xxp2;
+    struct cvmx_lmcx_fadr_s              cn50xx;
+    struct cvmx_lmcx_fadr_s              cn52xx;
+    struct cvmx_lmcx_fadr_s              cn52xxp1;
+    struct cvmx_lmcx_fadr_s              cn56xx;
+    struct cvmx_lmcx_fadr_s              cn56xxp1;
+    struct cvmx_lmcx_fadr_s              cn58xx;
+    struct cvmx_lmcx_fadr_s              cn58xxp1;
+} cvmx_lmcx_fadr_t;
+
+
+/**
+ * cvmx_lmc#_ifb_cnt_hi
+ *
+ * LMC_IFB_CNT_HI  = Performance Counters
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ifb_cnt_hi_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ifbcnt_hi               : 32;      /**< Performance Counter to measure Bus Utilization
+                                                         Upper 32-bits of 64-bit counter that increments every
+                                                         cycle there is something in the in-flight buffer. */
+#else
+        uint64_t ifbcnt_hi               : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn30xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn31xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn38xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn38xxp2;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn50xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn52xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn52xxp1;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn56xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn56xxp1;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn58xx;
+    struct cvmx_lmcx_ifb_cnt_hi_s        cn58xxp1;
+} cvmx_lmcx_ifb_cnt_hi_t;
+
+
+/**
+ * cvmx_lmc#_ifb_cnt_lo
+ *
+ * LMC_IFB_CNT_LO  = Performance Counters
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ifb_cnt_lo_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ifbcnt_lo               : 32;      /**< Performance Counter
+                                                         Low 32-bits of 64-bit counter that increments every
+                                                         cycle there is something in the in-flight buffer. */
+#else
+        uint64_t ifbcnt_lo               : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn30xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn31xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn38xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn38xxp2;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn50xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn52xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn52xxp1;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn56xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn56xxp1;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn58xx;
+    struct cvmx_lmcx_ifb_cnt_lo_s        cn58xxp1;
+} cvmx_lmcx_ifb_cnt_lo_t;
+
+
+/**
+ * cvmx_lmc#_mem_cfg0
+ *
+ * Specify the RSL base addresses for the block
+ * 
+ *                  LMC_MEM_CFG0 = LMC Memory Configuration Register0
+ * 
+ * This register controls certain parameters of  Memory Configuration
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_mem_cfg0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t reset                   : 1;       /**< Reset oneshot pulse for refresh counter,
+                                                         and LMC_OPS_CNT_*, LMC_IFB_CNT_*, and LMC_DCLK_CNT_*
+                                                         CSR's. SW should write this to a one, then re-write
+                                                         it to a zero to cause the reset. */
+        uint64_t silo_qc                 : 1;       /**< Adds a Quarter Cycle granularity to generate
+                                                         dqs pulse generation for silo.
+                                                         Combination of Silo_HC and Silo_QC gives the
+                                                         ability to position the read enable with quarter
+                                                         cycle resolution. This is applied on all the bytes
+                                                         uniformly. */
+        uint64_t bunk_ena                : 1;       /**< Bunk Enable aka RANK ena (for use with dual-rank DIMMs)
+                                                         For dual-rank DIMMs, the bunk_ena bit will enable
+                                                         the drive of the CS_N[1:0] pins based on the
+                                                         (pbank_lsb-1) address bit.
+                                                         Write 0 for SINGLE ranked DIMM's. */
+        uint64_t ded_err                 : 4;       /**< Double Error detected (DED) of Rd Data
+                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
+                                                         [25] corresponds to DQ[63:0], Phase0
+                                                         [26] corresponds to DQ[127:64], Phase0
+                                                         [27] corresponds to DQ[63:0], Phase1
+                                                         [28] corresponds to DQ[127:64], Phase1
+                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
+                                                         [25] corresponds to DQ[63:0], Phase0, cycle0
+                                                         [26] corresponds to DQ[63:0], Phase0, cycle1
+                                                         [27] corresponds to DQ[63:0], Phase1, cycle0
+                                                         [28] corresponds to DQ[63:0], Phase1, cycle1
+                                                         Write of 1 will clear the corresponding error bit */
+        uint64_t sec_err                 : 4;       /**< Single Error (corrected) of Rd Data
+                                                         In 128b mode, ecc is calulated on 1 cycle worth of data
+                                                         [21] corresponds to DQ[63:0], Phase0
+                                                         [22] corresponds to DQ[127:64], Phase0
+                                                         [23] corresponds to DQ[63:0], Phase1
+                                                         [24] corresponds to DQ[127:64], Phase1
+                                                         In 64b mode, ecc is calculated on 2 cycle worth of data
+                                                         [21] corresponds to DQ[63:0], Phase0, cycle0
+                                                         [22] corresponds to DQ[63:0], Phase0, cycle1
+                                                         [23] corresponds to DQ[63:0], Phase1, cycle0
+                                                         [24] corresponds to DQ[63:0], Phase1, cycle1
+                                                         Write of 1 will clear the corresponding error bit */
+        uint64_t intr_ded_ena            : 1;       /**< ECC Double Error Detect(DED) Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting an uncorrectable Dbl Bit ECC
+                                                         error. */
+        uint64_t intr_sec_ena            : 1;       /**< ECC Single Error Correct(SEC) Interrupt Enable bit
+                                                         When set, the memory controller raises a processor
+                                                         interrupt on detecting a correctable Single Bit ECC
+                                                         error. */
+        uint64_t tcl                     : 4;       /**< This register is not used */
+        uint64_t ref_int                 : 6;       /**< Refresh interval represented in \#of 512 dclk increments.
+                                                         Program this to RND-DN(tREFI/clkPeriod/512)
+                                                            - 000000: RESERVED
+                                                            - 000001: 1 * 512  = 512 dclks
+                                                             - ...
+                                                            - 111111: 63 * 512 = 32256 dclks */
+        uint64_t pbank_lsb               : 4;       /**< Physical Bank address select
+                                                                                 Reverting to the explanation for ROW_LSB,
+                                                                                 PBank_LSB would be Row_LSB bit + \#rowbits
+                                                                                 + \#rankbits
+                                                                                 In the 512MB DIMM Example, assuming no rank bits:
+                                                                                 pbank_lsb=mem_addr[15+13] for 64 b mode
+                                                                                          =mem_addr[16+13] for 128b mode
+                                                                                 Hence the parameter
+                                                         0000:pbank[1:0] = mem_adr[28:27]    / rank = mem_adr[26] (if bunk_ena)
+                                                         0001:pbank[1:0] = mem_adr[29:28]    / rank = mem_adr[27]      "
+                                                         0010:pbank[1:0] = mem_adr[30:29]    / rank = mem_adr[28]      "
+                                                         0011:pbank[1:0] = mem_adr[31:30]    / rank = mem_adr[29]      "
+                                                         0100:pbank[1:0] = mem_adr[32:31]    / rank = mem_adr[30]      "
+                                                         0101:pbank[1:0] = mem_adr[33:32]    / rank = mem_adr[31]      "
+                                                         0110:pbank[1:0] =[1'b0,mem_adr[33]] / rank = mem_adr[32]      "
+                                                         0111:pbank[1:0] =[2'b0]             / rank = mem_adr[33]      "
+                                                         1000-1111: RESERVED */
+        uint64_t row_lsb                 : 3;       /**< Encoding used to determine which memory address
+                                                         bit position represents the low order DDR ROW address.
+                                                         The processor's memory address[33:7] needs to be
+                                                         translated to DRAM addresses (bnk,row,col,rank and dimm)
+                                                         and that is a function of the following:
+                                                         1. \# Banks (4 or 8) - spec'd by BANK8
+                                                         2. Datapath Width(64 or 128) - MODE128b
+                                                         3. \# Ranks in a DIMM - spec'd by BUNK_ENA
+                                                         4. \# DIMM's in the system
+                                                         5. \# Column Bits of the memory part - spec'd indirectly
+                                                         by this register.
+                                                         6. \# Row Bits of the memory part - spec'd indirectly
+                                                         by the register below (PBANK_LSB).
+                                                         Illustration: For Micron's MT18HTF6472A,512MB DDR2
+                                                         Unbuffered DIMM which uses 256Mb parts (8M x 8 x 4),
+                                                         \# Banks = 4 -> 2 bits of BA
+                                                         \# Columns = 1K -> 10 bits of Col
+                                                         \# Rows = 8K -> 13 bits of Row
+                                                         Assuming that the total Data width is 128, this is how
+                                                         we arrive at row_lsb:
+                                                         Col Address starts from mem_addr[4] for 128b (16Bytes)
+                                                         dq width or from mem_addr[3] for 64b (8Bytes) dq width
+                                                         \# col + \# bank = 12. Hence row_lsb is mem_adr[15] for
+                                                         64bmode or mem_adr[16] for 128b mode. Hence row_lsb
+                                                         parameter should be set to 001 (64b) or 010 (128b).
+                                                              - 000: row_lsb = mem_adr[14]
+                                                              - 001: row_lsb = mem_adr[15]
+                                                              - 010: row_lsb = mem_adr[16]
+                                                              - 011: row_lsb = mem_adr[17]
+                                                              - 100: row_lsb = mem_adr[18]
+                                                              - 101-111:row_lsb = RESERVED */
+        uint64_t ecc_ena                 : 1;       /**< ECC Enable: When set will enable the 8b ECC
+                                                         check/correct logic. Should be 1 when used with DIMMs
+                                                         with ECC. 0, otherwise.
+                                                         When this mode is turned on, DQ[71:64] and DQ[143:137]
+                                                         on writes, will contain the ECC code generated for
+                                                         the lower 64 and upper 64 bits of data which will
+                                                         written in the memory and then later on reads, used
+                                                         to check for Single bit error (which will be auto-
+                                                         corrected) and Double Bit error (which will be
+                                                         reported). When not turned on, DQ[71:64] and DQ[143:137]
+                                                         are driven to 0.  Please refer to SEC_ERR, DED_ERR,
+                                                         LMC_FADR, and LMC_ECC_SYND registers
+                                                         for diagnostics information when there is an error. */
+        uint64_t init_start              : 1;       /**< A 0->1 transition starts the DDR memory initialization
+                                                         sequence. */
+#else
+        uint64_t init_start              : 1;
+        uint64_t ecc_ena                 : 1;
+        uint64_t row_lsb                 : 3;
+        uint64_t pbank_lsb               : 4;
+        uint64_t ref_int                 : 6;
+        uint64_t tcl                     : 4;
+        uint64_t intr_sec_ena            : 1;
+        uint64_t intr_ded_ena            : 1;
+        uint64_t sec_err                 : 4;
+        uint64_t ded_err                 : 4;
+        uint64_t bunk_ena                : 1;
+        uint64_t silo_qc                 : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_mem_cfg0_s          cn30xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn31xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn38xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn38xxp2;
+    struct cvmx_lmcx_mem_cfg0_s          cn50xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn52xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn52xxp1;
+    struct cvmx_lmcx_mem_cfg0_s          cn56xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn56xxp1;
+    struct cvmx_lmcx_mem_cfg0_s          cn58xx;
+    struct cvmx_lmcx_mem_cfg0_s          cn58xxp1;
+} cvmx_lmcx_mem_cfg0_t;
+
+
+/**
+ * cvmx_lmc#_mem_cfg1
+ *
+ * LMC_MEM_CFG1 = LMC Memory Configuration Register1
+ * 
+ * This register controls the External Memory Configuration Timing Parameters. Please refer to the
+ * appropriate DDR part spec from your memory vendor for the various values in this CSR.
+ * The details of each of these timing parameters can be found in the JEDEC spec or the vendor
+ * spec of the memory parts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_mem_cfg1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t comp_bypass             : 1;       /**< Compensation bypass. */
+        uint64_t trrd                    : 3;       /**< tRRD cycles: ACT-ACT timing parameter for different
+                                                         banks. (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,200MHz=3)
+                                                         For DDR2, TYP=7.5ns
+                                                            - 000: RESERVED
+                                                            - 001: 1 tCYC
+                                                            - 010: 2 tCYC
+                                                            - 011: 3 tCYC
+                                                            - 100: 4 tCYC
+                                                            - 101: 5 tCYC
+                                                            - 110: 6 tCYC
+                                                            - 111: 7 tCYC */
+        uint64_t caslat                  : 3;       /**< CAS Latency Encoding which is loaded into each DDR
+                                                         SDRAM device (MRS[6:4]) upon power-up (INIT_START=1).
+                                                         (Represented in tCYC cycles == 1 dclks)
+                                                            000 RESERVED
+                                                            001 RESERVED
+                                                            010 2.0 tCYC
+                                                            011 3.0 tCYC
+                                                            100 4.0 tCYC
+                                                            101 5.0 tCYC
+                                                            110 6.0 tCYC
+                                                            111 RESERVED
+                                                         eg). The parameters TSKW, SILO_HC, and SILO_QC can
+                                                         account for 1/4 cycle granularity in board/etch delays. */
+        uint64_t tmrd                    : 3;       /**< tMRD Cycles
+                                                         (Represented in dclk tCYC)
+                                                         For DDR2, its TYP 2*tCYC)
+                                                             - 000: RESERVED
+                                                             - 001: 1
+                                                             - 010: 2
+                                                             - 011: 3
+                                                             - 100: 4
+                                                             - 101-111: RESERVED */
+        uint64_t trfc                    : 5;       /**< 1/4 tRFC Cycles = RNDUP[tRFC(ns)/4*tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclks)
+                                                         For 2Gb, DDR2-667 parts, typ=195ns
+                                                         (TRFC = 195/3/4 = 5'd17 = 0x11)
+                                                             - 00000-00001: RESERVED
+                                                             - 00010: 8
+                                                             - 00011: 12
+                                                             - 00100: 16
+                                                             - ...
+                                                             - 11110: 120
+                                                             - 11111: 124 */
+        uint64_t trp                     : 4;       /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         When using parts with 8 banks (LMC_DDR2_CTL->BANK8
+                                                         is 1), load tRP cycles + 1 into this register. */
+        uint64_t twtr                    : 4;       /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
+                                                         Last Wr Data to Rd Command time.
+                                                         (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6, for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1000-1111: RESERVED */
+        uint64_t trcd                    : 4;       /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 1001: 9
+                                                             - 1010-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+        uint64_t tras                    : 5;       /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1 dclk)
+                                                             - 00000-0001: RESERVED
+                                                             - 00010: 2
+                                                             - ...
+                                                             - 11111: 31 */
+#else
+        uint64_t tras                    : 5;
+        uint64_t trcd                    : 4;
+        uint64_t twtr                    : 4;
+        uint64_t trp                     : 4;
+        uint64_t trfc                    : 5;
+        uint64_t tmrd                    : 3;
+        uint64_t caslat                  : 3;
+        uint64_t trrd                    : 3;
+        uint64_t comp_bypass             : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_mem_cfg1_s          cn30xx;
+    struct cvmx_lmcx_mem_cfg1_s          cn31xx;
+    struct cvmx_lmcx_mem_cfg1_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t trrd                    : 3;       /**< tRRD cycles: ACT-ACT timing parameter for different
+                                                         banks. (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,200MHz=3)
+                                                         For DDR2, TYP=7.5ns
+                                                            - 000: RESERVED
+                                                            - 001: 1 tCYC
+                                                            - 010: 2 tCYC
+                                                            - 011: 3 tCYC
+                                                            - 100: 4 tCYC
+                                                            - 101: 5 tCYC
+                                                            - 110-111: RESERVED */
+        uint64_t caslat                  : 3;       /**< CAS Latency Encoding which is loaded into each DDR
+                                                         SDRAM device (MRS[6:4]) upon power-up (INIT_START=1).
+                                                         (Represented in tCYC cycles == 1 dclks)
+                                                            000 RESERVED
+                                                            001 RESERVED
+                                                            010 2.0 tCYC
+                                                            011 3.0 tCYC
+                                                            100 4.0 tCYC
+                                                            101 5.0 tCYC
+                                                            110 6.0 tCYC (DDR2)
+                                                                2.5 tCYC (DDR1)
+                                                            111 RESERVED
+                                                         eg). The parameters TSKW, SILO_HC, and SILO_QC can
+                                                         account for 1/4 cycle granularity in board/etch delays. */
+        uint64_t tmrd                    : 3;       /**< tMRD Cycles
+                                                         (Represented in dclk tCYC)
+                                                         For DDR2, its TYP 2*tCYC)
+                                                             - 000: RESERVED
+                                                             - 001: 1
+                                                             - 010: 2
+                                                             - 011: 3
+                                                             - 100: 4
+                                                             - 101-111: RESERVED */
+        uint64_t trfc                    : 5;       /**< 1/4 tRFC Cycles = RNDUP[tRFC(ns)/4*tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclks)
+                                                         For DDR-I, the following encodings are used
+                                                         TYP=70ns (133MHz - 3; 333MHz - 6)
+                                                         For 2Gb, DDR2-667 parts, typ=195ns
+                                                         (TRFC = 195/3/4 = 5'd17 = 0x11)
+                                                             - 00000-00001: RESERVED
+                                                             - 00010: 8
+                                                             - 00011: 12
+                                                             - 00100: 16
+                                                             - ...
+                                                             - 11110: 120
+                                                             - 11111: 124 */
+        uint64_t trp                     : 4;       /**< tRP Cycles = RNDUP[tRP(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1000-1111: RESERVED
+                                                         When using parts with 8 banks (LMC_DDR2_CTL->BANK8
+                                                         is 1), load tRP cycles + 1 into this register. */
+        uint64_t twtr                    : 4;       /**< tWTR Cycles = RNDUP[tWTR(ns)/tcyc(ns)]
+                                                         Last Wr Data to Rd Command time.
+                                                         (Represented in tCYC cycles == 1dclks)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6, for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 1
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1000-1111: RESERVED */
+        uint64_t trcd                    : 4;       /**< tRCD Cycles = RNDUP[tRCD(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1dclk)
+                                                         TYP=15ns (66MHz=1,167MHz=3,400MHz=6 for TYP)
+                                                             - 0000: RESERVED
+                                                             - 0001: 2 (2 is the smallest value allowed)
+                                                             - 0002: 2
+                                                             - ...
+                                                             - 0111: 7
+                                                             - 1110-1111: RESERVED
+                                                         In 2T mode, make this register TRCD-1, not going
+                                                         below 2. */
+        uint64_t tras                    : 5;       /**< tRAS Cycles = RNDUP[tRAS(ns)/tcyc(ns)]
+                                                         (Represented in tCYC cycles == 1 dclk)
+                                                         For DDR-I mode:
+                                                         TYP=45ns (66MHz=3,167MHz=8,400MHz=18
+                                                             - 00000-0001: RESERVED
+                                                             - 00010: 2
+                                                             - ...
+                                                             - 10100: 20
+                                                             - 10101-11111: RESERVED */
+#else
+        uint64_t tras                    : 5;
+        uint64_t trcd                    : 4;
+        uint64_t twtr                    : 4;
+        uint64_t trp                     : 4;
+        uint64_t trfc                    : 5;
+        uint64_t tmrd                    : 3;
+        uint64_t caslat                  : 3;
+        uint64_t trrd                    : 3;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } cn38xx;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn38xxp2;
+    struct cvmx_lmcx_mem_cfg1_s          cn50xx;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn52xx;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn52xxp1;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn56xx;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn56xxp1;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn58xx;
+    struct cvmx_lmcx_mem_cfg1_cn38xx     cn58xxp1;
+} cvmx_lmcx_mem_cfg1_t;
+
+
+/**
+ * cvmx_lmc#_nxm
+ *
+ * LMC_NXM = LMC non-existent memory
+ *
+ *
+ * Notes:
+ * This CSR was introduced in pass2.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_nxm_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t cs_mask                 : 8;       /**< Chip select mask.
+                                                         This mask corresponds to the 8 chip selects for a memory
+                                                         configuration.  If LMC_MEM_CFG0[BUNK_ENA]==0 then this
+                                                         mask must be set in pairs because each reference address
+                                                         will assert a pair of chip selects.  If the chip
+                                                         select(s) have a corresponding CS_MASK bit set, then the
+                                                         reference is to non-existent memory.  LMC will alias the
+                                                         reference to use the lowest, legal chip select(s) in
+                                                         that case. */
+#else
+        uint64_t cs_mask                 : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_lmcx_nxm_s               cn52xx;
+    struct cvmx_lmcx_nxm_s               cn56xx;
+    struct cvmx_lmcx_nxm_s               cn58xx;
+} cvmx_lmcx_nxm_t;
+
+
+/**
+ * cvmx_lmc#_ops_cnt_hi
+ *
+ * LMC_OPS_CNT_HI  = Performance Counters
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ops_cnt_hi_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t opscnt_hi               : 32;      /**< Performance Counter to measure Bus Utilization
+                                                         Upper 32-bits of 64-bit counter
+                                                           DRAM bus utilization = LMC_OPS_CNT_* /LMC_DCLK_CNT_* */
+#else
+        uint64_t opscnt_hi               : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn30xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn31xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn38xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn38xxp2;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn50xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn52xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn52xxp1;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn56xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn56xxp1;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn58xx;
+    struct cvmx_lmcx_ops_cnt_hi_s        cn58xxp1;
+} cvmx_lmcx_ops_cnt_hi_t;
+
+
+/**
+ * cvmx_lmc#_ops_cnt_lo
+ *
+ * LMC_OPS_CNT_LO  = Performance Counters
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_ops_cnt_lo_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t opscnt_lo               : 32;      /**< Performance Counter
+                                                         Low 32-bits of 64-bit counter
+                                                           DRAM bus utilization = LMC_OPS_CNT_* /LMC_DCLK_CNT_* */
+#else
+        uint64_t opscnt_lo               : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn30xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn31xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn38xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn38xxp2;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn50xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn52xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn52xxp1;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn56xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn56xxp1;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn58xx;
+    struct cvmx_lmcx_ops_cnt_lo_s        cn58xxp1;
+} cvmx_lmcx_ops_cnt_lo_t;
+
+
+/**
+ * cvmx_lmc#_pll_bwctl
+ *
+ * LMC_PLL_BWCTL  = DDR PLL Bandwidth Control Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_pll_bwctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t bwupd                   : 1;       /**< Load this Bandwidth Register value into the PLL */
+        uint64_t bwctl                   : 4;       /**< Bandwidth Control Register for DDR PLL */
+#else
+        uint64_t bwctl                   : 4;
+        uint64_t bwupd                   : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_lmcx_pll_bwctl_s         cn30xx;
+    struct cvmx_lmcx_pll_bwctl_s         cn31xx;
+    struct cvmx_lmcx_pll_bwctl_s         cn38xx;
+    struct cvmx_lmcx_pll_bwctl_s         cn38xxp2;
+} cvmx_lmcx_pll_bwctl_t;
+
+
+/**
+ * cvmx_lmc#_pll_ctl
+ *
+ * LMC_PLL_CTL = LMC pll control
+ *
+ *
+ * Notes:
+ * This CSR is only relevant for LMC0. LMC1_PLL_CTL is not used.
+ * 
+ * Exactly one of EN2, EN4, EN6, EN8, EN12, EN16 must be set.
+ * 
+ * The resultant DDR_CK frequency is the DDR2_REF_CLK
+ * frequency multiplied by:
+ * 
+ *     (CLKF + 1) / ((CLKR + 1) * EN(2,4,6,8,12,16))
+ * 
+ * The PLL frequency, which is:
+ * 
+ *     (DDR2_REF_CLK freq) * ((CLKF + 1) / (CLKR + 1))
+ * 
+ * must reside between 1.2 and 2.5 GHz. A faster PLL frequency is desirable if there is a choice.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_pll_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_30_63          : 34;
+        uint64_t bypass                  : 1;       /**< PLL Bypass */
+        uint64_t fasten_n                : 1;       /**< Should be set, especially when CLKF > ~80 */
+        uint64_t div_reset               : 1;       /**< Analog pll divider reset
+                                                         De-assert at least 500*(CLKR+1) reference clock
+                                                         cycles following RESET_N de-assertion. */
+        uint64_t reset_n                 : 1;       /**< Analog pll reset
+                                                         De-assert at least 5 usec after CLKF, CLKR,
+                                                         and EN* are set up. */
+        uint64_t clkf                    : 12;      /**< Multiply reference by CLKF + 1
+                                                         CLKF must be <= 128 */
+        uint64_t clkr                    : 6;       /**< Divide reference by CLKR + 1 */
+        uint64_t reserved_6_7            : 2;
+        uint64_t en16                    : 1;       /**< Divide output by 16 */
+        uint64_t en12                    : 1;       /**< Divide output by 12 */
+        uint64_t en8                     : 1;       /**< Divide output by 8 */
+        uint64_t en6                     : 1;       /**< Divide output by 6 */
+        uint64_t en4                     : 1;       /**< Divide output by 4 */
+        uint64_t en2                     : 1;       /**< Divide output by 2 */
+#else
+        uint64_t en2                     : 1;
+        uint64_t en4                     : 1;
+        uint64_t en6                     : 1;
+        uint64_t en8                     : 1;
+        uint64_t en12                    : 1;
+        uint64_t en16                    : 1;
+        uint64_t reserved_6_7            : 2;
+        uint64_t clkr                    : 6;
+        uint64_t clkf                    : 12;
+        uint64_t reset_n                 : 1;
+        uint64_t div_reset               : 1;
+        uint64_t fasten_n                : 1;
+        uint64_t bypass                  : 1;
+        uint64_t reserved_30_63          : 34;
+#endif
+    } s;
+    struct cvmx_lmcx_pll_ctl_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t fasten_n                : 1;       /**< Should be set, especially when CLKF > ~80 */
+        uint64_t div_reset               : 1;       /**< Analog pll divider reset
+                                                         De-assert at least 500*(CLKR+1) reference clock
+                                                         cycles following RESET_N de-assertion. */
+        uint64_t reset_n                 : 1;       /**< Analog pll reset
+                                                         De-assert at least 5 usec after CLKF, CLKR,
+                                                         and EN* are set up. */
+        uint64_t clkf                    : 12;      /**< Multiply reference by CLKF + 1
+                                                         CLKF must be <= 256 */
+        uint64_t clkr                    : 6;       /**< Divide reference by CLKR + 1 */
+        uint64_t reserved_6_7            : 2;
+        uint64_t en16                    : 1;       /**< Divide output by 16 */
+        uint64_t en12                    : 1;       /**< Divide output by 12 */
+        uint64_t en8                     : 1;       /**< Divide output by 8 */
+        uint64_t en6                     : 1;       /**< Divide output by 6 */
+        uint64_t en4                     : 1;       /**< Divide output by 4 */
+        uint64_t en2                     : 1;       /**< Divide output by 2 */
+#else
+        uint64_t en2                     : 1;
+        uint64_t en4                     : 1;
+        uint64_t en6                     : 1;
+        uint64_t en8                     : 1;
+        uint64_t en12                    : 1;
+        uint64_t en16                    : 1;
+        uint64_t reserved_6_7            : 2;
+        uint64_t clkr                    : 6;
+        uint64_t clkf                    : 12;
+        uint64_t reset_n                 : 1;
+        uint64_t div_reset               : 1;
+        uint64_t fasten_n                : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn50xx;
+    struct cvmx_lmcx_pll_ctl_s           cn52xx;
+    struct cvmx_lmcx_pll_ctl_s           cn52xxp1;
+    struct cvmx_lmcx_pll_ctl_cn50xx      cn56xx;
+    struct cvmx_lmcx_pll_ctl_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t div_reset               : 1;       /**< Analog pll divider reset
+                                                         De-assert at least 500*(CLKR+1) reference clock
+                                                         cycles following RESET_N de-assertion. */
+        uint64_t reset_n                 : 1;       /**< Analog pll reset
+                                                         De-assert at least 5 usec after CLKF, CLKR,
+                                                         and EN* are set up. */
+        uint64_t clkf                    : 12;      /**< Multiply reference by CLKF + 1
+                                                         CLKF must be <= 128 */
+        uint64_t clkr                    : 6;       /**< Divide reference by CLKR + 1 */
+        uint64_t reserved_6_7            : 2;
+        uint64_t en16                    : 1;       /**< Divide output by 16 */
+        uint64_t en12                    : 1;       /**< Divide output by 12 */
+        uint64_t en8                     : 1;       /**< Divide output by 8 */
+        uint64_t en6                     : 1;       /**< Divide output by 6 */
+        uint64_t en4                     : 1;       /**< Divide output by 4 */
+        uint64_t en2                     : 1;       /**< Divide output by 2 */
+#else
+        uint64_t en2                     : 1;
+        uint64_t en4                     : 1;
+        uint64_t en6                     : 1;
+        uint64_t en8                     : 1;
+        uint64_t en12                    : 1;
+        uint64_t en16                    : 1;
+        uint64_t reserved_6_7            : 2;
+        uint64_t clkr                    : 6;
+        uint64_t clkf                    : 12;
+        uint64_t reset_n                 : 1;
+        uint64_t div_reset               : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn56xxp1;
+    struct cvmx_lmcx_pll_ctl_cn56xxp1    cn58xx;
+    struct cvmx_lmcx_pll_ctl_cn56xxp1    cn58xxp1;
+} cvmx_lmcx_pll_ctl_t;
+
+
+/**
+ * cvmx_lmc#_pll_status
+ *
+ * LMC_PLL_STATUS = LMC pll status
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_pll_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ddr__nctl               : 5;       /**< DDR nctl from compensation circuit */
+        uint64_t ddr__pctl               : 5;       /**< DDR pctl from compensation circuit */
+        uint64_t reserved_2_21           : 20;
+        uint64_t rfslip                  : 1;       /**< Reference clock slip */
+        uint64_t fbslip                  : 1;       /**< Feedback clock slip */
+#else
+        uint64_t fbslip                  : 1;
+        uint64_t rfslip                  : 1;
+        uint64_t reserved_2_21           : 20;
+        uint64_t ddr__pctl               : 5;
+        uint64_t ddr__nctl               : 5;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_pll_status_s        cn50xx;
+    struct cvmx_lmcx_pll_status_s        cn52xx;
+    struct cvmx_lmcx_pll_status_s        cn52xxp1;
+    struct cvmx_lmcx_pll_status_s        cn56xx;
+    struct cvmx_lmcx_pll_status_s        cn56xxp1;
+    struct cvmx_lmcx_pll_status_s        cn58xx;
+    struct cvmx_lmcx_pll_status_cn58xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t rfslip                  : 1;       /**< Reference clock slip */
+        uint64_t fbslip                  : 1;       /**< Feedback clock slip */
+#else
+        uint64_t fbslip                  : 1;
+        uint64_t rfslip                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn58xxp1;
+} cvmx_lmcx_pll_status_t;
+
+
+/**
+ * cvmx_lmc#_read_level_ctl
+ *
+ * Notes:
+ * The HW writes and reads the cache block selected by ROW, COL, BNK and the rank as part of a read-leveling sequence for a rank.
+ * A cache block write is 16 72-bit words. PATTERN selects the write value. For the first 8
+ * words, the write value is the bit PATTERN<i> duplicated into a 72-bit vector. The write value of
+ * the last 8 words is the inverse of the write value of the first 8 words.
+ * See LMC*_READ_LEVEL_RANK*.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_read_level_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t rankmask                : 4;       /**< Selects ranks to be leveled
+                                                         to read-level rank i, set RANKMASK<i> */
+        uint64_t pattern                 : 8;       /**< All DQ driven to PATTERN[burst], 0 <= burst <= 7
+                                                         All DQ driven to ~PATTERN[burst-8], 8 <= burst <= 15 */
+        uint64_t row                     : 16;      /**< Row    address used to write/read data pattern */
+        uint64_t col                     : 12;      /**< Column address used to write/read data pattern */
+        uint64_t reserved_3_3            : 1;
+        uint64_t bnk                     : 3;       /**< Bank   address used to write/read data pattern */
+#else
+        uint64_t bnk                     : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t col                     : 12;
+        uint64_t row                     : 16;
+        uint64_t pattern                 : 8;
+        uint64_t rankmask                : 4;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_lmcx_read_level_ctl_s    cn52xx;
+    struct cvmx_lmcx_read_level_ctl_s    cn52xxp1;
+    struct cvmx_lmcx_read_level_ctl_s    cn56xx;
+    struct cvmx_lmcx_read_level_ctl_s    cn56xxp1;
+} cvmx_lmcx_read_level_ctl_t;
+
+
+/**
+ * cvmx_lmc#_read_level_dbg
+ *
+ * Notes:
+ * A given read of LMC*_READ_LEVEL_DBG returns the read-leveling pass/fail results for all possible
+ * delay settings (i.e. the BITMASK) for only one byte in the last rank that the HW read-leveled.
+ * LMC*_READ_LEVEL_DBG[BYTE] selects the particular byte.
+ * To get these pass/fail results for another different rank, you must run the hardware read-leveling
+ * again. For example, it is possible to get the BITMASK results for every byte of every rank
+ * if you run read-leveling separately for each rank, probing LMC*_READ_LEVEL_DBG between each
+ * read-leveling.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_read_level_dbg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bitmask                 : 16;      /**< Bitmask generated during deskew settings sweep
+                                                         BITMASK[n]=0 means deskew setting n failed
+                                                         BITMASK[n]=1 means deskew setting n passed
+                                                         for 0 <= n <= 15 */
+        uint64_t reserved_4_15           : 12;
+        uint64_t byte                    : 4;       /**< 0 <= BYTE <= 8 */
+#else
+        uint64_t byte                    : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t bitmask                 : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_read_level_dbg_s    cn52xx;
+    struct cvmx_lmcx_read_level_dbg_s    cn52xxp1;
+    struct cvmx_lmcx_read_level_dbg_s    cn56xx;
+    struct cvmx_lmcx_read_level_dbg_s    cn56xxp1;
+} cvmx_lmcx_read_level_dbg_t;
+
+
+/**
+ * cvmx_lmc#_read_level_rank#
+ *
+ * Notes:
+ * This is four CSRs per LMC, one per each rank.
+ * Each CSR is written by HW during a read-leveling sequence for the rank. (HW sets STATUS==3 after HW read-leveling completes for the rank.)
+ * Each CSR may also be written by SW, but not while a read-leveling sequence is in progress. (HW sets STATUS==1 after a CSR write.)
+ * Deskew setting is measured in units of 1/4 DCLK, so the above BYTE* values can range over 4 DCLKs.
+ * SW initiates a HW read-leveling sequence by programming LMC*_READ_LEVEL_CTL and writing INIT_START=1 with SEQUENCE=1.
+ * See LMC*_READ_LEVEL_CTL.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_read_level_rankx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t status                  : 2;       /**< Indicates status of the read-levelling and where
+                                                         the BYTE* programmings in <35:0> came from:
+                                                         0 = BYTE* values are their reset value
+                                                         1 = BYTE* values were set via a CSR write to this register
+                                                         2 = read-leveling sequence currently in progress (BYTE* values are unpredictable)
+                                                         3 = BYTE* values came from a complete read-leveling sequence */
+        uint64_t byte8                   : 4;       /**< Deskew setting */
+        uint64_t byte7                   : 4;       /**< Deskew setting */
+        uint64_t byte6                   : 4;       /**< Deskew setting */
+        uint64_t byte5                   : 4;       /**< Deskew setting */
+        uint64_t byte4                   : 4;       /**< Deskew setting */
+        uint64_t byte3                   : 4;       /**< Deskew setting */
+        uint64_t byte2                   : 4;       /**< Deskew setting */
+        uint64_t byte1                   : 4;       /**< Deskew setting */
+        uint64_t byte0                   : 4;       /**< Deskew setting */
+#else
+        uint64_t byte0                   : 4;
+        uint64_t byte1                   : 4;
+        uint64_t byte2                   : 4;
+        uint64_t byte3                   : 4;
+        uint64_t byte4                   : 4;
+        uint64_t byte5                   : 4;
+        uint64_t byte6                   : 4;
+        uint64_t byte7                   : 4;
+        uint64_t byte8                   : 4;
+        uint64_t status                  : 2;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_lmcx_read_level_rankx_s  cn52xx;
+    struct cvmx_lmcx_read_level_rankx_s  cn52xxp1;
+    struct cvmx_lmcx_read_level_rankx_s  cn56xx;
+    struct cvmx_lmcx_read_level_rankx_s  cn56xxp1;
+} cvmx_lmcx_read_level_rankx_t;
+
+
+/**
+ * cvmx_lmc#_rodt_comp_ctl
+ *
+ * LMC_RODT_COMP_CTL = LMC Compensation control
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_rodt_comp_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t enable                  : 1;       /**< 0=not enabled, 1=enable */
+        uint64_t reserved_12_15          : 4;
+        uint64_t nctl                    : 4;       /**< Compensation control bits */
+        uint64_t reserved_5_7            : 3;
+        uint64_t pctl                    : 5;       /**< Compensation control bits */
+#else
+        uint64_t pctl                    : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t nctl                    : 4;
+        uint64_t reserved_12_15          : 4;
+        uint64_t enable                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn50xx;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn52xx;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn52xxp1;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn56xx;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn56xxp1;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn58xx;
+    struct cvmx_lmcx_rodt_comp_ctl_s     cn58xxp1;
+} cvmx_lmcx_rodt_comp_ctl_t;
+
+
+/**
+ * cvmx_lmc#_rodt_ctl
+ *
+ * LMC_RODT_CTL = Obsolete LMC Read OnDieTermination control
+ * See the description in LMC_WODT_CTL1. On Reads, Octeon only supports turning on ODT's in
+ * the lower 2 DIMM's with the masks as below.
+ *
+ * Notes:
+ * When a given RANK in position N is selected, the RODT _HI and _LO masks for that position are used.
+ * Mask[3:0] is used for RODT control of the RANKs in positions 3, 2, 1, and 0, respectively.
+ * In  64b mode, DIMMs are assumed to be ordered in the following order:
+ *  position 3: [unused        , DIMM1_RANK1_LO]
+ *  position 2: [unused        , DIMM1_RANK0_LO]
+ *  position 1: [unused        , DIMM0_RANK1_LO]
+ *  position 0: [unused        , DIMM0_RANK0_LO]
+ * In 128b mode, DIMMs are assumed to be ordered in the following order:
+ *  position 3: [DIMM3_RANK1_HI, DIMM1_RANK1_LO]
+ *  position 2: [DIMM3_RANK0_HI, DIMM1_RANK0_LO]
+ *  position 1: [DIMM2_RANK1_HI, DIMM0_RANK1_LO]
+ *  position 0: [DIMM2_RANK0_HI, DIMM0_RANK0_LO]
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_rodt_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rodt_hi3                : 4;       /**< Read ODT mask for position 3, data[127:64] */
+        uint64_t rodt_hi2                : 4;       /**< Read ODT mask for position 2, data[127:64] */
+        uint64_t rodt_hi1                : 4;       /**< Read ODT mask for position 1, data[127:64] */
+        uint64_t rodt_hi0                : 4;       /**< Read ODT mask for position 0, data[127:64] */
+        uint64_t rodt_lo3                : 4;       /**< Read ODT mask for position 3, data[ 63: 0] */
+        uint64_t rodt_lo2                : 4;       /**< Read ODT mask for position 2, data[ 63: 0] */
+        uint64_t rodt_lo1                : 4;       /**< Read ODT mask for position 1, data[ 63: 0] */
+        uint64_t rodt_lo0                : 4;       /**< Read ODT mask for position 0, data[ 63: 0] */
+#else
+        uint64_t rodt_lo0                : 4;
+        uint64_t rodt_lo1                : 4;
+        uint64_t rodt_lo2                : 4;
+        uint64_t rodt_lo3                : 4;
+        uint64_t rodt_hi0                : 4;
+        uint64_t rodt_hi1                : 4;
+        uint64_t rodt_hi2                : 4;
+        uint64_t rodt_hi3                : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_rodt_ctl_s          cn30xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn31xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn38xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn38xxp2;
+    struct cvmx_lmcx_rodt_ctl_s          cn50xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn52xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn52xxp1;
+    struct cvmx_lmcx_rodt_ctl_s          cn56xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn56xxp1;
+    struct cvmx_lmcx_rodt_ctl_s          cn58xx;
+    struct cvmx_lmcx_rodt_ctl_s          cn58xxp1;
+} cvmx_lmcx_rodt_ctl_t;
+
+
+/**
+ * cvmx_lmc#_wodt_ctl0
+ *
+ * LMC_WODT_CTL0 = LMC Write OnDieTermination control
+ * See the description in LMC_WODT_CTL1.
+ *
+ * Notes:
+ * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.  See LMC_WODT_CTL1.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_wodt_ctl0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_lmcx_wodt_ctl0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t wodt_d1_r1              : 8;       /**< Write ODT mask DIMM1, RANK1 */
+        uint64_t wodt_d1_r0              : 8;       /**< Write ODT mask DIMM1, RANK0 */
+        uint64_t wodt_d0_r1              : 8;       /**< Write ODT mask DIMM0, RANK1 */
+        uint64_t wodt_d0_r0              : 8;       /**< Write ODT mask DIMM0, RANK0 */
+#else
+        uint64_t wodt_d0_r0              : 8;
+        uint64_t wodt_d0_r1              : 8;
+        uint64_t wodt_d1_r0              : 8;
+        uint64_t wodt_d1_r1              : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn31xx;
+    struct cvmx_lmcx_wodt_ctl0_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t wodt_hi3                : 4;       /**< Write ODT mask for position 3, data[127:64] */
+        uint64_t wodt_hi2                : 4;       /**< Write ODT mask for position 2, data[127:64] */
+        uint64_t wodt_hi1                : 4;       /**< Write ODT mask for position 1, data[127:64] */
+        uint64_t wodt_hi0                : 4;       /**< Write ODT mask for position 0, data[127:64] */
+        uint64_t wodt_lo3                : 4;       /**< Write ODT mask for position 3, data[ 63: 0] */
+        uint64_t wodt_lo2                : 4;       /**< Write ODT mask for position 2, data[ 63: 0] */
+        uint64_t wodt_lo1                : 4;       /**< Write ODT mask for position 1, data[ 63: 0] */
+        uint64_t wodt_lo0                : 4;       /**< Write ODT mask for position 0, data[ 63: 0] */
+#else
+        uint64_t wodt_lo0                : 4;
+        uint64_t wodt_lo1                : 4;
+        uint64_t wodt_lo2                : 4;
+        uint64_t wodt_lo3                : 4;
+        uint64_t wodt_hi0                : 4;
+        uint64_t wodt_hi1                : 4;
+        uint64_t wodt_hi2                : 4;
+        uint64_t wodt_hi3                : 4;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn38xx;
+    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn38xxp2;
+    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn50xx;
+    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn52xx;
+    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn52xxp1;
+    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn56xx;
+    struct cvmx_lmcx_wodt_ctl0_cn30xx    cn56xxp1;
+    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn58xx;
+    struct cvmx_lmcx_wodt_ctl0_cn38xx    cn58xxp1;
+} cvmx_lmcx_wodt_ctl0_t;
+
+
+/**
+ * cvmx_lmc#_wodt_ctl1
+ *
+ * LMC_WODT_CTL1 = LMC Write OnDieTermination control
+ * System designers may desire to terminate DQ/DQS/DM lines for higher frequency DDR operations
+ * (667MHz and faster), especially on a multi-rank system. DDR2 DQ/DM/DQS I/O's have built in
+ * Termination resistor that can be turned on or off by the controller, after meeting tAOND and tAOF
+ * timing requirements. Each Rank has its own ODT pin that fans out to all the memory parts
+ * in that DIMM. System designers may prefer different combinations of ODT ON's for read and write
+ * into different ranks. Octeon supports full programmability by way of the mask register below.
+ * Each Rank position has its own 8-bit programmable field.
+ * When the controller does a write to that rank, it sets the 8 ODT pins to the MASK pins below.
+ * For eg., When doing a write into Rank0, a system designer may desire to terminate the lines
+ * with the resistor on Dimm0/Rank1. The mask WODT_D0_R0 would then be [00000010].
+ * If ODT feature is not desired, the DDR parts can be programmed to not look at these pins by
+ * writing 0 in QS_DIC. Octeon drives the appropriate mask values on the ODT pins by default.
+ * If this feature is not required, write 0 in this register.
+ *
+ * Notes:
+ * Together, the LMC_WODT_CTL1 and LMC_WODT_CTL0 CSRs control the write ODT mask.
+ * When a given RANK is selected, the WODT mask for that RANK is used.  The resulting WODT mask is
+ * driven to the DIMMs in the following manner:
+ *            BUNK_ENA=1     BUNK_ENA=0
+ * Mask[7] -> DIMM3, RANK1    DIMM3
+ * Mask[6] -> DIMM3, RANK0
+ * Mask[5] -> DIMM2, RANK1    DIMM2
+ * Mask[4] -> DIMM2, RANK0
+ * Mask[3] -> DIMM1, RANK1    DIMM1
+ * Mask[2] -> DIMM1, RANK0
+ * Mask[1] -> DIMM0, RANK1    DIMM0
+ * Mask[0] -> DIMM0, RANK0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_lmcx_wodt_ctl1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t wodt_d3_r1              : 8;       /**< Write ODT mask DIMM3, RANK1/DIMM3 in SingleRanked */
+        uint64_t wodt_d3_r0              : 8;       /**< Write ODT mask DIMM3, RANK0 */
+        uint64_t wodt_d2_r1              : 8;       /**< Write ODT mask DIMM2, RANK1/DIMM2 in SingleRanked */
+        uint64_t wodt_d2_r0              : 8;       /**< Write ODT mask DIMM2, RANK0 */
+#else
+        uint64_t wodt_d2_r0              : 8;
+        uint64_t wodt_d2_r1              : 8;
+        uint64_t wodt_d3_r0              : 8;
+        uint64_t wodt_d3_r1              : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_lmcx_wodt_ctl1_s         cn30xx;
+    struct cvmx_lmcx_wodt_ctl1_s         cn31xx;
+    struct cvmx_lmcx_wodt_ctl1_s         cn52xx;
+    struct cvmx_lmcx_wodt_ctl1_s         cn52xxp1;
+    struct cvmx_lmcx_wodt_ctl1_s         cn56xx;
+    struct cvmx_lmcx_wodt_ctl1_s         cn56xxp1;
+} cvmx_lmcx_wodt_ctl1_t;
+
+
+/**
+ * cvmx_mio_boot_bist_stat
+ *
+ * MIO_BOOT_BIST_STAT = MIO Boot BIST Status Register
+ * 
+ * Contains the BIST status for the MIO boot memories.  '0' = pass, '1' = fail.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_bist_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t loc                     : 1;       /**< Local memory BIST status */
+        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
+#else
+        uint64_t ncbi                    : 1;
+        uint64_t loc                     : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_boot_bist_stat_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ncbo_1                  : 1;       /**< NCB output FIFO 1 BIST status */
+        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO 0 BIST status */
+        uint64_t loc                     : 1;       /**< Local memory BIST status */
+        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
+#else
+        uint64_t ncbi                    : 1;
+        uint64_t loc                     : 1;
+        uint64_t ncbo_0                  : 1;
+        uint64_t ncbo_1                  : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
+    struct cvmx_mio_boot_bist_stat_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO BIST status */
+        uint64_t loc                     : 1;       /**< Local memory BIST status */
+        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
+#else
+        uint64_t ncbi                    : 1;
+        uint64_t loc                     : 1;
+        uint64_t ncbo_0                  : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn38xx;
+    struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
+    struct cvmx_mio_boot_bist_stat_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t pcm_1                   : 1;       /**< PCM memory 1 BIST status */
+        uint64_t pcm_0                   : 1;       /**< PCM memory 0 BIST status */
+        uint64_t ncbo_1                  : 1;       /**< NCB output FIFO 1 BIST status */
+        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO 0 BIST status */
+        uint64_t loc                     : 1;       /**< Local memory BIST status */
+        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
+#else
+        uint64_t ncbi                    : 1;
+        uint64_t loc                     : 1;
+        uint64_t ncbo_0                  : 1;
+        uint64_t ncbo_1                  : 1;
+        uint64_t pcm_0                   : 1;
+        uint64_t pcm_1                   : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } cn50xx;
+    struct cvmx_mio_boot_bist_stat_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t ndf                     : 2;       /**< NAND flash BIST status */
+        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO BIST status */
+        uint64_t dma                     : 1;       /**< DMA memory BIST status */
+        uint64_t loc                     : 1;       /**< Local memory BIST status */
+        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
+#else
+        uint64_t ncbi                    : 1;
+        uint64_t loc                     : 1;
+        uint64_t dma                     : 1;
+        uint64_t ncbo_0                  : 1;
+        uint64_t ndf                     : 2;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } cn52xx;
+    struct cvmx_mio_boot_bist_stat_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t ncbo_0                  : 1;       /**< NCB output FIFO BIST status */
+        uint64_t dma                     : 1;       /**< DMA memory BIST status */
+        uint64_t loc                     : 1;       /**< Local memory BIST status */
+        uint64_t ncbi                    : 1;       /**< NCB input FIFO BIST status */
+#else
+        uint64_t ncbi                    : 1;
+        uint64_t loc                     : 1;
+        uint64_t dma                     : 1;
+        uint64_t ncbo_0                  : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn52xxp1;
+    struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
+    struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
+    struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
+    struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+} cvmx_mio_boot_bist_stat_t;
+
+
+/**
+ * cvmx_mio_boot_comp
+ *
+ * MIO_BOOT_COMP = MIO Boot Compensation Register
+ * 
+ * Reset value is as follows:
+ * 
+ * no pullups,               PCTL=0x1f, NCTL=0x1f
+ * pullup on boot_ad[9],     PCTL=0x1b, NCTL=0x1b (20 ohm termination)
+ * pullup on boot_ad[10],    PCTL=0x07, NCTL=0x08 (50 ohm termination)
+ * pullups on boot_ad[10:9], PCTL=0x06, NCTL=0x04 (60 ohm termination)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_comp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pctl                    : 5;       /**< Boot bus PCTL */
+        uint64_t nctl                    : 5;       /**< Boot bus NCTL */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_mio_boot_comp_s          cn50xx;
+    struct cvmx_mio_boot_comp_s          cn52xx;
+    struct cvmx_mio_boot_comp_s          cn52xxp1;
+    struct cvmx_mio_boot_comp_s          cn56xx;
+    struct cvmx_mio_boot_comp_s          cn56xxp1;
+} cvmx_mio_boot_comp_t;
+
+
+/**
+ * cvmx_mio_boot_dma_cfg#
+ *
+ * MIO_BOOT_DMA_CFG = MIO Boot DMA Config Register (1 per engine * 2 engines)
+ * 
+ * SIZE is specified in number of bus transfers, where one transfer is equal to the following number
+ * of bytes dependent on MIO_BOOT_DMA_TIMn[WIDTH] and MIO_BOOT_DMA_TIMn[DDR]:
+ * 
+ * WIDTH     DDR      Transfer Size (bytes)
+ * ----------------------------------------
+ *   0        0               2
+ *   0        1               4
+ *   1        0               4
+ *   1        1               8
+ * 
+ * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_dma_cfgx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t en                      : 1;       /**< DMA Engine X enable */
+        uint64_t rw                      : 1;       /**< DMA Engine X R/W bit (0 = read, 1 = write) */
+        uint64_t clr                     : 1;       /**< DMA Engine X clear EN on device terminated burst */
+        uint64_t reserved_60_60          : 1;
+        uint64_t swap32                  : 1;       /**< DMA Engine X 32 bit swap */
+        uint64_t swap16                  : 1;       /**< DMA Engine X 16 bit swap */
+        uint64_t swap8                   : 1;       /**< DMA Engine X 8 bit swap */
+        uint64_t endian                  : 1;       /**< DMA Engine X NCB endian mode (0 = big, 1 = little) */
+        uint64_t size                    : 20;      /**< DMA Engine X size */
+        uint64_t adr                     : 36;      /**< DMA Engine X address */
+#else
+        uint64_t adr                     : 36;
+        uint64_t size                    : 20;
+        uint64_t endian                  : 1;
+        uint64_t swap8                   : 1;
+        uint64_t swap16                  : 1;
+        uint64_t swap32                  : 1;
+        uint64_t reserved_60_60          : 1;
+        uint64_t clr                     : 1;
+        uint64_t rw                      : 1;
+        uint64_t en                      : 1;
+#endif
+    } s;
+    struct cvmx_mio_boot_dma_cfgx_s      cn52xx;
+    struct cvmx_mio_boot_dma_cfgx_s      cn52xxp1;
+    struct cvmx_mio_boot_dma_cfgx_s      cn56xx;
+    struct cvmx_mio_boot_dma_cfgx_s      cn56xxp1;
+} cvmx_mio_boot_dma_cfgx_t;
+
+
+/**
+ * cvmx_mio_boot_dma_int#
+ *
+ * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_dma_intx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dmarq                   : 1;       /**< DMA Engine X DMARQ asserted interrupt */
+        uint64_t done                    : 1;       /**< DMA Engine X request completion interrupt */
+#else
+        uint64_t done                    : 1;
+        uint64_t dmarq                   : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_boot_dma_intx_s      cn52xx;
+    struct cvmx_mio_boot_dma_intx_s      cn52xxp1;
+    struct cvmx_mio_boot_dma_intx_s      cn56xx;
+    struct cvmx_mio_boot_dma_intx_s      cn56xxp1;
+} cvmx_mio_boot_dma_intx_t;
+
+
+/**
+ * cvmx_mio_boot_dma_int_en#
+ *
+ * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_dma_int_enx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dmarq                   : 1;       /**< DMA Engine X DMARQ asserted interrupt enable */
+        uint64_t done                    : 1;       /**< DMA Engine X request completion interrupt enable */
+#else
+        uint64_t done                    : 1;
+        uint64_t dmarq                   : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_boot_dma_int_enx_s   cn52xx;
+    struct cvmx_mio_boot_dma_int_enx_s   cn52xxp1;
+    struct cvmx_mio_boot_dma_int_enx_s   cn56xx;
+    struct cvmx_mio_boot_dma_int_enx_s   cn56xxp1;
+} cvmx_mio_boot_dma_int_enx_t;
+
+
+/**
+ * cvmx_mio_boot_dma_tim#
+ *
+ * MIO_BOOT_DMA_TIM = MIO Boot DMA Timing Register (1 per engine * 2 engines)
+ * 
+ * DMACK_PI inverts the assertion level of boot_dmack[n].  The default polarity of boot_dmack[1:0] is
+ * selected on the first de-assertion of reset by the values on boot_ad[12:11], where 0 is active high
+ * and 1 is active low (see MIO_BOOT_PIN_DEFS for a read-only copy of the default polarity).
+ * boot_ad[12:11] have internal pulldowns, so place a pullup on boot_ad[n+11] for active low default
+ * polarity on engine n.  To interface with CF cards in True IDE Mode, either a pullup should be placed
+ * on boot_ad[n+11] OR the corresponding DMACK_PI[n] should be set.
+ * 
+ * DMARQ_PI inverts the assertion level of boot_dmarq[n].  The default polarity of boot_dmarq[1:0] is
+ * active high, thus setting the polarity inversion bits changes the polarity to active low.  To
+ * interface with CF cards in True IDE Mode, the corresponding DMARQ_PI[n] should be clear.
+ * 
+ * TIM_MULT specifies the timing multiplier for an engine.  The timing multiplier applies to all timing
+ * parameters, except for DMARQ and RD_DLY, which simply count eclks.  TIM_MULT is encoded as follows:
+ * 0 = 4x, 1 = 1x, 2 = 2x, 3 = 8x.
+ * 
+ * RD_DLY specifies the read sample delay in eclk cycles for an engine.  For reads, the data bus is
+ * normally sampled on the same eclk edge that drives boot_oe_n high (and also low in DDR mode).
+ * This parameter can delay that sampling edge by up to 7 eclks.  Note: the number of eclk cycles
+ * counted by the OE_A and DMACK_H + PAUSE timing parameters must be greater than RD_DLY.
+ * 
+ * If DDR is set, then WE_N must be less than WE_A.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_dma_timx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dmack_pi                : 1;       /**< DMA Engine X DMA ack polarity inversion */
+        uint64_t dmarq_pi                : 1;       /**< DMA Engine X DMA request polarity inversion */
+        uint64_t tim_mult                : 2;       /**< DMA Engine X timing multiplier */
+        uint64_t rd_dly                  : 3;       /**< DMA Engine X read sample delay */
+        uint64_t ddr                     : 1;       /**< DMA Engine X DDR mode */
+        uint64_t width                   : 1;       /**< DMA Engine X bus width (0 = 16 bits, 1 = 32 bits) */
+        uint64_t reserved_48_54          : 7;
+        uint64_t pause                   : 6;       /**< DMA Engine X pause count */
+        uint64_t dmack_h                 : 6;       /**< DMA Engine X DMA ack hold count */
+        uint64_t we_n                    : 6;       /**< DMA Engine X write enable negated count */
+        uint64_t we_a                    : 6;       /**< DMA Engine X write enable asserted count */
+        uint64_t oe_n                    : 6;       /**< DMA Engine X output enable negated count */
+        uint64_t oe_a                    : 6;       /**< DMA Engine X output enable asserted count */
+        uint64_t dmack_s                 : 6;       /**< DMA Engine X DMA ack setup count */
+        uint64_t dmarq                   : 6;       /**< DMA Engine X DMA request count (must be non-zero) */
+#else
+        uint64_t dmarq                   : 6;
+        uint64_t dmack_s                 : 6;
+        uint64_t oe_a                    : 6;
+        uint64_t oe_n                    : 6;
+        uint64_t we_a                    : 6;
+        uint64_t we_n                    : 6;
+        uint64_t dmack_h                 : 6;
+        uint64_t pause                   : 6;
+        uint64_t reserved_48_54          : 7;
+        uint64_t width                   : 1;
+        uint64_t ddr                     : 1;
+        uint64_t rd_dly                  : 3;
+        uint64_t tim_mult                : 2;
+        uint64_t dmarq_pi                : 1;
+        uint64_t dmack_pi                : 1;
+#endif
+    } s;
+    struct cvmx_mio_boot_dma_timx_s      cn52xx;
+    struct cvmx_mio_boot_dma_timx_s      cn52xxp1;
+    struct cvmx_mio_boot_dma_timx_s      cn56xx;
+    struct cvmx_mio_boot_dma_timx_s      cn56xxp1;
+} cvmx_mio_boot_dma_timx_t;
+
+
+/**
+ * cvmx_mio_boot_err
+ *
+ * MIO_BOOT_ERR = MIO Boot Error Register
+ * 
+ * Contains the address decode error and wait mode error bits.  Address decode error is set when a
+ * boot bus access does not hit in any of the 8 remote regions or 2 local regions.  Wait mode error is
+ * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_err_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t wait_err                : 1;       /**< Wait mode error */
+        uint64_t adr_err                 : 1;       /**< Address decode error */
+#else
+        uint64_t adr_err                 : 1;
+        uint64_t wait_err                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_boot_err_s           cn30xx;
+    struct cvmx_mio_boot_err_s           cn31xx;
+    struct cvmx_mio_boot_err_s           cn38xx;
+    struct cvmx_mio_boot_err_s           cn38xxp2;
+    struct cvmx_mio_boot_err_s           cn50xx;
+    struct cvmx_mio_boot_err_s           cn52xx;
+    struct cvmx_mio_boot_err_s           cn52xxp1;
+    struct cvmx_mio_boot_err_s           cn56xx;
+    struct cvmx_mio_boot_err_s           cn56xxp1;
+    struct cvmx_mio_boot_err_s           cn58xx;
+    struct cvmx_mio_boot_err_s           cn58xxp1;
+} cvmx_mio_boot_err_t;
+
+
+/**
+ * cvmx_mio_boot_int
+ *
+ * MIO_BOOT_INT = MIO Boot Interrupt Register
+ * 
+ * Contains the interrupt enable bits for address decode error and wait mode error.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t wait_int                : 1;       /**< Wait mode error interrupt enable */
+        uint64_t adr_int                 : 1;       /**< Address decode error interrupt enable */
+#else
+        uint64_t adr_int                 : 1;
+        uint64_t wait_int                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_boot_int_s           cn30xx;
+    struct cvmx_mio_boot_int_s           cn31xx;
+    struct cvmx_mio_boot_int_s           cn38xx;
+    struct cvmx_mio_boot_int_s           cn38xxp2;
+    struct cvmx_mio_boot_int_s           cn50xx;
+    struct cvmx_mio_boot_int_s           cn52xx;
+    struct cvmx_mio_boot_int_s           cn52xxp1;
+    struct cvmx_mio_boot_int_s           cn56xx;
+    struct cvmx_mio_boot_int_s           cn56xxp1;
+    struct cvmx_mio_boot_int_s           cn58xx;
+    struct cvmx_mio_boot_int_s           cn58xxp1;
+} cvmx_mio_boot_int_t;
+
+
+/**
+ * cvmx_mio_boot_loc_adr
+ *
+ * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Address Register
+ * 
+ * Specifies the address for reading or writing the local memory.  This address will post-increment
+ * following an access to the MIO Boot Local Memory Data Register (MIO_BOOT_LOC_DAT).
+ * 
+ * Local memory region 0 exists from addresses 0x00 - 0x78.
+ * Local memory region 1 exists from addresses 0x80 - 0xf8.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_loc_adr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t adr                     : 5;       /**< Local memory address */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t adr                     : 5;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_boot_loc_adr_s       cn30xx;
+    struct cvmx_mio_boot_loc_adr_s       cn31xx;
+    struct cvmx_mio_boot_loc_adr_s       cn38xx;
+    struct cvmx_mio_boot_loc_adr_s       cn38xxp2;
+    struct cvmx_mio_boot_loc_adr_s       cn50xx;
+    struct cvmx_mio_boot_loc_adr_s       cn52xx;
+    struct cvmx_mio_boot_loc_adr_s       cn52xxp1;
+    struct cvmx_mio_boot_loc_adr_s       cn56xx;
+    struct cvmx_mio_boot_loc_adr_s       cn56xxp1;
+    struct cvmx_mio_boot_loc_adr_s       cn58xx;
+    struct cvmx_mio_boot_loc_adr_s       cn58xxp1;
+} cvmx_mio_boot_loc_adr_t;
+
+
+/**
+ * cvmx_mio_boot_loc_cfg#
+ *
+ * MIO_BOOT_LOC_CFG = MIO Boot Local Region Config Register (1 per region * 2 regions)
+ * 
+ * Contains local region enable and local region base address parameters.  Each local region is 128
+ * bytes organized as 16 entries x 8 bytes.
+ * 
+ * Base address specifies address bits [31:7] of the region.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_loc_cfgx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t en                      : 1;       /**< Local region X enable */
+        uint64_t reserved_28_30          : 3;
+        uint64_t base                    : 25;      /**< Local region X base address */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t base                    : 25;
+        uint64_t reserved_28_30          : 3;
+        uint64_t en                      : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_mio_boot_loc_cfgx_s      cn30xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn31xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn38xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn38xxp2;
+    struct cvmx_mio_boot_loc_cfgx_s      cn50xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn52xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn52xxp1;
+    struct cvmx_mio_boot_loc_cfgx_s      cn56xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn56xxp1;
+    struct cvmx_mio_boot_loc_cfgx_s      cn58xx;
+    struct cvmx_mio_boot_loc_cfgx_s      cn58xxp1;
+} cvmx_mio_boot_loc_cfgx_t;
+
+
+/**
+ * cvmx_mio_boot_loc_dat
+ *
+ * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Data Register
+ * 
+ * This is a pseudo-register that will read/write the local memory at the address specified by the MIO
+ * Boot Local Address Register (MIO_BOOT_LOC_ADR) when accessed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_loc_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Local memory data */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_mio_boot_loc_dat_s       cn30xx;
+    struct cvmx_mio_boot_loc_dat_s       cn31xx;
+    struct cvmx_mio_boot_loc_dat_s       cn38xx;
+    struct cvmx_mio_boot_loc_dat_s       cn38xxp2;
+    struct cvmx_mio_boot_loc_dat_s       cn50xx;
+    struct cvmx_mio_boot_loc_dat_s       cn52xx;
+    struct cvmx_mio_boot_loc_dat_s       cn52xxp1;
+    struct cvmx_mio_boot_loc_dat_s       cn56xx;
+    struct cvmx_mio_boot_loc_dat_s       cn56xxp1;
+    struct cvmx_mio_boot_loc_dat_s       cn58xx;
+    struct cvmx_mio_boot_loc_dat_s       cn58xxp1;
+} cvmx_mio_boot_loc_dat_t;
+
+
+/**
+ * cvmx_mio_boot_pin_defs
+ *
+ * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_pin_defs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ale                     : 1;       /**< Region 0 default ALE mode */
+        uint64_t width                   : 1;       /**< Region 0 default bus width */
+        uint64_t dmack_p2                : 1;       /**< boot_dmack[2] default polarity */
+        uint64_t dmack_p1                : 1;       /**< boot_dmack[1] default polarity */
+        uint64_t dmack_p0                : 1;       /**< boot_dmack[0] default polarity */
+        uint64_t term                    : 2;       /**< Selects default driver termination */
+        uint64_t nand                    : 1;       /**< Region 0 is NAND flash */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t nand                    : 1;
+        uint64_t term                    : 2;
+        uint64_t dmack_p0                : 1;
+        uint64_t dmack_p1                : 1;
+        uint64_t dmack_p2                : 1;
+        uint64_t width                   : 1;
+        uint64_t ale                     : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_mio_boot_pin_defs_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ale                     : 1;       /**< Region 0 default ALE mode */
+        uint64_t width                   : 1;       /**< Region 0 default bus width */
+        uint64_t reserved_13_13          : 1;
+        uint64_t dmack_p1                : 1;       /**< boot_dmack[1] default polarity */
+        uint64_t dmack_p0                : 1;       /**< boot_dmack[0] default polarity */
+        uint64_t term                    : 2;       /**< Selects default driver termination */
+        uint64_t nand                    : 1;       /**< Region 0 is NAND flash */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t nand                    : 1;
+        uint64_t term                    : 2;
+        uint64_t dmack_p0                : 1;
+        uint64_t dmack_p1                : 1;
+        uint64_t reserved_13_13          : 1;
+        uint64_t width                   : 1;
+        uint64_t ale                     : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn52xx;
+    struct cvmx_mio_boot_pin_defs_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ale                     : 1;       /**< Region 0 default ALE mode */
+        uint64_t width                   : 1;       /**< Region 0 default bus width */
+        uint64_t dmack_p2                : 1;       /**< boot_dmack[2] default polarity */
+        uint64_t dmack_p1                : 1;       /**< boot_dmack[1] default polarity */
+        uint64_t dmack_p0                : 1;       /**< boot_dmack[0] default polarity */
+        uint64_t term                    : 2;       /**< Selects default driver termination */
+        uint64_t reserved_0_8            : 9;
+#else
+        uint64_t reserved_0_8            : 9;
+        uint64_t term                    : 2;
+        uint64_t dmack_p0                : 1;
+        uint64_t dmack_p1                : 1;
+        uint64_t dmack_p2                : 1;
+        uint64_t width                   : 1;
+        uint64_t ale                     : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn56xx;
+} cvmx_mio_boot_pin_defs_t;
+
+
+/**
+ * cvmx_mio_boot_reg_cfg#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_reg_cfgx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t dmack                   : 2;       /**< Region X DMACK */
+        uint64_t tim_mult                : 2;       /**< Region X timing multiplier */
+        uint64_t rd_dly                  : 3;       /**< Region X read sample delay */
+        uint64_t sam                     : 1;       /**< Region X SAM mode */
+        uint64_t we_ext                  : 2;       /**< Region X write enable count extension */
+        uint64_t oe_ext                  : 2;       /**< Region X output enable count extension */
+        uint64_t en                      : 1;       /**< Region X enable */
+        uint64_t orbit                   : 1;       /**< Region X or bit */
+        uint64_t ale                     : 1;       /**< Region X ALE mode */
+        uint64_t width                   : 1;       /**< Region X bus width */
+        uint64_t size                    : 12;      /**< Region X size */
+        uint64_t base                    : 16;      /**< Region X base address */
+#else
+        uint64_t base                    : 16;
+        uint64_t size                    : 12;
+        uint64_t width                   : 1;
+        uint64_t ale                     : 1;
+        uint64_t orbit                   : 1;
+        uint64_t en                      : 1;
+        uint64_t oe_ext                  : 2;
+        uint64_t we_ext                  : 2;
+        uint64_t sam                     : 1;
+        uint64_t rd_dly                  : 3;
+        uint64_t tim_mult                : 2;
+        uint64_t dmack                   : 2;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_mio_boot_reg_cfgx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t sam                     : 1;       /**< Region X SAM mode */
+        uint64_t we_ext                  : 2;       /**< Region X write enable count extension */
+        uint64_t oe_ext                  : 2;       /**< Region X output enable count extension */
+        uint64_t en                      : 1;       /**< Region X enable */
+        uint64_t orbit                   : 1;       /**< Region X or bit */
+        uint64_t ale                     : 1;       /**< Region X ALE mode */
+        uint64_t width                   : 1;       /**< Region X bus width */
+        uint64_t size                    : 12;      /**< Region X size */
+        uint64_t base                    : 16;      /**< Region X base address */
+#else
+        uint64_t base                    : 16;
+        uint64_t size                    : 12;
+        uint64_t width                   : 1;
+        uint64_t ale                     : 1;
+        uint64_t orbit                   : 1;
+        uint64_t en                      : 1;
+        uint64_t oe_ext                  : 2;
+        uint64_t we_ext                  : 2;
+        uint64_t sam                     : 1;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } cn30xx;
+    struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
+    struct cvmx_mio_boot_reg_cfgx_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t en                      : 1;       /**< Region X enable */
+        uint64_t orbit                   : 1;       /**< Region X or bit */
+        uint64_t reserved_28_29          : 2;
+        uint64_t size                    : 12;      /**< Region X size */
+        uint64_t base                    : 16;      /**< Region X base address */
+#else
+        uint64_t base                    : 16;
+        uint64_t size                    : 12;
+        uint64_t reserved_28_29          : 2;
+        uint64_t orbit                   : 1;
+        uint64_t en                      : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn38xx;
+    struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
+    struct cvmx_mio_boot_reg_cfgx_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_42_63          : 22;
+        uint64_t tim_mult                : 2;       /**< Region X timing multiplier */
+        uint64_t rd_dly                  : 3;       /**< Region X read sample delay */
+        uint64_t sam                     : 1;       /**< Region X SAM mode */
+        uint64_t we_ext                  : 2;       /**< Region X write enable count extension */
+        uint64_t oe_ext                  : 2;       /**< Region X output enable count extension */
+        uint64_t en                      : 1;       /**< Region X enable */
+        uint64_t orbit                   : 1;       /**< Region X or bit */
+        uint64_t ale                     : 1;       /**< Region X ALE mode */
+        uint64_t width                   : 1;       /**< Region X bus width */
+        uint64_t size                    : 12;      /**< Region X size */
+        uint64_t base                    : 16;      /**< Region X base address */
+#else
+        uint64_t base                    : 16;
+        uint64_t size                    : 12;
+        uint64_t width                   : 1;
+        uint64_t ale                     : 1;
+        uint64_t orbit                   : 1;
+        uint64_t en                      : 1;
+        uint64_t oe_ext                  : 2;
+        uint64_t we_ext                  : 2;
+        uint64_t sam                     : 1;
+        uint64_t rd_dly                  : 3;
+        uint64_t tim_mult                : 2;
+        uint64_t reserved_42_63          : 22;
+#endif
+    } cn50xx;
+    struct cvmx_mio_boot_reg_cfgx_s      cn52xx;
+    struct cvmx_mio_boot_reg_cfgx_s      cn52xxp1;
+    struct cvmx_mio_boot_reg_cfgx_s      cn56xx;
+    struct cvmx_mio_boot_reg_cfgx_s      cn56xxp1;
+    struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
+    struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+} cvmx_mio_boot_reg_cfgx_t;
+
+
+/**
+ * cvmx_mio_boot_reg_tim#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_reg_timx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pagem                   : 1;       /**< Region X page mode */
+        uint64_t waitm                   : 1;       /**< Region X wait mode */
+        uint64_t pages                   : 2;       /**< Region X page size */
+        uint64_t ale                     : 6;       /**< Region X ALE count */
+        uint64_t page                    : 6;       /**< Region X page count */
+        uint64_t wait                    : 6;       /**< Region X wait count */
+        uint64_t pause                   : 6;       /**< Region X pause count */
+        uint64_t wr_hld                  : 6;       /**< Region X write hold count */
+        uint64_t rd_hld                  : 6;       /**< Region X read hold count */
+        uint64_t we                      : 6;       /**< Region X write enable count */
+        uint64_t oe                      : 6;       /**< Region X output enable count */
+        uint64_t ce                      : 6;       /**< Region X chip enable count */
+        uint64_t adr                     : 6;       /**< Region X address count */
+#else
+        uint64_t adr                     : 6;
+        uint64_t ce                      : 6;
+        uint64_t oe                      : 6;
+        uint64_t we                      : 6;
+        uint64_t rd_hld                  : 6;
+        uint64_t wr_hld                  : 6;
+        uint64_t pause                   : 6;
+        uint64_t wait                    : 6;
+        uint64_t page                    : 6;
+        uint64_t ale                     : 6;
+        uint64_t pages                   : 2;
+        uint64_t waitm                   : 1;
+        uint64_t pagem                   : 1;
+#endif
+    } s;
+    struct cvmx_mio_boot_reg_timx_s      cn30xx;
+    struct cvmx_mio_boot_reg_timx_s      cn31xx;
+    struct cvmx_mio_boot_reg_timx_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pagem                   : 1;       /**< Region X page mode */
+        uint64_t waitm                   : 1;       /**< Region X wait mode */
+        uint64_t pages                   : 2;       /**< Region X page size (NOT IN PASS 1) */
+        uint64_t reserved_54_59          : 6;
+        uint64_t page                    : 6;       /**< Region X page count */
+        uint64_t wait                    : 6;       /**< Region X wait count */
+        uint64_t pause                   : 6;       /**< Region X pause count */
+        uint64_t wr_hld                  : 6;       /**< Region X write hold count */
+        uint64_t rd_hld                  : 6;       /**< Region X read hold count */
+        uint64_t we                      : 6;       /**< Region X write enable count */
+        uint64_t oe                      : 6;       /**< Region X output enable count */
+        uint64_t ce                      : 6;       /**< Region X chip enable count */
+        uint64_t adr                     : 6;       /**< Region X address count */
+#else
+        uint64_t adr                     : 6;
+        uint64_t ce                      : 6;
+        uint64_t oe                      : 6;
+        uint64_t we                      : 6;
+        uint64_t rd_hld                  : 6;
+        uint64_t wr_hld                  : 6;
+        uint64_t pause                   : 6;
+        uint64_t wait                    : 6;
+        uint64_t page                    : 6;
+        uint64_t reserved_54_59          : 6;
+        uint64_t pages                   : 2;
+        uint64_t waitm                   : 1;
+        uint64_t pagem                   : 1;
+#endif
+    } cn38xx;
+    struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
+    struct cvmx_mio_boot_reg_timx_s      cn50xx;
+    struct cvmx_mio_boot_reg_timx_s      cn52xx;
+    struct cvmx_mio_boot_reg_timx_s      cn52xxp1;
+    struct cvmx_mio_boot_reg_timx_s      cn56xx;
+    struct cvmx_mio_boot_reg_timx_s      cn56xxp1;
+    struct cvmx_mio_boot_reg_timx_s      cn58xx;
+    struct cvmx_mio_boot_reg_timx_s      cn58xxp1;
+} cvmx_mio_boot_reg_timx_t;
+
+
+/**
+ * cvmx_mio_boot_thr
+ *
+ * MIO_BOOT_THR = MIO Boot Threshold Register
+ * 
+ * Contains MIO Boot threshold values:
+ * 
+ * FIF_THR = Assert ncb__busy when the Boot NCB input FIFO reaches this level (not typically for
+ *           customer use).
+ * 
+ * DMA_THR = When non-DMA accesses are pending, perform a DMA access after this value of non-DMA
+ *           accesses have completed.  If set to zero, only perform a DMA access when non-DMA
+ *           accesses are not pending.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_boot_thr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_22_63          : 42;
+        uint64_t dma_thr                 : 6;       /**< DMA threshold */
+        uint64_t reserved_14_15          : 2;
+        uint64_t fif_cnt                 : 6;       /**< Current NCB FIFO count */
+        uint64_t reserved_6_7            : 2;
+        uint64_t fif_thr                 : 6;       /**< NCB busy threshold */
+#else
+        uint64_t fif_thr                 : 6;
+        uint64_t reserved_6_7            : 2;
+        uint64_t fif_cnt                 : 6;
+        uint64_t reserved_14_15          : 2;
+        uint64_t dma_thr                 : 6;
+        uint64_t reserved_22_63          : 42;
+#endif
+    } s;
+    struct cvmx_mio_boot_thr_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t fif_cnt                 : 6;       /**< Current NCB FIFO count */
+        uint64_t reserved_6_7            : 2;
+        uint64_t fif_thr                 : 6;       /**< NCB busy threshold */
+#else
+        uint64_t fif_thr                 : 6;
+        uint64_t reserved_6_7            : 2;
+        uint64_t fif_cnt                 : 6;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn30xx;
+    struct cvmx_mio_boot_thr_cn30xx      cn31xx;
+    struct cvmx_mio_boot_thr_cn30xx      cn38xx;
+    struct cvmx_mio_boot_thr_cn30xx      cn38xxp2;
+    struct cvmx_mio_boot_thr_cn30xx      cn50xx;
+    struct cvmx_mio_boot_thr_s           cn52xx;
+    struct cvmx_mio_boot_thr_s           cn52xxp1;
+    struct cvmx_mio_boot_thr_s           cn56xx;
+    struct cvmx_mio_boot_thr_s           cn56xxp1;
+    struct cvmx_mio_boot_thr_cn30xx      cn58xx;
+    struct cvmx_mio_boot_thr_cn30xx      cn58xxp1;
+} cvmx_mio_boot_thr_t;
+
+
+/**
+ * cvmx_mio_fus_bnk_dat#
+ *
+ * Notes:
+ * The intial state of MIO_FUS_BNK_DAT* is as if bank1 was just read i.e. DAT* = fus[511:256]
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_bnk_datx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dat                     : 64;      /**< Efuse bank store
+                                                         For reads, the DAT gets the fus bank last read
+                                                         For write, the DAT determines which fuses to blow */
+#else
+        uint64_t dat                     : 64;
+#endif
+    } s;
+    struct cvmx_mio_fus_bnk_datx_s       cn50xx;
+    struct cvmx_mio_fus_bnk_datx_s       cn52xx;
+    struct cvmx_mio_fus_bnk_datx_s       cn52xxp1;
+    struct cvmx_mio_fus_bnk_datx_s       cn56xx;
+    struct cvmx_mio_fus_bnk_datx_s       cn56xxp1;
+    struct cvmx_mio_fus_bnk_datx_s       cn58xx;
+    struct cvmx_mio_fus_bnk_datx_s       cn58xxp1;
+} cvmx_mio_fus_bnk_datx_t;
+
+
+/**
+ * cvmx_mio_fus_dat0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_dat0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t man_info                : 32;      /**< Fuse information - manufacturing info [31:0] */
+#else
+        uint64_t man_info                : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_mio_fus_dat0_s           cn30xx;
+    struct cvmx_mio_fus_dat0_s           cn31xx;
+    struct cvmx_mio_fus_dat0_s           cn38xx;
+    struct cvmx_mio_fus_dat0_s           cn38xxp2;
+    struct cvmx_mio_fus_dat0_s           cn50xx;
+    struct cvmx_mio_fus_dat0_s           cn52xx;
+    struct cvmx_mio_fus_dat0_s           cn52xxp1;
+    struct cvmx_mio_fus_dat0_s           cn56xx;
+    struct cvmx_mio_fus_dat0_s           cn56xxp1;
+    struct cvmx_mio_fus_dat0_s           cn58xx;
+    struct cvmx_mio_fus_dat0_s           cn58xxp1;
+} cvmx_mio_fus_dat0_t;
+
+
+/**
+ * cvmx_mio_fus_dat1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_dat1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t man_info                : 32;      /**< Fuse information - manufacturing info [63:32] */
+#else
+        uint64_t man_info                : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_mio_fus_dat1_s           cn30xx;
+    struct cvmx_mio_fus_dat1_s           cn31xx;
+    struct cvmx_mio_fus_dat1_s           cn38xx;
+    struct cvmx_mio_fus_dat1_s           cn38xxp2;
+    struct cvmx_mio_fus_dat1_s           cn50xx;
+    struct cvmx_mio_fus_dat1_s           cn52xx;
+    struct cvmx_mio_fus_dat1_s           cn52xxp1;
+    struct cvmx_mio_fus_dat1_s           cn56xx;
+    struct cvmx_mio_fus_dat1_s           cn56xxp1;
+    struct cvmx_mio_fus_dat1_s           cn58xx;
+    struct cvmx_mio_fus_dat1_s           cn58xxp1;
+} cvmx_mio_fus_dat1_t;
+
+
+/**
+ * cvmx_mio_fus_dat2
+ *
+ * Notes:
+ * CHIP_ID is consumed in several places within Octeon.
+ * 
+ *    * Core COP0 ProcessorIdentification[Revision]
+ *    * Core EJTAG DeviceIdentification[Version]
+ *    * PCI_CFG02[RID]
+ *    * JTAG controller
+ * 
+ * Note: The JTAG controller gets CHIP_ID[3:0] solely from the laser fuses.
+ * Modification to the efuses will not change what the JTAG controller reports
+ * for CHIP_ID.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_dat2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
+        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled */
+        uint64_t reserved_30_31          : 2;
+        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t reserved_0_15           : 16;
+#else
+        uint64_t reserved_0_15           : 16;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t nokasu                  : 1;
+        uint64_t reserved_30_31          : 2;
+        uint64_t raid_en                 : 1;
+        uint64_t fus318                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_mio_fus_dat2_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t pll_off                 : 4;       /**< Fuse information - core pll offset
+                                                         Used to compute the base offset for the core pll.
+                                                         the offset will be (PLL_OFF ^ 8)
+                                                         Note, these fuses can only be set from laser fuse */
+        uint64_t reserved_1_11           : 11;
+        uint64_t pp_dis                  : 1;       /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 1;
+        uint64_t reserved_1_11           : 11;
+        uint64_t pll_off                 : 4;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn30xx;
+    struct cvmx_mio_fus_dat2_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t pll_off                 : 4;       /**< Fuse information - core pll offset
+                                                         Used to compute the base offset for the core pll.
+                                                         the offset will be (PLL_OFF ^ 8)
+                                                         Note, these fuses can only be set from laser fuse */
+        uint64_t reserved_2_11           : 10;
+        uint64_t pp_dis                  : 2;       /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 2;
+        uint64_t reserved_2_11           : 10;
+        uint64_t pll_off                 : 4;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn31xx;
+    struct cvmx_mio_fus_dat2_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2)
+                                                         (PASS2 Only) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable
+                                                         (PASS2 Only) */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable
+                                                         (PASS2 Only) */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t pp_dis                  : 16;      /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 16;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn38xx;
+    struct cvmx_mio_fus_dat2_cn38xx      cn38xxp2;
+    struct cvmx_mio_fus_dat2_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
+        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled
+                                                         (5020 does not have RAID co-processor) */
+        uint64_t reserved_30_31          : 2;
+        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2)
+                                                         (5020 does not have DFA co-processor) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t reserved_2_15           : 14;
+        uint64_t pp_dis                  : 2;       /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 2;
+        uint64_t reserved_2_15           : 14;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t nokasu                  : 1;
+        uint64_t reserved_30_31          : 2;
+        uint64_t raid_en                 : 1;
+        uint64_t fus318                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn50xx;
+    struct cvmx_mio_fus_dat2_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
+        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled */
+        uint64_t reserved_30_31          : 2;
+        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t reserved_4_15           : 12;
+        uint64_t pp_dis                  : 4;       /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 4;
+        uint64_t reserved_4_15           : 12;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t nokasu                  : 1;
+        uint64_t reserved_30_31          : 2;
+        uint64_t raid_en                 : 1;
+        uint64_t fus318                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn52xx;
+    struct cvmx_mio_fus_dat2_cn52xx      cn52xxp1;
+    struct cvmx_mio_fus_dat2_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t fus318                  : 1;       /**< Fuse information - a copy of fuse318 */
+        uint64_t raid_en                 : 1;       /**< Fuse information - RAID enabled */
+        uint64_t reserved_30_31          : 2;
+        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t reserved_12_15          : 4;
+        uint64_t pp_dis                  : 12;      /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 12;
+        uint64_t reserved_12_15          : 4;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t nokasu                  : 1;
+        uint64_t reserved_30_31          : 2;
+        uint64_t raid_en                 : 1;
+        uint64_t fus318                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn56xx;
+    struct cvmx_mio_fus_dat2_cn56xx      cn56xxp1;
+    struct cvmx_mio_fus_dat2_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_30_63          : 34;
+        uint64_t nokasu                  : 1;       /**< Fuse information - Disable Kasumi */
+        uint64_t nodfa_cp2               : 1;       /**< Fuse information - DFA Disable (CP2) */
+        uint64_t nomul                   : 1;       /**< Fuse information - VMUL disable */
+        uint64_t nocrypto                : 1;       /**< Fuse information - AES/DES/HASH disable */
+        uint64_t rst_sht                 : 1;       /**< Fuse information - When set, use short reset count */
+        uint64_t bist_dis                : 1;       /**< Fuse information - BIST Disable */
+        uint64_t chip_id                 : 8;       /**< Fuse information - CHIP_ID */
+        uint64_t pp_dis                  : 16;      /**< Fuse information - PP_DISABLES */
+#else
+        uint64_t pp_dis                  : 16;
+        uint64_t chip_id                 : 8;
+        uint64_t bist_dis                : 1;
+        uint64_t rst_sht                 : 1;
+        uint64_t nocrypto                : 1;
+        uint64_t nomul                   : 1;
+        uint64_t nodfa_cp2               : 1;
+        uint64_t nokasu                  : 1;
+        uint64_t reserved_30_63          : 34;
+#endif
+    } cn58xx;
+    struct cvmx_mio_fus_dat2_cn58xx      cn58xxp1;
+} cvmx_mio_fus_dat2_t;
+
+
+/**
+ * cvmx_mio_fus_dat3
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_dat3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pll_div4                : 1;       /**< Fuse information - PLL DIV4 mode
+                                                         (laser fuse only) */
+        uint64_t zip_crip                : 2;       /**< Fuse information - Zip Cripple */
+        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1') */
+        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown */
+        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store. */
+        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable */
+        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE) */
+        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
+#else
+        uint64_t icache                  : 24;
+        uint64_t nodfa_dte               : 1;
+        uint64_t nozip                   : 1;
+        uint64_t efus_ign                : 1;
+        uint64_t efus_lck                : 1;
+        uint64_t bar2_en                 : 1;
+        uint64_t zip_crip                : 2;
+        uint64_t pll_div4                : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_mio_fus_dat3_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pll_div4                : 1;       /**< Fuse information - PLL DIV4 mode
+                                                         (laser fuse only) */
+        uint64_t reserved_29_30          : 2;
+        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1') */
+        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown */
+        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store. */
+        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable */
+        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE) */
+        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
+#else
+        uint64_t icache                  : 24;
+        uint64_t nodfa_dte               : 1;
+        uint64_t nozip                   : 1;
+        uint64_t efus_ign                : 1;
+        uint64_t efus_lck                : 1;
+        uint64_t bar2_en                 : 1;
+        uint64_t reserved_29_30          : 2;
+        uint64_t pll_div4                : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_mio_fus_dat3_s           cn31xx;
+    struct cvmx_mio_fus_dat3_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t zip_crip                : 2;       /**< Fuse information - Zip Cripple
+                                                         (PASS3 Only) */
+        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1')
+                                                         (PASS2 Only) */
+        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown
+                                                         (PASS2 Only) */
+        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store.
+                                                         (PASS2 Only) */
+        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable
+                                                         (PASS2 Only) */
+        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE)
+                                                         (PASS2 Only) */
+        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
+#else
+        uint64_t icache                  : 24;
+        uint64_t nodfa_dte               : 1;
+        uint64_t nozip                   : 1;
+        uint64_t efus_ign                : 1;
+        uint64_t efus_lck                : 1;
+        uint64_t bar2_en                 : 1;
+        uint64_t zip_crip                : 2;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } cn38xx;
+    struct cvmx_mio_fus_dat3_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t bar2_en                 : 1;       /**< Fuse information - BAR2 Enable (when blown '1')
+                                                         (PASS2 Only) */
+        uint64_t efus_lck                : 1;       /**< Fuse information - efuse lockdown
+                                                         (PASS2 Only) */
+        uint64_t efus_ign                : 1;       /**< Fuse information - efuse ignore
+                                                         This bit only has side effects when blown in
+                                                         the laser fuses.  It is ignore if only set in
+                                                         efuse store.
+                                                         (PASS2 Only) */
+        uint64_t nozip                   : 1;       /**< Fuse information - ZIP disable
+                                                         (PASS2 Only) */
+        uint64_t nodfa_dte               : 1;       /**< Fuse information - DFA Disable (DTE)
+                                                         (PASS2 Only) */
+        uint64_t icache                  : 24;      /**< Fuse information - ICACHE Hard Repair Data */
+#else
+        uint64_t icache                  : 24;
+        uint64_t nodfa_dte               : 1;
+        uint64_t nozip                   : 1;
+        uint64_t efus_ign                : 1;
+        uint64_t efus_lck                : 1;
+        uint64_t bar2_en                 : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn38xxp2;
+    struct cvmx_mio_fus_dat3_cn38xx      cn50xx;
+    struct cvmx_mio_fus_dat3_cn38xx      cn52xx;
+    struct cvmx_mio_fus_dat3_cn38xx      cn52xxp1;
+    struct cvmx_mio_fus_dat3_cn38xx      cn56xx;
+    struct cvmx_mio_fus_dat3_cn38xx      cn56xxp1;
+    struct cvmx_mio_fus_dat3_cn38xx      cn58xx;
+    struct cvmx_mio_fus_dat3_cn38xx      cn58xxp1;
+} cvmx_mio_fus_dat3_t;
+
+
+/**
+ * cvmx_mio_fus_ema
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_ema_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t eff_ema                 : 3;       /**< Effective EMA value */
+        uint64_t reserved_3_3            : 1;
+        uint64_t ema                     : 3;       /**< EMA Settings */
+#else
+        uint64_t ema                     : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t eff_ema                 : 3;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mio_fus_ema_s            cn50xx;
+    struct cvmx_mio_fus_ema_s            cn52xx;
+    struct cvmx_mio_fus_ema_s            cn52xxp1;
+    struct cvmx_mio_fus_ema_s            cn56xx;
+    struct cvmx_mio_fus_ema_s            cn56xxp1;
+    struct cvmx_mio_fus_ema_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t ema                     : 2;       /**< EMA Settings */
+#else
+        uint64_t ema                     : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn58xx;
+    struct cvmx_mio_fus_ema_cn58xx       cn58xxp1;
+} cvmx_mio_fus_ema_t;
+
+
+/**
+ * cvmx_mio_fus_pdf
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_pdf_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pdf                     : 64;      /**< Fuse information - Product Definition Field */
+#else
+        uint64_t pdf                     : 64;
+#endif
+    } s;
+    struct cvmx_mio_fus_pdf_s            cn50xx;
+    struct cvmx_mio_fus_pdf_s            cn52xx;
+    struct cvmx_mio_fus_pdf_s            cn52xxp1;
+    struct cvmx_mio_fus_pdf_s            cn56xx;
+    struct cvmx_mio_fus_pdf_s            cn56xxp1;
+    struct cvmx_mio_fus_pdf_s            cn58xx;
+} cvmx_mio_fus_pdf_t;
+
+
+/**
+ * cvmx_mio_fus_pll
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_pll_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t rfslip                  : 1;       /**< PLL reference clock slip */
+        uint64_t fbslip                  : 1;       /**< PLL feedback clock slip */
+#else
+        uint64_t fbslip                  : 1;
+        uint64_t rfslip                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_fus_pll_s            cn50xx;
+    struct cvmx_mio_fus_pll_s            cn52xx;
+    struct cvmx_mio_fus_pll_s            cn52xxp1;
+    struct cvmx_mio_fus_pll_s            cn56xx;
+    struct cvmx_mio_fus_pll_s            cn56xxp1;
+    struct cvmx_mio_fus_pll_s            cn58xx;
+    struct cvmx_mio_fus_pll_s            cn58xxp1;
+} cvmx_mio_fus_pll_t;
+
+
+/**
+ * cvmx_mio_fus_prog
+ *
+ * Notes:
+ * To write a bank of fuses, SW must set MIO_FUS_WADR[ADDR] to the bank to be
+ * programmed and then set each bit within MIO_FUS_BNK_DATX to indicate which
+ * fuses to blow.  Once ADDR, and DAT are setup, SW can write to
+ * MIO_FUS_PROG[PROG] to start the bank write and poll on PROG.  Once PROG is
+ * clear, the bank write is complete.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_prog_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t prog                    : 1;       /**< Blow the fuse bank
+                                                         SW will set PROG, and then the HW will clear
+                                                         when the PROG bank is complete */
+#else
+        uint64_t prog                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_fus_prog_s           cn30xx;
+    struct cvmx_mio_fus_prog_s           cn31xx;
+    struct cvmx_mio_fus_prog_s           cn38xx;
+    struct cvmx_mio_fus_prog_s           cn38xxp2;
+    struct cvmx_mio_fus_prog_s           cn50xx;
+    struct cvmx_mio_fus_prog_s           cn52xx;
+    struct cvmx_mio_fus_prog_s           cn52xxp1;
+    struct cvmx_mio_fus_prog_s           cn56xx;
+    struct cvmx_mio_fus_prog_s           cn56xxp1;
+    struct cvmx_mio_fus_prog_s           cn58xx;
+    struct cvmx_mio_fus_prog_s           cn58xxp1;
+} cvmx_mio_fus_prog_t;
+
+
+/**
+ * cvmx_mio_fus_prog_times
+ *
+ * Notes:
+ * All values must be > 0 for correct electrical operation.
+ * 
+ * The reset values are a conservative version for a 50MHz ref_clk.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_prog_times_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_33_63          : 31;
+        uint64_t prog_pin                : 1;       /**< efuse program pin */
+        uint64_t out                     : 8;       /**< efuse timing param (ref_clks to delay 10ns) */
+        uint64_t sclk_lo                 : 4;       /**< efuse timing param (ref_clks to delay 5ns) */
+        uint64_t sclk_hi                 : 12;      /**< efuse timing param (ref_clks to delay 1000ns) */
+        uint64_t setup                   : 8;       /**< efuse timing param (ref_clks to delay 10ns) */
+#else
+        uint64_t setup                   : 8;
+        uint64_t sclk_hi                 : 12;
+        uint64_t sclk_lo                 : 4;
+        uint64_t out                     : 8;
+        uint64_t prog_pin                : 1;
+        uint64_t reserved_33_63          : 31;
+#endif
+    } s;
+    struct cvmx_mio_fus_prog_times_s     cn50xx;
+    struct cvmx_mio_fus_prog_times_s     cn52xx;
+    struct cvmx_mio_fus_prog_times_s     cn52xxp1;
+    struct cvmx_mio_fus_prog_times_s     cn56xx;
+    struct cvmx_mio_fus_prog_times_s     cn56xxp1;
+    struct cvmx_mio_fus_prog_times_s     cn58xx;
+    struct cvmx_mio_fus_prog_times_s     cn58xxp1;
+} cvmx_mio_fus_prog_times_t;
+
+
+/**
+ * cvmx_mio_fus_rcmd
+ *
+ * Notes:
+ * To read an efuse, SW writes MIO_FUS_RCMD[ADDR,PEND] with the byte address of
+ * the fuse in question, then SW can poll MIO_FUS_RCMD[PEND].  When PEND is
+ * clear, then MIO_FUS_RCMD[DAT] is valid.  In addition, if the efuse read went
+ * to the efuse banks (e.g. ADDR > (320/8) || EFUSE is set) SW can read
+ * MIO_FUS_BNK_DATX which contains all 256 fuses in the bank associated in
+ * ADDR.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_rcmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t dat                     : 8;       /**< 8bits of fuse data */
+        uint64_t reserved_13_15          : 3;
+        uint64_t pend                    : 1;       /**< SW sets this bit on a write to start FUSE read
+                                                         operation.  HW clears when read is complete and
+                                                         the DAT is valid */
+        uint64_t reserved_9_11           : 3;
+        uint64_t efuse                   : 1;       /**< When set, return data from the efuse storage
+                                                         rather than the local storage for the 320 HW fuses */
+        uint64_t addr                    : 8;       /**< The byte address of the fuse to read */
+#else
+        uint64_t addr                    : 8;
+        uint64_t efuse                   : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t pend                    : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t dat                     : 8;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_mio_fus_rcmd_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t dat                     : 8;       /**< 8bits of fuse data */
+        uint64_t reserved_13_15          : 3;
+        uint64_t pend                    : 1;       /**< SW sets this bit on a write to start FUSE read
+                                                         operation.  HW clears when read is complete and
+                                                         the DAT is valid */
+        uint64_t reserved_9_11           : 3;
+        uint64_t efuse                   : 1;       /**< When set, return data from the efuse storage
+                                                         rather than the local storage for the 320 HW fuses */
+        uint64_t reserved_7_7            : 1;
+        uint64_t addr                    : 7;       /**< The byte address of the fuse to read */
+#else
+        uint64_t addr                    : 7;
+        uint64_t reserved_7_7            : 1;
+        uint64_t efuse                   : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t pend                    : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t dat                     : 8;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } cn30xx;
+    struct cvmx_mio_fus_rcmd_cn30xx      cn31xx;
+    struct cvmx_mio_fus_rcmd_cn30xx      cn38xx;
+    struct cvmx_mio_fus_rcmd_cn30xx      cn38xxp2;
+    struct cvmx_mio_fus_rcmd_cn30xx      cn50xx;
+    struct cvmx_mio_fus_rcmd_s           cn52xx;
+    struct cvmx_mio_fus_rcmd_s           cn52xxp1;
+    struct cvmx_mio_fus_rcmd_s           cn56xx;
+    struct cvmx_mio_fus_rcmd_s           cn56xxp1;
+    struct cvmx_mio_fus_rcmd_cn30xx      cn58xx;
+    struct cvmx_mio_fus_rcmd_cn30xx      cn58xxp1;
+} cvmx_mio_fus_rcmd_t;
+
+
+/**
+ * cvmx_mio_fus_spr_repair_res
+ *
+ * Notes:
+ * Pass3 Only
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_spr_repair_res_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_42_63          : 22;
+        uint64_t repair2                 : 14;      /**< SPR BISR Results */
+        uint64_t repair1                 : 14;      /**< SPR BISR Results */
+        uint64_t repair0                 : 14;      /**< SPR BISR Results */
+#else
+        uint64_t repair0                 : 14;
+        uint64_t repair1                 : 14;
+        uint64_t repair2                 : 14;
+        uint64_t reserved_42_63          : 22;
+#endif
+    } s;
+    struct cvmx_mio_fus_spr_repair_res_s cn30xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn31xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn38xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn50xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn52xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
+    struct cvmx_mio_fus_spr_repair_res_s cn56xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
+    struct cvmx_mio_fus_spr_repair_res_s cn58xx;
+    struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+} cvmx_mio_fus_spr_repair_res_t;
+
+
+/**
+ * cvmx_mio_fus_spr_repair_sum
+ *
+ * Notes:
+ * Pass3 Only
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_spr_repair_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t too_many                : 1;       /**< Too Many Defects - cannot repair - bad part */
+#else
+        uint64_t too_many                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
+    struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
+    struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
+    struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+} cvmx_mio_fus_spr_repair_sum_t;
+
+
+/**
+ * cvmx_mio_fus_unlock
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_unlock_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t key                     : 24;      /**< When set to the typical value, allows SW to
+                                                         program the efuses */
+#else
+        uint64_t key                     : 24;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_mio_fus_unlock_s         cn30xx;
+    struct cvmx_mio_fus_unlock_s         cn31xx;
+} cvmx_mio_fus_unlock_t;
+
+
+/**
+ * cvmx_mio_fus_wadr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_fus_wadr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t addr                    : 10;      /**< Which of the four banks of 256 fuses to blow */
+#else
+        uint64_t addr                    : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_mio_fus_wadr_s           cn30xx;
+    struct cvmx_mio_fus_wadr_s           cn31xx;
+    struct cvmx_mio_fus_wadr_s           cn38xx;
+    struct cvmx_mio_fus_wadr_s           cn38xxp2;
+    struct cvmx_mio_fus_wadr_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t addr                    : 2;       /**< Which of the four banks of 256 fuses to blow */
+#else
+        uint64_t addr                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn50xx;
+    struct cvmx_mio_fus_wadr_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t addr                    : 3;       /**< Which of the four banks of 256 fuses to blow */
+#else
+        uint64_t addr                    : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn52xx;
+    struct cvmx_mio_fus_wadr_cn52xx      cn52xxp1;
+    struct cvmx_mio_fus_wadr_cn52xx      cn56xx;
+    struct cvmx_mio_fus_wadr_cn52xx      cn56xxp1;
+    struct cvmx_mio_fus_wadr_cn50xx      cn58xx;
+    struct cvmx_mio_fus_wadr_cn50xx      cn58xxp1;
+} cvmx_mio_fus_wadr_t;
+
+
+/**
+ * cvmx_mio_ndf_dma_cfg
+ *
+ * MIO_NDF_DMA_CFG = MIO NAND Flash DMA Config Register
+ * 
+ * SIZE is specified in number of 64 bit transfers (encoded in -1 notation).
+ * 
+ * ADR must be 64 bit aligned.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_ndf_dma_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t en                      : 1;       /**< DMA Engine enable */
+        uint64_t rw                      : 1;       /**< DMA Engine R/W bit (0 = read, 1 = write) */
+        uint64_t clr                     : 1;       /**< DMA Engine clear EN on device terminated burst */
+        uint64_t reserved_60_60          : 1;
+        uint64_t swap32                  : 1;       /**< DMA Engine 32 bit swap */
+        uint64_t swap16                  : 1;       /**< DMA Engine 16 bit swap */
+        uint64_t swap8                   : 1;       /**< DMA Engine 8 bit swap */
+        uint64_t endian                  : 1;       /**< DMA Engine NCB endian mode (0 = big, 1 = little) */
+        uint64_t size                    : 20;      /**< DMA Engine size */
+        uint64_t adr                     : 36;      /**< DMA Engine address */
+#else
+        uint64_t adr                     : 36;
+        uint64_t size                    : 20;
+        uint64_t endian                  : 1;
+        uint64_t swap8                   : 1;
+        uint64_t swap16                  : 1;
+        uint64_t swap32                  : 1;
+        uint64_t reserved_60_60          : 1;
+        uint64_t clr                     : 1;
+        uint64_t rw                      : 1;
+        uint64_t en                      : 1;
+#endif
+    } s;
+    struct cvmx_mio_ndf_dma_cfg_s        cn52xx;
+} cvmx_mio_ndf_dma_cfg_t;
+
+
+/**
+ * cvmx_mio_ndf_dma_int
+ *
+ * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_ndf_dma_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t done                    : 1;       /**< DMA Engine request completion interrupt */
+#else
+        uint64_t done                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_ndf_dma_int_s        cn52xx;
+} cvmx_mio_ndf_dma_int_t;
+
+
+/**
+ * cvmx_mio_ndf_dma_int_en
+ *
+ * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_ndf_dma_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t done                    : 1;       /**< DMA Engine request completion interrupt enable */
+#else
+        uint64_t done                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_ndf_dma_int_en_s     cn52xx;
+} cvmx_mio_ndf_dma_int_en_t;
+
+
+/**
+ * cvmx_mio_pll_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_pll_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t bw_ctl                  : 5;       /**< Core PLL bandwidth control */
+#else
+        uint64_t bw_ctl                  : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_mio_pll_ctl_s            cn30xx;
+    struct cvmx_mio_pll_ctl_s            cn31xx;
+} cvmx_mio_pll_ctl_t;
+
+
+/**
+ * cvmx_mio_pll_setting
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_pll_setting_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t setting                 : 17;      /**< Core PLL setting */
+#else
+        uint64_t setting                 : 17;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_mio_pll_setting_s        cn30xx;
+    struct cvmx_mio_pll_setting_s        cn31xx;
+} cvmx_mio_pll_setting_t;
+
+
+/**
+ * cvmx_mio_tws#_int
+ *
+ * MIO_TWSX_INT = TWSX Interrupt Register
+ * 
+ * This register contains the TWSI interrupt enable mask and the interrupt source bits.  Note: the
+ * interrupt source bit for the TWSI core interrupt (CORE_INT) is read-only, the appropriate sequence
+ * must be written to the TWSI core to clear this interrupt.  The other interrupt source bits are write-
+ * one-to-clear.  TS_INT is set on the update of the MIO_TWS_TWSI_SW register (i.e. when it is written
+ * by a TWSI device).  ST_INT is set whenever the valid bit of the MIO_TWS_SW_TWSI is cleared (see above
+ * for reasons).
+ * 
+ * Note: When using the high-level controller, CORE_EN should be clear and CORE_INT should be ignored.
+ * Conversely, when the high-level controller is disabled, ST_EN / TS_EN should be clear and ST_INT /
+ * TS_INT should be ignored.
+ * 
+ * This register also contains a read-only copy of the TWSI bus (SCL and SDA) as well as control bits to
+ * override the current state of the TWSI bus (SCL_OVR and SDA_OVR).  Setting an override bit high will
+ * result in the open drain driver being activated, thus driving the corresponding signal low.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_twsx_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t scl                     : 1;       /**< SCL (NOT IN PASS1 OR PASS2) */
+        uint64_t sda                     : 1;       /**< SDA (NOT IN PASS1 OR PASS2) */
+        uint64_t scl_ovr                 : 1;       /**< SCL override (NOT IN PASS1 OR PASS2) */
+        uint64_t sda_ovr                 : 1;       /**< SDA override (NOT IN PASS1 OR PASS2) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t core_en                 : 1;       /**< TWSI core interrupt enable */
+        uint64_t ts_en                   : 1;       /**< MIO_TWS_TWSI_SW register update interrupt enable */
+        uint64_t st_en                   : 1;       /**< MIO_TWS_SW_TWSI register update interrupt enable */
+        uint64_t reserved_3_3            : 1;
+        uint64_t core_int                : 1;       /**< TWSI core interrupt */
+        uint64_t ts_int                  : 1;       /**< MIO_TWS_TWSI_SW register update interrupt */
+        uint64_t st_int                  : 1;       /**< MIO_TWS_SW_TWSI register update interrupt */
+#else
+        uint64_t st_int                  : 1;
+        uint64_t ts_int                  : 1;
+        uint64_t core_int                : 1;
+        uint64_t reserved_3_3            : 1;
+        uint64_t st_en                   : 1;
+        uint64_t ts_en                   : 1;
+        uint64_t core_en                 : 1;
+        uint64_t reserved_7_7            : 1;
+        uint64_t sda_ovr                 : 1;
+        uint64_t scl_ovr                 : 1;
+        uint64_t sda                     : 1;
+        uint64_t scl                     : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_mio_twsx_int_s           cn30xx;
+    struct cvmx_mio_twsx_int_s           cn31xx;
+    struct cvmx_mio_twsx_int_s           cn38xx;
+    struct cvmx_mio_twsx_int_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t core_en                 : 1;       /**< TWSI core interrupt enable */
+        uint64_t ts_en                   : 1;       /**< MIO_TWS_TWSI_SW register update interrupt enable */
+        uint64_t st_en                   : 1;       /**< MIO_TWS_SW_TWSI register update interrupt enable */
+        uint64_t reserved_3_3            : 1;
+        uint64_t core_int                : 1;       /**< TWSI core interrupt */
+        uint64_t ts_int                  : 1;       /**< MIO_TWS_TWSI_SW register update interrupt */
+        uint64_t st_int                  : 1;       /**< MIO_TWS_SW_TWSI register update interrupt */
+#else
+        uint64_t st_int                  : 1;
+        uint64_t ts_int                  : 1;
+        uint64_t core_int                : 1;
+        uint64_t reserved_3_3            : 1;
+        uint64_t st_en                   : 1;
+        uint64_t ts_en                   : 1;
+        uint64_t core_en                 : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } cn38xxp2;
+    struct cvmx_mio_twsx_int_s           cn50xx;
+    struct cvmx_mio_twsx_int_s           cn52xx;
+    struct cvmx_mio_twsx_int_s           cn52xxp1;
+    struct cvmx_mio_twsx_int_s           cn56xx;
+    struct cvmx_mio_twsx_int_s           cn56xxp1;
+    struct cvmx_mio_twsx_int_s           cn58xx;
+    struct cvmx_mio_twsx_int_s           cn58xxp1;
+} cvmx_mio_twsx_int_t;
+
+
+/**
+ * cvmx_mio_tws#_sw_twsi
+ *
+ * MIO_TWSX_SW_TWSI = TWSX Software to TWSI Register
+ * 
+ * This register allows software to
+ *    - initiate TWSI interface master-mode operations with a write and read the result with a read
+ *    - load four bytes for later retrieval (slave mode) with a write and check validity with a read
+ *    - launch a TWSI controller configuration read/write with a write and read the result with a read
+ * 
+ * This register should be read or written by software, and read by the TWSI device. The TWSI device can
+ * use either two-byte or five-byte reads to reference this register.
+ * 
+ * The TWSI device considers this register valid when V==1 and SLONLY==1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_twsx_sw_twsi_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t v                       : 1;       /**< Valid bit
+                                                         - Set on a write (should always be written with
+                                                           a 1)
+                                                         - Cleared when a TWSI master mode op completes
+                                                         - Cleared when a TWSI configuration register
+                                                           access completes
+                                                         - Cleared when the TWSI device reads the
+                                                           register if SLONLY==1 */
+        uint64_t slonly                  : 1;       /**< Slave Only Mode
+                                                         - No operation is initiated with a write when
+                                                           this bit is set - only D field is updated in
+                                                           this case
+                                                         - When clear, a write initiates either a TWSI
+                                                           master-mode operation or a TWSI configuration
+                                                           register access */
+        uint64_t eia                     : 1;       /**< Extended Internal Address - send additional
+                                                         internal address byte (MSB of IA is from IA field
+                                                         of MIO_TWS_SW_TWSI_EXT) (NOT IN PASS 1) */
+        uint64_t op                      : 4;       /**< Opcode field - When the register is written with
+                                                         SLONLY==0, initiate a read or write:
+                                                           0000 => 7-bit Byte Master Mode TWSI Op
+                                                           0001 => 7-bit Byte Combined Read Master Mode Op
+                                                                   7-bit Byte Write w/ IA Master Mode Op
+                                                           0010 => 10-bit Byte Master Mode TWSI Op
+                                                           0011 => 10-bit Byte Combined Read Master Mode Op
+                                                                   10-bit Byte Write w/ IA Master Mode Op
+                                                           0100 => TWSI Master Clock Register
+                                                           0110 => See EOP field
+                                                           1000 => 7-bit 4-byte Master Mode TWSI Op
+                                                           1001 => 7-bit 4-byte Comb. Read Master Mode Op
+                                                                   7-bit 4-byte Write w/ IA Master Mode Op
+                                                           1010 => 10-bit 4-byte Master Mode TWSI Op
+                                                           1011 => 10-bit 4-byte Comb. Read Master Mode Op
+                                                                   10-bit 4-byte Write w/ IA Master Mode Op */
+        uint64_t r                       : 1;       /**< Read bit or result
+                                                         - If set on a write when SLONLY==0, the
+                                                           operation is a read
+                                                         - On a read, this bit returns the result
+                                                           indication for the most recent master mode
+                                                           operation (1 = success, 0 = fail) */
+        uint64_t sovr                    : 1;       /**< Size Override - if set, use the SIZE field to
+                                                         determine Master Mode Op size rather than what
+                                                         the Opcode field specifies.  For operations
+                                                         greater than 4 bytes, the additional data will be
+                                                         contained in the D field of MIO_TWS_SW_TWSI_EXT
+                                                         (NOT IN PASS 1) */
+        uint64_t size                    : 3;       /**< Size in bytes of Master Mode Op if the Size
+                                                         Override bit is set.  Specified in -1 notation
+                                                         (i.e. 0 = 1 byte, 1 = 2 bytes ... 7 = 8 bytes)
+                                                         (NOT IN PASS 1) */
+        uint64_t scr                     : 2;       /**< Scratch - unused, but retain state */
+        uint64_t a                       : 10;      /**< Address field
+                                                         - the address of the remote device for a master
+                                                           mode operation
+                                                         - A<9:7> are only used for 10-bit addressing */
+        uint64_t ia                      : 5;       /**< Internal Address - Used when launching a master
+                                                         mode combined read / write with internal address
+                                                         (lower 3 bits are contained in the EOP_IA field) */
+        uint64_t eop_ia                  : 3;       /**< Extra opcode (when OP<3:0> == 0110 and SLONLY==0):
+                                                           000 => TWSI Slave Address Register
+                                                           001 => TWSI Data Register
+                                                           010 => TWSI Control Register
+                                                           011 => TWSI Clock Control Register (when R == 0)
+                                                           011 => TWSI Status Register (when R == 1)
+                                                           100 => TWSI Extended Slave Register
+                                                           111 => TWSI Soft Reset Register
+                                                         Also the lower 3 bits of Internal Address when
+                                                           launching a master mode combined read / write
+                                                           with internal address */
+        uint64_t d                       : 32;      /**< Data Field
+                                                         Used on a write when
+                                                           - initiating a master-mode write (SLONLY==0)
+                                                           - writing a TWSI config register (SLONLY==0)
+                                                           - a slave mode write (SLONLY==1)
+                                                         The read value is updated by
+                                                           - a write to this register
+                                                           - master mode completion (contains result or
+                                                             error code)
+                                                           - TWSI config register read (contains result) */
+#else
+        uint64_t d                       : 32;
+        uint64_t eop_ia                  : 3;
+        uint64_t ia                      : 5;
+        uint64_t a                       : 10;
+        uint64_t scr                     : 2;
+        uint64_t size                    : 3;
+        uint64_t sovr                    : 1;
+        uint64_t r                       : 1;
+        uint64_t op                      : 4;
+        uint64_t eia                     : 1;
+        uint64_t slonly                  : 1;
+        uint64_t v                       : 1;
+#endif
+    } s;
+    struct cvmx_mio_twsx_sw_twsi_s       cn30xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn31xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn38xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn38xxp2;
+    struct cvmx_mio_twsx_sw_twsi_s       cn50xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn52xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn52xxp1;
+    struct cvmx_mio_twsx_sw_twsi_s       cn56xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn56xxp1;
+    struct cvmx_mio_twsx_sw_twsi_s       cn58xx;
+    struct cvmx_mio_twsx_sw_twsi_s       cn58xxp1;
+} cvmx_mio_twsx_sw_twsi_t;
+
+
+/**
+ * cvmx_mio_tws#_sw_twsi_ext
+ *
+ * MIO_TWSX_SW_TWSI_EXT = TWSX Software to TWSI Extension Register
+ * 
+ * This register contains an additional byte of internal address and 4 additional bytes of data to be
+ * used with TWSI master mode operations.  IA will be sent as the first byte of internal address when
+ * performing master mode combined read / write with internal address operations and the EIA bit of
+ * MIO_TWS_SW_TWSI is set.  D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR
+ * must be set to perform operations greater than 4 bytes).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_twsx_sw_twsi_ext_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t ia                      : 8;       /**< Extended Internal Address */
+        uint64_t d                       : 32;      /**< Extended Data Field */
+#else
+        uint64_t d                       : 32;
+        uint64_t ia                      : 8;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn30xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn31xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn38xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn38xxp2;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn50xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn52xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn52xxp1;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn56xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn56xxp1;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn58xx;
+    struct cvmx_mio_twsx_sw_twsi_ext_s   cn58xxp1;
+} cvmx_mio_twsx_sw_twsi_ext_t;
+
+
+/**
+ * cvmx_mio_tws#_twsi_sw
+ *
+ * MIO_TWSX_TWSI_SW = TWSX TWSI to Software Register
+ * 
+ * This register allows the TWSI device to transfer data to software and later check that software has
+ * received the information.
+ * 
+ * This register should be read or written by the TWSI device, and read by software. The TWSI device can
+ * use one-byte or four-byte payload writes, and two-byte payload reads.
+ * 
+ * The TWSI device considers this register valid when V==1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_twsx_twsi_sw_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t v                       : 2;       /**< Valid Bits
+                                                         - Not directly writable
+                                                         - Set to 1 on any write by the TWSI device
+                                                         - Cleared on any read by software */
+        uint64_t reserved_32_61          : 30;
+        uint64_t d                       : 32;      /**< Data Field - updated on a write by the TWSI device */
+#else
+        uint64_t d                       : 32;
+        uint64_t reserved_32_61          : 30;
+        uint64_t v                       : 2;
+#endif
+    } s;
+    struct cvmx_mio_twsx_twsi_sw_s       cn30xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn31xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn38xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn38xxp2;
+    struct cvmx_mio_twsx_twsi_sw_s       cn50xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn52xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn52xxp1;
+    struct cvmx_mio_twsx_twsi_sw_s       cn56xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn56xxp1;
+    struct cvmx_mio_twsx_twsi_sw_s       cn58xx;
+    struct cvmx_mio_twsx_twsi_sw_s       cn58xxp1;
+} cvmx_mio_twsx_twsi_sw_t;
+
+
+/**
+ * cvmx_mio_uart#_dlh
+ *
+ * MIO_UARTX_DLH = MIO UARTX Divisor Latch High Register
+ * 
+ * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
+ * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
+ * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
+ * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
+ * follows: baud rate = eclk / (16 * divisor).
+ * 
+ * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
+ * register. BUSY bit is always clear in PASS3.
+ * 
+ * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
+ * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
+ * of eclk should be allowed to pass before transmitting or receiving data.
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IER and DLH registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_dlh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dlh                     : 8;       /**< Divisor Latch High Register */
+#else
+        uint64_t dlh                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_dlh_s          cn30xx;
+    struct cvmx_mio_uartx_dlh_s          cn31xx;
+    struct cvmx_mio_uartx_dlh_s          cn38xx;
+    struct cvmx_mio_uartx_dlh_s          cn38xxp2;
+    struct cvmx_mio_uartx_dlh_s          cn50xx;
+    struct cvmx_mio_uartx_dlh_s          cn52xx;
+    struct cvmx_mio_uartx_dlh_s          cn52xxp1;
+    struct cvmx_mio_uartx_dlh_s          cn56xx;
+    struct cvmx_mio_uartx_dlh_s          cn56xxp1;
+    struct cvmx_mio_uartx_dlh_s          cn58xx;
+    struct cvmx_mio_uartx_dlh_s          cn58xxp1;
+} cvmx_mio_uartx_dlh_t;
+typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t;
+
+
+/**
+ * cvmx_mio_uart#_dll
+ *
+ * MIO_UARTX_DLL = MIO UARTX Divisor Latch Low Register
+ * 
+ * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a
+ * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is
+ * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud
+ * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as
+ * follows: baud rate = eclk / (16 * divisor).
+ * 
+ * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this
+ * register. BUSY bit is always clear in PASS3.
+ * 
+ * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled
+ * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles
+ * of eclk should be allowed to pass before transmitting or receiving data.
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * RBR, THR, and DLL registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_dll_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dll                     : 8;       /**< Divisor Latch Low Register */
+#else
+        uint64_t dll                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_dll_s          cn30xx;
+    struct cvmx_mio_uartx_dll_s          cn31xx;
+    struct cvmx_mio_uartx_dll_s          cn38xx;
+    struct cvmx_mio_uartx_dll_s          cn38xxp2;
+    struct cvmx_mio_uartx_dll_s          cn50xx;
+    struct cvmx_mio_uartx_dll_s          cn52xx;
+    struct cvmx_mio_uartx_dll_s          cn52xxp1;
+    struct cvmx_mio_uartx_dll_s          cn56xx;
+    struct cvmx_mio_uartx_dll_s          cn56xxp1;
+    struct cvmx_mio_uartx_dll_s          cn58xx;
+    struct cvmx_mio_uartx_dll_s          cn58xxp1;
+} cvmx_mio_uartx_dll_t;
+typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t;
+
+
+/**
+ * cvmx_mio_uart#_far
+ *
+ * MIO_UARTX_FAR = MIO UARTX FIFO Access Register
+ * 
+ * The FIFO Access Register (FAR) is used to enable a FIFO access mode for testing, so that the receive
+ * FIFO can be written by software and the transmit FIFO can be read by software when the FIFOs are
+ * enabled. When FIFOs are not enabled it allows the RBR to be written by software and the THR to be read
+ * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the
+ * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_far_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t far                     : 1;       /**< FIFO Access Register */
+#else
+        uint64_t far                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uartx_far_s          cn30xx;
+    struct cvmx_mio_uartx_far_s          cn31xx;
+    struct cvmx_mio_uartx_far_s          cn38xx;
+    struct cvmx_mio_uartx_far_s          cn38xxp2;
+    struct cvmx_mio_uartx_far_s          cn50xx;
+    struct cvmx_mio_uartx_far_s          cn52xx;
+    struct cvmx_mio_uartx_far_s          cn52xxp1;
+    struct cvmx_mio_uartx_far_s          cn56xx;
+    struct cvmx_mio_uartx_far_s          cn56xxp1;
+    struct cvmx_mio_uartx_far_s          cn58xx;
+    struct cvmx_mio_uartx_far_s          cn58xxp1;
+} cvmx_mio_uartx_far_t;
+typedef cvmx_mio_uartx_far_t cvmx_uart_far_t;
+
+
+/**
+ * cvmx_mio_uart#_fcr
+ *
+ * MIO_UARTX_FCR = MIO UARTX FIFO Control Register
+ * 
+ * The FIFO Control Register (FCR) is a write-only register that controls the read and write data FIFO
+ * operation. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls
+ * the THRE Interrupt empty threshold level.
+ * 
+ * Setting bit 0 of the FCR enables the transmit and receive FIFOs. Whenever the value of this bit is
+ * changed both the TX and RX FIFOs will be reset.
+ * 
+ * Writing a '1' to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is
+ * self-clearing and it is not necessary to clear this bit.
+ * 
+ * Writing a '1' to bit 2 of the FCR resets and flushes data in the transmit FIFO. Note that this bit is
+ * self-clearing and it is not necessary to clear this bit.
+ * 
+ * If the FIFOs and Programmable THRE Interrupt mode are enabled, bits 4 and 5 control the empty
+ * threshold level at which THRE Interrupts are generated when the mode is active.  See the following
+ * table for encodings:
+ * 
+ * TX Trigger
+ * ----------
+ * 00 = empty FIFO
+ * 01 = 2 chars in FIFO
+ * 10 = FIFO 1/4 full
+ * 11 = FIFO 1/2 full
+ * 
+ * If the FIFO mode is enabled (bit 0 of the FCR is set to '1') bits 6 and 7 are active. Bit 6 and bit 7
+ * set the trigger level in the receiver FIFO for the Enable Received Data Available Interrupt (ERBFI).
+ * In auto flow control mode the trigger is used to determine when the rts_n signal will be deasserted.
+ * See the following table for encodings:
+ * 
+ * RX Trigger
+ * ----------
+ * 00 = 1 char in FIFO
+ * 01 = FIFO 1/4 full
+ * 10 = FIFO 1/2 full
+ * 11 = FIFO 2 chars less than full
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IIR and FCR registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_fcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rxtrig                  : 2;       /**< RX Trigger */
+        uint64_t txtrig                  : 2;       /**< TX Trigger */
+        uint64_t reserved_3_3            : 1;
+        uint64_t txfr                    : 1;       /**< TX FIFO reset */
+        uint64_t rxfr                    : 1;       /**< RX FIFO reset */
+        uint64_t en                      : 1;       /**< FIFO enable */
+#else
+        uint64_t en                      : 1;
+        uint64_t rxfr                    : 1;
+        uint64_t txfr                    : 1;
+        uint64_t reserved_3_3            : 1;
+        uint64_t txtrig                  : 2;
+        uint64_t rxtrig                  : 2;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_fcr_s          cn30xx;
+    struct cvmx_mio_uartx_fcr_s          cn31xx;
+    struct cvmx_mio_uartx_fcr_s          cn38xx;
+    struct cvmx_mio_uartx_fcr_s          cn38xxp2;
+    struct cvmx_mio_uartx_fcr_s          cn50xx;
+    struct cvmx_mio_uartx_fcr_s          cn52xx;
+    struct cvmx_mio_uartx_fcr_s          cn52xxp1;
+    struct cvmx_mio_uartx_fcr_s          cn56xx;
+    struct cvmx_mio_uartx_fcr_s          cn56xxp1;
+    struct cvmx_mio_uartx_fcr_s          cn58xx;
+    struct cvmx_mio_uartx_fcr_s          cn58xxp1;
+} cvmx_mio_uartx_fcr_t;
+typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t;
+
+
+/**
+ * cvmx_mio_uart#_htx
+ *
+ * MIO_UARTX_HTX = MIO UARTX Halt TX Register
+ * 
+ * The Halt TX Register (HTX) is used to halt transmissions for testing, so that the transmit FIFO can be
+ * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will
+ * have no effect.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_htx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t htx                     : 1;       /**< Halt TX */
+#else
+        uint64_t htx                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uartx_htx_s          cn30xx;
+    struct cvmx_mio_uartx_htx_s          cn31xx;
+    struct cvmx_mio_uartx_htx_s          cn38xx;
+    struct cvmx_mio_uartx_htx_s          cn38xxp2;
+    struct cvmx_mio_uartx_htx_s          cn50xx;
+    struct cvmx_mio_uartx_htx_s          cn52xx;
+    struct cvmx_mio_uartx_htx_s          cn52xxp1;
+    struct cvmx_mio_uartx_htx_s          cn56xx;
+    struct cvmx_mio_uartx_htx_s          cn56xxp1;
+    struct cvmx_mio_uartx_htx_s          cn58xx;
+    struct cvmx_mio_uartx_htx_s          cn58xxp1;
+} cvmx_mio_uartx_htx_t;
+typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t;
+
+
+/**
+ * cvmx_mio_uart#_ier
+ *
+ * MIO_UARTX_IER = MIO UARTX Interrupt Enable Register
+ * 
+ * Interrupt Enable Register (IER) is a read/write register that contains four bits that enable
+ * the generation of interrupts. These four bits are the Enable Received Data Available Interrupt
+ * (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line
+ * Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI).
+ * 
+ * The IER also contains an enable bit (PTIME) for the Programmable THRE Interrupt mode.
+ * 
+ * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
+ * this register.
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IER and DLH registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_ier_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ptime                   : 1;       /**< Programmable THRE Interrupt mode enable */
+        uint64_t reserved_4_6            : 3;
+        uint64_t edssi                   : 1;       /**< Enable Modem Status Interrupt */
+        uint64_t elsi                    : 1;       /**< Enable Receiver Line Status Interrupt */
+        uint64_t etbei                   : 1;       /**< Enable Transmitter Holding Register Empty Interrupt */
+        uint64_t erbfi                   : 1;       /**< Enable Received Data Available Interrupt */
+#else
+        uint64_t erbfi                   : 1;
+        uint64_t etbei                   : 1;
+        uint64_t elsi                    : 1;
+        uint64_t edssi                   : 1;
+        uint64_t reserved_4_6            : 3;
+        uint64_t ptime                   : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_ier_s          cn30xx;
+    struct cvmx_mio_uartx_ier_s          cn31xx;
+    struct cvmx_mio_uartx_ier_s          cn38xx;
+    struct cvmx_mio_uartx_ier_s          cn38xxp2;
+    struct cvmx_mio_uartx_ier_s          cn50xx;
+    struct cvmx_mio_uartx_ier_s          cn52xx;
+    struct cvmx_mio_uartx_ier_s          cn52xxp1;
+    struct cvmx_mio_uartx_ier_s          cn56xx;
+    struct cvmx_mio_uartx_ier_s          cn56xxp1;
+    struct cvmx_mio_uartx_ier_s          cn58xx;
+    struct cvmx_mio_uartx_ier_s          cn58xxp1;
+} cvmx_mio_uartx_ier_t;
+typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t;
+
+
+/**
+ * cvmx_mio_uart#_iir
+ *
+ * MIO_UARTX_IIR = MIO UARTX Interrupt Identity Register
+ * 
+ * The Interrupt Identity Register (IIR) is a read-only register that identifies the source of an
+ * interrupt. The upper two bits of the register are FIFO-enabled bits. These bits are '00' if the FIFOs
+ * are disabled, and '11' if they are enabled. The lower four bits identify the highest priority pending
+ * interrupt. The following table defines interrupt source decoding, interrupt priority, and interrupt
+ * reset control:
+ * 
+ * Interrupt   Priority   Interrupt         Interrupt                                       Interrupt
+ * ID          Level      Type              Source                                          Reset By
+ * ---------------------------------------------------------------------------------------------------------------------------------
+ * 0001        -          None              None                                            -
+ * 
+ * 0110        Highest    Receiver Line     Overrun, parity, or framing errors or break     Reading the Line Status Register
+ *                        Status            interrupt
+ * 
+ * 0100        Second     Received Data     Receiver data available (FIFOs disabled) or     Reading the Receiver Buffer Register
+ *                        Available         RX FIFO trigger level reached (FIFOs            (FIFOs disabled) or the FIFO drops below
+ *                                          enabled)                                        the trigger level (FIFOs enabled)
+ * 
+ * 1100        Second     Character         No characters in or out of the RX FIFO          Reading the Receiver Buffer Register
+ *                        Timeout           during the last 4 character times and there
+ *                        Indication        is at least 1 character in it during this
+ *                                          time
+ * 
+ * 0010        Third      Transmitter       Transmitter Holding Register Empty              Reading the Interrupt Identity Register
+ *                        Holding           (Programmable THRE Mode disabled) or TX         (if source of interrupt) or writing into
+ *                        Register          FIFO at or below threshold (Programmable        THR (FIFOs or THRE Mode disabled) or TX
+ *                        Empty             THRE Mode enabled)                              FIFO above threshold (FIFOs and THRE
+ *                                                                                          Mode enabled)
+ * 
+ * 0000        Fourth     Modem Status      Clear To Send (CTS) or Data Set Ready (DSR)     Reading the Modem Status Register
+ *                        Changed           or Ring Indicator (RI) or Data Carrier
+ *                                          Detect (DCD) changed (note: if auto flow
+ *                                          control mode is enabled, a change in CTS
+ *                                          will not cause an interrupt)
+ * 
+ * 0111        Fifth      Busy Detect       Software has tried to write to the Line         Reading the UART Status Register
+ *                        Indication        Control Register while the BUSY bit of the
+ *                                          UART Status Register was set
+ * 
+ * Note: The Busy Detect Indication interrupt has been removed from PASS3 and will never assert.
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * IIR and FCR registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_iir_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t fen                     : 2;       /**< FIFO-enabled bits */
+        uint64_t reserved_4_5            : 2;
+        cvmx_uart_iid_t iid              : 4;       /**< Interrupt ID */
+#else
+        cvmx_uart_iid_t iid              : 4;
+        uint64_t reserved_4_5            : 2;
+        uint64_t fen                     : 2;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_iir_s          cn30xx;
+    struct cvmx_mio_uartx_iir_s          cn31xx;
+    struct cvmx_mio_uartx_iir_s          cn38xx;
+    struct cvmx_mio_uartx_iir_s          cn38xxp2;
+    struct cvmx_mio_uartx_iir_s          cn50xx;
+    struct cvmx_mio_uartx_iir_s          cn52xx;
+    struct cvmx_mio_uartx_iir_s          cn52xxp1;
+    struct cvmx_mio_uartx_iir_s          cn56xx;
+    struct cvmx_mio_uartx_iir_s          cn56xxp1;
+    struct cvmx_mio_uartx_iir_s          cn58xx;
+    struct cvmx_mio_uartx_iir_s          cn58xxp1;
+} cvmx_mio_uartx_iir_t;
+typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t;
+
+
+/**
+ * cvmx_mio_uart#_lcr
+ *
+ * MIO_UARTX_LCR = MIO UARTX Line Control Register
+ * 
+ * The Line Control Register (LCR) controls the format of the data that is transmitted and received by
+ * the UART.
+ * 
+ * LCR bits 0 and 1 are the Character Length Select field. This field is used to select the number of
+ * data bits per character that are transmitted and received. See the following table for encodings:
+ * 
+ * CLS
+ * ---
+ * 00 = 5 bits (bits 0-4 sent)
+ * 01 = 6 bits (bits 0-5 sent)
+ * 10 = 7 bits (bits 0-6 sent)
+ * 11 = 8 bits (all bits sent)
+ * 
+ * LCR bit 2 controls the number of stop bits transmitted. If bit 2 is a '0', one stop bit is transmitted
+ * in the serial data. If bit 2 is a '1' and the data bits are set to '00', one and a half stop bits are
+ * generated. Otherwise, two stop bits are generated and transmitted in the serial data out. Note that
+ * regardless of the number of stop bits selected the receiver will only check the first stop bit.
+ * 
+ * LCR bit 3 is the Parity Enable bit. This bit is used to enable and disable parity generation and
+ * detection in transmitted and received serial character respectively.
+ * 
+ * LCR bit 4 is the Even Parity Select bit. If parity is enabled, bit 4 selects between even and odd
+ * parity. If bit 4 is a '1', an even number of ones is transmitted or checked. If bit 4 is a '0', an odd
+ * number of ones is transmitted or checked.
+ * 
+ * LCR bit 6 is the Break Control bit. Setting the Break bit sends a break signal by holding the sout
+ * line low (when not in Loopback mode, as determined by Modem Control Register bit 4). When in Loopback
+ * mode, the break condition is internally looped back to the receiver.
+ * 
+ * LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the
+ * Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after
+ * initial baud rate setup in order to access other registers.
+ * 
+ * Note: The LCR is writeable only when the UART is not busy (when the BUSY bit (bit 0) of the UART
+ * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable
+ * because the BUSY bit is always clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_lcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dlab                    : 1;       /**< Divisor Latch Address bit */
+        uint64_t brk                     : 1;       /**< Break Control bit */
+        uint64_t reserved_5_5            : 1;
+        uint64_t eps                     : 1;       /**< Even Parity Select bit */
+        uint64_t pen                     : 1;       /**< Parity Enable bit */
+        uint64_t stop                    : 1;       /**< Stop Control bit */
+        cvmx_uart_bits_t cls             : 2;       /**< Character Length Select */
+#else
+        cvmx_uart_bits_t cls             : 2;
+        uint64_t stop                    : 1;
+        uint64_t pen                     : 1;
+        uint64_t eps                     : 1;
+        uint64_t reserved_5_5            : 1;
+        uint64_t brk                     : 1;
+        uint64_t dlab                    : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_lcr_s          cn30xx;
+    struct cvmx_mio_uartx_lcr_s          cn31xx;
+    struct cvmx_mio_uartx_lcr_s          cn38xx;
+    struct cvmx_mio_uartx_lcr_s          cn38xxp2;
+    struct cvmx_mio_uartx_lcr_s          cn50xx;
+    struct cvmx_mio_uartx_lcr_s          cn52xx;
+    struct cvmx_mio_uartx_lcr_s          cn52xxp1;
+    struct cvmx_mio_uartx_lcr_s          cn56xx;
+    struct cvmx_mio_uartx_lcr_s          cn56xxp1;
+    struct cvmx_mio_uartx_lcr_s          cn58xx;
+    struct cvmx_mio_uartx_lcr_s          cn58xxp1;
+} cvmx_mio_uartx_lcr_t;
+typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t;
+
+
+/**
+ * cvmx_mio_uart#_lsr
+ *
+ * MIO_UARTX_LSR = MIO UARTX Line Status Register
+ * 
+ * The Line Status Register (LSR) contains status of the receiver and transmitter data transfers. This
+ * status can be read by the user at anytime.
+ * 
+ * LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one
+ * character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO
+ * mode, or when the receiver FIFO is empty, in FIFO mode.
+ * 
+ * LSR bit 1 is the Overrun Error (OE) bit. When set, this bit indicates an overrun error has occurred
+ * because a new data character was received before the previous data was read. In the non-FIFO mode, the
+ * OE bit is set when a new character arrives in the receiver before the previous character was read from
+ * the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error
+ * occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is
+ * retained and the data in the receive shift register is lost.
+ * 
+ * LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the
+ * receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is
+ * associated with a character received, it is revealed when the character with the parity error arrives
+ * at the top of the FIFO. It should be noted that the Parity Error (PE) bit will be set if a break
+ * interrupt has occurred, as indicated by the Break Interrupt (BI) bit.
+ * 
+ * LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the
+ * receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received
+ * data. In the FIFO mode, since the framing error is associated with a character received, it is
+ * revealed when the character with the framing error is at the top of the FIFO. When a framing error
+ * occurs the UART will try resynchronize. It does this by assuming that the error was due to the start
+ * bit of the next character and then continues receiving the other bits (i.e. data and/or parity and
+ * stop). It should be noted that the Framing Error (FE) bit will be set if a break interrupt has
+ * occurred, as indicated by the Break Interrupt (BI) bit.
+ * 
+ * Note: The OE, PE, and FE bits are reset when a read of the LSR is performed.
+ * 
+ * LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in
+ * a 0 state for longer than the sum of start time + data bits + parity + stop bits. A break condition on
+ * sin causes one and only one character, consisting of all zeros, to be received by the UART. In the
+ * FIFO mode, the character associated with the break condition is carried through the FIFO and is
+ * revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-
+ * FIFO mode, the BI indication occurs immediately and persists until the LSR is read.
+ * 
+ * LSR bit 5 is the Transmitter Holding Register Empty (THRE) bit. When Programmable THRE Interrupt mode
+ * is disabled, this bit indicates that the UART can accept a new character for transmission. This bit is
+ * set whenever data is transferred from the THR (or TX FIFO) to the transmitter shift register and no
+ * new data has been written to the THR (or TX FIFO). This also causes a THRE Interrupt to occur, if the
+ * THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode are enabled, LSR bit 5
+ * functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE
+ * Interrupts, which are then controlled by the FCR[5:4] threshold setting.
+ * 
+ * LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the
+ * Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever
+ * the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is
+ * typically used to make sure it is safe to change control registers. Changing control registers while
+ * the transmitter is busy can result in corrupt data being transmitted.
+ * 
+ * LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is active only when FIFOs are enabled. It
+ * is set when there is at least one parity error, framing error, or break indication in the FIFO. This
+ * bit is cleared when the LSR is read and the character with the error is at the top of the receiver
+ * FIFO and there are no subsequent errors in the FIFO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_lsr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ferr                    : 1;       /**< Error in Receiver FIFO bit */
+        uint64_t temt                    : 1;       /**< Transmitter Empty bit */
+        uint64_t thre                    : 1;       /**< Transmitter Holding Register Empty bit */
+        uint64_t bi                      : 1;       /**< Break Interrupt bit */
+        uint64_t fe                      : 1;       /**< Framing Error bit */
+        uint64_t pe                      : 1;       /**< Parity Error bit */
+        uint64_t oe                      : 1;       /**< Overrun Error bit */
+        uint64_t dr                      : 1;       /**< Data Ready bit */
+#else
+        uint64_t dr                      : 1;
+        uint64_t oe                      : 1;
+        uint64_t pe                      : 1;
+        uint64_t fe                      : 1;
+        uint64_t bi                      : 1;
+        uint64_t thre                    : 1;
+        uint64_t temt                    : 1;
+        uint64_t ferr                    : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_lsr_s          cn30xx;
+    struct cvmx_mio_uartx_lsr_s          cn31xx;
+    struct cvmx_mio_uartx_lsr_s          cn38xx;
+    struct cvmx_mio_uartx_lsr_s          cn38xxp2;
+    struct cvmx_mio_uartx_lsr_s          cn50xx;
+    struct cvmx_mio_uartx_lsr_s          cn52xx;
+    struct cvmx_mio_uartx_lsr_s          cn52xxp1;
+    struct cvmx_mio_uartx_lsr_s          cn56xx;
+    struct cvmx_mio_uartx_lsr_s          cn56xxp1;
+    struct cvmx_mio_uartx_lsr_s          cn58xx;
+    struct cvmx_mio_uartx_lsr_s          cn58xxp1;
+} cvmx_mio_uartx_lsr_t;
+typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t;
+
+
+/**
+ * cvmx_mio_uart#_mcr
+ *
+ * MIO_UARTX_MCR = MIO UARTX Modem Control Register
+ * 
+ * The lower four bits of the Modem Control Register (MCR) directly manipulate the outputs of the UART.
+ * The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the
+ * corresponding UART outputs, dtr_n, rts_n, out1_n, and out2_n.  In loopback mode, these outputs are
+ * driven inactive high while the values in these locations are internally looped back to the inputs.
+ * 
+ * Note: When Auto RTS is enabled, the rts_n output is controlled in the same way, but is also gated
+ * with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The
+ * rts_n output will be de-asserted whenever RTS (bit 1) is set low.
+ * 
+ * Note: The UART0 out1_n and out2_n outputs are not present on the pins of the chip, but the UART0 OUT1
+ * and OUT2 bits still function in Loopback mode.  The UART1 dtr_n, out1_n, and out2_n outputs are not
+ * present on the pins of the chip, but the UART1 DTR, OUT1, and OUT2 bits still function in Loopback
+ * mode.
+ * 
+ * MCR bit 4 is the Loopback bit. When set, data on the sout line is held high, while serial data output
+ * is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This
+ * feature is used for diagnostic purposes. Also, in loopback mode, the modem control inputs (dsr_n,
+ * cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n)
+ * are looped back to the inputs, internally.
+ * 
+ * MCR bit 5 is the Auto Flow Control Enable (AFCE) bit. When FIFOs are enabled and this bit is set,
+ * 16750-compatible Auto RTS and Auto CTS serial data flow control features are enabled.
+ * 
+ * Auto RTS becomes active when the following occurs:
+ * 1. MCR bit 1 is set
+ * 2. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
+ * 3. MCR bit 5 is set (must be set after FCR bit 0)
+ * 
+ * When active, the rts_n output is forced inactive-high when the receiver FIFO level reaches the
+ * threshold set by FCR[7:6]. When rts_n is connected to the cts_n input of another UART device, the
+ * other UART stops sending serial data until the receiver FIFO has available space.
+ * 
+ * The selectable receiver FIFO threshold values are: 1, 1/4, 1/2, and 2 less than full. Since one
+ * additional character may be transmitted to the UART after rts_n has become inactive (due to data
+ * already having entered the transmitter block in the other UART), setting the threshold to 2 less
+ * than full allows maximum use of the FIFO with a safety zone of one character.
+ * 
+ * Once the receiver FIFO becomes completely empty by reading the Receiver Buffer Register (RBR), rts_n
+ * again becomes active-low, signalling the other UART to continue sending data. It is important to note
+ * that, even if everything else is set to Enabled and the correct MCR bits are set, if the FIFOs are
+ * disabled through FCR[0], Auto Flow Control is also disabled. When Auto RTS is disabled or inactive,
+ * rts_n is controlled solely by MCR[1].
+ * 
+ * Auto CTS becomes active when the following occurs:
+ * 1. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0
+ * 2. MCR bit 5 is set (must be set after FCR bit 0)
+ * 
+ * When active, the UART transmitter is disabled whenever the cts_n input becomes inactive-high. This
+ * prevents overflowing the FIFO of the receiving UART.
+ * 
+ * Note that, if the cts_n input is not inactivated before the middle of the last stop bit, another
+ * character is transmitted before the transmitter is disabled. While the transmitter is disabled, the
+ * transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, either
+ * the true FIFO depth (64 characters) must be known to software, or the Programmable THRE Interrupt mode
+ * must be enabled to access the FIFO full status through the Line Status Register. When using the FIFO
+ * full status, software can poll this before each write to the Transmitter FIFO.
+ * 
+ * Note: FIFO full status is also available in the UART Status Register (USR) or the actual level of the
+ * FIFO may be read through the Transmit FIFO Level (TFL) register.
+ * 
+ * When the cts_n input becomes active-low again, transmission resumes. It is important to note that,
+ * even if everything else is set to Enabled, Auto Flow Control is also disabled if the FIFOs are
+ * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by
+ * cts_n.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_mcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t afce                    : 1;       /**< Auto Flow Control Enable bit */
+        uint64_t loop                    : 1;       /**< Loopback bit */
+        uint64_t out2                    : 1;       /**< OUT2 output bit */
+        uint64_t out1                    : 1;       /**< OUT1 output bit */
+        uint64_t rts                     : 1;       /**< Request To Send output bit */
+        uint64_t dtr                     : 1;       /**< Data Terminal Ready output bit */
+#else
+        uint64_t dtr                     : 1;
+        uint64_t rts                     : 1;
+        uint64_t out1                    : 1;
+        uint64_t out2                    : 1;
+        uint64_t loop                    : 1;
+        uint64_t afce                    : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_mio_uartx_mcr_s          cn30xx;
+    struct cvmx_mio_uartx_mcr_s          cn31xx;
+    struct cvmx_mio_uartx_mcr_s          cn38xx;
+    struct cvmx_mio_uartx_mcr_s          cn38xxp2;
+    struct cvmx_mio_uartx_mcr_s          cn50xx;
+    struct cvmx_mio_uartx_mcr_s          cn52xx;
+    struct cvmx_mio_uartx_mcr_s          cn52xxp1;
+    struct cvmx_mio_uartx_mcr_s          cn56xx;
+    struct cvmx_mio_uartx_mcr_s          cn56xxp1;
+    struct cvmx_mio_uartx_mcr_s          cn58xx;
+    struct cvmx_mio_uartx_mcr_s          cn58xxp1;
+} cvmx_mio_uartx_mcr_t;
+typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t;
+
+
+/**
+ * cvmx_mio_uart#_msr
+ *
+ * MIO_UARTX_MSR = MIO UARTX Modem Status Register
+ * 
+ * The Modem Status Register (MSR) contains the current status of the modem control input lines and if
+ * they changed.
+ * 
+ * DCTS (bit 0), DDSR (bit 1), and DDCD (bit 3) bits record whether the modem control lines (cts_n,
+ * dsr_n, and dcd_n) have changed since the last time the user read the MSR. TERI (bit 2) indicates ri_n
+ * has changed from an active-low, to an inactive-high state since the last time the MSR was read. In
+ * Loopback mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR), and
+ * DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state
+ * from a high to a low.
+ * 
+ * Note: if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software
+ * or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains
+ * asserted.
+ * 
+ * The CTS, DSR, RI, and DCD Modem Status bits contain information on the current state of the modem
+ * control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI
+ * (bit 6) is the compliment of ri_n, and DCD (bit 7) is the compliment of dcd_n. In Loopback mode, CTS
+ * is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2
+ * (Out1), and DCD is the same as MCR bit 3 (Out2).
+ * 
+ * Note: The UART0 dsr_n and ri_n inputs are internally tied to power and not present on the pins of chip.
+ * Thus the UART0 DSR and RI bits will be '0' when not in Loopback mode.  The UART1 dsr_n, ri_n, and dcd_n
+ * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and
+ * DCD bits will be '0' when not in Loopback mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_msr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dcd                     : 1;       /**< Data Carrier Detect input bit */
+        uint64_t ri                      : 1;       /**< Ring Indicator input bit */
+        uint64_t dsr                     : 1;       /**< Data Set Ready input bit */
+        uint64_t cts                     : 1;       /**< Clear To Send input bit */
+        uint64_t ddcd                    : 1;       /**< Delta Data Carrier Detect bit */
+        uint64_t teri                    : 1;       /**< Trailing Edge of Ring Indicator bit */
+        uint64_t ddsr                    : 1;       /**< Delta Data Set Ready bit */
+        uint64_t dcts                    : 1;       /**< Delta Clear To Send bit */
+#else
+        uint64_t dcts                    : 1;
+        uint64_t ddsr                    : 1;
+        uint64_t teri                    : 1;
+        uint64_t ddcd                    : 1;
+        uint64_t cts                     : 1;
+        uint64_t dsr                     : 1;
+        uint64_t ri                      : 1;
+        uint64_t dcd                     : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_msr_s          cn30xx;
+    struct cvmx_mio_uartx_msr_s          cn31xx;
+    struct cvmx_mio_uartx_msr_s          cn38xx;
+    struct cvmx_mio_uartx_msr_s          cn38xxp2;
+    struct cvmx_mio_uartx_msr_s          cn50xx;
+    struct cvmx_mio_uartx_msr_s          cn52xx;
+    struct cvmx_mio_uartx_msr_s          cn52xxp1;
+    struct cvmx_mio_uartx_msr_s          cn56xx;
+    struct cvmx_mio_uartx_msr_s          cn56xxp1;
+    struct cvmx_mio_uartx_msr_s          cn58xx;
+    struct cvmx_mio_uartx_msr_s          cn58xxp1;
+} cvmx_mio_uartx_msr_t;
+typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t;
+
+
+/**
+ * cvmx_mio_uart#_rbr
+ *
+ * MIO_UARTX_RBR = MIO UARTX Receive Buffer Register
+ * 
+ * The Receive Buffer Register (RBR) is a read-only register that contains the data byte received on the
+ * serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the
+ * Line status Register (LSR) is set. When the FIFOs are programmed OFF, the data in the RBR must be
+ * read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. When
+ * the FIFOs are programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO
+ * is full (64 characters) and this register is not read before the next data character arrives, then the
+ * data already in the FIFO is preserved, but any incoming data is lost. An overrun error also occurs.
+ * 
+ * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
+ * this register.
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * RBR, THR, and DLL registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_rbr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rbr                     : 8;       /**< Receive Buffer Register */
+#else
+        uint64_t rbr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_rbr_s          cn30xx;
+    struct cvmx_mio_uartx_rbr_s          cn31xx;
+    struct cvmx_mio_uartx_rbr_s          cn38xx;
+    struct cvmx_mio_uartx_rbr_s          cn38xxp2;
+    struct cvmx_mio_uartx_rbr_s          cn50xx;
+    struct cvmx_mio_uartx_rbr_s          cn52xx;
+    struct cvmx_mio_uartx_rbr_s          cn52xxp1;
+    struct cvmx_mio_uartx_rbr_s          cn56xx;
+    struct cvmx_mio_uartx_rbr_s          cn56xxp1;
+    struct cvmx_mio_uartx_rbr_s          cn58xx;
+    struct cvmx_mio_uartx_rbr_s          cn58xxp1;
+} cvmx_mio_uartx_rbr_t;
+typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t;
+
+
+/**
+ * cvmx_mio_uart#_rfl
+ *
+ * MIO_UARTX_RFL = MIO UARTX Receive FIFO Level Register
+ * 
+ * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_rfl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t rfl                     : 7;       /**< Receive FIFO Level Register */
+#else
+        uint64_t rfl                     : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mio_uartx_rfl_s          cn30xx;
+    struct cvmx_mio_uartx_rfl_s          cn31xx;
+    struct cvmx_mio_uartx_rfl_s          cn38xx;
+    struct cvmx_mio_uartx_rfl_s          cn38xxp2;
+    struct cvmx_mio_uartx_rfl_s          cn50xx;
+    struct cvmx_mio_uartx_rfl_s          cn52xx;
+    struct cvmx_mio_uartx_rfl_s          cn52xxp1;
+    struct cvmx_mio_uartx_rfl_s          cn56xx;
+    struct cvmx_mio_uartx_rfl_s          cn56xxp1;
+    struct cvmx_mio_uartx_rfl_s          cn58xx;
+    struct cvmx_mio_uartx_rfl_s          cn58xxp1;
+} cvmx_mio_uartx_rfl_t;
+typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t;
+
+
+/**
+ * cvmx_mio_uart#_rfw
+ *
+ * MIO_UARTX_RFW = MIO UARTX Receive FIFO Write Register
+ * 
+ * The Receive FIFO Write Register (RFW) is only valid when FIFO access mode is enabled (FAR bit 0 is
+ * set). When FIFOs are enabled, this register is used to write data to the receive FIFO. Each
+ * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are
+ * not enabled, this register is used to write data to the RBR.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_rfw_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t rffe                    : 1;       /**< Receive FIFO Framing Error */
+        uint64_t rfpe                    : 1;       /**< Receive FIFO Parity Error */
+        uint64_t rfwd                    : 8;       /**< Receive FIFO Write Data */
+#else
+        uint64_t rfwd                    : 8;
+        uint64_t rfpe                    : 1;
+        uint64_t rffe                    : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_mio_uartx_rfw_s          cn30xx;
+    struct cvmx_mio_uartx_rfw_s          cn31xx;
+    struct cvmx_mio_uartx_rfw_s          cn38xx;
+    struct cvmx_mio_uartx_rfw_s          cn38xxp2;
+    struct cvmx_mio_uartx_rfw_s          cn50xx;
+    struct cvmx_mio_uartx_rfw_s          cn52xx;
+    struct cvmx_mio_uartx_rfw_s          cn52xxp1;
+    struct cvmx_mio_uartx_rfw_s          cn56xx;
+    struct cvmx_mio_uartx_rfw_s          cn56xxp1;
+    struct cvmx_mio_uartx_rfw_s          cn58xx;
+    struct cvmx_mio_uartx_rfw_s          cn58xxp1;
+} cvmx_mio_uartx_rfw_t;
+typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t;
+
+
+/**
+ * cvmx_mio_uart#_sbcr
+ *
+ * MIO_UARTX_SBCR = MIO UARTX Shadow Break Control Register
+ * 
+ * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can
+ * be used to remove the burden of having to perform a read-modify-write on the LCR.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_sbcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t sbcr                    : 1;       /**< Shadow Break Control */
+#else
+        uint64_t sbcr                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uartx_sbcr_s         cn30xx;
+    struct cvmx_mio_uartx_sbcr_s         cn31xx;
+    struct cvmx_mio_uartx_sbcr_s         cn38xx;
+    struct cvmx_mio_uartx_sbcr_s         cn38xxp2;
+    struct cvmx_mio_uartx_sbcr_s         cn50xx;
+    struct cvmx_mio_uartx_sbcr_s         cn52xx;
+    struct cvmx_mio_uartx_sbcr_s         cn52xxp1;
+    struct cvmx_mio_uartx_sbcr_s         cn56xx;
+    struct cvmx_mio_uartx_sbcr_s         cn56xxp1;
+    struct cvmx_mio_uartx_sbcr_s         cn58xx;
+    struct cvmx_mio_uartx_sbcr_s         cn58xxp1;
+} cvmx_mio_uartx_sbcr_t;
+typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t;
+
+
+/**
+ * cvmx_mio_uart#_scr
+ *
+ * MIO_UARTX_SCR = MIO UARTX Scratchpad Register
+ * 
+ * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary
+ * storage space.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_scr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t scr                     : 8;       /**< Scratchpad Register */
+#else
+        uint64_t scr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_scr_s          cn30xx;
+    struct cvmx_mio_uartx_scr_s          cn31xx;
+    struct cvmx_mio_uartx_scr_s          cn38xx;
+    struct cvmx_mio_uartx_scr_s          cn38xxp2;
+    struct cvmx_mio_uartx_scr_s          cn50xx;
+    struct cvmx_mio_uartx_scr_s          cn52xx;
+    struct cvmx_mio_uartx_scr_s          cn52xxp1;
+    struct cvmx_mio_uartx_scr_s          cn56xx;
+    struct cvmx_mio_uartx_scr_s          cn56xxp1;
+    struct cvmx_mio_uartx_scr_s          cn58xx;
+    struct cvmx_mio_uartx_scr_s          cn58xxp1;
+} cvmx_mio_uartx_scr_t;
+typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t;
+
+
+/**
+ * cvmx_mio_uart#_sfe
+ *
+ * MIO_UARTX_SFE = MIO UARTX Shadow FIFO Enable Register
+ * 
+ * The Shadow FIFO Enable Register (SFE) is a shadow register for the FIFO enable bit (FCR bit 0) that
+ * can be used to remove the burden of having to store the previously written value to the FCR in memory
+ * and having to mask this value so that only the FIFO enable bit gets updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_sfe_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t sfe                     : 1;       /**< Shadow FIFO Enable */
+#else
+        uint64_t sfe                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uartx_sfe_s          cn30xx;
+    struct cvmx_mio_uartx_sfe_s          cn31xx;
+    struct cvmx_mio_uartx_sfe_s          cn38xx;
+    struct cvmx_mio_uartx_sfe_s          cn38xxp2;
+    struct cvmx_mio_uartx_sfe_s          cn50xx;
+    struct cvmx_mio_uartx_sfe_s          cn52xx;
+    struct cvmx_mio_uartx_sfe_s          cn52xxp1;
+    struct cvmx_mio_uartx_sfe_s          cn56xx;
+    struct cvmx_mio_uartx_sfe_s          cn56xxp1;
+    struct cvmx_mio_uartx_sfe_s          cn58xx;
+    struct cvmx_mio_uartx_sfe_s          cn58xxp1;
+} cvmx_mio_uartx_sfe_t;
+typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t;
+
+
+/**
+ * cvmx_mio_uart#_srr
+ *
+ * MIO_UARTX_SRR = MIO UARTX Software Reset Register
+ * 
+ * The Software Reset Register (SRR) is a write-only register that resets the UART and/or the receive
+ * FIFO and/or the transmit FIFO.
+ * 
+ * Bit 0 of the SRR is the UART Soft Reset (USR) bit.  Setting this bit resets the UART.
+ * 
+ * Bit 1 of the SRR is a shadow copy of the RX FIFO Reset bit (FCR bit 1). This can be used to remove
+ * the burden on software having to store previously written FCR values (which are pretty static) just
+ * to reset the receive FIFO.
+ * 
+ * Bit 2 of the SRR is a shadow copy of the TX FIFO Reset bit (FCR bit 2). This can be used to remove
+ * the burden on software having to store previously written FCR values (which are pretty static) just
+ * to reset the transmit FIFO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_srr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t stfr                    : 1;       /**< Shadow TX FIFO Reset */
+        uint64_t srfr                    : 1;       /**< Shadow RX FIFO Reset */
+        uint64_t usr                     : 1;       /**< UART Soft Reset */
+#else
+        uint64_t usr                     : 1;
+        uint64_t srfr                    : 1;
+        uint64_t stfr                    : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_mio_uartx_srr_s          cn30xx;
+    struct cvmx_mio_uartx_srr_s          cn31xx;
+    struct cvmx_mio_uartx_srr_s          cn38xx;
+    struct cvmx_mio_uartx_srr_s          cn38xxp2;
+    struct cvmx_mio_uartx_srr_s          cn50xx;
+    struct cvmx_mio_uartx_srr_s          cn52xx;
+    struct cvmx_mio_uartx_srr_s          cn52xxp1;
+    struct cvmx_mio_uartx_srr_s          cn56xx;
+    struct cvmx_mio_uartx_srr_s          cn56xxp1;
+    struct cvmx_mio_uartx_srr_s          cn58xx;
+    struct cvmx_mio_uartx_srr_s          cn58xxp1;
+} cvmx_mio_uartx_srr_t;
+typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t;
+
+
+/**
+ * cvmx_mio_uart#_srt
+ *
+ * MIO_UARTX_SRT = MIO UARTX Shadow RX Trigger Register
+ * 
+ * The Shadow RX Trigger Register (SRT) is a shadow register for the RX Trigger bits (FCR bits 7:6) that
+ * can be used to remove the burden of having to store the previously written value to the FCR in memory
+ * and having to mask this value so that only the RX Trigger bits get updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_srt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t srt                     : 2;       /**< Shadow RX Trigger */
+#else
+        uint64_t srt                     : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_uartx_srt_s          cn30xx;
+    struct cvmx_mio_uartx_srt_s          cn31xx;
+    struct cvmx_mio_uartx_srt_s          cn38xx;
+    struct cvmx_mio_uartx_srt_s          cn38xxp2;
+    struct cvmx_mio_uartx_srt_s          cn50xx;
+    struct cvmx_mio_uartx_srt_s          cn52xx;
+    struct cvmx_mio_uartx_srt_s          cn52xxp1;
+    struct cvmx_mio_uartx_srt_s          cn56xx;
+    struct cvmx_mio_uartx_srt_s          cn56xxp1;
+    struct cvmx_mio_uartx_srt_s          cn58xx;
+    struct cvmx_mio_uartx_srt_s          cn58xxp1;
+} cvmx_mio_uartx_srt_t;
+typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t;
+
+
+/**
+ * cvmx_mio_uart#_srts
+ *
+ * MIO_UARTX_SRTS = MIO UARTX Shadow Request To Send Register
+ * 
+ * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can
+ * be used to remove the burden of having to perform a read-modify-write on the MCR.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_srts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t srts                    : 1;       /**< Shadow Request To Send */
+#else
+        uint64_t srts                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uartx_srts_s         cn30xx;
+    struct cvmx_mio_uartx_srts_s         cn31xx;
+    struct cvmx_mio_uartx_srts_s         cn38xx;
+    struct cvmx_mio_uartx_srts_s         cn38xxp2;
+    struct cvmx_mio_uartx_srts_s         cn50xx;
+    struct cvmx_mio_uartx_srts_s         cn52xx;
+    struct cvmx_mio_uartx_srts_s         cn52xxp1;
+    struct cvmx_mio_uartx_srts_s         cn56xx;
+    struct cvmx_mio_uartx_srts_s         cn56xxp1;
+    struct cvmx_mio_uartx_srts_s         cn58xx;
+    struct cvmx_mio_uartx_srts_s         cn58xxp1;
+} cvmx_mio_uartx_srts_t;
+typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t;
+
+
+/**
+ * cvmx_mio_uart#_stt
+ *
+ * MIO_UARTX_STT = MIO UARTX Shadow TX Trigger Register
+ * 
+ * The Shadow TX Trigger Register (STT) is a shadow register for the TX Trigger bits (FCR bits 5:4) that
+ * can be used to remove the burden of having to store the previously written value to the FCR in memory
+ * and having to mask this value so that only the TX Trigger bits get updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_stt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t stt                     : 2;       /**< Shadow TX Trigger */
+#else
+        uint64_t stt                     : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_uartx_stt_s          cn30xx;
+    struct cvmx_mio_uartx_stt_s          cn31xx;
+    struct cvmx_mio_uartx_stt_s          cn38xx;
+    struct cvmx_mio_uartx_stt_s          cn38xxp2;
+    struct cvmx_mio_uartx_stt_s          cn50xx;
+    struct cvmx_mio_uartx_stt_s          cn52xx;
+    struct cvmx_mio_uartx_stt_s          cn52xxp1;
+    struct cvmx_mio_uartx_stt_s          cn56xx;
+    struct cvmx_mio_uartx_stt_s          cn56xxp1;
+    struct cvmx_mio_uartx_stt_s          cn58xx;
+    struct cvmx_mio_uartx_stt_s          cn58xxp1;
+} cvmx_mio_uartx_stt_t;
+typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t;
+
+
+/**
+ * cvmx_mio_uart#_tfl
+ *
+ * MIO_UARTX_TFL = MIO UARTX Transmit FIFO Level Register
+ * 
+ * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_tfl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t tfl                     : 7;       /**< Transmit FIFO Level Register */
+#else
+        uint64_t tfl                     : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mio_uartx_tfl_s          cn30xx;
+    struct cvmx_mio_uartx_tfl_s          cn31xx;
+    struct cvmx_mio_uartx_tfl_s          cn38xx;
+    struct cvmx_mio_uartx_tfl_s          cn38xxp2;
+    struct cvmx_mio_uartx_tfl_s          cn50xx;
+    struct cvmx_mio_uartx_tfl_s          cn52xx;
+    struct cvmx_mio_uartx_tfl_s          cn52xxp1;
+    struct cvmx_mio_uartx_tfl_s          cn56xx;
+    struct cvmx_mio_uartx_tfl_s          cn56xxp1;
+    struct cvmx_mio_uartx_tfl_s          cn58xx;
+    struct cvmx_mio_uartx_tfl_s          cn58xxp1;
+} cvmx_mio_uartx_tfl_t;
+typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t;
+
+
+/**
+ * cvmx_mio_uart#_tfr
+ *
+ * MIO_UARTX_TFR = MIO UARTX Transmit FIFO Read Register
+ * 
+ * The Transmit FIFO Read Register (TFR) is only valid when FIFO access mode is enabled (FAR bit 0 is
+ * set). When FIFOs are enabled, reading this register gives the data at the top of the transmit FIFO.
+ * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the
+ * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_tfr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t tfr                     : 8;       /**< Transmit FIFO Read Register */
+#else
+        uint64_t tfr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_tfr_s          cn30xx;
+    struct cvmx_mio_uartx_tfr_s          cn31xx;
+    struct cvmx_mio_uartx_tfr_s          cn38xx;
+    struct cvmx_mio_uartx_tfr_s          cn38xxp2;
+    struct cvmx_mio_uartx_tfr_s          cn50xx;
+    struct cvmx_mio_uartx_tfr_s          cn52xx;
+    struct cvmx_mio_uartx_tfr_s          cn52xxp1;
+    struct cvmx_mio_uartx_tfr_s          cn56xx;
+    struct cvmx_mio_uartx_tfr_s          cn56xxp1;
+    struct cvmx_mio_uartx_tfr_s          cn58xx;
+    struct cvmx_mio_uartx_tfr_s          cn58xxp1;
+} cvmx_mio_uartx_tfr_t;
+typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t;
+
+
+/**
+ * cvmx_mio_uart#_thr
+ *
+ * MIO_UARTX_THR = MIO UARTX Transmit Holding Register
+ * 
+ * Transmit Holding Register (THR) is a write-only register that contains data to be transmitted on the
+ * serial output port (sout). Data can be written to the THR any time that the THR Empty (THRE) bit of
+ * the Line Status Register (LSR) is set.
+ * 
+ * If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any
+ * additional writes to the THR before the THRE is set again causes the THR data to be overwritten.
+ * 
+ * If FIFOs are enabled and THRE is set (and Programmable THRE mode disabled), 64 characters of data may
+ * be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results
+ * in the write data being lost.
+ * 
+ * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access
+ * this register.
+ * 
+ * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the
+ * RBR, THR, and DLL registers are the same.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_thr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t thr                     : 8;       /**< Transmit Holding Register */
+#else
+        uint64_t thr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uartx_thr_s          cn30xx;
+    struct cvmx_mio_uartx_thr_s          cn31xx;
+    struct cvmx_mio_uartx_thr_s          cn38xx;
+    struct cvmx_mio_uartx_thr_s          cn38xxp2;
+    struct cvmx_mio_uartx_thr_s          cn50xx;
+    struct cvmx_mio_uartx_thr_s          cn52xx;
+    struct cvmx_mio_uartx_thr_s          cn52xxp1;
+    struct cvmx_mio_uartx_thr_s          cn56xx;
+    struct cvmx_mio_uartx_thr_s          cn56xxp1;
+    struct cvmx_mio_uartx_thr_s          cn58xx;
+    struct cvmx_mio_uartx_thr_s          cn58xxp1;
+} cvmx_mio_uartx_thr_t;
+typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t;
+
+
+/**
+ * cvmx_mio_uart#_usr
+ *
+ * MIO_UARTX_USR = MIO UARTX UART Status Register
+ * 
+ * The UART Status Register (USR) contains UART status information.
+ * 
+ * USR bit 0 is the BUSY bit.  When set this bit indicates that a serial transfer is in progress, when
+ * clear it indicates that the UART is idle or inactive.
+ * 
+ * Note: In PASS3, the BUSY bit will always be clear.
+ * 
+ * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX
+ * FIFO Not Empty (RFNE), and RX FIFO Full (RFF).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uartx_usr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t rff                     : 1;       /**< RX FIFO Full */
+        uint64_t rfne                    : 1;       /**< RX FIFO Not Empty */
+        uint64_t tfe                     : 1;       /**< TX FIFO Empty */
+        uint64_t tfnf                    : 1;       /**< TX FIFO Not Full */
+        uint64_t busy                    : 1;       /**< Busy bit (always 0 in PASS3) */
+#else
+        uint64_t busy                    : 1;
+        uint64_t tfnf                    : 1;
+        uint64_t tfe                     : 1;
+        uint64_t rfne                    : 1;
+        uint64_t rff                     : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_mio_uartx_usr_s          cn30xx;
+    struct cvmx_mio_uartx_usr_s          cn31xx;
+    struct cvmx_mio_uartx_usr_s          cn38xx;
+    struct cvmx_mio_uartx_usr_s          cn38xxp2;
+    struct cvmx_mio_uartx_usr_s          cn50xx;
+    struct cvmx_mio_uartx_usr_s          cn52xx;
+    struct cvmx_mio_uartx_usr_s          cn52xxp1;
+    struct cvmx_mio_uartx_usr_s          cn56xx;
+    struct cvmx_mio_uartx_usr_s          cn56xxp1;
+    struct cvmx_mio_uartx_usr_s          cn58xx;
+    struct cvmx_mio_uartx_usr_s          cn58xxp1;
+} cvmx_mio_uartx_usr_t;
+typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t;
+
+
+/**
+ * cvmx_mio_uart2_dlh
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_dlh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dlh                     : 8;       /**< Divisor Latch High Register */
+#else
+        uint64_t dlh                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_dlh_s          cn52xx;
+    struct cvmx_mio_uart2_dlh_s          cn52xxp1;
+} cvmx_mio_uart2_dlh_t;
+
+
+/**
+ * cvmx_mio_uart2_dll
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_dll_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dll                     : 8;       /**< Divisor Latch Low Register */
+#else
+        uint64_t dll                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_dll_s          cn52xx;
+    struct cvmx_mio_uart2_dll_s          cn52xxp1;
+} cvmx_mio_uart2_dll_t;
+
+
+/**
+ * cvmx_mio_uart2_far
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_far_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t far                     : 1;       /**< FIFO Access Register */
+#else
+        uint64_t far                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uart2_far_s          cn52xx;
+    struct cvmx_mio_uart2_far_s          cn52xxp1;
+} cvmx_mio_uart2_far_t;
+
+
+/**
+ * cvmx_mio_uart2_fcr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_fcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rxtrig                  : 2;       /**< RX Trigger */
+        uint64_t txtrig                  : 2;       /**< TX Trigger */
+        uint64_t reserved_3_3            : 1;
+        uint64_t txfr                    : 1;       /**< TX FIFO reset */
+        uint64_t rxfr                    : 1;       /**< RX FIFO reset */
+        uint64_t en                      : 1;       /**< FIFO enable */
+#else
+        uint64_t en                      : 1;
+        uint64_t rxfr                    : 1;
+        uint64_t txfr                    : 1;
+        uint64_t reserved_3_3            : 1;
+        uint64_t txtrig                  : 2;
+        uint64_t rxtrig                  : 2;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_fcr_s          cn52xx;
+    struct cvmx_mio_uart2_fcr_s          cn52xxp1;
+} cvmx_mio_uart2_fcr_t;
+
+
+/**
+ * cvmx_mio_uart2_htx
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_htx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t htx                     : 1;       /**< Halt TX */
+#else
+        uint64_t htx                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uart2_htx_s          cn52xx;
+    struct cvmx_mio_uart2_htx_s          cn52xxp1;
+} cvmx_mio_uart2_htx_t;
+
+
+/**
+ * cvmx_mio_uart2_ier
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_ier_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ptime                   : 1;       /**< Programmable THRE Interrupt mode enable */
+        uint64_t reserved_4_6            : 3;
+        uint64_t edssi                   : 1;       /**< Enable Modem Status Interrupt */
+        uint64_t elsi                    : 1;       /**< Enable Receiver Line Status Interrupt */
+        uint64_t etbei                   : 1;       /**< Enable Transmitter Holding Register Empty Interrupt */
+        uint64_t erbfi                   : 1;       /**< Enable Received Data Available Interrupt */
+#else
+        uint64_t erbfi                   : 1;
+        uint64_t etbei                   : 1;
+        uint64_t elsi                    : 1;
+        uint64_t edssi                   : 1;
+        uint64_t reserved_4_6            : 3;
+        uint64_t ptime                   : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_ier_s          cn52xx;
+    struct cvmx_mio_uart2_ier_s          cn52xxp1;
+} cvmx_mio_uart2_ier_t;
+
+
+/**
+ * cvmx_mio_uart2_iir
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_iir_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t fen                     : 2;       /**< FIFO-enabled bits */
+        uint64_t reserved_4_5            : 2;
+        uint64_t iid                     : 4;       /**< Interrupt ID */
+#else
+        uint64_t iid                     : 4;
+        uint64_t reserved_4_5            : 2;
+        uint64_t fen                     : 2;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_iir_s          cn52xx;
+    struct cvmx_mio_uart2_iir_s          cn52xxp1;
+} cvmx_mio_uart2_iir_t;
+
+
+/**
+ * cvmx_mio_uart2_lcr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_lcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dlab                    : 1;       /**< Divisor Latch Address bit */
+        uint64_t brk                     : 1;       /**< Break Control bit */
+        uint64_t reserved_5_5            : 1;
+        uint64_t eps                     : 1;       /**< Even Parity Select bit */
+        uint64_t pen                     : 1;       /**< Parity Enable bit */
+        uint64_t stop                    : 1;       /**< Stop Control bit */
+        uint64_t cls                     : 2;       /**< Character Length Select */
+#else
+        uint64_t cls                     : 2;
+        uint64_t stop                    : 1;
+        uint64_t pen                     : 1;
+        uint64_t eps                     : 1;
+        uint64_t reserved_5_5            : 1;
+        uint64_t brk                     : 1;
+        uint64_t dlab                    : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_lcr_s          cn52xx;
+    struct cvmx_mio_uart2_lcr_s          cn52xxp1;
+} cvmx_mio_uart2_lcr_t;
+
+
+/**
+ * cvmx_mio_uart2_lsr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_lsr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t ferr                    : 1;       /**< Error in Receiver FIFO bit */
+        uint64_t temt                    : 1;       /**< Transmitter Empty bit */
+        uint64_t thre                    : 1;       /**< Transmitter Holding Register Empty bit */
+        uint64_t bi                      : 1;       /**< Break Interrupt bit */
+        uint64_t fe                      : 1;       /**< Framing Error bit */
+        uint64_t pe                      : 1;       /**< Parity Error bit */
+        uint64_t oe                      : 1;       /**< Overrun Error bit */
+        uint64_t dr                      : 1;       /**< Data Ready bit */
+#else
+        uint64_t dr                      : 1;
+        uint64_t oe                      : 1;
+        uint64_t pe                      : 1;
+        uint64_t fe                      : 1;
+        uint64_t bi                      : 1;
+        uint64_t thre                    : 1;
+        uint64_t temt                    : 1;
+        uint64_t ferr                    : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_lsr_s          cn52xx;
+    struct cvmx_mio_uart2_lsr_s          cn52xxp1;
+} cvmx_mio_uart2_lsr_t;
+
+
+/**
+ * cvmx_mio_uart2_mcr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_mcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t afce                    : 1;       /**< Auto Flow Control Enable bit */
+        uint64_t loop                    : 1;       /**< Loopback bit */
+        uint64_t out2                    : 1;       /**< OUT2 output bit */
+        uint64_t out1                    : 1;       /**< OUT1 output bit */
+        uint64_t rts                     : 1;       /**< Request To Send output bit */
+        uint64_t dtr                     : 1;       /**< Data Terminal Ready output bit */
+#else
+        uint64_t dtr                     : 1;
+        uint64_t rts                     : 1;
+        uint64_t out1                    : 1;
+        uint64_t out2                    : 1;
+        uint64_t loop                    : 1;
+        uint64_t afce                    : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_mio_uart2_mcr_s          cn52xx;
+    struct cvmx_mio_uart2_mcr_s          cn52xxp1;
+} cvmx_mio_uart2_mcr_t;
+
+
+/**
+ * cvmx_mio_uart2_msr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_msr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t dcd                     : 1;       /**< Data Carrier Detect input bit */
+        uint64_t ri                      : 1;       /**< Ring Indicator input bit */
+        uint64_t dsr                     : 1;       /**< Data Set Ready input bit */
+        uint64_t cts                     : 1;       /**< Clear To Send input bit */
+        uint64_t ddcd                    : 1;       /**< Delta Data Carrier Detect bit */
+        uint64_t teri                    : 1;       /**< Trailing Edge of Ring Indicator bit */
+        uint64_t ddsr                    : 1;       /**< Delta Data Set Ready bit */
+        uint64_t dcts                    : 1;       /**< Delta Clear To Send bit */
+#else
+        uint64_t dcts                    : 1;
+        uint64_t ddsr                    : 1;
+        uint64_t teri                    : 1;
+        uint64_t ddcd                    : 1;
+        uint64_t cts                     : 1;
+        uint64_t dsr                     : 1;
+        uint64_t ri                      : 1;
+        uint64_t dcd                     : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_msr_s          cn52xx;
+    struct cvmx_mio_uart2_msr_s          cn52xxp1;
+} cvmx_mio_uart2_msr_t;
+
+
+/**
+ * cvmx_mio_uart2_rbr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_rbr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rbr                     : 8;       /**< Receive Buffer Register */
+#else
+        uint64_t rbr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_rbr_s          cn52xx;
+    struct cvmx_mio_uart2_rbr_s          cn52xxp1;
+} cvmx_mio_uart2_rbr_t;
+
+
+/**
+ * cvmx_mio_uart2_rfl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_rfl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t rfl                     : 7;       /**< Receive FIFO Level Register */
+#else
+        uint64_t rfl                     : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mio_uart2_rfl_s          cn52xx;
+    struct cvmx_mio_uart2_rfl_s          cn52xxp1;
+} cvmx_mio_uart2_rfl_t;
+
+
+/**
+ * cvmx_mio_uart2_rfw
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_rfw_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t rffe                    : 1;       /**< Receive FIFO Framing Error */
+        uint64_t rfpe                    : 1;       /**< Receive FIFO Parity Error */
+        uint64_t rfwd                    : 8;       /**< Receive FIFO Write Data */
+#else
+        uint64_t rfwd                    : 8;
+        uint64_t rfpe                    : 1;
+        uint64_t rffe                    : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_mio_uart2_rfw_s          cn52xx;
+    struct cvmx_mio_uart2_rfw_s          cn52xxp1;
+} cvmx_mio_uart2_rfw_t;
+
+
+/**
+ * cvmx_mio_uart2_sbcr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_sbcr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t sbcr                    : 1;       /**< Shadow Break Control */
+#else
+        uint64_t sbcr                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uart2_sbcr_s         cn52xx;
+    struct cvmx_mio_uart2_sbcr_s         cn52xxp1;
+} cvmx_mio_uart2_sbcr_t;
+
+
+/**
+ * cvmx_mio_uart2_scr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_scr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t scr                     : 8;       /**< Scratchpad Register */
+#else
+        uint64_t scr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_scr_s          cn52xx;
+    struct cvmx_mio_uart2_scr_s          cn52xxp1;
+} cvmx_mio_uart2_scr_t;
+
+
+/**
+ * cvmx_mio_uart2_sfe
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_sfe_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t sfe                     : 1;       /**< Shadow FIFO Enable */
+#else
+        uint64_t sfe                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uart2_sfe_s          cn52xx;
+    struct cvmx_mio_uart2_sfe_s          cn52xxp1;
+} cvmx_mio_uart2_sfe_t;
+
+
+/**
+ * cvmx_mio_uart2_srr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_srr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t stfr                    : 1;       /**< Shadow TX FIFO Reset */
+        uint64_t srfr                    : 1;       /**< Shadow RX FIFO Reset */
+        uint64_t usr                     : 1;       /**< UART Soft Reset */
+#else
+        uint64_t usr                     : 1;
+        uint64_t srfr                    : 1;
+        uint64_t stfr                    : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_mio_uart2_srr_s          cn52xx;
+    struct cvmx_mio_uart2_srr_s          cn52xxp1;
+} cvmx_mio_uart2_srr_t;
+
+
+/**
+ * cvmx_mio_uart2_srt
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_srt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t srt                     : 2;       /**< Shadow RX Trigger */
+#else
+        uint64_t srt                     : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_uart2_srt_s          cn52xx;
+    struct cvmx_mio_uart2_srt_s          cn52xxp1;
+} cvmx_mio_uart2_srt_t;
+
+
+/**
+ * cvmx_mio_uart2_srts
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_srts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t srts                    : 1;       /**< Shadow Request To Send */
+#else
+        uint64_t srts                    : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_mio_uart2_srts_s         cn52xx;
+    struct cvmx_mio_uart2_srts_s         cn52xxp1;
+} cvmx_mio_uart2_srts_t;
+
+
+/**
+ * cvmx_mio_uart2_stt
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_stt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t stt                     : 2;       /**< Shadow TX Trigger */
+#else
+        uint64_t stt                     : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_mio_uart2_stt_s          cn52xx;
+    struct cvmx_mio_uart2_stt_s          cn52xxp1;
+} cvmx_mio_uart2_stt_t;
+
+
+/**
+ * cvmx_mio_uart2_tfl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_tfl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t tfl                     : 7;       /**< Transmit FIFO Level Register */
+#else
+        uint64_t tfl                     : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mio_uart2_tfl_s          cn52xx;
+    struct cvmx_mio_uart2_tfl_s          cn52xxp1;
+} cvmx_mio_uart2_tfl_t;
+
+
+/**
+ * cvmx_mio_uart2_tfr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_tfr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t tfr                     : 8;       /**< Transmit FIFO Read Register */
+#else
+        uint64_t tfr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_tfr_s          cn52xx;
+    struct cvmx_mio_uart2_tfr_s          cn52xxp1;
+} cvmx_mio_uart2_tfr_t;
+
+
+/**
+ * cvmx_mio_uart2_thr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_thr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t thr                     : 8;       /**< Transmit Holding Register */
+#else
+        uint64_t thr                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mio_uart2_thr_s          cn52xx;
+    struct cvmx_mio_uart2_thr_s          cn52xxp1;
+} cvmx_mio_uart2_thr_t;
+
+
+/**
+ * cvmx_mio_uart2_usr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mio_uart2_usr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t rff                     : 1;       /**< RX FIFO Full */
+        uint64_t rfne                    : 1;       /**< RX FIFO Not Empty */
+        uint64_t tfe                     : 1;       /**< TX FIFO Empty */
+        uint64_t tfnf                    : 1;       /**< TX FIFO Not Full */
+        uint64_t busy                    : 1;       /**< Busy bit (always 0 in PASS3) */
+#else
+        uint64_t busy                    : 1;
+        uint64_t tfnf                    : 1;
+        uint64_t tfe                     : 1;
+        uint64_t rfne                    : 1;
+        uint64_t rff                     : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_mio_uart2_usr_s          cn52xx;
+    struct cvmx_mio_uart2_usr_s          cn52xxp1;
+} cvmx_mio_uart2_usr_t;
+
+
+/**
+ * cvmx_mix#_bist
+ *
+ * MIX_BIST = MIX BIST Register
+ * 
+ * Description:
+ *  NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_bist_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t mrqdat                  : 1;       /**< Bist Results for NBR CSR RdReq RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t ipfdat                  : 1;       /**< Bist Results for MIX Inbound Packet RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t irfdat                  : 1;       /**< Bist Results for MIX I-Ring Entry RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t orfdat                  : 1;       /**< Bist Results for MIX O-Ring Entry RAM
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t orfdat                  : 1;
+        uint64_t irfdat                  : 1;
+        uint64_t ipfdat                  : 1;
+        uint64_t mrqdat                  : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_mixx_bist_s              cn52xx;
+    struct cvmx_mixx_bist_s              cn52xxp1;
+    struct cvmx_mixx_bist_s              cn56xx;
+    struct cvmx_mixx_bist_s              cn56xxp1;
+} cvmx_mixx_bist_t;
+
+
+/**
+ * cvmx_mix#_ctl
+ *
+ * MIX_CTL = MIX Control Register
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t crc_strip               : 1;       /**< HW CRC Strip Enable
+                                                         When enabled, the last 4 bytes(CRC) of the ingress packet
+                                                         are not included in cumulative packet byte length.
+                                                         In other words, the cumulative LEN field for all
+                                                         I-Ring Buffer Entries associated with a given ingress
+                                                         packet will be 4 bytes less (so that the final 4B HW CRC
+                                                         packet data is not processed by software). */
+        uint64_t busy                    : 1;       /**< MIX Busy Status bit
+                                                         MIX will assert busy status any time there are:
+                                                           1) L2/DRAM reads in-flight (NCB-arb to read
+                                                              response)
+                                                           2) L2/DRAM writes in-flight (NCB-arb to write
+                                                              data is sent.
+                                                           3) L2/DRAM write commits in-flight (NCB-arb to write
+                                                              commit response).
+                                                         NOTE: After MIX_CTL[EN]=0, the MIX will eventually
+                                                         complete any "inflight" transactions, at which point the
+                                                         BUSY will de-assert. */
+        uint64_t en                      : 1;       /**< MIX Enable bit
+                                                         When EN=0, MIX will no longer arbitrate for
+                                                         any new L2/DRAM read/write requests on the NCB Bus.
+                                                         MIX will complete any requests that are currently
+                                                         pended for the NCB Bus. */
+        uint64_t reset                   : 1;       /**< MIX Soft Reset
+                                                         When SW writes a '1' to MIX_CTL[RESET], the
+                                                         MIX logic will be soft reset.
+                                                         NOTE: The MIX-AGL RSL-CSR accesses are not effected
+                                                         by soft reset (to allow RSL accesses during soft reset).
+                                                         NOTE: The MIX-MIX NCB-direct CSR accesses are not effected
+                                                         by soft reset (to allow RSL accesses during soft reset).
+                                                         NOTE: Writing '1' will create a "64 eclk" soft reset
+                                                         pulse chain used by both MIX/AGL subcomponents to
+                                                         soft reset the MIX/AGL. SW should avoid sending any MIX/AGL
+                                                         CSR R/Ws until after this 64 eclk reset window has
+                                                         expired (unpredictable results).
+                                                         NOTE: RESET is intentionally 'read as zero'.
+                                                         The intended "soft reset" sequence is:
+                                                            1) Write MIX_CTL[EN]=0
+                                                               [To prevent any NEW transactions from being started]
+                                                            2) Wait for MIX_CTL[BUSY]=0
+                                                               [To indicate that all inflight transactions have
+                                                                completed]
+                                                            3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read
+                                                               and wait for the result.
+                                                               This will generate the soft-reset pulse chain that will
+                                                               reset MIX/AGL (except logic to gain access to CSRs).
+                                                            4) Re-Initialize the MIX/AGL just as would be done
+                                                               for a hard reset. */
+        uint64_t lendian                 : 1;       /**< Packet Little Endian Mode
+                                                         (0: Big Endian Mode/1: Little Endian Mode)
+                                                         When the mode is set, MIX will byte-swap packet data
+                                                         loads/stores at the MIX/NCB boundary. */
+        uint64_t nbtarb                  : 1;       /**< MIX CB-Request Arbitration Mode.
+                                                         When set to zero, the arbiter is fixed priority with
+                                                         the following priority scheme:
+                                                             Highest Priority: I-Ring Packet Write Request
+                                                                               O-Ring Packet Read Request
+                                                                               I-Ring Entry Write Request
+                                                                               I-Ring Entry Read Request
+                                                                               O-Ring Entry Read Request
+                                                         When set to one, the arbiter is round robin. */
+        uint64_t mrq_hwm                 : 2;       /**< MIX CB-Request FIFO Programmable High Water Mark.
+                                                         The MRQ contains 16 CB-Requests which are CSR Rd/Wr
+                                                         Requests. If the MRQ backs up with "HWM" entries,
+                                                         then new CB-Requests are 'stalled'.
+                                                            [0]: HWM = 16
+                                                            [1]: HWM = 15
+                                                            [2]: HWM = 14
+                                                            [3]: HWM = 13
+                                                         NOTE: This must only be written at power-on/boot time. */
+#else
+        uint64_t mrq_hwm                 : 2;
+        uint64_t nbtarb                  : 1;
+        uint64_t lendian                 : 1;
+        uint64_t reset                   : 1;
+        uint64_t en                      : 1;
+        uint64_t busy                    : 1;
+        uint64_t crc_strip               : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mixx_ctl_s               cn52xx;
+    struct cvmx_mixx_ctl_s               cn52xxp1;
+    struct cvmx_mixx_ctl_s               cn56xx;
+    struct cvmx_mixx_ctl_s               cn56xxp1;
+} cvmx_mixx_ctl_t;
+
+
+/**
+ * cvmx_mix#_intena
+ *
+ * MIX_INTENA = MIX Local Interrupt Enable Mask Register
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_intena_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t orunena                 : 1;       /**< ORCNT UnderFlow Detected
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an ORCNT underflow condition
+                                                         MIX_ISR[ORUN]. */
+        uint64_t irunena                 : 1;       /**< IRCNT UnderFlow Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an IRCNT underflow condition
+                                                         MIX_ISR[IRUN]. */
+        uint64_t data_drpena             : 1;       /**< Data was dropped due to RX FIFO full Interrupt
+                                                         enable. If both the global interrupt mask bits
+                                                         (CIU_INTx_EN*[MII]) and the local interrupt mask
+                                                         bit(DATA_DRPENA) is set, than an interrupt is
+                                                         reported for this event. */
+        uint64_t ithena                  : 1;       /**< Inbound Ring Threshold Exceeded Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Inbound Ring Threshold
+                                                         Exceeded event(IRTHRESH). */
+        uint64_t othena                  : 1;       /**< Outbound Ring Threshold Exceeded Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Ring Threshold
+                                                         Exceeded event(ORTHRESH). */
+        uint64_t ivfena                  : 1;       /**< Inbound DoorBell(IDBELL) Overflow Detected
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Inbound Doorbell Overflow
+                                                         event(IDBOVF). */
+        uint64_t ovfena                  : 1;       /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and this local interrupt mask bit is set, than an
+                                                         interrupt is reported for an Outbound Doorbell Overflow
+                                                         event(ODBOVF). */
+#else
+        uint64_t ovfena                  : 1;
+        uint64_t ivfena                  : 1;
+        uint64_t othena                  : 1;
+        uint64_t ithena                  : 1;
+        uint64_t data_drpena             : 1;
+        uint64_t irunena                 : 1;
+        uint64_t orunena                 : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mixx_intena_s            cn52xx;
+    struct cvmx_mixx_intena_s            cn52xxp1;
+    struct cvmx_mixx_intena_s            cn56xx;
+    struct cvmx_mixx_intena_s            cn56xxp1;
+} cvmx_mixx_intena_t;
+
+
+/**
+ * cvmx_mix#_ircnt
+ *
+ * MIX_IRCNT = MIX I-Ring Pending Packet Counter
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_ircnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t ircnt                   : 20;      /**< Pending \# of I-Ring Packets.
+                                                         Whenever HW writes a completion code of Done, Trunc,
+                                                         CRCErr or Err, it increments the IRCNT (to indicate
+                                                         to SW the \# of pending Input packets in system memory).
+                                                         NOTE: The HW guarantees that the completion code write
+                                                         is always visible in system memory BEFORE it increments
+                                                         the IRCNT.
+                                                         Reads of IRCNT return the current inbound packet count.
+                                                         Writes of IRCNT decrement the count by the value
+                                                         written.
+                                                         This register is used to generate interrupts to alert
+                                                         SW of pending inbound MIX packets in system memory.
+                                                         NOTE: In the case of inbound packets that span multiple
+                                                         I-Ring entries, SW must keep track of the \# of I-Ring Entries
+                                                         associated with a given inbound packet to reclaim the
+                                                         proper \# of I-Ring Entries for re-use. */
+#else
+        uint64_t ircnt                   : 20;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_mixx_ircnt_s             cn52xx;
+    struct cvmx_mixx_ircnt_s             cn52xxp1;
+    struct cvmx_mixx_ircnt_s             cn56xx;
+    struct cvmx_mixx_ircnt_s             cn56xxp1;
+} cvmx_mixx_ircnt_t;
+
+
+/**
+ * cvmx_mix#_irhwm
+ *
+ * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_irhwm_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t ibplwm                  : 20;      /**< I-Ring BackPressure Low Water Mark Threshold.
+                                                         When the \#of available I-Ring Entries (IDBELL)
+                                                         is less than IBPLWM, the AGL-MAC will:
+                                                           a) In full-duplex mode: send periodic PAUSE packets.
+                                                           b) In half-duplex mode: Force collisions.
+                                                         This programmable mechanism is provided as a means
+                                                         to backpressure input traffic 'early' enough (so
+                                                         that packets are not 'dropped' by OCTEON). */
+        uint64_t irhwm                   : 20;      /**< I-Ring Entry High Water Mark Threshold.
+                                                         Used to determine when the \# of Inbound packets
+                                                         in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM
+                                                         threshold.
+                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
+                                                         interrupt enable bits is zero and must be enabled
+                                                         to allow interrupts to be reported. */
+#else
+        uint64_t irhwm                   : 20;
+        uint64_t ibplwm                  : 20;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_mixx_irhwm_s             cn52xx;
+    struct cvmx_mixx_irhwm_s             cn52xxp1;
+    struct cvmx_mixx_irhwm_s             cn56xx;
+    struct cvmx_mixx_irhwm_s             cn56xxp1;
+} cvmx_mixx_irhwm_t;
+
+
+/**
+ * cvmx_mix#_iring1
+ *
+ * MIX_IRING1 = MIX Inbound Ring Register \#1
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_iring1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t isize                   : 20;      /**< Represents the Inbound Ring Buffer's Size(in 8B
+                                                         words). The ring can be as large as 1M entries.
+                                                         NOTE: This CSR MUST BE setup written by SW poweron
+                                                         (when IDBELL/IRCNT=0). */
+        uint64_t reserved_36_39          : 4;
+        uint64_t ibase                   : 33;      /**< Represents the 8B-aligned base address of the first
+                                                         Inbound Ring entry in system memory.
+                                                         NOTE: SW MUST ONLY write to this register during
+                                                         power-on/boot code. */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t ibase                   : 33;
+        uint64_t reserved_36_39          : 4;
+        uint64_t isize                   : 20;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } s;
+    struct cvmx_mixx_iring1_s            cn52xx;
+    struct cvmx_mixx_iring1_s            cn52xxp1;
+    struct cvmx_mixx_iring1_s            cn56xx;
+    struct cvmx_mixx_iring1_s            cn56xxp1;
+} cvmx_mixx_iring1_t;
+
+
+/**
+ * cvmx_mix#_iring2
+ *
+ * MIX_IRING2 = MIX Inbound Ring Register \#2
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_iring2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_52_63          : 12;
+        uint64_t itlptr                  : 20;      /**< The Inbound Ring Tail Pointer selects the I-Ring
+                                                         Entry that the HW will process next. After the HW
+                                                         completes receiving an inbound packet, it increments
+                                                         the I-Ring Tail Pointer. [NOTE: The I-Ring Tail
+                                                         Pointer HW increment is always modulo ISIZE.
+                                                         NOTE: This field is 'read-only' to SW. */
+        uint64_t reserved_20_31          : 12;
+        uint64_t idbell                  : 20;      /**< Represents the cumulative total of pending
+                                                         Inbound Ring Buffer Entries. Each I-Ring
+                                                         Buffer Entry contains 1) an L2/DRAM byte pointer
+                                                         along with a 2) a Byte Length.
+                                                         After SW inserts a new entry into the I-Ring Buffer,
+                                                         it "rings the doorbell for the inbound ring". When
+                                                         the MIX HW receives the doorbell ring, it advances
+                                                         the doorbell count for the I-Ring.
+                                                         SW must never cause the doorbell count for the
+                                                         I-Ring to exceed the size of the I-ring(ISIZE).
+                                                         A read of the CSR indicates the current doorbell
+                                                         count. */
+#else
+        uint64_t idbell                  : 20;
+        uint64_t reserved_20_31          : 12;
+        uint64_t itlptr                  : 20;
+        uint64_t reserved_52_63          : 12;
+#endif
+    } s;
+    struct cvmx_mixx_iring2_s            cn52xx;
+    struct cvmx_mixx_iring2_s            cn52xxp1;
+    struct cvmx_mixx_iring2_s            cn56xx;
+    struct cvmx_mixx_iring2_s            cn56xxp1;
+} cvmx_mixx_iring2_t;
+
+
+/**
+ * cvmx_mix#_isr
+ *
+ * MIX_ISR = MIX Interrupt/Status Register
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_isr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t orun                    : 1;       /**< ORCNT UnderFlow Detected
+                                                         If SW writes a larger value than what is currently
+                                                         in the MIX_ORCNT[ORCNT], then HW will report the
+                                                         underflow condition.
+                                                         NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.
+                                                         NOTE: If an ORUN underflow condition is detected,
+                                                         the integrity of the MIX/AGL HW state has
+                                                         been compromised. To recover, SW must issue a
+                                                         software reset sequence (see: MIX_CTL[RESET] */
+        uint64_t irun                    : 1;       /**< IRCNT UnderFlow Detected
+                                                         If SW writes a larger value than what is currently
+                                                         in the MIX_IRCNT[IRCNT], then HW will report the
+                                                         underflow condition.
+                                                         NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.
+                                                         NOTE: If an IRUN underflow condition is detected,
+                                                         the integrity of the MIX/AGL HW state has
+                                                         been compromised. To recover, SW must issue a
+                                                         software reset sequence (see: MIX_CTL[RESET] */
+        uint64_t data_drp                : 1;       /**< Data was dropped due to RX FIFO full
+                                                         If this does occur, the DATA_DRP is set and the
+                                                         CIU_INTx_SUM0,4[MII] bits are set.
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(DATA_DRPENA) is set, than an
+                                                         interrupt is reported for this event. */
+        uint64_t irthresh                : 1;       /**< Inbound Ring Packet Threshold Exceeded
+                                                         When the pending \#inbound packets in system
+                                                         memory(IRCNT) has exceeded a programmable threshold
+                                                         (IRHWM), then this bit is set. If this does occur,
+                                                         the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
+                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(ITHENA) is set, than an
+                                                         interrupt is reported for this event. */
+        uint64_t orthresh                : 1;       /**< Outbound Ring Packet Threshold Exceeded
+                                                         When the pending \#outbound packets in system
+                                                         memory(ORCNT) has exceeded a programmable threshold
+                                                         (ORHWM), then this bit is set. If this does occur,
+                                                         the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits
+                                                         are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(OTHENA) is set, than an
+                                                         interrupt is reported for this event. */
+        uint64_t idblovf                 : 1;       /**< Inbound DoorBell(IDBELL) Overflow Detected
+                                                         If SW attempts to write to the MIX_IRING2[IDBELL]
+                                                         with a value greater than the remaining \#of
+                                                         I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then
+                                                         the following occurs:
+                                                         1) The  MIX_IRING2[IDBELL] write is IGNORED
+                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
+                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(IVFENA) is set, than an
+                                                         interrupt is reported for this event.
+                                                         SW should keep track of the \#I-Ring Entries in use
+                                                         (ie: cumulative \# of IDBELL writes),  and ensure that
+                                                         future IDBELL writes don't exceed the size of the
+                                                         I-Ring Buffer (MIX_IRING2[ISIZE]).
+                                                         SW must reclaim I-Ring Entries by keeping track of the
+                                                         \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT].
+                                                         NOTE: The MIX_IRCNT[IRCNT] register represents the
+                                                         total \#packets(not IRing Entries) and SW must further
+                                                         keep track of the \# of I-Ring Entries associated with
+                                                         each packet as they are processed.
+                                                         NOTE: There is no recovery from an IDBLOVF Interrupt.
+                                                         If it occurs, it's an indication that SW has
+                                                         overwritten the I-Ring buffer, and the only recourse
+                                                         is a HW reset. */
+        uint64_t odblovf                 : 1;       /**< Outbound DoorBell(ODBELL) Overflow Detected
+                                                         If SW attempts to write to the MIX_ORING2[ODBELL]
+                                                         with a value greater than the remaining \#of
+                                                         O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then
+                                                         the following occurs:
+                                                         1) The  MIX_ORING2[ODBELL] write is IGNORED
+                                                         2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]
+                                                            bits are set if ((MIX_ISR & MIX_INTENA) != 0)).
+                                                         If both the global interrupt mask bits (CIU_INTx_EN*[MII])
+                                                         and the local interrupt mask bit(OVFENA) is set, than an
+                                                         interrupt is reported for this event.
+                                                         SW should keep track of the \#I-Ring Entries in use
+                                                         (ie: cumulative \# of ODBELL writes),  and ensure that
+                                                         future ODBELL writes don't exceed the size of the
+                                                         O-Ring Buffer (MIX_ORING2[OSIZE]).
+                                                         SW must reclaim O-Ring Entries by writing to the
+                                                         MIX_ORCNT[ORCNT]. .
+                                                         NOTE: There is no recovery from an ODBLOVF Interrupt.
+                                                         If it occurs, it's an indication that SW has
+                                                         overwritten the O-Ring buffer, and the only recourse
+                                                         is a HW reset. */
+#else
+        uint64_t odblovf                 : 1;
+        uint64_t idblovf                 : 1;
+        uint64_t orthresh                : 1;
+        uint64_t irthresh                : 1;
+        uint64_t data_drp                : 1;
+        uint64_t irun                    : 1;
+        uint64_t orun                    : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_mixx_isr_s               cn52xx;
+    struct cvmx_mixx_isr_s               cn52xxp1;
+    struct cvmx_mixx_isr_s               cn56xx;
+    struct cvmx_mixx_isr_s               cn56xxp1;
+} cvmx_mixx_isr_t;
+
+
+/**
+ * cvmx_mix#_orcnt
+ *
+ * MIX_ORCNT = MIX O-Ring Packets Sent Counter
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_orcnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t orcnt                   : 20;      /**< Pending \# of O-Ring Packets.
+                                                         Whenever HW removes a packet from the O-Ring, it
+                                                         increments the ORCNT (to indicate to SW the \# of
+                                                         Output packets in system memory that can be reclaimed).
+                                                         Reads of ORCNT return the current count.
+                                                         Writes of ORCNT decrement the count by the value
+                                                         written.
+                                                         This register is used to generate interrupts to alert
+                                                         SW of pending outbound MIX packets that have been
+                                                         removed from system memory. (see MIX_ISR[ORTHRESH]
+                                                         description for more details).
+                                                         NOTE: For outbound packets, the \# of O-Ring Packets
+                                                         is equal to the \# of O-Ring Entries. */
+#else
+        uint64_t orcnt                   : 20;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_mixx_orcnt_s             cn52xx;
+    struct cvmx_mixx_orcnt_s             cn52xxp1;
+    struct cvmx_mixx_orcnt_s             cn56xx;
+    struct cvmx_mixx_orcnt_s             cn56xxp1;
+} cvmx_mixx_orcnt_t;
+
+
+/**
+ * cvmx_mix#_orhwm
+ *
+ * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_orhwm_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t orhwm                   : 20;      /**< O-Ring Entry High Water Mark Threshold.
+                                                         Used to determine when the \# of Outbound packets
+                                                         in system memory that can be reclaimed
+                                                         (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold.
+                                                         NOTE: The power-on value of the CIU_INTx_EN*[MII]
+                                                         interrupt enable bits is zero and must be enabled
+                                                         to allow interrupts to be reported. */
+#else
+        uint64_t orhwm                   : 20;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_mixx_orhwm_s             cn52xx;
+    struct cvmx_mixx_orhwm_s             cn52xxp1;
+    struct cvmx_mixx_orhwm_s             cn56xx;
+    struct cvmx_mixx_orhwm_s             cn56xxp1;
+} cvmx_mixx_orhwm_t;
+
+
+/**
+ * cvmx_mix#_oring1
+ *
+ * MIX_ORING1 = MIX Outbound Ring Register \#1
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_oring1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t osize                   : 20;      /**< Represents the Outbound Ring Buffer's Size(in 8B
+                                                         words). The ring can be as large as 1M entries.
+                                                         NOTE: This CSR MUST BE setup written by SW poweron
+                                                         (when ODBELL/ORCNT=0). */
+        uint64_t reserved_36_39          : 4;
+        uint64_t obase                   : 33;      /**< Represents the 8B-aligned base address of the first
+                                                         Outbound Ring(O-Ring) Entry in system memory.
+                                                         NOTE: SW MUST ONLY write to this register during
+                                                         power-on/boot code. */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t obase                   : 33;
+        uint64_t reserved_36_39          : 4;
+        uint64_t osize                   : 20;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } s;
+    struct cvmx_mixx_oring1_s            cn52xx;
+    struct cvmx_mixx_oring1_s            cn52xxp1;
+    struct cvmx_mixx_oring1_s            cn56xx;
+    struct cvmx_mixx_oring1_s            cn56xxp1;
+} cvmx_mixx_oring1_t;
+
+
+/**
+ * cvmx_mix#_oring2
+ *
+ * MIX_ORING2 = MIX Outbound Ring Register \#2
+ * 
+ * Description:
+ *  NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO.
+ *        To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_oring2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_52_63          : 12;
+        uint64_t otlptr                  : 20;      /**< The Outbound Ring Tail Pointer selects the O-Ring
+                                                         Entry that the HW will process next. After the HW
+                                                         completes sending an outbound packet, it increments
+                                                         the O-Ring Tail Pointer. [NOTE: The O-Ring Tail
+                                                         Pointer HW increment is always modulo
+                                                         MIX_ORING2[OSIZE].
+                                                         NOTE: This field is 'read-only' to SW. */
+        uint64_t reserved_20_31          : 12;
+        uint64_t odbell                  : 20;      /**< Represents the cumulative total of pending
+                                                         Outbound Ring(O-Ring) Buffer Entries. Each O-Ring
+                                                         Buffer Entry contains 1) an L2/DRAM byte pointer
+                                                         along with a 2) a Byte Length.
+                                                         After SW inserts new entries into the O-Ring Buffer,
+                                                         it "rings the doorbell with the count of the newly
+                                                         inserted entries". When the MIX HW receives the
+                                                         doorbell ring, it increments the current doorbell
+                                                         count by the CSR write value.
+                                                         SW must never cause the doorbell count for the
+                                                         O-Ring to exceed the size of the ring(OSIZE).
+                                                         A read of the CSR indicates the current doorbell
+                                                         count. */
+#else
+        uint64_t odbell                  : 20;
+        uint64_t reserved_20_31          : 12;
+        uint64_t otlptr                  : 20;
+        uint64_t reserved_52_63          : 12;
+#endif
+    } s;
+    struct cvmx_mixx_oring2_s            cn52xx;
+    struct cvmx_mixx_oring2_s            cn52xxp1;
+    struct cvmx_mixx_oring2_s            cn56xx;
+    struct cvmx_mixx_oring2_s            cn56xxp1;
+} cvmx_mixx_oring2_t;
+
+
+/**
+ * cvmx_mix#_remcnt
+ *
+ * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only)
+ * 
+ * Description:
+ *  NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mixx_remcnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_52_63          : 12;
+        uint64_t iremcnt                 : 20;      /**< Remaining I-Ring Buffer Count
+                                                         Reflects the \# of unused/remaining I-Ring Entries
+                                                         that HW  currently detects in the I-Ring Buffer.
+                                                         HW uses this value to detect I-Ring Doorbell overflows.
+                                                         (see: MIX_ISR[IDBLOVF])
+                                                         When SW writes the MIX_IRING1[ISIZE], the IREMCNT
+                                                         is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only
+                                                         be written at power-on, when it's known that there are
+                                                         no I-Ring Entries currently in use by HW).
+                                                         When SW writes to the IDBELL register, the IREMCNT
+                                                         is decremented by the CSR write value.
+                                                         When HW issues an IRing Write Request(onto NCB Bus),
+                                                         the IREMCNT is incremented by 1. */
+        uint64_t reserved_20_31          : 12;
+        uint64_t oremcnt                 : 20;      /**< Remaining O-Ring Buffer Count
+                                                         Reflects the \# of unused/remaining O-Ring Entries
+                                                         that HW  currently detects in the O-Ring Buffer.
+                                                         HW uses this value to detect O-Ring Doorbell overflows.
+                                                         (see: MIX_ISR[ODBLOVF])
+                                                         When SW writes the MIX_IRING1[OSIZE], the OREMCNT
+                                                         is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only
+                                                         be written at power-on, when it's known that there are
+                                                         no O-Ring Entries currently in use by HW).
+                                                         When SW writes to the ODBELL register, the OREMCNT
+                                                         is decremented by the CSR write value.
+                                                         When SW writes to MIX_[OREMCNT], the OREMCNT is decremented
+                                                         by the CSR write value. */
+#else
+        uint64_t oremcnt                 : 20;
+        uint64_t reserved_20_31          : 12;
+        uint64_t iremcnt                 : 20;
+        uint64_t reserved_52_63          : 12;
+#endif
+    } s;
+    struct cvmx_mixx_remcnt_s            cn52xx;
+    struct cvmx_mixx_remcnt_s            cn52xxp1;
+    struct cvmx_mixx_remcnt_s            cn56xx;
+    struct cvmx_mixx_remcnt_s            cn56xxp1;
+} cvmx_mixx_remcnt_t;
+
+
+/**
+ * cvmx_mpi_cfg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mpi_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t clkdiv                  : 13;      /**< Fsclk = Feclk / (2 * CLKDIV)
+                                                         CLKDIV = Feclk / (2 * Fsclk) */
+        uint64_t reserved_12_15          : 4;
+        uint64_t cslate                  : 1;       /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
+                                                            1, MPI_CS assert coincident with transaction
+                                                         NOTE: only used if CSENA == 1 */
+        uint64_t tritx                   : 1;       /**< If 0, MPI_TX pin is driven when slave is not
+                                                               expected to be driving
+                                                            1, MPI_TX pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+        uint64_t idleclks                : 2;       /**< Guarantee IDLECLKS idle sclk cycles between
+                                                         commands. */
+        uint64_t cshi                    : 1;       /**< If 0, CS is low asserted
+                                                         1, CS is high asserted */
+        uint64_t csena                   : 1;       /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
+                                                         1, CS is driven per MPI_TX intruction */
+        uint64_t int_ena                 : 1;       /**< If 0, polling is required
+                                                         1, MPI engine interrupts X end of transaction */
+        uint64_t lsbfirst                : 1;       /**< If 0, shift MSB first
+                                                         1, shift LSB first */
+        uint64_t wireor                  : 1;       /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
+                                                               MPI_TX pin is always driven
+                                                            1, MPI_TX/RX is all from MPI_TX pin (MPI)
+                                                               MPI_TX pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, MPI_RX pin is not used by the
+                                                               MPI engine */
+        uint64_t clk_cont                : 1;       /**< If 0, clock idles to value given by IDLELO after
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+        uint64_t idlelo                  : 1;       /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
+                                                         1, MPI_CLK idles low, 1st transition is lo->hi */
+        uint64_t enable                  : 1;       /**< If 0, all MPI pins are GPIOs
+                                                         1, MPI_CLK, MPI_CS, and MPI_TX are driven */
+#else
+        uint64_t enable                  : 1;
+        uint64_t idlelo                  : 1;
+        uint64_t clk_cont                : 1;
+        uint64_t wireor                  : 1;
+        uint64_t lsbfirst                : 1;
+        uint64_t int_ena                 : 1;
+        uint64_t csena                   : 1;
+        uint64_t cshi                    : 1;
+        uint64_t idleclks                : 2;
+        uint64_t tritx                   : 1;
+        uint64_t cslate                  : 1;
+        uint64_t reserved_12_15          : 4;
+        uint64_t clkdiv                  : 13;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_mpi_cfg_s                cn30xx;
+    struct cvmx_mpi_cfg_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t clkdiv                  : 13;      /**< Fsclk = Feclk / (2 * CLKDIV)
+                                                         CLKDIV = Feclk / (2 * Fsclk) */
+        uint64_t reserved_11_15          : 5;
+        uint64_t tritx                   : 1;       /**< If 0, MPI_TX pin is driven when slave is not
+                                                               expected to be driving
+                                                            1, MPI_TX pin is tristated when not transmitting
+                                                         NOTE: only used when WIREOR==1 */
+        uint64_t idleclks                : 2;       /**< Guarantee IDLECLKS idle sclk cycles between
+                                                         commands. */
+        uint64_t cshi                    : 1;       /**< If 0, CS is low asserted
+                                                         1, CS is high asserted */
+        uint64_t csena                   : 1;       /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
+                                                         1, CS is driven per MPI_TX intruction */
+        uint64_t int_ena                 : 1;       /**< If 0, polling is required
+                                                         1, MPI engine interrupts X end of transaction */
+        uint64_t lsbfirst                : 1;       /**< If 0, shift MSB first
+                                                         1, shift LSB first */
+        uint64_t wireor                  : 1;       /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
+                                                               MPI_TX pin is always driven
+                                                            1, MPI_TX/RX is all from MPI_TX pin (MPI)
+                                                               MPI_TX pin is tristated when not transmitting
+                                                         NOTE: if WIREOR==1, MPI_RX pin is not used by the
+                                                               MPI engine */
+        uint64_t clk_cont                : 1;       /**< If 0, clock idles to value given by IDLELO after
+                                                            completion of MPI transaction
+                                                         1, clock never idles, requires CS deassertion
+                                                            assertion between commands */
+        uint64_t idlelo                  : 1;       /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
+                                                         1, MPI_CLK idles low, 1st transition is lo->hi */
+        uint64_t enable                  : 1;       /**< If 0, all MPI pins are GPIOs
+                                                         1, MPI_CLK, MPI_CS, and MPI_TX are driven */
+#else
+        uint64_t enable                  : 1;
+        uint64_t idlelo                  : 1;
+        uint64_t clk_cont                : 1;
+        uint64_t wireor                  : 1;
+        uint64_t lsbfirst                : 1;
+        uint64_t int_ena                 : 1;
+        uint64_t csena                   : 1;
+        uint64_t cshi                    : 1;
+        uint64_t idleclks                : 2;
+        uint64_t tritx                   : 1;
+        uint64_t reserved_11_15          : 5;
+        uint64_t clkdiv                  : 13;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn31xx;
+    struct cvmx_mpi_cfg_s                cn50xx;
+} cvmx_mpi_cfg_t;
+
+
+/**
+ * cvmx_mpi_dat#
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mpi_datx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t data                    : 8;       /**< Data to transmit/received */
+#else
+        uint64_t data                    : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_mpi_datx_s               cn30xx;
+    struct cvmx_mpi_datx_s               cn31xx;
+    struct cvmx_mpi_datx_s               cn50xx;
+} cvmx_mpi_datx_t;
+
+
+/**
+ * cvmx_mpi_sts
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mpi_sts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t rxnum                   : 5;       /**< Number of bytes written for transaction */
+        uint64_t reserved_1_7            : 7;
+        uint64_t busy                    : 1;       /**< If 0, no MPI transaction in progress
+                                                         1, MPI engine is processing a transaction */
+#else
+        uint64_t busy                    : 1;
+        uint64_t reserved_1_7            : 7;
+        uint64_t rxnum                   : 5;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_mpi_sts_s                cn30xx;
+    struct cvmx_mpi_sts_s                cn31xx;
+    struct cvmx_mpi_sts_s                cn50xx;
+} cvmx_mpi_sts_t;
+
+
+/**
+ * cvmx_mpi_tx
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_mpi_tx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t leavecs                 : 1;       /**< If 0, deassert CS after transaction is done
+                                                         1, leave CS asserted after transactrion is done */
+        uint64_t reserved_13_15          : 3;
+        uint64_t txnum                   : 5;       /**< Number of bytes to transmit */
+        uint64_t reserved_5_7            : 3;
+        uint64_t totnum                  : 5;       /**< Number of bytes to shift (transmit + receive) */
+#else
+        uint64_t totnum                  : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t txnum                   : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t leavecs                 : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_mpi_tx_s                 cn30xx;
+    struct cvmx_mpi_tx_s                 cn31xx;
+    struct cvmx_mpi_tx_s                 cn50xx;
+} cvmx_mpi_tx_t;
+
+
+/**
+ * cvmx_ndf_bt_pg_info
+ *
+ * Notes:
+ * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR
+ * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is
+ * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is
+ * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value.
+ * 
+ * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes.
+ * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values
+ * 
+ * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this
+ * field, and a SW CSR write with a value greater than 8, will write an 8 to this field.
+ * 
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_bt_pg_info_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t t_mult                  : 4;       /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
+                                                         command */
+        uint64_t adr_cyc                 : 4;       /**< # of column address cycles */
+        uint64_t size                    : 3;       /**< bytes per page in the nand device */
+#else
+        uint64_t size                    : 3;
+        uint64_t adr_cyc                 : 4;
+        uint64_t t_mult                  : 4;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_ndf_bt_pg_info_s         cn52xx;
+} cvmx_ndf_bt_pg_info_t;
+
+
+/**
+ * cvmx_ndf_cmd
+ *
+ * Notes:
+ * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes
+ * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it
+ * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these
+ * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr.
+ * 
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_cmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t nf_cmd                  : 64;      /**< 8 Command Bytes */
+#else
+        uint64_t nf_cmd                  : 64;
+#endif
+    } s;
+    struct cvmx_ndf_cmd_s                cn52xx;
+} cvmx_ndf_cmd_t;
+
+
+/**
+ * cvmx_ndf_drbell
+ *
+ * Notes:
+ * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value.
+ * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the
+ * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will
+ * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a
+ * non-zero data value, can the execution unit come out of the stalled condition, and resume execution.
+ * 
+ * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit
+ * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by
+ * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of
+ * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and
+ * the last command in the sequence will be a bus release command. The execution unit will start execution of
+ * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first
+ * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command
+ * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the
+ * CNT field by the number of the command sequences, loaded to the command fifo.
+ * 
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_drbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t cnt                     : 8;       /**< Doorbell count register, 2's complement 8 bit value */
+#else
+        uint64_t cnt                     : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_ndf_drbell_s             cn52xx;
+} cvmx_ndf_drbell_t;
+
+
+/**
+ * cvmx_ndf_ecc_cnt
+ *
+ * Notes:
+ * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256]
+ *         ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot
+ *         ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash
+ * 
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_ecc_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t xor_ecc                 : 24;      /**< result of XOR of ecc read bytes and ecc genarated
+                                                         bytes. The value pertains to the last 1 bit ecc err */
+        uint64_t ecc_err                 : 8;       /**< Count = \# of 1 bit errors fixed during boot
+                                                         This count saturates instead of wrapping around. */
+#else
+        uint64_t ecc_err                 : 8;
+        uint64_t xor_ecc                 : 24;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_ndf_ecc_cnt_s            cn52xx;
+} cvmx_ndf_ecc_cnt_t;
+
+
+/**
+ * cvmx_ndf_int
+ *
+ * Notes:
+ * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it.
+ * 
+ * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the
+ * last instruction out of the command fifo.
+ * 
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t ovrf                    : 1;       /**< NDF_CMD write when fifo is full. Generally a
+                                                         fatal error. */
+        uint64_t ecc_mult                : 1;       /**< Multi bit ECC error detected during boot */
+        uint64_t ecc_1bit                : 1;       /**< Single bit ECC error detected and fixed during boot */
+        uint64_t sm_bad                  : 1;       /**< One of the state machines in a bad state */
+        uint64_t wdog                    : 1;       /**< Watch Dog timer expired during command execution */
+        uint64_t full                    : 1;       /**< Command fifo is full */
+        uint64_t empty                   : 1;       /**< Command fifo is empty */
+#else
+        uint64_t empty                   : 1;
+        uint64_t full                    : 1;
+        uint64_t wdog                    : 1;
+        uint64_t sm_bad                  : 1;
+        uint64_t ecc_1bit                : 1;
+        uint64_t ecc_mult                : 1;
+        uint64_t ovrf                    : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_ndf_int_s                cn52xx;
+} cvmx_ndf_int_t;
+
+
+/**
+ * cvmx_ndf_int_en
+ *
+ * Notes:
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t ovrf                    : 1;       /**< Wrote to a full command fifo */
+        uint64_t ecc_mult                : 1;       /**< Multi bit ECC error detected during boot */
+        uint64_t ecc_1bit                : 1;       /**< Single bit ECC error detected and fixed during boot */
+        uint64_t sm_bad                  : 1;       /**< One of the state machines in a bad state */
+        uint64_t wdog                    : 1;       /**< Watch Dog timer expired during command execution */
+        uint64_t full                    : 1;       /**< Command fifo is full */
+        uint64_t empty                   : 1;       /**< Command fifo is empty */
+#else
+        uint64_t empty                   : 1;
+        uint64_t full                    : 1;
+        uint64_t wdog                    : 1;
+        uint64_t sm_bad                  : 1;
+        uint64_t ecc_1bit                : 1;
+        uint64_t ecc_mult                : 1;
+        uint64_t ovrf                    : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_ndf_int_en_s             cn52xx;
+} cvmx_ndf_int_en_t;
+
+
+/**
+ * cvmx_ndf_misc
+ *
+ * Notes:
+ * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo.
+ *   the fifo size is 16 entries.
+ * 
+ * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count
+ *   represents number of eclk cycles.
+ * 
+ * FR_BYT  this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands
+ *   complete execution and exit. (fifo is 256 bytes when BT_DIS=0,  and 1536 bytes when BT_DIS=1)
+ * 
+ * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo,
+ *   in response to RD_CMD bit being set to 1 by SW.
+ * 
+ * RD_VAL  this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response
+ *   to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0.
+ * 
+ * RD_CMD  this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the
+ *   RD_VAL bit in  this csr to see if next 8 bytes from the command fifo are available in the
+ *   NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the
+ *   middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD
+ *   bit will be cleared on any NDF_CMD csr write by SW.
+ * 
+ * BT_DMA  this indicates to the NAND flash boot control state machine that boot dma read can begin.
+ *   SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0
+ *   when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is
+ *   permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0.
+ * 
+ * BT_DIS  this R/W bit indicates to NAND flash boot control state machine that boot operation has ended.
+ *   whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must
+ *   never be set when booting from nand flash and region zero is enabled.
+ * 
+ * EX_DIS  When 1, command execution stops after completing execution of all commands currently in the command
+ *   fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution
+ *   will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo
+ *   is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0.
+ * 
+ * RST_FF  reset command fifo to make it empty, any command inflight is not aborted before reseting
+ *   the fifo. The fifo comes up empty at the end of power on reset.
+ * 
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_misc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t nbr_hwm                 : 3;       /**< Hi Water mark for NBR fifo or load/stores */
+        uint64_t wait_cnt                : 6;       /**< WAIT input filter count */
+        uint64_t fr_byt                  : 11;      /**< Number of unfilled Command fifo bytes */
+        uint64_t rd_done                 : 1;       /**< This W1C bit is set to 1 by HW when it completes
+                                                         command fifo read out, in response to RD_CMD */
+        uint64_t rd_val                  : 1;       /**< This RO bit is set to 1 by HW when it reads next 8
+                                                         bytes from Command fifo into the NDF_CMD csr
+                                                         SW reads NDF_CMD csr, HW clears this bit to 0 */
+        uint64_t rd_cmd                  : 1;       /**< When 1, HW reads out contents of the Command fifo 8
+                                                         bytes at a time into the NDF_CMD csr */
+        uint64_t bt_dma                  : 1;       /**< When set to 1, boot time dma is enabled */
+        uint64_t bt_dis                  : 1;       /**< When boot operation is over SW must set to 1
+                                                         causes boot state mchines to sleep */
+        uint64_t ex_dis                  : 1;       /**< When set to 1, suspends execution of commands at
+                                                         next command in the fifo. */
+        uint64_t rst_ff                  : 1;       /**< 1=reset command fifo to make it empty,
+                                                         0=normal operation */
+#else
+        uint64_t rst_ff                  : 1;
+        uint64_t ex_dis                  : 1;
+        uint64_t bt_dis                  : 1;
+        uint64_t bt_dma                  : 1;
+        uint64_t rd_cmd                  : 1;
+        uint64_t rd_val                  : 1;
+        uint64_t rd_done                 : 1;
+        uint64_t fr_byt                  : 11;
+        uint64_t wait_cnt                : 6;
+        uint64_t nbr_hwm                 : 3;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } s;
+    struct cvmx_ndf_misc_s               cn52xx;
+} cvmx_ndf_misc_t;
+
+
+/**
+ * cvmx_ndf_st_reg
+ *
+ * Notes:
+ * This CSR aggregates all state machines used in nand flash controller for debug.
+ * Like all NDF_... registers, 64-bit operations must be used to access this register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_ndf_st_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t exe_idle                : 1;       /**< Command Execution status 1=IDLE, 0=Busy
+                                                         1 means execution of command sequence is complete
+                                                         and command fifo is empty */
+        uint64_t exe_sm                  : 4;       /**< Command Execution State machine states */
+        uint64_t bt_sm                   : 4;       /**< Boot load and Boot dma State machine states */
+        uint64_t rd_ff_bad               : 1;       /**< CMD fifo read back State machine in bad state */
+        uint64_t rd_ff                   : 2;       /**< CMD fifo read back State machine states */
+        uint64_t main_bad                : 1;       /**< Main State machine in bad state */
+        uint64_t main_sm                 : 3;       /**< Main State machine states */
+#else
+        uint64_t main_sm                 : 3;
+        uint64_t main_bad                : 1;
+        uint64_t rd_ff                   : 2;
+        uint64_t rd_ff_bad               : 1;
+        uint64_t bt_sm                   : 4;
+        uint64_t exe_sm                  : 4;
+        uint64_t exe_idle                : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_ndf_st_reg_s             cn52xx;
+} cvmx_ndf_st_reg_t;
+
+
+/**
+ * cvmx_npei_bar1_index#
+ *
+ * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B)
+ * 
+ * General  5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General)
+ * PktMem  10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet)
+ * Rsvd     1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode)
+ *                                   == NPEI_PKT_CNT_INT_ENB[PORT]
+ *                                   == NPEI_PKT_TIME_INT_ENB[PORT]
+ *                                   == NPEI_PKT_CNT_INT[PORT]
+ *                                   == NPEI_PKT_TIME_INT[PORT]
+ *                                   == NPEI_PKT_PCIE_PORT[PP]
+ *                                   == NPEI_PKT_SLIST_ROR[ROR]
+ *                                   == NPEI_PKT_SLIST_ROR[NSR] ?
+ *                                   == NPEI_PKT_SLIST_ES[ES]
+ *                                   == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
+ *                                   == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
+ *                                   == NPEI_PKTn_CNTS[CNT]
+ * NPEI_CTL_STATUS[OUTn_ENB]         == NPEI_PKT_OUT_ENB[ENB]
+ * NPEI_BASE_ADDRESS_OUTPUTn[BADDR]  == NPEI_PKTn_SLIST_BADDR[ADDR]
+ * NPEI_DESC_OUTPUTn[SIZE]           == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE]
+ * NPEI_Pn_DBPAIR_ADDR[NADDR]        == NPEI_PKTn_SLIST_BADDR[ADDR] + NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF]
+ * NPEI_PKT_CREDITSn[PTR_CNT]        == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
+ * NPEI_P0_PAIR_CNTS[AVAIL]          == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL]
+ * NPEI_P0_PAIR_CNTS[FCNT]           ==
+ * NPEI_PKTS_SENTn[PKT_CNT]          == NPEI_PKTn_CNTS[CNT]
+ * NPEI_OUTPUT_CONTROL[Pn_BMODE]     == NPEI_PKT_OUT_BMODE[BMODE]
+ * NPEI_PKT_CREDITSn[PKT_CNT]        == NPEI_PKTn_CNTS[CNT]
+ * NPEI_BUFF_SIZE_OUTPUTn[BSIZE]     == NPEI_PKT_SLIST_ID_SIZE[BSIZE]
+ * NPEI_BUFF_SIZE_OUTPUTn[ISIZE]     == NPEI_PKT_SLIST_ID_SIZE[ISIZE]
+ * NPEI_OUTPUT_CONTROL[On_CSRM]      == NPEI_PKT_DPADDR[DPTR] & NPEI_PKT_OUT_USE_IPTR[PORT]
+ * NPEI_OUTPUT_CONTROL[On_ES]        == NPEI_PKT_DATA_OUT_ES[ES]
+ * NPEI_OUTPUT_CONTROL[On_NS]        == NPEI_PKT_DATA_OUT_NS[NSR] ?
+ * NPEI_OUTPUT_CONTROL[On_RO]        == NPEI_PKT_DATA_OUT_ROR[ROR]
+ * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT]  == NPEI_PKT_INT_LEVELS[CNT]
+ * NPEI_PKTS_SENT_TIMEn[PKT_TIME]    == NPEI_PKT_INT_LEVELS[TIME]
+ * NPEI_OUTPUT_CONTROL[IPTR_On]      == NPEI_PKT_IPTR[IPTR]
+ * NPEI_PCIE_PORT_OUTPUT[]           == NPEI_PKT_PCIE_PORT[PP]
+ * 
+ *                  NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register
+ * 
+ * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
+ * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16
+ * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_npei_bar1_indexx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_18_31          : 14;
+        uint32_t addr_idx                : 14;      /**< Address bits [35:22] sent to L2C */
+        uint32_t ca                      : 1;       /**< Set '1' when access is not to be cached in L2. */
+        uint32_t end_swp                 : 2;       /**< Endian Swap Mode */
+        uint32_t addr_v                  : 1;       /**< Set '1' when the selected address range is valid. */
+#else
+        uint32_t addr_v                  : 1;
+        uint32_t end_swp                 : 2;
+        uint32_t ca                      : 1;
+        uint32_t addr_idx                : 14;
+        uint32_t reserved_18_31          : 14;
+#endif
+    } s;
+    struct cvmx_npei_bar1_indexx_s       cn52xx;
+    struct cvmx_npei_bar1_indexx_s       cn52xxp1;
+    struct cvmx_npei_bar1_indexx_s       cn56xx;
+    struct cvmx_npei_bar1_indexx_s       cn56xxp1;
+} cvmx_npei_bar1_indexx_t;
+
+
+/**
+ * cvmx_npei_bist_status
+ *
+ * NPEI_BIST_STATUS = NPI's BIST Status Register
+ * 
+ * Results from BIST runs of NPEI's memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pkt_rdf                 : 1;       /**< BIST Status for PKT Read FIFO */
+        uint64_t reserved_60_62          : 3;
+        uint64_t pcr_gim                 : 1;       /**< BIST Status for PKT Gather Instr MEM */
+        uint64_t pkt_pif                 : 1;       /**< BIST Status for PKT INB FIFO */
+        uint64_t pcsr_int                : 1;       /**< BIST Status for PKT pout_int_bstatus */
+        uint64_t pcsr_im                 : 1;       /**< BIST Status for PKT pcsr_instr_mem_bstatus */
+        uint64_t pcsr_cnt                : 1;       /**< BIST Status for PKT pin_cnt_bstatus */
+        uint64_t pcsr_id                 : 1;       /**< BIST Status for PKT pcsr_in_done_bstatus */
+        uint64_t pcsr_sl                 : 1;       /**< BIST Status for PKT pcsr_slist_bstatus */
+        uint64_t reserved_50_52          : 3;
+        uint64_t pkt_ind                 : 1;       /**< BIST Status for PKT Instruction Done MEM */
+        uint64_t pkt_slm                 : 1;       /**< BIST Status for PKT SList MEM */
+        uint64_t reserved_36_47          : 12;
+        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
+        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
+        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
+        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
+        uint64_t reserved_31_31          : 1;
+        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
+        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
+        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
+        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
+        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
+        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
+        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
+        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
+        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
+        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
+        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
+        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
+        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
+        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
+        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
+        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
+        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
+        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
+        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
+        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
+        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
+        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
+        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
+        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
+        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t reserved_2_2            : 1;
+        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
+        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
+#else
+        uint64_t ncb_cmd                 : 1;
+        uint64_t msi                     : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t dif3                    : 1;
+        uint64_t dif2                    : 1;
+        uint64_t dif1                    : 1;
+        uint64_t dif0                    : 1;
+        uint64_t csm1                    : 1;
+        uint64_t csm0                    : 1;
+        uint64_t p2n1_p1                 : 1;
+        uint64_t p2n1_p0                 : 1;
+        uint64_t p2n1_n                  : 1;
+        uint64_t p2n1_c1                 : 1;
+        uint64_t p2n1_c0                 : 1;
+        uint64_t p2n0_p1                 : 1;
+        uint64_t p2n0_p0                 : 1;
+        uint64_t p2n0_n                  : 1;
+        uint64_t p2n0_c1                 : 1;
+        uint64_t p2n0_c0                 : 1;
+        uint64_t p2n0_co                 : 1;
+        uint64_t p2n0_no                 : 1;
+        uint64_t p2n0_po                 : 1;
+        uint64_t p2n1_co                 : 1;
+        uint64_t p2n1_no                 : 1;
+        uint64_t p2n1_po                 : 1;
+        uint64_t cpl_p1                  : 1;
+        uint64_t cpl_p0                  : 1;
+        uint64_t n2p1_o                  : 1;
+        uint64_t n2p1_c                  : 1;
+        uint64_t n2p0_o                  : 1;
+        uint64_t n2p0_c                  : 1;
+        uint64_t reserved_31_31          : 1;
+        uint64_t d3_pst                  : 1;
+        uint64_t d2_pst                  : 1;
+        uint64_t d1_pst                  : 1;
+        uint64_t d0_pst                  : 1;
+        uint64_t reserved_36_47          : 12;
+        uint64_t pkt_slm                 : 1;
+        uint64_t pkt_ind                 : 1;
+        uint64_t reserved_50_52          : 3;
+        uint64_t pcsr_sl                 : 1;
+        uint64_t pcsr_id                 : 1;
+        uint64_t pcsr_cnt                : 1;
+        uint64_t pcsr_im                 : 1;
+        uint64_t pcsr_int                : 1;
+        uint64_t pkt_pif                 : 1;
+        uint64_t pcr_gim                 : 1;
+        uint64_t reserved_60_62          : 3;
+        uint64_t pkt_rdf                 : 1;
+#endif
+    } s;
+    struct cvmx_npei_bist_status_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pkt_rdf                 : 1;       /**< BIST Status for PKT Read FIFO */
+        uint64_t reserved_60_62          : 3;
+        uint64_t pcr_gim                 : 1;       /**< BIST Status for PKT Gather Instr MEM */
+        uint64_t pkt_pif                 : 1;       /**< BIST Status for PKT INB FIFO */
+        uint64_t pcsr_int                : 1;       /**< BIST Status for PKT OUTB Interrupt MEM */
+        uint64_t pcsr_im                 : 1;       /**< BIST Status for PKT CSR Instr MEM */
+        uint64_t pcsr_cnt                : 1;       /**< BIST Status for PKT INB Count MEM */
+        uint64_t pcsr_id                 : 1;       /**< BIST Status for PKT INB Instr Done MEM */
+        uint64_t pcsr_sl                 : 1;       /**< BIST Status for PKT OUTB SLIST MEM */
+        uint64_t pkt_imem                : 1;       /**< BIST Status for PKT OUTB IFIFO */
+        uint64_t pkt_pfm                 : 1;       /**< BIST Status for PKT Front MEM */
+        uint64_t pkt_pof                 : 1;       /**< BIST Status for PKT OUTB FIFO */
+        uint64_t reserved_48_49          : 2;
+        uint64_t pkt_pop0                : 1;       /**< BIST Status for PKT OUTB Slist0 */
+        uint64_t pkt_pop1                : 1;       /**< BIST Status for PKT OUTB Slist1 */
+        uint64_t d0_mem                  : 1;       /**< BIST Status for DMA MEM 0 */
+        uint64_t d1_mem                  : 1;       /**< BIST Status for DMA MEM 1 */
+        uint64_t d2_mem                  : 1;       /**< BIST Status for DMA MEM 2 */
+        uint64_t d3_mem                  : 1;       /**< BIST Status for DMA MEM 3 */
+        uint64_t d4_mem                  : 1;       /**< BIST Status for DMA MEM 4 */
+        uint64_t ds_mem                  : 1;       /**< BIST Status for DMA  Memory */
+        uint64_t reserved_36_39          : 4;
+        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
+        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
+        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
+        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
+        uint64_t d4_pst                  : 1;       /**< BIST Status for DMA4 Pcie Store */
+        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
+        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
+        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
+        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
+        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
+        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
+        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
+        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
+        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
+        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
+        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
+        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
+        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
+        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
+        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
+        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
+        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
+        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
+        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
+        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
+        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
+        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
+        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
+        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
+        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif4                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
+        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
+#else
+        uint64_t ncb_cmd                 : 1;
+        uint64_t msi                     : 1;
+        uint64_t dif4                    : 1;
+        uint64_t dif3                    : 1;
+        uint64_t dif2                    : 1;
+        uint64_t dif1                    : 1;
+        uint64_t dif0                    : 1;
+        uint64_t csm1                    : 1;
+        uint64_t csm0                    : 1;
+        uint64_t p2n1_p1                 : 1;
+        uint64_t p2n1_p0                 : 1;
+        uint64_t p2n1_n                  : 1;
+        uint64_t p2n1_c1                 : 1;
+        uint64_t p2n1_c0                 : 1;
+        uint64_t p2n0_p1                 : 1;
+        uint64_t p2n0_p0                 : 1;
+        uint64_t p2n0_n                  : 1;
+        uint64_t p2n0_c1                 : 1;
+        uint64_t p2n0_c0                 : 1;
+        uint64_t p2n0_co                 : 1;
+        uint64_t p2n0_no                 : 1;
+        uint64_t p2n0_po                 : 1;
+        uint64_t p2n1_co                 : 1;
+        uint64_t p2n1_no                 : 1;
+        uint64_t p2n1_po                 : 1;
+        uint64_t cpl_p1                  : 1;
+        uint64_t cpl_p0                  : 1;
+        uint64_t n2p1_o                  : 1;
+        uint64_t n2p1_c                  : 1;
+        uint64_t n2p0_o                  : 1;
+        uint64_t n2p0_c                  : 1;
+        uint64_t d4_pst                  : 1;
+        uint64_t d3_pst                  : 1;
+        uint64_t d2_pst                  : 1;
+        uint64_t d1_pst                  : 1;
+        uint64_t d0_pst                  : 1;
+        uint64_t reserved_36_39          : 4;
+        uint64_t ds_mem                  : 1;
+        uint64_t d4_mem                  : 1;
+        uint64_t d3_mem                  : 1;
+        uint64_t d2_mem                  : 1;
+        uint64_t d1_mem                  : 1;
+        uint64_t d0_mem                  : 1;
+        uint64_t pkt_pop1                : 1;
+        uint64_t pkt_pop0                : 1;
+        uint64_t reserved_48_49          : 2;
+        uint64_t pkt_pof                 : 1;
+        uint64_t pkt_pfm                 : 1;
+        uint64_t pkt_imem                : 1;
+        uint64_t pcsr_sl                 : 1;
+        uint64_t pcsr_id                 : 1;
+        uint64_t pcsr_cnt                : 1;
+        uint64_t pcsr_im                 : 1;
+        uint64_t pcsr_int                : 1;
+        uint64_t pkt_pif                 : 1;
+        uint64_t pcr_gim                 : 1;
+        uint64_t reserved_60_62          : 3;
+        uint64_t pkt_rdf                 : 1;
+#endif
+    } cn52xx;
+    struct cvmx_npei_bist_status_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_46_63          : 18;
+        uint64_t d0_mem0                 : 1;       /**< BIST Status for DMA0 Memory */
+        uint64_t d1_mem1                 : 1;       /**< BIST Status for DMA1 Memory */
+        uint64_t d2_mem2                 : 1;       /**< BIST Status for DMA2 Memory */
+        uint64_t d3_mem3                 : 1;       /**< BIST Status for DMA3 Memory */
+        uint64_t dr0_mem                 : 1;       /**< BIST Status for DMA0 Store */
+        uint64_t d0_mem                  : 1;       /**< BIST Status for DMA0 Memory */
+        uint64_t d1_mem                  : 1;       /**< BIST Status for DMA1 Memory */
+        uint64_t d2_mem                  : 1;       /**< BIST Status for DMA2 Memory */
+        uint64_t d3_mem                  : 1;       /**< BIST Status for DMA3 Memory */
+        uint64_t dr1_mem                 : 1;       /**< BIST Status for DMA1 Store */
+        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
+        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
+        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
+        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
+        uint64_t dr2_mem                 : 1;       /**< BIST Status for DMA2 Store */
+        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
+        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
+        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
+        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
+        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
+        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
+        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
+        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
+        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
+        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
+        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
+        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
+        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
+        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
+        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
+        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
+        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
+        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
+        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
+        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
+        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
+        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
+        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
+        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
+        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dr3_mem                 : 1;       /**< BIST Status for DMA3 Store */
+        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
+        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
+#else
+        uint64_t ncb_cmd                 : 1;
+        uint64_t msi                     : 1;
+        uint64_t dr3_mem                 : 1;
+        uint64_t dif3                    : 1;
+        uint64_t dif2                    : 1;
+        uint64_t dif1                    : 1;
+        uint64_t dif0                    : 1;
+        uint64_t csm1                    : 1;
+        uint64_t csm0                    : 1;
+        uint64_t p2n1_p1                 : 1;
+        uint64_t p2n1_p0                 : 1;
+        uint64_t p2n1_n                  : 1;
+        uint64_t p2n1_c1                 : 1;
+        uint64_t p2n1_c0                 : 1;
+        uint64_t p2n0_p1                 : 1;
+        uint64_t p2n0_p0                 : 1;
+        uint64_t p2n0_n                  : 1;
+        uint64_t p2n0_c1                 : 1;
+        uint64_t p2n0_c0                 : 1;
+        uint64_t p2n0_co                 : 1;
+        uint64_t p2n0_no                 : 1;
+        uint64_t p2n0_po                 : 1;
+        uint64_t p2n1_co                 : 1;
+        uint64_t p2n1_no                 : 1;
+        uint64_t p2n1_po                 : 1;
+        uint64_t cpl_p1                  : 1;
+        uint64_t cpl_p0                  : 1;
+        uint64_t n2p1_o                  : 1;
+        uint64_t n2p1_c                  : 1;
+        uint64_t n2p0_o                  : 1;
+        uint64_t n2p0_c                  : 1;
+        uint64_t dr2_mem                 : 1;
+        uint64_t d3_pst                  : 1;
+        uint64_t d2_pst                  : 1;
+        uint64_t d1_pst                  : 1;
+        uint64_t d0_pst                  : 1;
+        uint64_t dr1_mem                 : 1;
+        uint64_t d3_mem                  : 1;
+        uint64_t d2_mem                  : 1;
+        uint64_t d1_mem                  : 1;
+        uint64_t d0_mem                  : 1;
+        uint64_t dr0_mem                 : 1;
+        uint64_t d3_mem3                 : 1;
+        uint64_t d2_mem2                 : 1;
+        uint64_t d1_mem1                 : 1;
+        uint64_t d0_mem0                 : 1;
+        uint64_t reserved_46_63          : 18;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_bist_status_cn52xx  cn56xx;
+    struct cvmx_npei_bist_status_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_58_63          : 6;
+        uint64_t pcsr_int                : 1;       /**< BIST Status for PKT pout_int_bstatus */
+        uint64_t pcsr_im                 : 1;       /**< BIST Status for PKT pcsr_instr_mem_bstatus */
+        uint64_t pcsr_cnt                : 1;       /**< BIST Status for PKT pin_cnt_bstatus */
+        uint64_t pcsr_id                 : 1;       /**< BIST Status for PKT pcsr_in_done_bstatus */
+        uint64_t pcsr_sl                 : 1;       /**< BIST Status for PKT pcsr_slist_bstatus */
+        uint64_t pkt_pout                : 1;       /**< BIST Status for PKT OUT Count MEM */
+        uint64_t pkt_imem                : 1;       /**< BIST Status for PKT Instruction MEM */
+        uint64_t pkt_cntm                : 1;       /**< BIST Status for PKT Count MEM */
+        uint64_t pkt_ind                 : 1;       /**< BIST Status for PKT Instruction Done MEM */
+        uint64_t pkt_slm                 : 1;       /**< BIST Status for PKT SList MEM */
+        uint64_t pkt_odf                 : 1;       /**< BIST Status for PKT Output Data FIFO */
+        uint64_t pkt_oif                 : 1;       /**< BIST Status for PKT Output INFO FIFO */
+        uint64_t pkt_out                 : 1;       /**< BIST Status for PKT Output FIFO */
+        uint64_t pkt_i0                  : 1;       /**< BIST Status for PKT Instr0 */
+        uint64_t pkt_i1                  : 1;       /**< BIST Status for PKT Instr1 */
+        uint64_t pkt_s0                  : 1;       /**< BIST Status for PKT Slist0 */
+        uint64_t pkt_s1                  : 1;       /**< BIST Status for PKT Slist1 */
+        uint64_t d0_mem                  : 1;       /**< BIST Status for DMA0 Memory */
+        uint64_t d1_mem                  : 1;       /**< BIST Status for DMA1 Memory */
+        uint64_t d2_mem                  : 1;       /**< BIST Status for DMA2 Memory */
+        uint64_t d3_mem                  : 1;       /**< BIST Status for DMA3 Memory */
+        uint64_t d4_mem                  : 1;       /**< BIST Status for DMA4 Memory */
+        uint64_t d0_pst                  : 1;       /**< BIST Status for DMA0 Pcie Store */
+        uint64_t d1_pst                  : 1;       /**< BIST Status for DMA1 Pcie Store */
+        uint64_t d2_pst                  : 1;       /**< BIST Status for DMA2 Pcie Store */
+        uint64_t d3_pst                  : 1;       /**< BIST Status for DMA3 Pcie Store */
+        uint64_t d4_pst                  : 1;       /**< BIST Status for DMA4 Pcie Store */
+        uint64_t n2p0_c                  : 1;       /**< BIST Status for N2P Port0 Cmd */
+        uint64_t n2p0_o                  : 1;       /**< BIST Status for N2P Port0 Data */
+        uint64_t n2p1_c                  : 1;       /**< BIST Status for N2P Port1 Cmd */
+        uint64_t n2p1_o                  : 1;       /**< BIST Status for N2P Port1 Data */
+        uint64_t cpl_p0                  : 1;       /**< BIST Status for CPL Port 0 */
+        uint64_t cpl_p1                  : 1;       /**< BIST Status for CPL Port 1 */
+        uint64_t p2n1_po                 : 1;       /**< BIST Status for P2N Port1 P Order */
+        uint64_t p2n1_no                 : 1;       /**< BIST Status for P2N Port1 N Order */
+        uint64_t p2n1_co                 : 1;       /**< BIST Status for P2N Port1 C Order */
+        uint64_t p2n0_po                 : 1;       /**< BIST Status for P2N Port0 P Order */
+        uint64_t p2n0_no                 : 1;       /**< BIST Status for P2N Port0 N Order */
+        uint64_t p2n0_co                 : 1;       /**< BIST Status for P2N Port0 C Order */
+        uint64_t p2n0_c0                 : 1;       /**< BIST Status for P2N Port0 C0 */
+        uint64_t p2n0_c1                 : 1;       /**< BIST Status for P2N Port0 C1 */
+        uint64_t p2n0_n                  : 1;       /**< BIST Status for P2N Port0 N */
+        uint64_t p2n0_p0                 : 1;       /**< BIST Status for P2N Port0 P0 */
+        uint64_t p2n0_p1                 : 1;       /**< BIST Status for P2N Port0 P1 */
+        uint64_t p2n1_c0                 : 1;       /**< BIST Status for P2N Port1 C0 */
+        uint64_t p2n1_c1                 : 1;       /**< BIST Status for P2N Port1 C1 */
+        uint64_t p2n1_n                  : 1;       /**< BIST Status for P2N Port1 N */
+        uint64_t p2n1_p0                 : 1;       /**< BIST Status for P2N Port1 P0 */
+        uint64_t p2n1_p1                 : 1;       /**< BIST Status for P2N Port1 P1 */
+        uint64_t csm0                    : 1;       /**< BIST Status for CSM0 */
+        uint64_t csm1                    : 1;       /**< BIST Status for CSM1 */
+        uint64_t dif0                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif1                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif2                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif3                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t dif4                    : 1;       /**< BIST Status for DMA Instr0 */
+        uint64_t msi                     : 1;       /**< BIST Status for MSI Memory Map */
+        uint64_t ncb_cmd                 : 1;       /**< BIST Status for NCB Outbound Commands */
+#else
+        uint64_t ncb_cmd                 : 1;
+        uint64_t msi                     : 1;
+        uint64_t dif4                    : 1;
+        uint64_t dif3                    : 1;
+        uint64_t dif2                    : 1;
+        uint64_t dif1                    : 1;
+        uint64_t dif0                    : 1;
+        uint64_t csm1                    : 1;
+        uint64_t csm0                    : 1;
+        uint64_t p2n1_p1                 : 1;
+        uint64_t p2n1_p0                 : 1;
+        uint64_t p2n1_n                  : 1;
+        uint64_t p2n1_c1                 : 1;
+        uint64_t p2n1_c0                 : 1;
+        uint64_t p2n0_p1                 : 1;
+        uint64_t p2n0_p0                 : 1;
+        uint64_t p2n0_n                  : 1;
+        uint64_t p2n0_c1                 : 1;
+        uint64_t p2n0_c0                 : 1;
+        uint64_t p2n0_co                 : 1;
+        uint64_t p2n0_no                 : 1;
+        uint64_t p2n0_po                 : 1;
+        uint64_t p2n1_co                 : 1;
+        uint64_t p2n1_no                 : 1;
+        uint64_t p2n1_po                 : 1;
+        uint64_t cpl_p1                  : 1;
+        uint64_t cpl_p0                  : 1;
+        uint64_t n2p1_o                  : 1;
+        uint64_t n2p1_c                  : 1;
+        uint64_t n2p0_o                  : 1;
+        uint64_t n2p0_c                  : 1;
+        uint64_t d4_pst                  : 1;
+        uint64_t d3_pst                  : 1;
+        uint64_t d2_pst                  : 1;
+        uint64_t d1_pst                  : 1;
+        uint64_t d0_pst                  : 1;
+        uint64_t d4_mem                  : 1;
+        uint64_t d3_mem                  : 1;
+        uint64_t d2_mem                  : 1;
+        uint64_t d1_mem                  : 1;
+        uint64_t d0_mem                  : 1;
+        uint64_t pkt_s1                  : 1;
+        uint64_t pkt_s0                  : 1;
+        uint64_t pkt_i1                  : 1;
+        uint64_t pkt_i0                  : 1;
+        uint64_t pkt_out                 : 1;
+        uint64_t pkt_oif                 : 1;
+        uint64_t pkt_odf                 : 1;
+        uint64_t pkt_slm                 : 1;
+        uint64_t pkt_ind                 : 1;
+        uint64_t pkt_cntm                : 1;
+        uint64_t pkt_imem                : 1;
+        uint64_t pkt_pout                : 1;
+        uint64_t pcsr_sl                 : 1;
+        uint64_t pcsr_id                 : 1;
+        uint64_t pcsr_cnt                : 1;
+        uint64_t pcsr_im                 : 1;
+        uint64_t pcsr_int                : 1;
+        uint64_t reserved_58_63          : 6;
+#endif
+    } cn56xxp1;
+} cvmx_npei_bist_status_t;
+
+
+/**
+ * cvmx_npei_bist_status2
+ *
+ * NPEI_BIST_STATUS2 = NPI's BIST Status Register2
+ * 
+ * Results from BIST runs of NPEI's memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_bist_status2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t prd_tag                 : 1;       /**< BIST Status for DMA PCIE RD Tag MEM */
+        uint64_t prd_st0                 : 1;       /**< BIST Status for DMA PCIE RD state MEM 0 */
+        uint64_t prd_st1                 : 1;       /**< BIST Status for DMA PCIE RD state MEM 1 */
+        uint64_t prd_err                 : 1;       /**< BIST Status for DMA PCIE RD ERR state MEM */
+        uint64_t nrd_st                  : 1;       /**< BIST Status for DMA L2C RD state MEM */
+        uint64_t nwe_st                  : 1;       /**< BIST Status for DMA L2C WR state MEM */
+        uint64_t nwe_wr0                 : 1;       /**< BIST Status for DMA L2C WR MEM 0 */
+        uint64_t nwe_wr1                 : 1;       /**< BIST Status for DMA L2C WR MEM 1 */
+        uint64_t pkt_rd                  : 1;       /**< BIST Status for Inbound PKT MEM */
+        uint64_t psc_p0                  : 1;       /**< BIST Status for PSC TLP 0 MEM */
+        uint64_t psc_p1                  : 1;       /**< BIST Status for PSC TLP 1 MEM */
+        uint64_t pkt_gd                  : 1;       /**< BIST Status for PKT OUTB Gather Data FIFO */
+        uint64_t pkt_gl                  : 1;       /**< BIST Status for PKT_OUTB Gather List FIFO */
+        uint64_t pkt_blk                 : 1;       /**< BIST Status for PKT OUTB Blocked FIFO */
+#else
+        uint64_t pkt_blk                 : 1;
+        uint64_t pkt_gl                  : 1;
+        uint64_t pkt_gd                  : 1;
+        uint64_t psc_p1                  : 1;
+        uint64_t psc_p0                  : 1;
+        uint64_t pkt_rd                  : 1;
+        uint64_t nwe_wr1                 : 1;
+        uint64_t nwe_wr0                 : 1;
+        uint64_t nwe_st                  : 1;
+        uint64_t nrd_st                  : 1;
+        uint64_t prd_err                 : 1;
+        uint64_t prd_st1                 : 1;
+        uint64_t prd_st0                 : 1;
+        uint64_t prd_tag                 : 1;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_npei_bist_status2_s      cn52xx;
+    struct cvmx_npei_bist_status2_s      cn56xx;
+} cvmx_npei_bist_status2_t;
+
+
+/**
+ * cvmx_npei_ctl_port0
+ *
+ * NPEI_CTL_PORT0 = NPEI's Control Port 0
+ * 
+ * Contains control for access for Port0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_ctl_port0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t waitl_com               : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional completions
+                                                         to the L2C from the PCIe.
+                                                         Set this for more conservative behavior. Clear
+                                                         this for more aggressive, higher-performance
+                                                         behavior */
+        uint64_t intd                    : 1;       /**< When '0' Intd wire asserted. Before mapping. */
+        uint64_t intc                    : 1;       /**< When '0' Intc wire asserted. Before mapping. */
+        uint64_t intb                    : 1;       /**< When '0' Intb wire asserted. Before mapping. */
+        uint64_t inta                    : 1;       /**< When '0' Inta wire asserted. Before mapping. */
+        uint64_t intd_map                : 2;       /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t intc_map                : 2;       /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t intb_map                : 2;       /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t inta_map                : 2;       /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t ctlp_ro                 : 1;       /**< Relaxed ordering enable for Completion TLPS. */
+        uint64_t reserved_6_6            : 1;
+        uint64_t ptlp_ro                 : 1;       /**< Relaxed ordering enable for Posted TLPS. */
+        uint64_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will cause UR responses. */
+        uint64_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+        uint64_t bar2_cax                : 1;       /**< Value will be XORed with pcie-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         Not cached in L2 if XOR result is 1 */
+        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional stores to
+                                                         the L2C from the PCIe.
+                                                         Most applications will not notice a difference, so
+                                                         should not set this bit. Setting the bit is more
+                                                         conservative on ordering, lower performance */
+#else
+        uint64_t wait_com                : 1;
+        uint64_t bar2_cax                : 1;
+        uint64_t bar2_esx                : 2;
+        uint64_t bar2_enb                : 1;
+        uint64_t ptlp_ro                 : 1;
+        uint64_t reserved_6_6            : 1;
+        uint64_t ctlp_ro                 : 1;
+        uint64_t inta_map                : 2;
+        uint64_t intb_map                : 2;
+        uint64_t intc_map                : 2;
+        uint64_t intd_map                : 2;
+        uint64_t inta                    : 1;
+        uint64_t intb                    : 1;
+        uint64_t intc                    : 1;
+        uint64_t intd                    : 1;
+        uint64_t waitl_com               : 1;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } s;
+    struct cvmx_npei_ctl_port0_s         cn52xx;
+    struct cvmx_npei_ctl_port0_s         cn52xxp1;
+    struct cvmx_npei_ctl_port0_s         cn56xx;
+    struct cvmx_npei_ctl_port0_s         cn56xxp1;
+} cvmx_npei_ctl_port0_t;
+
+
+/**
+ * cvmx_npei_ctl_port1
+ *
+ * NPEI_CTL_PORT1 = NPEI's Control Port1
+ * 
+ * Contains control for access for Port1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_ctl_port1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t waitl_com               : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional completions
+                                                         to the L2C from the PCIe.
+                                                         Set this for more conservative behavior. Clear
+                                                         this for more aggressive, higher-performance */
+        uint64_t intd                    : 1;       /**< When '0' Intd wire asserted. Before mapping. */
+        uint64_t intc                    : 1;       /**< When '0' Intc wire asserted. Before mapping. */
+        uint64_t intb                    : 1;       /**< When '0' Intv wire asserted. Before mapping. */
+        uint64_t inta                    : 1;       /**< When '0' Inta wire asserted. Before mapping. */
+        uint64_t intd_map                : 2;       /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t intc_map                : 2;       /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t intb_map                : 2;       /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t inta_map                : 2;       /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
+                                                         INTD (11). */
+        uint64_t ctlp_ro                 : 1;       /**< Relaxed ordering enable for Completion TLPS. */
+        uint64_t reserved_6_6            : 1;
+        uint64_t ptlp_ro                 : 1;       /**< Relaxed ordering enable for Posted TLPS. */
+        uint64_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will cause UR responses. */
+        uint64_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+        uint64_t bar2_cax                : 1;       /**< Value will be XORed with pcie-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         Not cached in L2 if XOR result is 1 */
+        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional stores to
+                                                         the L2C from the PCIe.
+                                                         Most applications will not notice a difference, so
+                                                         should not set this bit. Setting the bit is more
+                                                         conservative on ordering, lower performance */
+#else
+        uint64_t wait_com                : 1;
+        uint64_t bar2_cax                : 1;
+        uint64_t bar2_esx                : 2;
+        uint64_t bar2_enb                : 1;
+        uint64_t ptlp_ro                 : 1;
+        uint64_t reserved_6_6            : 1;
+        uint64_t ctlp_ro                 : 1;
+        uint64_t inta_map                : 2;
+        uint64_t intb_map                : 2;
+        uint64_t intc_map                : 2;
+        uint64_t intd_map                : 2;
+        uint64_t inta                    : 1;
+        uint64_t intb                    : 1;
+        uint64_t intc                    : 1;
+        uint64_t intd                    : 1;
+        uint64_t waitl_com               : 1;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } s;
+    struct cvmx_npei_ctl_port1_s         cn52xx;
+    struct cvmx_npei_ctl_port1_s         cn52xxp1;
+    struct cvmx_npei_ctl_port1_s         cn56xx;
+    struct cvmx_npei_ctl_port1_s         cn56xxp1;
+} cvmx_npei_ctl_port1_t;
+
+
+/**
+ * cvmx_npei_ctl_status
+ *
+ * NPEI_CTL_STATUS = NPEI Control Status Register
+ * 
+ * Contains control and status for NPEI. Writes to this register are not oSrdered with writes/reads to the PCIe Memory space.
+ * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space)
+ * that requires the value of this register to be updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t p1_ntags                : 6;       /**< Number of tags avaiable for PCIe Port1.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+        uint64_t p0_ntags                : 6;       /**< Number of tags avaiable for PCIe Port0.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+        uint64_t cfg_rtry                : 16;      /**< The time x 0x10000 in core clocks to wait for a
+                                                         CPL to a CFG RD that does not carry a Retry Status.
+                                                         Until such time that the timeout occurs and Retry
+                                                         Status is received for a CFG RD, the Read CFG Read
+                                                         will be resent. A value of 0 disables retries and
+                                                         treats a CPL Retry as a CPL UR. */
+        uint64_t ring_en                 : 1;       /**< When '0' forces "relative Q position" received
+                                                         from PKO to be zero, and replicates the back-
+                                                         pressure indication for the first ring attached
+                                                         to a PKO port across all the rings attached to a
+                                                         PKO port. When '0', only rings 0-3 can be used. */
+        uint64_t lnk_rst                 : 1;       /**< Set when PCIe Core 0 request a link reset due to
+                                                         link down state. This bit is only reset on raw
+                                                         reset so it can be read for state to determine if
+                                                         a reset occured. Bit is cleared when a '1' is
+                                                         written to this field. */
+        uint64_t arb                     : 1;       /**< PCIe switch arbitration mode. '0' == fixed priority
+                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
+        uint64_t pkt_bp                  : 4;       /**< Unused */
+        uint64_t host_mode               : 1;       /**< Host mode */
+        uint64_t chip_rev                : 8;       /**< The chip revision. */
+#else
+        uint64_t chip_rev                : 8;
+        uint64_t host_mode               : 1;
+        uint64_t pkt_bp                  : 4;
+        uint64_t arb                     : 1;
+        uint64_t lnk_rst                 : 1;
+        uint64_t ring_en                 : 1;
+        uint64_t cfg_rtry                : 16;
+        uint64_t p0_ntags                : 6;
+        uint64_t p1_ntags                : 6;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npei_ctl_status_s        cn52xx;
+    struct cvmx_npei_ctl_status_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t p1_ntags                : 6;       /**< Number of tags avaiable for PCIe Port1.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+        uint64_t p0_ntags                : 6;       /**< Number of tags avaiable for PCIe Port0.
+                                                         In RC mode 1 tag is needed for each outbound TLP
+                                                         that requires a CPL TLP. In Endpoint mode the
+                                                         number of tags required for a TLP request is
+                                                         1 per 64-bytes of CPL data + 1.
+                                                         This field should only be written as part of
+                                                         reset sequence, before issuing any reads, CFGs, or
+                                                         IO transactions from the core(s). */
+        uint64_t cfg_rtry                : 16;      /**< The time x 0x10000 in core clocks to wait for a
+                                                         CPL to a CFG RD that does not carry a Retry Status.
+                                                         Until such time that the timeout occurs and Retry
+                                                         Status is received for a CFG RD, the Read CFG Read
+                                                         will be resent. A value of 0 disables retries and
+                                                         treats a CPL Retry as a CPL UR. */
+        uint64_t reserved_15_15          : 1;
+        uint64_t lnk_rst                 : 1;       /**< Set when PCIe Core 0 request a link reset due to
+                                                         link down state. This bit is only reset on raw
+                                                         reset so it can be read for state to determine if
+                                                         a reset occured. Bit is cleared when a '1' is
+                                                         written to this field. */
+        uint64_t arb                     : 1;       /**< PCIe switch arbitration mode. '0' == fixed priority
+                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
+        uint64_t reserved_9_12           : 4;
+        uint64_t host_mode               : 1;       /**< Host mode */
+        uint64_t chip_rev                : 8;       /**< The chip revision. */
+#else
+        uint64_t chip_rev                : 8;
+        uint64_t host_mode               : 1;
+        uint64_t reserved_9_12           : 4;
+        uint64_t arb                     : 1;
+        uint64_t lnk_rst                 : 1;
+        uint64_t reserved_15_15          : 1;
+        uint64_t cfg_rtry                : 16;
+        uint64_t p0_ntags                : 6;
+        uint64_t p1_ntags                : 6;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_ctl_status_s        cn56xx;
+    struct cvmx_npei_ctl_status_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t lnk_rst                 : 1;       /**< Set when PCIe Core 0 request a link reset due to
+                                                         link down state. This bit is only reset on raw
+                                                         reset so it can be read for state to determine if
+                                                         a reset occured. Bit is cleared when a '1' is
+                                                         written to this field. */
+        uint64_t arb                     : 1;       /**< PCIe switch arbitration mode. '0' == fixed priority
+                                                         NPEI, PCIe0, then PCIe1. '1' == round robin. */
+        uint64_t pkt_bp                  : 4;       /**< Unused */
+        uint64_t host_mode               : 1;       /**< Host mode */
+        uint64_t chip_rev                : 8;       /**< The chip revision. */
+#else
+        uint64_t chip_rev                : 8;
+        uint64_t host_mode               : 1;
+        uint64_t pkt_bp                  : 4;
+        uint64_t arb                     : 1;
+        uint64_t lnk_rst                 : 1;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } cn56xxp1;
+} cvmx_npei_ctl_status_t;
+
+
+/**
+ * cvmx_npei_ctl_status2
+ *
+ * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register
+ * 
+ * Contains control and status for NPEI.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_ctl_status2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mps                     : 1;       /**< Max Payload Size
+                                                                  0  = 128B
+                                                                  1  = 256B
+                                                         Note: PCIE*_CFG030[MPS] must be set to the same
+                                                               value for proper function. */
+        uint64_t mrrs                    : 3;       /**< Max Read Request Size
+                                                                 0 = 128B
+                                                                 1 = 256B
+                                                                 2 = 512B
+                                                                 3 = 1024B
+                                                                 4 = 2048B
+                                                                 5 = 4096B
+                                                         Note: This field must not exceed the desired
+                                                               max read request size. This means this field
+                                                               should not exceed PCIE*_CFG030[MRRS]. */
+        uint64_t c1_w_flt                : 1;       /**< When '1' enables the window filter for reads and
+                                                         writes using the window registers.
+                                                         PCIE-Port1.
+                                                         Unfilter writes are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId1
+                                                         POW,   SubId2
+                                                         POW,   SubId3
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7 */
+        uint64_t c0_w_flt                : 1;       /**< When '1' enables the window filter for reads and
+                                                         writes using the window registers.
+                                                         PCIE-Port0.
+                                                         Unfilter writes are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO,   SubId0
+                                                         MIO,   SubId7
+                                                         NPEI,  SubId0
+                                                         NPEI,  SubId7
+                                                         POW,   SubId1
+                                                         POW,   SubId2
+                                                         POW,   SubId3
+                                                         POW,   SubId7
+                                                         IPD,   SubId7
+                                                         USBN0, SubId7 */
+        uint64_t c1_b1_s                 : 3;       /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB,
+                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
+                                                         0 and 7 are reserved. */
+        uint64_t c0_b1_s                 : 3;       /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
+                                                         3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
+                                                         0 and 7 are reserved. */
+        uint64_t c1_wi_d                 : 1;       /**< When set '1' disables access to the Window
+                                                         Registers from the PCIe-Port1. */
+        uint64_t c1_b0_d                 : 1;       /**< When set '1' disables access from PCIe-Port1 to
+                                                         BAR-0 address offsets: Less Than 0x270,
+                                                         Greater than 0x270 AND less than 0x0520, 0x3BC0,
+                                                         0x3CD0. */
+        uint64_t c0_wi_d                 : 1;       /**< When set '1' disables access to the Window
+                                                         Registers from the PCIe-Port0. */
+        uint64_t c0_b0_d                 : 1;       /**< When set '1' disables access from PCIe-Port0 to
+                                                         BAR-0 address offsets: Less Than 0x270,
+                                                         Greater than 0x270 AND less than 0x0520, 0x3BC0,
+                                                         0x3CD0. */
+#else
+        uint64_t c0_b0_d                 : 1;
+        uint64_t c0_wi_d                 : 1;
+        uint64_t c1_b0_d                 : 1;
+        uint64_t c1_wi_d                 : 1;
+        uint64_t c0_b1_s                 : 3;
+        uint64_t c1_b1_s                 : 3;
+        uint64_t c0_w_flt                : 1;
+        uint64_t c1_w_flt                : 1;
+        uint64_t mrrs                    : 3;
+        uint64_t mps                     : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npei_ctl_status2_s       cn52xx;
+    struct cvmx_npei_ctl_status2_s       cn52xxp1;
+    struct cvmx_npei_ctl_status2_s       cn56xx;
+    struct cvmx_npei_ctl_status2_s       cn56xxp1;
+} cvmx_npei_ctl_status2_t;
+
+
+/**
+ * cvmx_npei_data_out_cnt
+ *
+ * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT
+ * 
+ * The EXEC data out fifo-count and the data unload counter.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_data_out_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t p1_ucnt                 : 16;      /**< PCIE-Port1 Fifo Unload Count. This counter is
+                                                         incremented by '1' every time a word is removed
+                                                         from the Data Out FIFO, whose count is shown in
+                                                         P0_FCNT. */
+        uint64_t p1_fcnt                 : 6;       /**< PCIE-Port1 Data Out Fifo Count. Number of address
+                                                         data words to be sent out the PCIe port presently
+                                                         buffered in the FIFO. */
+        uint64_t p0_ucnt                 : 16;      /**< PCIE-Port0 Fifo Unload Count. This counter is
+                                                         incremented by '1' every time a word is removed
+                                                         from the Data Out FIFO, whose count is shown in
+                                                         P0_FCNT. */
+        uint64_t p0_fcnt                 : 6;       /**< PCIE-Port0 Data Out Fifo Count. Number of address
+                                                         data words to be sent out the PCIe port presently
+                                                         buffered in the FIFO. */
+#else
+        uint64_t p0_fcnt                 : 6;
+        uint64_t p0_ucnt                 : 16;
+        uint64_t p1_fcnt                 : 6;
+        uint64_t p1_ucnt                 : 16;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npei_data_out_cnt_s      cn52xx;
+    struct cvmx_npei_data_out_cnt_s      cn52xxp1;
+    struct cvmx_npei_data_out_cnt_s      cn56xx;
+    struct cvmx_npei_data_out_cnt_s      cn56xxp1;
+} cvmx_npei_data_out_cnt_t;
+
+
+/**
+ * cvmx_npei_dbg_data
+ *
+ * NPEI_DBG_DATA = NPEI Debug Data Register
+ * 
+ * Value returned on the debug-data lines from the RSLs
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dbg_data_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t qlm0_rev_lanes          : 1;       /**< Lane reversal for PCIe port 0 */
+        uint64_t reserved_25_26          : 2;
+        uint64_t qlm1_spd                : 2;       /**< Sets the QLM1 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+        uint64_t c_mul                   : 5;       /**< PLL_MUL pins sampled at DCOK assertion
+                                                         Core frequency = 50MHz*C_MUL */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t qlm1_spd                : 2;
+        uint64_t reserved_25_26          : 2;
+        uint64_t qlm0_rev_lanes          : 1;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_npei_dbg_data_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t qlm0_link_width         : 1;       /**< Link width of PCIe port 0
+                                                         0 = PCIe port 0 is 2 lanes,
+                                                             2 lane PCIe port 1 exists
+                                                         1 = PCIe port 0 is 4 lanes,
+                                                             PCIe port 1 does not exist */
+        uint64_t qlm0_rev_lanes          : 1;       /**< Lane reversal for PCIe port 0 */
+        uint64_t qlm1_mode               : 2;       /**< Sets the QLM1 Mode
+                                                         0=Reserved
+                                                         1=XAUI
+                                                         2=SGMII
+                                                         3=PICMG */
+        uint64_t qlm1_spd                : 2;       /**< Sets the QLM1 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+        uint64_t c_mul                   : 5;       /**< PLL_MUL pins sampled at DCOK assertion
+                                                         Core frequency = 50MHz*C_MUL */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t qlm1_spd                : 2;
+        uint64_t qlm1_mode               : 2;
+        uint64_t qlm0_rev_lanes          : 1;
+        uint64_t qlm0_link_width         : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn52xx;
+    struct cvmx_npei_dbg_data_cn52xx     cn52xxp1;
+    struct cvmx_npei_dbg_data_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t qlm2_rev_lanes          : 1;       /**< Lane reversal for PCIe port 1 */
+        uint64_t qlm0_rev_lanes          : 1;       /**< Lane reversal for PCIe port 0 */
+        uint64_t qlm3_spd                : 2;       /**< Sets the QLM3 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+        uint64_t qlm1_spd                : 2;       /**< Sets the QLM1 frequency
+                                                         0=1.25 Gbaud
+                                                         1=2.5 Gbaud
+                                                         2=3.125 Gbaud
+                                                         3=3.75 Gbaud */
+        uint64_t c_mul                   : 5;       /**< PLL_MUL pins sampled at DCOK assertion
+                                                         Core frequency = 50MHz*C_MUL */
+        uint64_t dsel_ext                : 1;       /**< Allows changes in the external pins to set the
+                                                         debug select value. */
+        uint64_t data                    : 17;      /**< Value on the debug data lines. */
+#else
+        uint64_t data                    : 17;
+        uint64_t dsel_ext                : 1;
+        uint64_t c_mul                   : 5;
+        uint64_t qlm1_spd                : 2;
+        uint64_t qlm3_spd                : 2;
+        uint64_t qlm0_rev_lanes          : 1;
+        uint64_t qlm2_rev_lanes          : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn56xx;
+    struct cvmx_npei_dbg_data_cn56xx     cn56xxp1;
+} cvmx_npei_dbg_data_t;
+
+
+/**
+ * cvmx_npei_dbg_select
+ *
+ * NPEI_DBG_SELECT = Debug Select Register
+ * 
+ * Contains the debug select value last written to the RSLs.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dbg_select_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dbg_sel                 : 16;      /**< When this register is written its value is sent to
+                                                         all RSLs. */
+#else
+        uint64_t dbg_sel                 : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npei_dbg_select_s        cn52xx;
+    struct cvmx_npei_dbg_select_s        cn52xxp1;
+    struct cvmx_npei_dbg_select_s        cn56xx;
+    struct cvmx_npei_dbg_select_s        cn56xxp1;
+} cvmx_npei_dbg_select_t;
+
+
+/**
+ * cvmx_npei_dma#_counts
+ *
+ * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts
+ * 
+ * Values for determing the number of instructions for DMA[0..4] in the NPEI.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dmax_counts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t fcnt                    : 7;       /**< Number of words in the Instruction FIFO. */
+        uint64_t dbell                   : 32;      /**< Number of available words of Instructions to read. */
+#else
+        uint64_t dbell                   : 32;
+        uint64_t fcnt                    : 7;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } s;
+    struct cvmx_npei_dmax_counts_s       cn52xx;
+    struct cvmx_npei_dmax_counts_s       cn52xxp1;
+    struct cvmx_npei_dmax_counts_s       cn56xx;
+    struct cvmx_npei_dmax_counts_s       cn56xxp1;
+} cvmx_npei_dmax_counts_t;
+
+
+/**
+ * cvmx_npei_dma#_dbell
+ *
+ * NPEI_DMA_DBELL[0..4] = DMA Door Bell
+ * 
+ * The door bell register for DMA[0..4] queue.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_npei_dmax_dbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t dbell                   : 16;      /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the low priority dma queue. */
+#else
+        uint32_t dbell                   : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_npei_dmax_dbell_s        cn52xx;
+    struct cvmx_npei_dmax_dbell_s        cn52xxp1;
+    struct cvmx_npei_dmax_dbell_s        cn56xx;
+    struct cvmx_npei_dmax_dbell_s        cn56xxp1;
+} cvmx_npei_dmax_dbell_t;
+
+
+/**
+ * cvmx_npei_dma#_ibuff_saddr
+ *
+ * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
+ * 
+ * The address to start reading Instructions from for DMA[0..4].
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dmax_ibuff_saddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t idle                    : 1;       /**< DMA Engine IDLE state */
+        uint64_t saddr                   : 29;      /**< The 128 byte aligned starting address to read the
+                                                         first instruction. SADDR is address bit 35:7 of the
+                                                         first instructions address. */
+        uint64_t reserved_0_6            : 7;
+#else
+        uint64_t reserved_0_6            : 7;
+        uint64_t saddr                   : 29;
+        uint64_t idle                    : 1;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } s;
+    struct cvmx_npei_dmax_ibuff_saddr_s  cn52xx;
+    struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t saddr                   : 29;      /**< The 128 byte aligned starting address to read the
+                                                         first instruction. SADDR is address bit 35:7 of the
+                                                         first instructions address. */
+        uint64_t reserved_0_6            : 7;
+#else
+        uint64_t reserved_0_6            : 7;
+        uint64_t saddr                   : 29;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_dmax_ibuff_saddr_s  cn56xx;
+    struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
+} cvmx_npei_dmax_ibuff_saddr_t;
+
+
+/**
+ * cvmx_npei_dma#_naddr
+ *
+ * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address
+ * 
+ * Place NPEI will read the next Ichunk data from. This is valid when state is 0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dmax_naddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< The next L2C address to read DMA# instructions
+                                                         from. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_npei_dmax_naddr_s        cn52xx;
+    struct cvmx_npei_dmax_naddr_s        cn52xxp1;
+    struct cvmx_npei_dmax_naddr_s        cn56xx;
+    struct cvmx_npei_dmax_naddr_s        cn56xxp1;
+} cvmx_npei_dmax_naddr_t;
+
+
+/**
+ * cvmx_npei_dma0_int_level
+ *
+ * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level
+ * 
+ * Thresholds for DMA count and timer interrupts for DMA0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma0_int_level_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t time                    : 32;      /**< Whenever the DMA_CNT0 timer exceeds
+                                                         this value, NPEI_INT_SUM[DTIME0] is set.
+                                                         The DMA_CNT0 timer increments every core clock
+                                                         whenever NPEI_DMA_CNTS[DMA0]!=0, and is cleared
+                                                         when NPEI_INT_SUM[DTIME0] is written with one. */
+        uint64_t cnt                     : 32;      /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value,
+                                                         NPEI_INT_SUM[DCNT0] is set. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t time                    : 32;
+#endif
+    } s;
+    struct cvmx_npei_dma0_int_level_s    cn52xx;
+    struct cvmx_npei_dma0_int_level_s    cn52xxp1;
+    struct cvmx_npei_dma0_int_level_s    cn56xx;
+    struct cvmx_npei_dma0_int_level_s    cn56xxp1;
+} cvmx_npei_dma0_int_level_t;
+
+
+/**
+ * cvmx_npei_dma1_int_level
+ *
+ * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level
+ * 
+ * Thresholds for DMA count and timer interrupts for DMA1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma1_int_level_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t time                    : 32;      /**< Whenever the DMA_CNT1 timer exceeds
+                                                         this value, NPEI_INT_SUM[DTIME1] is set.
+                                                         The DMA_CNT1 timer increments every core clock
+                                                         whenever NPEI_DMA_CNTS[DMA1]!=0, and is cleared
+                                                         when NPEI_INT_SUM[DTIME1] is written with one. */
+        uint64_t cnt                     : 32;      /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value,
+                                                         NPEI_INT_SUM[DCNT1] is set. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t time                    : 32;
+#endif
+    } s;
+    struct cvmx_npei_dma1_int_level_s    cn52xx;
+    struct cvmx_npei_dma1_int_level_s    cn52xxp1;
+    struct cvmx_npei_dma1_int_level_s    cn56xx;
+    struct cvmx_npei_dma1_int_level_s    cn56xxp1;
+} cvmx_npei_dma1_int_level_t;
+
+
+/**
+ * cvmx_npei_dma_cnts
+ *
+ * NPEI_DMA_CNTS = NPEI DMA Count
+ * 
+ * The DMA Count values for DMA0 and DMA1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_cnts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dma1                    : 32;      /**< The DMA counter 1.
+                                                         Writing this field will cause the written value to
+                                                         be subtracted from DMA1. SW should use a 4-byte
+                                                         write to access this field so as not to change the
+                                                         value of other fields in this register.
+                                                         HW will optionally increment this field after
+                                                         it completes an OUTBOUND or EXTERNAL-ONLY DMA
+                                                         instruction. These increments may cause interrupts.
+                                                         Refer to NPEI_DMA1_INT_LEVEL and
+                                                         NPEI_INT_SUM[DCNT1,DTIME1]. */
+        uint64_t dma0                    : 32;      /**< The DMA counter 0.
+                                                         Writing this field will cause the written value to
+                                                         be subtracted from DMA0. SW should use a 4-byte
+                                                         write to access this field so as not to change the
+                                                         value of other fields in this register.
+                                                         HW will optionally increment this field after
+                                                         it completes an OUTBOUND or EXTERNAL-ONLY DMA
+                                                         instruction. These increments may cause interrupts.
+                                                         Refer to NPEI_DMA0_INT_LEVEL and
+                                                         NPEI_INT_SUM[DCNT0,DTIME0]. */
+#else
+        uint64_t dma0                    : 32;
+        uint64_t dma1                    : 32;
+#endif
+    } s;
+    struct cvmx_npei_dma_cnts_s          cn52xx;
+    struct cvmx_npei_dma_cnts_s          cn52xxp1;
+    struct cvmx_npei_dma_cnts_s          cn56xx;
+    struct cvmx_npei_dma_cnts_s          cn56xxp1;
+} cvmx_npei_dma_cnts_t;
+
+
+/**
+ * cvmx_npei_dma_control
+ *
+ * NPEI_DMA_CONTROL = DMA Control Register
+ * 
+ * Controls operation of the DMA IN/OUT.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t p_32b_m                 : 1;       /**< DMA PCIE 32-bit word read disable bit
+                                                         When 0, enable the feature */
+        uint64_t dma4_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma3_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma2_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma1_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma0_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPEI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+        uint64_t dwb_denb                : 1;       /**< When set '1' the NPEI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
+        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
+        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
+        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+        uint64_t csize                   : 14;
+        uint64_t o_mode                  : 1;
+        uint64_t o_es                    : 2;
+        uint64_t o_ns                    : 1;
+        uint64_t o_ro                    : 1;
+        uint64_t o_add1                  : 1;
+        uint64_t fpa_que                 : 3;
+        uint64_t dwb_ichk                : 9;
+        uint64_t dwb_denb                : 1;
+        uint64_t b0_lend                 : 1;
+        uint64_t dma0_enb                : 1;
+        uint64_t dma1_enb                : 1;
+        uint64_t dma2_enb                : 1;
+        uint64_t dma3_enb                : 1;
+        uint64_t dma4_enb                : 1;
+        uint64_t p_32b_m                 : 1;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_npei_dma_control_s       cn52xx;
+    struct cvmx_npei_dma_control_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t dma3_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma2_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma1_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma0_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPEI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+        uint64_t dwb_denb                : 1;       /**< When set '1' the NPEI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
+        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
+        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
+        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+        uint64_t csize                   : 14;
+        uint64_t o_mode                  : 1;
+        uint64_t o_es                    : 2;
+        uint64_t o_ns                    : 1;
+        uint64_t o_ro                    : 1;
+        uint64_t o_add1                  : 1;
+        uint64_t fpa_que                 : 3;
+        uint64_t dwb_ichk                : 9;
+        uint64_t dwb_denb                : 1;
+        uint64_t b0_lend                 : 1;
+        uint64_t dma0_enb                : 1;
+        uint64_t dma1_enb                : 1;
+        uint64_t dma2_enb                : 1;
+        uint64_t dma3_enb                : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_dma_control_s       cn56xx;
+    struct cvmx_npei_dma_control_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t dma4_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma3_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma2_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma1_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t dma0_enb                : 1;       /**< DMA# enable. Enables the operation of the DMA
+                                                         engine. After being enabled a DMA engine should not
+                                                         be dis-abled while processing instructions. */
+        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPEI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. */
+        uint64_t dwb_denb                : 1;       /**< When set '1' the NPEI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data. */
+        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
+        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
+        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
+        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+        uint64_t csize                   : 14;
+        uint64_t o_mode                  : 1;
+        uint64_t o_es                    : 2;
+        uint64_t o_ns                    : 1;
+        uint64_t o_ro                    : 1;
+        uint64_t o_add1                  : 1;
+        uint64_t fpa_que                 : 3;
+        uint64_t dwb_ichk                : 9;
+        uint64_t dwb_denb                : 1;
+        uint64_t b0_lend                 : 1;
+        uint64_t dma0_enb                : 1;
+        uint64_t dma1_enb                : 1;
+        uint64_t dma2_enb                : 1;
+        uint64_t dma3_enb                : 1;
+        uint64_t dma4_enb                : 1;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } cn56xxp1;
+} cvmx_npei_dma_control_t;
+
+
+/**
+ * cvmx_npei_dma_pcie_req_num
+ *
+ * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number
+ * 
+ * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_pcie_req_num_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dma_arb                 : 1;       /**< DMA_PKT Read Request Arbitration
+                                                         - 1: DMA0-4 and PKT are round robin. i.e.
+                                                             DMA0-DMA1-DMA2-DMA3-DMA4-PKT...
+                                                         - 0: DMA0-4 are round robin, pkt gets selected
+                                                             half the time. i.e.
+                                                             DMA0-PKT-DMA1-PKT-DMA2-PKT-DMA3-PKT-DMA4-PKT... */
+        uint64_t reserved_53_62          : 10;
+        uint64_t pkt_cnt                 : 5;       /**< PKT outstanding PCIE Read Request Number for each
+                                                         PCIe port
+                                                         When PKT_CNT=x, for each PCIe port, the number
+                                                         of outstanding PCIe memory space reads by the PCIe
+                                                         packet input/output will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+        uint64_t reserved_45_47          : 3;
+        uint64_t dma4_cnt                : 5;       /**< DMA4 outstanding PCIE Read Request Number
+                                                         When DMA4_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 4
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+        uint64_t reserved_37_39          : 3;
+        uint64_t dma3_cnt                : 5;       /**< DMA3 outstanding PCIE Read Request Number
+                                                         When DMA3_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 3
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+        uint64_t reserved_29_31          : 3;
+        uint64_t dma2_cnt                : 5;       /**< DMA2 outstanding PCIE Read Request Number
+                                                         When DMA2_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 2
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+        uint64_t reserved_21_23          : 3;
+        uint64_t dma1_cnt                : 5;       /**< DMA1 outstanding PCIE Read Request Number
+                                                         When DMA1_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 1
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+        uint64_t reserved_13_15          : 3;
+        uint64_t dma0_cnt                : 5;       /**< DMA0 outstanding PCIE Read Request Number
+                                                         When DMA0_CNT=x, the number of outstanding PCIe
+                                                         memory space reads by the PCIe DMA engine 0
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+        uint64_t reserved_5_7            : 3;
+        uint64_t dma_cnt                 : 5;       /**< Total outstanding PCIE Read Request Number for each
+                                                         PCIe port
+                                                         When DMA_CNT=x, for each PCIe port, the total
+                                                         number of outstanding PCIe memory space reads
+                                                         by the PCIe DMA engines and packet input/output
+                                                         will not exceed x.
+                                                         Valid Number is between 1 and 16 */
+#else
+        uint64_t dma_cnt                 : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t dma0_cnt                : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t dma1_cnt                : 5;
+        uint64_t reserved_21_23          : 3;
+        uint64_t dma2_cnt                : 5;
+        uint64_t reserved_29_31          : 3;
+        uint64_t dma3_cnt                : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t dma4_cnt                : 5;
+        uint64_t reserved_45_47          : 3;
+        uint64_t pkt_cnt                 : 5;
+        uint64_t reserved_53_62          : 10;
+        uint64_t dma_arb                 : 1;
+#endif
+    } s;
+    struct cvmx_npei_dma_pcie_req_num_s  cn52xx;
+    struct cvmx_npei_dma_pcie_req_num_s  cn56xx;
+} cvmx_npei_dma_pcie_req_num_t;
+
+
+/**
+ * cvmx_npei_dma_state1
+ *
+ * NPEI_DMA_STATE1 = NPI's DMA State 1
+ * 
+ * Results from DMA state register 1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t d4_dwe                  : 8;       /**< DMA4 PICe Write State */
+        uint64_t d3_dwe                  : 8;       /**< DMA3 PICe Write State */
+        uint64_t d2_dwe                  : 8;       /**< DMA2 PICe Write State */
+        uint64_t d1_dwe                  : 8;       /**< DMA1 PICe Write State */
+        uint64_t d0_dwe                  : 8;       /**< DMA0 PICe Write State */
+#else
+        uint64_t d0_dwe                  : 8;
+        uint64_t d1_dwe                  : 8;
+        uint64_t d2_dwe                  : 8;
+        uint64_t d3_dwe                  : 8;
+        uint64_t d4_dwe                  : 8;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_npei_dma_state1_s        cn52xx;
+} cvmx_npei_dma_state1_t;
+
+
+/**
+ * cvmx_npei_dma_state1_p1
+ *
+ * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State
+ * 
+ * DMA engine Debug information.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state1_p1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t d0_difst                : 7;       /**< DMA engine 0 dif instruction read state */
+        uint64_t d1_difst                : 7;       /**< DMA engine 1 dif instruction read state */
+        uint64_t d2_difst                : 7;       /**< DMA engine 2 dif instruction read state */
+        uint64_t d3_difst                : 7;       /**< DMA engine 3 dif instruction read state */
+        uint64_t d4_difst                : 7;       /**< DMA engine 4 dif instruction read state */
+        uint64_t d0_reqst                : 5;       /**< DMA engine 0 request data state */
+        uint64_t d1_reqst                : 5;       /**< DMA engine 1 request data state */
+        uint64_t d2_reqst                : 5;       /**< DMA engine 2 request data state */
+        uint64_t d3_reqst                : 5;       /**< DMA engine 3 request data state */
+        uint64_t d4_reqst                : 5;       /**< DMA engine 4 request data state */
+#else
+        uint64_t d4_reqst                : 5;
+        uint64_t d3_reqst                : 5;
+        uint64_t d2_reqst                : 5;
+        uint64_t d1_reqst                : 5;
+        uint64_t d0_reqst                : 5;
+        uint64_t d4_difst                : 7;
+        uint64_t d3_difst                : 7;
+        uint64_t d2_difst                : 7;
+        uint64_t d1_difst                : 7;
+        uint64_t d0_difst                : 7;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } s;
+    struct cvmx_npei_dma_state1_p1_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t d0_difst                : 7;       /**< DMA engine 0 dif instruction read state */
+        uint64_t d1_difst                : 7;       /**< DMA engine 1 dif instruction read state */
+        uint64_t d2_difst                : 7;       /**< DMA engine 2 dif instruction read state */
+        uint64_t d3_difst                : 7;       /**< DMA engine 3 dif instruction read state */
+        uint64_t reserved_25_31          : 7;
+        uint64_t d0_reqst                : 5;       /**< DMA engine 0 request data state */
+        uint64_t d1_reqst                : 5;       /**< DMA engine 1 request data state */
+        uint64_t d2_reqst                : 5;       /**< DMA engine 2 request data state */
+        uint64_t d3_reqst                : 5;       /**< DMA engine 3 request data state */
+        uint64_t reserved_0_4            : 5;
+#else
+        uint64_t reserved_0_4            : 5;
+        uint64_t d3_reqst                : 5;
+        uint64_t d2_reqst                : 5;
+        uint64_t d1_reqst                : 5;
+        uint64_t d0_reqst                : 5;
+        uint64_t reserved_25_31          : 7;
+        uint64_t d3_difst                : 7;
+        uint64_t d2_difst                : 7;
+        uint64_t d1_difst                : 7;
+        uint64_t d0_difst                : 7;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_dma_state1_p1_s     cn56xxp1;
+} cvmx_npei_dma_state1_p1_t;
+
+
+/**
+ * cvmx_npei_dma_state2
+ *
+ * NPEI_DMA_STATE2 = NPI's DMA State 2
+ * 
+ * Results from DMA state register 2
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t ndwe                    : 4;       /**< DMA L2C Write State */
+        uint64_t reserved_21_23          : 3;
+        uint64_t ndre                    : 5;       /**< DMA L2C Read State */
+        uint64_t reserved_10_15          : 6;
+        uint64_t prd                     : 10;      /**< DMA PICe Read State */
+#else
+        uint64_t prd                     : 10;
+        uint64_t reserved_10_15          : 6;
+        uint64_t ndre                    : 5;
+        uint64_t reserved_21_23          : 3;
+        uint64_t ndwe                    : 4;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_npei_dma_state2_s        cn52xx;
+} cvmx_npei_dma_state2_t;
+
+
+/**
+ * cvmx_npei_dma_state2_p1
+ *
+ * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State
+ * 
+ * DMA engine Debug information.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state2_p1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_45_63          : 19;
+        uint64_t d0_dffst                : 9;       /**< DMA engine 0 dif instruction fetch state */
+        uint64_t d1_dffst                : 9;       /**< DMA engine 1 dif instruction fetch state */
+        uint64_t d2_dffst                : 9;       /**< DMA engine 2 dif instruction fetch state */
+        uint64_t d3_dffst                : 9;       /**< DMA engine 3 dif instruction fetch state */
+        uint64_t d4_dffst                : 9;       /**< DMA engine 4 dif instruction fetch state */
+#else
+        uint64_t d4_dffst                : 9;
+        uint64_t d3_dffst                : 9;
+        uint64_t d2_dffst                : 9;
+        uint64_t d1_dffst                : 9;
+        uint64_t d0_dffst                : 9;
+        uint64_t reserved_45_63          : 19;
+#endif
+    } s;
+    struct cvmx_npei_dma_state2_p1_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_45_63          : 19;
+        uint64_t d0_dffst                : 9;       /**< DMA engine 0 dif instruction fetch state */
+        uint64_t d1_dffst                : 9;       /**< DMA engine 1 dif instruction fetch state */
+        uint64_t d2_dffst                : 9;       /**< DMA engine 2 dif instruction fetch state */
+        uint64_t d3_dffst                : 9;       /**< DMA engine 3 dif instruction fetch state */
+        uint64_t reserved_0_8            : 9;
+#else
+        uint64_t reserved_0_8            : 9;
+        uint64_t d3_dffst                : 9;
+        uint64_t d2_dffst                : 9;
+        uint64_t d1_dffst                : 9;
+        uint64_t d0_dffst                : 9;
+        uint64_t reserved_45_63          : 19;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_dma_state2_p1_s     cn56xxp1;
+} cvmx_npei_dma_state2_p1_t;
+
+
+/**
+ * cvmx_npei_dma_state3_p1
+ *
+ * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State
+ * 
+ * DMA engine Debug information.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state3_p1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t d0_drest                : 15;      /**< DMA engine 0 dre state */
+        uint64_t d1_drest                : 15;      /**< DMA engine 1 dre state */
+        uint64_t d2_drest                : 15;      /**< DMA engine 2 dre state */
+        uint64_t d3_drest                : 15;      /**< DMA engine 3 dre state */
+#else
+        uint64_t d3_drest                : 15;
+        uint64_t d2_drest                : 15;
+        uint64_t d1_drest                : 15;
+        uint64_t d0_drest                : 15;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } s;
+    struct cvmx_npei_dma_state3_p1_s     cn52xxp1;
+    struct cvmx_npei_dma_state3_p1_s     cn56xxp1;
+} cvmx_npei_dma_state3_p1_t;
+
+
+/**
+ * cvmx_npei_dma_state4_p1
+ *
+ * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State
+ * 
+ * DMA engine Debug information.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state4_p1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_52_63          : 12;
+        uint64_t d0_dwest                : 13;      /**< DMA engine 0 dwe state */
+        uint64_t d1_dwest                : 13;      /**< DMA engine 1 dwe state */
+        uint64_t d2_dwest                : 13;      /**< DMA engine 2 dwe state */
+        uint64_t d3_dwest                : 13;      /**< DMA engine 3 dwe state */
+#else
+        uint64_t d3_dwest                : 13;
+        uint64_t d2_dwest                : 13;
+        uint64_t d1_dwest                : 13;
+        uint64_t d0_dwest                : 13;
+        uint64_t reserved_52_63          : 12;
+#endif
+    } s;
+    struct cvmx_npei_dma_state4_p1_s     cn52xxp1;
+    struct cvmx_npei_dma_state4_p1_s     cn56xxp1;
+} cvmx_npei_dma_state4_p1_t;
+
+
+/**
+ * cvmx_npei_dma_state5_p1
+ *
+ * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State
+ * 
+ * DMA engine Debug information.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_dma_state5_p1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t d4_drest                : 15;      /**< DMA engine 4 dre state */
+        uint64_t d4_dwest                : 13;      /**< DMA engine 4 dwe state */
+#else
+        uint64_t d4_dwest                : 13;
+        uint64_t d4_drest                : 15;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_npei_dma_state5_p1_s     cn56xxp1;
+} cvmx_npei_dma_state5_p1_t;
+
+
+/**
+ * cvmx_npei_int_a_enb
+ *
+ * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register
+ * 
+ * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_a_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pout_err                : 1;       /**< Enables NPEI_INT_A_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pin_bp                  : 1;       /**< Enables NPEI_INT_A_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t p1_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t p0_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pgl_err                 : 1;       /**< Enables NPEI_INT_A_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pdi_err                 : 1;       /**< Enables NPEI_INT_A_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pop_err                 : 1;       /**< Enables NPEI_INT_A_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pins_err                : 1;       /**< Enables NPEI_INT_A_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t dma0_cpl                : 1;
+        uint64_t dma1_cpl                : 1;
+        uint64_t pins_err                : 1;
+        uint64_t pop_err                 : 1;
+        uint64_t pdi_err                 : 1;
+        uint64_t pgl_err                 : 1;
+        uint64_t p0_rdlk                 : 1;
+        uint64_t p1_rdlk                 : 1;
+        uint64_t pin_bp                  : 1;
+        uint64_t pout_err                : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_npei_int_a_enb_s         cn52xx;
+    struct cvmx_npei_int_a_enb_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t dma0_cpl                : 1;
+        uint64_t dma1_cpl                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_int_a_enb_s         cn56xx;
+} cvmx_npei_int_a_enb_t;
+
+
+/**
+ * cvmx_npei_int_a_enb2
+ *
+ * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register
+ * 
+ * Used to enable the various interrupting conditions of NPEI
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_a_enb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pout_err                : 1;       /**< Enables NPEI_INT_A_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pin_bp                  : 1;       /**< Enables NPEI_INT_A_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t p1_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[7] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t p0_rdlk                 : 1;       /**< Enables NPEI_INT_A_SUM[6] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pgl_err                 : 1;       /**< Enables NPEI_INT_A_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pdi_err                 : 1;       /**< Enables NPEI_INT_A_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pop_err                 : 1;       /**< Enables NPEI_INT_A_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pins_err                : 1;       /**< Enables NPEI_INT_A_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t dma0_cpl                : 1;
+        uint64_t dma1_cpl                : 1;
+        uint64_t pins_err                : 1;
+        uint64_t pop_err                 : 1;
+        uint64_t pdi_err                 : 1;
+        uint64_t pgl_err                 : 1;
+        uint64_t p0_rdlk                 : 1;
+        uint64_t p1_rdlk                 : 1;
+        uint64_t pin_bp                  : 1;
+        uint64_t pout_err                : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_npei_int_a_enb2_s        cn52xx;
+    struct cvmx_npei_int_a_enb2_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dma1_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0_cpl                : 1;       /**< Enables NPEI_INT_A_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t dma0_cpl                : 1;
+        uint64_t dma1_cpl                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_int_a_enb2_s        cn56xx;
+} cvmx_npei_int_a_enb2_t;
+
+
+/**
+ * cvmx_npei_int_a_sum
+ *
+ * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register
+ * 
+ * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and
+ * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_a_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pout_err                : 1;       /**< Set when PKO sends packet data with the error bit
+                                                         set. */
+        uint64_t pin_bp                  : 1;       /**< Packet input count has exceeded the WMARK.
+                                                         See NPEI_PKT_IN_BP */
+        uint64_t p1_rdlk                 : 1;       /**< PCIe port 1 received a read lock. */
+        uint64_t p0_rdlk                 : 1;       /**< PCIe port 0 received a read lock. */
+        uint64_t pgl_err                 : 1;       /**< When a read error occurs on a packet gather list
+                                                         read this bit is set. */
+        uint64_t pdi_err                 : 1;       /**< When a read error occurs on a packet data read
+                                                         this bit is set. */
+        uint64_t pop_err                 : 1;       /**< When a read error occurs on a packet scatter
+                                                         pointer pair this bit is set. */
+        uint64_t pins_err                : 1;       /**< When a read error occurs on a packet instruction
+                                                         this bit is set. */
+        uint64_t dma1_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 1 */
+        uint64_t dma0_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 0 */
+#else
+        uint64_t dma0_cpl                : 1;
+        uint64_t dma1_cpl                : 1;
+        uint64_t pins_err                : 1;
+        uint64_t pop_err                 : 1;
+        uint64_t pdi_err                 : 1;
+        uint64_t pgl_err                 : 1;
+        uint64_t p0_rdlk                 : 1;
+        uint64_t p1_rdlk                 : 1;
+        uint64_t pin_bp                  : 1;
+        uint64_t pout_err                : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_npei_int_a_sum_s         cn52xx;
+    struct cvmx_npei_int_a_sum_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t dma1_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 1 */
+        uint64_t dma0_cpl                : 1;       /**< Set each time any PCIe DMA engine recieves a UR/CA
+                                                         response from PCIe Port 0 */
+#else
+        uint64_t dma0_cpl                : 1;
+        uint64_t dma1_cpl                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_int_a_sum_s         cn56xx;
+} cvmx_npei_int_a_sum_t;
+
+
+/**
+ * cvmx_npei_int_enb
+ *
+ * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register
+ * 
+ * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Enables NPEI_INT_SUM[63] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_62_62          : 1;
+        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM[61] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM[29] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM[27] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM[22] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM[20] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t dma4dbo                 : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_62          : 1;
+        uint64_t mio_inta                : 1;
+#endif
+    } s;
+    struct cvmx_npei_int_enb_s           cn52xx;
+    struct cvmx_npei_int_enb_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Enables NPEI_INT_SUM[63] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_62_62          : 1;
+        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM[61] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM[29] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM[27] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM[22] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM[20] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_62          : 1;
+        uint64_t mio_inta                : 1;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_int_enb_s           cn56xx;
+    struct cvmx_npei_int_enb_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Enables NPEI_INT_SUM[63] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_61_62          : 2;
+        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_29_29          : 1;
+        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_27_27          : 1;
+        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_22_22          : 1;
+        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t reserved_20_20          : 1;
+        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM[0] to generate an
+                                                         interrupt to the PCIE core for MSI/inta. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t dma4dbo                 : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t reserved_20_20          : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t reserved_22_22          : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t reserved_27_27          : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t reserved_29_29          : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t reserved_61_62          : 2;
+        uint64_t mio_inta                : 1;
+#endif
+    } cn56xxp1;
+} cvmx_npei_int_enb_t;
+
+
+/**
+ * cvmx_npei_int_enb2
+ *
+ * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register
+ * 
+ * Used to enable the various interrupting conditions of NPI
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_enb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM2[61] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM2[29] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM2[27] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM2[22] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM2[20] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_UM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t dma4dbo                 : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } s;
+    struct cvmx_npei_int_enb2_s          cn52xx;
+    struct cvmx_npei_int_enb2_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t int_a                   : 1;       /**< Enables NPEI_INT_SUM2[61] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM2[60] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM2[59] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM2[58] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM2[57] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM2[56] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM2[55] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM2[54] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM2[53] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM2[52] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM2[51] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM2[50] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM2[49] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM2[48] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM2[47] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM2[46] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM2[45] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM2[44] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM2[43] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM2[42] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM2[41] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM2[40] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM2[39] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM2[38] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM2[37] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM2[36] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM2[35] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM2[34] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM2[33] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM2[32] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM2[31] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM2[30] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs1_dr                 : 1;       /**< Enables NPEI_INT_SUM2[29] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM2[28] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs1_er                 : 1;       /**< Enables NPEI_INT_SUM2[27] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM2[26] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM2[25] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM2[24] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM2[23] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs0_dr                 : 1;       /**< Enables NPEI_INT_SUM2[22] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM2[21] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t crs0_er                 : 1;       /**< Enables NPEI_INT_SUM2[20] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM2[19] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM2[18] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM2[17] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM2[16] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM2[15] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM2[14] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM2[13] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM2[12] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM2[11] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM2[10] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM2[9] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM2[7] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM2[6] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM2[5] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM2[4] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM2[3] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM2[2] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM2[1] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_SUM2[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_int_enb2_s          cn56xx;
+    struct cvmx_npei_int_enb2_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_61_63          : 3;
+        uint64_t c1_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[60] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_ldwn                 : 1;       /**< Enables NPEI_INT_SUM[59] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_exc                  : 1;       /**< Enables NPEI_INT_SUM[58] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_exc                  : 1;       /**< Enables NPEI_INT_SUM[57] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_wf                : 1;       /**< Enables NPEI_INT_SUM[56] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_wf                : 1;       /**< Enables NPEI_INT_SUM[55] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_wf                : 1;       /**< Enables NPEI_INT_SUM[54] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_wf                : 1;       /**< Enables NPEI_INT_SUM[53] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_bx                : 1;       /**< Enables NPEI_INT_SUM[52] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_wi                : 1;       /**< Enables NPEI_INT_SUM[51] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b2                : 1;       /**< Enables NPEI_INT_SUM[50] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b1                : 1;       /**< Enables NPEI_INT_SUM[49] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_un_b0                : 1;       /**< Enables NPEI_INT_SUM[48] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_bx                : 1;       /**< Enables NPEI_INT_SUM[47] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_wi                : 1;       /**< Enables NPEI_INT_SUM[46] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b2                : 1;       /**< Enables NPEI_INT_SUM[45] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b1                : 1;       /**< Enables NPEI_INT_SUM[44] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_up_b0                : 1;       /**< Enables NPEI_INT_SUM[43] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_bx                : 1;       /**< Enables NPEI_INT_SUM[42] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_wi                : 1;       /**< Enables NPEI_INT_SUM[41] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b2                : 1;       /**< Enables NPEI_INT_SUM[40] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b1                : 1;       /**< Enables NPEI_INT_SUM[39] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_un_b0                : 1;       /**< Enables NPEI_INT_SUM[38] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_bx                : 1;       /**< Enables NPEI_INT_SUM[37] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_wi                : 1;       /**< Enables NPEI_INT_SUM[36] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b2                : 1;       /**< Enables NPEI_INT_SUM[35] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b1                : 1;       /**< Enables NPEI_INT_SUM[34] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_up_b0                : 1;       /**< Enables NPEI_INT_SUM[33] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_hpint                : 1;       /**< Enables NPEI_INT_SUM[32] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_pmei                 : 1;       /**< Enables NPEI_INT_SUM[31] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c1_wake                 : 1;       /**< Enables NPEI_INT_SUM[30] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t reserved_29_29          : 1;
+        uint64_t c1_se                   : 1;       /**< Enables NPEI_INT_SUM[28] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t reserved_27_27          : 1;
+        uint64_t c1_aeri                 : 1;       /**< Enables NPEI_INT_SUM[26] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_hpint                : 1;       /**< Enables NPEI_INT_SUM[25] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_pmei                 : 1;       /**< Enables NPEI_INT_SUM[24] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t c0_wake                 : 1;       /**< Enables NPEI_INT_SUM[23] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t reserved_22_22          : 1;
+        uint64_t c0_se                   : 1;       /**< Enables NPEI_INT_SUM[21] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t reserved_20_20          : 1;
+        uint64_t c0_aeri                 : 1;       /**< Enables NPEI_INT_SUM[19] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t ptime                   : 1;       /**< Enables NPEI_INT_SUM[18] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pcnt                    : 1;       /**< Enables NPEI_INT_SUM[17] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t pidbof                  : 1;       /**< Enables NPEI_INT_SUM[16] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t psldbof                 : 1;       /**< Enables NPEI_INT_SUM[15] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dtime1                  : 1;       /**< Enables NPEI_INT_SUM[14] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dtime0                  : 1;       /**< Enables NPEI_INT_SUM[13] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dcnt1                   : 1;       /**< Enables NPEI_INT_SUM[12] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dcnt0                   : 1;       /**< Enables NPEI_INT_SUM[11] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1fi                  : 1;       /**< Enables NPEI_INT_SUM[10] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma0fi                  : 1;       /**< Enables NPEI_INT_SUM[9] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma4dbo                 : 1;       /**< Enables NPEI_INT_SUM[8] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma3dbo                 : 1;       /**< Enables NPEI_INT_SUM[7] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma2dbo                 : 1;       /**< Enables NPEI_INT_SUM[6] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma1dbo                 : 1;       /**< Enables NPEI_INT_SUM[5] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t dma0dbo                 : 1;       /**< Enables NPEI_INT_SUM[4] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t iob2big                 : 1;       /**< Enables NPEI_INT_SUM[3] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t bar0_to                 : 1;       /**< Enables NPEI_INT_SUM[2] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPEI_INT_SUM[1] to generate an
+                                                         interrupt on the RSL. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPEI_INT_UM[0] to generate an
+                                                         interrupt on the RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t dma4dbo                 : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t reserved_20_20          : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t reserved_22_22          : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t reserved_27_27          : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t reserved_29_29          : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t reserved_61_63          : 3;
+#endif
+    } cn56xxp1;
+} cvmx_npei_int_enb2_t;
+
+
+/**
+ * cvmx_npei_int_info
+ *
+ * NPEI_INT_INFO = NPI Interrupt Information
+ * 
+ * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_info_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t pidbof                  : 6;       /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit
+                                                         is set. This field when set will not change again
+                                                         unitl NPEI_INTERRUPT_SUM[PIDBOF] is cleared. */
+        uint64_t psldbof                 : 6;       /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit
+                                                         is set. This field when set will not change again
+                                                         unitl NPEI_INTERRUPT_SUM[PSLDBOF] is cleared. */
+#else
+        uint64_t psldbof                 : 6;
+        uint64_t pidbof                  : 6;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_npei_int_info_s          cn52xx;
+    struct cvmx_npei_int_info_s          cn56xx;
+    struct cvmx_npei_int_info_s          cn56xxp1;
+} cvmx_npei_int_info_t;
+
+
+/**
+ * cvmx_npei_int_sum
+ *
+ * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register
+ * 
+ * Set when an interrupt condition occurs, write '1' to clear.
+ * 
+ * HACK: These used to exist, how are TO handled?
+ *  <3>     PO0_2SML R/W1C    0x0         0         The packet being sent out on Port0 is smaller          $R     NS
+ *                                                            than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.
+ * <7>     I0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
+ *                                                 read instructions.
+ * <15>    P0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
+ *                                                 read packet data.
+ * <23>    G0_RTOUT R/W1C    0x0         0         Port-0 had a read timeout while attempting to          $R     NS
+ *                                                 read a gather list.
+ * <31>    P0_PTOUT R/W1C    0x0         0         Port-0 output had a read timeout on a DATA/INFO         $R     NS
+ *                                                 pair.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Interrupt from MIO. */
+        uint64_t reserved_62_62          : 1;
+        uint64_t int_a                   : 1;       /**< Set when a bit in the NPEI_INT_A_SUM register and
+                                                         the cooresponding bit in the NPEI_INT_A_ENB
+                                                         register is set. */
+        uint64_t c1_ldwn                 : 1;       /**< Reset request due to link1 down status. */
+        uint64_t c0_ldwn                 : 1;       /**< Reset request due to link0 down status. */
+        uint64_t c1_exc                  : 1;       /**< Set when the PESC1_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
+                                                         is set. */
+        uint64_t c0_exc                  : 1;       /**< Set when the PESC0_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
+                                                         is set. */
+        uint64_t c1_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core1. */
+        uint64_t c0_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core0. */
+        uint64_t c1_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core1. */
+        uint64_t c0_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core0. */
+        uint64_t c1_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 1. */
+        uint64_t c1_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 1. */
+        uint64_t c1_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 1. */
+        uint64_t c1_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 1. */
+        uint64_t c1_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 1. */
+        uint64_t c1_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 1. */
+        uint64_t c1_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 1. */
+        uint64_t c1_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 1. */
+        uint64_t c1_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 1. */
+        uint64_t c1_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 1. */
+        uint64_t c0_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 0. */
+        uint64_t c0_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 0. */
+        uint64_t c0_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 0. */
+        uint64_t c0_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 0. */
+        uint64_t c0_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 0. */
+        uint64_t c0_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 0. */
+        uint64_t c0_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 0. */
+        uint64_t c0_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 0. */
+        uint64_t c0_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 0. */
+        uint64_t c0_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 0. */
+        uint64_t c1_hpint                : 1;       /**< Hot-Plug Interrupt.
+                                                         Pcie Core 1 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+        uint64_t c1_pmei                 : 1;       /**< PME Interrupt.
+                                                         Pcie Core 1. (cfg_pme_int) */
+        uint64_t c1_wake                 : 1;       /**< Wake up from Power Management Unit.
+                                                         Pcie Core 1. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+        uint64_t crs1_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
+        uint64_t c1_se                   : 1;       /**< System Error, RC Mode Only.
+                                                         Pcie Core 1. (cfg_sys_err_rc) */
+        uint64_t crs1_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
+        uint64_t c1_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 1. */
+        uint64_t c0_hpint                : 1;       /**< Hot-Plug Interrupt.
+                                                         Pcie Core 0 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+        uint64_t c0_pmei                 : 1;       /**< PME Interrupt.
+                                                         Pcie Core 0. (cfg_pme_int) */
+        uint64_t c0_wake                 : 1;       /**< Wake up from Power Management Unit.
+                                                         Pcie Core 0. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+        uint64_t crs0_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
+        uint64_t c0_se                   : 1;       /**< System Error, RC Mode Only.
+                                                         Pcie Core 0. (cfg_sys_err_rc) */
+        uint64_t crs0_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
+        uint64_t c0_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
+        uint64_t ptime                   : 1;       /**< Packet Timer has an interrupt. Which rings can
+                                                         be found in NPEI_PKT_TIME_INT. */
+        uint64_t pcnt                    : 1;       /**< Packet Counter has an interrupt. Which rings can
+                                                         be found in NPEI_PKT_CNT_INT. */
+        uint64_t pidbof                  : 1;       /**< Packet Instruction Doorbell count overflowed. Which
+                                                         doorbell can be found in NPEI_INT_INFO[PIDBOF] */
+        uint64_t psldbof                 : 1;       /**< Packet Scatterlist Doorbell count overflowed. Which
+                                                         doorbell can be found in NPEI_INT_INFO[PSLDBOF] */
+        uint64_t dtime1                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
+                                                         DMA_CNT1 timer increments every core clock. When
+                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT1 timer. */
+        uint64_t dtime0                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
+                                                         DMA_CNT0 timer increments every core clock. When
+                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT0 timer. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
+                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
+                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
+        uint64_t dma1fi                  : 1;       /**< DMA0 set Forced Interrupt. */
+        uint64_t dma0fi                  : 1;       /**< DMA0 set Forced Interrupt. */
+        uint64_t dma4dbo                 : 1;       /**< DMA4 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma3dbo                 : 1;       /**< DMA3 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma2dbo                 : 1;       /**< DMA2 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma1dbo                 : 1;       /**< DMA1 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma0dbo                 : 1;       /**< DMA0 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t iob2big                 : 1;       /**< A requested IOBDMA is to large. */
+        uint64_t bar0_to                 : 1;       /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+        uint64_t rml_wto                 : 1;       /**< RML write did not get commit in 0xffff core clocks. */
+        uint64_t rml_rto                 : 1;       /**< RML read did not return data in 0xffff core clocks. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t dma4dbo                 : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t psldbof                 : 1;
+        uint64_t pidbof                  : 1;
+        uint64_t pcnt                    : 1;
+        uint64_t ptime                   : 1;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_62          : 1;
+        uint64_t mio_inta                : 1;
+#endif
+    } s;
+    struct cvmx_npei_int_sum_s           cn52xx;
+    struct cvmx_npei_int_sum_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Interrupt from MIO. */
+        uint64_t reserved_62_62          : 1;
+        uint64_t int_a                   : 1;       /**< Set when a bit in the NPEI_INT_A_SUM register and
+                                                         the cooresponding bit in the NPEI_INT_A_ENB
+                                                         register is set. */
+        uint64_t c1_ldwn                 : 1;       /**< Reset request due to link1 down status. */
+        uint64_t c0_ldwn                 : 1;       /**< Reset request due to link0 down status. */
+        uint64_t c1_exc                  : 1;       /**< Set when the PESC1_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
+                                                         is set. */
+        uint64_t c0_exc                  : 1;       /**< Set when the PESC0_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
+                                                         is set. */
+        uint64_t c1_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core1. */
+        uint64_t c0_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core0. */
+        uint64_t c1_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core1. */
+        uint64_t c0_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core0. */
+        uint64_t c1_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 1. */
+        uint64_t c1_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 1. */
+        uint64_t c1_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 1. */
+        uint64_t c1_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 1. */
+        uint64_t c1_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 1. */
+        uint64_t c1_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 1. */
+        uint64_t c1_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 1. */
+        uint64_t c1_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 1. */
+        uint64_t c1_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 1. */
+        uint64_t c1_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 1. */
+        uint64_t c0_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 0. */
+        uint64_t c0_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 0. */
+        uint64_t c0_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 0. */
+        uint64_t c0_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 0. */
+        uint64_t c0_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 0. */
+        uint64_t c0_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 0. */
+        uint64_t c0_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 0. */
+        uint64_t c0_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 0. */
+        uint64_t c0_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 0. */
+        uint64_t c0_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 0. */
+        uint64_t c1_hpint                : 1;       /**< Hot-Plug Interrupt.
+                                                         Pcie Core 1 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+        uint64_t c1_pmei                 : 1;       /**< PME Interrupt.
+                                                         Pcie Core 1. (cfg_pme_int) */
+        uint64_t c1_wake                 : 1;       /**< Wake up from Power Management Unit.
+                                                         Pcie Core 1. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+        uint64_t crs1_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
+        uint64_t c1_se                   : 1;       /**< System Error, RC Mode Only.
+                                                         Pcie Core 1. (cfg_sys_err_rc) */
+        uint64_t crs1_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
+        uint64_t c1_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 1. */
+        uint64_t c0_hpint                : 1;       /**< Hot-Plug Interrupt.
+                                                         Pcie Core 0 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+        uint64_t c0_pmei                 : 1;       /**< PME Interrupt.
+                                                         Pcie Core 0. (cfg_pme_int) */
+        uint64_t c0_wake                 : 1;       /**< Wake up from Power Management Unit.
+                                                         Pcie Core 0. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+        uint64_t crs0_dr                 : 1;       /**< Had a CRS when Retries were disabled. */
+        uint64_t c0_se                   : 1;       /**< System Error, RC Mode Only.
+                                                         Pcie Core 0. (cfg_sys_err_rc) */
+        uint64_t crs0_er                 : 1;       /**< Had a CRS Timeout when Retries were enabled. */
+        uint64_t c0_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
+        uint64_t reserved_15_18          : 4;
+        uint64_t dtime1                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
+                                                         DMA_CNT1 timer increments every core clock. When
+                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT1 timer. */
+        uint64_t dtime0                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
+                                                         DMA_CNT0 timer increments every core clock. When
+                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT0 timer. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
+                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
+                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
+        uint64_t dma1fi                  : 1;       /**< DMA0 set Forced Interrupt. */
+        uint64_t dma0fi                  : 1;       /**< DMA0 set Forced Interrupt. */
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma3dbo                 : 1;       /**< DMA3 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma2dbo                 : 1;       /**< DMA2 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma1dbo                 : 1;       /**< DMA1 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma0dbo                 : 1;       /**< DMA0 doorbell count overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t iob2big                 : 1;       /**< A requested IOBDMA is to large. */
+        uint64_t bar0_to                 : 1;       /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+        uint64_t rml_wto                 : 1;       /**< RML write did not get commit in 0xffff core clocks. */
+        uint64_t rml_rto                 : 1;       /**< RML read did not return data in 0xffff core clocks. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t reserved_15_18          : 4;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_62          : 1;
+        uint64_t mio_inta                : 1;
+#endif
+    } cn52xxp1;
+    struct cvmx_npei_int_sum_s           cn56xx;
+    struct cvmx_npei_int_sum_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Interrupt from MIO. */
+        uint64_t reserved_61_62          : 2;
+        uint64_t c1_ldwn                 : 1;       /**< Reset request due to link1 down status. */
+        uint64_t c0_ldwn                 : 1;       /**< Reset request due to link0 down status. */
+        uint64_t c1_exc                  : 1;       /**< Set when the PESC1_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC1_DBG_INFO_EN bit
+                                                         is set. */
+        uint64_t c0_exc                  : 1;       /**< Set when the PESC0_DBG_INFO register has a bit
+                                                         set and its cooresponding PESC0_DBG_INFO_EN bit
+                                                         is set. */
+        uint64_t c1_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core1. */
+        uint64_t c0_up_wf                : 1;       /**< Received Unsupported P-TLP for filtered window
+                                                         register. Core0. */
+        uint64_t c1_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core1. */
+        uint64_t c0_un_wf                : 1;       /**< Received Unsupported N-TLP for filtered window
+                                                         register. Core0. */
+        uint64_t c1_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 1. */
+        uint64_t c1_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 1. */
+        uint64_t c1_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 1. */
+        uint64_t c1_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 1. */
+        uint64_t c1_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 1. */
+        uint64_t c1_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 1. */
+        uint64_t c1_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 1. */
+        uint64_t c1_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 1. */
+        uint64_t c1_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 1. */
+        uint64_t c1_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 1. */
+        uint64_t c0_un_bx                : 1;       /**< Received Unsupported N-TLP for unknown Bar.
+                                                         Core 0. */
+        uint64_t c0_un_wi                : 1;       /**< Received Unsupported N-TLP for Window Register.
+                                                         Core 0. */
+        uint64_t c0_un_b2                : 1;       /**< Received Unsupported N-TLP for Bar2.
+                                                         Core 0. */
+        uint64_t c0_un_b1                : 1;       /**< Received Unsupported N-TLP for Bar1.
+                                                         Core 0. */
+        uint64_t c0_un_b0                : 1;       /**< Received Unsupported N-TLP for Bar0.
+                                                         Core 0. */
+        uint64_t c0_up_bx                : 1;       /**< Received Unsupported P-TLP for unknown Bar.
+                                                         Core 0. */
+        uint64_t c0_up_wi                : 1;       /**< Received Unsupported P-TLP for Window Register.
+                                                         Core 0. */
+        uint64_t c0_up_b2                : 1;       /**< Received Unsupported P-TLP for Bar2.
+                                                         Core 0. */
+        uint64_t c0_up_b1                : 1;       /**< Received Unsupported P-TLP for Bar1.
+                                                         Core 0. */
+        uint64_t c0_up_b0                : 1;       /**< Received Unsupported P-TLP for Bar0.
+                                                         Core 0. */
+        uint64_t c1_hpint                : 1;       /**< Hot-Plug Interrupt.
+                                                         Pcie Core 1 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC1_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+        uint64_t c1_pmei                 : 1;       /**< PME Interrupt.
+                                                         Pcie Core 1. (cfg_pme_int) */
+        uint64_t c1_wake                 : 1;       /**< Wake up from Power Management Unit.
+                                                         Pcie Core 1. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+        uint64_t reserved_29_29          : 1;
+        uint64_t c1_se                   : 1;       /**< System Error, RC Mode Only.
+                                                         Pcie Core 1. (cfg_sys_err_rc) */
+        uint64_t reserved_27_27          : 1;
+        uint64_t c1_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 1. */
+        uint64_t c0_hpint                : 1;       /**< Hot-Plug Interrupt.
+                                                         Pcie Core 0 (hp_int).
+                                                         This interrupt will only be generated when
+                                                         PCIERC0_CFG034[DLLS_C] is generated. Hot plug is
+                                                         not supported. */
+        uint64_t c0_pmei                 : 1;       /**< PME Interrupt.
+                                                         Pcie Core 0. (cfg_pme_int) */
+        uint64_t c0_wake                 : 1;       /**< Wake up from Power Management Unit.
+                                                         Pcie Core 0. (wake_n)
+                                                         Octeon will never generate this interrupt. */
+        uint64_t reserved_22_22          : 1;
+        uint64_t c0_se                   : 1;       /**< System Error, RC Mode Only.
+                                                         Pcie Core 0. (cfg_sys_err_rc) */
+        uint64_t reserved_20_20          : 1;
+        uint64_t c0_aeri                 : 1;       /**< Advanced Error Reporting Interrupt, RC Mode Only.
+                                                         Pcie Core 0 (cfg_aer_rc_err_int). */
+        uint64_t reserved_15_18          : 4;
+        uint64_t dtime1                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the
+                                                         DMA_CNT1 timer increments every core clock. When
+                                                         DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT1 timer. */
+        uint64_t dtime0                  : 1;       /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the
+                                                         DMA_CNT0 timer increments every core clock. When
+                                                         DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],
+                                                         this bit is set. Writing a '1' to this bit also
+                                                         clears the DMA_CNT0 timer. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is
+                                                         greater than NPEI_DMA1_INT_LEVEL[CNT]. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is
+                                                         greater than NPEI_DMA0_INT_LEVEL[CNT]. */
+        uint64_t dma1fi                  : 1;       /**< DMA0 set Forced Interrupt. */
+        uint64_t dma0fi                  : 1;       /**< DMA0 set Forced Interrupt. */
+        uint64_t dma4dbo                 : 1;       /**< DMA4 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma3dbo                 : 1;       /**< DMA3 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma2dbo                 : 1;       /**< DMA2 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma1dbo                 : 1;       /**< DMA1 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t dma0dbo                 : 1;       /**< DMA0 doorbell overflow.
+                                                         Bit[32] of the doorbell count was set. */
+        uint64_t iob2big                 : 1;       /**< A requested IOBDMA is to large. */
+        uint64_t bar0_to                 : 1;       /**< BAR0 R/W to a NCB device did not receive
+                                                         read-data/commit in 0xffff core clocks. */
+        uint64_t rml_wto                 : 1;       /**< RML write did not get commit in 0xffff core clocks. */
+        uint64_t rml_rto                 : 1;       /**< RML read did not return data in 0xffff core clocks. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t dma4dbo                 : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t reserved_15_18          : 4;
+        uint64_t c0_aeri                 : 1;
+        uint64_t reserved_20_20          : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t reserved_22_22          : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t reserved_27_27          : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t reserved_29_29          : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t reserved_61_62          : 2;
+        uint64_t mio_inta                : 1;
+#endif
+    } cn56xxp1;
+} cvmx_npei_int_sum_t;
+
+
+/**
+ * cvmx_npei_int_sum2
+ *
+ * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register
+ * 
+ * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_int_sum2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mio_inta                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t reserved_62_62          : 1;
+        uint64_t int_a                   : 1;       /**< Set when a bit in the NPEI_INT_A_SUM register and
+                                                         the cooresponding bit in the NPEI_INT_A_ENB2
+                                                         register is set. */
+        uint64_t c1_ldwn                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_ldwn                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_exc                  : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_exc                  : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_up_wf                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_up_wf                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_un_wf                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_un_wf                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_un_bx                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_un_wi                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_un_b2                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_un_b1                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_un_b0                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_up_bx                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_up_wi                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_up_b2                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_up_b1                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_up_b0                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_un_bx                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_un_wi                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_un_b2                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_un_b1                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_un_b0                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_up_bx                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_up_wi                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_up_b2                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_up_b1                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_up_b0                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_hpint                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_pmei                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_wake                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t crs1_dr                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_se                   : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t crs1_er                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c1_aeri                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_hpint                : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_pmei                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_wake                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t crs0_dr                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_se                   : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t crs0_er                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t c0_aeri                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t reserved_15_18          : 4;
+        uint64_t dtime1                  : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dtime0                  : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dcnt1                   : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dcnt0                   : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dma1fi                  : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dma0fi                  : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma3dbo                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dma2dbo                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dma1dbo                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t dma0dbo                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t iob2big                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t bar0_to                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t rml_wto                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+        uint64_t rml_rto                 : 1;       /**< Equal to the cooresponding bit if the
+                                                         NPEI_INT_SUM register. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t bar0_to                 : 1;
+        uint64_t iob2big                 : 1;
+        uint64_t dma0dbo                 : 1;
+        uint64_t dma1dbo                 : 1;
+        uint64_t dma2dbo                 : 1;
+        uint64_t dma3dbo                 : 1;
+        uint64_t reserved_8_8            : 1;
+        uint64_t dma0fi                  : 1;
+        uint64_t dma1fi                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t reserved_15_18          : 4;
+        uint64_t c0_aeri                 : 1;
+        uint64_t crs0_er                 : 1;
+        uint64_t c0_se                   : 1;
+        uint64_t crs0_dr                 : 1;
+        uint64_t c0_wake                 : 1;
+        uint64_t c0_pmei                 : 1;
+        uint64_t c0_hpint                : 1;
+        uint64_t c1_aeri                 : 1;
+        uint64_t crs1_er                 : 1;
+        uint64_t c1_se                   : 1;
+        uint64_t crs1_dr                 : 1;
+        uint64_t c1_wake                 : 1;
+        uint64_t c1_pmei                 : 1;
+        uint64_t c1_hpint                : 1;
+        uint64_t c0_up_b0                : 1;
+        uint64_t c0_up_b1                : 1;
+        uint64_t c0_up_b2                : 1;
+        uint64_t c0_up_wi                : 1;
+        uint64_t c0_up_bx                : 1;
+        uint64_t c0_un_b0                : 1;
+        uint64_t c0_un_b1                : 1;
+        uint64_t c0_un_b2                : 1;
+        uint64_t c0_un_wi                : 1;
+        uint64_t c0_un_bx                : 1;
+        uint64_t c1_up_b0                : 1;
+        uint64_t c1_up_b1                : 1;
+        uint64_t c1_up_b2                : 1;
+        uint64_t c1_up_wi                : 1;
+        uint64_t c1_up_bx                : 1;
+        uint64_t c1_un_b0                : 1;
+        uint64_t c1_un_b1                : 1;
+        uint64_t c1_un_b2                : 1;
+        uint64_t c1_un_wi                : 1;
+        uint64_t c1_un_bx                : 1;
+        uint64_t c0_un_wf                : 1;
+        uint64_t c1_un_wf                : 1;
+        uint64_t c0_up_wf                : 1;
+        uint64_t c1_up_wf                : 1;
+        uint64_t c0_exc                  : 1;
+        uint64_t c1_exc                  : 1;
+        uint64_t c0_ldwn                 : 1;
+        uint64_t c1_ldwn                 : 1;
+        uint64_t int_a                   : 1;
+        uint64_t reserved_62_62          : 1;
+        uint64_t mio_inta                : 1;
+#endif
+    } s;
+    struct cvmx_npei_int_sum2_s          cn52xx;
+    struct cvmx_npei_int_sum2_s          cn52xxp1;
+    struct cvmx_npei_int_sum2_s          cn56xx;
+} cvmx_npei_int_sum2_t;
+
+
+/**
+ * cvmx_npei_last_win_rdata0
+ *
+ * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0
+ * 
+ * The data from the last initiated window read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_last_win_rdata0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Last window read data. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_last_win_rdata0_s   cn52xx;
+    struct cvmx_npei_last_win_rdata0_s   cn52xxp1;
+    struct cvmx_npei_last_win_rdata0_s   cn56xx;
+    struct cvmx_npei_last_win_rdata0_s   cn56xxp1;
+} cvmx_npei_last_win_rdata0_t;
+
+
+/**
+ * cvmx_npei_last_win_rdata1
+ *
+ * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1
+ * 
+ * The data from the last initiated window read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_last_win_rdata1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Last window read data. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_last_win_rdata1_s   cn52xx;
+    struct cvmx_npei_last_win_rdata1_s   cn52xxp1;
+    struct cvmx_npei_last_win_rdata1_s   cn56xx;
+    struct cvmx_npei_last_win_rdata1_s   cn56xxp1;
+} cvmx_npei_last_win_rdata1_t;
+
+
+/**
+ * cvmx_npei_mem_access_ctl
+ *
+ * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control
+ * 
+ * Contains control for access to the PCIe address space.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_mem_access_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t max_word                : 4;       /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCIe. Legal
+                                                         values are 1 to 16, where a '0' is treated as 16. */
+        uint64_t timer                   : 10;      /**< When the NPEI starts a PP to PCIe write it waits
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+        uint64_t timer                   : 10;
+        uint64_t max_word                : 4;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_npei_mem_access_ctl_s    cn52xx;
+    struct cvmx_npei_mem_access_ctl_s    cn52xxp1;
+    struct cvmx_npei_mem_access_ctl_s    cn56xx;
+    struct cvmx_npei_mem_access_ctl_s    cn56xxp1;
+} cvmx_npei_mem_access_ctl_t;
+
+
+/**
+ * cvmx_npei_mem_access_subid#
+ *
+ * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register
+ * 
+ * Contains address index and control bits for access to memory from Core PPs.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_mem_access_subidx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_42_63          : 22;
+        uint64_t zero                    : 1;       /**< Causes all byte reads to be zero length reads.
+                                                         Returns to the EXEC a zero for all read data. */
+        uint64_t port                    : 2;       /**< Port the request is sent to. */
+        uint64_t nmerge                  : 1;       /**< No merging is allowed in this window. */
+        uint64_t esr                     : 2;       /**< Endian-swap for Reads. */
+        uint64_t esw                     : 2;       /**< Endian-swap for Writes. */
+        uint64_t nsr                     : 1;       /**< No Snoop for Reads. */
+        uint64_t nsw                     : 1;       /**< No Snoop for Writes. */
+        uint64_t ror                     : 1;       /**< Relaxed Ordering for Reads. */
+        uint64_t row                     : 1;       /**< Relaxed Ordering for Writes. */
+        uint64_t ba                      : 30;      /**< PCIe Adddress Bits <63:34>. */
+#else
+        uint64_t ba                      : 30;
+        uint64_t row                     : 1;
+        uint64_t ror                     : 1;
+        uint64_t nsw                     : 1;
+        uint64_t nsr                     : 1;
+        uint64_t esw                     : 2;
+        uint64_t esr                     : 2;
+        uint64_t nmerge                  : 1;
+        uint64_t port                    : 2;
+        uint64_t zero                    : 1;
+        uint64_t reserved_42_63          : 22;
+#endif
+    } s;
+    struct cvmx_npei_mem_access_subidx_s cn52xx;
+    struct cvmx_npei_mem_access_subidx_s cn52xxp1;
+    struct cvmx_npei_mem_access_subidx_s cn56xx;
+    struct cvmx_npei_mem_access_subidx_s cn56xxp1;
+} cvmx_npei_mem_access_subidx_t;
+
+
+/**
+ * cvmx_npei_msi_enb0
+ *
+ * NPEI_MSI_ENB0 = NPEI MSI Enable0
+ * 
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_enb0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV0. */
+#else
+        uint64_t enb                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_enb0_s          cn52xx;
+    struct cvmx_npei_msi_enb0_s          cn52xxp1;
+    struct cvmx_npei_msi_enb0_s          cn56xx;
+    struct cvmx_npei_msi_enb0_s          cn56xxp1;
+} cvmx_npei_msi_enb0_t;
+
+
+/**
+ * cvmx_npei_msi_enb1
+ *
+ * NPEI_MSI_ENB1 = NPEI MSI Enable1
+ * 
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_enb1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV1. */
+#else
+        uint64_t enb                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_enb1_s          cn52xx;
+    struct cvmx_npei_msi_enb1_s          cn52xxp1;
+    struct cvmx_npei_msi_enb1_s          cn56xx;
+    struct cvmx_npei_msi_enb1_s          cn56xxp1;
+} cvmx_npei_msi_enb1_t;
+
+
+/**
+ * cvmx_npei_msi_enb2
+ *
+ * NPEI_MSI_ENB2 = NPEI MSI Enable2
+ * 
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_enb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV2. */
+#else
+        uint64_t enb                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_enb2_s          cn52xx;
+    struct cvmx_npei_msi_enb2_s          cn52xxp1;
+    struct cvmx_npei_msi_enb2_s          cn56xx;
+    struct cvmx_npei_msi_enb2_s          cn56xxp1;
+} cvmx_npei_msi_enb2_t;
+
+
+/**
+ * cvmx_npei_msi_enb3
+ *
+ * NPEI_MSI_ENB3 = NPEI MSI Enable3
+ * 
+ * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_enb3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t enb                     : 64;      /**< Enables bit [63:0] of NPEI_MSI_RCV3. */
+#else
+        uint64_t enb                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_enb3_s          cn52xx;
+    struct cvmx_npei_msi_enb3_s          cn52xxp1;
+    struct cvmx_npei_msi_enb3_s          cn56xx;
+    struct cvmx_npei_msi_enb3_s          cn56xxp1;
+} cvmx_npei_msi_enb3_t;
+
+
+/**
+ * cvmx_npei_msi_rcv0
+ *
+ * NPEI_MSI_RCV0 = NPEI MSI Receive0
+ * 
+ * Contains bits [63:0] of the 256 bits oof MSI interrupts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_rcv0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t intr                    : 64;      /**< Bits 63-0 of the 256 bits of MSI interrupt. */
+#else
+        uint64_t intr                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_rcv0_s          cn52xx;
+    struct cvmx_npei_msi_rcv0_s          cn52xxp1;
+    struct cvmx_npei_msi_rcv0_s          cn56xx;
+    struct cvmx_npei_msi_rcv0_s          cn56xxp1;
+} cvmx_npei_msi_rcv0_t;
+
+
+/**
+ * cvmx_npei_msi_rcv1
+ *
+ * NPEI_MSI_RCV1 = NPEI MSI Receive1
+ * 
+ * Contains bits [127:64] of the 256 bits oof MSI interrupts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_rcv1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t intr                    : 64;      /**< Bits 127-64 of the 256 bits of MSI interrupt. */
+#else
+        uint64_t intr                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_rcv1_s          cn52xx;
+    struct cvmx_npei_msi_rcv1_s          cn52xxp1;
+    struct cvmx_npei_msi_rcv1_s          cn56xx;
+    struct cvmx_npei_msi_rcv1_s          cn56xxp1;
+} cvmx_npei_msi_rcv1_t;
+
+
+/**
+ * cvmx_npei_msi_rcv2
+ *
+ * NPEI_MSI_RCV2 = NPEI MSI Receive2
+ * 
+ * Contains bits [191:128] of the 256 bits oof MSI interrupts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_rcv2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t intr                    : 64;      /**< Bits 191-128 of the 256 bits of MSI interrupt. */
+#else
+        uint64_t intr                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_rcv2_s          cn52xx;
+    struct cvmx_npei_msi_rcv2_s          cn52xxp1;
+    struct cvmx_npei_msi_rcv2_s          cn56xx;
+    struct cvmx_npei_msi_rcv2_s          cn56xxp1;
+} cvmx_npei_msi_rcv2_t;
+
+
+/**
+ * cvmx_npei_msi_rcv3
+ *
+ * NPEI_MSI_RCV3 = NPEI MSI Receive3
+ * 
+ * Contains bits [255:192] of the 256 bits oof MSI interrupts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_rcv3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t intr                    : 64;      /**< Bits 255-192 of the 256 bits of MSI interrupt. */
+#else
+        uint64_t intr                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_rcv3_s          cn52xx;
+    struct cvmx_npei_msi_rcv3_s          cn52xxp1;
+    struct cvmx_npei_msi_rcv3_s          cn56xx;
+    struct cvmx_npei_msi_rcv3_s          cn56xxp1;
+} cvmx_npei_msi_rcv3_t;
+
+
+/**
+ * cvmx_npei_msi_rd_map
+ *
+ * NPEI_MSI_RD_MAP = NPEI MSI Read MAP
+ * 
+ * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_rd_map_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t rd_int                  : 8;       /**< The value of the map at the location PREVIOUSLY
+                                                         written to the MSI_INT field of this register. */
+        uint64_t msi_int                 : 8;       /**< Selects the value that would be received when the
+                                                         NPEI_PCIE_MSI_RCV register is written. */
+#else
+        uint64_t msi_int                 : 8;
+        uint64_t rd_int                  : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npei_msi_rd_map_s        cn52xx;
+    struct cvmx_npei_msi_rd_map_s        cn52xxp1;
+    struct cvmx_npei_msi_rd_map_s        cn56xx;
+    struct cvmx_npei_msi_rd_map_s        cn56xxp1;
+} cvmx_npei_msi_rd_map_t;
+
+
+/**
+ * cvmx_npei_msi_w1c_enb0
+ *
+ * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0
+ * 
+ * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1c_enb0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB0.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t clr                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1c_enb0_s      cn52xx;
+    struct cvmx_npei_msi_w1c_enb0_s      cn56xx;
+} cvmx_npei_msi_w1c_enb0_t;
+
+
+/**
+ * cvmx_npei_msi_w1c_enb1
+ *
+ * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1
+ * 
+ * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1c_enb1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB1.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t clr                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1c_enb1_s      cn52xx;
+    struct cvmx_npei_msi_w1c_enb1_s      cn56xx;
+} cvmx_npei_msi_w1c_enb1_t;
+
+
+/**
+ * cvmx_npei_msi_w1c_enb2
+ *
+ * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2
+ * 
+ * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1c_enb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB2.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t clr                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1c_enb2_s      cn52xx;
+    struct cvmx_npei_msi_w1c_enb2_s      cn56xx;
+} cvmx_npei_msi_w1c_enb2_t;
+
+
+/**
+ * cvmx_npei_msi_w1c_enb3
+ *
+ * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3
+ * 
+ * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1c_enb3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t clr                     : 64;      /**< A write of '1' to a vector will clear the
+                                                         cooresponding bit in NPEI_MSI_ENB3.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t clr                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1c_enb3_s      cn52xx;
+    struct cvmx_npei_msi_w1c_enb3_s      cn56xx;
+} cvmx_npei_msi_w1c_enb3_t;
+
+
+/**
+ * cvmx_npei_msi_w1s_enb0
+ *
+ * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0
+ * 
+ * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1s_enb0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB0.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t set                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1s_enb0_s      cn52xx;
+    struct cvmx_npei_msi_w1s_enb0_s      cn56xx;
+} cvmx_npei_msi_w1s_enb0_t;
+
+
+/**
+ * cvmx_npei_msi_w1s_enb1
+ *
+ * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1
+ * 
+ * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1s_enb1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB1.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t set                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1s_enb1_s      cn52xx;
+    struct cvmx_npei_msi_w1s_enb1_s      cn56xx;
+} cvmx_npei_msi_w1s_enb1_t;
+
+
+/**
+ * cvmx_npei_msi_w1s_enb2
+ *
+ * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2
+ * 
+ * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1s_enb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB2.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t set                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1s_enb2_s      cn52xx;
+    struct cvmx_npei_msi_w1s_enb2_s      cn56xx;
+} cvmx_npei_msi_w1s_enb2_t;
+
+
+/**
+ * cvmx_npei_msi_w1s_enb3
+ *
+ * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3
+ * 
+ * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_w1s_enb3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t set                     : 64;      /**< A write of '1' to a vector will set the
+                                                         cooresponding bit in NPEI_MSI_ENB3.
+                                                         A read to this address will return 0. */
+#else
+        uint64_t set                     : 64;
+#endif
+    } s;
+    struct cvmx_npei_msi_w1s_enb3_s      cn52xx;
+    struct cvmx_npei_msi_w1s_enb3_s      cn56xx;
+} cvmx_npei_msi_w1s_enb3_t;
+
+
+/**
+ * cvmx_npei_msi_wr_map
+ *
+ * NPEI_MSI_WR_MAP = NPEI MSI Write MAP
+ * 
+ * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_msi_wr_map_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ciu_int                 : 8;       /**< Selects which bit in the NPEI_MSI_RCV# (0-255)
+                                                         will be set when the value specified in the
+                                                         MSI_INT of this register is recevied during a
+                                                         write to the NPEI_PCIE_MSI_RCV register. */
+        uint64_t msi_int                 : 8;       /**< Selects the value that would be received when the
+                                                         NPEI_PCIE_MSI_RCV register is written. */
+#else
+        uint64_t msi_int                 : 8;
+        uint64_t ciu_int                 : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npei_msi_wr_map_s        cn52xx;
+    struct cvmx_npei_msi_wr_map_s        cn52xxp1;
+    struct cvmx_npei_msi_wr_map_s        cn56xx;
+    struct cvmx_npei_msi_wr_map_s        cn56xxp1;
+} cvmx_npei_msi_wr_map_t;
+
+
+/**
+ * cvmx_npei_pcie_credit_cnt
+ *
+ * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count
+ * 
+ * Contains the number of credits for the pcie port FIFOs used by the NPEI. This value needs to be set BEFORE PCIe traffic
+ * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two
+ * PCIE ports to be reset to the value in this register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pcie_credit_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t p1_ccnt                 : 8;       /**< Port1 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+        uint64_t p1_ncnt                 : 8;       /**< Port1 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+        uint64_t p1_pcnt                 : 8;       /**< Port1 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+        uint64_t p0_ccnt                 : 8;       /**< Port0 C-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+        uint64_t p0_ncnt                 : 8;       /**< Port0 N-TLP FIFO Credits.
+                                                         Legal values are 0x5 to 0x10. */
+        uint64_t p0_pcnt                 : 8;       /**< Port0 P-TLP FIFO Credits.
+                                                         Legal values are 0x25 to 0x80. */
+#else
+        uint64_t p0_pcnt                 : 8;
+        uint64_t p0_ncnt                 : 8;
+        uint64_t p0_ccnt                 : 8;
+        uint64_t p1_pcnt                 : 8;
+        uint64_t p1_ncnt                 : 8;
+        uint64_t p1_ccnt                 : 8;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_npei_pcie_credit_cnt_s   cn52xx;
+    struct cvmx_npei_pcie_credit_cnt_s   cn56xx;
+} cvmx_npei_pcie_credit_cnt_t;
+
+
+/**
+ * cvmx_npei_pcie_msi_rcv
+ *
+ * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive
+ * 
+ * Register where MSI writes are directed from the PCIe.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pcie_msi_rcv_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+#else
+        uint64_t intr                    : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_npei_pcie_msi_rcv_s      cn52xx;
+    struct cvmx_npei_pcie_msi_rcv_s      cn52xxp1;
+    struct cvmx_npei_pcie_msi_rcv_s      cn56xx;
+    struct cvmx_npei_pcie_msi_rcv_s      cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_t;
+
+
+/**
+ * cvmx_npei_pcie_msi_rcv_b1
+ *
+ * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1
+ * 
+ * Register where MSI writes are directed from the PCIe.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pcie_msi_rcv_b1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t intr                    : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npei_pcie_msi_rcv_b1_s   cn52xx;
+    struct cvmx_npei_pcie_msi_rcv_b1_s   cn52xxp1;
+    struct cvmx_npei_pcie_msi_rcv_b1_s   cn56xx;
+    struct cvmx_npei_pcie_msi_rcv_b1_s   cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_b1_t;
+
+
+/**
+ * cvmx_npei_pcie_msi_rcv_b2
+ *
+ * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2
+ * 
+ * Register where MSI writes are directed from the PCIe.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pcie_msi_rcv_b2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+        uint64_t reserved_0_15           : 16;
+#else
+        uint64_t reserved_0_15           : 16;
+        uint64_t intr                    : 8;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_npei_pcie_msi_rcv_b2_s   cn52xx;
+    struct cvmx_npei_pcie_msi_rcv_b2_s   cn52xxp1;
+    struct cvmx_npei_pcie_msi_rcv_b2_s   cn56xx;
+    struct cvmx_npei_pcie_msi_rcv_b2_s   cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_b2_t;
+
+
+/**
+ * cvmx_npei_pcie_msi_rcv_b3
+ *
+ * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3
+ * 
+ * Register where MSI writes are directed from the PCIe.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pcie_msi_rcv_b3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t intr                    : 8;       /**< A write to this register will result in a bit in
+                                                         one of the NPEI_MSI_RCV# registers being set.
+                                                         Which bit is set is dependent on the previously
+                                                         written using the NPEI_MSI_WR_MAP register or if
+                                                         not previously written the reset value of the MAP. */
+        uint64_t reserved_0_23           : 24;
+#else
+        uint64_t reserved_0_23           : 24;
+        uint64_t intr                    : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pcie_msi_rcv_b3_s   cn52xx;
+    struct cvmx_npei_pcie_msi_rcv_b3_s   cn52xxp1;
+    struct cvmx_npei_pcie_msi_rcv_b3_s   cn56xx;
+    struct cvmx_npei_pcie_msi_rcv_b3_s   cn56xxp1;
+} cvmx_npei_pcie_msi_rcv_b3_t;
+
+
+/**
+ * cvmx_npei_pkt#_cnts
+ *
+ * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts
+ * 
+ * The counters for output rings.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_cnts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_54_63          : 10;
+        uint64_t timer                   : 22;      /**< Timer incremented every 1024 core clocks
+                                                         when NPEI_PKTS#_CNTS[CNT] is non zero. Field
+                                                         cleared when NPEI_PKTS#_CNTS[CNT] goes to 0.
+                                                         Field is also cleared when NPEI_PKT_TIME_INT is
+                                                         cleared.
+                                                         The first increment of this count can occur
+                                                         between 0 to 1023 core clocks. */
+        uint64_t cnt                     : 32;      /**< ring counter. This field is incremented as
+                                                         packets are sent out and decremented in response to
+                                                         writes to this field.
+                                                         When NPEI_PKT_OUT_BMODE is '0' a value of 1 is
+                                                         added to the register for each packet, when '1'
+                                                         and the info-pointer is NOT used the length of the
+                                                         packet plus 8 is added, when '1' and info-pointer
+                                                         mode IS used the packet length is added to this
+                                                         field. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t timer                   : 22;
+        uint64_t reserved_54_63          : 10;
+#endif
+    } s;
+    struct cvmx_npei_pktx_cnts_s         cn52xx;
+    struct cvmx_npei_pktx_cnts_s         cn56xx;
+} cvmx_npei_pktx_cnts_t;
+
+
+/**
+ * cvmx_npei_pkt#_in_bp
+ *
+ * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure
+ * 
+ * The counters and thresholds for input packets to apply backpressure to processing of the packets.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_in_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t wmark                   : 32;      /**< When CNT is greater than this threshold no more
+                                                         packets will be processed for this ring.
+                                                         When writing this field of the NPEI_PKT#_IN_BP
+                                                         register, use a 4-byte write so as to not write
+                                                         any other field of this register. */
+        uint64_t cnt                     : 32;      /**< ring counter. This field is incremented by one
+                                                         whenever OCTEON receives, buffers, and creates a
+                                                         work queue entry for a packet that arrives by the
+                                                         cooresponding input ring. A write to this field
+                                                         will be subtracted from the field value.
+                                                         When writing this field of the NPEI_PKT#_IN_BP
+                                                         register, use a 4-byte write so as to not write
+                                                         any other field of this register. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t wmark                   : 32;
+#endif
+    } s;
+    struct cvmx_npei_pktx_in_bp_s        cn52xx;
+    struct cvmx_npei_pktx_in_bp_s        cn56xx;
+} cvmx_npei_pktx_in_bp_t;
+
+
+/**
+ * cvmx_npei_pkt#_instr_baddr
+ *
+ * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address
+ * 
+ * Start of Instruction for input packets.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_instr_baddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 61;      /**< Base address for Instructions. */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t addr                    : 61;
+#endif
+    } s;
+    struct cvmx_npei_pktx_instr_baddr_s  cn52xx;
+    struct cvmx_npei_pktx_instr_baddr_s  cn56xx;
+} cvmx_npei_pktx_instr_baddr_t;
+
+
+/**
+ * cvmx_npei_pkt#_instr_baoff_dbell
+ *
+ * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base Address Offset and Doorbell
+ * 
+ * The doorbell and base address offset for next read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_instr_baoff_dbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t aoff                    : 32;      /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR
+                                                         where the next instruction will be read. */
+        uint64_t dbell                   : 32;      /**< Instruction doorbell count. Writes to this field
+                                                         will increment the value here. Reads will return
+                                                         present value. A write of 0xffffffff will set the
+                                                         DBELL and AOFF fields to '0'. */
+#else
+        uint64_t dbell                   : 32;
+        uint64_t aoff                    : 32;
+#endif
+    } s;
+    struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
+    struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
+} cvmx_npei_pktx_instr_baoff_dbell_t;
+
+
+/**
+ * cvmx_npei_pkt#_instr_fifo_rsize
+ *
+ * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and Ring Size.
+ * 
+ * Fifo field and ring size for Instructions.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_instr_fifo_rsize_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t max                     : 9;       /**< Max Fifo Size. */
+        uint64_t rrp                     : 9;       /**< Fifo read pointer. */
+        uint64_t wrp                     : 9;       /**< Fifo write pointer. */
+        uint64_t fcnt                    : 5;       /**< Fifo count. */
+        uint64_t rsize                   : 32;      /**< Instruction ring size. */
+#else
+        uint64_t rsize                   : 32;
+        uint64_t fcnt                    : 5;
+        uint64_t wrp                     : 9;
+        uint64_t rrp                     : 9;
+        uint64_t max                     : 9;
+#endif
+    } s;
+    struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
+    struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
+} cvmx_npei_pktx_instr_fifo_rsize_t;
+
+
+/**
+ * cvmx_npei_pkt#_instr_header
+ *
+ * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header.
+ * 
+ * VAlues used to build input packet header.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_instr_header_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
+        uint64_t reserved_38_42          : 5;
+        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
+        uint64_t reserved_35_35          : 1;
+        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
+        uint64_t reserved_22_27          : 6;
+        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+        uint64_t reserved_16_20          : 5;
+        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t reserved_13_13          : 1;
+        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t reserved_0_5            : 6;
+#else
+        uint64_t reserved_0_5            : 6;
+        uint64_t skp_len                 : 7;
+        uint64_t reserved_13_13          : 1;
+        uint64_t par_mode                : 2;
+        uint64_t reserved_16_20          : 5;
+        uint64_t use_ihdr                : 1;
+        uint64_t reserved_22_27          : 6;
+        uint64_t rskp_len                : 7;
+        uint64_t reserved_35_35          : 1;
+        uint64_t rparmode                : 2;
+        uint64_t reserved_38_42          : 5;
+        uint64_t pbp                     : 1;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npei_pktx_instr_header_s cn52xx;
+    struct cvmx_npei_pktx_instr_header_s cn56xx;
+} cvmx_npei_pktx_instr_header_t;
+
+
+/**
+ * cvmx_npei_pkt#_slist_baddr
+ *
+ * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address
+ * 
+ * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_slist_baddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 60;      /**< Base address for scatter list pointers. */
+        uint64_t reserved_0_3            : 4;
+#else
+        uint64_t reserved_0_3            : 4;
+        uint64_t addr                    : 60;
+#endif
+    } s;
+    struct cvmx_npei_pktx_slist_baddr_s  cn52xx;
+    struct cvmx_npei_pktx_slist_baddr_s  cn56xx;
+} cvmx_npei_pktx_slist_baddr_t;
+
+
+/**
+ * cvmx_npei_pkt#_slist_baoff_dbell
+ *
+ * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base Address Offset and Doorbell
+ * 
+ * The doorbell and base address offset for next read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_slist_baoff_dbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t aoff                    : 32;      /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR
+                                                         where the next SList pointer will be read.
+                                                         A write of 0xFFFFFFFF to the DBELL field will
+                                                         clear DBELL and AOFF */
+        uint64_t dbell                   : 32;      /**< Scatter list doorbell count. Writes to this field
+                                                         will increment the value here. Reads will return
+                                                         present value. The value of this field is
+                                                         decremented as read operations are ISSUED for
+                                                         scatter pointers.
+                                                         A write of 0xFFFFFFFF will clear DBELL and AOFF */
+#else
+        uint64_t dbell                   : 32;
+        uint64_t aoff                    : 32;
+#endif
+    } s;
+    struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
+    struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
+} cvmx_npei_pktx_slist_baoff_dbell_t;
+
+
+/**
+ * cvmx_npei_pkt#_slist_fifo_rsize
+ *
+ * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and Ring Size.
+ * 
+ * The number of scatter pointer pairs in the scatter list.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pktx_slist_fifo_rsize_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rsize                   : 32;      /**< The number of scatter pointer pairs contained in
+                                                         the scatter list ring. */
+#else
+        uint64_t rsize                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
+    struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
+} cvmx_npei_pktx_slist_fifo_rsize_t;
+
+
+/**
+ * cvmx_npei_pkt_cnt_int
+ *
+ * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt
+ * 
+ * The packets rings that are interrupting because of Packet Counters.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_cnt_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number is set when
+                                                         NPEI_PKT#_CNTS[CNT] is greater
+                                                         than NPEI_PKT_INT_LEVELS[CNT]. */
+#else
+        uint64_t port                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_cnt_int_s       cn52xx;
+    struct cvmx_npei_pkt_cnt_int_s       cn56xx;
+} cvmx_npei_pkt_cnt_int_t;
+
+
+/**
+ * cvmx_npei_pkt_cnt_int_enb
+ *
+ * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable
+ * 
+ * Enable for the packets rings that are interrupting because of Packet Counters.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_cnt_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number when set
+                                                         allows NPEI_PKT_CNT_INT to generate an interrupt. */
+#else
+        uint64_t port                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_cnt_int_enb_s   cn52xx;
+    struct cvmx_npei_pkt_cnt_int_enb_s   cn56xx;
+} cvmx_npei_pkt_cnt_int_enb_t;
+
+
+/**
+ * cvmx_npei_pkt_data_out_es
+ *
+ * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap
+ * 
+ * The Endian Swap for writing Data Out.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_data_out_es_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t es                      : 64;      /**< The endian swap mode for Packet rings 0 through 31.
+                                                         Two bits are used per ring (i.e. ring 0 [1:0],
+                                                         ring 1 [3:2], ....). */
+#else
+        uint64_t es                      : 64;
+#endif
+    } s;
+    struct cvmx_npei_pkt_data_out_es_s   cn52xx;
+    struct cvmx_npei_pkt_data_out_es_s   cn56xx;
+} cvmx_npei_pkt_data_out_es_t;
+
+
+/**
+ * cvmx_npei_pkt_data_out_ns
+ *
+ * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop
+ * 
+ * The NS field for the TLP when writing packet data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_data_out_ns_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t nsr                     : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable NS in TLP header. */
+#else
+        uint64_t nsr                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_data_out_ns_s   cn52xx;
+    struct cvmx_npei_pkt_data_out_ns_s   cn56xx;
+} cvmx_npei_pkt_data_out_ns_t;
+
+
+/**
+ * cvmx_npei_pkt_data_out_ror
+ *
+ * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering
+ * 
+ * The ROR field for the TLP when writing Packet Data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_data_out_ror_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ror                     : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable ROR in TLP header. */
+#else
+        uint64_t ror                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_data_out_ror_s  cn52xx;
+    struct cvmx_npei_pkt_data_out_ror_s  cn56xx;
+} cvmx_npei_pkt_data_out_ror_t;
+
+
+/**
+ * cvmx_npei_pkt_dpaddr
+ *
+ * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr
+ * 
+ * Used to detemine address and attributes for packet data writes.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_dpaddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t dptr                    : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will use:
+                                                         the address[63:60] to write packet data
+                                                         comes from the DPTR[63:60] in the scatter-list
+                                                         pair and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. */
+#else
+        uint64_t dptr                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_dpaddr_s        cn52xx;
+    struct cvmx_npei_pkt_dpaddr_s        cn56xx;
+} cvmx_npei_pkt_dpaddr_t;
+
+
+/**
+ * cvmx_npei_pkt_in_bp
+ *
+ * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure
+ * 
+ * Which input rings have backpressure applied.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_in_bp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bp                      : 32;      /**< A packet input  ring that has its count greater
+                                                         than its WMARK will have backpressure applied.
+                                                         Each of the 32 bits coorespond to an input ring.
+                                                         When '1' that ring has backpressure applied an
+                                                         will fetch no more instructions, but will process
+                                                         any previously fetched instructions. */
+#else
+        uint64_t bp                      : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_in_bp_s         cn52xx;
+    struct cvmx_npei_pkt_in_bp_s         cn56xx;
+} cvmx_npei_pkt_in_bp_t;
+
+
+/**
+ * cvmx_npei_pkt_in_done#_cnts
+ *
+ * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts
+ * 
+ * Counters for instructions completed on Input rings.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_in_donex_cnts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< This field is incrmented by '1' when an instruction
+                                                         is completed. This field is incremented as the
+                                                         last of the data is read from the PCIe. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
+    struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
+} cvmx_npei_pkt_in_donex_cnts_t;
+
+
+/**
+ * cvmx_npei_pkt_in_instr_counts
+ *
+ * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts
+ * 
+ * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_in_instr_counts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t wr_cnt                  : 32;      /**< Shows the number of packets sent to the IPD. */
+        uint64_t rd_cnt                  : 32;      /**< Shows the value of instructions that have had reads
+                                                         issued for them.
+                                                         to the Packet-ring is in reset. */
+#else
+        uint64_t rd_cnt                  : 32;
+        uint64_t wr_cnt                  : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
+    struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
+} cvmx_npei_pkt_in_instr_counts_t;
+
+
+/**
+ * cvmx_npei_pkt_in_pcie_port
+ *
+ * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment
+ * 
+ * Assigns Packet Input rings to PCIe ports.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_in_pcie_port_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pp                      : 64;      /**< The PCIe port that the Packet ring number is
+                                                         assigned. Two bits are used per ring (i.e. ring 0
+                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
+                                                         that the Packetring is assign to PCIe Port 0, a '1'
+                                                         PCIe Port 1, '2' and '3' are reserved. */
+#else
+        uint64_t pp                      : 64;
+#endif
+    } s;
+    struct cvmx_npei_pkt_in_pcie_port_s  cn52xx;
+    struct cvmx_npei_pkt_in_pcie_port_s  cn56xx;
+} cvmx_npei_pkt_in_pcie_port_t;
+
+
+/**
+ * cvmx_npei_pkt_input_control
+ *
+ * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control
+ * 
+ * Control for reads for gather list and instructions.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_input_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t pkt_rr                  : 1;       /**< When set '1' the input packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the input packet ring is fixed in priority,
+                                                         where the lower ring number has higher priority. */
+        uint64_t pbp_dhi                 : 13;      /**< Field when in [PBP] is set to be used in
+                                                         calculating a DPTR. */
+        uint64_t d_nsr                   : 1;       /**< Enables '1' NoSnoop for reading of
+                                                         gather data. */
+        uint64_t d_esr                   : 2;       /**< The Endian-Swap-Mode for reading of
+                                                         gather data. */
+        uint64_t d_ror                   : 1;       /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather data. */
+        uint64_t use_csr                 : 1;       /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+        uint64_t nsr                     : 1;       /**< Enables '1' NoSnoop for reading of
+                                                         gather list and gather instruction. */
+        uint64_t esr                     : 2;       /**< The Endian-Swap-Mode for reading of
+                                                         gather list and gather instruction. */
+        uint64_t ror                     : 1;       /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather list and gather instruction. */
+#else
+        uint64_t ror                     : 1;
+        uint64_t esr                     : 2;
+        uint64_t nsr                     : 1;
+        uint64_t use_csr                 : 1;
+        uint64_t d_ror                   : 1;
+        uint64_t d_esr                   : 2;
+        uint64_t d_nsr                   : 1;
+        uint64_t pbp_dhi                 : 13;
+        uint64_t pkt_rr                  : 1;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_npei_pkt_input_control_s cn52xx;
+    struct cvmx_npei_pkt_input_control_s cn56xx;
+} cvmx_npei_pkt_input_control_t;
+
+
+/**
+ * cvmx_npei_pkt_instr_enb
+ *
+ * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable
+ * 
+ * Enables the instruction fetch for a Packet-ring.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_instr_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t enb                     : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring is enabled. */
+#else
+        uint64_t enb                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_instr_enb_s     cn52xx;
+    struct cvmx_npei_pkt_instr_enb_s     cn56xx;
+} cvmx_npei_pkt_instr_enb_t;
+
+
+/**
+ * cvmx_npei_pkt_instr_rd_size
+ *
+ * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size
+ * 
+ * The number of instruction allowed to be read at one time.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_instr_rd_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t rdsize                  : 64;      /**< Number of instructions to be read in one PCIe read
+                                                         request for the 4 PKOport - 8 rings. Every two bits
+                                                         (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring
+                                                         combinations.
+                                                         - 15:0  PKOPort0,Ring 7..0  31:16 PKOPort1,Ring 7..0
+                                                         - 47:32 PKOPort2,Ring 7..0  63:48 PKOPort3,Ring 7..0
+                                                         Two bit value are:
+                                                         0 - 1 Instruction
+                                                         1 - 2 Instructions
+                                                         2 - 3 Instructions
+                                                         3 - 4 Instructions */
+#else
+        uint64_t rdsize                  : 64;
+#endif
+    } s;
+    struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
+    struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
+} cvmx_npei_pkt_instr_rd_size_t;
+
+
+/**
+ * cvmx_npei_pkt_instr_size
+ *
+ * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size
+ * 
+ * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_instr_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t is_64b                  : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring is a 64-byte instruction. */
+#else
+        uint64_t is_64b                  : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_instr_size_s    cn52xx;
+    struct cvmx_npei_pkt_instr_size_s    cn56xx;
+} cvmx_npei_pkt_instr_size_t;
+
+
+/**
+ * cvmx_npei_pkt_int_levels
+ *
+ * 0x90F0 reserved NPEI_PKT_PCIE_PORT2
+ * 
+ * 
+ *                  NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels
+ * 
+ * Output packet interrupt levels.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_int_levels_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_54_63          : 10;
+        uint64_t time                    : 22;      /**< When NPEI_PKT#_CNTS[TIME] is equal to this value
+                                                         an interrupt is generated. */
+        uint64_t cnt                     : 32;      /**< When NPEI_PKT#_CNTS[CNT] becomes
+                                                         greater than this value an interrupt is generated. */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t time                    : 22;
+        uint64_t reserved_54_63          : 10;
+#endif
+    } s;
+    struct cvmx_npei_pkt_int_levels_s    cn52xx;
+    struct cvmx_npei_pkt_int_levels_s    cn56xx;
+} cvmx_npei_pkt_int_levels_t;
+
+
+/**
+ * cvmx_npei_pkt_iptr
+ *
+ * NPEI_PKT_IPTR = NPEI's Packet Info Poitner
+ * 
+ * Controls using the Info-Pointer to store length and data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_iptr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iptr                    : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will use the Info-Pointer to
+                                                         store length and data. */
+#else
+        uint64_t iptr                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_iptr_s          cn52xx;
+    struct cvmx_npei_pkt_iptr_s          cn56xx;
+} cvmx_npei_pkt_iptr_t;
+
+
+/**
+ * cvmx_npei_pkt_out_bmode
+ *
+ * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode
+ * 
+ * Control the updating of the NPEI_PKT#_CNT register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_out_bmode_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t bmode                   : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will have its NPEI_PKT#_CNT
+                                                         register updated with the number of bytes in the
+                                                         packet sent, when '0' the register will have a
+                                                         value of '1' added. */
+#else
+        uint64_t bmode                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_out_bmode_s     cn52xx;
+    struct cvmx_npei_pkt_out_bmode_s     cn56xx;
+} cvmx_npei_pkt_out_bmode_t;
+
+
+/**
+ * cvmx_npei_pkt_out_enb
+ *
+ * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable
+ * 
+ * Enables the output packet engines.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_out_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t enb                     : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring is enabled.
+                                                         If an error occurs on reading pointers for an
+                                                         output ring, the ring will be disabled by clearing
+                                                         the bit associated with the ring to '0'. */
+#else
+        uint64_t enb                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_out_enb_s       cn52xx;
+    struct cvmx_npei_pkt_out_enb_s       cn56xx;
+} cvmx_npei_pkt_out_enb_t;
+
+
+/**
+ * cvmx_npei_pkt_output_wmark
+ *
+ * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark
+ * 
+ * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_output_wmark_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t wmark                   : 32;      /**< Value when DBELL count drops below backpressure
+                                                         for the ring will be applied to the PKO. */
+#else
+        uint64_t wmark                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_output_wmark_s  cn52xx;
+    struct cvmx_npei_pkt_output_wmark_s  cn56xx;
+} cvmx_npei_pkt_output_wmark_t;
+
+
+/**
+ * cvmx_npei_pkt_pcie_port
+ *
+ * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment
+ * 
+ * Assigns Packet Ports to PCIe ports.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_pcie_port_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pp                      : 64;      /**< The PCIe port that the Packet ring number is
+                                                         assigned. Two bits are used per ring (i.e. ring 0
+                                                         [1:0], ring 1 [3:2], ....). A value of '0 means
+                                                         that the Packetring is assign to PCIe Port 0, a '1'
+                                                         PCIe Port 1, '2' and '3' are reserved. */
+#else
+        uint64_t pp                      : 64;
+#endif
+    } s;
+    struct cvmx_npei_pkt_pcie_port_s     cn52xx;
+    struct cvmx_npei_pkt_pcie_port_s     cn56xx;
+} cvmx_npei_pkt_pcie_port_t;
+
+
+/**
+ * cvmx_npei_pkt_port_in_rst
+ *
+ * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset
+ * 
+ * Vector bits related to ring-port for ones that are reset.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_port_in_rst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t in_rst                  : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the inbound Packet-ring is in reset. */
+        uint64_t out_rst                 : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the outbound Packet-ring is in reset. */
+#else
+        uint64_t out_rst                 : 32;
+        uint64_t in_rst                  : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_port_in_rst_s   cn52xx;
+    struct cvmx_npei_pkt_port_in_rst_s   cn56xx;
+} cvmx_npei_pkt_port_in_rst_t;
+
+
+/**
+ * cvmx_npei_pkt_slist_es
+ *
+ * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap
+ * 
+ * The Endian Swap for Scatter List Read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_slist_es_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t es                      : 64;      /**< The endian swap mode for Packet rings 0 through 31.
+                                                         Two bits are used per ring (i.e. ring 0 [1:0],
+                                                         ring 1 [3:2], ....). */
+#else
+        uint64_t es                      : 64;
+#endif
+    } s;
+    struct cvmx_npei_pkt_slist_es_s      cn52xx;
+    struct cvmx_npei_pkt_slist_es_s      cn56xx;
+} cvmx_npei_pkt_slist_es_t;
+
+
+/**
+ * cvmx_npei_pkt_slist_id_size
+ *
+ * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size
+ * 
+ * The Size of the information and data fields pointed to by Scatter List pointers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_slist_id_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t isize                   : 7;       /**< Information size. Legal sizes are 0 to 120. */
+        uint64_t bsize                   : 16;      /**< Data size. */
+#else
+        uint64_t bsize                   : 16;
+        uint64_t isize                   : 7;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_npei_pkt_slist_id_size_s cn52xx;
+    struct cvmx_npei_pkt_slist_id_size_s cn56xx;
+} cvmx_npei_pkt_slist_id_size_t;
+
+
+/**
+ * cvmx_npei_pkt_slist_ns
+ *
+ * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop
+ * 
+ * The NS field for the TLP when fetching Scatter List.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_slist_ns_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t nsr                     : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable NS in TLP header. */
+#else
+        uint64_t nsr                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_slist_ns_s      cn52xx;
+    struct cvmx_npei_pkt_slist_ns_s      cn56xx;
+} cvmx_npei_pkt_slist_ns_t;
+
+
+/**
+ * cvmx_npei_pkt_slist_ror
+ *
+ * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering
+ * 
+ * The ROR field for the TLP when fetching Scatter List.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_slist_ror_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ror                     : 32;      /**< When asserted '1' the vector bit cooresponding
+                                                         to the Packet-ring will enable ROR in TLP header. */
+#else
+        uint64_t ror                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_slist_ror_s     cn52xx;
+    struct cvmx_npei_pkt_slist_ror_s     cn56xx;
+} cvmx_npei_pkt_slist_ror_t;
+
+
+/**
+ * cvmx_npei_pkt_time_int
+ *
+ * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt
+ * 
+ * The packets rings that are interrupting because of Packet Timers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_time_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number is set when
+                                                         NPEI_PKT#_CNTS[TIMER] is greater than
+                                                         NPEI_PKT_INT_LEVELS[TIME]. */
+#else
+        uint64_t port                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_time_int_s      cn52xx;
+    struct cvmx_npei_pkt_time_int_s      cn56xx;
+} cvmx_npei_pkt_time_int_t;
+
+
+/**
+ * cvmx_npei_pkt_time_int_enb
+ *
+ * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable
+ * 
+ * The packets rings that are interrupting because of Packet Timers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_pkt_time_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t port                    : 32;      /**< Bit vector cooresponding to ring number when set
+                                                         allows NPEI_PKT_TIME_INT to generate an interrupt. */
+#else
+        uint64_t port                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_pkt_time_int_enb_s  cn52xx;
+    struct cvmx_npei_pkt_time_int_enb_s  cn56xx;
+} cvmx_npei_pkt_time_int_enb_t;
+
+
+/**
+ * cvmx_npei_rsl_int_blocks
+ *
+ * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register
+ * 
+ * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
+ * that presently has an interrupt pending. The Field Description below supplies the name of the
+ * register that software should read to find out why that intterupt bit is set.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_rsl_int_blocks_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
+        uint64_t lmc1                    : 1;       /**< LMC1_MEM_CFG0 */
+        uint64_t agl                     : 1;       /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */
+        uint64_t reserved_24_27          : 4;
+        uint64_t asxpcs1                 : 1;       /**< PCS1_INT*_REG */
+        uint64_t asxpcs0                 : 1;       /**< PCS0_INT*_REG */
+        uint64_t reserved_21_21          : 1;
+        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
+        uint64_t spx1                    : 1;       /**< Always reads as zero */
+        uint64_t spx0                    : 1;       /**< Always reads as zero */
+        uint64_t lmc0                    : 1;       /**< LMC0_MEM_CFG0 */
+        uint64_t l2c                     : 1;       /**< L2C_INT_STAT */
+        uint64_t usb1                    : 1;       /**< Always reads as zero */
+        uint64_t rad                     : 1;       /**< RAD_REG_ERROR */
+        uint64_t usb                     : 1;       /**< USBN0_INT_SUM */
+        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
+        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
+        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
+        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
+        uint64_t reserved_8_8            : 1;
+        uint64_t zip                     : 1;       /**< ZIP_ERROR */
+        uint64_t dfa                     : 1;       /**< Always reads as zero */
+        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
+        uint64_t key                     : 1;       /**< KEY_INT_SUM */
+        uint64_t npei                    : 1;       /**< NPEI_INT_SUM */
+        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
+#else
+        uint64_t mio                     : 1;
+        uint64_t gmx0                    : 1;
+        uint64_t gmx1                    : 1;
+        uint64_t npei                    : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t reserved_8_8            : 1;
+        uint64_t ipd                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t tim                     : 1;
+        uint64_t pow                     : 1;
+        uint64_t usb                     : 1;
+        uint64_t rad                     : 1;
+        uint64_t usb1                    : 1;
+        uint64_t l2c                     : 1;
+        uint64_t lmc0                    : 1;
+        uint64_t spx0                    : 1;
+        uint64_t spx1                    : 1;
+        uint64_t pip                     : 1;
+        uint64_t reserved_21_21          : 1;
+        uint64_t asxpcs0                 : 1;
+        uint64_t asxpcs1                 : 1;
+        uint64_t reserved_24_27          : 4;
+        uint64_t agl                     : 1;
+        uint64_t lmc1                    : 1;
+        uint64_t iob                     : 1;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_npei_rsl_int_blocks_s    cn52xx;
+    struct cvmx_npei_rsl_int_blocks_s    cn52xxp1;
+    struct cvmx_npei_rsl_int_blocks_s    cn56xx;
+    struct cvmx_npei_rsl_int_blocks_s    cn56xxp1;
+} cvmx_npei_rsl_int_blocks_t;
+
+
+/**
+ * cvmx_npei_scratch_1
+ *
+ * NPEI_SCRATCH_1 = NPEI's Scratch 1
+ * 
+ * A general purpose 64 bit register for SW use.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_scratch_1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< The value in this register is totaly SW dependent. */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_npei_scratch_1_s         cn52xx;
+    struct cvmx_npei_scratch_1_s         cn52xxp1;
+    struct cvmx_npei_scratch_1_s         cn56xx;
+    struct cvmx_npei_scratch_1_s         cn56xxp1;
+} cvmx_npei_scratch_1_t;
+
+
+/**
+ * cvmx_npei_state1
+ *
+ * NPEI_STATE1 = NPEI State 1
+ * 
+ * State machines in NPEI. For debug.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_state1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t cpl1                    : 12;      /**< CPL1 State */
+        uint64_t cpl0                    : 12;      /**< CPL0 State */
+        uint64_t arb                     : 1;       /**< ARB State */
+        uint64_t csr                     : 39;      /**< CSR State */
+#else
+        uint64_t csr                     : 39;
+        uint64_t arb                     : 1;
+        uint64_t cpl0                    : 12;
+        uint64_t cpl1                    : 12;
+#endif
+    } s;
+    struct cvmx_npei_state1_s            cn52xx;
+    struct cvmx_npei_state1_s            cn52xxp1;
+    struct cvmx_npei_state1_s            cn56xx;
+    struct cvmx_npei_state1_s            cn56xxp1;
+} cvmx_npei_state1_t;
+
+
+/**
+ * cvmx_npei_state2
+ *
+ * NPEI_STATE2 = NPEI State 2
+ * 
+ * State machines in NPEI. For debug.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_state2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t npei                    : 1;       /**< NPEI State */
+        uint64_t rac                     : 1;       /**< RAC State */
+        uint64_t csm1                    : 15;      /**< CSM1 State */
+        uint64_t csm0                    : 15;      /**< CSM0 State */
+        uint64_t nnp0                    : 8;       /**< NNP0 State */
+        uint64_t nnd                     : 8;       /**< NND State */
+#else
+        uint64_t nnd                     : 8;
+        uint64_t nnp0                    : 8;
+        uint64_t csm0                    : 15;
+        uint64_t csm1                    : 15;
+        uint64_t rac                     : 1;
+        uint64_t npei                    : 1;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_npei_state2_s            cn52xx;
+    struct cvmx_npei_state2_s            cn52xxp1;
+    struct cvmx_npei_state2_s            cn56xx;
+    struct cvmx_npei_state2_s            cn56xxp1;
+} cvmx_npei_state2_t;
+
+
+/**
+ * cvmx_npei_state3
+ *
+ * NPEI_STATE3 = NPEI State 3
+ * 
+ * State machines in NPEI. For debug.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_state3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t psm1                    : 15;      /**< PSM1 State */
+        uint64_t psm0                    : 15;      /**< PSM0 State */
+        uint64_t nsm1                    : 13;      /**< NSM1 State */
+        uint64_t nsm0                    : 13;      /**< NSM0 State */
+#else
+        uint64_t nsm0                    : 13;
+        uint64_t nsm1                    : 13;
+        uint64_t psm0                    : 15;
+        uint64_t psm1                    : 15;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } s;
+    struct cvmx_npei_state3_s            cn52xx;
+    struct cvmx_npei_state3_s            cn52xxp1;
+    struct cvmx_npei_state3_s            cn56xx;
+    struct cvmx_npei_state3_s            cn56xxp1;
+} cvmx_npei_state3_t;
+
+
+/**
+ * cvmx_npei_win_rd_addr
+ *
+ * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register
+ * 
+ * The address to be read when the NPEI_WIN_RD_DATA register is read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_win_rd_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_51_63          : 13;
+        uint64_t ld_cmd                  : 2;       /**< The load command sent wit hthe read.
+                                                         0x0 == Load 8-bytes, 0x1 == Load 4-bytes,
+                                                         0x2 == Load 2-bytes, 0x3 == Load 1-bytes, */
+        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+        uint64_t rd_addr                 : 48;      /**< The address to be read from. Whenever the LSB of
+                                                         this register is written, the Read Operation will
+                                                         take place.
+                                                         [47:40] = NCB_ID
+                                                         [39:0]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:0]  == RSL Register Offset */
+#else
+        uint64_t rd_addr                 : 48;
+        uint64_t iobit                   : 1;
+        uint64_t ld_cmd                  : 2;
+        uint64_t reserved_51_63          : 13;
+#endif
+    } s;
+    struct cvmx_npei_win_rd_addr_s       cn52xx;
+    struct cvmx_npei_win_rd_addr_s       cn52xxp1;
+    struct cvmx_npei_win_rd_addr_s       cn56xx;
+    struct cvmx_npei_win_rd_addr_s       cn56xxp1;
+} cvmx_npei_win_rd_addr_t;
+
+
+/**
+ * cvmx_npei_win_rd_data
+ *
+ * NPEI_WIN_RD_DATA = NPEI Window Read Data Register
+ * 
+ * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR
+ * register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_win_rd_data_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t rd_data                 : 64;      /**< The read data. */
+#else
+        uint64_t rd_data                 : 64;
+#endif
+    } s;
+    struct cvmx_npei_win_rd_data_s       cn52xx;
+    struct cvmx_npei_win_rd_data_s       cn52xxp1;
+    struct cvmx_npei_win_rd_data_s       cn56xx;
+    struct cvmx_npei_win_rd_data_s       cn56xxp1;
+} cvmx_npei_win_rd_data_t;
+
+
+/**
+ * cvmx_npei_win_wr_addr
+ *
+ * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register
+ * 
+ * Contains the address to be writen to when a write operation is started by writing the
+ * NPEI_WIN_WR_DATA register (see below).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_win_wr_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+        uint64_t wr_addr                 : 46;      /**< The address that will be written to when the
+                                                         NPEI_WIN_WR_DATA register is written.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:2]  == RSL Register Offset
+                                                              [1:0]   == x, Not Used */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t wr_addr                 : 46;
+        uint64_t iobit                   : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_npei_win_wr_addr_s       cn52xx;
+    struct cvmx_npei_win_wr_addr_s       cn52xxp1;
+    struct cvmx_npei_win_wr_addr_s       cn56xx;
+    struct cvmx_npei_win_wr_addr_s       cn56xxp1;
+} cvmx_npei_win_wr_addr_t;
+
+
+/**
+ * cvmx_npei_win_wr_data
+ *
+ * NPEI_WIN_WR_DATA = NPEI Window Write Data Register
+ * 
+ * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register.
+ * Writing the least-significant-byte of this register will cause a write operation to take place.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_win_wr_data_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t wr_data                 : 64;      /**< The data to be written. Whenever the LSB of this
+                                                         register is written, the Window Write will take
+                                                         place. */
+#else
+        uint64_t wr_data                 : 64;
+#endif
+    } s;
+    struct cvmx_npei_win_wr_data_s       cn52xx;
+    struct cvmx_npei_win_wr_data_s       cn52xxp1;
+    struct cvmx_npei_win_wr_data_s       cn56xx;
+    struct cvmx_npei_win_wr_data_s       cn56xxp1;
+} cvmx_npei_win_wr_data_t;
+
+
+/**
+ * cvmx_npei_win_wr_mask
+ *
+ * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register
+ * 
+ * Contains the mask for the data in the NPEI_WIN_WR_DATA Register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_win_wr_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t wr_mask                 : 8;       /**< The data to be written. When a bit is '0'
+                                                         the corresponding byte will be written. */
+#else
+        uint64_t wr_mask                 : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_npei_win_wr_mask_s       cn52xx;
+    struct cvmx_npei_win_wr_mask_s       cn52xxp1;
+    struct cvmx_npei_win_wr_mask_s       cn56xx;
+    struct cvmx_npei_win_wr_mask_s       cn56xxp1;
+} cvmx_npei_win_wr_mask_t;
+
+
+/**
+ * cvmx_npei_window_ctl
+ *
+ * NPEI_WINDOW_CTL = NPEI's Window Control
+ * 
+ * The name of this register is misleading. The timeout value is used for BAR0 access from PCIE0 and PCIE1.
+ * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. At time of timeout the next
+ * RML access will start, and interrupt will be set, and in the case of reads no data will be returned.
+ * 
+ * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register
+ * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npei_window_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t time                    : 32;      /**< Time to wait in core clocks to wait for a
+                                                         BAR0 access to completeon the NCB
+                                                         before timing out. A value of 0 will cause no
+                                                         timeouts. A minimum value of 0x200000 should be
+                                                         used when this register is not set to 0x0. */
+#else
+        uint64_t time                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npei_window_ctl_s        cn52xx;
+    struct cvmx_npei_window_ctl_s        cn52xxp1;
+    struct cvmx_npei_window_ctl_s        cn56xx;
+    struct cvmx_npei_window_ctl_s        cn56xxp1;
+} cvmx_npei_window_ctl_t;
+
+
+/**
+ * cvmx_npi_base_addr_input#
+ *
+ * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register
+ * 
+ * The address to start reading Instructions from for Input-0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_base_addr_inputx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t baddr                   : 61;      /**< The address to read Instruction from for output 0.
+                                                         This address is 8-byte aligned, for this reason
+                                                         address bits [2:0] will always be zero. */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t baddr                   : 61;
+#endif
+    } s;
+    struct cvmx_npi_base_addr_inputx_s   cn30xx;
+    struct cvmx_npi_base_addr_inputx_s   cn31xx;
+    struct cvmx_npi_base_addr_inputx_s   cn38xx;
+    struct cvmx_npi_base_addr_inputx_s   cn38xxp2;
+    struct cvmx_npi_base_addr_inputx_s   cn50xx;
+    struct cvmx_npi_base_addr_inputx_s   cn58xx;
+    struct cvmx_npi_base_addr_inputx_s   cn58xxp1;
+} cvmx_npi_base_addr_inputx_t;
+
+
+/**
+ * cvmx_npi_base_addr_output#
+ *
+ * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register
+ * 
+ * The address to start reading Instructions from for Output-0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_base_addr_outputx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t baddr                   : 61;      /**< The address to read Instruction from for output 0.
+                                                         This address is 8-byte aligned, for this reason
+                                                         address bits [2:0] will always be zero. */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t baddr                   : 61;
+#endif
+    } s;
+    struct cvmx_npi_base_addr_outputx_s  cn30xx;
+    struct cvmx_npi_base_addr_outputx_s  cn31xx;
+    struct cvmx_npi_base_addr_outputx_s  cn38xx;
+    struct cvmx_npi_base_addr_outputx_s  cn38xxp2;
+    struct cvmx_npi_base_addr_outputx_s  cn50xx;
+    struct cvmx_npi_base_addr_outputx_s  cn58xx;
+    struct cvmx_npi_base_addr_outputx_s  cn58xxp1;
+} cvmx_npi_base_addr_outputx_t;
+
+
+/**
+ * cvmx_npi_bist_status
+ *
+ * NPI_BIST_STATUS = NPI's BIST Status Register
+ * 
+ * Results from BIST runs of NPI's memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t csr_bs                  : 1;       /**< BIST Status for the csr_fifo */
+        uint64_t dif_bs                  : 1;       /**< BIST Status for the dif_fifo */
+        uint64_t rdp_bs                  : 1;       /**< BIST Status for the rdp_fifo */
+        uint64_t pcnc_bs                 : 1;       /**< BIST Status for the pcn_cnt_fifo */
+        uint64_t pcn_bs                  : 1;       /**< BIST Status for the pcn_fifo */
+        uint64_t rdn_bs                  : 1;       /**< BIST Status for the rdn_fifo */
+        uint64_t pcac_bs                 : 1;       /**< BIST Status for the pca_cmd_fifo */
+        uint64_t pcad_bs                 : 1;       /**< BIST Status for the pca_data_fifo */
+        uint64_t rdnl_bs                 : 1;       /**< BIST Status for the rdn_length_fifo */
+        uint64_t pgf_bs                  : 1;       /**< BIST Status for the pgf_fifo */
+        uint64_t pig_bs                  : 1;       /**< BIST Status for the pig_fifo */
+        uint64_t pof0_bs                 : 1;       /**< BIST Status for the pof0_fifo */
+        uint64_t pof1_bs                 : 1;       /**< BIST Status for the pof1_fifo */
+        uint64_t pof2_bs                 : 1;       /**< BIST Status for the pof2_fifo */
+        uint64_t pof3_bs                 : 1;       /**< BIST Status for the pof3_fifo */
+        uint64_t pos_bs                  : 1;       /**< BIST Status for the pos_fifo */
+        uint64_t nus_bs                  : 1;       /**< BIST Status for the nus_fifo */
+        uint64_t dob_bs                  : 1;       /**< BIST Status for the dob_fifo */
+        uint64_t pdf_bs                  : 1;       /**< BIST Status for the pdf_fifo */
+        uint64_t dpi_bs                  : 1;       /**< BIST Status for the dpi_fifo */
+#else
+        uint64_t dpi_bs                  : 1;
+        uint64_t pdf_bs                  : 1;
+        uint64_t dob_bs                  : 1;
+        uint64_t nus_bs                  : 1;
+        uint64_t pos_bs                  : 1;
+        uint64_t pof3_bs                 : 1;
+        uint64_t pof2_bs                 : 1;
+        uint64_t pof1_bs                 : 1;
+        uint64_t pof0_bs                 : 1;
+        uint64_t pig_bs                  : 1;
+        uint64_t pgf_bs                  : 1;
+        uint64_t rdnl_bs                 : 1;
+        uint64_t pcad_bs                 : 1;
+        uint64_t pcac_bs                 : 1;
+        uint64_t rdn_bs                  : 1;
+        uint64_t pcn_bs                  : 1;
+        uint64_t pcnc_bs                 : 1;
+        uint64_t rdp_bs                  : 1;
+        uint64_t dif_bs                  : 1;
+        uint64_t csr_bs                  : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_npi_bist_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t csr_bs                  : 1;       /**< BIST Status for the csr_fifo */
+        uint64_t dif_bs                  : 1;       /**< BIST Status for the dif_fifo */
+        uint64_t rdp_bs                  : 1;       /**< BIST Status for the rdp_fifo */
+        uint64_t pcnc_bs                 : 1;       /**< BIST Status for the pcn_cnt_fifo */
+        uint64_t pcn_bs                  : 1;       /**< BIST Status for the pcn_fifo */
+        uint64_t rdn_bs                  : 1;       /**< BIST Status for the rdn_fifo */
+        uint64_t pcac_bs                 : 1;       /**< BIST Status for the pca_cmd_fifo */
+        uint64_t pcad_bs                 : 1;       /**< BIST Status for the pca_data_fifo */
+        uint64_t rdnl_bs                 : 1;       /**< BIST Status for the rdn_length_fifo */
+        uint64_t pgf_bs                  : 1;       /**< BIST Status for the pgf_fifo */
+        uint64_t pig_bs                  : 1;       /**< BIST Status for the pig_fifo */
+        uint64_t pof0_bs                 : 1;       /**< BIST Status for the pof0_fifo */
+        uint64_t reserved_5_7            : 3;
+        uint64_t pos_bs                  : 1;       /**< BIST Status for the pos_fifo */
+        uint64_t nus_bs                  : 1;       /**< BIST Status for the nus_fifo */
+        uint64_t dob_bs                  : 1;       /**< BIST Status for the dob_fifo */
+        uint64_t pdf_bs                  : 1;       /**< BIST Status for the pdf_fifo */
+        uint64_t dpi_bs                  : 1;       /**< BIST Status for the dpi_fifo */
+#else
+        uint64_t dpi_bs                  : 1;
+        uint64_t pdf_bs                  : 1;
+        uint64_t dob_bs                  : 1;
+        uint64_t nus_bs                  : 1;
+        uint64_t pos_bs                  : 1;
+        uint64_t reserved_5_7            : 3;
+        uint64_t pof0_bs                 : 1;
+        uint64_t pig_bs                  : 1;
+        uint64_t pgf_bs                  : 1;
+        uint64_t rdnl_bs                 : 1;
+        uint64_t pcad_bs                 : 1;
+        uint64_t pcac_bs                 : 1;
+        uint64_t rdn_bs                  : 1;
+        uint64_t pcn_bs                  : 1;
+        uint64_t pcnc_bs                 : 1;
+        uint64_t rdp_bs                  : 1;
+        uint64_t dif_bs                  : 1;
+        uint64_t csr_bs                  : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn30xx;
+    struct cvmx_npi_bist_status_s        cn31xx;
+    struct cvmx_npi_bist_status_s        cn38xx;
+    struct cvmx_npi_bist_status_s        cn38xxp2;
+    struct cvmx_npi_bist_status_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t csr_bs                  : 1;       /**< BIST Status for the csr_fifo */
+        uint64_t dif_bs                  : 1;       /**< BIST Status for the dif_fifo */
+        uint64_t rdp_bs                  : 1;       /**< BIST Status for the rdp_fifo */
+        uint64_t pcnc_bs                 : 1;       /**< BIST Status for the pcn_cnt_fifo */
+        uint64_t pcn_bs                  : 1;       /**< BIST Status for the pcn_fifo */
+        uint64_t rdn_bs                  : 1;       /**< BIST Status for the rdn_fifo */
+        uint64_t pcac_bs                 : 1;       /**< BIST Status for the pca_cmd_fifo */
+        uint64_t pcad_bs                 : 1;       /**< BIST Status for the pca_data_fifo */
+        uint64_t rdnl_bs                 : 1;       /**< BIST Status for the rdn_length_fifo */
+        uint64_t pgf_bs                  : 1;       /**< BIST Status for the pgf_fifo */
+        uint64_t pig_bs                  : 1;       /**< BIST Status for the pig_fifo */
+        uint64_t pof0_bs                 : 1;       /**< BIST Status for the pof0_fifo */
+        uint64_t pof1_bs                 : 1;       /**< BIST Status for the pof1_fifo */
+        uint64_t reserved_5_6            : 2;
+        uint64_t pos_bs                  : 1;       /**< BIST Status for the pos_fifo */
+        uint64_t nus_bs                  : 1;       /**< BIST Status for the nus_fifo */
+        uint64_t dob_bs                  : 1;       /**< BIST Status for the dob_fifo */
+        uint64_t pdf_bs                  : 1;       /**< BIST Status for the pdf_fifo */
+        uint64_t dpi_bs                  : 1;       /**< BIST Status for the dpi_fifo */
+#else
+        uint64_t dpi_bs                  : 1;
+        uint64_t pdf_bs                  : 1;
+        uint64_t dob_bs                  : 1;
+        uint64_t nus_bs                  : 1;
+        uint64_t pos_bs                  : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t pof1_bs                 : 1;
+        uint64_t pof0_bs                 : 1;
+        uint64_t pig_bs                  : 1;
+        uint64_t pgf_bs                  : 1;
+        uint64_t rdnl_bs                 : 1;
+        uint64_t pcad_bs                 : 1;
+        uint64_t pcac_bs                 : 1;
+        uint64_t rdn_bs                  : 1;
+        uint64_t pcn_bs                  : 1;
+        uint64_t pcnc_bs                 : 1;
+        uint64_t rdp_bs                  : 1;
+        uint64_t dif_bs                  : 1;
+        uint64_t csr_bs                  : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn50xx;
+    struct cvmx_npi_bist_status_s        cn58xx;
+    struct cvmx_npi_bist_status_s        cn58xxp1;
+} cvmx_npi_bist_status_t;
+
+
+/**
+ * cvmx_npi_buff_size_output#
+ *
+ * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0
+ * 
+ * The size in bytes of the Data Bufffer and Information Buffer for output 0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_buff_size_outputx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t isize                   : 7;       /**< The number of bytes to move to the Info-Pointer
+                                                         from the front of the packet.
+                                                         Legal values are 0-120. */
+        uint64_t bsize                   : 16;      /**< The size in bytes of the area pointed to by
+                                                         buffer pointer for output packet data. */
+#else
+        uint64_t bsize                   : 16;
+        uint64_t isize                   : 7;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_npi_buff_size_outputx_s  cn30xx;
+    struct cvmx_npi_buff_size_outputx_s  cn31xx;
+    struct cvmx_npi_buff_size_outputx_s  cn38xx;
+    struct cvmx_npi_buff_size_outputx_s  cn38xxp2;
+    struct cvmx_npi_buff_size_outputx_s  cn50xx;
+    struct cvmx_npi_buff_size_outputx_s  cn58xx;
+    struct cvmx_npi_buff_size_outputx_s  cn58xxp1;
+} cvmx_npi_buff_size_outputx_t;
+
+
+/**
+ * cvmx_npi_comp_ctl
+ *
+ * NPI_COMP_CTL = PCI Compensation Control
+ * 
+ * PCI Compensation Control
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_comp_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t pctl                    : 5;       /**< Bypass value for PCTL */
+        uint64_t nctl                    : 5;       /**< Bypass value for NCTL */
+#else
+        uint64_t nctl                    : 5;
+        uint64_t pctl                    : 5;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_npi_comp_ctl_s           cn50xx;
+    struct cvmx_npi_comp_ctl_s           cn58xx;
+    struct cvmx_npi_comp_ctl_s           cn58xxp1;
+} cvmx_npi_comp_ctl_t;
+
+
+/**
+ * cvmx_npi_ctl_status
+ *
+ * NPI_CTL_STATUS = NPI's Control Status Register
+ * 
+ * Contains control ans status for NPI.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_63_63          : 1;
+        uint64_t chip_rev                : 8;       /**< The revision of the N3. */
+        uint64_t dis_pniw                : 1;       /**< When asserted '1' access from the PNI Window
+                                                         Registers are disabled. */
+        uint64_t out3_enb                : 1;       /**< When asserted '1' the output3 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t out2_enb                : 1;       /**< When asserted '1' the output2 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t out1_enb                : 1;       /**< When asserted '1' the output1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t out0_enb                : 1;       /**< When asserted '1' the output0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t ins3_enb                : 1;       /**< When asserted '1' the gather3 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t ins2_enb                : 1;       /**< When asserted '1' the gather2 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t ins1_enb                : 1;       /**< When asserted '1' the gather1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t ins0_enb                : 1;       /**< When asserted '1' the gather0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t ins3_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather3 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t ins2_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather2 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t ins1_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather1 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t ins0_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather0 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t pci_wdis                : 1;       /**< When set '1' disables access to registers in
+                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
+        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional access to
+                                                         the L2C from the PCI. */
+        uint64_t reserved_37_39          : 3;
+        uint64_t max_word                : 5;       /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCI. Legal
+                                                         values are 1 to 32, where a '0' is treated as 32. */
+        uint64_t reserved_10_31          : 22;
+        uint64_t timer                   : 10;      /**< When the NPI starts a PP to PCI write it will wait
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+        uint64_t timer                   : 10;
+        uint64_t reserved_10_31          : 22;
+        uint64_t max_word                : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t wait_com                : 1;
+        uint64_t pci_wdis                : 1;
+        uint64_t ins0_64b                : 1;
+        uint64_t ins1_64b                : 1;
+        uint64_t ins2_64b                : 1;
+        uint64_t ins3_64b                : 1;
+        uint64_t ins0_enb                : 1;
+        uint64_t ins1_enb                : 1;
+        uint64_t ins2_enb                : 1;
+        uint64_t ins3_enb                : 1;
+        uint64_t out0_enb                : 1;
+        uint64_t out1_enb                : 1;
+        uint64_t out2_enb                : 1;
+        uint64_t out3_enb                : 1;
+        uint64_t dis_pniw                : 1;
+        uint64_t chip_rev                : 8;
+        uint64_t reserved_63_63          : 1;
+#endif
+    } s;
+    struct cvmx_npi_ctl_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_63_63          : 1;
+        uint64_t chip_rev                : 8;       /**< The revision of the N3. */
+        uint64_t dis_pniw                : 1;       /**< When asserted '1' access from the PNI Window
+                                                         Registers are disabled. */
+        uint64_t reserved_51_53          : 3;
+        uint64_t out0_enb                : 1;       /**< When asserted '1' the output0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t reserved_47_49          : 3;
+        uint64_t ins0_enb                : 1;       /**< When asserted '1' the gather0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t reserved_43_45          : 3;
+        uint64_t ins0_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather0 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t pci_wdis                : 1;       /**< When set '1' disables access to registers in
+                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
+        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional access to
+                                                         the L2C from the PCI. */
+        uint64_t reserved_37_39          : 3;
+        uint64_t max_word                : 5;       /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCI. Legal
+                                                         values are 1 to 32, where a '0' is treated as 32. */
+        uint64_t reserved_10_31          : 22;
+        uint64_t timer                   : 10;      /**< When the NPI starts a PP to PCI write it will wait
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+        uint64_t timer                   : 10;
+        uint64_t reserved_10_31          : 22;
+        uint64_t max_word                : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t wait_com                : 1;
+        uint64_t pci_wdis                : 1;
+        uint64_t ins0_64b                : 1;
+        uint64_t reserved_43_45          : 3;
+        uint64_t ins0_enb                : 1;
+        uint64_t reserved_47_49          : 3;
+        uint64_t out0_enb                : 1;
+        uint64_t reserved_51_53          : 3;
+        uint64_t dis_pniw                : 1;
+        uint64_t chip_rev                : 8;
+        uint64_t reserved_63_63          : 1;
+#endif
+    } cn30xx;
+    struct cvmx_npi_ctl_status_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_63_63          : 1;
+        uint64_t chip_rev                : 8;       /**< The revision of the N3.
+                                                         0 => pass1.x, 1 => 2.0 */
+        uint64_t dis_pniw                : 1;       /**< When asserted '1' access from the PNI Window
+                                                         Registers are disabled. */
+        uint64_t reserved_52_53          : 2;
+        uint64_t out1_enb                : 1;       /**< When asserted '1' the output1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t out0_enb                : 1;       /**< When asserted '1' the output0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t reserved_48_49          : 2;
+        uint64_t ins1_enb                : 1;       /**< When asserted '1' the gather1 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t ins0_enb                : 1;       /**< When asserted '1' the gather0 engine is enabled.
+                                                         After enabling the values of the associated
+                                                         Address and Size Register should not be changed. */
+        uint64_t reserved_44_45          : 2;
+        uint64_t ins1_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather1 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t ins0_64b                : 1;       /**< When asserted '1' the instructions read by the
+                                                         gather0 engine are 64-Byte instructions, when
+                                                         de-asserted '0' instructions are 32-byte. */
+        uint64_t pci_wdis                : 1;       /**< When set '1' disables access to registers in
+                                                         PNI address range 0x1000 - 0x17FF from the PCI. */
+        uint64_t wait_com                : 1;       /**< When set '1' casues the NPI to wait for a commit
+                                                         from the L2C before sending additional access to
+                                                         the L2C from the PCI. */
+        uint64_t reserved_37_39          : 3;
+        uint64_t max_word                : 5;       /**< The maximum number of words to merge into a single
+                                                         write operation from the PPs to the PCI. Legal
+                                                         values are 1 to 32, where a '0' is treated as 32. */
+        uint64_t reserved_10_31          : 22;
+        uint64_t timer                   : 10;      /**< When the NPI starts a PP to PCI write it will wait
+                                                         no longer than the value of TIMER in eclks to
+                                                         merge additional writes from the PPs into 1
+                                                         large write. The values for this field is 1 to
+                                                         1024 where a value of '0' is treated as 1024. */
+#else
+        uint64_t timer                   : 10;
+        uint64_t reserved_10_31          : 22;
+        uint64_t max_word                : 5;
+        uint64_t reserved_37_39          : 3;
+        uint64_t wait_com                : 1;
+        uint64_t pci_wdis                : 1;
+        uint64_t ins0_64b                : 1;
+        uint64_t ins1_64b                : 1;
+        uint64_t reserved_44_45          : 2;
+        uint64_t ins0_enb                : 1;
+        uint64_t ins1_enb                : 1;
+        uint64_t reserved_48_49          : 2;
+        uint64_t out0_enb                : 1;
+        uint64_t out1_enb                : 1;
+        uint64_t reserved_52_53          : 2;
+        uint64_t dis_pniw                : 1;
+        uint64_t chip_rev                : 8;
+        uint64_t reserved_63_63          : 1;
+#endif
+    } cn31xx;
+    struct cvmx_npi_ctl_status_s         cn38xx;
+    struct cvmx_npi_ctl_status_s         cn38xxp2;
+    struct cvmx_npi_ctl_status_cn31xx    cn50xx;
+    struct cvmx_npi_ctl_status_s         cn58xx;
+    struct cvmx_npi_ctl_status_s         cn58xxp1;
+} cvmx_npi_ctl_status_t;
+
+
+/**
+ * cvmx_npi_dbg_select
+ *
+ * NPI_DBG_SELECT = Debug Select Register
+ * 
+ * Contains the debug select value in last written to the RSLs.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_dbg_select_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dbg_sel                 : 16;      /**< When this register is written its value is sent to
+                                                         all RSLs. */
+#else
+        uint64_t dbg_sel                 : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npi_dbg_select_s         cn30xx;
+    struct cvmx_npi_dbg_select_s         cn31xx;
+    struct cvmx_npi_dbg_select_s         cn38xx;
+    struct cvmx_npi_dbg_select_s         cn38xxp2;
+    struct cvmx_npi_dbg_select_s         cn50xx;
+    struct cvmx_npi_dbg_select_s         cn58xx;
+    struct cvmx_npi_dbg_select_s         cn58xxp1;
+} cvmx_npi_dbg_select_t;
+
+
+/**
+ * cvmx_npi_dma_control
+ *
+ * NPI_DMA_CONTROL = DMA Control Register
+ * 
+ * Controls operation of the DMA IN/OUT of the NPI.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_dma_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t b0_lend                 : 1;       /**< When set '1' and the NPI is in the mode to write
+                                                         0 to L2C memory when a DMA is done, the address
+                                                         to be written to will be treated as a Little
+                                                         Endian address. This field is new to PASS-2. */
+        uint64_t dwb_denb                : 1;       /**< When set '1' the NPI will send a value in the DWB
+                                                         field for a free page operation for the memory
+                                                         that contained the data in N3. */
+        uint64_t dwb_ichk                : 9;       /**< When Instruction Chunks for DMA operations are freed
+                                                         this value is used for the DWB field of the
+                                                         operation. */
+        uint64_t fpa_que                 : 3;       /**< The FPA queue that the instruction-chunk page will
+                                                         be returned to when used. */
+        uint64_t o_add1                  : 1;       /**< When set '1' 1 will be added to the DMA counters,
+                                                         if '0' then the number of bytes in the dma transfer
+                                                         will be added to the count register. */
+        uint64_t o_ro                    : 1;       /**< Relaxed Ordering Mode for DMA. */
+        uint64_t o_ns                    : 1;       /**< Nosnoop For DMA. */
+        uint64_t o_es                    : 2;       /**< Endian Swap Mode for DMA. */
+        uint64_t o_mode                  : 1;       /**< Select PCI_POINTER MODE to be used.
+                                                         '1' use pointer values for address and register
+                                                         values for RO, ES, and NS, '0' use register
+                                                         values for address and pointer values for
+                                                         RO, ES, and NS. */
+        uint64_t hp_enb                  : 1;       /**< Enables the High Priority DMA.
+                                                         While this bit is disabled '0' then the value
+                                                         in the NPI_HIGHP_IBUFF_SADDR is re-loaded to the
+                                                         starting address of the High Priority DMA engine.
+                                                         CSIZE field will be reloaded, for the High Priority
+                                                         DMA Engine. */
+        uint64_t lp_enb                  : 1;       /**< Enables the Low Priority DMA.
+                                                         While this bit is disabled '0' then the value
+                                                         in the NPI_LOWP_IBUFF_SADDR is re-loaded to the
+                                                         starting address of the Low Priority DMA engine.
+                                                         PASS-2: When this bit is '0' the value in the
+                                                         CSIZE field will be reloaded, for the Low Priority
+                                                         DMA Engine. */
+        uint64_t csize                   : 14;      /**< The size in words of the DMA Instruction Chunk.
+                                                         This value should only be written once. After
+                                                         writing this value a new value will not be
+                                                         recognized until the end of the DMA I-Chunk is
+                                                         reached. */
+#else
+        uint64_t csize                   : 14;
+        uint64_t lp_enb                  : 1;
+        uint64_t hp_enb                  : 1;
+        uint64_t o_mode                  : 1;
+        uint64_t o_es                    : 2;
+        uint64_t o_ns                    : 1;
+        uint64_t o_ro                    : 1;
+        uint64_t o_add1                  : 1;
+        uint64_t fpa_que                 : 3;
+        uint64_t dwb_ichk                : 9;
+        uint64_t dwb_denb                : 1;
+        uint64_t b0_lend                 : 1;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_npi_dma_control_s        cn30xx;
+    struct cvmx_npi_dma_control_s        cn31xx;
+    struct cvmx_npi_dma_control_s        cn38xx;
+    struct cvmx_npi_dma_control_s        cn38xxp2;
+    struct cvmx_npi_dma_control_s        cn50xx;
+    struct cvmx_npi_dma_control_s        cn58xx;
+    struct cvmx_npi_dma_control_s        cn58xxp1;
+} cvmx_npi_dma_control_t;
+
+
+/**
+ * cvmx_npi_dma_highp_counts
+ *
+ * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts
+ * 
+ * Values for determing the number of instructions for High Priority DMA in the NPI.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_dma_highp_counts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t fcnt                    : 7;       /**< Number of words in the Instruction FIFO. */
+        uint64_t dbell                   : 32;      /**< Number of available words of Instructions to read. */
+#else
+        uint64_t dbell                   : 32;
+        uint64_t fcnt                    : 7;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } s;
+    struct cvmx_npi_dma_highp_counts_s   cn30xx;
+    struct cvmx_npi_dma_highp_counts_s   cn31xx;
+    struct cvmx_npi_dma_highp_counts_s   cn38xx;
+    struct cvmx_npi_dma_highp_counts_s   cn38xxp2;
+    struct cvmx_npi_dma_highp_counts_s   cn50xx;
+    struct cvmx_npi_dma_highp_counts_s   cn58xx;
+    struct cvmx_npi_dma_highp_counts_s   cn58xxp1;
+} cvmx_npi_dma_highp_counts_t;
+
+
+/**
+ * cvmx_npi_dma_highp_naddr
+ *
+ * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address
+ * 
+ * Place NPI will read the next Ichunk data from. This is valid when state is 0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_dma_highp_naddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t state                   : 4;       /**< The DMA instruction engine state vector.
+                                                         Typical value is 0 (IDLE). */
+        uint64_t addr                    : 36;      /**< The next L2C address to read DMA instructions
+                                                         from for the High Priority DMA engine. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t state                   : 4;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_npi_dma_highp_naddr_s    cn30xx;
+    struct cvmx_npi_dma_highp_naddr_s    cn31xx;
+    struct cvmx_npi_dma_highp_naddr_s    cn38xx;
+    struct cvmx_npi_dma_highp_naddr_s    cn38xxp2;
+    struct cvmx_npi_dma_highp_naddr_s    cn50xx;
+    struct cvmx_npi_dma_highp_naddr_s    cn58xx;
+    struct cvmx_npi_dma_highp_naddr_s    cn58xxp1;
+} cvmx_npi_dma_highp_naddr_t;
+
+
+/**
+ * cvmx_npi_dma_lowp_counts
+ *
+ * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts
+ * 
+ * Values for determing the number of instructions for Low Priority DMA in the NPI.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_dma_lowp_counts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_39_63          : 25;
+        uint64_t fcnt                    : 7;       /**< Number of words in the Instruction FIFO. */
+        uint64_t dbell                   : 32;      /**< Number of available words of Instructions to read. */
+#else
+        uint64_t dbell                   : 32;
+        uint64_t fcnt                    : 7;
+        uint64_t reserved_39_63          : 25;
+#endif
+    } s;
+    struct cvmx_npi_dma_lowp_counts_s    cn30xx;
+    struct cvmx_npi_dma_lowp_counts_s    cn31xx;
+    struct cvmx_npi_dma_lowp_counts_s    cn38xx;
+    struct cvmx_npi_dma_lowp_counts_s    cn38xxp2;
+    struct cvmx_npi_dma_lowp_counts_s    cn50xx;
+    struct cvmx_npi_dma_lowp_counts_s    cn58xx;
+    struct cvmx_npi_dma_lowp_counts_s    cn58xxp1;
+} cvmx_npi_dma_lowp_counts_t;
+
+
+/**
+ * cvmx_npi_dma_lowp_naddr
+ *
+ * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address
+ * 
+ * Place NPI will read the next Ichunk data from. This is valid when state is 0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_dma_lowp_naddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t state                   : 4;       /**< The DMA instruction engine state vector.
+                                                         Typical value is 0 (IDLE). */
+        uint64_t addr                    : 36;      /**< The next L2C address to read DMA instructions
+                                                         from for the Low Priority DMA engine. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t state                   : 4;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_npi_dma_lowp_naddr_s     cn30xx;
+    struct cvmx_npi_dma_lowp_naddr_s     cn31xx;
+    struct cvmx_npi_dma_lowp_naddr_s     cn38xx;
+    struct cvmx_npi_dma_lowp_naddr_s     cn38xxp2;
+    struct cvmx_npi_dma_lowp_naddr_s     cn50xx;
+    struct cvmx_npi_dma_lowp_naddr_s     cn58xx;
+    struct cvmx_npi_dma_lowp_naddr_s     cn58xxp1;
+} cvmx_npi_dma_lowp_naddr_t;
+
+
+/**
+ * cvmx_npi_highp_dbell
+ *
+ * NPI_HIGHP_DBELL = High Priority Door Bell
+ * 
+ * The door bell register for the high priority DMA queue.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_highp_dbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dbell                   : 16;      /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the high priority dma queue. */
+#else
+        uint64_t dbell                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npi_highp_dbell_s        cn30xx;
+    struct cvmx_npi_highp_dbell_s        cn31xx;
+    struct cvmx_npi_highp_dbell_s        cn38xx;
+    struct cvmx_npi_highp_dbell_s        cn38xxp2;
+    struct cvmx_npi_highp_dbell_s        cn50xx;
+    struct cvmx_npi_highp_dbell_s        cn58xx;
+    struct cvmx_npi_highp_dbell_s        cn58xxp1;
+} cvmx_npi_highp_dbell_t;
+
+
+/**
+ * cvmx_npi_highp_ibuff_saddr
+ *
+ * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address
+ * 
+ * The address to start reading Instructions from for HIGHP.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_highp_ibuff_saddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t saddr                   : 36;      /**< The starting address to read the first instruction. */
+#else
+        uint64_t saddr                   : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn30xx;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn31xx;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn38xx;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn38xxp2;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn50xx;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn58xx;
+    struct cvmx_npi_highp_ibuff_saddr_s  cn58xxp1;
+} cvmx_npi_highp_ibuff_saddr_t;
+
+
+/**
+ * cvmx_npi_input_control
+ *
+ * NPI_INPUT_CONTROL = NPI's Input Control Register
+ * 
+ * Control for reads for gather list and instructions.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_input_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t pkt_rr                  : 1;       /**< When set '1' the input packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the input packet port is fixed in priority,
+                                                         where the lower port number has higher priority.
+                                                         PASS3 Field */
+        uint64_t pbp_dhi                 : 13;      /**< Field when in [PBP] is set to be used in
+                                                         calculating a DPTR. */
+        uint64_t d_nsr                   : 1;       /**< Enables '1' NoSnoop for reading of
+                                                         gather data. */
+        uint64_t d_esr                   : 2;       /**< The Endian-Swap-Mode for reading of
+                                                         gather data. */
+        uint64_t d_ror                   : 1;       /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather data. */
+        uint64_t use_csr                 : 1;       /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+        uint64_t nsr                     : 1;       /**< Enables '1' NoSnoop for reading of
+                                                         gather list and gather instruction. */
+        uint64_t esr                     : 2;       /**< The Endian-Swap-Mode for reading of
+                                                         gather list and gather instruction. */
+        uint64_t ror                     : 1;       /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather list and gather instruction. */
+#else
+        uint64_t ror                     : 1;
+        uint64_t esr                     : 2;
+        uint64_t nsr                     : 1;
+        uint64_t use_csr                 : 1;
+        uint64_t d_ror                   : 1;
+        uint64_t d_esr                   : 2;
+        uint64_t d_nsr                   : 1;
+        uint64_t pbp_dhi                 : 13;
+        uint64_t pkt_rr                  : 1;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_npi_input_control_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_22_63          : 42;
+        uint64_t pbp_dhi                 : 13;      /**< Field when in [PBP] is set to be used in
+                                                         calculating a DPTR. */
+        uint64_t d_nsr                   : 1;       /**< Enables '1' NoSnoop for reading of
+                                                         gather data. */
+        uint64_t d_esr                   : 2;       /**< The Endian-Swap-Mode for reading of
+                                                         gather data. */
+        uint64_t d_ror                   : 1;       /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather data. */
+        uint64_t use_csr                 : 1;       /**< When set '1' the csr value will be used for
+                                                         ROR, ESR, and NSR. When clear '0' the value in
+                                                         DPTR will be used. In turn the bits not used for
+                                                         ROR, ESR, and NSR, will be used for bits [63:60]
+                                                         of the address used to fetch packet data. */
+        uint64_t nsr                     : 1;       /**< Enables '1' NoSnoop for reading of
+                                                         gather list and gather instruction. */
+        uint64_t esr                     : 2;       /**< The Endian-Swap-Mode for reading of
+                                                         gather list and gather instruction. */
+        uint64_t ror                     : 1;       /**< Enables '1' Relaxed Ordering for reading of
+                                                         gather list and gather instruction. */
+#else
+        uint64_t ror                     : 1;
+        uint64_t esr                     : 2;
+        uint64_t nsr                     : 1;
+        uint64_t use_csr                 : 1;
+        uint64_t d_ror                   : 1;
+        uint64_t d_esr                   : 2;
+        uint64_t d_nsr                   : 1;
+        uint64_t pbp_dhi                 : 13;
+        uint64_t reserved_22_63          : 42;
+#endif
+    } cn30xx;
+    struct cvmx_npi_input_control_cn30xx cn31xx;
+    struct cvmx_npi_input_control_s      cn38xx;
+    struct cvmx_npi_input_control_cn30xx cn38xxp2;
+    struct cvmx_npi_input_control_s      cn50xx;
+    struct cvmx_npi_input_control_s      cn58xx;
+    struct cvmx_npi_input_control_s      cn58xxp1;
+} cvmx_npi_input_control_t;
+
+
+/**
+ * cvmx_npi_int_enb
+ *
+ * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register
+ * 
+ * Used to enable the various interrupting conditions of NPI
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t q1_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q1_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pdf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
+                                                         interrupt. */
+        uint64_t pdf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
+                                                         interrupt. */
+        uint64_t pcf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
+                                                         interrupt. */
+        uint64_t pcf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
+                                                         interrupt. */
+        uint64_t rdx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
+                                                         interrupt. */
+        uint64_t rwx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pnc_a_f                 : 1;       /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
+                                                         interrupt. */
+        uint64_t pnc_s_e                 : 1;       /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
+                                                         interrupt. */
+        uint64_t com_a_f                 : 1;       /**< Enables NPI_INT_SUM[COM_A_F] to generate an
+                                                         interrupt. */
+        uint64_t com_s_e                 : 1;       /**< Enables NPI_INT_SUM[COM_S_E] to generate an
+                                                         interrupt. */
+        uint64_t q3_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q3_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
+                                                         interrupt. */
+        uint64_t q2_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q2_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
+                                                         interrupt. */
+        uint64_t pcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
+                                                         interrupt. */
+        uint64_t fcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
+                                                         interrupt. */
+        uint64_t fcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
+                                                         interrupt. */
+        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+        uint64_t i3_pperr                : 1;       /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i2_pperr                : 1;       /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i1_pperr                : 1;       /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p3_ptout                : 1;       /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p2_ptout                : 1;       /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p1_ptout                : 1;       /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p3_pperr                : 1;       /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p2_pperr                : 1;       /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p1_pperr                : 1;       /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t g3_rtout                : 1;       /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g2_rtout                : 1;       /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g1_rtout                : 1;       /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p3_perr                 : 1;       /**< Enables NPI_INT_SUM[P3_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p2_perr                 : 1;       /**< Enables NPI_INT_SUM[P2_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p1_perr                 : 1;       /**< Enables NPI_INT_SUM[P1_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p3_rtout                : 1;       /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p2_rtout                : 1;       /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p1_rtout                : 1;       /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i3_overf                : 1;       /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i2_overf                : 1;       /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i1_overf                : 1;       /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i3_rtout                : 1;       /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i2_rtout                : 1;       /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i1_rtout                : 1;       /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t po3_2sml                : 1;       /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po2_2sml                : 1;       /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po1_2sml                : 1;       /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t po1_2sml                : 1;
+        uint64_t po2_2sml                : 1;
+        uint64_t po3_2sml                : 1;
+        uint64_t i0_rtout                : 1;
+        uint64_t i1_rtout                : 1;
+        uint64_t i2_rtout                : 1;
+        uint64_t i3_rtout                : 1;
+        uint64_t i0_overf                : 1;
+        uint64_t i1_overf                : 1;
+        uint64_t i2_overf                : 1;
+        uint64_t i3_overf                : 1;
+        uint64_t p0_rtout                : 1;
+        uint64_t p1_rtout                : 1;
+        uint64_t p2_rtout                : 1;
+        uint64_t p3_rtout                : 1;
+        uint64_t p0_perr                 : 1;
+        uint64_t p1_perr                 : 1;
+        uint64_t p2_perr                 : 1;
+        uint64_t p3_perr                 : 1;
+        uint64_t g0_rtout                : 1;
+        uint64_t g1_rtout                : 1;
+        uint64_t g2_rtout                : 1;
+        uint64_t g3_rtout                : 1;
+        uint64_t p0_pperr                : 1;
+        uint64_t p1_pperr                : 1;
+        uint64_t p2_pperr                : 1;
+        uint64_t p3_pperr                : 1;
+        uint64_t p0_ptout                : 1;
+        uint64_t p1_ptout                : 1;
+        uint64_t p2_ptout                : 1;
+        uint64_t p3_ptout                : 1;
+        uint64_t i0_pperr                : 1;
+        uint64_t i1_pperr                : 1;
+        uint64_t i2_pperr                : 1;
+        uint64_t i3_pperr                : 1;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t fcr_s_e                 : 1;
+        uint64_t fcr_a_f                 : 1;
+        uint64_t pcr_s_e                 : 1;
+        uint64_t pcr_a_f                 : 1;
+        uint64_t q2_s_e                  : 1;
+        uint64_t q2_a_f                  : 1;
+        uint64_t q3_s_e                  : 1;
+        uint64_t q3_a_f                  : 1;
+        uint64_t com_s_e                 : 1;
+        uint64_t com_a_f                 : 1;
+        uint64_t pnc_s_e                 : 1;
+        uint64_t pnc_a_f                 : 1;
+        uint64_t rwx_s_e                 : 1;
+        uint64_t rdx_s_e                 : 1;
+        uint64_t pcf_p_e                 : 1;
+        uint64_t pcf_p_f                 : 1;
+        uint64_t pdf_p_e                 : 1;
+        uint64_t pdf_p_f                 : 1;
+        uint64_t q1_s_e                  : 1;
+        uint64_t q1_a_f                  : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } s;
+    struct cvmx_npi_int_enb_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t q1_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q1_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pdf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
+                                                         interrupt. */
+        uint64_t pdf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
+                                                         interrupt. */
+        uint64_t pcf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
+                                                         interrupt. */
+        uint64_t pcf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
+                                                         interrupt. */
+        uint64_t rdx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
+                                                         interrupt. */
+        uint64_t rwx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pnc_a_f                 : 1;       /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
+                                                         interrupt. */
+        uint64_t pnc_s_e                 : 1;       /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
+                                                         interrupt. */
+        uint64_t com_a_f                 : 1;       /**< Enables NPI_INT_SUM[COM_A_F] to generate an
+                                                         interrupt. */
+        uint64_t com_s_e                 : 1;       /**< Enables NPI_INT_SUM[COM_S_E] to generate an
+                                                         interrupt. */
+        uint64_t q3_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q3_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
+                                                         interrupt. */
+        uint64_t q2_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q2_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
+                                                         interrupt. */
+        uint64_t pcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
+                                                         interrupt. */
+        uint64_t fcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
+                                                         interrupt. */
+        uint64_t fcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
+                                                         interrupt. */
+        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+        uint64_t reserved_36_38          : 3;
+        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t reserved_32_34          : 3;
+        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_28_30          : 3;
+        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t reserved_24_26          : 3;
+        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_20_22          : 3;
+        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+        uint64_t reserved_16_18          : 3;
+        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_12_14          : 3;
+        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t reserved_8_10           : 3;
+        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_4_6            : 3;
+        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t reserved_4_6            : 3;
+        uint64_t i0_rtout                : 1;
+        uint64_t reserved_8_10           : 3;
+        uint64_t i0_overf                : 1;
+        uint64_t reserved_12_14          : 3;
+        uint64_t p0_rtout                : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t p0_perr                 : 1;
+        uint64_t reserved_20_22          : 3;
+        uint64_t g0_rtout                : 1;
+        uint64_t reserved_24_26          : 3;
+        uint64_t p0_pperr                : 1;
+        uint64_t reserved_28_30          : 3;
+        uint64_t p0_ptout                : 1;
+        uint64_t reserved_32_34          : 3;
+        uint64_t i0_pperr                : 1;
+        uint64_t reserved_36_38          : 3;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t fcr_s_e                 : 1;
+        uint64_t fcr_a_f                 : 1;
+        uint64_t pcr_s_e                 : 1;
+        uint64_t pcr_a_f                 : 1;
+        uint64_t q2_s_e                  : 1;
+        uint64_t q2_a_f                  : 1;
+        uint64_t q3_s_e                  : 1;
+        uint64_t q3_a_f                  : 1;
+        uint64_t com_s_e                 : 1;
+        uint64_t com_a_f                 : 1;
+        uint64_t pnc_s_e                 : 1;
+        uint64_t pnc_a_f                 : 1;
+        uint64_t rwx_s_e                 : 1;
+        uint64_t rdx_s_e                 : 1;
+        uint64_t pcf_p_e                 : 1;
+        uint64_t pcf_p_f                 : 1;
+        uint64_t pdf_p_e                 : 1;
+        uint64_t pdf_p_f                 : 1;
+        uint64_t q1_s_e                  : 1;
+        uint64_t q1_a_f                  : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } cn30xx;
+    struct cvmx_npi_int_enb_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t q1_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q1_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q1_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q1_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pdf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_F] to generate an
+                                                         interrupt. */
+        uint64_t pdf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PDF_P_E] to generate an
+                                                         interrupt. */
+        uint64_t pcf_p_f                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_F] to generate an
+                                                         interrupt. */
+        uint64_t pcf_p_e                 : 1;       /**< Enables NPI_INT_SUM[PCF_P_E] to generate an
+                                                         interrupt. */
+        uint64_t rdx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RDX_S_E] to generate an
+                                                         interrupt. */
+        uint64_t rwx_s_e                 : 1;       /**< Enables NPI_INT_SUM[RWX_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pnc_a_f                 : 1;       /**< Enables NPI_INT_SUM[PNC_A_F] to generate an
+                                                         interrupt. */
+        uint64_t pnc_s_e                 : 1;       /**< Enables NPI_INT_SUM[PNC_S_E] to generate an
+                                                         interrupt. */
+        uint64_t com_a_f                 : 1;       /**< Enables NPI_INT_SUM[COM_A_F] to generate an
+                                                         interrupt. */
+        uint64_t com_s_e                 : 1;       /**< Enables NPI_INT_SUM[COM_S_E] to generate an
+                                                         interrupt. */
+        uint64_t q3_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q3_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q3_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q3_S_E] to generate an
+                                                         interrupt. */
+        uint64_t q2_a_f                  : 1;       /**< Enables NPI_INT_SUM[Q2_A_F] to generate an
+                                                         interrupt. */
+        uint64_t q2_s_e                  : 1;       /**< Enables NPI_INT_SUM[Q2_S_E] to generate an
+                                                         interrupt. */
+        uint64_t pcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[PCR_A_F] to generate an
+                                                         interrupt. */
+        uint64_t pcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[PCR_S_E] to generate an
+                                                         interrupt. */
+        uint64_t fcr_a_f                 : 1;       /**< Enables NPI_INT_SUM[FCR_A_F] to generate an
+                                                         interrupt. */
+        uint64_t fcr_s_e                 : 1;       /**< Enables NPI_INT_SUM[FCR_S_E] to generate an
+                                                         interrupt. */
+        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+        uint64_t reserved_37_38          : 2;
+        uint64_t i1_pperr                : 1;       /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t reserved_33_34          : 2;
+        uint64_t p1_ptout                : 1;       /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_29_30          : 2;
+        uint64_t p1_pperr                : 1;       /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t reserved_25_26          : 2;
+        uint64_t g1_rtout                : 1;       /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_21_22          : 2;
+        uint64_t p1_perr                 : 1;       /**< Enables NPI_INT_SUM[P1_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+        uint64_t reserved_17_18          : 2;
+        uint64_t p1_rtout                : 1;       /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_13_14          : 2;
+        uint64_t i1_overf                : 1;       /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t reserved_9_10           : 2;
+        uint64_t i1_rtout                : 1;       /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t reserved_5_6            : 2;
+        uint64_t po1_2sml                : 1;       /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t po1_2sml                : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t i0_rtout                : 1;
+        uint64_t i1_rtout                : 1;
+        uint64_t reserved_9_10           : 2;
+        uint64_t i0_overf                : 1;
+        uint64_t i1_overf                : 1;
+        uint64_t reserved_13_14          : 2;
+        uint64_t p0_rtout                : 1;
+        uint64_t p1_rtout                : 1;
+        uint64_t reserved_17_18          : 2;
+        uint64_t p0_perr                 : 1;
+        uint64_t p1_perr                 : 1;
+        uint64_t reserved_21_22          : 2;
+        uint64_t g0_rtout                : 1;
+        uint64_t g1_rtout                : 1;
+        uint64_t reserved_25_26          : 2;
+        uint64_t p0_pperr                : 1;
+        uint64_t p1_pperr                : 1;
+        uint64_t reserved_29_30          : 2;
+        uint64_t p0_ptout                : 1;
+        uint64_t p1_ptout                : 1;
+        uint64_t reserved_33_34          : 2;
+        uint64_t i0_pperr                : 1;
+        uint64_t i1_pperr                : 1;
+        uint64_t reserved_37_38          : 2;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t fcr_s_e                 : 1;
+        uint64_t fcr_a_f                 : 1;
+        uint64_t pcr_s_e                 : 1;
+        uint64_t pcr_a_f                 : 1;
+        uint64_t q2_s_e                  : 1;
+        uint64_t q2_a_f                  : 1;
+        uint64_t q3_s_e                  : 1;
+        uint64_t q3_a_f                  : 1;
+        uint64_t com_s_e                 : 1;
+        uint64_t com_a_f                 : 1;
+        uint64_t pnc_s_e                 : 1;
+        uint64_t pnc_a_f                 : 1;
+        uint64_t rwx_s_e                 : 1;
+        uint64_t rdx_s_e                 : 1;
+        uint64_t pcf_p_e                 : 1;
+        uint64_t pcf_p_f                 : 1;
+        uint64_t pdf_p_e                 : 1;
+        uint64_t pdf_p_f                 : 1;
+        uint64_t q1_s_e                  : 1;
+        uint64_t q1_a_f                  : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } cn31xx;
+    struct cvmx_npi_int_enb_s            cn38xx;
+    struct cvmx_npi_int_enb_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_42_63          : 22;
+        uint64_t iobdma                  : 1;       /**< Enables NPI_INT_SUM[IOBDMA] to generate an
+                                                         interrupt. */
+        uint64_t p_dperr                 : 1;       /**< Enables NPI_INT_SUM[P_DPERR] to generate an
+                                                         interrupt. */
+        uint64_t win_rto                 : 1;       /**< Enables NPI_INT_SUM[WIN_RTO] to generate an
+                                                         interrupt. */
+        uint64_t i3_pperr                : 1;       /**< Enables NPI_INT_SUM[I3_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i2_pperr                : 1;       /**< Enables NPI_INT_SUM[I2_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i1_pperr                : 1;       /**< Enables NPI_INT_SUM[I1_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t i0_pperr                : 1;       /**< Enables NPI_INT_SUM[I0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p3_ptout                : 1;       /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p2_ptout                : 1;       /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p1_ptout                : 1;       /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p0_ptout                : 1;       /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p3_pperr                : 1;       /**< Enables NPI_INT_SUM[P3_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p2_pperr                : 1;       /**< Enables NPI_INT_SUM[P2_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p1_pperr                : 1;       /**< Enables NPI_INT_SUM[P1_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t p0_pperr                : 1;       /**< Enables NPI_INT_SUM[P0_PPERR] to generate an
+                                                         interrupt. */
+        uint64_t g3_rtout                : 1;       /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g2_rtout                : 1;       /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g1_rtout                : 1;       /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t g0_rtout                : 1;       /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p3_perr                 : 1;       /**< Enables NPI_INT_SUM[P3_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p2_perr                 : 1;       /**< Enables NPI_INT_SUM[P2_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p1_perr                 : 1;       /**< Enables NPI_INT_SUM[P1_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p0_perr                 : 1;       /**< Enables NPI_INT_SUM[P0_PERR] to generate an
+                                                         interrupt. */
+        uint64_t p3_rtout                : 1;       /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p2_rtout                : 1;       /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p1_rtout                : 1;       /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t p0_rtout                : 1;       /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i3_overf                : 1;       /**< Enables NPI_INT_SUM[I3_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i2_overf                : 1;       /**< Enables NPI_INT_SUM[I2_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i1_overf                : 1;       /**< Enables NPI_INT_SUM[I1_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i0_overf                : 1;       /**< Enables NPI_INT_SUM[I0_OVERF] to generate an
+                                                         interrupt. */
+        uint64_t i3_rtout                : 1;       /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i2_rtout                : 1;       /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i1_rtout                : 1;       /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t i0_rtout                : 1;       /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an
+                                                         interrupt. */
+        uint64_t po3_2sml                : 1;       /**< Enables NPI_INT_SUM[PO3_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po2_2sml                : 1;       /**< Enables NPI_INT_SUM[PO2_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po1_2sml                : 1;       /**< Enables NPI_INT_SUM[PO1_2SML] to generate an
+                                                         interrupt. */
+        uint64_t po0_2sml                : 1;       /**< Enables NPI_INT_SUM[PO0_2SML] to generate an
+                                                         interrupt. */
+        uint64_t pci_rsl                 : 1;       /**< Enables NPI_INT_SUM[PCI_RSL] to generate an
+                                                         interrupt. */
+        uint64_t rml_wto                 : 1;       /**< Enables NPI_INT_SUM[RML_WTO] to generate an
+                                                         interrupt. */
+        uint64_t rml_rto                 : 1;       /**< Enables NPI_INT_SUM[RML_RTO] to generate an
+                                                         interrupt. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t po1_2sml                : 1;
+        uint64_t po2_2sml                : 1;
+        uint64_t po3_2sml                : 1;
+        uint64_t i0_rtout                : 1;
+        uint64_t i1_rtout                : 1;
+        uint64_t i2_rtout                : 1;
+        uint64_t i3_rtout                : 1;
+        uint64_t i0_overf                : 1;
+        uint64_t i1_overf                : 1;
+        uint64_t i2_overf                : 1;
+        uint64_t i3_overf                : 1;
+        uint64_t p0_rtout                : 1;
+        uint64_t p1_rtout                : 1;
+        uint64_t p2_rtout                : 1;
+        uint64_t p3_rtout                : 1;
+        uint64_t p0_perr                 : 1;
+        uint64_t p1_perr                 : 1;
+        uint64_t p2_perr                 : 1;
+        uint64_t p3_perr                 : 1;
+        uint64_t g0_rtout                : 1;
+        uint64_t g1_rtout                : 1;
+        uint64_t g2_rtout                : 1;
+        uint64_t g3_rtout                : 1;
+        uint64_t p0_pperr                : 1;
+        uint64_t p1_pperr                : 1;
+        uint64_t p2_pperr                : 1;
+        uint64_t p3_pperr                : 1;
+        uint64_t p0_ptout                : 1;
+        uint64_t p1_ptout                : 1;
+        uint64_t p2_ptout                : 1;
+        uint64_t p3_ptout                : 1;
+        uint64_t i0_pperr                : 1;
+        uint64_t i1_pperr                : 1;
+        uint64_t i2_pperr                : 1;
+        uint64_t i3_pperr                : 1;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t reserved_42_63          : 22;
+#endif
+    } cn38xxp2;
+    struct cvmx_npi_int_enb_cn31xx       cn50xx;
+    struct cvmx_npi_int_enb_s            cn58xx;
+    struct cvmx_npi_int_enb_s            cn58xxp1;
+} cvmx_npi_int_enb_t;
+
+
+/**
+ * cvmx_npi_int_sum
+ *
+ * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register
+ * 
+ * Set when an interrupt condition occurs, write '1' to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t q1_a_f                  : 1;       /**< Attempted to add when Queue-1 FIFO is full.
+                                                         PASS3 Field. */
+        uint64_t q1_s_e                  : 1;       /**< Attempted to subtract when Queue-1 FIFO is empty.
+                                                         PASS3 Field. */
+        uint64_t pdf_p_f                 : 1;       /**< Attempted to push a full PCN-DATA-FIFO.
+                                                         PASS3 Field. */
+        uint64_t pdf_p_e                 : 1;       /**< Attempted to pop an empty PCN-DATA-FIFO.
+                                                         PASS3 Field. */
+        uint64_t pcf_p_f                 : 1;       /**< Attempted to push a full PCN-CNT-FIFO.
+                                                         PASS3 Field. */
+        uint64_t pcf_p_e                 : 1;       /**< Attempted to pop an empty PCN-CNT-FIFO.
+                                                         PASS3 Field. */
+        uint64_t rdx_s_e                 : 1;       /**< Attempted to subtract when DPI-XFR-Wait count is 0.
+                                                         PASS3 Field. */
+        uint64_t rwx_s_e                 : 1;       /**< Attempted to subtract when RDN-XFR-Wait count is 0.
+                                                         PASS3 Field. */
+        uint64_t pnc_a_f                 : 1;       /**< Attempted to add when PNI-NPI Credits are max.
+                                                         PASS3 Field. */
+        uint64_t pnc_s_e                 : 1;       /**< Attempted to subtract when PNI-NPI Credits are 0.
+                                                         PASS3 Field. */
+        uint64_t com_a_f                 : 1;       /**< Attempted to add when PCN-Commit Counter is max.
+                                                         PASS3 Field. */
+        uint64_t com_s_e                 : 1;       /**< Attempted to subtract when PCN-Commit Counter is 0.
+                                                         PASS3 Field. */
+        uint64_t q3_a_f                  : 1;       /**< Attempted to add when Queue-3 FIFO is full.
+                                                         PASS3 Field. */
+        uint64_t q3_s_e                  : 1;       /**< Attempted to subtract when Queue-3 FIFO is empty.
+                                                         PASS3 Field. */
+        uint64_t q2_a_f                  : 1;       /**< Attempted to add when Queue-2 FIFO is full.
+                                                         PASS3 Field. */
+        uint64_t q2_s_e                  : 1;       /**< Attempted to subtract when Queue-2 FIFO is empty.
+                                                         PASS3 Field. */
+        uint64_t pcr_a_f                 : 1;       /**< Attempted to add when POW Credits is full.
+                                                         PASS3 Field. */
+        uint64_t pcr_s_e                 : 1;       /**< Attempted to subtract when POW Credits is empty.
+                                                         PASS3 Field. */
+        uint64_t fcr_a_f                 : 1;       /**< Attempted to add when FPA Credits is full.
+                                                         PASS3 Field. */
+        uint64_t fcr_s_e                 : 1;       /**< Attempted to subtract when FPA Credits is empty.
+                                                         PASS3 Field. */
+        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
+        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
+        uint64_t i3_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i2_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i1_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t p3_ptout                : 1;       /**< Port-3 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p2_ptout                : 1;       /**< Port-2 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p1_ptout                : 1;       /**< Port-1 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p3_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p2_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p1_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t g3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t p3_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p2_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p1_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t i3_overf                : 1;       /**< Port-3 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i2_overf                : 1;       /**< Port-2 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i1_overf                : 1;       /**< Port-1 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t po3_2sml                : 1;       /**< The packet being sent out on Port3 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
+        uint64_t po2_2sml                : 1;       /**< The packet being sent out on Port2 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
+        uint64_t po1_2sml                : 1;       /**< The packet being sent out on Port1 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
+        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t po1_2sml                : 1;
+        uint64_t po2_2sml                : 1;
+        uint64_t po3_2sml                : 1;
+        uint64_t i0_rtout                : 1;
+        uint64_t i1_rtout                : 1;
+        uint64_t i2_rtout                : 1;
+        uint64_t i3_rtout                : 1;
+        uint64_t i0_overf                : 1;
+        uint64_t i1_overf                : 1;
+        uint64_t i2_overf                : 1;
+        uint64_t i3_overf                : 1;
+        uint64_t p0_rtout                : 1;
+        uint64_t p1_rtout                : 1;
+        uint64_t p2_rtout                : 1;
+        uint64_t p3_rtout                : 1;
+        uint64_t p0_perr                 : 1;
+        uint64_t p1_perr                 : 1;
+        uint64_t p2_perr                 : 1;
+        uint64_t p3_perr                 : 1;
+        uint64_t g0_rtout                : 1;
+        uint64_t g1_rtout                : 1;
+        uint64_t g2_rtout                : 1;
+        uint64_t g3_rtout                : 1;
+        uint64_t p0_pperr                : 1;
+        uint64_t p1_pperr                : 1;
+        uint64_t p2_pperr                : 1;
+        uint64_t p3_pperr                : 1;
+        uint64_t p0_ptout                : 1;
+        uint64_t p1_ptout                : 1;
+        uint64_t p2_ptout                : 1;
+        uint64_t p3_ptout                : 1;
+        uint64_t i0_pperr                : 1;
+        uint64_t i1_pperr                : 1;
+        uint64_t i2_pperr                : 1;
+        uint64_t i3_pperr                : 1;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t fcr_s_e                 : 1;
+        uint64_t fcr_a_f                 : 1;
+        uint64_t pcr_s_e                 : 1;
+        uint64_t pcr_a_f                 : 1;
+        uint64_t q2_s_e                  : 1;
+        uint64_t q2_a_f                  : 1;
+        uint64_t q3_s_e                  : 1;
+        uint64_t q3_a_f                  : 1;
+        uint64_t com_s_e                 : 1;
+        uint64_t com_a_f                 : 1;
+        uint64_t pnc_s_e                 : 1;
+        uint64_t pnc_a_f                 : 1;
+        uint64_t rwx_s_e                 : 1;
+        uint64_t rdx_s_e                 : 1;
+        uint64_t pcf_p_e                 : 1;
+        uint64_t pcf_p_f                 : 1;
+        uint64_t pdf_p_e                 : 1;
+        uint64_t pdf_p_f                 : 1;
+        uint64_t q1_s_e                  : 1;
+        uint64_t q1_a_f                  : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } s;
+    struct cvmx_npi_int_sum_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t q1_a_f                  : 1;       /**< Attempted to add when Queue-1 FIFO is full. */
+        uint64_t q1_s_e                  : 1;       /**< Attempted to subtract when Queue-1 FIFO is empty. */
+        uint64_t pdf_p_f                 : 1;       /**< Attempted to push a full PCN-DATA-FIFO. */
+        uint64_t pdf_p_e                 : 1;       /**< Attempted to pop an empty PCN-DATA-FIFO. */
+        uint64_t pcf_p_f                 : 1;       /**< Attempted to push a full PCN-CNT-FIFO. */
+        uint64_t pcf_p_e                 : 1;       /**< Attempted to pop an empty PCN-CNT-FIFO. */
+        uint64_t rdx_s_e                 : 1;       /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
+        uint64_t rwx_s_e                 : 1;       /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
+        uint64_t pnc_a_f                 : 1;       /**< Attempted to add when PNI-NPI Credits are max. */
+        uint64_t pnc_s_e                 : 1;       /**< Attempted to subtract when PNI-NPI Credits are 0. */
+        uint64_t com_a_f                 : 1;       /**< Attempted to add when PCN-Commit Counter is max. */
+        uint64_t com_s_e                 : 1;       /**< Attempted to subtract when PCN-Commit Counter is 0. */
+        uint64_t q3_a_f                  : 1;       /**< Attempted to add when Queue-3 FIFO is full. */
+        uint64_t q3_s_e                  : 1;       /**< Attempted to subtract when Queue-3 FIFO is empty. */
+        uint64_t q2_a_f                  : 1;       /**< Attempted to add when Queue-2 FIFO is full. */
+        uint64_t q2_s_e                  : 1;       /**< Attempted to subtract when Queue-2 FIFO is empty. */
+        uint64_t pcr_a_f                 : 1;       /**< Attempted to add when POW Credits is full. */
+        uint64_t pcr_s_e                 : 1;       /**< Attempted to subtract when POW Credits is empty. */
+        uint64_t fcr_a_f                 : 1;       /**< Attempted to add when FPA Credits is full. */
+        uint64_t fcr_s_e                 : 1;       /**< Attempted to subtract when FPA Credits is empty. */
+        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
+        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
+        uint64_t reserved_36_38          : 3;
+        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t reserved_32_34          : 3;
+        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t reserved_28_30          : 3;
+        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t reserved_24_26          : 3;
+        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t reserved_20_22          : 3;
+        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t reserved_16_18          : 3;
+        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t reserved_12_14          : 3;
+        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t reserved_8_10           : 3;
+        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t reserved_4_6            : 3;
+        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t reserved_4_6            : 3;
+        uint64_t i0_rtout                : 1;
+        uint64_t reserved_8_10           : 3;
+        uint64_t i0_overf                : 1;
+        uint64_t reserved_12_14          : 3;
+        uint64_t p0_rtout                : 1;
+        uint64_t reserved_16_18          : 3;
+        uint64_t p0_perr                 : 1;
+        uint64_t reserved_20_22          : 3;
+        uint64_t g0_rtout                : 1;
+        uint64_t reserved_24_26          : 3;
+        uint64_t p0_pperr                : 1;
+        uint64_t reserved_28_30          : 3;
+        uint64_t p0_ptout                : 1;
+        uint64_t reserved_32_34          : 3;
+        uint64_t i0_pperr                : 1;
+        uint64_t reserved_36_38          : 3;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t fcr_s_e                 : 1;
+        uint64_t fcr_a_f                 : 1;
+        uint64_t pcr_s_e                 : 1;
+        uint64_t pcr_a_f                 : 1;
+        uint64_t q2_s_e                  : 1;
+        uint64_t q2_a_f                  : 1;
+        uint64_t q3_s_e                  : 1;
+        uint64_t q3_a_f                  : 1;
+        uint64_t com_s_e                 : 1;
+        uint64_t com_a_f                 : 1;
+        uint64_t pnc_s_e                 : 1;
+        uint64_t pnc_a_f                 : 1;
+        uint64_t rwx_s_e                 : 1;
+        uint64_t rdx_s_e                 : 1;
+        uint64_t pcf_p_e                 : 1;
+        uint64_t pcf_p_f                 : 1;
+        uint64_t pdf_p_e                 : 1;
+        uint64_t pdf_p_f                 : 1;
+        uint64_t q1_s_e                  : 1;
+        uint64_t q1_a_f                  : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } cn30xx;
+    struct cvmx_npi_int_sum_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t q1_a_f                  : 1;       /**< Attempted to add when Queue-1 FIFO is full. */
+        uint64_t q1_s_e                  : 1;       /**< Attempted to subtract when Queue-1 FIFO is empty. */
+        uint64_t pdf_p_f                 : 1;       /**< Attempted to push a full PCN-DATA-FIFO. */
+        uint64_t pdf_p_e                 : 1;       /**< Attempted to pop an empty PCN-DATA-FIFO. */
+        uint64_t pcf_p_f                 : 1;       /**< Attempted to push a full PCN-CNT-FIFO. */
+        uint64_t pcf_p_e                 : 1;       /**< Attempted to pop an empty PCN-CNT-FIFO. */
+        uint64_t rdx_s_e                 : 1;       /**< Attempted to subtract when DPI-XFR-Wait count is 0. */
+        uint64_t rwx_s_e                 : 1;       /**< Attempted to subtract when RDN-XFR-Wait count is 0. */
+        uint64_t pnc_a_f                 : 1;       /**< Attempted to add when PNI-NPI Credits are max. */
+        uint64_t pnc_s_e                 : 1;       /**< Attempted to subtract when PNI-NPI Credits are 0. */
+        uint64_t com_a_f                 : 1;       /**< Attempted to add when PCN-Commit Counter is max. */
+        uint64_t com_s_e                 : 1;       /**< Attempted to subtract when PCN-Commit Counter is 0. */
+        uint64_t q3_a_f                  : 1;       /**< Attempted to add when Queue-3 FIFO is full. */
+        uint64_t q3_s_e                  : 1;       /**< Attempted to subtract when Queue-3 FIFO is empty. */
+        uint64_t q2_a_f                  : 1;       /**< Attempted to add when Queue-2 FIFO is full. */
+        uint64_t q2_s_e                  : 1;       /**< Attempted to subtract when Queue-2 FIFO is empty. */
+        uint64_t pcr_a_f                 : 1;       /**< Attempted to add when POW Credits is full. */
+        uint64_t pcr_s_e                 : 1;       /**< Attempted to subtract when POW Credits is empty. */
+        uint64_t fcr_a_f                 : 1;       /**< Attempted to add when FPA Credits is full. */
+        uint64_t fcr_s_e                 : 1;       /**< Attempted to subtract when FPA Credits is empty. */
+        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
+        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
+        uint64_t reserved_37_38          : 2;
+        uint64_t i1_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t reserved_33_34          : 2;
+        uint64_t p1_ptout                : 1;       /**< Port-1 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t reserved_29_30          : 2;
+        uint64_t p1_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t reserved_25_26          : 2;
+        uint64_t g1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t reserved_21_22          : 2;
+        uint64_t p1_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t reserved_17_18          : 2;
+        uint64_t p1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t reserved_13_14          : 2;
+        uint64_t i1_overf                : 1;       /**< Port-1 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t reserved_9_10           : 2;
+        uint64_t i1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t reserved_5_6            : 2;
+        uint64_t po1_2sml                : 1;       /**< The packet being sent out on Port1 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
+        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t po1_2sml                : 1;
+        uint64_t reserved_5_6            : 2;
+        uint64_t i0_rtout                : 1;
+        uint64_t i1_rtout                : 1;
+        uint64_t reserved_9_10           : 2;
+        uint64_t i0_overf                : 1;
+        uint64_t i1_overf                : 1;
+        uint64_t reserved_13_14          : 2;
+        uint64_t p0_rtout                : 1;
+        uint64_t p1_rtout                : 1;
+        uint64_t reserved_17_18          : 2;
+        uint64_t p0_perr                 : 1;
+        uint64_t p1_perr                 : 1;
+        uint64_t reserved_21_22          : 2;
+        uint64_t g0_rtout                : 1;
+        uint64_t g1_rtout                : 1;
+        uint64_t reserved_25_26          : 2;
+        uint64_t p0_pperr                : 1;
+        uint64_t p1_pperr                : 1;
+        uint64_t reserved_29_30          : 2;
+        uint64_t p0_ptout                : 1;
+        uint64_t p1_ptout                : 1;
+        uint64_t reserved_33_34          : 2;
+        uint64_t i0_pperr                : 1;
+        uint64_t i1_pperr                : 1;
+        uint64_t reserved_37_38          : 2;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t fcr_s_e                 : 1;
+        uint64_t fcr_a_f                 : 1;
+        uint64_t pcr_s_e                 : 1;
+        uint64_t pcr_a_f                 : 1;
+        uint64_t q2_s_e                  : 1;
+        uint64_t q2_a_f                  : 1;
+        uint64_t q3_s_e                  : 1;
+        uint64_t q3_a_f                  : 1;
+        uint64_t com_s_e                 : 1;
+        uint64_t com_a_f                 : 1;
+        uint64_t pnc_s_e                 : 1;
+        uint64_t pnc_a_f                 : 1;
+        uint64_t rwx_s_e                 : 1;
+        uint64_t rdx_s_e                 : 1;
+        uint64_t pcf_p_e                 : 1;
+        uint64_t pcf_p_f                 : 1;
+        uint64_t pdf_p_e                 : 1;
+        uint64_t pdf_p_f                 : 1;
+        uint64_t q1_s_e                  : 1;
+        uint64_t q1_a_f                  : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } cn31xx;
+    struct cvmx_npi_int_sum_s            cn38xx;
+    struct cvmx_npi_int_sum_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_42_63          : 22;
+        uint64_t iobdma                  : 1;       /**< Requested IOBDMA read size exceeded 128 words. */
+        uint64_t p_dperr                 : 1;       /**< If a parity error occured on data written to L2C
+                                                         from the PCI this bit may be set. */
+        uint64_t win_rto                 : 1;       /**< Windowed Load Timed Out. */
+        uint64_t i3_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i2_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i1_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t i0_pperr                : 1;       /**< If a parity error occured on the port's instruction
+                                                         this bit may be set. */
+        uint64_t p3_ptout                : 1;       /**< Port-3 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p2_ptout                : 1;       /**< Port-2 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p1_ptout                : 1;       /**< Port-1 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p0_ptout                : 1;       /**< Port-0 output had a read timeout on a DATA/INFO
+                                                         pair. */
+        uint64_t p3_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p2_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p1_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t p0_pperr                : 1;       /**< If a parity error occured on the port DATA/INFO
+                                                         pointer-pair, this bit may be set. */
+        uint64_t g3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t g0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read a gather list. */
+        uint64_t p3_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p2_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p1_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p0_perr                 : 1;       /**< If a parity error occured on the port's packet
+                                                         data this bit may be set. */
+        uint64_t p3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t p0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read packet data. */
+        uint64_t i3_overf                : 1;       /**< Port-3 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i2_overf                : 1;       /**< Port-2 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i1_overf                : 1;       /**< Port-1 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i0_overf                : 1;       /**< Port-0 had a doorbell overflow. Bit[31] of the
+                                                         doorbell count was set. */
+        uint64_t i3_rtout                : 1;       /**< Port-3 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i2_rtout                : 1;       /**< Port-2 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i1_rtout                : 1;       /**< Port-1 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t i0_rtout                : 1;       /**< Port-0 had a read timeout while attempting to
+                                                         read instructions. */
+        uint64_t po3_2sml                : 1;       /**< The packet being sent out on Port3 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */
+        uint64_t po2_2sml                : 1;       /**< The packet being sent out on Port2 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */
+        uint64_t po1_2sml                : 1;       /**< The packet being sent out on Port1 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */
+        uint64_t po0_2sml                : 1;       /**< The packet being sent out on Port0 is smaller
+                                                         than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */
+        uint64_t pci_rsl                 : 1;       /**< This '1' when a bit in PCI_INT_SUM2 is SET and the
+                                                         corresponding bit in the PCI_INT_ENB2 is SET. */
+        uint64_t rml_wto                 : 1;       /**< Set '1' when the RML does not receive a commit
+                                                         back from a RSL after sending a write command to
+                                                         a RSL. */
+        uint64_t rml_rto                 : 1;       /**< Set '1' when the RML does not receive read data
+                                                         back from a RSL after sending a read command to
+                                                         a RSL. */
+#else
+        uint64_t rml_rto                 : 1;
+        uint64_t rml_wto                 : 1;
+        uint64_t pci_rsl                 : 1;
+        uint64_t po0_2sml                : 1;
+        uint64_t po1_2sml                : 1;
+        uint64_t po2_2sml                : 1;
+        uint64_t po3_2sml                : 1;
+        uint64_t i0_rtout                : 1;
+        uint64_t i1_rtout                : 1;
+        uint64_t i2_rtout                : 1;
+        uint64_t i3_rtout                : 1;
+        uint64_t i0_overf                : 1;
+        uint64_t i1_overf                : 1;
+        uint64_t i2_overf                : 1;
+        uint64_t i3_overf                : 1;
+        uint64_t p0_rtout                : 1;
+        uint64_t p1_rtout                : 1;
+        uint64_t p2_rtout                : 1;
+        uint64_t p3_rtout                : 1;
+        uint64_t p0_perr                 : 1;
+        uint64_t p1_perr                 : 1;
+        uint64_t p2_perr                 : 1;
+        uint64_t p3_perr                 : 1;
+        uint64_t g0_rtout                : 1;
+        uint64_t g1_rtout                : 1;
+        uint64_t g2_rtout                : 1;
+        uint64_t g3_rtout                : 1;
+        uint64_t p0_pperr                : 1;
+        uint64_t p1_pperr                : 1;
+        uint64_t p2_pperr                : 1;
+        uint64_t p3_pperr                : 1;
+        uint64_t p0_ptout                : 1;
+        uint64_t p1_ptout                : 1;
+        uint64_t p2_ptout                : 1;
+        uint64_t p3_ptout                : 1;
+        uint64_t i0_pperr                : 1;
+        uint64_t i1_pperr                : 1;
+        uint64_t i2_pperr                : 1;
+        uint64_t i3_pperr                : 1;
+        uint64_t win_rto                 : 1;
+        uint64_t p_dperr                 : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t reserved_42_63          : 22;
+#endif
+    } cn38xxp2;
+    struct cvmx_npi_int_sum_cn31xx       cn50xx;
+    struct cvmx_npi_int_sum_s            cn58xx;
+    struct cvmx_npi_int_sum_s            cn58xxp1;
+} cvmx_npi_int_sum_t;
+
+
+/**
+ * cvmx_npi_lowp_dbell
+ *
+ * NPI_LOWP_DBELL = Low Priority Door Bell
+ * 
+ * The door bell register for the low priority DMA queue.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_lowp_dbell_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dbell                   : 16;      /**< The value written to this register is added to the
+                                                         number of 8byte words to be read and processes for
+                                                         the low priority dma queue. */
+#else
+        uint64_t dbell                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_npi_lowp_dbell_s         cn30xx;
+    struct cvmx_npi_lowp_dbell_s         cn31xx;
+    struct cvmx_npi_lowp_dbell_s         cn38xx;
+    struct cvmx_npi_lowp_dbell_s         cn38xxp2;
+    struct cvmx_npi_lowp_dbell_s         cn50xx;
+    struct cvmx_npi_lowp_dbell_s         cn58xx;
+    struct cvmx_npi_lowp_dbell_s         cn58xxp1;
+} cvmx_npi_lowp_dbell_t;
+
+
+/**
+ * cvmx_npi_lowp_ibuff_saddr
+ *
+ * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address
+ * 
+ * The address to start reading Instructions from for LOWP.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_lowp_ibuff_saddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t saddr                   : 36;      /**< The starting address to read the first instruction. */
+#else
+        uint64_t saddr                   : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn30xx;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn31xx;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn38xx;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn38xxp2;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn50xx;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn58xx;
+    struct cvmx_npi_lowp_ibuff_saddr_s   cn58xxp1;
+} cvmx_npi_lowp_ibuff_saddr_t;
+
+
+/**
+ * cvmx_npi_mem_access_subid#
+ *
+ * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register
+ * 
+ * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_mem_access_subidx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t shortl                  : 1;       /**< Generate CMD-6 on PCI(x) when '1'.
+                                                         Loads from the cores to the corresponding subid
+                                                         that are 32-bits or smaller:
+                                                         - Will generate the PCI-X "Memory Read DWORD"
+                                                           command in PCI-X mode. (Note that "Memory
+                                                           Read DWORD" appears much like an IO read on
+                                                           the PCI-X bus.)
+                                                         - Will generate the PCI "Memory Read" command
+                                                           in PCI-X mode, irrespective of the
+                                                           NPI_PCI_READ_CMD[CMD_SIZE] value.
+                                                         NOT IN PASS 1 NOR PASS 2 */
+        uint64_t nmerge                  : 1;       /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */
+        uint64_t esr                     : 2;       /**< Endian-Swap on read. */
+        uint64_t esw                     : 2;       /**< Endian-Swap on write. */
+        uint64_t nsr                     : 1;       /**< No-Snoop on read. */
+        uint64_t nsw                     : 1;       /**< No-Snoop on write. */
+        uint64_t ror                     : 1;       /**< Relax Read on read. */
+        uint64_t row                     : 1;       /**< Relax Order on write. */
+        uint64_t ba                      : 28;      /**< PCI Address bits [63:36]. */
+#else
+        uint64_t ba                      : 28;
+        uint64_t row                     : 1;
+        uint64_t ror                     : 1;
+        uint64_t nsw                     : 1;
+        uint64_t nsr                     : 1;
+        uint64_t esw                     : 2;
+        uint64_t esr                     : 2;
+        uint64_t nmerge                  : 1;
+        uint64_t shortl                  : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_npi_mem_access_subidx_s  cn30xx;
+    struct cvmx_npi_mem_access_subidx_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t esr                     : 2;       /**< Endian-Swap on read. */
+        uint64_t esw                     : 2;       /**< Endian-Swap on write. */
+        uint64_t nsr                     : 1;       /**< No-Snoop on read. */
+        uint64_t nsw                     : 1;       /**< No-Snoop on write. */
+        uint64_t ror                     : 1;       /**< Relax Read on read. */
+        uint64_t row                     : 1;       /**< Relax Order on write. */
+        uint64_t ba                      : 28;      /**< PCI Address bits [63:36]. */
+#else
+        uint64_t ba                      : 28;
+        uint64_t row                     : 1;
+        uint64_t ror                     : 1;
+        uint64_t nsw                     : 1;
+        uint64_t nsr                     : 1;
+        uint64_t esw                     : 2;
+        uint64_t esr                     : 2;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } cn31xx;
+    struct cvmx_npi_mem_access_subidx_s  cn38xx;
+    struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
+    struct cvmx_npi_mem_access_subidx_s  cn50xx;
+    struct cvmx_npi_mem_access_subidx_s  cn58xx;
+    struct cvmx_npi_mem_access_subidx_s  cn58xxp1;
+} cvmx_npi_mem_access_subidx_t;
+
+
+/**
+ * cvmx_npi_msi_rcv
+ *
+ * NPI_MSI_RCV = NPI MSI Receive Vector Register
+ * 
+ * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_msi_rcv_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t int_vec                 : 64;      /**< Refer to PCI_MSI_RCV */
+#else
+        uint64_t int_vec                 : 64;
+#endif
+    } s;
+    struct cvmx_npi_msi_rcv_s            cn30xx;
+    struct cvmx_npi_msi_rcv_s            cn31xx;
+    struct cvmx_npi_msi_rcv_s            cn38xx;
+    struct cvmx_npi_msi_rcv_s            cn38xxp2;
+    struct cvmx_npi_msi_rcv_s            cn50xx;
+    struct cvmx_npi_msi_rcv_s            cn58xx;
+    struct cvmx_npi_msi_rcv_s            cn58xxp1;
+} cvmx_npi_msi_rcv_t;
+
+
+/**
+ * cvmx_npi_num_desc_output#
+ *
+ * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0
+ * 
+ * The size of the Buffer/Info Pointer Pair ring for Output-0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_num_desc_outputx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t size                    : 32;      /**< The size of the Buffer/Info Pointer Pair ring. */
+#else
+        uint64_t size                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npi_num_desc_outputx_s   cn30xx;
+    struct cvmx_npi_num_desc_outputx_s   cn31xx;
+    struct cvmx_npi_num_desc_outputx_s   cn38xx;
+    struct cvmx_npi_num_desc_outputx_s   cn38xxp2;
+    struct cvmx_npi_num_desc_outputx_s   cn50xx;
+    struct cvmx_npi_num_desc_outputx_s   cn58xx;
+    struct cvmx_npi_num_desc_outputx_s   cn58xxp1;
+} cvmx_npi_num_desc_outputx_t;
+
+
+/**
+ * cvmx_npi_output_control
+ *
+ * NPI_OUTPUT_CONTROL = NPI's Output Control Register
+ * 
+ * The address to start reading Instructions from for Output-3.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_output_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t pkt_rr                  : 1;       /**< When set '1' the output packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the output packet port is fixed in priority,
+                                                         where the lower port number has higher priority.
+                                                         PASS3 Field */
+        uint64_t p3_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT3 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p2_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT2 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t o3_es                   : 2;       /**< Endian Swap for Output3 Data. */
+        uint64_t o3_ns                   : 1;       /**< NoSnoop Enable for Output3 Data. */
+        uint64_t o3_ro                   : 1;       /**< Relaxed Ordering Enable for Output3 Data. */
+        uint64_t o2_es                   : 2;       /**< Endian Swap for Output2 Data. */
+        uint64_t o2_ns                   : 1;       /**< NoSnoop Enable for Output2 Data. */
+        uint64_t o2_ro                   : 1;       /**< Relaxed Ordering Enable for Output2 Data. */
+        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
+        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
+        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
+        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
+        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
+        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
+        uint64_t o3_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O3_ES,
+                                                         O3_NS, O3_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
+        uint64_t o2_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O2_ES,
+                                                         O2_NS, O2_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
+        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+        uint64_t reserved_20_23          : 4;
+        uint64_t iptr_o3                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-3. */
+        uint64_t iptr_o2                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-2. */
+        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+        uint64_t esr_sl3                 : 2;       /**< The Endian-Swap-Mode for Slist3 reads. */
+        uint64_t nsr_sl3                 : 1;       /**< Enables '1' NoSnoop for Slist3 reads. */
+        uint64_t ror_sl3                 : 1;       /**< Enables '1' Relaxed Ordering for Slist3 reads. */
+        uint64_t esr_sl2                 : 2;       /**< The Endian-Swap-Mode for Slist2 reads. */
+        uint64_t nsr_sl2                 : 1;       /**< Enables '1' NoSnoop for Slist2 reads. */
+        uint64_t ror_sl2                 : 1;       /**< Enables '1' Relaxed Ordering for Slist2 reads. */
+        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
+        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
+        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
+        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
+        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+        uint64_t ror_sl0                 : 1;
+        uint64_t nsr_sl0                 : 1;
+        uint64_t esr_sl0                 : 2;
+        uint64_t ror_sl1                 : 1;
+        uint64_t nsr_sl1                 : 1;
+        uint64_t esr_sl1                 : 2;
+        uint64_t ror_sl2                 : 1;
+        uint64_t nsr_sl2                 : 1;
+        uint64_t esr_sl2                 : 2;
+        uint64_t ror_sl3                 : 1;
+        uint64_t nsr_sl3                 : 1;
+        uint64_t esr_sl3                 : 2;
+        uint64_t iptr_o0                 : 1;
+        uint64_t iptr_o1                 : 1;
+        uint64_t iptr_o2                 : 1;
+        uint64_t iptr_o3                 : 1;
+        uint64_t reserved_20_23          : 4;
+        uint64_t o0_csrm                 : 1;
+        uint64_t o1_csrm                 : 1;
+        uint64_t o2_csrm                 : 1;
+        uint64_t o3_csrm                 : 1;
+        uint64_t o0_ro                   : 1;
+        uint64_t o0_ns                   : 1;
+        uint64_t o0_es                   : 2;
+        uint64_t o1_ro                   : 1;
+        uint64_t o1_ns                   : 1;
+        uint64_t o1_es                   : 2;
+        uint64_t o2_ro                   : 1;
+        uint64_t o2_ns                   : 1;
+        uint64_t o2_es                   : 2;
+        uint64_t o3_ro                   : 1;
+        uint64_t o3_ns                   : 1;
+        uint64_t o3_es                   : 2;
+        uint64_t p0_bmode                : 1;
+        uint64_t p1_bmode                : 1;
+        uint64_t p2_bmode                : 1;
+        uint64_t p3_bmode                : 1;
+        uint64_t pkt_rr                  : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_npi_output_control_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_45_63          : 19;
+        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t reserved_32_43          : 12;
+        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
+        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
+        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
+        uint64_t reserved_25_27          : 3;
+        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+        uint64_t reserved_17_23          : 7;
+        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+        uint64_t reserved_4_15           : 12;
+        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
+        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
+        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+        uint64_t ror_sl0                 : 1;
+        uint64_t nsr_sl0                 : 1;
+        uint64_t esr_sl0                 : 2;
+        uint64_t reserved_4_15           : 12;
+        uint64_t iptr_o0                 : 1;
+        uint64_t reserved_17_23          : 7;
+        uint64_t o0_csrm                 : 1;
+        uint64_t reserved_25_27          : 3;
+        uint64_t o0_ro                   : 1;
+        uint64_t o0_ns                   : 1;
+        uint64_t o0_es                   : 2;
+        uint64_t reserved_32_43          : 12;
+        uint64_t p0_bmode                : 1;
+        uint64_t reserved_45_63          : 19;
+#endif
+    } cn30xx;
+    struct cvmx_npi_output_control_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_46_63          : 18;
+        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t reserved_36_43          : 8;
+        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
+        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
+        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
+        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
+        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
+        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
+        uint64_t reserved_26_27          : 2;
+        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+        uint64_t reserved_18_23          : 6;
+        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+        uint64_t reserved_8_15           : 8;
+        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
+        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
+        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
+        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
+        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+        uint64_t ror_sl0                 : 1;
+        uint64_t nsr_sl0                 : 1;
+        uint64_t esr_sl0                 : 2;
+        uint64_t ror_sl1                 : 1;
+        uint64_t nsr_sl1                 : 1;
+        uint64_t esr_sl1                 : 2;
+        uint64_t reserved_8_15           : 8;
+        uint64_t iptr_o0                 : 1;
+        uint64_t iptr_o1                 : 1;
+        uint64_t reserved_18_23          : 6;
+        uint64_t o0_csrm                 : 1;
+        uint64_t o1_csrm                 : 1;
+        uint64_t reserved_26_27          : 2;
+        uint64_t o0_ro                   : 1;
+        uint64_t o0_ns                   : 1;
+        uint64_t o0_es                   : 2;
+        uint64_t o1_ro                   : 1;
+        uint64_t o1_ns                   : 1;
+        uint64_t o1_es                   : 2;
+        uint64_t reserved_36_43          : 8;
+        uint64_t p0_bmode                : 1;
+        uint64_t p1_bmode                : 1;
+        uint64_t reserved_46_63          : 18;
+#endif
+    } cn31xx;
+    struct cvmx_npi_output_control_s     cn38xx;
+    struct cvmx_npi_output_control_cn38xxp2
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t p3_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT3 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p2_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT2 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t o3_es                   : 2;       /**< Endian Swap for Output3 Data. */
+        uint64_t o3_ns                   : 1;       /**< NoSnoop Enable for Output3 Data. */
+        uint64_t o3_ro                   : 1;       /**< Relaxed Ordering Enable for Output3 Data. */
+        uint64_t o2_es                   : 2;       /**< Endian Swap for Output2 Data. */
+        uint64_t o2_ns                   : 1;       /**< NoSnoop Enable for Output2 Data. */
+        uint64_t o2_ro                   : 1;       /**< Relaxed Ordering Enable for Output2 Data. */
+        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
+        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
+        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
+        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
+        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
+        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
+        uint64_t o3_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O3_ES,
+                                                         O3_NS, O3_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */
+        uint64_t o2_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O2_ES,
+                                                         O2_NS, O2_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */
+        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+        uint64_t reserved_20_23          : 4;
+        uint64_t iptr_o3                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-3. */
+        uint64_t iptr_o2                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-2. */
+        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+        uint64_t esr_sl3                 : 2;       /**< The Endian-Swap-Mode for Slist3 reads. */
+        uint64_t nsr_sl3                 : 1;       /**< Enables '1' NoSnoop for Slist3 reads. */
+        uint64_t ror_sl3                 : 1;       /**< Enables '1' Relaxed Ordering for Slist3 reads. */
+        uint64_t esr_sl2                 : 2;       /**< The Endian-Swap-Mode for Slist2 reads. */
+        uint64_t nsr_sl2                 : 1;       /**< Enables '1' NoSnoop for Slist2 reads. */
+        uint64_t ror_sl2                 : 1;       /**< Enables '1' Relaxed Ordering for Slist2 reads. */
+        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
+        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
+        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
+        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
+        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+        uint64_t ror_sl0                 : 1;
+        uint64_t nsr_sl0                 : 1;
+        uint64_t esr_sl0                 : 2;
+        uint64_t ror_sl1                 : 1;
+        uint64_t nsr_sl1                 : 1;
+        uint64_t esr_sl1                 : 2;
+        uint64_t ror_sl2                 : 1;
+        uint64_t nsr_sl2                 : 1;
+        uint64_t esr_sl2                 : 2;
+        uint64_t ror_sl3                 : 1;
+        uint64_t nsr_sl3                 : 1;
+        uint64_t esr_sl3                 : 2;
+        uint64_t iptr_o0                 : 1;
+        uint64_t iptr_o1                 : 1;
+        uint64_t iptr_o2                 : 1;
+        uint64_t iptr_o3                 : 1;
+        uint64_t reserved_20_23          : 4;
+        uint64_t o0_csrm                 : 1;
+        uint64_t o1_csrm                 : 1;
+        uint64_t o2_csrm                 : 1;
+        uint64_t o3_csrm                 : 1;
+        uint64_t o0_ro                   : 1;
+        uint64_t o0_ns                   : 1;
+        uint64_t o0_es                   : 2;
+        uint64_t o1_ro                   : 1;
+        uint64_t o1_ns                   : 1;
+        uint64_t o1_es                   : 2;
+        uint64_t o2_ro                   : 1;
+        uint64_t o2_ns                   : 1;
+        uint64_t o2_es                   : 2;
+        uint64_t o3_ro                   : 1;
+        uint64_t o3_ns                   : 1;
+        uint64_t o3_es                   : 2;
+        uint64_t p0_bmode                : 1;
+        uint64_t p1_bmode                : 1;
+        uint64_t p2_bmode                : 1;
+        uint64_t p3_bmode                : 1;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } cn38xxp2;
+    struct cvmx_npi_output_control_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t pkt_rr                  : 1;       /**< When set '1' the output packet selection will be
+                                                         made with a Round Robin arbitration. When '0'
+                                                         the output packet port is fixed in priority,
+                                                         where the lower port number has higher priority.
+                                                         PASS2 Field */
+        uint64_t reserved_46_47          : 2;
+        uint64_t p1_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT1 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t p0_bmode                : 1;       /**< When set '1' PCI_PKTS_SENT0 register will be
+                                                         updated with the number of bytes in the packet
+                                                         sent, when '0' the register will have a value
+                                                         of '1' added. */
+        uint64_t reserved_36_43          : 8;
+        uint64_t o1_es                   : 2;       /**< Endian Swap for Output1 Data. */
+        uint64_t o1_ns                   : 1;       /**< NoSnoop Enable for Output1 Data. */
+        uint64_t o1_ro                   : 1;       /**< Relaxed Ordering Enable for Output1 Data. */
+        uint64_t o0_es                   : 2;       /**< Endian Swap for Output0 Data. */
+        uint64_t o0_ns                   : 1;       /**< NoSnoop Enable for Output0 Data. */
+        uint64_t o0_ro                   : 1;       /**< Relaxed Ordering Enable for Output0 Data. */
+        uint64_t reserved_26_27          : 2;
+        uint64_t o1_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O1_ES,
+                                                         O1_NS, O1_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */
+        uint64_t o0_csrm                 : 1;       /**< When '1' the address[63:60] to write packet data,
+                                                         comes from the DPTR[63:60] in the scatter-list pair,
+                                                         and the RO, NS, ES values come from the O0_ES,
+                                                         O0_NS, O0_RO. When '0' the RO == DPTR[60],
+                                                         NS == DPTR[61], ES == DPTR[63:62], the address the
+                                                         packet will be written to is ADDR[63:60] ==
+                                                         O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */
+        uint64_t reserved_18_23          : 6;
+        uint64_t iptr_o1                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-1. */
+        uint64_t iptr_o0                 : 1;       /**< Uses the Info-Pointer to store length and data
+                                                         for output-0. */
+        uint64_t reserved_8_15           : 8;
+        uint64_t esr_sl1                 : 2;       /**< The Endian-Swap-Mode for Slist1 reads. */
+        uint64_t nsr_sl1                 : 1;       /**< Enables '1' NoSnoop for Slist1 reads. */
+        uint64_t ror_sl1                 : 1;       /**< Enables '1' Relaxed Ordering for Slist1 reads. */
+        uint64_t esr_sl0                 : 2;       /**< The Endian-Swap-Mode for Slist0 reads. */
+        uint64_t nsr_sl0                 : 1;       /**< Enables '1' NoSnoop for Slist0 reads. */
+        uint64_t ror_sl0                 : 1;       /**< Enables '1' Relaxed Ordering for Slist0 reads. */
+#else
+        uint64_t ror_sl0                 : 1;
+        uint64_t nsr_sl0                 : 1;
+        uint64_t esr_sl0                 : 2;
+        uint64_t ror_sl1                 : 1;
+        uint64_t nsr_sl1                 : 1;
+        uint64_t esr_sl1                 : 2;
+        uint64_t reserved_8_15           : 8;
+        uint64_t iptr_o0                 : 1;
+        uint64_t iptr_o1                 : 1;
+        uint64_t reserved_18_23          : 6;
+        uint64_t o0_csrm                 : 1;
+        uint64_t o1_csrm                 : 1;
+        uint64_t reserved_26_27          : 2;
+        uint64_t o0_ro                   : 1;
+        uint64_t o0_ns                   : 1;
+        uint64_t o0_es                   : 2;
+        uint64_t o1_ro                   : 1;
+        uint64_t o1_ns                   : 1;
+        uint64_t o1_es                   : 2;
+        uint64_t reserved_36_43          : 8;
+        uint64_t p0_bmode                : 1;
+        uint64_t p1_bmode                : 1;
+        uint64_t reserved_46_47          : 2;
+        uint64_t pkt_rr                  : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } cn50xx;
+    struct cvmx_npi_output_control_s     cn58xx;
+    struct cvmx_npi_output_control_s     cn58xxp1;
+} cvmx_npi_output_control_t;
+
+
+/**
+ * cvmx_npi_p#_dbpair_addr
+ *
+ * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address.
+ * 
+ * Contains the next address to read for Port's-0 Data/Buffer Pair.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_px_dbpair_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_63_63          : 1;
+        uint64_t state                   : 2;       /**< POS state machine vector. Used to tell when NADDR
+                                                         is valid (when STATE == 0). */
+        uint64_t naddr                   : 61;      /**< Bits [63:3] of the next Data-Info Pair to read.
+                                                         Value is only valid when STATE == 0. */
+#else
+        uint64_t naddr                   : 61;
+        uint64_t state                   : 2;
+        uint64_t reserved_63_63          : 1;
+#endif
+    } s;
+    struct cvmx_npi_px_dbpair_addr_s     cn30xx;
+    struct cvmx_npi_px_dbpair_addr_s     cn31xx;
+    struct cvmx_npi_px_dbpair_addr_s     cn38xx;
+    struct cvmx_npi_px_dbpair_addr_s     cn38xxp2;
+    struct cvmx_npi_px_dbpair_addr_s     cn50xx;
+    struct cvmx_npi_px_dbpair_addr_s     cn58xx;
+    struct cvmx_npi_px_dbpair_addr_s     cn58xxp1;
+} cvmx_npi_px_dbpair_addr_t;
+
+
+/**
+ * cvmx_npi_p#_instr_addr
+ *
+ * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address.
+ * 
+ * Contains the next address to read for Port's-0 Instructions.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_px_instr_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t state                   : 3;       /**< Gather engine state vector. Used to tell when
+                                                         NADDR is valid (when STATE == 0). */
+        uint64_t naddr                   : 61;      /**< Bits [63:3] of the next Instruction to read.
+                                                         Value is only valid when STATE == 0. */
+#else
+        uint64_t naddr                   : 61;
+        uint64_t state                   : 3;
+#endif
+    } s;
+    struct cvmx_npi_px_instr_addr_s      cn30xx;
+    struct cvmx_npi_px_instr_addr_s      cn31xx;
+    struct cvmx_npi_px_instr_addr_s      cn38xx;
+    struct cvmx_npi_px_instr_addr_s      cn38xxp2;
+    struct cvmx_npi_px_instr_addr_s      cn50xx;
+    struct cvmx_npi_px_instr_addr_s      cn58xx;
+    struct cvmx_npi_px_instr_addr_s      cn58xxp1;
+} cvmx_npi_px_instr_addr_t;
+
+
+/**
+ * cvmx_npi_p#_instr_cnts
+ *
+ * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In.
+ * 
+ * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_px_instr_cnts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t fcnt                    : 6;       /**< Number entries in the Instruction FIFO. */
+        uint64_t avail                   : 32;      /**< Doorbell count to be read. */
+#else
+        uint64_t avail                   : 32;
+        uint64_t fcnt                    : 6;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_npi_px_instr_cnts_s      cn30xx;
+    struct cvmx_npi_px_instr_cnts_s      cn31xx;
+    struct cvmx_npi_px_instr_cnts_s      cn38xx;
+    struct cvmx_npi_px_instr_cnts_s      cn38xxp2;
+    struct cvmx_npi_px_instr_cnts_s      cn50xx;
+    struct cvmx_npi_px_instr_cnts_s      cn58xx;
+    struct cvmx_npi_px_instr_cnts_s      cn58xxp1;
+} cvmx_npi_px_instr_cnts_t;
+
+
+/**
+ * cvmx_npi_p#_pair_cnts
+ *
+ * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out.
+ * 
+ * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_px_pair_cnts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t fcnt                    : 5;       /**< 16 - number entries in the D/I Pair FIFO. */
+        uint64_t avail                   : 32;      /**< Doorbell count to be read. */
+#else
+        uint64_t avail                   : 32;
+        uint64_t fcnt                    : 5;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } s;
+    struct cvmx_npi_px_pair_cnts_s       cn30xx;
+    struct cvmx_npi_px_pair_cnts_s       cn31xx;
+    struct cvmx_npi_px_pair_cnts_s       cn38xx;
+    struct cvmx_npi_px_pair_cnts_s       cn38xxp2;
+    struct cvmx_npi_px_pair_cnts_s       cn50xx;
+    struct cvmx_npi_px_pair_cnts_s       cn58xx;
+    struct cvmx_npi_px_pair_cnts_s       cn58xxp1;
+} cvmx_npi_px_pair_cnts_t;
+
+
+/**
+ * cvmx_npi_pci_burst_size
+ *
+ * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register
+ * 
+ * Control the number of words the NPI will attempt to read / write to/from the PCI.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_pci_burst_size_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t wr_brst                 : 7;       /**< The number of 8B words to write to PCI in any one
+                                                         write operation. A zero is equal to 128. This
+                                                         value is used the packet reads and is clamped at
+                                                         a max of 112 for dma writes. */
+        uint64_t rd_brst                 : 7;       /**< Number of 8B words to read from PCI in any one
+                                                         read operation. Legal values are 1 to 127, where
+                                                         a 0 will be treated as a 1.
+                                                         "For reading of packet data value is limited to 64
+                                                         in PASS-2."
+                                                         This value does not control the size of a read
+                                                         caused by an IOBDMA from a PP. */
+#else
+        uint64_t rd_brst                 : 7;
+        uint64_t wr_brst                 : 7;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_npi_pci_burst_size_s     cn30xx;
+    struct cvmx_npi_pci_burst_size_s     cn31xx;
+    struct cvmx_npi_pci_burst_size_s     cn38xx;
+    struct cvmx_npi_pci_burst_size_s     cn38xxp2;
+    struct cvmx_npi_pci_burst_size_s     cn50xx;
+    struct cvmx_npi_pci_burst_size_s     cn58xx;
+    struct cvmx_npi_pci_burst_size_s     cn58xxp1;
+} cvmx_npi_pci_burst_size_t;
+
+
+/**
+ * cvmx_npi_pci_int_arb_cfg
+ *
+ * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter
+ * 
+ * Controls operation of the Internal PCI Arbiter.  This register should
+ * only be written when PRST# is asserted.  NPI_PCI_INT_ARB_CFG[EN] should
+ * only be set when Octane is a host.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_pci_int_arb_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t hostmode                : 1;       /**< PCI Host Mode Pin (sampled for use by software).
+                                                         This bit reflects the sampled PCI_HOSTMODE pin.
+                                                         In HOST Mode, OCTEON drives the PCI_CLK_OUT and
+                                                         PCI initialization pattern during PCI_RST_N deassertion).
+                                                         *** NOTE: O9N PASS1 Addition */
+        uint64_t pci_ovr                 : 4;       /**< PCI Host Mode Bus Speed/Type Override
+                                                          When in Host Mode(PCI_HOSTMODE pin =1), OCTEON acting
+                                                          as the PCI Central Agent, samples the PCI_PCI100,
+                                                          PCI_M66EN and PCI_PCIXCAP pins to determine the
+                                                          'sampled' PCI Bus speed and Bus Type (PCI or PCIX).
+                                                          (see: PCI_CNT_REG[HM_SPEED,HM_PCIX])
+                                                          However, in some cases, SW may want to override the
+                                                          the 'sampled' PCI Bus Type/Speed, and use some
+                                                          SLOWER Bus frequency.
+                                                          The PCI_OVR field encoding represents the 'override'
+                                                          PCI Bus Type/Speed which will be used to generate the
+                                                          PCI_CLK_OUT and determines the PCI initialization pattern
+                                                          driven during PCI_RST_N deassertion.
+                                                              PCI_OVR[3]: OVERRIDE (0:DISABLE/1:ENABLE)
+                                                              PCI_OVR[2]: BUS TYPE(0:PCI/1:PCIX)
+                                                              PCI_OVR[1:0]: BUS SPEED(0:33/1:66/2:100/3:133)
+                                                         OVERRIDE TYPE SPEED |  Override Configuration
+                                                            [3]   [2]  [1:0] | TYPE       SPEED
+                                                           ------------------+-------------------------------
+                                                             0     x      xx | No override(uses 'sampled'
+                                                                             | Bus Speed(HM_SPEED) and Bus Type(HM_PCIX)
+                                                             1     0      00 | PCI Mode    33MHz
+                                                             1     0      01 | PCI Mode    66MHz
+                                                             1     0      10 | RESERVED (DO NOT USE)
+                                                             1     0      11 | RESERVED (DO NOT USE)
+                                                             1     1      00 | RESERVED (DO NOT USE)
+                                                             1     1      01 | PCIX Mode   66MHz
+                                                             1     1      10 | PCIX Mode  100MHz
+                                                             1     1      11 | PCIX Mode  133MHz
+                                                          NOTES:
+                                                          - NPI_PCI_INT_ARB_CFG[PCI_OVR] has NO EFFECT on
+                                                            PCI_CNT_REG[HM_SPEED,HM_PCIX] (ie: the sampled PCI Bus
+                                                            Type/Speed), but WILL EFFECT PCI_CTL_STATUS_2[AP_PCIX]
+                                                            which reflects the actual PCI Bus Type(0:PCI/1:PCIX).
+                                                          - Software should never 'up' configure the recommended values.
+                                                            In other words, if the 'sampled' Bus Type=PCI(HM_PCIX=0),
+                                                            then SW should NOT attempt to set TYPE[2]=1 for PCIX Mode.
+                                                            Likewise, if the sampled Bus Speed=66MHz(HM_SPEED=01),
+                                                            then SW should NOT attempt to 'speed up' the bus [ie:
+                                                            SPEED[1:0]=10(100MHz)].
+                                                          - If PCI_OVR<3> is set prior to PCI reset de-assertion
+                                                            in host mode, NPI_PCI_INT_ARB_CFG[PCI_OVR]
+                                                            indicates the Bus Type/Speed that OCTEON drove on the
+                                                            DEVSEL/STOP/TRDY pins during reset de-assertion. (user
+                                                            should then ignore the 'sampled' Bus Type/Speed
+                                                            contained in the PCI_CNT_REG[HM_PCIX, HM_SPEED]) fields.
+                                                          - If PCI_OVR<3> is clear prior to PCI reset de-assertion
+                                                            in host mode, PCI_CNT_REG[HM_PCIX,HM_SPEED])
+                                                            indicates the Bus Type/Speed that OCTEON drove on the
+                                                            DEVSEL/STOP/TRDY pins during reset de-assertion.
+                                                          *** NOTE: O9N PASS1 Addition */
+        uint64_t reserved_5_7            : 3;
+        uint64_t en                      : 1;       /**< Internal arbiter enable. */
+        uint64_t park_mod                : 1;       /**< Bus park mode. 0=park on last, 1=park on device. */
+        uint64_t park_dev                : 3;       /**< Bus park device. 0-3 External device, 4 = Octane. */
+#else
+        uint64_t park_dev                : 3;
+        uint64_t park_mod                : 1;
+        uint64_t en                      : 1;
+        uint64_t reserved_5_7            : 3;
+        uint64_t pci_ovr                 : 4;
+        uint64_t hostmode                : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_npi_pci_int_arb_cfg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t en                      : 1;       /**< Internal arbiter enable. */
+        uint64_t park_mod                : 1;       /**< Bus park mode. 0=park on last, 1=park on device. */
+        uint64_t park_dev                : 3;       /**< Bus park device. 0-3 External device, 4 = Octane. */
+#else
+        uint64_t park_dev                : 3;
+        uint64_t park_mod                : 1;
+        uint64_t en                      : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } cn30xx;
+    struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
+    struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
+    struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
+    struct cvmx_npi_pci_int_arb_cfg_s    cn50xx;
+    struct cvmx_npi_pci_int_arb_cfg_s    cn58xx;
+    struct cvmx_npi_pci_int_arb_cfg_s    cn58xxp1;
+} cvmx_npi_pci_int_arb_cfg_t;
+
+
+/**
+ * cvmx_npi_pci_read_cmd
+ *
+ * NPI_PCI_READ_CMD = NPI PCI Read Command Register
+ * 
+ * Controls the type of read command sent.
+ * Writes to this register are not ordered with writes/reads to the PCI Memory space.
+ * To ensure that a write has completed the user must read the register before
+ * making an access(i.e. PCI memory space) that requires the value of this register to be updated.
+ * Also any previously issued reads/writes to PCI memory space, still stored in the outbound
+ * FIFO will use the value of this register after it has been updated.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_pci_read_cmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t cmd_size                : 11;      /**< Number bytes to be read is equal to or exceeds this
+                                                         size will cause the PCI in PCI mode to use a
+                                                         Memory-Read-Multiple. This register has a value
+                                                         from 8 to 2048. A value of 0-7 will be treated as
+                                                         a value of 2048. */
+#else
+        uint64_t cmd_size                : 11;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_npi_pci_read_cmd_s       cn30xx;
+    struct cvmx_npi_pci_read_cmd_s       cn31xx;
+    struct cvmx_npi_pci_read_cmd_s       cn38xx;
+    struct cvmx_npi_pci_read_cmd_s       cn38xxp2;
+    struct cvmx_npi_pci_read_cmd_s       cn50xx;
+    struct cvmx_npi_pci_read_cmd_s       cn58xx;
+    struct cvmx_npi_pci_read_cmd_s       cn58xxp1;
+} cvmx_npi_pci_read_cmd_t;
+
+
+/**
+ * cvmx_npi_port32_instr_hdr
+ *
+ * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header
+ * 
+ * Contains bits [62:42] of the Instruction Header for port 32.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_port32_instr_hdr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
+        uint64_t rsv_f                   : 5;       /**< Reserved */
+        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
+        uint64_t rsv_e                   : 1;       /**< Reserved */
+        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
+        uint64_t rsv_d                   : 6;       /**< Reserved */
+        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+        uint64_t rsv_c                   : 5;       /**< Reserved */
+        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_b                   : 1;       /**< Reserved
+                                                         instruction header sent to IPD. */
+        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_a                   : 6;       /**< Reserved */
+#else
+        uint64_t rsv_a                   : 6;
+        uint64_t skp_len                 : 7;
+        uint64_t rsv_b                   : 1;
+        uint64_t par_mode                : 2;
+        uint64_t rsv_c                   : 5;
+        uint64_t use_ihdr                : 1;
+        uint64_t rsv_d                   : 6;
+        uint64_t rskp_len                : 7;
+        uint64_t rsv_e                   : 1;
+        uint64_t rparmode                : 2;
+        uint64_t rsv_f                   : 5;
+        uint64_t pbp                     : 1;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npi_port32_instr_hdr_s   cn30xx;
+    struct cvmx_npi_port32_instr_hdr_s   cn31xx;
+    struct cvmx_npi_port32_instr_hdr_s   cn38xx;
+    struct cvmx_npi_port32_instr_hdr_s   cn38xxp2;
+    struct cvmx_npi_port32_instr_hdr_s   cn50xx;
+    struct cvmx_npi_port32_instr_hdr_s   cn58xx;
+    struct cvmx_npi_port32_instr_hdr_s   cn58xxp1;
+} cvmx_npi_port32_instr_hdr_t;
+
+
+/**
+ * cvmx_npi_port33_instr_hdr
+ *
+ * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header
+ * 
+ * Contains bits [62:42] of the Instruction Header for port 33.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_port33_instr_hdr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
+        uint64_t rsv_f                   : 5;       /**< Reserved */
+        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
+        uint64_t rsv_e                   : 1;       /**< Reserved */
+        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
+        uint64_t rsv_d                   : 6;       /**< Reserved */
+        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+        uint64_t rsv_c                   : 5;       /**< Reserved */
+        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_b                   : 1;       /**< Reserved
+                                                         instruction header sent to IPD. */
+        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_a                   : 6;       /**< Reserved */
+#else
+        uint64_t rsv_a                   : 6;
+        uint64_t skp_len                 : 7;
+        uint64_t rsv_b                   : 1;
+        uint64_t par_mode                : 2;
+        uint64_t rsv_c                   : 5;
+        uint64_t use_ihdr                : 1;
+        uint64_t rsv_d                   : 6;
+        uint64_t rskp_len                : 7;
+        uint64_t rsv_e                   : 1;
+        uint64_t rparmode                : 2;
+        uint64_t rsv_f                   : 5;
+        uint64_t pbp                     : 1;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npi_port33_instr_hdr_s   cn31xx;
+    struct cvmx_npi_port33_instr_hdr_s   cn38xx;
+    struct cvmx_npi_port33_instr_hdr_s   cn38xxp2;
+    struct cvmx_npi_port33_instr_hdr_s   cn50xx;
+    struct cvmx_npi_port33_instr_hdr_s   cn58xx;
+    struct cvmx_npi_port33_instr_hdr_s   cn58xxp1;
+} cvmx_npi_port33_instr_hdr_t;
+
+
+/**
+ * cvmx_npi_port34_instr_hdr
+ *
+ * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header
+ * 
+ * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_port34_instr_hdr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
+        uint64_t rsv_f                   : 5;       /**< Reserved */
+        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
+        uint64_t rsv_e                   : 1;       /**< Reserved */
+        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
+        uint64_t rsv_d                   : 6;       /**< Reserved */
+        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+        uint64_t rsv_c                   : 5;       /**< Reserved */
+        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_b                   : 1;       /**< Reserved
+                                                         instruction header sent to IPD. */
+        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_a                   : 6;       /**< Reserved */
+#else
+        uint64_t rsv_a                   : 6;
+        uint64_t skp_len                 : 7;
+        uint64_t rsv_b                   : 1;
+        uint64_t par_mode                : 2;
+        uint64_t rsv_c                   : 5;
+        uint64_t use_ihdr                : 1;
+        uint64_t rsv_d                   : 6;
+        uint64_t rskp_len                : 7;
+        uint64_t rsv_e                   : 1;
+        uint64_t rparmode                : 2;
+        uint64_t rsv_f                   : 5;
+        uint64_t pbp                     : 1;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npi_port34_instr_hdr_s   cn38xx;
+    struct cvmx_npi_port34_instr_hdr_s   cn38xxp2;
+    struct cvmx_npi_port34_instr_hdr_s   cn58xx;
+    struct cvmx_npi_port34_instr_hdr_s   cn58xxp1;
+} cvmx_npi_port34_instr_hdr_t;
+
+
+/**
+ * cvmx_npi_port35_instr_hdr
+ *
+ * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header
+ * 
+ * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_port35_instr_hdr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_44_63          : 20;
+        uint64_t pbp                     : 1;       /**< Enable Packet-by-packet mode. */
+        uint64_t rsv_f                   : 5;       /**< Reserved */
+        uint64_t rparmode                : 2;       /**< Parse Mode. Used when packet is raw and PBP==0. */
+        uint64_t rsv_e                   : 1;       /**< Reserved */
+        uint64_t rskp_len                : 7;       /**< Skip Length. Used when packet is raw and PBP==0. */
+        uint64_t rsv_d                   : 6;       /**< Reserved */
+        uint64_t use_ihdr                : 1;       /**< When set '1' the instruction header will be sent
+                                                         as part of the packet data, regardless of the
+                                                         value of bit [63] of the instruction header.
+                                                         USE_IHDR must be set whenever PBP is set. */
+        uint64_t rsv_c                   : 5;       /**< Reserved */
+        uint64_t par_mode                : 2;       /**< Parse Mode. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_b                   : 1;       /**< Reserved
+                                                         instruction header sent to IPD. */
+        uint64_t skp_len                 : 7;       /**< Skip Length. Used when USE_IHDR is set and packet
+                                                         is not raw and PBP is not set. */
+        uint64_t rsv_a                   : 6;       /**< Reserved */
+#else
+        uint64_t rsv_a                   : 6;
+        uint64_t skp_len                 : 7;
+        uint64_t rsv_b                   : 1;
+        uint64_t par_mode                : 2;
+        uint64_t rsv_c                   : 5;
+        uint64_t use_ihdr                : 1;
+        uint64_t rsv_d                   : 6;
+        uint64_t rskp_len                : 7;
+        uint64_t rsv_e                   : 1;
+        uint64_t rparmode                : 2;
+        uint64_t rsv_f                   : 5;
+        uint64_t pbp                     : 1;
+        uint64_t reserved_44_63          : 20;
+#endif
+    } s;
+    struct cvmx_npi_port35_instr_hdr_s   cn38xx;
+    struct cvmx_npi_port35_instr_hdr_s   cn38xxp2;
+    struct cvmx_npi_port35_instr_hdr_s   cn58xx;
+    struct cvmx_npi_port35_instr_hdr_s   cn58xxp1;
+} cvmx_npi_port35_instr_hdr_t;
+
+
+/**
+ * cvmx_npi_port_bp_control
+ *
+ * NPI_PORT_BP_CONTROL = Port Backpressure Control
+ * 
+ * Enables Port Level Backpressure
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_port_bp_control_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t bp_on                   : 4;       /**< Port 35-32 port level backpressure applied. */
+        uint64_t enb                     : 4;       /**< Enables port level backpressure from the IPD. */
+#else
+        uint64_t enb                     : 4;
+        uint64_t bp_on                   : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_npi_port_bp_control_s    cn30xx;
+    struct cvmx_npi_port_bp_control_s    cn31xx;
+    struct cvmx_npi_port_bp_control_s    cn38xx;
+    struct cvmx_npi_port_bp_control_s    cn38xxp2;
+    struct cvmx_npi_port_bp_control_s    cn50xx;
+    struct cvmx_npi_port_bp_control_s    cn58xx;
+    struct cvmx_npi_port_bp_control_s    cn58xxp1;
+} cvmx_npi_port_bp_control_t;
+
+
+/**
+ * cvmx_npi_rsl_int_blocks
+ *
+ * RSL_INT_BLOCKS = RSL Interrupt Blocks Register
+ * 
+ * Reading this register will return a vector with a bit set '1' for a corresponding RSL block
+ * that presently has an interrupt pending. The Field Description below supplies the name of the
+ * register that software should read to find out why that intterupt bit is set.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_rsl_int_blocks_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rint_31                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
+        uint64_t reserved_28_29          : 2;
+        uint64_t rint_27                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_26                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_25                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_24                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t asx1                    : 1;       /**< ASX1_INT_REG */
+        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
+        uint64_t rint_21                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
+        uint64_t spx1                    : 1;       /**< SPX1_INT_REG & STX1_INT_REG */
+        uint64_t spx0                    : 1;       /**< SPX0_INT_REG & STX0_INT_REG */
+        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
+        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
+        uint64_t rint_15                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t reserved_13_14          : 2;
+        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
+        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
+        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
+        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
+        uint64_t rint_8                  : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t zip                     : 1;       /**< ZIP_ERROR */
+        uint64_t dfa                     : 1;       /**< DFA_ERR */
+        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
+        uint64_t key                     : 1;       /**< KEY_INT_SUM */
+        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
+        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
+#else
+        uint64_t mio                     : 1;
+        uint64_t gmx0                    : 1;
+        uint64_t gmx1                    : 1;
+        uint64_t npi                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t rint_8                  : 1;
+        uint64_t ipd                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t tim                     : 1;
+        uint64_t pow                     : 1;
+        uint64_t reserved_13_14          : 2;
+        uint64_t rint_15                 : 1;
+        uint64_t l2c                     : 1;
+        uint64_t lmc                     : 1;
+        uint64_t spx0                    : 1;
+        uint64_t spx1                    : 1;
+        uint64_t pip                     : 1;
+        uint64_t rint_21                 : 1;
+        uint64_t asx0                    : 1;
+        uint64_t asx1                    : 1;
+        uint64_t rint_24                 : 1;
+        uint64_t rint_25                 : 1;
+        uint64_t rint_26                 : 1;
+        uint64_t rint_27                 : 1;
+        uint64_t reserved_28_29          : 2;
+        uint64_t iob                     : 1;
+        uint64_t rint_31                 : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npi_rsl_int_blocks_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rint_31                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
+        uint64_t rint_29                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_28                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_27                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_26                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_25                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_24                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t asx1                    : 1;       /**< ASX1_INT_REG */
+        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
+        uint64_t rint_21                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
+        uint64_t spx1                    : 1;       /**< SPX1_INT_REG & STX1_INT_REG */
+        uint64_t spx0                    : 1;       /**< SPX0_INT_REG & STX0_INT_REG */
+        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
+        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
+        uint64_t rint_15                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_14                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t usb                     : 1;       /**< USBN_INT_SUM */
+        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
+        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
+        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
+        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
+        uint64_t rint_8                  : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t zip                     : 1;       /**< ZIP_ERROR */
+        uint64_t dfa                     : 1;       /**< DFA_ERR */
+        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
+        uint64_t key                     : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
+        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
+#else
+        uint64_t mio                     : 1;
+        uint64_t gmx0                    : 1;
+        uint64_t gmx1                    : 1;
+        uint64_t npi                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t rint_8                  : 1;
+        uint64_t ipd                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t tim                     : 1;
+        uint64_t pow                     : 1;
+        uint64_t usb                     : 1;
+        uint64_t rint_14                 : 1;
+        uint64_t rint_15                 : 1;
+        uint64_t l2c                     : 1;
+        uint64_t lmc                     : 1;
+        uint64_t spx0                    : 1;
+        uint64_t spx1                    : 1;
+        uint64_t pip                     : 1;
+        uint64_t rint_21                 : 1;
+        uint64_t asx0                    : 1;
+        uint64_t asx1                    : 1;
+        uint64_t rint_24                 : 1;
+        uint64_t rint_25                 : 1;
+        uint64_t rint_26                 : 1;
+        uint64_t rint_27                 : 1;
+        uint64_t rint_28                 : 1;
+        uint64_t rint_29                 : 1;
+        uint64_t iob                     : 1;
+        uint64_t rint_31                 : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn30xx;
+    struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
+    struct cvmx_npi_rsl_int_blocks_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rint_31                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
+        uint64_t rint_29                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_28                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_27                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_26                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_25                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_24                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t asx1                    : 1;       /**< ASX1_INT_REG */
+        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
+        uint64_t rint_21                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
+        uint64_t spx1                    : 1;       /**< SPX1_INT_REG & STX1_INT_REG */
+        uint64_t spx0                    : 1;       /**< SPX0_INT_REG & STX0_INT_REG */
+        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
+        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
+        uint64_t rint_15                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_14                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t rint_13                 : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
+        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
+        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
+        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
+        uint64_t rint_8                  : 1;       /**< Set '1' when RSL bLock has an interrupt. */
+        uint64_t zip                     : 1;       /**< ZIP_ERROR */
+        uint64_t dfa                     : 1;       /**< DFA_ERR */
+        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
+        uint64_t key                     : 1;       /**< KEY_INT_SUM */
+        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
+        uint64_t gmx1                    : 1;       /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */
+        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
+#else
+        uint64_t mio                     : 1;
+        uint64_t gmx0                    : 1;
+        uint64_t gmx1                    : 1;
+        uint64_t npi                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t rint_8                  : 1;
+        uint64_t ipd                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t tim                     : 1;
+        uint64_t pow                     : 1;
+        uint64_t rint_13                 : 1;
+        uint64_t rint_14                 : 1;
+        uint64_t rint_15                 : 1;
+        uint64_t l2c                     : 1;
+        uint64_t lmc                     : 1;
+        uint64_t spx0                    : 1;
+        uint64_t spx1                    : 1;
+        uint64_t pip                     : 1;
+        uint64_t rint_21                 : 1;
+        uint64_t asx0                    : 1;
+        uint64_t asx1                    : 1;
+        uint64_t rint_24                 : 1;
+        uint64_t rint_25                 : 1;
+        uint64_t rint_26                 : 1;
+        uint64_t rint_27                 : 1;
+        uint64_t rint_28                 : 1;
+        uint64_t rint_29                 : 1;
+        uint64_t iob                     : 1;
+        uint64_t rint_31                 : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn38xx;
+    struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
+    struct cvmx_npi_rsl_int_blocks_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t iob                     : 1;       /**< IOB_INT_SUM */
+        uint64_t lmc1                    : 1;       /**< Always reads as zero */
+        uint64_t agl                     : 1;       /**< Always reads as zero */
+        uint64_t reserved_24_27          : 4;
+        uint64_t asx1                    : 1;       /**< Always reads as zero */
+        uint64_t asx0                    : 1;       /**< ASX0_INT_REG */
+        uint64_t reserved_21_21          : 1;
+        uint64_t pip                     : 1;       /**< PIP_INT_REG. */
+        uint64_t spx1                    : 1;       /**< Always reads as zero */
+        uint64_t spx0                    : 1;       /**< Always reads as zero */
+        uint64_t lmc                     : 1;       /**< LMC_MEM_CFG0 */
+        uint64_t l2c                     : 1;       /**< L2T_ERR & L2D_ERR */
+        uint64_t reserved_15_15          : 1;
+        uint64_t rad                     : 1;       /**< Always reads as zero */
+        uint64_t usb                     : 1;       /**< USBN_INT_SUM */
+        uint64_t pow                     : 1;       /**< POW_ECC_ERR */
+        uint64_t tim                     : 1;       /**< TIM_REG_ERROR */
+        uint64_t pko                     : 1;       /**< PKO_REG_ERROR */
+        uint64_t ipd                     : 1;       /**< IPD_INT_SUM */
+        uint64_t reserved_8_8            : 1;
+        uint64_t zip                     : 1;       /**< Always reads as zero */
+        uint64_t dfa                     : 1;       /**< Always reads as zero */
+        uint64_t fpa                     : 1;       /**< FPA_INT_SUM */
+        uint64_t key                     : 1;       /**< Always reads as zero */
+        uint64_t npi                     : 1;       /**< NPI_INT_SUM */
+        uint64_t gmx1                    : 1;       /**< Always reads as zero */
+        uint64_t gmx0                    : 1;       /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */
+        uint64_t mio                     : 1;       /**< MIO_BOOT_ERR */
+#else
+        uint64_t mio                     : 1;
+        uint64_t gmx0                    : 1;
+        uint64_t gmx1                    : 1;
+        uint64_t npi                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t reserved_8_8            : 1;
+        uint64_t ipd                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t tim                     : 1;
+        uint64_t pow                     : 1;
+        uint64_t usb                     : 1;
+        uint64_t rad                     : 1;
+        uint64_t reserved_15_15          : 1;
+        uint64_t l2c                     : 1;
+        uint64_t lmc                     : 1;
+        uint64_t spx0                    : 1;
+        uint64_t spx1                    : 1;
+        uint64_t pip                     : 1;
+        uint64_t reserved_21_21          : 1;
+        uint64_t asx0                    : 1;
+        uint64_t asx1                    : 1;
+        uint64_t reserved_24_27          : 4;
+        uint64_t agl                     : 1;
+        uint64_t lmc1                    : 1;
+        uint64_t iob                     : 1;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } cn50xx;
+    struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
+    struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
+} cvmx_npi_rsl_int_blocks_t;
+
+
+/**
+ * cvmx_npi_size_input#
+ *
+ * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register
+ * 
+ * The size (in instructions) of Instruction Queue-0.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_size_inputx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t size                    : 32;      /**< The size of the Instruction Queue used by Octane.
+                                                         The value [SIZE] is in Instructions.
+                                                         A value of 0 in this field is illegal. */
+#else
+        uint64_t size                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npi_size_inputx_s        cn30xx;
+    struct cvmx_npi_size_inputx_s        cn31xx;
+    struct cvmx_npi_size_inputx_s        cn38xx;
+    struct cvmx_npi_size_inputx_s        cn38xxp2;
+    struct cvmx_npi_size_inputx_s        cn50xx;
+    struct cvmx_npi_size_inputx_s        cn58xx;
+    struct cvmx_npi_size_inputx_s        cn58xxp1;
+} cvmx_npi_size_inputx_t;
+
+
+/**
+ * cvmx_npi_win_read_to
+ *
+ * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register
+ * 
+ * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_npi_win_read_to_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t time                    : 32;      /**< Time to wait in core clocks. A value of 0 will
+                                                         cause no timeouts. */
+#else
+        uint64_t time                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_npi_win_read_to_s        cn30xx;
+    struct cvmx_npi_win_read_to_s        cn31xx;
+    struct cvmx_npi_win_read_to_s        cn38xx;
+    struct cvmx_npi_win_read_to_s        cn38xxp2;
+    struct cvmx_npi_win_read_to_s        cn50xx;
+    struct cvmx_npi_win_read_to_s        cn58xx;
+    struct cvmx_npi_win_read_to_s        cn58xxp1;
+} cvmx_npi_win_read_to_t;
+
+
+/**
+ * cvmx_pci_bar1_index#
+ *
+ * PCI_BAR1_INDEXX = PCI IndexX Register
+ * 
+ * Contains address index and control bits for access to memory ranges of Bar-1,
+ * when PCI supplied address-bits [26:22] == X.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_bar1_indexx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_18_31          : 14;
+        uint32_t addr_idx                : 14;      /**< Address bits [35:22] sent to L2C */
+        uint32_t ca                      : 1;       /**< Set '1' when access is not to be cached in L2. */
+        uint32_t end_swp                 : 2;       /**< Endian Swap Mode */
+        uint32_t addr_v                  : 1;       /**< Set '1' when the selected address range is valid. */
+#else
+        uint32_t addr_v                  : 1;
+        uint32_t end_swp                 : 2;
+        uint32_t ca                      : 1;
+        uint32_t addr_idx                : 14;
+        uint32_t reserved_18_31          : 14;
+#endif
+    } s;
+    struct cvmx_pci_bar1_indexx_s        cn30xx;
+    struct cvmx_pci_bar1_indexx_s        cn31xx;
+    struct cvmx_pci_bar1_indexx_s        cn38xx;
+    struct cvmx_pci_bar1_indexx_s        cn38xxp2;
+    struct cvmx_pci_bar1_indexx_s        cn50xx;
+    struct cvmx_pci_bar1_indexx_s        cn58xx;
+    struct cvmx_pci_bar1_indexx_s        cn58xxp1;
+} cvmx_pci_bar1_indexx_t;
+
+
+/**
+ * cvmx_pci_bist_reg
+ *
+ * PCI_BIST_REG = PCI PNI BIST Status Register
+ * 
+ * Contains the bist results for the PNI memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_bist_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t rsp_bs                  : 1;       /**< Bist Status For b12_rsp_fifo_bist
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t dma0_bs                 : 1;       /**< Bist Status For dmao_count
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t cmd0_bs                 : 1;       /**< Bist Status For npi_cmd0_pni_am0
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t cmd_bs                  : 1;       /**< Bist Status For npi_cmd_pni_am1
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t csr2p_bs                : 1;       /**< Bist Status For npi_csr_2_pni_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t csrr_bs                 : 1;       /**< Bist Status For npi_csr_rsp_2_pni_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t rsp2p_bs                : 1;       /**< Bist Status For npi_rsp_2_pni_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t csr2n_bs                : 1;       /**< Bist Status For pni_csr_2_npi_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t dat2n_bs                : 1;       /**< Bist Status For pni_data_2_npi_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+        uint64_t dbg2n_bs                : 1;       /**< Bist Status For pni_dbg_data_2_npi_am
+                                                         The value of this register is available 100,000
+                                                         core clocks + 21,000 pclks after:
+                                                         Host Mode - deassertion of pci_rst_n
+                                                         Non Host Mode - deassertion of pci_rst_n */
+#else
+        uint64_t dbg2n_bs                : 1;
+        uint64_t dat2n_bs                : 1;
+        uint64_t csr2n_bs                : 1;
+        uint64_t rsp2p_bs                : 1;
+        uint64_t csrr_bs                 : 1;
+        uint64_t csr2p_bs                : 1;
+        uint64_t cmd_bs                  : 1;
+        uint64_t cmd0_bs                 : 1;
+        uint64_t dma0_bs                 : 1;
+        uint64_t rsp_bs                  : 1;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_pci_bist_reg_s           cn50xx;
+} cvmx_pci_bist_reg_t;
+
+
+/**
+ * cvmx_pci_cfg00
+ *
+ * Registers at address 0x1000 -> 0x17FF are PNI
+ * Start at 0x100 into range
+ * these are shifted by 2 to the left to make address
+ *                Registers at address 0x1800 -> 0x18FF are CFG
+ * these are shifted by 2 to the left to make address
+ * 
+ *           PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device)
+ * 
+ * This register contains the first 32-bits of the PCI config space registers
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg00_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t devid                   : 16;      /**< This is the device ID for OCTEON (90nm shhrink) */
+        uint32_t vendid                  : 16;      /**< This is the Cavium's vendor ID */
+#else
+        uint32_t vendid                  : 16;
+        uint32_t devid                   : 16;
+#endif
+    } s;
+    struct cvmx_pci_cfg00_s              cn30xx;
+    struct cvmx_pci_cfg00_s              cn31xx;
+    struct cvmx_pci_cfg00_s              cn38xx;
+    struct cvmx_pci_cfg00_s              cn38xxp2;
+    struct cvmx_pci_cfg00_s              cn50xx;
+    struct cvmx_pci_cfg00_s              cn58xx;
+    struct cvmx_pci_cfg00_s              cn58xxp1;
+} cvmx_pci_cfg00_t;
+
+
+/**
+ * cvmx_pci_cfg01
+ *
+ * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg01_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dpe                     : 1;       /**< Detected Parity Error */
+        uint32_t sse                     : 1;       /**< Signaled System Error */
+        uint32_t rma                     : 1;       /**< Received Master Abort */
+        uint32_t rta                     : 1;       /**< Received Target Abort */
+        uint32_t sta                     : 1;       /**< Signaled Target Abort */
+        uint32_t devt                    : 2;       /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */
+        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
+        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Transactions Capable
+                                                         Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */
+        uint32_t reserved_22_22          : 1;
+        uint32_t m66                     : 1;       /**< 66MHz Capable */
+        uint32_t cle                     : 1;       /**< Capabilities List Enable */
+        uint32_t i_stat                  : 1;       /**< When INTx# is asserted by OCTEON this bit will be set.
+                                                         When deasserted by OCTEON this bit will be cleared. */
+        uint32_t reserved_11_18          : 8;
+        uint32_t i_dis                   : 1;       /**< When asserted '1' disables the generation of INTx#
+                                                         by OCTEON. When disabled '0' allows assertion of INTx#
+                                                         by OCTEON. */
+        uint32_t fbbe                    : 1;       /**< Fast Back to Back Transaction Enable */
+        uint32_t see                     : 1;       /**< System Error Enable */
+        uint32_t ads                     : 1;       /**< Address/Data Stepping
+                                                         NOTE: Octeon does NOT support address/data stepping. */
+        uint32_t pee                     : 1;       /**< PERR# Enable */
+        uint32_t vps                     : 1;       /**< VGA Palette Snooping */
+        uint32_t mwice                   : 1;       /**< Memory Write & Invalidate Command Enable */
+        uint32_t scse                    : 1;       /**< Special Cycle Snooping Enable */
+        uint32_t me                      : 1;       /**< Master Enable
+                                                         Must be set for OCTEON to master a PCI/PCI-X
+                                                         transaction. This should always be set any time
+                                                         that OCTEON is connected to a PCI/PCI-X bus. */
+        uint32_t msae                    : 1;       /**< Memory Space Access Enable
+                                                         Must be set to recieve a PCI/PCI-X memory space
+                                                         transaction. This must always be set any time that
+                                                         OCTEON is connected to a PCI/PCI-X bus. */
+        uint32_t isae                    : 1;       /**< I/O Space Access Enable
+                                                         NOTE: For OCTEON, this bit MUST NEVER be set
+                                                         (it is read-only and OCTEON does not respond to I/O
+                                                         Space accesses). */
+#else
+        uint32_t isae                    : 1;
+        uint32_t msae                    : 1;
+        uint32_t me                      : 1;
+        uint32_t scse                    : 1;
+        uint32_t mwice                   : 1;
+        uint32_t vps                     : 1;
+        uint32_t pee                     : 1;
+        uint32_t ads                     : 1;
+        uint32_t see                     : 1;
+        uint32_t fbbe                    : 1;
+        uint32_t i_dis                   : 1;
+        uint32_t reserved_11_18          : 8;
+        uint32_t i_stat                  : 1;
+        uint32_t cle                     : 1;
+        uint32_t m66                     : 1;
+        uint32_t reserved_22_22          : 1;
+        uint32_t fbb                     : 1;
+        uint32_t mdpe                    : 1;
+        uint32_t devt                    : 2;
+        uint32_t sta                     : 1;
+        uint32_t rta                     : 1;
+        uint32_t rma                     : 1;
+        uint32_t sse                     : 1;
+        uint32_t dpe                     : 1;
+#endif
+    } s;
+    struct cvmx_pci_cfg01_s              cn30xx;
+    struct cvmx_pci_cfg01_s              cn31xx;
+    struct cvmx_pci_cfg01_s              cn38xx;
+    struct cvmx_pci_cfg01_s              cn38xxp2;
+    struct cvmx_pci_cfg01_s              cn50xx;
+    struct cvmx_pci_cfg01_s              cn58xx;
+    struct cvmx_pci_cfg01_s              cn58xxp1;
+} cvmx_pci_cfg01_t;
+
+
+/**
+ * cvmx_pci_cfg02
+ *
+ * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg02_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t cc                      : 24;      /**< Class Code (Processor/MIPS)
+                                                         (was 0x100000 in pass 1 and pass 2) */
+        uint32_t rid                     : 8;       /**< Revision ID
+                                                         (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */
+#else
+        uint32_t rid                     : 8;
+        uint32_t cc                      : 24;
+#endif
+    } s;
+    struct cvmx_pci_cfg02_s              cn30xx;
+    struct cvmx_pci_cfg02_s              cn31xx;
+    struct cvmx_pci_cfg02_s              cn38xx;
+    struct cvmx_pci_cfg02_s              cn38xxp2;
+    struct cvmx_pci_cfg02_s              cn50xx;
+    struct cvmx_pci_cfg02_s              cn58xx;
+    struct cvmx_pci_cfg02_s              cn58xxp1;
+} cvmx_pci_cfg02_t;
+
+
+/**
+ * cvmx_pci_cfg03
+ *
+ * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg03_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t bcap                    : 1;       /**< BIST Capable */
+        uint32_t brb                     : 1;       /**< BIST Request/busy bit
+                                                         Note: OCTEON does not support PCI BIST, therefore
+                                                         this bit should remain zero. */
+        uint32_t reserved_28_29          : 2;
+        uint32_t bcod                    : 4;       /**< BIST Code */
+        uint32_t ht                      : 8;       /**< Header Type (Type 0) */
+        uint32_t lt                      : 8;       /**< Latency Timer
+                                                         (0=PCI)                 (0=PCI)
+                                                         (0x40=PCIX)             (0x40=PCIX) */
+        uint32_t cls                     : 8;       /**< Cache Line Size */
+#else
+        uint32_t cls                     : 8;
+        uint32_t lt                      : 8;
+        uint32_t ht                      : 8;
+        uint32_t bcod                    : 4;
+        uint32_t reserved_28_29          : 2;
+        uint32_t brb                     : 1;
+        uint32_t bcap                    : 1;
+#endif
+    } s;
+    struct cvmx_pci_cfg03_s              cn30xx;
+    struct cvmx_pci_cfg03_s              cn31xx;
+    struct cvmx_pci_cfg03_s              cn38xx;
+    struct cvmx_pci_cfg03_s              cn38xxp2;
+    struct cvmx_pci_cfg03_s              cn50xx;
+    struct cvmx_pci_cfg03_s              cn58xx;
+    struct cvmx_pci_cfg03_s              cn58xxp1;
+} cvmx_pci_cfg03_t;
+
+
+/**
+ * cvmx_pci_cfg04
+ *
+ * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low)
+ * 
+ * Description: BAR0: 4KB 64-bit Prefetchable Memory Space
+ *       [0]:     0 (Memory Space)
+ *       [2:1]:   2 (64bit memory decoder)
+ *       [3]:     1 (Prefetchable)
+ *       [11:4]:  RAZ (to imply 4KB space)
+ *       [31:12]: RW (User may define base address)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg04_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lbase                   : 20;      /**< Base Address[31:12]
+                                                         Base Address[30:12] read as zero if
+                                                         PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */
+        uint32_t lbasez                  : 8;       /**< Base Address[11:4] (Read as Zero) */
+        uint32_t pf                      : 1;       /**< Prefetchable Space */
+        uint32_t typ                     : 2;       /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
+        uint32_t mspc                    : 1;       /**< Memory Space Indicator */
+#else
+        uint32_t mspc                    : 1;
+        uint32_t typ                     : 2;
+        uint32_t pf                      : 1;
+        uint32_t lbasez                  : 8;
+        uint32_t lbase                   : 20;
+#endif
+    } s;
+    struct cvmx_pci_cfg04_s              cn30xx;
+    struct cvmx_pci_cfg04_s              cn31xx;
+    struct cvmx_pci_cfg04_s              cn38xx;
+    struct cvmx_pci_cfg04_s              cn38xxp2;
+    struct cvmx_pci_cfg04_s              cn50xx;
+    struct cvmx_pci_cfg04_s              cn58xx;
+    struct cvmx_pci_cfg04_s              cn58xxp1;
+} cvmx_pci_cfg04_t;
+
+
+/**
+ * cvmx_pci_cfg05
+ *
+ * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg05_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t hbase                   : 32;      /**< Base Address[63:32] */
+#else
+        uint32_t hbase                   : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg05_s              cn30xx;
+    struct cvmx_pci_cfg05_s              cn31xx;
+    struct cvmx_pci_cfg05_s              cn38xx;
+    struct cvmx_pci_cfg05_s              cn38xxp2;
+    struct cvmx_pci_cfg05_s              cn50xx;
+    struct cvmx_pci_cfg05_s              cn58xx;
+    struct cvmx_pci_cfg05_s              cn58xxp1;
+} cvmx_pci_cfg05_t;
+
+
+/**
+ * cvmx_pci_cfg06
+ *
+ * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low)
+ * 
+ * Description: BAR1: 128MB 64-bit Prefetchable Memory Space
+ *       [0]:     0 (Memory Space)
+ *       [2:1]:   2 (64bit memory decoder)
+ *       [3]:     1 (Prefetchable)
+ *       [26:4]:  RAZ (to imply 128MB space)
+ *       [31:27]: RW (User may define base address)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg06_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lbase                   : 5;       /**< Base Address[31:27]
+                                                         In pass 3+:
+                                                           Base Address[29:27] read as zero if
+                                                            PCI_CTL_STATUS_2[BB1] is set
+                                                           Base Address[30] reads as zero if
+                                                            PCI_CTL_STATUS_2[BB1] is set and
+                                                            PCI_CTL_STATUS_2[BB1_SIZE] is set */
+        uint32_t lbasez                  : 23;      /**< Base Address[26:4] (Read as Zero) */
+        uint32_t pf                      : 1;       /**< Prefetchable Space */
+        uint32_t typ                     : 2;       /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
+        uint32_t mspc                    : 1;       /**< Memory Space Indicator */
+#else
+        uint32_t mspc                    : 1;
+        uint32_t typ                     : 2;
+        uint32_t pf                      : 1;
+        uint32_t lbasez                  : 23;
+        uint32_t lbase                   : 5;
+#endif
+    } s;
+    struct cvmx_pci_cfg06_s              cn30xx;
+    struct cvmx_pci_cfg06_s              cn31xx;
+    struct cvmx_pci_cfg06_s              cn38xx;
+    struct cvmx_pci_cfg06_s              cn38xxp2;
+    struct cvmx_pci_cfg06_s              cn50xx;
+    struct cvmx_pci_cfg06_s              cn58xx;
+    struct cvmx_pci_cfg06_s              cn58xxp1;
+} cvmx_pci_cfg06_t;
+
+
+/**
+ * cvmx_pci_cfg07
+ *
+ * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg07_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t hbase                   : 32;      /**< Base Address[63:32] */
+#else
+        uint32_t hbase                   : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg07_s              cn30xx;
+    struct cvmx_pci_cfg07_s              cn31xx;
+    struct cvmx_pci_cfg07_s              cn38xx;
+    struct cvmx_pci_cfg07_s              cn38xxp2;
+    struct cvmx_pci_cfg07_s              cn50xx;
+    struct cvmx_pci_cfg07_s              cn58xx;
+    struct cvmx_pci_cfg07_s              cn58xxp1;
+} cvmx_pci_cfg07_t;
+
+
+/**
+ * cvmx_pci_cfg08
+ *
+ * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low)
+ * 
+ * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space
+ *       [0]:     0 (Memory Space)
+ *       [2:1]:   2 (64bit memory decoder)
+ *       [3]:     1 (Prefetchable)
+ *       [31:4]:  RAZ
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg08_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lbasez                  : 28;      /**< Base Address[31:4] (Read as Zero) */
+        uint32_t pf                      : 1;       /**< Prefetchable Space */
+        uint32_t typ                     : 2;       /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */
+        uint32_t mspc                    : 1;       /**< Memory Space Indicator */
+#else
+        uint32_t mspc                    : 1;
+        uint32_t typ                     : 2;
+        uint32_t pf                      : 1;
+        uint32_t lbasez                  : 28;
+#endif
+    } s;
+    struct cvmx_pci_cfg08_s              cn30xx;
+    struct cvmx_pci_cfg08_s              cn31xx;
+    struct cvmx_pci_cfg08_s              cn38xx;
+    struct cvmx_pci_cfg08_s              cn38xxp2;
+    struct cvmx_pci_cfg08_s              cn50xx;
+    struct cvmx_pci_cfg08_s              cn58xx;
+    struct cvmx_pci_cfg08_s              cn58xxp1;
+} cvmx_pci_cfg08_t;
+
+
+/**
+ * cvmx_pci_cfg09
+ *
+ * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg09_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t hbase                   : 25;      /**< Base Address[63:39] */
+        uint32_t hbasez                  : 7;       /**< Base Address[38:31]  (Read as Zero) */
+#else
+        uint32_t hbasez                  : 7;
+        uint32_t hbase                   : 25;
+#endif
+    } s;
+    struct cvmx_pci_cfg09_s              cn30xx;
+    struct cvmx_pci_cfg09_s              cn31xx;
+    struct cvmx_pci_cfg09_s              cn38xx;
+    struct cvmx_pci_cfg09_s              cn38xxp2;
+    struct cvmx_pci_cfg09_s              cn50xx;
+    struct cvmx_pci_cfg09_s              cn58xx;
+    struct cvmx_pci_cfg09_s              cn58xxp1;
+} cvmx_pci_cfg09_t;
+
+
+/**
+ * cvmx_pci_cfg10
+ *
+ * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg10_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t cisp                    : 32;      /**< CardBus CIS Pointer (UNUSED) */
+#else
+        uint32_t cisp                    : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg10_s              cn30xx;
+    struct cvmx_pci_cfg10_s              cn31xx;
+    struct cvmx_pci_cfg10_s              cn38xx;
+    struct cvmx_pci_cfg10_s              cn38xxp2;
+    struct cvmx_pci_cfg10_s              cn50xx;
+    struct cvmx_pci_cfg10_s              cn58xx;
+    struct cvmx_pci_cfg10_s              cn58xxp1;
+} cvmx_pci_cfg10_t;
+
+
+/**
+ * cvmx_pci_cfg11
+ *
+ * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg11_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ssid                    : 16;      /**< SubSystem ID */
+        uint32_t ssvid                   : 16;      /**< Subsystem Vendor ID */
+#else
+        uint32_t ssvid                   : 16;
+        uint32_t ssid                    : 16;
+#endif
+    } s;
+    struct cvmx_pci_cfg11_s              cn30xx;
+    struct cvmx_pci_cfg11_s              cn31xx;
+    struct cvmx_pci_cfg11_s              cn38xx;
+    struct cvmx_pci_cfg11_s              cn38xxp2;
+    struct cvmx_pci_cfg11_s              cn50xx;
+    struct cvmx_pci_cfg11_s              cn58xx;
+    struct cvmx_pci_cfg11_s              cn58xxp1;
+} cvmx_pci_cfg11_t;
+
+
+/**
+ * cvmx_pci_cfg12
+ *
+ * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg12_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t erbar                   : 16;      /**< Expansion ROM Base Address[31:16] 64KB in size */
+        uint32_t erbarz                  : 5;       /**< Expansion ROM Base Base Address (Read as Zero) */
+        uint32_t reserved_1_10           : 10;
+        uint32_t erbar_en                : 1;       /**< Expansion ROM Address Decode Enable */
+#else
+        uint32_t erbar_en                : 1;
+        uint32_t reserved_1_10           : 10;
+        uint32_t erbarz                  : 5;
+        uint32_t erbar                   : 16;
+#endif
+    } s;
+    struct cvmx_pci_cfg12_s              cn30xx;
+    struct cvmx_pci_cfg12_s              cn31xx;
+    struct cvmx_pci_cfg12_s              cn38xx;
+    struct cvmx_pci_cfg12_s              cn38xxp2;
+    struct cvmx_pci_cfg12_s              cn50xx;
+    struct cvmx_pci_cfg12_s              cn58xx;
+    struct cvmx_pci_cfg12_s              cn58xxp1;
+} cvmx_pci_cfg12_t;
+
+
+/**
+ * cvmx_pci_cfg13
+ *
+ * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg13_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_8_31           : 24;
+        uint32_t cp                      : 8;       /**< Capabilities Pointer */
+#else
+        uint32_t cp                      : 8;
+        uint32_t reserved_8_31           : 24;
+#endif
+    } s;
+    struct cvmx_pci_cfg13_s              cn30xx;
+    struct cvmx_pci_cfg13_s              cn31xx;
+    struct cvmx_pci_cfg13_s              cn38xx;
+    struct cvmx_pci_cfg13_s              cn38xxp2;
+    struct cvmx_pci_cfg13_s              cn50xx;
+    struct cvmx_pci_cfg13_s              cn58xx;
+    struct cvmx_pci_cfg13_s              cn58xxp1;
+} cvmx_pci_cfg13_t;
+
+
+/**
+ * cvmx_pci_cfg15
+ *
+ * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg15_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ml                      : 8;       /**< Maximum Latency */
+        uint32_t mg                      : 8;       /**< Minimum Grant */
+        uint32_t inta                    : 8;       /**< Interrupt Pin (INTA#) */
+        uint32_t il                      : 8;       /**< Interrupt Line */
+#else
+        uint32_t il                      : 8;
+        uint32_t inta                    : 8;
+        uint32_t mg                      : 8;
+        uint32_t ml                      : 8;
+#endif
+    } s;
+    struct cvmx_pci_cfg15_s              cn30xx;
+    struct cvmx_pci_cfg15_s              cn31xx;
+    struct cvmx_pci_cfg15_s              cn38xx;
+    struct cvmx_pci_cfg15_s              cn38xxp2;
+    struct cvmx_pci_cfg15_s              cn50xx;
+    struct cvmx_pci_cfg15_s              cn58xx;
+    struct cvmx_pci_cfg15_s              cn58xxp1;
+} cvmx_pci_cfg15_t;
+
+
+/**
+ * cvmx_pci_cfg16
+ *
+ * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg16_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t trdnpr                  : 1;       /**< Target Read Delayed Transaction for I/O and
+                                                         non-prefetchable regions discarded. */
+        uint32_t trdard                  : 1;       /**< Target Read Delayed Transaction for all regions
+                                                         discarded. */
+        uint32_t rdsati                  : 1;       /**< Target(I/O and Memory) Read Delayed/Split at
+                                                          timeout/immediately (default timeout).
+                                                         Note: OCTEON requires that this bit MBZ(must be zero). */
+        uint32_t trdrs                   : 1;       /**< Target(I/O and Memory) Read Delayed/Split or Retry
+                                                         select (of the application interface is not ready)
+                                                          0 = Delayed Split Transaction
+                                                          1 = Retry Transaction (always Immediate Retry, no
+                                                              AT_REQ to application). */
+        uint32_t trtae                   : 1;       /**< Target(I/O and Memory) Read Target Abort Enable
+                                                         (if application interface is not ready at the
+                                                         latency timeout).
+                                                         Note: OCTEON as target will never target-abort,
+                                                         therefore this bit should never be set. */
+        uint32_t twsei                   : 1;       /**< Target(I/O) Write Split Enable (at timeout /
+                                                         immediately; default timeout) */
+        uint32_t twsen                   : 1;       /**< T(I/O) write split Enable (if the application
+                                                         interface is not ready) */
+        uint32_t twtae                   : 1;       /**< Target(I/O and Memory) Write Target Abort Enable
+                                                         (if the application interface is not ready at the
+                                                         start of the cycle).
+                                                         Note: OCTEON as target will never target-abort,
+                                                         therefore this bit should never be set. */
+        uint32_t tmae                    : 1;       /**< Target(Read/Write) Master Abort Enable; check
+                                                         at the start of each transaction.
+                                                         Note: This bit can be used to force a Master
+                                                         Abort when OCTEON is acting as the intended target
+                                                         device. */
+        uint32_t tslte                   : 3;       /**< Target Subsequent(2nd-last) Latency Timeout Enable
+                                                         Valid range: [1..7] and 0=8. */
+        uint32_t tilt                    : 4;       /**< Target Initial(1st data) Latency Timeout in PCI
+                                                         ModeValid range: [8..15] and 0=16. */
+        uint32_t pbe                     : 12;      /**< Programmable Boundary Enable to disconnect/prefetch
+                                                         for target burst read cycles to prefetchable
+                                                         region in PCI. A value of 1 indicates end of
+                                                         boundary (64 KB down to 16 Bytes). */
+        uint32_t dppmr                   : 1;       /**< Disconnect/Prefetch to prefetchable memory
+                                                         regions Enable. Prefetchable memory regions
+                                                         are always disconnected on a region boundary.
+                                                         Non-prefetchable regions for PCI are always
+                                                         disconnected on the first transfer.
+                                                         Note: OCTEON as target will never target-disconnect,
+                                                         therefore this bit should never be set. */
+        uint32_t reserved_2_2            : 1;
+        uint32_t tswc                    : 1;       /**< Target Split Write Control
+                                                         0 = Blocks all requests except PMW
+                                                         1 = Blocks all requests including PMW until
+                                                             split completion occurs. */
+        uint32_t mltd                    : 1;       /**< Master Latency Timer Disable
+                                                         Note: For OCTEON, it is recommended that this bit
+                                                         be set(to disable the Master Latency timer). */
+#else
+        uint32_t mltd                    : 1;
+        uint32_t tswc                    : 1;
+        uint32_t reserved_2_2            : 1;
+        uint32_t dppmr                   : 1;
+        uint32_t pbe                     : 12;
+        uint32_t tilt                    : 4;
+        uint32_t tslte                   : 3;
+        uint32_t tmae                    : 1;
+        uint32_t twtae                   : 1;
+        uint32_t twsen                   : 1;
+        uint32_t twsei                   : 1;
+        uint32_t trtae                   : 1;
+        uint32_t trdrs                   : 1;
+        uint32_t rdsati                  : 1;
+        uint32_t trdard                  : 1;
+        uint32_t trdnpr                  : 1;
+#endif
+    } s;
+    struct cvmx_pci_cfg16_s              cn30xx;
+    struct cvmx_pci_cfg16_s              cn31xx;
+    struct cvmx_pci_cfg16_s              cn38xx;
+    struct cvmx_pci_cfg16_s              cn38xxp2;
+    struct cvmx_pci_cfg16_s              cn50xx;
+    struct cvmx_pci_cfg16_s              cn58xx;
+    struct cvmx_pci_cfg16_s              cn58xxp1;
+} cvmx_pci_cfg16_t;
+
+
+/**
+ * cvmx_pci_cfg17
+ *
+ * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message
+ * Enable Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg17_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t tscme                   : 32;      /**< Target Split Completion Message Enable
+                                                          [31:30]: 00
+                                                          [29]: Split Completion Error Indication
+                                                          [28]: 0
+                                                          [27:20]: Split Completion Message Index
+                                                          [19:0]: 0x00000
+                                                         For OCTEON, this register is intended for debug use
+                                                         only. (as such, it is recommended NOT to be written
+                                                         with anything other than ZEROES). */
+#else
+        uint32_t tscme                   : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg17_s              cn30xx;
+    struct cvmx_pci_cfg17_s              cn31xx;
+    struct cvmx_pci_cfg17_s              cn38xx;
+    struct cvmx_pci_cfg17_s              cn38xxp2;
+    struct cvmx_pci_cfg17_s              cn50xx;
+    struct cvmx_pci_cfg17_s              cn58xx;
+    struct cvmx_pci_cfg17_s              cn58xxp1;
+} cvmx_pci_cfg17_t;
+
+
+/**
+ * cvmx_pci_cfg18
+ *
+ * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request
+ * Pending Sequences)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg18_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t tdsrps                  : 32;      /**< Target Delayed/Split Request Pending Sequences
+                                                         The application uses this address to remove a
+                                                         pending split sequence from the target queue by
+                                                         clearing the appropriate bit. Example: Clearing [14]
+                                                         clears the pending sequence \#14. An application
+                                                         or configuration write to this address can clear this
+                                                         register.
+                                                         For OCTEON, this register is intended for debug use
+                                                         only and MUST NEVER be written with anything other
+                                                         than ZEROES. */
+#else
+        uint32_t tdsrps                  : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg18_s              cn30xx;
+    struct cvmx_pci_cfg18_s              cn31xx;
+    struct cvmx_pci_cfg18_s              cn38xx;
+    struct cvmx_pci_cfg18_s              cn38xxp2;
+    struct cvmx_pci_cfg18_s              cn50xx;
+    struct cvmx_pci_cfg18_s              cn58xx;
+    struct cvmx_pci_cfg18_s              cn58xxp1;
+} cvmx_pci_cfg18_t;
+
+
+/**
+ * cvmx_pci_cfg19
+ *
+ * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg19_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t mrbcm                   : 1;       /**< Master Request (Memory Read) Byte Count/Byte
+                                                         Enable select.
+                                                           0 = Byte Enables valid. In PCI mode, a burst
+                                                               transaction cannot be performed using
+                                                               Memory Read command=4'h6.
+                                                           1 = DWORD Byte Count valid (default). In PCI
+                                                               Mode, the memory read byte enables are
+                                                               automatically generated by the core.
+                                                          NOTE:  For OCTEON, this bit must always be one
+                                                          for proper operation. */
+        uint32_t mrbci                   : 1;       /**< Master Request (I/O and CR cycles) byte count/byte
+                                                         enable select.
+                                                           0 = Byte Enables valid (default)
+                                                           1 = DWORD byte count valid
+                                                          NOTE: For OCTEON, this bit must always be zero
+                                                          for proper operation (in support of
+                                                          Type0/1 Cfg Space accesses which require byte
+                                                          enable generation directly from a read mask). */
+        uint32_t mdwe                    : 1;       /**< Master (Retry) Deferred Write Enable (allow
+                                                         read requests to pass).
+                                                          NOTE: Applicable to PCI Mode I/O and memory
+                                                          transactions only.
+                                                           0 = New read requests are NOT accepted until
+                                                               the current write cycle completes. [Reads
+                                                               cannot pass writes]
+                                                           1 = New read requests are accepted, even when
+                                                               there is a write cycle pending [Reads can
+                                                               pass writes].
+                                                          NOTE: For OCTEON, this bit must always be zero
+                                                          for proper operation. */
+        uint32_t mdre                    : 1;       /**< Master (Retry) Deferred Read Enable (Allows
+                                                         read/write requests to pass).
+                                                          NOTE: Applicable to PCI mode I/O and memory
+                                                          transactions only.
+                                                           0 = New read/write requests are NOT accepted
+                                                               until the current read cycle completes.
+                                                               [Read/write requests CANNOT pass reads]
+                                                           1 = New read/write requests are accepted, even
+                                                               when there is a read cycle pending.
+                                                               [Read/write requests CAN pass reads]
+                                                          NOTE: For OCTEON, this bit must always be zero
+                                                          for proper operation. */
+        uint32_t mdrimc                  : 1;       /**< Master I/O Deferred/Split Request Outstanding
+                                                         Maximum Count
+                                                           0 = MDRRMC[26:24]
+                                                           1 = 1 */
+        uint32_t mdrrmc                  : 3;       /**< Master Deferred Read Request Outstanding Max
+                                                         Count (PCI only).
+                                                          CR4C[26:24]  Max SAC cycles   MAX DAC cycles
+                                                           000              8                4
+                                                           001              1                0
+                                                           010              2                1
+                                                           011              3                1
+                                                           100              4                2
+                                                           101              5                2
+                                                           110              6                3
+                                                           111              7                3
+                                                          For example, if these bits are programmed to
+                                                          100, the core can support 2 DAC cycles, 4 SAC
+                                                          cycles or a combination of 1 DAC and 2 SAC cycles.
+                                                          NOTE: For the PCI-X maximum outstanding split
+                                                          transactions, refer to CRE0[22:20] */
+        uint32_t tmes                    : 8;       /**< Target/Master Error Sequence \# */
+        uint32_t teci                    : 1;       /**< Target Error Command Indication
+                                                         0 = Delayed/Split
+                                                         1 = Others */
+        uint32_t tmei                    : 1;       /**< Target/Master Error Indication
+                                                         0 = Target
+                                                         1 = Master */
+        uint32_t tmse                    : 1;       /**< Target/Master System Error. This bit is set
+                                                         whenever ATM_SERR_O is active. */
+        uint32_t tmdpes                  : 1;       /**< Target/Master Data PERR# error status. This
+                                                         bit is set whenever ATM_DATA_PERR_O is active. */
+        uint32_t tmapes                  : 1;       /**< Target/Master Address PERR# error status. This
+                                                         bit is set whenever ATM_ADDR_PERR_O is active. */
+        uint32_t reserved_9_10           : 2;
+        uint32_t tibcd                   : 1;       /**< Target Illegal I/O DWORD byte combinations detected. */
+        uint32_t tibde                   : 1;       /**< Target Illegal I/O DWORD byte detection enable */
+        uint32_t reserved_6_6            : 1;
+        uint32_t tidomc                  : 1;       /**< Target I/O Delayed/Split request outstanding
+                                                         maximum count.
+                                                          0 = TDOMC[4:0]
+                                                          1 = 1 */
+        uint32_t tdomc                   : 5;       /**< Target Delayed/Split request outstanding maximum
+                                                         count. [1..31] and 0=32.
+                                                         NOTE: If the user programs these bits beyond the
+                                                         Designed Maximum outstanding count, then the
+                                                         designed maximum table depth will be used instead.
+                                                         No additional Deferred/Split transactions will be
+                                                         accepted if this outstanding maximum count
+                                                         is reached. Furthermore, no additional
+                                                         deferred/split transactions will be accepted if
+                                                         the I/O delay/ I/O Split Request outstanding
+                                                         maximum is reached.
+                                                         NOTE: For OCTEON in PCI Mode, this field MUST BE
+                                                         programmed to 1. (OCTEON can only handle 1 delayed
+                                                         read at a time).
+                                                         For OCTEON in PCIX Mode, this field can range from
+                                                         1-4. (The designed maximum table depth is 4
+                                                         for PCIX mode splits). */
+#else
+        uint32_t tdomc                   : 5;
+        uint32_t tidomc                  : 1;
+        uint32_t reserved_6_6            : 1;
+        uint32_t tibde                   : 1;
+        uint32_t tibcd                   : 1;
+        uint32_t reserved_9_10           : 2;
+        uint32_t tmapes                  : 1;
+        uint32_t tmdpes                  : 1;
+        uint32_t tmse                    : 1;
+        uint32_t tmei                    : 1;
+        uint32_t teci                    : 1;
+        uint32_t tmes                    : 8;
+        uint32_t mdrrmc                  : 3;
+        uint32_t mdrimc                  : 1;
+        uint32_t mdre                    : 1;
+        uint32_t mdwe                    : 1;
+        uint32_t mrbci                   : 1;
+        uint32_t mrbcm                   : 1;
+#endif
+    } s;
+    struct cvmx_pci_cfg19_s              cn30xx;
+    struct cvmx_pci_cfg19_s              cn31xx;
+    struct cvmx_pci_cfg19_s              cn38xx;
+    struct cvmx_pci_cfg19_s              cn38xxp2;
+    struct cvmx_pci_cfg19_s              cn50xx;
+    struct cvmx_pci_cfg19_s              cn58xx;
+    struct cvmx_pci_cfg19_s              cn58xxp1;
+} cvmx_pci_cfg19_t;
+
+
+/**
+ * cvmx_pci_cfg20
+ *
+ * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg20_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t mdsp                    : 32;      /**< Master Deferred/Split sequence Pending
+                                                         For OCTEON, this register is intended for debug use
+                                                         only and MUST NEVER be written with anything other
+                                                         than ZEROES. */
+#else
+        uint32_t mdsp                    : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg20_s              cn30xx;
+    struct cvmx_pci_cfg20_s              cn31xx;
+    struct cvmx_pci_cfg20_s              cn38xx;
+    struct cvmx_pci_cfg20_s              cn38xxp2;
+    struct cvmx_pci_cfg20_s              cn50xx;
+    struct cvmx_pci_cfg20_s              cn58xx;
+    struct cvmx_pci_cfg20_s              cn58xxp1;
+} cvmx_pci_cfg20_t;
+
+
+/**
+ * cvmx_pci_cfg21
+ *
+ * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg21_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t scmre                   : 32;      /**< Master Split Completion message received with
+                                                         error message.
+                                                         For OCTEON, this register is intended for debug use
+                                                         only and MUST NEVER be written with anything other
+                                                         than ZEROES. */
+#else
+        uint32_t scmre                   : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg21_s              cn30xx;
+    struct cvmx_pci_cfg21_s              cn31xx;
+    struct cvmx_pci_cfg21_s              cn38xx;
+    struct cvmx_pci_cfg21_s              cn38xxp2;
+    struct cvmx_pci_cfg21_s              cn50xx;
+    struct cvmx_pci_cfg21_s              cn58xx;
+    struct cvmx_pci_cfg21_s              cn58xxp1;
+} cvmx_pci_cfg21_t;
+
+
+/**
+ * cvmx_pci_cfg22
+ *
+ * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg22_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t mac                     : 7;       /**< Master Arbiter Control
+                                                         [31:26]: Used only in Fixed Priority mode
+                                                                  (when [25]=1)
+                                                         [31:30]: MSI Request
+                                                            00 = Highest Priority
+                                                            01 = Medium Priority
+                                                            10 = Lowest Priority
+                                                            11 = RESERVED
+                                                         [29:28]: Target Split Completion
+                                                            00 = Highest Priority
+                                                            01 = Medium Priority
+                                                            10 = Lowest Priority
+                                                            11 = RESERVED
+                                                         [27:26]: New Request; Deferred Read,Deferred Write
+                                                            00 = Highest Priority
+                                                            01 = Medium Priority
+                                                            10 = Lowest Priority
+                                                            11 = RESERVED
+                                                         [25]: Fixed/Round Robin Priority Selector
+                                                            0 = Round Robin
+                                                            1 = Fixed
+                                                         NOTE: When [25]=1(fixed priority), the three levels
+                                                         [31:26] MUST BE programmed to have mutually exclusive
+                                                         priority levels for proper operation. (Failure to do
+                                                         so may result in PCI hangs). */
+        uint32_t reserved_19_24          : 6;
+        uint32_t flush                   : 1;       /**< AM_DO_FLUSH_I control
+                                                         NOTE: This bit MUST BE ONE for proper OCTEON operation */
+        uint32_t mra                     : 1;       /**< Master Retry Aborted */
+        uint32_t mtta                    : 1;       /**< Master TRDY timeout aborted */
+        uint32_t mrv                     : 8;       /**< Master Retry Value [1..255] and 0=infinite */
+        uint32_t mttv                    : 8;       /**< Master TRDY timeout value [1..255] and 0=disabled
+                                                         NOTE: For OCTEON, this bit must always be zero
+                                                         for proper operation. (OCTEON does not support
+                                                         master TRDY timeout - target is expected to be
+                                                         well behaved). */
+#else
+        uint32_t mttv                    : 8;
+        uint32_t mrv                     : 8;
+        uint32_t mtta                    : 1;
+        uint32_t mra                     : 1;
+        uint32_t flush                   : 1;
+        uint32_t reserved_19_24          : 6;
+        uint32_t mac                     : 7;
+#endif
+    } s;
+    struct cvmx_pci_cfg22_s              cn30xx;
+    struct cvmx_pci_cfg22_s              cn31xx;
+    struct cvmx_pci_cfg22_s              cn38xx;
+    struct cvmx_pci_cfg22_s              cn38xxp2;
+    struct cvmx_pci_cfg22_s              cn50xx;
+    struct cvmx_pci_cfg22_s              cn58xx;
+    struct cvmx_pci_cfg22_s              cn58xxp1;
+} cvmx_pci_cfg22_t;
+
+
+/**
+ * cvmx_pci_cfg56
+ *
+ * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg56_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_23_31          : 9;
+        uint32_t most                    : 3;       /**< Maximum outstanding Split transactions
+                                                           Encoded Value    \#Max outstanding splits
+                                                               000                   1
+                                                               001                   2
+                                                               010                   3
+                                                               011                   4
+                                                               100                   8
+                                                               101                   8(clamped)
+                                                               110                   8(clamped)
+                                                               111                   8(clamped)
+                                                         NOTE: OCTEON only supports upto a MAXIMUM of 8
+                                                         outstanding master split transactions. */
+        uint32_t mmbc                    : 2;       /**< Maximum Memory Byte Count
+                                                                 [0=512B,1=1024B,2=2048B,3=4096B]
+                                                         NOTE: OCTEON does not support this field and has
+                                                         no effect on limiting the maximum memory byte count. */
+        uint32_t roe                     : 1;       /**< Relaxed Ordering Enable */
+        uint32_t dpere                   : 1;       /**< Data Parity Error Recovery Enable */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer */
+        uint32_t pxcid                   : 8;       /**< PCI-X Capability ID */
+#else
+        uint32_t pxcid                   : 8;
+        uint32_t ncp                     : 8;
+        uint32_t dpere                   : 1;
+        uint32_t roe                     : 1;
+        uint32_t mmbc                    : 2;
+        uint32_t most                    : 3;
+        uint32_t reserved_23_31          : 9;
+#endif
+    } s;
+    struct cvmx_pci_cfg56_s              cn30xx;
+    struct cvmx_pci_cfg56_s              cn31xx;
+    struct cvmx_pci_cfg56_s              cn38xx;
+    struct cvmx_pci_cfg56_s              cn38xxp2;
+    struct cvmx_pci_cfg56_s              cn50xx;
+    struct cvmx_pci_cfg56_s              cn58xx;
+    struct cvmx_pci_cfg56_s              cn58xxp1;
+} cvmx_pci_cfg56_t;
+
+
+/**
+ * cvmx_pci_cfg57
+ *
+ * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg57_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t scemr                   : 1;       /**< Split Completion Error Message Received */
+        uint32_t mcrsd                   : 3;       /**< Maximum Cumulative Read Size designed */
+        uint32_t mostd                   : 3;       /**< Maximum Outstanding Split transaction designed */
+        uint32_t mmrbcd                  : 2;       /**< Maximum Memory Read byte count designed */
+        uint32_t dc                      : 1;       /**< Device Complexity
+                                                         0 = Simple Device
+                                                         1 = Bridge Device */
+        uint32_t usc                     : 1;       /**< Unexpected Split Completion */
+        uint32_t scd                     : 1;       /**< Split Completion Discarded */
+        uint32_t m133                    : 1;       /**< 133MHz Capable */
+        uint32_t w64                     : 1;       /**< Indicates a 32b(=0) or 64b(=1) device */
+        uint32_t bn                      : 8;       /**< Bus Number. Updated on all configuration write
+                                                         (0x11=PCI)             cycles. Its value is dependent upon the PCI/X
+                                                         (0xFF=PCIX)            mode. */
+        uint32_t dn                      : 5;       /**< Device Number. Updated on all configuration
+                                                         write cycles. */
+        uint32_t fn                      : 3;       /**< Function Number */
+#else
+        uint32_t fn                      : 3;
+        uint32_t dn                      : 5;
+        uint32_t bn                      : 8;
+        uint32_t w64                     : 1;
+        uint32_t m133                    : 1;
+        uint32_t scd                     : 1;
+        uint32_t usc                     : 1;
+        uint32_t dc                      : 1;
+        uint32_t mmrbcd                  : 2;
+        uint32_t mostd                   : 3;
+        uint32_t mcrsd                   : 3;
+        uint32_t scemr                   : 1;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_pci_cfg57_s              cn30xx;
+    struct cvmx_pci_cfg57_s              cn31xx;
+    struct cvmx_pci_cfg57_s              cn38xx;
+    struct cvmx_pci_cfg57_s              cn38xxp2;
+    struct cvmx_pci_cfg57_s              cn50xx;
+    struct cvmx_pci_cfg57_s              cn58xx;
+    struct cvmx_pci_cfg57_s              cn58xxp1;
+} cvmx_pci_cfg57_t;
+
+
+/**
+ * cvmx_pci_cfg58
+ *
+ * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg58_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pmes                    : 5;       /**< PME Support (D0 to D3cold) */
+        uint32_t d2s                     : 1;       /**< D2_Support */
+        uint32_t d1s                     : 1;       /**< D1_Support */
+        uint32_t auxc                    : 3;       /**< AUX_Current (0..375mA) */
+        uint32_t dsi                     : 1;       /**< Device Specific Initialization */
+        uint32_t reserved_20_20          : 1;
+        uint32_t pmec                    : 1;       /**< PME Clock */
+        uint32_t pcimiv                  : 3;       /**< Indicates the version of the PCI
+                                                         Management
+                                                          Interface Specification with which the core
+                                                          complies.
+                                                            010b = Complies with PCI Management Interface
+                                                            Specification Revision 1.1 */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer */
+        uint32_t pmcid                   : 8;       /**< Power Management Capability ID */
+#else
+        uint32_t pmcid                   : 8;
+        uint32_t ncp                     : 8;
+        uint32_t pcimiv                  : 3;
+        uint32_t pmec                    : 1;
+        uint32_t reserved_20_20          : 1;
+        uint32_t dsi                     : 1;
+        uint32_t auxc                    : 3;
+        uint32_t d1s                     : 1;
+        uint32_t d2s                     : 1;
+        uint32_t pmes                    : 5;
+#endif
+    } s;
+    struct cvmx_pci_cfg58_s              cn30xx;
+    struct cvmx_pci_cfg58_s              cn31xx;
+    struct cvmx_pci_cfg58_s              cn38xx;
+    struct cvmx_pci_cfg58_s              cn38xxp2;
+    struct cvmx_pci_cfg58_s              cn50xx;
+    struct cvmx_pci_cfg58_s              cn58xx;
+    struct cvmx_pci_cfg58_s              cn58xxp1;
+} cvmx_pci_cfg58_t;
+
+
+/**
+ * cvmx_pci_cfg59
+ *
+ * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s))
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg59_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pmdia                   : 8;       /**< Power Management data input from application
+                                                         (PME_DATA) */
+        uint32_t bpccen                  : 1;       /**< BPCC_En (bus power/clock control) enable */
+        uint32_t bd3h                    : 1;       /**< B2_B3\#, B2/B3 Support for D3hot */
+        uint32_t reserved_16_21          : 6;
+        uint32_t pmess                   : 1;       /**< PME_Status sticky bit */
+        uint32_t pmedsia                 : 2;       /**< PME_Data_Scale input from application
+                                                         Device                  (PME_DATA_SCALE[1:0])
+                                                         Specific */
+        uint32_t pmds                    : 4;       /**< Power Management Data_select */
+        uint32_t pmeens                  : 1;       /**< PME_En sticky bit */
+        uint32_t reserved_2_7            : 6;
+        uint32_t ps                      : 2;       /**< Power State (D0 to D3)
+                                                         The N2 DOES NOT support D1/D2 Power Management
+                                                         states, therefore writing to this register has
+                                                         no effect (please refer to the PCI Power
+                                                         Management
+                                                         Specification v1.1 for further details about
+                                                         it?s R/W nature. This is not a conventional
+                                                         R/W style register. */
+#else
+        uint32_t ps                      : 2;
+        uint32_t reserved_2_7            : 6;
+        uint32_t pmeens                  : 1;
+        uint32_t pmds                    : 4;
+        uint32_t pmedsia                 : 2;
+        uint32_t pmess                   : 1;
+        uint32_t reserved_16_21          : 6;
+        uint32_t bd3h                    : 1;
+        uint32_t bpccen                  : 1;
+        uint32_t pmdia                   : 8;
+#endif
+    } s;
+    struct cvmx_pci_cfg59_s              cn30xx;
+    struct cvmx_pci_cfg59_s              cn31xx;
+    struct cvmx_pci_cfg59_s              cn38xx;
+    struct cvmx_pci_cfg59_s              cn38xxp2;
+    struct cvmx_pci_cfg59_s              cn50xx;
+    struct cvmx_pci_cfg59_s              cn58xx;
+    struct cvmx_pci_cfg59_s              cn58xxp1;
+} cvmx_pci_cfg59_t;
+
+
+/**
+ * cvmx_pci_cfg60
+ *
+ * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg60_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t m64                     : 1;       /**< 32/64 b message */
+        uint32_t mme                     : 3;       /**< Multiple Message Enable(1,2,4,8,16,32) */
+        uint32_t mmc                     : 3;       /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */
+        uint32_t msien                   : 1;       /**< MSI Enable */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer */
+        uint32_t msicid                  : 8;       /**< MSI Capability ID */
+#else
+        uint32_t msicid                  : 8;
+        uint32_t ncp                     : 8;
+        uint32_t msien                   : 1;
+        uint32_t mmc                     : 3;
+        uint32_t mme                     : 3;
+        uint32_t m64                     : 1;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pci_cfg60_s              cn30xx;
+    struct cvmx_pci_cfg60_s              cn31xx;
+    struct cvmx_pci_cfg60_s              cn38xx;
+    struct cvmx_pci_cfg60_s              cn38xxp2;
+    struct cvmx_pci_cfg60_s              cn50xx;
+    struct cvmx_pci_cfg60_s              cn58xx;
+    struct cvmx_pci_cfg60_s              cn58xxp1;
+} cvmx_pci_cfg60_t;
+
+
+/**
+ * cvmx_pci_cfg61
+ *
+ * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg61_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t msi31t2                 : 30;      /**< App Specific    MSI Address [31:2] */
+        uint32_t reserved_0_1            : 2;
+#else
+        uint32_t reserved_0_1            : 2;
+        uint32_t msi31t2                 : 30;
+#endif
+    } s;
+    struct cvmx_pci_cfg61_s              cn30xx;
+    struct cvmx_pci_cfg61_s              cn31xx;
+    struct cvmx_pci_cfg61_s              cn38xx;
+    struct cvmx_pci_cfg61_s              cn38xxp2;
+    struct cvmx_pci_cfg61_s              cn50xx;
+    struct cvmx_pci_cfg61_s              cn58xx;
+    struct cvmx_pci_cfg61_s              cn58xxp1;
+} cvmx_pci_cfg61_t;
+
+
+/**
+ * cvmx_pci_cfg62
+ *
+ * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg62_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t msi                     : 32;      /**< MSI Address [63:32] */
+#else
+        uint32_t msi                     : 32;
+#endif
+    } s;
+    struct cvmx_pci_cfg62_s              cn30xx;
+    struct cvmx_pci_cfg62_s              cn31xx;
+    struct cvmx_pci_cfg62_s              cn38xx;
+    struct cvmx_pci_cfg62_s              cn38xxp2;
+    struct cvmx_pci_cfg62_s              cn50xx;
+    struct cvmx_pci_cfg62_s              cn58xx;
+    struct cvmx_pci_cfg62_s              cn58xxp1;
+} cvmx_pci_cfg62_t;
+
+
+/**
+ * cvmx_pci_cfg63
+ *
+ * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_cfg63_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t msimd                   : 16;      /**< MSI Message Data */
+#else
+        uint32_t msimd                   : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_pci_cfg63_s              cn30xx;
+    struct cvmx_pci_cfg63_s              cn31xx;
+    struct cvmx_pci_cfg63_s              cn38xx;
+    struct cvmx_pci_cfg63_s              cn38xxp2;
+    struct cvmx_pci_cfg63_s              cn50xx;
+    struct cvmx_pci_cfg63_s              cn58xx;
+    struct cvmx_pci_cfg63_s              cn58xxp1;
+} cvmx_pci_cfg63_t;
+
+
+/**
+ * cvmx_pci_cnt_reg
+ *
+ * PCI_CNT_REG = PCI Clock Count Register
+ * 
+ * This register is provided to software as a means to determine PCI Bus Type/Speed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_cnt_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t hm_pcix                 : 1;       /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX)
+                                                         This field represents what OCTEON(in Host mode)
+                                                         sampled as the 'intended' PCI Bus Type based on
+                                                         the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed
+                                                         encoding table). */
+        uint64_t hm_speed                : 2;       /**< PCI Host Mode Sampled Bus Speed
+                                                          This field represents what OCTEON(in Host mode)
+                                                          sampled as the 'intended' PCI Bus Speed based on
+                                                          the PCI100, PCI_M66EN and PCI_PCIXCAP pins.
+                                                          NOTE: This DOES NOT reflect what the actual PCI
+                                                          Bus Type/Speed values are. They only indicate what
+                                                          OCTEON sampled as the 'intended' values.
+                                                          PCI Host Mode Sampled Bus Type/Speed Table:
+                                                            M66EN | PCIXCAP | PCI100  |  HM_PCIX | HM_SPEED[1:0]
+                                                         ---------+---------+---------+----------+-------------
+                                                              0   |    0    |    0    | 0=PCI    |  00=33 MHz
+                                                              0   |    0    |    1    | 0=PCI    |  00=33 MHz
+                                                              0   |    Z    |    0    | 0=PCI    |  01=66 MHz
+                                                              0   |    Z    |    1    | 0=PCI    |  01=66 MHz
+                                                              1   |    0    |    0    | 0=PCI    |  01=66 MHz
+                                                              1   |    0    |    1    | 0=PCI    |  01=66 MHz
+                                                              1   |    Z    |    0    | 0=PCI    |  01=66 MHz
+                                                              1   |    Z    |    1    | 0=PCI    |  01=66 MHz
+                                                              0   |    1    |    1    | 1=PCIX   |  10=100 MHz
+                                                              1   |    1    |    1    | 1=PCIX   |  10=100 MHz
+                                                              0   |    1    |    0    | 1=PCIX   |  11=133 MHz
+                                                              1   |    1    |    0    | 1=PCIX   |  11=133 MHz
+                                                          NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification
+                                                          for more details on board level hookup to achieve these
+                                                          values.
+                                                          NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR]
+                                                          to override the 'sampled' PCI Bus Type/Speed.
+                                                          NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine
+                                                          the exact PCI(X) Bus speed.
+                                                          Example: PCI_REF_CLKIN=133MHz
+                                                             PCI_HOST_MODE=1
+                                                             PCI_M66EN=0
+                                                             PCI_PCIXCAP=1
+                                                             PCI_PCI100=1
+                                                          For this example, OCTEON will generate
+                                                          PCI_CLK_OUT=100MHz and drive the proper PCI
+                                                          Initialization sequence (DEVSEL#=Deasserted,
+                                                          STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N
+                                                          deassertion.
+                                                          NOTE: The HM_SPEED field is only valid after
+                                                          PLL_REF_CLK is active and PLL_DCOK is asserted.
+                                                          (see HRM description for power-on/reset sequence).
+                                                          NOTE: PCI_REF_CLKIN input must be 133MHz (and is used
+                                                          to generate the PCI_CLK_OUT pin in Host Mode).
+                                                          *** NOTE: O9N PASS1 Addition */
+        uint64_t ap_pcix                 : 1;       /**< PCI(X) Bus Type (0:PCI/1:PCIX)
+                                                         At PCI_RST_N de-assertion, the PCI Initialization
+                                                         pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is
+                                                         captured to provide information to software regarding
+                                                         the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */
+        uint64_t ap_speed                : 2;       /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133)
+                                                                                    At PCI_RST_N de-assertion, the PCI Initialization
+                                                                                    pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is
+                                                                                    captured to provide information to software regarding
+                                                                                    the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range.
+                                                                                    PCI-X Initialization Pattern(see PCIX Spec):
+                                                           PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode    MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz)
+                                                         -------------+----------+----------+-------+---------+----------+----------+------------------
+                                                            Deasserted Deasserted Deasserted PCI 33    --         30          0         33
+                                                                                             PCI 66    30         15         33         66
+                                                            Deasserted Deasserted Asserted   PCI-X     20         15         50         66
+                                                            Deasserted Asserted   Deasserted PCI-X     15         10         66        100
+                                                            Deasserted Asserted   Asserted   PCI-X     10         7.5       100        133
+                                                            Asserted   Deasserted Deasserted PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                            Asserted   Deasserted Asserted   PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                            Asserted   Asserted   Deasserted PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                            Asserted   Asserted   Asserted   PCI-X   Reserved   Reserved   Reserved   Reserved
+                                                                                    NOTE: The PCI Bus speed 'assumed' from the initialization
+                                                                                    pattern is really intended for an operational range.
+                                                                                    For example: If PINIT=100, this indicates PCI-X in the
+                                                                                    100-133MHz range. The PCI_CNT field can be used to further
+                                                                                    determine a more exacting PCI Bus frequency value if
+                                                                                    required.
+                                                                                    *** NOTE: O9N PASS1 Addition */
+        uint64_t pcicnt                  : 32;      /**< Free Running PCI Clock counter.
+                                                         At PCI Reset, the PCICNT=0, and is auto-incremented
+                                                         on every PCI clock and will auto-wrap back to zero
+                                                         when saturated.
+                                                         NOTE: Writes override the auto-increment to allow
+                                                         software to preload any initial value.
+                                                         The PCICNT field is provided to software as a means
+                                                         to determine the PCI Bus Speed.
+                                                         Assuming software has knowledge of the core frequency
+                                                         (eclk), this register can be written with a value X,
+                                                         wait 'n' core clocks(eclk) and then read later(Y) to
+                                                         determine \#PCI clocks(Y-X) have elapsed within 'n' core
+                                                         clocks to determine the PCI input Clock frequency.
+                                                         *** NOTE: O9N PASS1 Addition */
+#else
+        uint64_t pcicnt                  : 32;
+        uint64_t ap_speed                : 2;
+        uint64_t ap_pcix                 : 1;
+        uint64_t hm_speed                : 2;
+        uint64_t hm_pcix                 : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_pci_cnt_reg_s            cn50xx;
+    struct cvmx_pci_cnt_reg_s            cn58xx;
+    struct cvmx_pci_cnt_reg_s            cn58xxp1;
+} cvmx_pci_cnt_reg_t;
+
+
+/**
+ * cvmx_pci_ctl_status_2
+ *
+ * PCI_CTL_STATUS_2 = PCI Control Status 2 Register
+ * 
+ * Control status register accessable from both PCI and NCB.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_ctl_status_2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_29_31          : 3;
+        uint32_t bb1_hole                : 3;       /**< Big BAR 1 Hole
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB1]=1, this field defines
+                                                         an encoded size of the upper BAR1 region which
+                                                         OCTEON will mask out (ie: not respond to).
+                                                         (see definition of BB1_HOLE and BB1_SIZ encodings
+                                                         in the PCI_CTL_STATUS_2[BB1] definition below). */
+        uint32_t bb1_siz                 : 1;       /**< Big BAR 1 Size
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB1]=1, this field defines
+                                                         the programmable SIZE of BAR 1.
+                                                           - 0: 1GB / 1: 2GB */
+        uint32_t bb_ca                   : 1;       /**< Set to '1' for Big Bar Mode to do STT/LDT L2C
+                                                         operations.
+                                                         NOT IN PASS 1 NOR PASS 2 */
+        uint32_t bb_es                   : 2;       /**< Big Bar Node Endian Swap Mode
+                                                           - 0: No Swizzle
+                                                           - 1: Byte Swizzle (per-QW)
+                                                           - 2: Byte Swizzle (per-LW)
+                                                           - 3: LongWord Swizzle
+                                                         NOT IN PASS 1 NOR PASS 2 */
+        uint32_t bb1                     : 1;       /**< Big Bar 1 Enable
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB1] is set, the following differences
+                                                         occur:
+                                                         - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather
+                                                           than the default 128MB.
+                                                         - The following table indicates the effective size of
+                                                           BAR1 when BB1 is set:
+                                                             BB1_SIZ   BB1_HOLE  Effective size    Comment
+                                                           +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+                                                                0          0         1024 MB      Normal 1GB BAR
+                                                                0          1         1008 MB      1 GB, 16 MB hole
+                                                                0          2          992 MB      1 GB, 32 MB hole
+                                                                0          3          960 MB      1 GB, 64 MB hole
+                                                                0          4          896 MB      1 GB,128 MB hole
+                                                                0          5          768 MB      1 GB,256 MB hole
+                                                                0          6          512 MB      1 GB,512 MB hole
+                                                                0          7         Illegal
+                                                                1          0         2048 MB      Normal 2GB BAR
+                                                                1          1         2032 MB      2 GB, 16 MB hole
+                                                                1          2         2016 MB      2 GB, 32 MB hole
+                                                                1          3         1984 MB      2 GB, 64 MB hole
+                                                                1          4         1920 MB      2 GB,128 MB hole
+                                                                1          5         1792 MB      2 GB,256 MB hole
+                                                                1          6         1536 MB      2 GB,512 MB hole
+                                                                1          7         Illegal
+                                                         - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero
+                                                           and are ignored on write. BAR1 is an entirely ordinary
+                                                           1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0.
+                                                           When BB1_HOLE is not zero, BAR1 addresses are programmed
+                                                           as if the BAR were 1GB, but, OCTEON does not respond
+                                                           to addresses in the programmed holes.
+                                                         - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero
+                                                           and are ignored on write. BAR1 is an entirely ordinary
+                                                           2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0.
+                                                           When BB1_HOLE is not zero, BAR1 addresses are programmed
+                                                           as if the BAR were 2GB, but, OCTEON does not respond
+                                                           to addresses in the programmed holes.
+                                                         - Note that the BB1_HOLE value has no effect on the
+                                                           PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether
+                                                           OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE]
+                                                           behavior, however.
+                                                         - The first 128MB, i.e. addresses on the PCI bus in the range
+                                                             BAR1+0          .. BAR1+0x07FFFFFF
+                                                           access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's
+                                                           as before
+                                                         - The remaining address space, i.e. addresses
+                                                           on the PCI bus in the range
+                                                              BAR1+0x08000000 .. BAR1+size-1,
+                                                           where size is the size of BAR1 as selected by the above
+                                                           table (based on the BB1_SIZ and BB1_HOLE values), are mapped to
+                                                           OCTEON physical DRAM addresses as follows:
+                                                                   PCI Address Range         OCTEON Physical Address Range
+                                                           ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+                                                            BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size
+                                                           and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and
+                                                           PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit
+                                                           for these references.
+                                                           The consequences of any burst that crosses the end of the PCI
+                                                           Address Range for BAR1 are unpredicable.
+                                                         - The consequences of any burst access that crosses the boundary
+                                                           between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X
+                                                           mode. OCTEON may disconnect PCI references at this boundary. */
+        uint32_t bb0                     : 1;       /**< Big Bar 0 Enable
+                                                         NOT IN PASS 1 NOR PASS 2
+                                                         When PCI_CTL_STATUS_2[BB0] is set, the following
+                                                         differences occur:
+                                                         - OCTEON's BAR0 becomes 2GB rather than the default 4KB.
+                                                           PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write.
+                                                         - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON
+                                                           single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0
+                                                           writes, and splits (burstably) PCI-X BAR0 reads.)
+                                                         - The first 4KB, i.e. addresses on the PCI bus in the range
+                                                               BAR0+0      .. BAR0+0xFFF
+                                                           access OCTEON's PCI-type CSR's as when BB0 is clear.
+                                                         - The remaining address space, i.e. addresses on the PCI bus
+                                                           in the range
+                                                               BAR0+0x1000 .. BAR0+0x7FFFFFFF
+                                                           are mapped to OCTEON physical DRAM addresses as follows:
+                                                              PCI Address Range                  OCTEON Physical Address Range
+                                                           ------------------------------------+------------------------------
+                                                            BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF
+                                                            BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF
+                                                            BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF
+                                                           and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and
+                                                           PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit
+                                                           for these references.
+                                                           The consequences of any burst that crosses the end of the PCI
+                                                           Address Range for BAR0 are unpredicable.
+                                                         - The consequences of any burst access that crosses the boundary
+                                                           between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X
+                                                           mode. OCTEON may disconnect PCI references at this boundary.
+                                                         - The results of any burst read that crosses the boundary
+                                                           between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable.
+                                                           The consequences of any burst write that crosses this same
+                                                           boundary are unpredictable.
+                                                         - The results of any burst read that crosses the boundary
+                                                           between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable.
+                                                           The consequences of any burst write that crosses this same
+                                                           boundary are unpredictable. */
+        uint32_t erst_n                  : 1;       /**< Reset active Low. PASS-2 */
+        uint32_t bar2pres                : 1;       /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
+                                                         is NOT blown the value of this field is '0' after
+                                                         reset and BAR2 is NOT present. When the fuse IS
+                                                         blown the value of this field is '1' after reset
+                                                         and BAR2 is present. Note that SW can change this
+                                                         field after reset. This is a PASS-2 field. */
+        uint32_t scmtyp                  : 1;       /**< Split Completion Message CMD Type (0=RD/1=WR)
+                                                         When SCM=1, SCMTYP specifies the CMD intent (R/W) */
+        uint32_t scm                     : 1;       /**< Split Completion Message Detected (Read or Write) */
+        uint32_t en_wfilt                : 1;       /**< When '1' the window-access filter is enabled.
+                                                         Unfilter writes are:
+                                                         MIO, SubId0
+                                                         MIO, SubId7
+                                                         NPI, SubId0
+                                                         NPI, SubId7
+                                                         POW, SubId7
+                                                         DFA, SubId7
+                                                         IPD, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO, SubId0
+                                                         MIO, SubId7
+                                                         NPI, SubId0
+                                                         NPI, SubId7
+                                                         POW, SubId1
+                                                         POW, SubId2
+                                                         POW, SubId3
+                                                         POW, SubId7
+                                                         DFA, SubId7
+                                                         IPD, SubId7 */
+        uint32_t reserved_14_14          : 1;
+        uint32_t ap_pcix                 : 1;       /**< PCX Core Mode status (0=PCI Bus/1=PCIX)
+                                                         If one or more of PCI_DEVSEL_N, PCI_STOP_N, and
+                                                         PCI_TRDY_N are asserted at the rising edge of
+                                                         PCI_RST_N, the device enters PCI-X mode.
+                                                         Otherwise, the device enters conventional PCI
+                                                         mode at the rising edge of RST#. */
+        uint32_t ap_64ad                 : 1;       /**< PCX Core Bus status (0=32b Bus/1=64b Bus)
+                                                         When PCI_RST_N pin is de-asserted, the state
+                                                         of PCI_REQ64_N(driven by central agent) determines
+                                                         the width of the PCI/X bus. */
+        uint32_t b12_bist                : 1;       /**< Bist Status For Memeory In B12 */
+        uint32_t pmo_amod                : 1;       /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */
+        uint32_t pmo_fpc                 : 3;       /**< PMO-ARB Fixed Priority Counter
+                                                         When PMO_AMOD=0 (FP mode), this field represents
+                                                         the \# of CMD1 requests that are issued (at higher
+                                                         priority) before a single lower priority CMD0
+                                                         is allowed to issue (to ensure foward progress).
+                                                           - 0: 1 CMD1 Request issued before CMD0 allowed
+                                                           - ...
+                                                           - 7: 8 CMD1 Requests issued before CMD0 allowed */
+        uint32_t tsr_hwm                 : 3;       /**< Target Split-Read ADB(allowable disconnect boundary)
+                                                         High Water Mark.
+                                                         Specifies the number of ADBs(128 Byte aligned chunks)
+                                                         that are accumulated(pending) BEFORE the Target Split
+                                                         completion is attempted on the PCI bus.
+                                                            - 0: RESERVED/ILLEGAL
+                                                            - 1: 2 Pending ADBs (129B-256B)
+                                                            - 2: 3 Pending ADBs (257B-384B)
+                                                            - 3: 4 Pending ADBs (385B-512B)
+                                                            - 4: 5 Pending ADBs (513B-640B)
+                                                            - 5: 6 Pending ADBs (641B-768B)
+                                                            - 6: 7 Pending ADBs (769B-896B)
+                                                            - 7: 8 Pending ADBs (897B-1024B)
+                                                         Example: Suppose a 1KB target memory request with
+                                                         starting byte offset address[6:0]=0x7F is split by
+                                                         the OCTEON and the TSR_HWM=1(2 ADBs).
+                                                         The OCTEON will start the target split completion
+                                                         on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B
+                                                         of data have been received from memory (even though
+                                                         the remaining 895B has not yet been received). The
+                                                         OCTEON will continue the split completion until it
+                                                         has consumed all of the pended split data. If the
+                                                         full transaction length(1KB) of data was NOT entirely
+                                                         transferred, then OCTEON will terminate the split
+                                                         completion and again wait for another 2 ADB-aligned data
+                                                         chunks(256B) of pended split data to be received from
+                                                         memory before starting another split completion request.
+                                                         This allows Octeon (as split completer), to send back
+                                                         multiple split completions for a given large split
+                                                         transaction without having to wait for the entire
+                                                         transaction length to be received from memory.
+                                                         NOTE: For split transaction sizes 'smaller' than the
+                                                         specified TSR_HWM value, the split completion
+                                                         is started when the last datum has been received from
+                                                         memory.
+                                                         NOTE: It is IMPERATIVE that this field NEVER BE
+                                                         written to a ZERO value. A value of zero is
+                                                         reserved/illegal and can result in PCIX bus hangs). */
+        uint32_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will be target-aborted. */
+        uint32_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+        uint32_t bar2_cax                : 1;       /**< Value will be XORed with pci-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         When XOR result is 1, not cached in L2 */
+#else
+        uint32_t bar2_cax                : 1;
+        uint32_t bar2_esx                : 2;
+        uint32_t bar2_enb                : 1;
+        uint32_t tsr_hwm                 : 3;
+        uint32_t pmo_fpc                 : 3;
+        uint32_t pmo_amod                : 1;
+        uint32_t b12_bist                : 1;
+        uint32_t ap_64ad                 : 1;
+        uint32_t ap_pcix                 : 1;
+        uint32_t reserved_14_14          : 1;
+        uint32_t en_wfilt                : 1;
+        uint32_t scm                     : 1;
+        uint32_t scmtyp                  : 1;
+        uint32_t bar2pres                : 1;
+        uint32_t erst_n                  : 1;
+        uint32_t bb0                     : 1;
+        uint32_t bb1                     : 1;
+        uint32_t bb_es                   : 2;
+        uint32_t bb_ca                   : 1;
+        uint32_t bb1_siz                 : 1;
+        uint32_t bb1_hole                : 3;
+        uint32_t reserved_29_31          : 3;
+#endif
+    } s;
+    struct cvmx_pci_ctl_status_2_s       cn30xx;
+    struct cvmx_pci_ctl_status_2_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t erst_n                  : 1;       /**< Reset active Low. */
+        uint32_t bar2pres                : 1;       /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN])
+                                                         is NOT blown the value of this field is '0' after
+                                                         reset and BAR2 is NOT present. When the fuse IS
+                                                         blown the value of this field is '1' after reset
+                                                         and BAR2 is present. Note that SW can change this
+                                                         field after reset. */
+        uint32_t scmtyp                  : 1;       /**< Split Completion Message CMD Type (0=RD/1=WR)
+                                                         When SCM=1, SCMTYP specifies the CMD intent (R/W) */
+        uint32_t scm                     : 1;       /**< Split Completion Message Detected (Read or Write) */
+        uint32_t en_wfilt                : 1;       /**< When '1' the window-access filter is enabled.
+                                                         Unfilter writes are:
+                                                         MIO,  SubId0
+                                                         MIO,  SubId7
+                                                         NPI,  SubId0
+                                                         NPI,  SubId7
+                                                         POW,  SubId7
+                                                         DFA,  SubId7
+                                                         IPD,  SubId7
+                                                         USBN, SubId7
+                                                         Unfiltered Reads are:
+                                                         MIO,  SubId0
+                                                         MIO,  SubId7
+                                                         NPI,  SubId0
+                                                         NPI,  SubId7
+                                                         POW,  SubId1
+                                                         POW,  SubId2
+                                                         POW,  SubId3
+                                                         POW,  SubId7
+                                                         DFA,  SubId7
+                                                         IPD,  SubId7
+                                                         USBN, SubId7 */
+        uint32_t reserved_14_14          : 1;
+        uint32_t ap_pcix                 : 1;       /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */
+        uint32_t ap_64ad                 : 1;       /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */
+        uint32_t b12_bist                : 1;       /**< Bist Status For Memeory In B12 */
+        uint32_t pmo_amod                : 1;       /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */
+        uint32_t pmo_fpc                 : 3;       /**< PMO-ARB Fixed Priority Counter
+                                                         When PMO_AMOD=0 (FP mode), this field represents
+                                                         the \# of CMD1 requests that are issued (at higher
+                                                         priority) before a single lower priority CMD0
+                                                         is allowed to issue (to ensure foward progress).
+                                                           - 0: 1 CMD1 Request issued before CMD0 allowed
+                                                           - ...
+                                                           - 7: 8 CMD1 Requests issued before CMD0 allowed */
+        uint32_t tsr_hwm                 : 3;       /**< Target Split-Read ADB(allowable disconnect boundary)
+                                                         High Water Mark.
+                                                         Specifies the number of ADBs(128 Byte aligned chunks)
+                                                         that are accumulated(pending) BEFORE the Target Split
+                                                         completion is attempted on the PCI bus.
+                                                            - 0: RESERVED/ILLEGAL
+                                                            - 1: 2 Pending ADBs (129B-256B)
+                                                            - 2: 3 Pending ADBs (257B-384B)
+                                                            - 3: 4 Pending ADBs (385B-512B)
+                                                            - 4: 5 Pending ADBs (513B-640B)
+                                                            - 5: 6 Pending ADBs (641B-768B)
+                                                            - 6: 7 Pending ADBs (769B-896B)
+                                                            - 7: 8 Pending ADBs (897B-1024B)
+                                                         Example: Suppose a 1KB target memory request with
+                                                         starting byte offset address[6:0]=0x7F is split by
+                                                         the OCTEON and the TSR_HWM=1(2 ADBs).
+                                                         The OCTEON will start the target split completion
+                                                         on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B
+                                                         of data have been received from memory (even though
+                                                         the remaining 895B has not yet been received). The
+                                                         OCTEON will continue the split completion until it
+                                                         has consumed all of the pended split data. If the
+                                                         full transaction length(1KB) of data was NOT entirely
+                                                         transferred, then OCTEON will terminate the split
+                                                         completion and again wait for another 2 ADB-aligned data
+                                                         chunks(256B) of pended split data to be received from
+                                                         memory before starting another split completion request.
+                                                         This allows Octeon (as split completer), to send back
+                                                         multiple split completions for a given large split
+                                                         transaction without having to wait for the entire
+                                                         transaction length to be received from memory.
+                                                         NOTE: For split transaction sizes 'smaller' than the
+                                                         specified TSR_HWM value, the split completion
+                                                         is started when the last datum has been received from
+                                                         memory.
+                                                         NOTE: It is IMPERATIVE that this field NEVER BE
+                                                         written to a ZERO value. A value of zero is
+                                                         reserved/illegal and can result in PCIX bus hangs). */
+        uint32_t bar2_enb                : 1;       /**< When set '1' BAR2 is enable and will respond when
+                                                         clear '0' BAR2 access will be target-aborted. */
+        uint32_t bar2_esx                : 2;       /**< Value will be XORed with pci-address[37:36] to
+                                                         determine the endian swap mode. */
+        uint32_t bar2_cax                : 1;       /**< Value will be XORed with pci-address[38] to
+                                                         determine the L2 cache attribute.
+                                                         When XOR result is 1, not allocated in L2 cache */
+#else
+        uint32_t bar2_cax                : 1;
+        uint32_t bar2_esx                : 2;
+        uint32_t bar2_enb                : 1;
+        uint32_t tsr_hwm                 : 3;
+        uint32_t pmo_fpc                 : 3;
+        uint32_t pmo_amod                : 1;
+        uint32_t b12_bist                : 1;
+        uint32_t ap_64ad                 : 1;
+        uint32_t ap_pcix                 : 1;
+        uint32_t reserved_14_14          : 1;
+        uint32_t en_wfilt                : 1;
+        uint32_t scm                     : 1;
+        uint32_t scmtyp                  : 1;
+        uint32_t bar2pres                : 1;
+        uint32_t erst_n                  : 1;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } cn31xx;
+    struct cvmx_pci_ctl_status_2_s       cn38xx;
+    struct cvmx_pci_ctl_status_2_cn31xx  cn38xxp2;
+    struct cvmx_pci_ctl_status_2_s       cn50xx;
+    struct cvmx_pci_ctl_status_2_s       cn58xx;
+    struct cvmx_pci_ctl_status_2_s       cn58xxp1;
+} cvmx_pci_ctl_status_2_t;
+
+
+/**
+ * cvmx_pci_dbell#
+ *
+ * PCI_DBELL0 = PCI Doorbell-0
+ * 
+ * The value to write to the doorbell 0 register. The value in this register is acted upon when the
+ * least-significant-byte of this register is written.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_dbellx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t inc_val                 : 16;      /**< Software writes this register with the
+                                                         number of new Instructions to be processed
+                                                         on the Instruction Queue. When read this
+                                                         register contains the last write value. */
+#else
+        uint32_t inc_val                 : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_pci_dbellx_s             cn30xx;
+    struct cvmx_pci_dbellx_s             cn31xx;
+    struct cvmx_pci_dbellx_s             cn38xx;
+    struct cvmx_pci_dbellx_s             cn38xxp2;
+    struct cvmx_pci_dbellx_s             cn50xx;
+    struct cvmx_pci_dbellx_s             cn58xx;
+    struct cvmx_pci_dbellx_s             cn58xxp1;
+} cvmx_pci_dbellx_t;
+
+
+/**
+ * cvmx_pci_dma_cnt#
+ *
+ * PCI_DMA_CNT0 = PCI DMA Count0
+ * 
+ * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the
+ * least-significant-byte of this register is written.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_dma_cntx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dma_cnt                 : 32;      /**< Update with the number of DMAs completed or the
+                                                         number of bytes sent for DMA's associated with
+                                                         this counter. When this register is written the
+                                                         value written to [15:0] will be subtracted from
+                                                         the value in this register. */
+#else
+        uint32_t dma_cnt                 : 32;
+#endif
+    } s;
+    struct cvmx_pci_dma_cntx_s           cn30xx;
+    struct cvmx_pci_dma_cntx_s           cn31xx;
+    struct cvmx_pci_dma_cntx_s           cn38xx;
+    struct cvmx_pci_dma_cntx_s           cn38xxp2;
+    struct cvmx_pci_dma_cntx_s           cn50xx;
+    struct cvmx_pci_dma_cntx_s           cn58xx;
+    struct cvmx_pci_dma_cntx_s           cn58xxp1;
+} cvmx_pci_dma_cntx_t;
+
+
+/**
+ * cvmx_pci_dma_int_lev#
+ *
+ * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0
+ * 
+ * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_dma_int_levx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pkt_cnt                 : 32;      /**< When PCI_DMA_CNT0 exceeds the value in this
+                                                         DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */
+#else
+        uint32_t pkt_cnt                 : 32;
+#endif
+    } s;
+    struct cvmx_pci_dma_int_levx_s       cn30xx;
+    struct cvmx_pci_dma_int_levx_s       cn31xx;
+    struct cvmx_pci_dma_int_levx_s       cn38xx;
+    struct cvmx_pci_dma_int_levx_s       cn38xxp2;
+    struct cvmx_pci_dma_int_levx_s       cn50xx;
+    struct cvmx_pci_dma_int_levx_s       cn58xx;
+    struct cvmx_pci_dma_int_levx_s       cn58xxp1;
+} cvmx_pci_dma_int_levx_t;
+
+
+/**
+ * cvmx_pci_dma_time#
+ *
+ * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0
+ * 
+ * Time to wait from DMA being sent before issuing an interrupt.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_dma_timex_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dma_time                : 32;      /**< Number of PCI clock cycle to wait before
+                                                         setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2.
+                                                         After PCI_DMA_CNT0 becomes non-zero.
+                                                         The timer is reset when the
+                                                         PCI_INT_SUM[27] register is cleared. */
+#else
+        uint32_t dma_time                : 32;
+#endif
+    } s;
+    struct cvmx_pci_dma_timex_s          cn30xx;
+    struct cvmx_pci_dma_timex_s          cn31xx;
+    struct cvmx_pci_dma_timex_s          cn38xx;
+    struct cvmx_pci_dma_timex_s          cn38xxp2;
+    struct cvmx_pci_dma_timex_s          cn50xx;
+    struct cvmx_pci_dma_timex_s          cn58xx;
+    struct cvmx_pci_dma_timex_s          cn58xxp1;
+} cvmx_pci_dma_timex_t;
+
+
+/**
+ * cvmx_pci_instr_count#
+ *
+ * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count
+ * 
+ * The number of instructions to be fetched by the Instruction-0 Engine.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_instr_countx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t icnt                    : 32;      /**< Number of Instructions to be fetched by the
+                                                         Instruction Engine.
+                                                         A write of any non zero value to this register
+                                                         will clear the value of this register. */
+#else
+        uint32_t icnt                    : 32;
+#endif
+    } s;
+    struct cvmx_pci_instr_countx_s       cn30xx;
+    struct cvmx_pci_instr_countx_s       cn31xx;
+    struct cvmx_pci_instr_countx_s       cn38xx;
+    struct cvmx_pci_instr_countx_s       cn38xxp2;
+    struct cvmx_pci_instr_countx_s       cn50xx;
+    struct cvmx_pci_instr_countx_s       cn58xx;
+    struct cvmx_pci_instr_countx_s       cn58xxp1;
+} cvmx_pci_instr_countx_t;
+
+
+/**
+ * cvmx_pci_int_enb
+ *
+ * PCI_INT_ENB = PCI Interrupt Enable
+ * 
+ * Enables interrupt bits in the PCI_INT_SUM register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
+        uint64_t ill_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
+        uint64_t win_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
+        uint64_t dma1_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
+        uint64_t dma0_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
+        uint64_t idtime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
+        uint64_t idtime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
+        uint64_t idcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
+        uint64_t idcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
+        uint64_t iptime3                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */
+        uint64_t iptime2                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */
+        uint64_t iptime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */
+        uint64_t iptime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
+        uint64_t ipcnt3                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */
+        uint64_t ipcnt2                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */
+        uint64_t ipcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */
+        uint64_t ipcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
+        uint64_t irsl_int                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
+        uint64_t ill_rrd                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
+        uint64_t ill_rwr                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
+        uint64_t idperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
+        uint64_t iaperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
+        uint64_t iserr                   : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
+        uint64_t itsr_abt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
+        uint64_t imsc_msg                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
+        uint64_t imsi_mabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
+        uint64_t imsi_tabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
+        uint64_t imsi_per                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
+        uint64_t imr_tto                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
+        uint64_t imr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
+        uint64_t itr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
+        uint64_t imr_wtto                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
+        uint64_t imr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
+        uint64_t itr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
+#else
+        uint64_t itr_wabt                : 1;
+        uint64_t imr_wabt                : 1;
+        uint64_t imr_wtto                : 1;
+        uint64_t itr_abt                 : 1;
+        uint64_t imr_abt                 : 1;
+        uint64_t imr_tto                 : 1;
+        uint64_t imsi_per                : 1;
+        uint64_t imsi_tabt               : 1;
+        uint64_t imsi_mabt               : 1;
+        uint64_t imsc_msg                : 1;
+        uint64_t itsr_abt                : 1;
+        uint64_t iserr                   : 1;
+        uint64_t iaperr                  : 1;
+        uint64_t idperr                  : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t irsl_int                : 1;
+        uint64_t ipcnt0                  : 1;
+        uint64_t ipcnt1                  : 1;
+        uint64_t ipcnt2                  : 1;
+        uint64_t ipcnt3                  : 1;
+        uint64_t iptime0                 : 1;
+        uint64_t iptime1                 : 1;
+        uint64_t iptime2                 : 1;
+        uint64_t iptime3                 : 1;
+        uint64_t idcnt0                  : 1;
+        uint64_t idcnt1                  : 1;
+        uint64_t idtime0                 : 1;
+        uint64_t idtime1                 : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_pci_int_enb_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
+        uint64_t ill_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
+        uint64_t win_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
+        uint64_t dma1_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
+        uint64_t dma0_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
+        uint64_t idtime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
+        uint64_t idtime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
+        uint64_t idcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
+        uint64_t idcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
+        uint64_t reserved_22_24          : 3;
+        uint64_t iptime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
+        uint64_t reserved_18_20          : 3;
+        uint64_t ipcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
+        uint64_t irsl_int                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
+        uint64_t ill_rrd                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
+        uint64_t ill_rwr                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
+        uint64_t idperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
+        uint64_t iaperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
+        uint64_t iserr                   : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
+        uint64_t itsr_abt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
+        uint64_t imsc_msg                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
+        uint64_t imsi_mabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
+        uint64_t imsi_tabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
+        uint64_t imsi_per                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
+        uint64_t imr_tto                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
+        uint64_t imr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
+        uint64_t itr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
+        uint64_t imr_wtto                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
+        uint64_t imr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
+        uint64_t itr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
+#else
+        uint64_t itr_wabt                : 1;
+        uint64_t imr_wabt                : 1;
+        uint64_t imr_wtto                : 1;
+        uint64_t itr_abt                 : 1;
+        uint64_t imr_abt                 : 1;
+        uint64_t imr_tto                 : 1;
+        uint64_t imsi_per                : 1;
+        uint64_t imsi_tabt               : 1;
+        uint64_t imsi_mabt               : 1;
+        uint64_t imsc_msg                : 1;
+        uint64_t itsr_abt                : 1;
+        uint64_t iserr                   : 1;
+        uint64_t iaperr                  : 1;
+        uint64_t idperr                  : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t irsl_int                : 1;
+        uint64_t ipcnt0                  : 1;
+        uint64_t reserved_18_20          : 3;
+        uint64_t iptime0                 : 1;
+        uint64_t reserved_22_24          : 3;
+        uint64_t idcnt0                  : 1;
+        uint64_t idcnt1                  : 1;
+        uint64_t idtime0                 : 1;
+        uint64_t idtime1                 : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn30xx;
+    struct cvmx_pci_int_enb_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */
+        uint64_t ill_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */
+        uint64_t win_wr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */
+        uint64_t dma1_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */
+        uint64_t dma0_fi                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */
+        uint64_t idtime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */
+        uint64_t idtime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */
+        uint64_t idcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */
+        uint64_t idcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */
+        uint64_t reserved_23_24          : 2;
+        uint64_t iptime1                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */
+        uint64_t iptime0                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */
+        uint64_t reserved_19_20          : 2;
+        uint64_t ipcnt1                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */
+        uint64_t ipcnt0                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */
+        uint64_t irsl_int                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */
+        uint64_t ill_rrd                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */
+        uint64_t ill_rwr                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */
+        uint64_t idperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */
+        uint64_t iaperr                  : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */
+        uint64_t iserr                   : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */
+        uint64_t itsr_abt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */
+        uint64_t imsc_msg                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */
+        uint64_t imsi_mabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */
+        uint64_t imsi_tabt               : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */
+        uint64_t imsi_per                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */
+        uint64_t imr_tto                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */
+        uint64_t imr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */
+        uint64_t itr_abt                 : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */
+        uint64_t imr_wtto                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */
+        uint64_t imr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */
+        uint64_t itr_wabt                : 1;       /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */
+#else
+        uint64_t itr_wabt                : 1;
+        uint64_t imr_wabt                : 1;
+        uint64_t imr_wtto                : 1;
+        uint64_t itr_abt                 : 1;
+        uint64_t imr_abt                 : 1;
+        uint64_t imr_tto                 : 1;
+        uint64_t imsi_per                : 1;
+        uint64_t imsi_tabt               : 1;
+        uint64_t imsi_mabt               : 1;
+        uint64_t imsc_msg                : 1;
+        uint64_t itsr_abt                : 1;
+        uint64_t iserr                   : 1;
+        uint64_t iaperr                  : 1;
+        uint64_t idperr                  : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t irsl_int                : 1;
+        uint64_t ipcnt0                  : 1;
+        uint64_t ipcnt1                  : 1;
+        uint64_t reserved_19_20          : 2;
+        uint64_t iptime0                 : 1;
+        uint64_t iptime1                 : 1;
+        uint64_t reserved_23_24          : 2;
+        uint64_t idcnt0                  : 1;
+        uint64_t idcnt1                  : 1;
+        uint64_t idtime0                 : 1;
+        uint64_t idtime1                 : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn31xx;
+    struct cvmx_pci_int_enb_s            cn38xx;
+    struct cvmx_pci_int_enb_s            cn38xxp2;
+    struct cvmx_pci_int_enb_cn31xx       cn50xx;
+    struct cvmx_pci_int_enb_s            cn58xx;
+    struct cvmx_pci_int_enb_s            cn58xxp1;
+} cvmx_pci_int_enb_t;
+
+
+/**
+ * cvmx_pci_int_enb2
+ *
+ * PCI_INT_ENB2 = PCI Interrupt Enable2 Register
+ * 
+ * Enables interrupt bits in the PCI_INT_SUM2 register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_int_enb2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
+        uint64_t ill_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
+        uint64_t win_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
+        uint64_t dma1_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
+        uint64_t dma0_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
+        uint64_t rdtime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
+        uint64_t rdtime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
+        uint64_t rdcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
+        uint64_t rdcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
+        uint64_t rptime3                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */
+        uint64_t rptime2                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */
+        uint64_t rptime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */
+        uint64_t rptime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
+        uint64_t rpcnt3                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */
+        uint64_t rpcnt2                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */
+        uint64_t rpcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */
+        uint64_t rpcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
+        uint64_t rrsl_int                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
+        uint64_t ill_rrd                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
+        uint64_t ill_rwr                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
+        uint64_t rdperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
+        uint64_t raperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
+        uint64_t rserr                   : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
+        uint64_t rtsr_abt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
+        uint64_t rmsc_msg                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
+        uint64_t rmsi_mabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
+        uint64_t rmsi_tabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
+        uint64_t rmsi_per                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
+        uint64_t rmr_tto                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
+        uint64_t rmr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
+        uint64_t rtr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
+        uint64_t rmr_wtto                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
+        uint64_t rmr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
+        uint64_t rtr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
+#else
+        uint64_t rtr_wabt                : 1;
+        uint64_t rmr_wabt                : 1;
+        uint64_t rmr_wtto                : 1;
+        uint64_t rtr_abt                 : 1;
+        uint64_t rmr_abt                 : 1;
+        uint64_t rmr_tto                 : 1;
+        uint64_t rmsi_per                : 1;
+        uint64_t rmsi_tabt               : 1;
+        uint64_t rmsi_mabt               : 1;
+        uint64_t rmsc_msg                : 1;
+        uint64_t rtsr_abt                : 1;
+        uint64_t rserr                   : 1;
+        uint64_t raperr                  : 1;
+        uint64_t rdperr                  : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rrsl_int                : 1;
+        uint64_t rpcnt0                  : 1;
+        uint64_t rpcnt1                  : 1;
+        uint64_t rpcnt2                  : 1;
+        uint64_t rpcnt3                  : 1;
+        uint64_t rptime0                 : 1;
+        uint64_t rptime1                 : 1;
+        uint64_t rptime2                 : 1;
+        uint64_t rptime3                 : 1;
+        uint64_t rdcnt0                  : 1;
+        uint64_t rdcnt1                  : 1;
+        uint64_t rdtime0                 : 1;
+        uint64_t rdtime1                 : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_pci_int_enb2_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
+        uint64_t ill_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
+        uint64_t win_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
+        uint64_t dma1_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
+        uint64_t dma0_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
+        uint64_t rdtime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
+        uint64_t rdtime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
+        uint64_t rdcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
+        uint64_t rdcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
+        uint64_t reserved_22_24          : 3;
+        uint64_t rptime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
+        uint64_t reserved_18_20          : 3;
+        uint64_t rpcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
+        uint64_t rrsl_int                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
+        uint64_t ill_rrd                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
+        uint64_t ill_rwr                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
+        uint64_t rdperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
+        uint64_t raperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
+        uint64_t rserr                   : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
+        uint64_t rtsr_abt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
+        uint64_t rmsc_msg                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
+        uint64_t rmsi_mabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
+        uint64_t rmsi_tabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
+        uint64_t rmsi_per                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
+        uint64_t rmr_tto                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
+        uint64_t rmr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
+        uint64_t rtr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
+        uint64_t rmr_wtto                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
+        uint64_t rmr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
+        uint64_t rtr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
+#else
+        uint64_t rtr_wabt                : 1;
+        uint64_t rmr_wabt                : 1;
+        uint64_t rmr_wtto                : 1;
+        uint64_t rtr_abt                 : 1;
+        uint64_t rmr_abt                 : 1;
+        uint64_t rmr_tto                 : 1;
+        uint64_t rmsi_per                : 1;
+        uint64_t rmsi_tabt               : 1;
+        uint64_t rmsi_mabt               : 1;
+        uint64_t rmsc_msg                : 1;
+        uint64_t rtsr_abt                : 1;
+        uint64_t rserr                   : 1;
+        uint64_t raperr                  : 1;
+        uint64_t rdperr                  : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rrsl_int                : 1;
+        uint64_t rpcnt0                  : 1;
+        uint64_t reserved_18_20          : 3;
+        uint64_t rptime0                 : 1;
+        uint64_t reserved_22_24          : 3;
+        uint64_t rdcnt0                  : 1;
+        uint64_t rdcnt1                  : 1;
+        uint64_t rdtime0                 : 1;
+        uint64_t rdtime1                 : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn30xx;
+    struct cvmx_pci_int_enb2_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */
+        uint64_t ill_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */
+        uint64_t win_wr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */
+        uint64_t dma1_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */
+        uint64_t dma0_fi                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */
+        uint64_t rdtime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */
+        uint64_t rdtime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */
+        uint64_t rdcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */
+        uint64_t rdcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */
+        uint64_t reserved_23_24          : 2;
+        uint64_t rptime1                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */
+        uint64_t rptime0                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */
+        uint64_t reserved_19_20          : 2;
+        uint64_t rpcnt1                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */
+        uint64_t rpcnt0                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */
+        uint64_t rrsl_int                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */
+        uint64_t ill_rrd                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */
+        uint64_t ill_rwr                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */
+        uint64_t rdperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */
+        uint64_t raperr                  : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */
+        uint64_t rserr                   : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */
+        uint64_t rtsr_abt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */
+        uint64_t rmsc_msg                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */
+        uint64_t rmsi_mabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */
+        uint64_t rmsi_tabt               : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */
+        uint64_t rmsi_per                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */
+        uint64_t rmr_tto                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */
+        uint64_t rmr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */
+        uint64_t rtr_abt                 : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */
+        uint64_t rmr_wtto                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */
+        uint64_t rmr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */
+        uint64_t rtr_wabt                : 1;       /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */
+#else
+        uint64_t rtr_wabt                : 1;
+        uint64_t rmr_wabt                : 1;
+        uint64_t rmr_wtto                : 1;
+        uint64_t rtr_abt                 : 1;
+        uint64_t rmr_abt                 : 1;
+        uint64_t rmr_tto                 : 1;
+        uint64_t rmsi_per                : 1;
+        uint64_t rmsi_tabt               : 1;
+        uint64_t rmsi_mabt               : 1;
+        uint64_t rmsc_msg                : 1;
+        uint64_t rtsr_abt                : 1;
+        uint64_t rserr                   : 1;
+        uint64_t raperr                  : 1;
+        uint64_t rdperr                  : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rrsl_int                : 1;
+        uint64_t rpcnt0                  : 1;
+        uint64_t rpcnt1                  : 1;
+        uint64_t reserved_19_20          : 2;
+        uint64_t rptime0                 : 1;
+        uint64_t rptime1                 : 1;
+        uint64_t reserved_23_24          : 2;
+        uint64_t rdcnt0                  : 1;
+        uint64_t rdcnt1                  : 1;
+        uint64_t rdtime0                 : 1;
+        uint64_t rdtime1                 : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn31xx;
+    struct cvmx_pci_int_enb2_s           cn38xx;
+    struct cvmx_pci_int_enb2_s           cn38xxp2;
+    struct cvmx_pci_int_enb2_cn31xx      cn50xx;
+    struct cvmx_pci_int_enb2_s           cn58xx;
+    struct cvmx_pci_int_enb2_s           cn58xxp1;
+} cvmx_pci_int_enb2_t;
+
+
+/**
+ * cvmx_pci_int_sum
+ *
+ * PCI_INT_SUM = PCI Interrupt Summary
+ * 
+ * The PCI Interrupt Summary Register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+        uint64_t ptime3                  : 1;       /**< When the value in the PCI_PKTS_SENT3
+                                                         register is not 0 the Sent-3 timer counts.
+                                                         When the Sent-3 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME3 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime2                  : 1;       /**< When the value in the PCI_PKTS_SENT2
+                                                         register is not 0 the Sent-2 timer counts.
+                                                         When the Sent-2 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME2 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t pcnt3                   : 1;       /**< This bit indicates that PCI_PKTS_SENT3
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV3 register. */
+        uint64_t pcnt2                   : 1;       /**< This bit indicates that PCI_PKTS_SENT2
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV2 register. */
+        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+        uint64_t rsl_int                 : 1;       /**< This bit is set when the mio_pci_inta_dr wire
+                                                         is asserted by the MIO. */
+        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
+        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
+        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
+        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
+        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
+        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected
+                                                         O9N (as completer), has encountered an error
+                                                         which prevents the split transaction from
+                                                         completing. In this event, the O9N (as completer),
+                                                         sends a SCM (Split Completion Message) to the
+                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
+                                                            [31:28]: Message Class = 2(completer error)
+                                                            [27:20]: Message Index = 0x80
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:0]: Remaining Byte Count */
+        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message (SCM) Detected
+                                                         for either a Split-Read/Write error case.
+                                                         Set if:
+                                                            a) A Split-Write SCM is detected with SCE=1.
+                                                            b) A Split-Read SCM is detected (regardless
+                                                               of SCE status).
+                                                         The Split completion message(SCM)
+                                                         is also latched into the PCI_SCM_REG[SCM] to
+                                                         assist SW with error recovery. */
+        uint64_t msi_mabt                : 1;       /**< PCI Master Abort on Master MSI */
+        uint64_t msi_tabt                : 1;       /**< PCI Target-Abort on Master MSI */
+        uint64_t msi_per                 : 1;       /**< PCI Parity Error on Master MSI */
+        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Master-Read */
+        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Master-Read */
+        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Master-Read */
+        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on Master-write */
+        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on Master-write */
+        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on Master-write */
+#else
+        uint64_t tr_wabt                 : 1;
+        uint64_t mr_wabt                 : 1;
+        uint64_t mr_wtto                 : 1;
+        uint64_t tr_abt                  : 1;
+        uint64_t mr_abt                  : 1;
+        uint64_t mr_tto                  : 1;
+        uint64_t msi_per                 : 1;
+        uint64_t msi_tabt                : 1;
+        uint64_t msi_mabt                : 1;
+        uint64_t msc_msg                 : 1;
+        uint64_t tsr_abt                 : 1;
+        uint64_t serr                    : 1;
+        uint64_t aperr                   : 1;
+        uint64_t dperr                   : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rsl_int                 : 1;
+        uint64_t pcnt0                   : 1;
+        uint64_t pcnt1                   : 1;
+        uint64_t pcnt2                   : 1;
+        uint64_t pcnt3                   : 1;
+        uint64_t ptime0                  : 1;
+        uint64_t ptime1                  : 1;
+        uint64_t ptime2                  : 1;
+        uint64_t ptime3                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_pci_int_sum_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+        uint64_t reserved_22_24          : 3;
+        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t reserved_18_20          : 3;
+        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+        uint64_t rsl_int                 : 1;       /**< This bit is set when the mio_pci_inta_dr wire
+                                                         is asserted by the MIO */
+        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
+        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
+        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
+        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
+        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
+        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected
+                                                         N3K (as completer), has encountered an error
+                                                         which prevents the split transaction from
+                                                         completing. In this event, the N3K (as completer),
+                                                         sends a SCM (Split Completion Message) to the
+                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
+                                                            [31:28]: Message Class = 2(completer error)
+                                                            [27:20]: Message Index = 0x80
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:0]: Remaining Byte Count */
+        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message (SCM) Detected
+                                                         for either a Split-Read/Write error case.
+                                                         Set if:
+                                                            a) A Split-Write SCM is detected with SCE=1.
+                                                            b) A Split-Read SCM is detected (regardless
+                                                               of SCE status).
+                                                         The Split completion message(SCM)
+                                                         is also latched into the PCI_SCM_REG[SCM] to
+                                                         assist SW with error recovery. */
+        uint64_t msi_mabt                : 1;       /**< PCI Master Abort on Master MSI */
+        uint64_t msi_tabt                : 1;       /**< PCI Target-Abort on Master MSI */
+        uint64_t msi_per                 : 1;       /**< PCI Parity Error on Master MSI */
+        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Master-Read */
+        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Master-Read */
+        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Master-Read */
+        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on Master-write */
+        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on Master-write */
+        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on Master-write */
+#else
+        uint64_t tr_wabt                 : 1;
+        uint64_t mr_wabt                 : 1;
+        uint64_t mr_wtto                 : 1;
+        uint64_t tr_abt                  : 1;
+        uint64_t mr_abt                  : 1;
+        uint64_t mr_tto                  : 1;
+        uint64_t msi_per                 : 1;
+        uint64_t msi_tabt                : 1;
+        uint64_t msi_mabt                : 1;
+        uint64_t msc_msg                 : 1;
+        uint64_t tsr_abt                 : 1;
+        uint64_t serr                    : 1;
+        uint64_t aperr                   : 1;
+        uint64_t dperr                   : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rsl_int                 : 1;
+        uint64_t pcnt0                   : 1;
+        uint64_t reserved_18_20          : 3;
+        uint64_t ptime0                  : 1;
+        uint64_t reserved_22_24          : 3;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn30xx;
+    struct cvmx_pci_int_sum_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+        uint64_t reserved_23_24          : 2;
+        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t reserved_19_20          : 2;
+        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+        uint64_t rsl_int                 : 1;       /**< This bit is set when the mio_pci_inta_dr wire
+                                                         is asserted by the MIO */
+        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
+        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
+        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
+        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
+        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
+        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected
+                                                         N3K (as completer), has encountered an error
+                                                         which prevents the split transaction from
+                                                         completing. In this event, the N3K (as completer),
+                                                         sends a SCM (Split Completion Message) to the
+                                                         initiator. See: PCIX Spec v1.0a Fig 2-40.
+                                                            [31:28]: Message Class = 2(completer error)
+                                                            [27:20]: Message Index = 0x80
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:0]: Remaining Byte Count */
+        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message (SCM) Detected
+                                                         for either a Split-Read/Write error case.
+                                                         Set if:
+                                                            a) A Split-Write SCM is detected with SCE=1.
+                                                            b) A Split-Read SCM is detected (regardless
+                                                               of SCE status).
+                                                         The Split completion message(SCM)
+                                                         is also latched into the PCI_SCM_REG[SCM] to
+                                                         assist SW with error recovery. */
+        uint64_t msi_mabt                : 1;       /**< PCI Master Abort on Master MSI */
+        uint64_t msi_tabt                : 1;       /**< PCI Target-Abort on Master MSI */
+        uint64_t msi_per                 : 1;       /**< PCI Parity Error on Master MSI */
+        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Master-Read */
+        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Master-Read */
+        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Master-Read */
+        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on Master-write */
+        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on Master-write */
+        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on Master-write */
+#else
+        uint64_t tr_wabt                 : 1;
+        uint64_t mr_wabt                 : 1;
+        uint64_t mr_wtto                 : 1;
+        uint64_t tr_abt                  : 1;
+        uint64_t mr_abt                  : 1;
+        uint64_t mr_tto                  : 1;
+        uint64_t msi_per                 : 1;
+        uint64_t msi_tabt                : 1;
+        uint64_t msi_mabt                : 1;
+        uint64_t msc_msg                 : 1;
+        uint64_t tsr_abt                 : 1;
+        uint64_t serr                    : 1;
+        uint64_t aperr                   : 1;
+        uint64_t dperr                   : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rsl_int                 : 1;
+        uint64_t pcnt0                   : 1;
+        uint64_t pcnt1                   : 1;
+        uint64_t reserved_19_20          : 2;
+        uint64_t ptime0                  : 1;
+        uint64_t ptime1                  : 1;
+        uint64_t reserved_23_24          : 2;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn31xx;
+    struct cvmx_pci_int_sum_s            cn38xx;
+    struct cvmx_pci_int_sum_s            cn38xxp2;
+    struct cvmx_pci_int_sum_cn31xx       cn50xx;
+    struct cvmx_pci_int_sum_s            cn58xx;
+    struct cvmx_pci_int_sum_s            cn58xxp1;
+} cvmx_pci_int_sum_t;
+
+
+/**
+ * cvmx_pci_int_sum2
+ *
+ * PCI_INT_SUM2 = PCI Interrupt Summary2 Register
+ * 
+ * The PCI Interrupt Summary2 Register copy used for RSL interrupts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_int_sum2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+        uint64_t ptime3                  : 1;       /**< When the value in the PCI_PKTS_SENT3
+                                                         register is not 0 the Sent-3 timer counts.
+                                                         When the Sent-3 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME3 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime2                  : 1;       /**< When the value in the PCI_PKTS_SENT2
+                                                         register is not 0 the Sent-2 timer counts.
+                                                         When the Sent-2 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME2 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t pcnt3                   : 1;       /**< This bit indicates that PCI_PKTS_SENT3
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV3 register. */
+        uint64_t pcnt2                   : 1;       /**< This bit indicates that PCI_PKTS_SENT2
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV2 register. */
+        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+        uint64_t rsl_int                 : 1;       /**< This bit is set when the RSL Chain has
+                                                         generated an interrupt. */
+        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
+        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
+        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
+        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
+        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
+        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected */
+        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message Detected */
+        uint64_t msi_mabt                : 1;       /**< PCI MSI Master Abort. */
+        uint64_t msi_tabt                : 1;       /**< PCI MSI Target Abort. */
+        uint64_t msi_per                 : 1;       /**< PCI MSI Parity Error. */
+        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Read. */
+        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Read. */
+        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Read. */
+        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on write. */
+        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on write. */
+        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on write. */
+#else
+        uint64_t tr_wabt                 : 1;
+        uint64_t mr_wabt                 : 1;
+        uint64_t mr_wtto                 : 1;
+        uint64_t tr_abt                  : 1;
+        uint64_t mr_abt                  : 1;
+        uint64_t mr_tto                  : 1;
+        uint64_t msi_per                 : 1;
+        uint64_t msi_tabt                : 1;
+        uint64_t msi_mabt                : 1;
+        uint64_t msc_msg                 : 1;
+        uint64_t tsr_abt                 : 1;
+        uint64_t serr                    : 1;
+        uint64_t aperr                   : 1;
+        uint64_t dperr                   : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rsl_int                 : 1;
+        uint64_t pcnt0                   : 1;
+        uint64_t pcnt1                   : 1;
+        uint64_t pcnt2                   : 1;
+        uint64_t pcnt3                   : 1;
+        uint64_t ptime0                  : 1;
+        uint64_t ptime1                  : 1;
+        uint64_t ptime2                  : 1;
+        uint64_t ptime3                  : 1;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } s;
+    struct cvmx_pci_int_sum2_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+        uint64_t reserved_22_24          : 3;
+        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t reserved_18_20          : 3;
+        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+        uint64_t rsl_int                 : 1;       /**< This bit is set when the RSL Chain has
+                                                         generated an interrupt. */
+        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
+        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
+        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
+        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
+        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
+        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected */
+        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message Detected */
+        uint64_t msi_mabt                : 1;       /**< PCI MSI Master Abort. */
+        uint64_t msi_tabt                : 1;       /**< PCI MSI Target Abort. */
+        uint64_t msi_per                 : 1;       /**< PCI MSI Parity Error. */
+        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Read. */
+        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Read. */
+        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Read. */
+        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on write. */
+        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on write. */
+        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on write. */
+#else
+        uint64_t tr_wabt                 : 1;
+        uint64_t mr_wabt                 : 1;
+        uint64_t mr_wtto                 : 1;
+        uint64_t tr_abt                  : 1;
+        uint64_t mr_abt                  : 1;
+        uint64_t mr_tto                  : 1;
+        uint64_t msi_per                 : 1;
+        uint64_t msi_tabt                : 1;
+        uint64_t msi_mabt                : 1;
+        uint64_t msc_msg                 : 1;
+        uint64_t tsr_abt                 : 1;
+        uint64_t serr                    : 1;
+        uint64_t aperr                   : 1;
+        uint64_t dperr                   : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rsl_int                 : 1;
+        uint64_t pcnt0                   : 1;
+        uint64_t reserved_18_20          : 3;
+        uint64_t ptime0                  : 1;
+        uint64_t reserved_22_24          : 3;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn30xx;
+    struct cvmx_pci_int_sum2_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_34_63          : 30;
+        uint64_t ill_rd                  : 1;       /**< A read to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t ill_wr                  : 1;       /**< A write to a disabled area of bar1 or bar2,
+                                                         when the mem area is disabled. */
+        uint64_t win_wr                  : 1;       /**< A write to the disabled Window Write Data or
+                                                         Read-Address Register took place. */
+        uint64_t dma1_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 1. */
+        uint64_t dma0_fi                 : 1;       /**< A DMA operation operation finished that was
+                                                         required to set the FORCE-INT bit for counter 0. */
+        uint64_t dtime1                  : 1;       /**< When the value in the PCI_DMA_CNT1
+                                                         register is not 0 the DMA_CNT1 timer counts.
+                                                         When the DMA1_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dtime0                  : 1;       /**< When the value in the PCI_DMA_CNT0
+                                                         register is not 0 the DMA_CNT0 timer counts.
+                                                         When the DMA0_CNT timer has a value greater
+                                                         than the PCI_DMA_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t dcnt1                   : 1;       /**< This bit indicates that PCI_DMA_CNT1
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV1 register. */
+        uint64_t dcnt0                   : 1;       /**< This bit indicates that PCI_DMA_CNT0
+                                                         value is greater than the value
+                                                         in the PCI_DMA_INT_LEV0 register. */
+        uint64_t reserved_23_24          : 2;
+        uint64_t ptime1                  : 1;       /**< When the value in the PCI_PKTS_SENT1
+                                                         register is not 0 the Sent-1 timer counts.
+                                                         When the Sent-1 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME1 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t ptime0                  : 1;       /**< When the value in the PCI_PKTS_SENT0
+                                                         register is not 0 the Sent-0 timer counts.
+                                                         When the Sent-0 timer has a value greater
+                                                         than the PCI_PKTS_SENT_TIME0 register this
+                                                         bit is set. The timer is reset when bit is
+                                                         written with a one. */
+        uint64_t reserved_19_20          : 2;
+        uint64_t pcnt1                   : 1;       /**< This bit indicates that PCI_PKTS_SENT1
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV1 register. */
+        uint64_t pcnt0                   : 1;       /**< This bit indicates that PCI_PKTS_SENT0
+                                                         value is greater than the value
+                                                         in the PCI_PKTS_SENT_INT_LEV0 register. */
+        uint64_t rsl_int                 : 1;       /**< This bit is set when the RSL Chain has
+                                                         generated an interrupt. */
+        uint64_t ill_rrd                 : 1;       /**< A read  to the disabled PCI registers took place. */
+        uint64_t ill_rwr                 : 1;       /**< A write to the disabled PCI registers took place. */
+        uint64_t dperr                   : 1;       /**< Data Parity Error detected by PCX Core */
+        uint64_t aperr                   : 1;       /**< Address Parity Error detected by PCX Core */
+        uint64_t serr                    : 1;       /**< SERR# detected by PCX Core */
+        uint64_t tsr_abt                 : 1;       /**< Target Split-Read Abort Detected */
+        uint64_t msc_msg                 : 1;       /**< Master Split Completion Message Detected */
+        uint64_t msi_mabt                : 1;       /**< PCI MSI Master Abort. */
+        uint64_t msi_tabt                : 1;       /**< PCI MSI Target Abort. */
+        uint64_t msi_per                 : 1;       /**< PCI MSI Parity Error. */
+        uint64_t mr_tto                  : 1;       /**< PCI Master Retry Timeout On Read. */
+        uint64_t mr_abt                  : 1;       /**< PCI Master Abort On Read. */
+        uint64_t tr_abt                  : 1;       /**< PCI Target Abort On Read. */
+        uint64_t mr_wtto                 : 1;       /**< PCI Master Retry Timeout on write. */
+        uint64_t mr_wabt                 : 1;       /**< PCI Master Abort detected on write. */
+        uint64_t tr_wabt                 : 1;       /**< PCI Target Abort detected on write. */
+#else
+        uint64_t tr_wabt                 : 1;
+        uint64_t mr_wabt                 : 1;
+        uint64_t mr_wtto                 : 1;
+        uint64_t tr_abt                  : 1;
+        uint64_t mr_abt                  : 1;
+        uint64_t mr_tto                  : 1;
+        uint64_t msi_per                 : 1;
+        uint64_t msi_tabt                : 1;
+        uint64_t msi_mabt                : 1;
+        uint64_t msc_msg                 : 1;
+        uint64_t tsr_abt                 : 1;
+        uint64_t serr                    : 1;
+        uint64_t aperr                   : 1;
+        uint64_t dperr                   : 1;
+        uint64_t ill_rwr                 : 1;
+        uint64_t ill_rrd                 : 1;
+        uint64_t rsl_int                 : 1;
+        uint64_t pcnt0                   : 1;
+        uint64_t pcnt1                   : 1;
+        uint64_t reserved_19_20          : 2;
+        uint64_t ptime0                  : 1;
+        uint64_t ptime1                  : 1;
+        uint64_t reserved_23_24          : 2;
+        uint64_t dcnt0                   : 1;
+        uint64_t dcnt1                   : 1;
+        uint64_t dtime0                  : 1;
+        uint64_t dtime1                  : 1;
+        uint64_t dma0_fi                 : 1;
+        uint64_t dma1_fi                 : 1;
+        uint64_t win_wr                  : 1;
+        uint64_t ill_wr                  : 1;
+        uint64_t ill_rd                  : 1;
+        uint64_t reserved_34_63          : 30;
+#endif
+    } cn31xx;
+    struct cvmx_pci_int_sum2_s           cn38xx;
+    struct cvmx_pci_int_sum2_s           cn38xxp2;
+    struct cvmx_pci_int_sum2_cn31xx      cn50xx;
+    struct cvmx_pci_int_sum2_s           cn58xx;
+    struct cvmx_pci_int_sum2_s           cn58xxp1;
+} cvmx_pci_int_sum2_t;
+
+
+/**
+ * cvmx_pci_msi_rcv
+ *
+ * PCI_MSI_RCV = PCI's MSI Received Vector Register
+ * 
+ * A bit is set in this register relative to the vector received during a MSI. The value in this
+ * register is acted upon when the least-significant-byte of this register is written.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_msi_rcv_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_6_31           : 26;
+        uint32_t intr                    : 6;       /**< When an MSI is received on the PCI the bit selected
+                                                         by data [5:0] will be set in this register. To
+                                                         clear this bit a write must take place to the
+                                                         NPI_MSI_RCV register where any bit set to 1 is
+                                                         cleared. Reading this address will return an
+                                                         unpredicatable value. */
+#else
+        uint32_t intr                    : 6;
+        uint32_t reserved_6_31           : 26;
+#endif
+    } s;
+    struct cvmx_pci_msi_rcv_s            cn30xx;
+    struct cvmx_pci_msi_rcv_s            cn31xx;
+    struct cvmx_pci_msi_rcv_s            cn38xx;
+    struct cvmx_pci_msi_rcv_s            cn38xxp2;
+    struct cvmx_pci_msi_rcv_s            cn50xx;
+    struct cvmx_pci_msi_rcv_s            cn58xx;
+    struct cvmx_pci_msi_rcv_s            cn58xxp1;
+} cvmx_pci_msi_rcv_t;
+
+
+/**
+ * cvmx_pci_pkt_credits#
+ *
+ * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0
+ * 
+ * Used to decrease the number of packets to be processed by the host from Output-0 and return
+ * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the
+ * least-significant-byte of this register is written.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_pkt_creditsx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pkt_cnt                 : 16;      /**< The value written to this field will be
+                                                         subtracted from PCI_PKTS_SENT0[PKT_CNT]. */
+        uint32_t ptr_cnt                 : 16;      /**< This field value is added to the
+                                                         NPI's internal Buffer/Info Pointer Pair count. */
+#else
+        uint32_t ptr_cnt                 : 16;
+        uint32_t pkt_cnt                 : 16;
+#endif
+    } s;
+    struct cvmx_pci_pkt_creditsx_s       cn30xx;
+    struct cvmx_pci_pkt_creditsx_s       cn31xx;
+    struct cvmx_pci_pkt_creditsx_s       cn38xx;
+    struct cvmx_pci_pkt_creditsx_s       cn38xxp2;
+    struct cvmx_pci_pkt_creditsx_s       cn50xx;
+    struct cvmx_pci_pkt_creditsx_s       cn58xx;
+    struct cvmx_pci_pkt_creditsx_s       cn58xxp1;
+} cvmx_pci_pkt_creditsx_t;
+
+
+/**
+ * cvmx_pci_pkts_sent#
+ *
+ * PCI_PKTS_SENT0 = PCI Packets Sent 0
+ * 
+ * Number of packets sent to the host memory from PCI Output 0
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_pkts_sentx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pkt_cnt                 : 32;      /**< Each time a packet is written to the memory via
+                                                         PCI from PCI Output 0,  this counter is
+                                                         incremented by 1 or the byte count of the packet
+                                                         as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */
+#else
+        uint32_t pkt_cnt                 : 32;
+#endif
+    } s;
+    struct cvmx_pci_pkts_sentx_s         cn30xx;
+    struct cvmx_pci_pkts_sentx_s         cn31xx;
+    struct cvmx_pci_pkts_sentx_s         cn38xx;
+    struct cvmx_pci_pkts_sentx_s         cn38xxp2;
+    struct cvmx_pci_pkts_sentx_s         cn50xx;
+    struct cvmx_pci_pkts_sentx_s         cn58xx;
+    struct cvmx_pci_pkts_sentx_s         cn58xxp1;
+} cvmx_pci_pkts_sentx_t;
+
+
+/**
+ * cvmx_pci_pkts_sent_int_lev#
+ *
+ * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0
+ * 
+ * Interrupt when number of packets sent is equal to or greater than the register value.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_pkts_sent_int_levx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pkt_cnt                 : 32;      /**< When corresponding port's PCI_PKTS_SENT0 value
+                                                         exceeds the value in this register, PCNT0 of the
+                                                         PCI_INT_SUM and PCI_INT_SUM2 will be set. */
+#else
+        uint32_t pkt_cnt                 : 32;
+#endif
+    } s;
+    struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
+    struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
+    struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
+    struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
+    struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
+    struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
+    struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
+} cvmx_pci_pkts_sent_int_levx_t;
+
+
+/**
+ * cvmx_pci_pkts_sent_time#
+ *
+ * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0
+ * 
+ * Time to wait from packet being sent to host from Output-0 before issuing an interrupt.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_pkts_sent_timex_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pkt_time                : 32;      /**< Number of PCI clock cycle to wait before
+                                                         issuing an interrupt to the host when a
+                                                         packet from this port has been sent to the
+                                                         host.  The timer is reset when the
+                                                         PCI_INT_SUM[21] register is cleared. */
+#else
+        uint32_t pkt_time                : 32;
+#endif
+    } s;
+    struct cvmx_pci_pkts_sent_timex_s    cn30xx;
+    struct cvmx_pci_pkts_sent_timex_s    cn31xx;
+    struct cvmx_pci_pkts_sent_timex_s    cn38xx;
+    struct cvmx_pci_pkts_sent_timex_s    cn38xxp2;
+    struct cvmx_pci_pkts_sent_timex_s    cn50xx;
+    struct cvmx_pci_pkts_sent_timex_s    cn58xx;
+    struct cvmx_pci_pkts_sent_timex_s    cn58xxp1;
+} cvmx_pci_pkts_sent_timex_t;
+
+
+/**
+ * cvmx_pci_read_cmd_6
+ *
+ * PCI_READ_CMD_6 = PCI Read Command 6 Register
+ * 
+ * Contains control inforamtion related to a received PCI Command 6.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_read_cmd_6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_9_31           : 23;
+        uint32_t min_data                : 6;       /**< The number of words to have buffered in the PNI
+                                                         before informing the PCIX-Core that we have
+                                                         read data available for the outstanding Delayed
+                                                         read. 0 is treated as a 64.
+                                                         For reads to the expansion this value is not used. */
+        uint32_t prefetch                : 3;       /**< Control the amount of data to be preteched when
+                                                         this type of bhmstREAD command is received.
+                                                         0 = 1 32/64 bit word.
+                                                         1 = From address to end of 128B block.
+                                                         2 = From address to end of 128B block plus 128B.
+                                                         3 = From address to end of 128B block plus 256B.
+                                                         4 = From address to end of 128B block plus 384B.
+                                                         For reads to the expansion this value is not used. */
+#else
+        uint32_t prefetch                : 3;
+        uint32_t min_data                : 6;
+        uint32_t reserved_9_31           : 23;
+#endif
+    } s;
+    struct cvmx_pci_read_cmd_6_s         cn30xx;
+    struct cvmx_pci_read_cmd_6_s         cn31xx;
+    struct cvmx_pci_read_cmd_6_s         cn38xx;
+    struct cvmx_pci_read_cmd_6_s         cn38xxp2;
+    struct cvmx_pci_read_cmd_6_s         cn50xx;
+    struct cvmx_pci_read_cmd_6_s         cn58xx;
+    struct cvmx_pci_read_cmd_6_s         cn58xxp1;
+} cvmx_pci_read_cmd_6_t;
+
+
+/**
+ * cvmx_pci_read_cmd_c
+ *
+ * PCI_READ_CMD_C = PCI Read Command C Register
+ * 
+ * Contains control inforamtion related to a received PCI Command C.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_read_cmd_c_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_9_31           : 23;
+        uint32_t min_data                : 6;       /**< The number of words to have buffered in the PNI
+                                                         before informing the PCIX-Core that we have
+                                                         read data available for the outstanding Delayed
+                                                         read. 0 is treated as a 64.
+                                                         For reads to the expansion this value is not used. */
+        uint32_t prefetch                : 3;       /**< Control the amount of data to be preteched when
+                                                         this type of READ command is received.
+                                                         0 = 1 32/64 bit word.
+                                                         1 = From address to end of 128B block.
+                                                         2 = From address to end of 128B block plus 128B.
+                                                         3 = From address to end of 128B block plus 256B.
+                                                         4 = From address to end of 128B block plus 384B.
+                                                         For reads to the expansion this value is not used. */
+#else
+        uint32_t prefetch                : 3;
+        uint32_t min_data                : 6;
+        uint32_t reserved_9_31           : 23;
+#endif
+    } s;
+    struct cvmx_pci_read_cmd_c_s         cn30xx;
+    struct cvmx_pci_read_cmd_c_s         cn31xx;
+    struct cvmx_pci_read_cmd_c_s         cn38xx;
+    struct cvmx_pci_read_cmd_c_s         cn38xxp2;
+    struct cvmx_pci_read_cmd_c_s         cn50xx;
+    struct cvmx_pci_read_cmd_c_s         cn58xx;
+    struct cvmx_pci_read_cmd_c_s         cn58xxp1;
+} cvmx_pci_read_cmd_c_t;
+
+
+/**
+ * cvmx_pci_read_cmd_e
+ *
+ * PCI_READ_CMD_E = PCI Read Command E Register
+ * 
+ * Contains control inforamtion related to a received PCI Command 6.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pci_read_cmd_e_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_9_31           : 23;
+        uint32_t min_data                : 6;       /**< The number of words to have buffered in the PNI
+                                                         before informaing the PCIX-Core that we have
+                                                         read data available for the outstanding Delayed
+                                                         read. 0 is treated as a 64.
+                                                         For reads to the expansion this value is not used. */
+        uint32_t prefetch                : 3;       /**< Control the amount of data to be preteched when
+                                                         this type of READ command is received.
+                                                         0 = 1 32/64 bit word.
+                                                         1 = From address to end of 128B block.
+                                                         2 = From address to end of 128B block plus 128B.
+                                                         3 = From address to end of 128B block plus 256B.
+                                                         4 = From address to end of 128B block plus 384B.
+                                                         For reads to the expansion this value is not used. */
+#else
+        uint32_t prefetch                : 3;
+        uint32_t min_data                : 6;
+        uint32_t reserved_9_31           : 23;
+#endif
+    } s;
+    struct cvmx_pci_read_cmd_e_s         cn30xx;
+    struct cvmx_pci_read_cmd_e_s         cn31xx;
+    struct cvmx_pci_read_cmd_e_s         cn38xx;
+    struct cvmx_pci_read_cmd_e_s         cn38xxp2;
+    struct cvmx_pci_read_cmd_e_s         cn50xx;
+    struct cvmx_pci_read_cmd_e_s         cn58xx;
+    struct cvmx_pci_read_cmd_e_s         cn58xxp1;
+} cvmx_pci_read_cmd_e_t;
+
+
+/**
+ * cvmx_pci_read_timeout
+ *
+ * PCI_READ_TIMEOUT = PCI Read Timeour Register
+ * 
+ * The address to start reading Instructions from for Input-3.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_read_timeout_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t enb                     : 1;       /**< Enable the use of the Timeout function. */
+        uint64_t cnt                     : 31;      /**< The number of eclk cycles to wait after issuing
+                                                         a read request to the PNI before setting a
+                                                         timeout and not expecting the data to return.
+                                                         This is considered a fatal condition by the NPI. */
+#else
+        uint64_t cnt                     : 31;
+        uint64_t enb                     : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pci_read_timeout_s       cn30xx;
+    struct cvmx_pci_read_timeout_s       cn31xx;
+    struct cvmx_pci_read_timeout_s       cn38xx;
+    struct cvmx_pci_read_timeout_s       cn38xxp2;
+    struct cvmx_pci_read_timeout_s       cn50xx;
+    struct cvmx_pci_read_timeout_s       cn58xx;
+    struct cvmx_pci_read_timeout_s       cn58xxp1;
+} cvmx_pci_read_timeout_t;
+
+
+/**
+ * cvmx_pci_scm_reg
+ *
+ * PCI_SCM_REG = PCI Master Split Completion Message Register
+ * 
+ * This register contains the Master Split Completion Message(SCM) generated when a master split
+ * transaction is aborted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_scm_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t scm                     : 32;      /**< Contains the Split Completion Message (SCM)
+                                                         driven when a master-split transaction is aborted.
+                                                            [31:28]: Message Class
+                                                            [27:20]: Message Index
+                                                            [19]:    Reserved
+                                                            [18:12]: Remaining Lower Address
+                                                            [11:8]:  Upper Remaining Byte Count
+                                                            [7:0]:   Lower Remaining Byte Count
+                                                         Refer to the PCIX1.0a specification, Fig 2-40
+                                                         for additional details for the split completion
+                                                         message format. */
+#else
+        uint64_t scm                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pci_scm_reg_s            cn30xx;
+    struct cvmx_pci_scm_reg_s            cn31xx;
+    struct cvmx_pci_scm_reg_s            cn38xx;
+    struct cvmx_pci_scm_reg_s            cn38xxp2;
+    struct cvmx_pci_scm_reg_s            cn50xx;
+    struct cvmx_pci_scm_reg_s            cn58xx;
+    struct cvmx_pci_scm_reg_s            cn58xxp1;
+} cvmx_pci_scm_reg_t;
+
+
+/**
+ * cvmx_pci_tsr_reg
+ *
+ * PCI_TSR_REG = PCI Target Split Attribute Register
+ * 
+ * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split
+ * transaction is aborted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_tsr_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t tsr                     : 36;      /**< Contains the Target Split Attribute field when a
+                                                         target-split transaction is aborted.
+                                                           [35:32]: Upper Byte Count
+                                                           [31]:    BCM=Byte Count Modified
+                                                           [30]:    SCE=Split Completion Error
+                                                           [29]:    SCM=Split Completion Message
+                                                           [28:24]: RESERVED
+                                                           [23:16]: Completer Bus Number
+                                                           [15:11]: Completer Device Number
+                                                           [10:8]:  Completer Function Number
+                                                           [7:0]:   Lower Byte Count
+                                                         Refer to the PCIX1.0a specification, Fig 2-39
+                                                         for additional details on the completer attribute
+                                                         bit assignments. */
+#else
+        uint64_t tsr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_pci_tsr_reg_s            cn30xx;
+    struct cvmx_pci_tsr_reg_s            cn31xx;
+    struct cvmx_pci_tsr_reg_s            cn38xx;
+    struct cvmx_pci_tsr_reg_s            cn38xxp2;
+    struct cvmx_pci_tsr_reg_s            cn50xx;
+    struct cvmx_pci_tsr_reg_s            cn58xx;
+    struct cvmx_pci_tsr_reg_s            cn58xxp1;
+} cvmx_pci_tsr_reg_t;
+
+
+/**
+ * cvmx_pci_win_rd_addr
+ *
+ * PCI_WIN_RD_ADDR = PCI Window Read Address Register
+ * 
+ * Writing the least-significant-byte of this register will cause a read operation to take place,
+ * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA
+ * register is read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_win_rd_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+        uint64_t reserved_0_47           : 48;
+#else
+        uint64_t reserved_0_47           : 48;
+        uint64_t iobit                   : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_pci_win_rd_addr_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+        uint64_t rd_addr                 : 46;      /**< The address to be read from. Whenever the LSB of
+                                                         this register is written, the Read Operation will
+                                                         take place.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:2]  == RSL Register Offset
+                                                              [1:0]   == x, Not Used */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t rd_addr                 : 46;
+        uint64_t iobit                   : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } cn30xx;
+    struct cvmx_pci_win_rd_addr_cn30xx   cn31xx;
+    struct cvmx_pci_win_rd_addr_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+        uint64_t rd_addr                 : 45;      /**< The address to be read from. Whenever the LSB of
+                                                         this register is written, the Read Operation will
+                                                         take place.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:3]  == RSL Register Offset
+                                                              [2:0]   == x, Not Used */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t rd_addr                 : 45;
+        uint64_t iobit                   : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } cn38xx;
+    struct cvmx_pci_win_rd_addr_cn38xx   cn38xxp2;
+    struct cvmx_pci_win_rd_addr_cn30xx   cn50xx;
+    struct cvmx_pci_win_rd_addr_cn38xx   cn58xx;
+    struct cvmx_pci_win_rd_addr_cn38xx   cn58xxp1;
+} cvmx_pci_win_rd_addr_t;
+
+
+/**
+ * cvmx_pci_win_rd_data
+ *
+ * PCI_WIN_RD_DATA = PCI Window Read Data Register
+ * 
+ * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR
+ * register was written.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_win_rd_data_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t rd_data                 : 64;      /**< The read data. */
+#else
+        uint64_t rd_data                 : 64;
+#endif
+    } s;
+    struct cvmx_pci_win_rd_data_s        cn30xx;
+    struct cvmx_pci_win_rd_data_s        cn31xx;
+    struct cvmx_pci_win_rd_data_s        cn38xx;
+    struct cvmx_pci_win_rd_data_s        cn38xxp2;
+    struct cvmx_pci_win_rd_data_s        cn50xx;
+    struct cvmx_pci_win_rd_data_s        cn58xx;
+    struct cvmx_pci_win_rd_data_s        cn58xxp1;
+} cvmx_pci_win_rd_data_t;
+
+
+/**
+ * cvmx_pci_win_wr_addr
+ *
+ * PCI_WIN_WR_ADDR = PCI Window Write Address Register
+ * 
+ * Contains the address to be writen to when a write operation is started by writing the
+ * PCI_WIN_WR_DATA register (see below).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_win_wr_addr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t iobit                   : 1;       /**< A 1 or 0 can be written here but this will always
+                                                         read as '0'. */
+        uint64_t wr_addr                 : 45;      /**< The address that will be written to when the
+                                                         PCI_WIN_WR_DATA register is written.
+                                                         [47:40] = NCB_ID
+                                                         [39:3]  = Address
+                                                         When [47:43] == NPI & [42:0] == 0 bits [39:0] are:
+                                                              [39:32] == x, Not Used
+                                                              [31:27] == RSL_ID
+                                                              [12:3]  == RSL Register Offset
+                                                              [2:0]   == x, Not Used */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t wr_addr                 : 45;
+        uint64_t iobit                   : 1;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_pci_win_wr_addr_s        cn30xx;
+    struct cvmx_pci_win_wr_addr_s        cn31xx;
+    struct cvmx_pci_win_wr_addr_s        cn38xx;
+    struct cvmx_pci_win_wr_addr_s        cn38xxp2;
+    struct cvmx_pci_win_wr_addr_s        cn50xx;
+    struct cvmx_pci_win_wr_addr_s        cn58xx;
+    struct cvmx_pci_win_wr_addr_s        cn58xxp1;
+} cvmx_pci_win_wr_addr_t;
+
+
+/**
+ * cvmx_pci_win_wr_data
+ *
+ * PCI_WIN_WR_DATA = PCI Window Write Data Register
+ * 
+ * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register.
+ * Writing the least-significant-byte of this register will cause a write operation to take place.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_win_wr_data_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t wr_data                 : 64;      /**< The data to be written. Whenever the LSB of this
+                                                         register is written, the Window Write will take
+                                                         place. */
+#else
+        uint64_t wr_data                 : 64;
+#endif
+    } s;
+    struct cvmx_pci_win_wr_data_s        cn30xx;
+    struct cvmx_pci_win_wr_data_s        cn31xx;
+    struct cvmx_pci_win_wr_data_s        cn38xx;
+    struct cvmx_pci_win_wr_data_s        cn38xxp2;
+    struct cvmx_pci_win_wr_data_s        cn50xx;
+    struct cvmx_pci_win_wr_data_s        cn58xx;
+    struct cvmx_pci_win_wr_data_s        cn58xxp1;
+} cvmx_pci_win_wr_data_t;
+
+
+/**
+ * cvmx_pci_win_wr_mask
+ *
+ * PCI_WIN_WR_MASK = PCI Window Write Mask Register
+ * 
+ * Contains the mask for the data in the PCI_WIN_WR_DATA Register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pci_win_wr_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t wr_mask                 : 8;       /**< The data to be written. When a bit is set '1'
+                                                         the corresponding byte will not be written. */
+#else
+        uint64_t wr_mask                 : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pci_win_wr_mask_s        cn30xx;
+    struct cvmx_pci_win_wr_mask_s        cn31xx;
+    struct cvmx_pci_win_wr_mask_s        cn38xx;
+    struct cvmx_pci_win_wr_mask_s        cn38xxp2;
+    struct cvmx_pci_win_wr_mask_s        cn50xx;
+    struct cvmx_pci_win_wr_mask_s        cn58xx;
+    struct cvmx_pci_win_wr_mask_s        cn58xxp1;
+} cvmx_pci_win_wr_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg000
+ *
+ * PCIE_CFG000 = First 32-bits of PCIE type 0 config space (Device ID and Vendor ID Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg000_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t devid                   : 16;      /**< Device ID, writable through the DBI
+                                                          However, the application must not change this field.
+                                                         For EEPROM loads also see VENDID of this register. */
+        uint32_t vendid                  : 16;      /**< Vendor ID, writable through the DBI
+                                                          However, the application must not change this field.
+                                                         During and EPROM Load is a value of 0xFFFF is loaded to this
+                                                         field and a value of 0xFFFF is loaded to the DEVID field of
+                                                         this register, the value will not be loaded, EEPROM load will
+                                                         stop, and the FastLinkEnable bit will be set in the
+                                                         PCIE_CFG452 register. */
+#else
+        uint32_t vendid                  : 16;
+        uint32_t devid                   : 16;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg000_s          cn52xx;
+    struct cvmx_pcieep_cfg000_s          cn52xxp1;
+    struct cvmx_pcieep_cfg000_s          cn56xx;
+    struct cvmx_pcieep_cfg000_s          cn56xxp1;
+} cvmx_pcieep_cfg000_t;
+
+
+/**
+ * cvmx_pcieep_cfg001
+ *
+ * PCIE_CFG001 = Second 32-bits of PCIE type 0 config space (Command/Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg001_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dpe                     : 1;       /**< Detected Parity Error */
+        uint32_t sse                     : 1;       /**< Signaled System Error */
+        uint32_t rma                     : 1;       /**< Received Master Abort */
+        uint32_t rta                     : 1;       /**< Received Target Abort */
+        uint32_t sta                     : 1;       /**< Signaled Target Abort */
+        uint32_t devt                    : 2;       /**< DEVSEL Timing
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
+        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t reserved_22_22          : 1;
+        uint32_t m66                     : 1;       /**< 66 MHz Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t cl                      : 1;       /**< Capabilities List
+                                                         Indicates presence of an extended capability item.
+                                                         Hardwired to 1. */
+        uint32_t i_stat                  : 1;       /**< INTx Status */
+        uint32_t reserved_11_18          : 8;
+        uint32_t i_dis                   : 1;       /**< INTx Assertion Disable */
+        uint32_t fbbe                    : 1;       /**< Fast Back-to-Back Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t see                     : 1;       /**< SERR# Enable */
+        uint32_t ids_wcc                 : 1;       /**< IDSEL Stepping/Wait Cycle Control
+                                                         Not applicable for PCI Express. Must be hardwired to 0 */
+        uint32_t per                     : 1;       /**< Parity Error Response */
+        uint32_t vps                     : 1;       /**< VGA Palette Snoop
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t mwice                   : 1;       /**< Memory Write and Invalidate
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t scse                    : 1;       /**< Special Cycle Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t me                      : 1;       /**< Bus Master Enable */
+        uint32_t msae                    : 1;       /**< Memory Space Enable */
+        uint32_t isae                    : 1;       /**< I/O Space Enable */
+#else
+        uint32_t isae                    : 1;
+        uint32_t msae                    : 1;
+        uint32_t me                      : 1;
+        uint32_t scse                    : 1;
+        uint32_t mwice                   : 1;
+        uint32_t vps                     : 1;
+        uint32_t per                     : 1;
+        uint32_t ids_wcc                 : 1;
+        uint32_t see                     : 1;
+        uint32_t fbbe                    : 1;
+        uint32_t i_dis                   : 1;
+        uint32_t reserved_11_18          : 8;
+        uint32_t i_stat                  : 1;
+        uint32_t cl                      : 1;
+        uint32_t m66                     : 1;
+        uint32_t reserved_22_22          : 1;
+        uint32_t fbb                     : 1;
+        uint32_t mdpe                    : 1;
+        uint32_t devt                    : 2;
+        uint32_t sta                     : 1;
+        uint32_t rta                     : 1;
+        uint32_t rma                     : 1;
+        uint32_t sse                     : 1;
+        uint32_t dpe                     : 1;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg001_s          cn52xx;
+    struct cvmx_pcieep_cfg001_s          cn52xxp1;
+    struct cvmx_pcieep_cfg001_s          cn56xx;
+    struct cvmx_pcieep_cfg001_s          cn56xxp1;
+} cvmx_pcieep_cfg001_t;
+
+
+/**
+ * cvmx_pcieep_cfg002
+ *
+ * PCIE_CFG002 = Third 32-bits of PCIE type 0 config space (Revision ID/Class Code Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg002_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t bcc                     : 8;       /**< Base Class Code, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t sc                      : 8;       /**< Subclass Code, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t pi                      : 8;       /**< Programming Interface, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t rid                     : 8;       /**< Revision ID, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t rid                     : 8;
+        uint32_t pi                      : 8;
+        uint32_t sc                      : 8;
+        uint32_t bcc                     : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg002_s          cn52xx;
+    struct cvmx_pcieep_cfg002_s          cn52xxp1;
+    struct cvmx_pcieep_cfg002_s          cn56xx;
+    struct cvmx_pcieep_cfg002_s          cn56xxp1;
+} cvmx_pcieep_cfg002_t;
+
+
+/**
+ * cvmx_pcieep_cfg003
+ *
+ * PCIE_CFG003 = Fourth 32-bits of PCIE type 0 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg003_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t bist                    : 8;       /**< The BIST register functions are not supported.
+                                                         All 8 bits of the BIST register are hardwired to 0. */
+        uint32_t mfd                     : 1;       /**< Multi Function Device
+                                                         The Multi Function Device bit is writable through the DBI.
+                                                         However, this is a single function device. Therefore, the
+                                                         application must not write a 1 to this bit. */
+        uint32_t chf                     : 7;       /**< Configuration Header Format
+                                                         Hardwired to 0 for type 0. */
+        uint32_t lt                      : 8;       /**< Master Latency Timer
+                                                         Not applicable for PCI Express, hardwired to 0. */
+        uint32_t cls                     : 8;       /**< Cache Line Size
+                                                         The Cache Line Size register is RW for legacy compatibility
+                                                         purposes and is not applicable to PCI Express device
+                                                         functionality.
+                                                         Writing to the Cache Line Size register does not impact
+                                                         functionality. */
+#else
+        uint32_t cls                     : 8;
+        uint32_t lt                      : 8;
+        uint32_t chf                     : 7;
+        uint32_t mfd                     : 1;
+        uint32_t bist                    : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg003_s          cn52xx;
+    struct cvmx_pcieep_cfg003_s          cn52xxp1;
+    struct cvmx_pcieep_cfg003_s          cn56xx;
+    struct cvmx_pcieep_cfg003_s          cn56xxp1;
+} cvmx_pcieep_cfg003_t;
+
+
+/**
+ * cvmx_pcieep_cfg004
+ *
+ * PCIE_CFG004 = Fifth 32-bits of PCIE type 0 config space (Base Address Register 0 - Low)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg004_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lbab                    : 18;      /**< Lower bits of the BAR 0 base address */
+        uint32_t reserved_4_13           : 10;
+        uint32_t pf                      : 1;       /**< Prefetchable
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t typ                     : 2;       /**< BAR type
+                                                            o 00 = 32-bit BAR
+                                                            o 10 = 64-bit BAR
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t mspc                    : 1;       /**< Memory Space Indicator
+                                                            o 0 = BAR 0 is a memory BAR
+                                                            o 1 = BAR 0 is an I/O BAR
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t mspc                    : 1;
+        uint32_t typ                     : 2;
+        uint32_t pf                      : 1;
+        uint32_t reserved_4_13           : 10;
+        uint32_t lbab                    : 18;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg004_s          cn52xx;
+    struct cvmx_pcieep_cfg004_s          cn52xxp1;
+    struct cvmx_pcieep_cfg004_s          cn56xx;
+    struct cvmx_pcieep_cfg004_s          cn56xxp1;
+} cvmx_pcieep_cfg004_t;
+
+
+/**
+ * cvmx_pcieep_cfg004_mask
+ *
+ * PCIE_CFG004_MASK (BAR Mask 0 - Low)
+ * The BAR 0 Mask register is invisible to host software and not readable from the application.
+ * The BAR 0 Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg004_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lmask                   : 31;      /**< Bar Mask Low */
+        uint32_t enb                     : 1;       /**< Bar Enable
+                                                         o 0: BAR 0 is disabled
+                                                         o 1: BAR 0 is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+        uint32_t enb                     : 1;
+        uint32_t lmask                   : 31;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg004_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg004_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg004_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg004_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg004_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg005
+ *
+ * PCIE_CFG005 = Sixth 32-bits of PCIE type 0 config space (Base Address Register 0 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg005_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ubab                    : 32;      /**< Contains the upper 32 bits of the BAR 0 base address. */
+#else
+        uint32_t ubab                    : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg005_s          cn52xx;
+    struct cvmx_pcieep_cfg005_s          cn52xxp1;
+    struct cvmx_pcieep_cfg005_s          cn56xx;
+    struct cvmx_pcieep_cfg005_s          cn56xxp1;
+} cvmx_pcieep_cfg005_t;
+
+
+/**
+ * cvmx_pcieep_cfg005_mask
+ *
+ * PCIE_CFG005_MASK = (BAR Mask 0 - High)
+ * The BAR 0 Mask register is invisible to host software and not readable from the application.
+ * The BAR 0 Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg005_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umask                   : 32;      /**< Bar Mask High */
+#else
+        uint32_t umask                   : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg005_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg005_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg005_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg005_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg005_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg006
+ *
+ * PCIE_CFG006 = Seventh 32-bits of PCIE type 0 config space (Base Address Register 1 - Low)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg006_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lbab                    : 6;       /**< Lower bits of the BAR 1 base address */
+        uint32_t reserved_4_25           : 22;
+        uint32_t pf                      : 1;       /**< Prefetchable
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t typ                     : 2;       /**< BAR type
+                                                            o 00 = 32-bit BAR
+                                                            o 10 = 64-bit BAR
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t mspc                    : 1;       /**< Memory Space Indicator
+                                                            o 0 = BAR 0 is a memory BAR
+                                                            o 1 = BAR 0 is an I/O BAR
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t mspc                    : 1;
+        uint32_t typ                     : 2;
+        uint32_t pf                      : 1;
+        uint32_t reserved_4_25           : 22;
+        uint32_t lbab                    : 6;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg006_s          cn52xx;
+    struct cvmx_pcieep_cfg006_s          cn52xxp1;
+    struct cvmx_pcieep_cfg006_s          cn56xx;
+    struct cvmx_pcieep_cfg006_s          cn56xxp1;
+} cvmx_pcieep_cfg006_t;
+
+
+/**
+ * cvmx_pcieep_cfg006_mask
+ *
+ * PCIE_CFG006_MASK (BAR Mask 1 - Low)
+ * The BAR 1 Mask register is invisible to host software and not readable from the application.
+ * The BAR 1 Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg006_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lmask                   : 31;      /**< Bar Mask Low */
+        uint32_t enb                     : 1;       /**< Bar Enable
+                                                         o 0: BAR 1 is disabled
+                                                         o 1: BAR 1 is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+        uint32_t enb                     : 1;
+        uint32_t lmask                   : 31;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg006_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg006_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg006_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg006_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg006_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg007
+ *
+ * PCIE_CFG007 = Eighth 32-bits of PCIE type 0 config space (Base Address Register 1 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg007_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ubab                    : 32;      /**< Contains the upper 32 bits of the BAR 1 base address. */
+#else
+        uint32_t ubab                    : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg007_s          cn52xx;
+    struct cvmx_pcieep_cfg007_s          cn52xxp1;
+    struct cvmx_pcieep_cfg007_s          cn56xx;
+    struct cvmx_pcieep_cfg007_s          cn56xxp1;
+} cvmx_pcieep_cfg007_t;
+
+
+/**
+ * cvmx_pcieep_cfg007_mask
+ *
+ * PCIE_CFG007_MASK (BAR Mask 1 - High)
+ * The BAR 1 Mask register is invisible to host software and not readable from the application.
+ * The BAR 1 Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg007_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umask                   : 32;      /**< Bar Mask High */
+#else
+        uint32_t umask                   : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg007_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg007_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg007_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg007_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg007_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg008
+ *
+ * PCIE_CFG008 = Ninth 32-bits of PCIE type 0 config space (Base Address Register 2 - Low)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg008_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_4_31           : 28;
+        uint32_t pf                      : 1;       /**< Prefetchable
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t typ                     : 2;       /**< BAR type
+                                                            o 00 = 32-bit BAR
+                                                            o 10 = 64-bit BAR
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t mspc                    : 1;       /**< Memory Space Indicator
+                                                            o 0 = BAR 0 is a memory BAR
+                                                            o 1 = BAR 0 is an I/O BAR
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t mspc                    : 1;
+        uint32_t typ                     : 2;
+        uint32_t pf                      : 1;
+        uint32_t reserved_4_31           : 28;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg008_s          cn52xx;
+    struct cvmx_pcieep_cfg008_s          cn52xxp1;
+    struct cvmx_pcieep_cfg008_s          cn56xx;
+    struct cvmx_pcieep_cfg008_s          cn56xxp1;
+} cvmx_pcieep_cfg008_t;
+
+
+/**
+ * cvmx_pcieep_cfg008_mask
+ *
+ * PCIE_CFG008_MASK (BAR Mask 2 - Low)
+ * The BAR 2 Mask register is invisible to host software and not readable from the application.
+ * The BAR 2 Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg008_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lmask                   : 31;      /**< Bar Mask Low */
+        uint32_t enb                     : 1;       /**< Bar Enable
+                                                         o 0: BAR 2 is disabled
+                                                         o 1: BAR 2 is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+        uint32_t enb                     : 1;
+        uint32_t lmask                   : 31;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg008_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg008_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg008_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg008_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg008_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg009
+ *
+ * PCIE_CFG009 = Tenth 32-bits of PCIE type 0 config space (Base Address Register 2 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg009_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ubab                    : 25;      /**< Contains the upper 32 bits of the BAR 2 base address. */
+        uint32_t reserved_0_6            : 7;
+#else
+        uint32_t reserved_0_6            : 7;
+        uint32_t ubab                    : 25;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg009_s          cn52xx;
+    struct cvmx_pcieep_cfg009_s          cn52xxp1;
+    struct cvmx_pcieep_cfg009_s          cn56xx;
+    struct cvmx_pcieep_cfg009_s          cn56xxp1;
+} cvmx_pcieep_cfg009_t;
+
+
+/**
+ * cvmx_pcieep_cfg009_mask
+ *
+ * PCIE_CFG009_MASK (BAR Mask 2 - High)
+ * The BAR 2 Mask register is invisible to host software and not readable from the application.
+ * The BAR 2 Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg009_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umask                   : 32;      /**< Bar Mask High */
+#else
+        uint32_t umask                   : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg009_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg009_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg009_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg009_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg009_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg010
+ *
+ * PCIE_CFG010 = Eleventh 32-bits of PCIE type 0 config space (CardBus CIS Pointer Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg010_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t cisp                    : 32;      /**< CardBus CIS Pointer
+                                                         Optional, writable through the DBI. */
+#else
+        uint32_t cisp                    : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg010_s          cn52xx;
+    struct cvmx_pcieep_cfg010_s          cn52xxp1;
+    struct cvmx_pcieep_cfg010_s          cn56xx;
+    struct cvmx_pcieep_cfg010_s          cn56xxp1;
+} cvmx_pcieep_cfg010_t;
+
+
+/**
+ * cvmx_pcieep_cfg011
+ *
+ * PCIE_CFG011 = Twelfth 32-bits of PCIE type 0 config space (Subsystem ID and Subsystem Vendor ID Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg011_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ssid                    : 16;      /**< Subsystem ID
+                                                         Assigned by PCI-SIG, writable through the DBI.                                                                                                               However, the application must not change this field. */
+        uint32_t ssvid                   : 16;      /**< Subsystem Vendor ID
+                                                         Assigned by PCI-SIG, writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t ssvid                   : 16;
+        uint32_t ssid                    : 16;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg011_s          cn52xx;
+    struct cvmx_pcieep_cfg011_s          cn52xxp1;
+    struct cvmx_pcieep_cfg011_s          cn56xx;
+    struct cvmx_pcieep_cfg011_s          cn56xxp1;
+} cvmx_pcieep_cfg011_t;
+
+
+/**
+ * cvmx_pcieep_cfg012
+ *
+ * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 0 config space (Expansion ROM Base Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg012_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t eraddr                  : 16;      /**< Expansion ROM Address */
+        uint32_t reserved_1_15           : 15;
+        uint32_t er_en                   : 1;       /**< Expansion ROM Enable */
+#else
+        uint32_t er_en                   : 1;
+        uint32_t reserved_1_15           : 15;
+        uint32_t eraddr                  : 16;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg012_s          cn52xx;
+    struct cvmx_pcieep_cfg012_s          cn52xxp1;
+    struct cvmx_pcieep_cfg012_s          cn56xx;
+    struct cvmx_pcieep_cfg012_s          cn56xxp1;
+} cvmx_pcieep_cfg012_t;
+
+
+/**
+ * cvmx_pcieep_cfg012_mask
+ *
+ * PCIE_CFG012_MASK (Exapansion ROM BAR Mask)
+ * The ROM Mask register is invisible to host software and not readable from the application.
+ * The ROM Mask register is only writable through the DBI.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg012_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t mask                    : 31;      /**< Bar Mask Low */
+        uint32_t enb                     : 1;       /**< Bar Enable
+                                                         o 0: BAR ROM is disabled
+                                                         o 1: BAR ROM is enabled
+                                                         Bit 0 is interpreted as BAR Enable when writing to the BAR Mask
+                                                         register rather than as a mask bit because bit 0 of a BAR is
+                                                         always masked from writing by host software. Bit 0 must be
+                                                         written prior to writing the other mask bits. */
+#else
+        uint32_t enb                     : 1;
+        uint32_t mask                    : 31;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg012_mask_s     cn52xx;
+    struct cvmx_pcieep_cfg012_mask_s     cn52xxp1;
+    struct cvmx_pcieep_cfg012_mask_s     cn56xx;
+    struct cvmx_pcieep_cfg012_mask_s     cn56xxp1;
+} cvmx_pcieep_cfg012_mask_t;
+
+
+/**
+ * cvmx_pcieep_cfg013
+ *
+ * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 0 config space (Capability Pointer Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg013_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_8_31           : 24;
+        uint32_t cp                      : 8;       /**< First Capability Pointer.
+                                                         Points to Power Management Capability structure by
+                                                         default, writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t cp                      : 8;
+        uint32_t reserved_8_31           : 24;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg013_s          cn52xx;
+    struct cvmx_pcieep_cfg013_s          cn52xxp1;
+    struct cvmx_pcieep_cfg013_s          cn56xx;
+    struct cvmx_pcieep_cfg013_s          cn56xxp1;
+} cvmx_pcieep_cfg013_t;
+
+
+/**
+ * cvmx_pcieep_cfg015
+ *
+ * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 0 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg015_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ml                      : 8;       /**< Maximum Latency     (Hardwired to 0) */
+        uint32_t mg                      : 8;       /**< Minimum Grant       (Hardwired to 0) */
+        uint32_t inta                    : 8;       /**< Interrupt Pin
+                                                         Identifies the legacy interrupt Message that the device
+                                                         (or device function) uses.
+                                                         The Interrupt Pin register is writable through the DBI.
+                                                         In a single-function configuration, only INTA is used.
+                                                         Therefore, the application must not change this field. */
+        uint32_t il                      : 8;       /**< Interrupt Line */
+#else
+        uint32_t il                      : 8;
+        uint32_t inta                    : 8;
+        uint32_t mg                      : 8;
+        uint32_t ml                      : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg015_s          cn52xx;
+    struct cvmx_pcieep_cfg015_s          cn52xxp1;
+    struct cvmx_pcieep_cfg015_s          cn56xx;
+    struct cvmx_pcieep_cfg015_s          cn56xxp1;
+} cvmx_pcieep_cfg015_t;
+
+
+/**
+ * cvmx_pcieep_cfg016
+ *
+ * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 0 config space
+ * (Power Management Capability ID/
+ * Power Management Next Item Pointer/
+ * Power Management Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg016_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pmes                    : 5;       /**< PME_Support
+                                                         o Bit 11: If set, PME Messages can be generated from D0
+                                                         o Bit 12: If set, PME Messages can be generated from D1
+                                                         o Bit 13: If set, PME Messages can be generated from D2
+                                                         o Bit 14: If set, PME Messages can be generated from D3hot
+                                                         o Bit 15: If set, PME Messages can be generated from D3cold
+                                                         The PME_Support field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t d2s                     : 1;       /**< D2 Support, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t d1s                     : 1;       /**< D1 Support, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t auxc                    : 3;       /**< AUX Current, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t dsi                     : 1;       /**< Device Specific Initialization (DSI), writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t pme_clock               : 1;       /**< PME Clock, hardwired to 0 */
+        uint32_t pmsv                    : 3;       /**< Power Management Specification Version, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer
+                                                         Points to the MSI capabilities by default, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t pmcid                   : 8;       /**< Power Management Capability ID */
+#else
+        uint32_t pmcid                   : 8;
+        uint32_t ncp                     : 8;
+        uint32_t pmsv                    : 3;
+        uint32_t pme_clock               : 1;
+        uint32_t reserved_20_20          : 1;
+        uint32_t dsi                     : 1;
+        uint32_t auxc                    : 3;
+        uint32_t d1s                     : 1;
+        uint32_t d2s                     : 1;
+        uint32_t pmes                    : 5;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg016_s          cn52xx;
+    struct cvmx_pcieep_cfg016_s          cn52xxp1;
+    struct cvmx_pcieep_cfg016_s          cn56xx;
+    struct cvmx_pcieep_cfg016_s          cn56xxp1;
+} cvmx_pcieep_cfg016_t;
+
+
+/**
+ * cvmx_pcieep_cfg017
+ *
+ * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 0 config space (Power Management Control and Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg017_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pmdia                   : 8;       /**< Data register for additional information (not supported) */
+        uint32_t bpccee                  : 1;       /**< Bus Power/Clock Control Enable, hardwired to 0 */
+        uint32_t bd3h                    : 1;       /**< B2/B3 Support, hardwired to 0 */
+        uint32_t reserved_16_21          : 6;
+        uint32_t pmess                   : 1;       /**< PME Status
+                                                         Indicates if a previously enabled PME event occurred or not. */
+        uint32_t pmedsia                 : 2;       /**< Data Scale (not supported) */
+        uint32_t pmds                    : 4;       /**< Data Select (not supported) */
+        uint32_t pmeens                  : 1;       /**< PME Enable
+                                                         A value of 1 indicates that the device is enabled to
+                                                         generate PME. */
+        uint32_t reserved_4_7            : 4;
+        uint32_t nsr                     : 1;       /**< No Soft Reset, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_2_2            : 1;
+        uint32_t ps                      : 2;       /**< Power State
+                                                         Controls the device power state:
+                                                           o 00b: D0
+                                                           o 01b: D1
+                                                           o 10b: D2
+                                                           o 11b: D3
+                                                         The written value is ignored if the specific state is
+                                                         not supported. */
+#else
+        uint32_t ps                      : 2;
+        uint32_t reserved_2_2            : 1;
+        uint32_t nsr                     : 1;
+        uint32_t reserved_4_7            : 4;
+        uint32_t pmeens                  : 1;
+        uint32_t pmds                    : 4;
+        uint32_t pmedsia                 : 2;
+        uint32_t pmess                   : 1;
+        uint32_t reserved_16_21          : 6;
+        uint32_t bd3h                    : 1;
+        uint32_t bpccee                  : 1;
+        uint32_t pmdia                   : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg017_s          cn52xx;
+    struct cvmx_pcieep_cfg017_s          cn52xxp1;
+    struct cvmx_pcieep_cfg017_s          cn56xx;
+    struct cvmx_pcieep_cfg017_s          cn56xxp1;
+} cvmx_pcieep_cfg017_t;
+
+
+/**
+ * cvmx_pcieep_cfg020
+ *
+ * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 0 config space
+ * (MSI Capability ID/
+ *  MSI Next Item Pointer/
+ *  MSI Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg020_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t m64                     : 1;       /**< 64-bit Address Capable, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t mme                     : 3;       /**< Multiple Message Enabled
+                                                         Indicates that multiple Message mode is enabled by system
+                                                         software. The number of Messages enabled must be less than
+                                                         or equal to the Multiple Message Capable value. */
+        uint32_t mmc                     : 3;       /**< Multiple Message Capable, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t msien                   : 1;       /**< MSI Enabled
+                                                         When set, INTx must be disabled. */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer
+                                                         Points to PCI Express Capabilities by default,
+                                                         writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t msicid                  : 8;       /**< MSI Capability ID */
+#else
+        uint32_t msicid                  : 8;
+        uint32_t ncp                     : 8;
+        uint32_t msien                   : 1;
+        uint32_t mmc                     : 3;
+        uint32_t mme                     : 3;
+        uint32_t m64                     : 1;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg020_s          cn52xx;
+    struct cvmx_pcieep_cfg020_s          cn52xxp1;
+    struct cvmx_pcieep_cfg020_s          cn56xx;
+    struct cvmx_pcieep_cfg020_s          cn56xxp1;
+} cvmx_pcieep_cfg020_t;
+
+
+/**
+ * cvmx_pcieep_cfg021
+ *
+ * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 0 config space (MSI Lower 32 Bits Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg021_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lmsi                    : 30;      /**< Lower 32-bit Address */
+        uint32_t reserved_0_1            : 2;
+#else
+        uint32_t reserved_0_1            : 2;
+        uint32_t lmsi                    : 30;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg021_s          cn52xx;
+    struct cvmx_pcieep_cfg021_s          cn52xxp1;
+    struct cvmx_pcieep_cfg021_s          cn56xx;
+    struct cvmx_pcieep_cfg021_s          cn56xxp1;
+} cvmx_pcieep_cfg021_t;
+
+
+/**
+ * cvmx_pcieep_cfg022
+ *
+ * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 0 config space (MSI Upper 32 bits Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg022_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umsi                    : 32;      /**< Upper 32-bit Address */
+#else
+        uint32_t umsi                    : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg022_s          cn52xx;
+    struct cvmx_pcieep_cfg022_s          cn52xxp1;
+    struct cvmx_pcieep_cfg022_s          cn56xx;
+    struct cvmx_pcieep_cfg022_s          cn56xxp1;
+} cvmx_pcieep_cfg022_t;
+
+
+/**
+ * cvmx_pcieep_cfg023
+ *
+ * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 0 config space (MSI Data Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg023_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t msimd                   : 16;      /**< MSI Data
+                                                         Pattern assigned by system software, bits [4:0] are Or-ed with
+                                                         MSI_VECTOR to generate 32 MSI Messages per function. */
+#else
+        uint32_t msimd                   : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg023_s          cn52xx;
+    struct cvmx_pcieep_cfg023_s          cn52xxp1;
+    struct cvmx_pcieep_cfg023_s          cn56xx;
+    struct cvmx_pcieep_cfg023_s          cn56xxp1;
+} cvmx_pcieep_cfg023_t;
+
+
+/**
+ * cvmx_pcieep_cfg028
+ *
+ * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 0 config space
+ * (PCI Express Capabilities List Register/
+ *  PCI Express Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg028_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t imn                     : 5;       /**< Interrupt Message Number
+                                                         Updated by hardware, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t si                      : 1;       /**< Slot Implemented
+                                                         This bit is writable through the DBI. However, it must be 0 for
+                                                         an Endpoint device. Therefore, the application must not write a
+                                                         1 to this bit. */
+        uint32_t dpt                     : 4;       /**< Device Port Type */
+        uint32_t pciecv                  : 4;       /**< PCI Express Capability Version */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer
+                                                         Writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t pcieid                  : 8;       /**< PCIE Capability ID */
+#else
+        uint32_t pcieid                  : 8;
+        uint32_t ncp                     : 8;
+        uint32_t pciecv                  : 4;
+        uint32_t dpt                     : 4;
+        uint32_t si                      : 1;
+        uint32_t imn                     : 5;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg028_s          cn52xx;
+    struct cvmx_pcieep_cfg028_s          cn52xxp1;
+    struct cvmx_pcieep_cfg028_s          cn56xx;
+    struct cvmx_pcieep_cfg028_s          cn56xxp1;
+} cvmx_pcieep_cfg028_t;
+
+
+/**
+ * cvmx_pcieep_cfg029
+ *
+ * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 0 config space (Device Capabilities Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg029_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_28_31          : 4;
+        uint32_t cspls                   : 2;       /**< Captured Slot Power Limit Scale
+                                                         From Message from RC, upstream port only. */
+        uint32_t csplv                   : 8;       /**< Captured Slot Power Limit Value
+                                                         From Message from RC, upstream port only. */
+        uint32_t reserved_16_17          : 2;
+        uint32_t rber                    : 1;       /**< Role-Based Error Reporting, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_12_14          : 3;
+        uint32_t el1al                   : 3;       /**< Endpoint L1 Acceptable Latency, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t el0al                   : 3;       /**< Endpoint L0s Acceptable Latency, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t etfs                    : 1;       /**< Extended Tag Field Supported
+                                                         This bit is writable through the DBI. However, the application
+                                                         must not write a 1 to this bit. */
+        uint32_t pfs                     : 2;       /**< Phantom Function Supported
+                                                         This field is writable through the DBI. However, Phantom
+                                                         Function is not supported. Therefore, the application must not
+                                                         write any value other than 0x0 to this field. */
+        uint32_t mpss                    : 3;       /**< Max_Payload_Size Supported, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t mpss                    : 3;
+        uint32_t pfs                     : 2;
+        uint32_t etfs                    : 1;
+        uint32_t el0al                   : 3;
+        uint32_t el1al                   : 3;
+        uint32_t reserved_12_14          : 3;
+        uint32_t rber                    : 1;
+        uint32_t reserved_16_17          : 2;
+        uint32_t csplv                   : 8;
+        uint32_t cspls                   : 2;
+        uint32_t reserved_28_31          : 4;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg029_s          cn52xx;
+    struct cvmx_pcieep_cfg029_s          cn52xxp1;
+    struct cvmx_pcieep_cfg029_s          cn56xx;
+    struct cvmx_pcieep_cfg029_s          cn56xxp1;
+} cvmx_pcieep_cfg029_t;
+
+
+/**
+ * cvmx_pcieep_cfg030
+ *
+ * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 0 config space
+ * (Device Control Register/Device Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg030_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_22_31          : 10;
+        uint32_t tp                      : 1;       /**< Transaction Pending
+                                                         Set to 1 when Non-Posted Requests are not yet completed
+                                                         and clear when they are completed. */
+        uint32_t ap_d                    : 1;       /**< Aux Power Detected
+                                                         Set to 1 if Aux power detected. */
+        uint32_t ur_d                    : 1;       /**< Unsupported Request Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         UR_D occurs when we receive something we don't support.
+                                                         Unsupported requests are Nonfatal errors, so UR_D should
+                                                         cause NFE_D.  Receiving a  vendor defined message should
+                                                         cause an unsupported request. */
+        uint32_t fe_d                    : 1;       /**< Fatal Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
+                                                         has a severity set to Fatal.  Malformed TLP's generally fit
+                                                         into this category. */
+        uint32_t nfe_d                   : 1;       /**< Non-Fatal Error detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
+                                                         that has a severity set to Nonfatal and does NOT meet Advisory
+                                                         Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which
+                                                         most poisoned TLP's should be. */
+        uint32_t ce_d                    : 1;       /**< Correctable Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
+                                                         for example a Replay Timer Timeout.  Also, it can be set if
+                                                         we get any of the errors in PCIE_CFG066 that has a severity
+                                                         set to Nonfatal and meets the Advisory Nonfatal criteria
+                                                         (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors
+                                                         should be. */
+        uint32_t reserved_15_15          : 1;
+        uint32_t mrrs                    : 3;       /**< Max Read Request Size
+                                                          0 = 128B
+                                                          1 = 256B
+                                                          2 = 512B
+                                                          3 = 1024B
+                                                          4 = 2048B
+                                                          5 = 4096B
+                                                         Note: NPEI_CTL_STATUS2[MRRS] also must be set properly.
+                                                         NPEI_CTL_STATUS2[MRRS] must not exceed the
+                                                         desired max read request size. */
+        uint32_t ns_en                   : 1;       /**< Enable No Snoop */
+        uint32_t ap_en                   : 1;       /**< AUX Power PM Enable */
+        uint32_t pf_en                   : 1;       /**< Phantom Function Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         phantom functions. */
+        uint32_t etf_en                  : 1;       /**< Extended Tag Field Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         extended tags. */
+        uint32_t mps                     : 3;       /**< Max Payload Size
+                                                          Legal values:
+                                                           0  = 128B
+                                                           1  = 256B
+                                                          Larger sizes not supported by OCTEON.
+                                                         Note: NPEI_CTL_STATUS2[MPS] must be set to the same
+                                                               value for proper functionality. */
+        uint32_t ro_en                   : 1;       /**< Enable Relaxed Ordering */
+        uint32_t ur_en                   : 1;       /**< Unsupported Request Reporting Enable */
+        uint32_t fe_en                   : 1;       /**< Fatal Error Reporting Enable */
+        uint32_t nfe_en                  : 1;       /**< Non-Fatal Error Reporting Enable */
+        uint32_t ce_en                   : 1;       /**< Correctable Error Reporting Enable */
+#else
+        uint32_t ce_en                   : 1;
+        uint32_t nfe_en                  : 1;
+        uint32_t fe_en                   : 1;
+        uint32_t ur_en                   : 1;
+        uint32_t ro_en                   : 1;
+        uint32_t mps                     : 3;
+        uint32_t etf_en                  : 1;
+        uint32_t pf_en                   : 1;
+        uint32_t ap_en                   : 1;
+        uint32_t ns_en                   : 1;
+        uint32_t mrrs                    : 3;
+        uint32_t reserved_15_15          : 1;
+        uint32_t ce_d                    : 1;
+        uint32_t nfe_d                   : 1;
+        uint32_t fe_d                    : 1;
+        uint32_t ur_d                    : 1;
+        uint32_t ap_d                    : 1;
+        uint32_t tp                      : 1;
+        uint32_t reserved_22_31          : 10;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg030_s          cn52xx;
+    struct cvmx_pcieep_cfg030_s          cn52xxp1;
+    struct cvmx_pcieep_cfg030_s          cn56xx;
+    struct cvmx_pcieep_cfg030_s          cn56xxp1;
+} cvmx_pcieep_cfg030_t;
+
+
+/**
+ * cvmx_pcieep_cfg031
+ *
+ * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 0 config space
+ * (Link Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg031_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pnum                    : 8;       /**< Port Number, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_22_23          : 2;
+        uint32_t lbnc                    : 1;       /**< Link Bandwith Notification Capability */
+        uint32_t dllarc                  : 1;       /**< Data Link Layer Active Reporting Capable */
+        uint32_t sderc                   : 1;       /**< Surprise Down Error Reporting Capable
+                                                         Not supported, hardwired to 0x0. */
+        uint32_t cpm                     : 1;       /**< Clock Power Management
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t l1el                    : 3;       /**< L1 Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t l0el                    : 3;       /**< L0s Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t aslpms                  : 2;       /**< Active State Link PM Support
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t mlw                     : 6;       /**< Maximum Link Width
+                                                         The default value is the value you specify during hardware
+                                                         configuration (x1, x4, x8, or x16), writable through the DBI. */
+        uint32_t mls                     : 4;       /**< Maximum Link Speed
+                                                         Default value is 0x1 for 2.5 Gbps Link.
+                                                         This field is writable through the DBI. However, 0x1 is the
+                                                         only supported value. Therefore, the application must not write
+                                                         any value other than 0x1 to this field. */
+#else
+        uint32_t mls                     : 4;
+        uint32_t mlw                     : 6;
+        uint32_t aslpms                  : 2;
+        uint32_t l0el                    : 3;
+        uint32_t l1el                    : 3;
+        uint32_t cpm                     : 1;
+        uint32_t sderc                   : 1;
+        uint32_t dllarc                  : 1;
+        uint32_t lbnc                    : 1;
+        uint32_t reserved_22_23          : 2;
+        uint32_t pnum                    : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg031_s          cn52xx;
+    struct cvmx_pcieep_cfg031_s          cn52xxp1;
+    struct cvmx_pcieep_cfg031_s          cn56xx;
+    struct cvmx_pcieep_cfg031_s          cn56xxp1;
+} cvmx_pcieep_cfg031_t;
+
+
+/**
+ * cvmx_pcieep_cfg032
+ *
+ * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 0 config space
+ * (Link Control Register/Link Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg032_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t dlla                    : 1;       /**< Data Link Layer Active
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+        uint32_t scc                     : 1;       /**< Slot Clock Configuration
+                                                         Indicates that the component uses the same physical reference
+                                                         clock that the platform provides on the connector.
+                                                         Writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t lt                      : 1;       /**< Link Training
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+        uint32_t reserved_26_26          : 1;
+        uint32_t nlw                     : 6;       /**< Negotiated Link Width
+                                                         Set automatically by hardware after Link initialization. */
+        uint32_t ls                      : 4;       /**< Link Speed
+                                                         The negotiated Link speed: 2.5 Gbps */
+        uint32_t reserved_10_15          : 6;
+        uint32_t hawd                    : 1;       /**< Hardware Autonomous Width Disable
+                                                         (Not Supported) */
+        uint32_t ecpm                    : 1;       /**< Enable Clock Power Management
+                                                         Hardwired to 0 if Clock Power Management is disabled in
+                                                         the Link Capabilities register. */
+        uint32_t es                      : 1;       /**< Extended Synch */
+        uint32_t ccc                     : 1;       /**< Common Clock Configuration */
+        uint32_t rl                      : 1;       /**< Retrain Link
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+        uint32_t ld                      : 1;       /**< Link Disable
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+        uint32_t rcb                     : 1;       /**< Read Completion Boundary (RCB) */
+        uint32_t reserved_2_2            : 1;
+        uint32_t aslpc                   : 2;       /**< Active State Link PM Control */
+#else
+        uint32_t aslpc                   : 2;
+        uint32_t reserved_2_2            : 1;
+        uint32_t rcb                     : 1;
+        uint32_t ld                      : 1;
+        uint32_t rl                      : 1;
+        uint32_t ccc                     : 1;
+        uint32_t es                      : 1;
+        uint32_t ecpm                    : 1;
+        uint32_t hawd                    : 1;
+        uint32_t reserved_10_15          : 6;
+        uint32_t ls                      : 4;
+        uint32_t nlw                     : 6;
+        uint32_t reserved_26_26          : 1;
+        uint32_t lt                      : 1;
+        uint32_t scc                     : 1;
+        uint32_t dlla                    : 1;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg032_s          cn52xx;
+    struct cvmx_pcieep_cfg032_s          cn52xxp1;
+    struct cvmx_pcieep_cfg032_s          cn56xx;
+    struct cvmx_pcieep_cfg032_s          cn56xxp1;
+} cvmx_pcieep_cfg032_t;
+
+
+/**
+ * cvmx_pcieep_cfg033
+ *
+ * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 0 config space
+ * (Slot Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg033_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ps_num                  : 13;      /**< Physical Slot Number, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t nccs                    : 1;       /**< No Command Complete Support, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t emip                    : 1;       /**< Electromechanical Interlock Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t sp_ls                   : 2;       /**< Slot Power Limit Scale, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t sp_lv                   : 8;       /**< Slot Power Limit Value, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t hp_c                    : 1;       /**< Hot-Plug Capable, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t hp_s                    : 1;       /**< Hot-Plug Surprise, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t pip                     : 1;       /**< Power Indicator Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t aip                     : 1;       /**< Attention Indicator Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t mrlsp                   : 1;       /**< MRL Sensor Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t pcp                     : 1;       /**< Power Controller Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t abp                     : 1;       /**< Attention Button Present, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t abp                     : 1;
+        uint32_t pcp                     : 1;
+        uint32_t mrlsp                   : 1;
+        uint32_t aip                     : 1;
+        uint32_t pip                     : 1;
+        uint32_t hp_s                    : 1;
+        uint32_t hp_c                    : 1;
+        uint32_t sp_lv                   : 8;
+        uint32_t sp_ls                   : 2;
+        uint32_t emip                    : 1;
+        uint32_t nccs                    : 1;
+        uint32_t ps_num                  : 13;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg033_s          cn52xx;
+    struct cvmx_pcieep_cfg033_s          cn52xxp1;
+    struct cvmx_pcieep_cfg033_s          cn56xx;
+    struct cvmx_pcieep_cfg033_s          cn56xxp1;
+} cvmx_pcieep_cfg033_t;
+
+
+/**
+ * cvmx_pcieep_cfg034
+ *
+ * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 0 config space
+ * (Slot Control Register/Slot Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg034_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_25_31          : 7;
+        uint32_t dlls_c                  : 1;       /**< Data Link Layer State Changed
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+        uint32_t emis                    : 1;       /**< Electromechanical Interlock Status */
+        uint32_t pds                     : 1;       /**< Presence Detect State */
+        uint32_t mrlss                   : 1;       /**< MRL Sensor State */
+        uint32_t ccint_d                 : 1;       /**< Command Completed */
+        uint32_t pd_c                    : 1;       /**< Presence Detect Changed */
+        uint32_t mrls_c                  : 1;       /**< MRL Sensor Changed */
+        uint32_t pf_d                    : 1;       /**< Power Fault Detected */
+        uint32_t abp_d                   : 1;       /**< Attention Button Pressed */
+        uint32_t reserved_13_15          : 3;
+        uint32_t dlls_en                 : 1;       /**< Data Link Layer State Changed Enable
+                                                         Not applicable for an upstream Port or Endpoint device,
+                                                         hardwired to 0. */
+        uint32_t emic                    : 1;       /**< Electromechanical Interlock Control */
+        uint32_t pcc                     : 1;       /**< Power Controller Control */
+        uint32_t pic                     : 2;       /**< Power Indicator Control */
+        uint32_t aic                     : 2;       /**< Attention Indicator Control */
+        uint32_t hpint_en                : 1;       /**< Hot-Plug Interrupt Enable */
+        uint32_t ccint_en                : 1;       /**< Command Completed Interrupt Enable */
+        uint32_t pd_en                   : 1;       /**< Presence Detect Changed Enable */
+        uint32_t mrls_en                 : 1;       /**< MRL Sensor Changed Enable */
+        uint32_t pf_en                   : 1;       /**< Power Fault Detected Enable */
+        uint32_t abp_en                  : 1;       /**< Attention Button Pressed Enable */
+#else
+        uint32_t abp_en                  : 1;
+        uint32_t pf_en                   : 1;
+        uint32_t mrls_en                 : 1;
+        uint32_t pd_en                   : 1;
+        uint32_t ccint_en                : 1;
+        uint32_t hpint_en                : 1;
+        uint32_t aic                     : 2;
+        uint32_t pic                     : 2;
+        uint32_t pcc                     : 1;
+        uint32_t emic                    : 1;
+        uint32_t dlls_en                 : 1;
+        uint32_t reserved_13_15          : 3;
+        uint32_t abp_d                   : 1;
+        uint32_t pf_d                    : 1;
+        uint32_t mrls_c                  : 1;
+        uint32_t pd_c                    : 1;
+        uint32_t ccint_d                 : 1;
+        uint32_t mrlss                   : 1;
+        uint32_t pds                     : 1;
+        uint32_t emis                    : 1;
+        uint32_t dlls_c                  : 1;
+        uint32_t reserved_25_31          : 7;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg034_s          cn52xx;
+    struct cvmx_pcieep_cfg034_s          cn52xxp1;
+    struct cvmx_pcieep_cfg034_s          cn56xx;
+    struct cvmx_pcieep_cfg034_s          cn56xxp1;
+} cvmx_pcieep_cfg034_t;
+
+
+/**
+ * cvmx_pcieep_cfg037
+ *
+ * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 0 config space
+ * (Device Capabilities 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg037_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t ctds                    : 1;       /**< Completion Timeout Disable Supported */
+        uint32_t ctrs                    : 4;       /**< Completion Timeout Ranges Supported
+                                                         Value of 0 indicates that Completion Timeout Programming
+                                                         is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+        uint32_t ctrs                    : 4;
+        uint32_t ctds                    : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg037_s          cn52xx;
+    struct cvmx_pcieep_cfg037_s          cn52xxp1;
+    struct cvmx_pcieep_cfg037_s          cn56xx;
+    struct cvmx_pcieep_cfg037_s          cn56xxp1;
+} cvmx_pcieep_cfg037_t;
+
+
+/**
+ * cvmx_pcieep_cfg038
+ *
+ * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 0 config space
+ * (Device Control 2 Register/Device Status 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg038_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t ctd                     : 1;       /**< Completion Timeout Disable */
+        uint32_t ctv                     : 4;       /**< Completion Timeout Value
+                                                         Completion Timeout Programming is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+        uint32_t ctv                     : 4;
+        uint32_t ctd                     : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg038_s          cn52xx;
+    struct cvmx_pcieep_cfg038_s          cn52xxp1;
+    struct cvmx_pcieep_cfg038_s          cn56xx;
+    struct cvmx_pcieep_cfg038_s          cn56xxp1;
+} cvmx_pcieep_cfg038_t;
+
+
+/**
+ * cvmx_pcieep_cfg039
+ *
+ * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 0 config space
+ * (Link Capabilities 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg039_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg039_s          cn52xx;
+    struct cvmx_pcieep_cfg039_s          cn52xxp1;
+    struct cvmx_pcieep_cfg039_s          cn56xx;
+    struct cvmx_pcieep_cfg039_s          cn56xxp1;
+} cvmx_pcieep_cfg039_t;
+
+
+/**
+ * cvmx_pcieep_cfg040
+ *
+ * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 0 config space
+ * (Link Control 2 Register/Link Status 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg040_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg040_s          cn52xx;
+    struct cvmx_pcieep_cfg040_s          cn52xxp1;
+    struct cvmx_pcieep_cfg040_s          cn56xx;
+    struct cvmx_pcieep_cfg040_s          cn56xxp1;
+} cvmx_pcieep_cfg040_t;
+
+
+/**
+ * cvmx_pcieep_cfg041
+ *
+ * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 0 config space
+ * (Slot Capabilities 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg041_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg041_s          cn52xx;
+    struct cvmx_pcieep_cfg041_s          cn52xxp1;
+    struct cvmx_pcieep_cfg041_s          cn56xx;
+    struct cvmx_pcieep_cfg041_s          cn56xxp1;
+} cvmx_pcieep_cfg041_t;
+
+
+/**
+ * cvmx_pcieep_cfg042
+ *
+ * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 0 config space
+ * (Slot Control 2 Register/Slot Status 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg042_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg042_s          cn52xx;
+    struct cvmx_pcieep_cfg042_s          cn52xxp1;
+    struct cvmx_pcieep_cfg042_s          cn56xx;
+    struct cvmx_pcieep_cfg042_s          cn56xxp1;
+} cvmx_pcieep_cfg042_t;
+
+
+/**
+ * cvmx_pcieep_cfg064
+ *
+ * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 0 config space
+ * (PCI Express Enhanced Capability Header)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg064_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t nco                     : 12;      /**< Next Capability Offset */
+        uint32_t cv                      : 4;       /**< Capability Version */
+        uint32_t pcieec                  : 16;      /**< PCIE Express Extended Capability */
+#else
+        uint32_t pcieec                  : 16;
+        uint32_t cv                      : 4;
+        uint32_t nco                     : 12;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg064_s          cn52xx;
+    struct cvmx_pcieep_cfg064_s          cn52xxp1;
+    struct cvmx_pcieep_cfg064_s          cn56xx;
+    struct cvmx_pcieep_cfg064_s          cn56xxp1;
+} cvmx_pcieep_cfg064_t;
+
+
+/**
+ * cvmx_pcieep_cfg065
+ *
+ * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 0 config space
+ * (Uncorrectable Error Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg065_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t ures                    : 1;       /**< Unsupported Request Error Status */
+        uint32_t ecrces                  : 1;       /**< ECRC Error Status */
+        uint32_t mtlps                   : 1;       /**< Malformed TLP Status */
+        uint32_t ros                     : 1;       /**< Receiver Overflow Status */
+        uint32_t ucs                     : 1;       /**< Unexpected Completion Status */
+        uint32_t cas                     : 1;       /**< Completer Abort Status */
+        uint32_t cts                     : 1;       /**< Completion Timeout Status */
+        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Status */
+        uint32_t ptlps                   : 1;       /**< Poisoned TLP Status */
+        uint32_t reserved_6_11           : 6;
+        uint32_t sdes                    : 1;       /**< Surprise Down Error Status (not supported) */
+        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Status */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t dlpes                   : 1;
+        uint32_t sdes                    : 1;
+        uint32_t reserved_6_11           : 6;
+        uint32_t ptlps                   : 1;
+        uint32_t fcpes                   : 1;
+        uint32_t cts                     : 1;
+        uint32_t cas                     : 1;
+        uint32_t ucs                     : 1;
+        uint32_t ros                     : 1;
+        uint32_t mtlps                   : 1;
+        uint32_t ecrces                  : 1;
+        uint32_t ures                    : 1;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg065_s          cn52xx;
+    struct cvmx_pcieep_cfg065_s          cn52xxp1;
+    struct cvmx_pcieep_cfg065_s          cn56xx;
+    struct cvmx_pcieep_cfg065_s          cn56xxp1;
+} cvmx_pcieep_cfg065_t;
+
+
+/**
+ * cvmx_pcieep_cfg066
+ *
+ * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 0 config space
+ * (Uncorrectable Error Mask Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg066_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t urem                    : 1;       /**< Unsupported Request Error Mask */
+        uint32_t ecrcem                  : 1;       /**< ECRC Error Mask */
+        uint32_t mtlpm                   : 1;       /**< Malformed TLP Mask */
+        uint32_t rom                     : 1;       /**< Receiver Overflow Mask */
+        uint32_t ucm                     : 1;       /**< Unexpected Completion Mask */
+        uint32_t cam                     : 1;       /**< Completer Abort Mask */
+        uint32_t ctm                     : 1;       /**< Completion Timeout Mask */
+        uint32_t fcpem                   : 1;       /**< Flow Control Protocol Error Mask */
+        uint32_t ptlpm                   : 1;       /**< Poisoned TLP Mask */
+        uint32_t reserved_6_11           : 6;
+        uint32_t sdem                    : 1;       /**< Surprise Down Error Mask (not supported) */
+        uint32_t dlpem                   : 1;       /**< Data Link Protocol Error Mask */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t dlpem                   : 1;
+        uint32_t sdem                    : 1;
+        uint32_t reserved_6_11           : 6;
+        uint32_t ptlpm                   : 1;
+        uint32_t fcpem                   : 1;
+        uint32_t ctm                     : 1;
+        uint32_t cam                     : 1;
+        uint32_t ucm                     : 1;
+        uint32_t rom                     : 1;
+        uint32_t mtlpm                   : 1;
+        uint32_t ecrcem                  : 1;
+        uint32_t urem                    : 1;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg066_s          cn52xx;
+    struct cvmx_pcieep_cfg066_s          cn52xxp1;
+    struct cvmx_pcieep_cfg066_s          cn56xx;
+    struct cvmx_pcieep_cfg066_s          cn56xxp1;
+} cvmx_pcieep_cfg066_t;
+
+
+/**
+ * cvmx_pcieep_cfg067
+ *
+ * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 0 config space
+ * (Uncorrectable Error Severity Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg067_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t ures                    : 1;       /**< Unsupported Request Error Severity */
+        uint32_t ecrces                  : 1;       /**< ECRC Error Severity */
+        uint32_t mtlps                   : 1;       /**< Malformed TLP Severity */
+        uint32_t ros                     : 1;       /**< Receiver Overflow Severity */
+        uint32_t ucs                     : 1;       /**< Unexpected Completion Severity */
+        uint32_t cas                     : 1;       /**< Completer Abort Severity */
+        uint32_t cts                     : 1;       /**< Completion Timeout Severity */
+        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Severity */
+        uint32_t ptlps                   : 1;       /**< Poisoned TLP Severity */
+        uint32_t reserved_6_11           : 6;
+        uint32_t sdes                    : 1;       /**< Surprise Down Error Severity (not supported) */
+        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Severity */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t dlpes                   : 1;
+        uint32_t sdes                    : 1;
+        uint32_t reserved_6_11           : 6;
+        uint32_t ptlps                   : 1;
+        uint32_t fcpes                   : 1;
+        uint32_t cts                     : 1;
+        uint32_t cas                     : 1;
+        uint32_t ucs                     : 1;
+        uint32_t ros                     : 1;
+        uint32_t mtlps                   : 1;
+        uint32_t ecrces                  : 1;
+        uint32_t ures                    : 1;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg067_s          cn52xx;
+    struct cvmx_pcieep_cfg067_s          cn52xxp1;
+    struct cvmx_pcieep_cfg067_s          cn56xx;
+    struct cvmx_pcieep_cfg067_s          cn56xxp1;
+} cvmx_pcieep_cfg067_t;
+
+
+/**
+ * cvmx_pcieep_cfg068
+ *
+ * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 0 config space
+ * (Correctable Error Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg068_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_14_31          : 18;
+        uint32_t anfes                   : 1;       /**< Advisory Non-Fatal Error Status */
+        uint32_t rtts                    : 1;       /**< Reply Timer Timeout Status */
+        uint32_t reserved_9_11           : 3;
+        uint32_t rnrs                    : 1;       /**< REPLAY_NUM Rollover Status */
+        uint32_t bdllps                  : 1;       /**< Bad DLLP Status */
+        uint32_t btlps                   : 1;       /**< Bad TLP Status */
+        uint32_t reserved_1_5            : 5;
+        uint32_t res                     : 1;       /**< Receiver Error Status */
+#else
+        uint32_t res                     : 1;
+        uint32_t reserved_1_5            : 5;
+        uint32_t btlps                   : 1;
+        uint32_t bdllps                  : 1;
+        uint32_t rnrs                    : 1;
+        uint32_t reserved_9_11           : 3;
+        uint32_t rtts                    : 1;
+        uint32_t anfes                   : 1;
+        uint32_t reserved_14_31          : 18;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg068_s          cn52xx;
+    struct cvmx_pcieep_cfg068_s          cn52xxp1;
+    struct cvmx_pcieep_cfg068_s          cn56xx;
+    struct cvmx_pcieep_cfg068_s          cn56xxp1;
+} cvmx_pcieep_cfg068_t;
+
+
+/**
+ * cvmx_pcieep_cfg069
+ *
+ * PCIE_CFG069 = Seventieth 32-bits of PCIE type 0 config space
+ * (Correctable Error Mask Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg069_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_14_31          : 18;
+        uint32_t anfem                   : 1;       /**< Advisory Non-Fatal Error Mask */
+        uint32_t rttm                    : 1;       /**< Reply Timer Timeout Mask */
+        uint32_t reserved_9_11           : 3;
+        uint32_t rnrm                    : 1;       /**< REPLAY_NUM Rollover Mask */
+        uint32_t bdllpm                  : 1;       /**< Bad DLLP Mask */
+        uint32_t btlpm                   : 1;       /**< Bad TLP Mask */
+        uint32_t reserved_1_5            : 5;
+        uint32_t rem                     : 1;       /**< Receiver Error Mask */
+#else
+        uint32_t rem                     : 1;
+        uint32_t reserved_1_5            : 5;
+        uint32_t btlpm                   : 1;
+        uint32_t bdllpm                  : 1;
+        uint32_t rnrm                    : 1;
+        uint32_t reserved_9_11           : 3;
+        uint32_t rttm                    : 1;
+        uint32_t anfem                   : 1;
+        uint32_t reserved_14_31          : 18;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg069_s          cn52xx;
+    struct cvmx_pcieep_cfg069_s          cn52xxp1;
+    struct cvmx_pcieep_cfg069_s          cn56xx;
+    struct cvmx_pcieep_cfg069_s          cn56xxp1;
+} cvmx_pcieep_cfg069_t;
+
+
+/**
+ * cvmx_pcieep_cfg070
+ *
+ * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 0 config space
+ * (Advanced Error Capabilities and Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg070_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_9_31           : 23;
+        uint32_t ce                      : 1;       /**< ECRC Check Enable */
+        uint32_t cc                      : 1;       /**< ECRC Check Capable */
+        uint32_t ge                      : 1;       /**< ECRC Generation Enable */
+        uint32_t gc                      : 1;       /**< ECRC Generation Capability */
+        uint32_t fep                     : 5;       /**< First Error Pointer */
+#else
+        uint32_t fep                     : 5;
+        uint32_t gc                      : 1;
+        uint32_t ge                      : 1;
+        uint32_t cc                      : 1;
+        uint32_t ce                      : 1;
+        uint32_t reserved_9_31           : 23;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg070_s          cn52xx;
+    struct cvmx_pcieep_cfg070_s          cn52xxp1;
+    struct cvmx_pcieep_cfg070_s          cn56xx;
+    struct cvmx_pcieep_cfg070_s          cn56xxp1;
+} cvmx_pcieep_cfg070_t;
+
+
+/**
+ * cvmx_pcieep_cfg071
+ *
+ * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 0 config space
+ * (Header Log Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg071_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword1                  : 32;      /**< Header Log Register (first DWORD) */
+#else
+        uint32_t dword1                  : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg071_s          cn52xx;
+    struct cvmx_pcieep_cfg071_s          cn52xxp1;
+    struct cvmx_pcieep_cfg071_s          cn56xx;
+    struct cvmx_pcieep_cfg071_s          cn56xxp1;
+} cvmx_pcieep_cfg071_t;
+
+
+/**
+ * cvmx_pcieep_cfg072
+ *
+ * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 0 config space
+ * (Header Log Register 2)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg072_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword2                  : 32;      /**< Header Log Register (second DWORD) */
+#else
+        uint32_t dword2                  : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg072_s          cn52xx;
+    struct cvmx_pcieep_cfg072_s          cn52xxp1;
+    struct cvmx_pcieep_cfg072_s          cn56xx;
+    struct cvmx_pcieep_cfg072_s          cn56xxp1;
+} cvmx_pcieep_cfg072_t;
+
+
+/**
+ * cvmx_pcieep_cfg073
+ *
+ * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 0 config space
+ * (Header Log Register 3)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg073_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword3                  : 32;      /**< Header Log Register (third DWORD) */
+#else
+        uint32_t dword3                  : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg073_s          cn52xx;
+    struct cvmx_pcieep_cfg073_s          cn52xxp1;
+    struct cvmx_pcieep_cfg073_s          cn56xx;
+    struct cvmx_pcieep_cfg073_s          cn56xxp1;
+} cvmx_pcieep_cfg073_t;
+
+
+/**
+ * cvmx_pcieep_cfg074
+ *
+ * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 0 config space
+ * (Header Log Register 4)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg074_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword4                  : 32;      /**< Header Log Register (fourth DWORD) */
+#else
+        uint32_t dword4                  : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg074_s          cn52xx;
+    struct cvmx_pcieep_cfg074_s          cn52xxp1;
+    struct cvmx_pcieep_cfg074_s          cn56xx;
+    struct cvmx_pcieep_cfg074_s          cn56xxp1;
+} cvmx_pcieep_cfg074_t;
+
+
+/**
+ * cvmx_pcieep_cfg448
+ *
+ * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 0 config space
+ * (Ack Latency Timer and Replay Timer Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg448_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t rtl                     : 16;      /**< Replay Time Limit
+                                                         The replay timer expires when it reaches this limit. The PCI
+                                                         Express bus initiates a replay upon reception of a Nak or when
+                                                         the replay timer expires.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+        uint32_t rtltl                   : 16;      /**< Round Trip Latency Time Limit
+                                                         The Ack/Nak latency timer expires when it reaches this limit.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+#else
+        uint32_t rtltl                   : 16;
+        uint32_t rtl                     : 16;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg448_s          cn52xx;
+    struct cvmx_pcieep_cfg448_s          cn52xxp1;
+    struct cvmx_pcieep_cfg448_s          cn56xx;
+    struct cvmx_pcieep_cfg448_s          cn56xxp1;
+} cvmx_pcieep_cfg448_t;
+
+
+/**
+ * cvmx_pcieep_cfg449
+ *
+ * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 0 config space
+ * (Other Message Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg449_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t omr                     : 32;      /**< Other Message Register
+                                                         This register can be used for either of the following purposes:
+                                                         o To send a specific PCI Express Message, the application
+                                                           writes the payload of the Message into this register, then
+                                                           sets bit 0 of the Port Link Control Register to send the
+                                                           Message.
+                                                         o To store a corruption pattern for corrupting the LCRC on all
+                                                           TLPs, the application places a 32-bit corruption pattern into
+                                                           this register and enables this function by setting bit 25 of
+                                                           the Port Link Control Register. When enabled, the transmit
+                                                           LCRC result is XOR'd with this pattern before inserting
+                                                           it into the packet. */
+#else
+        uint32_t omr                     : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg449_s          cn52xx;
+    struct cvmx_pcieep_cfg449_s          cn52xxp1;
+    struct cvmx_pcieep_cfg449_s          cn56xx;
+    struct cvmx_pcieep_cfg449_s          cn56xxp1;
+} cvmx_pcieep_cfg449_t;
+
+
+/**
+ * cvmx_pcieep_cfg450
+ *
+ * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 0 config space
+ * (Port Force Link Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg450_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lpec                    : 8;       /**< Low Power Entrance Count
+                                                         The Power Management state will wait for this many clock cycles
+                                                         for the associated completion of a CfgWr to PCIE_CFG017 register
+                                                         Power State (PS) field register to go low-power. This register
+                                                         is intended for applications that do not let the PCI Express
+                                                         bus handle a completion for configuration request to the
+                                                         Power Management Control and Status (PCIE_CFG017) register. */
+        uint32_t reserved_22_23          : 2;
+        uint32_t link_state              : 6;       /**< Link State
+                                                         The Link state that the PCI Express Bus will be forced to
+                                                         when bit 15 (Force Link) is set.
+                                                         State encoding:
+                                                         o DETECT_QUIET              00h
+                                                         o DETECT_ACT                01h
+                                                         o POLL_ACTIVE               02h
+                                                         o POLL_COMPLIANCE           03h
+                                                         o POLL_CONFIG               04h
+                                                         o PRE_DETECT_QUIET          05h
+                                                         o DETECT_WAIT               06h
+                                                         o CFG_LINKWD_START          07h
+                                                         o CFG_LINKWD_ACEPT          08h
+                                                         o CFG_LANENUM_WAIT          09h
+                                                         o CFG_LANENUM_ACEPT         0Ah
+                                                         o CFG_COMPLETE              0Bh
+                                                         o CFG_IDLE                  0Ch
+                                                         o RCVRY_LOCK                0Dh
+                                                         o RCVRY_SPEED               0Eh
+                                                         o RCVRY_RCVRCFG             0Fh
+                                                         o RCVRY_IDLE                10h
+                                                         o L0                        11h
+                                                         o L0S                       12h
+                                                         o L123_SEND_EIDLE           13h
+                                                         o L1_IDLE                   14h
+                                                         o L2_IDLE                   15h
+                                                         o L2_WAKE                   16h
+                                                         o DISABLED_ENTRY            17h
+                                                         o DISABLED_IDLE             18h
+                                                         o DISABLED                  19h
+                                                         o LPBK_ENTRY                1Ah
+                                                         o LPBK_ACTIVE               1Bh
+                                                         o LPBK_EXIT                 1Ch
+                                                         o LPBK_EXIT_TIMEOUT         1Dh
+                                                         o HOT_RESET_ENTRY           1Eh
+                                                         o HOT_RESET                 1Fh */
+        uint32_t force_link              : 1;       /**< Force Link
+                                                         Forces the Link to the state specified by the Link State field.
+                                                         The Force Link pulse will trigger Link re-negotiation.
+                                                         * As the The Force Link is a pulse, writing a 1 to it does
+                                                           trigger the forced link state event, even thought reading it
+                                                           always returns a 0. */
+        uint32_t reserved_8_14           : 7;
+        uint32_t link_num                : 8;       /**< Link Number
+                                                         Not used for Endpoint */
+#else
+        uint32_t link_num                : 8;
+        uint32_t reserved_8_14           : 7;
+        uint32_t force_link              : 1;
+        uint32_t link_state              : 6;
+        uint32_t reserved_22_23          : 2;
+        uint32_t lpec                    : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg450_s          cn52xx;
+    struct cvmx_pcieep_cfg450_s          cn52xxp1;
+    struct cvmx_pcieep_cfg450_s          cn56xx;
+    struct cvmx_pcieep_cfg450_s          cn56xxp1;
+} cvmx_pcieep_cfg450_t;
+
+
+/**
+ * cvmx_pcieep_cfg451
+ *
+ * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 0 config space
+ * (Ack Frequency Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg451_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t l1el                    : 3;       /**< L1 Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 4 ms
+                                                         o 011: 8 ms
+                                                         o 100: 16 ms
+                                                         o 101: 32 ms
+                                                         o 110 or 111: 64 ms */
+        uint32_t l0el                    : 3;       /**< L0s Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 3 ms
+                                                         o 011: 4 ms
+                                                         o 100: 5 ms
+                                                         o 101: 6 ms
+                                                         o 110 or 111: 7 ms */
+        uint32_t n_fts_cc                : 8;       /**< N_FTS when common clock is used.
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                          Note: A value of zero is not supported; a value of
+                                                                zero can cause the LTSSM to go into the recovery state
+                                                                when exiting from L0s. */
+        uint32_t n_fts                   : 8;       /**< N_FTS
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                         Note: A value of zero is not supported; a value of
+                                                               zero can cause the LTSSM to go into the recovery state
+                                                               when exiting from L0s. */
+        uint32_t ack_freq                : 8;       /**< Ack Frequency
+                                                         The number of pending Ack's specified here (up to 255) before
+                                                         sending an Ack. */
+#else
+        uint32_t ack_freq                : 8;
+        uint32_t n_fts                   : 8;
+        uint32_t n_fts_cc                : 8;
+        uint32_t l0el                    : 3;
+        uint32_t l1el                    : 3;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg451_s          cn52xx;
+    struct cvmx_pcieep_cfg451_s          cn52xxp1;
+    struct cvmx_pcieep_cfg451_s          cn56xx;
+    struct cvmx_pcieep_cfg451_s          cn56xxp1;
+} cvmx_pcieep_cfg451_t;
+
+
+/**
+ * cvmx_pcieep_cfg452
+ *
+ * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 0 config space
+ * (Port Link Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg452_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t eccrc                   : 1;       /**< Enable Corrupted CRC
+                                                         Causes corrupt LCRC for TLPs when set,
+                                                         using the pattern contained in the Other Message register.
+                                                         This is a test feature, not to be used in normal operation. */
+        uint32_t reserved_22_24          : 3;
+        uint32_t lme                     : 6;       /**< Link Mode Enable
+                                                         o 000001: x1
+                                                         o 000011: x2
+                                                         o 000111: x4
+                                                         o 001111: x8
+                                                         o 011111: x16 (not supported)
+                                                         o 111111: x32 (not supported)
+                                                         This field indicates the MAXIMUM number of lanes supported
+                                                         by the PCIe port. It is set to 0xF or 0x7 depending
+                                                         on the value of the QLM_CFG bits (0xF when QLM_CFG == 0
+                                                         otherwise 0x7). The value can be set less than 0xF or 0x7
+                                                         to limit the number of lanes the PCIe will attempt to use.
+                                                         If the value of 0xF or 0x7 set by the HW is not desired,
+                                                         this field can be programmed to a smaller value (i.e. EEPROM)
+                                                         See also MLW.
+                                                         (Note: The value of this field does NOT indicate the number
+                                                          of lanes in use by the PCIe. LME sets the max number of lanes
+                                                          in the PCIe core that COULD be used. As per the PCIe specs,
+                                                          the PCIe core can negotiate a smaller link width, so all
+                                                          of x8, x4, x2, and x1 are supported when LME=0xF,
+                                                          for example.) */
+        uint32_t reserved_8_15           : 8;
+        uint32_t flm                     : 1;       /**< Fast Link Mode
+                                                         Sets all internal timers to fast mode for simulation purposes.
+                                                         If during an eeprom load, the first word loaded is 0xffffffff,
+                                                         then the EEPROM load will be terminated and this bit will be set. */
+        uint32_t reserved_6_6            : 1;
+        uint32_t dllle                   : 1;       /**< DLL Link Enable
+                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
+                                                         Express bus does not transmit InitFC DLLPs and does not
+                                                         establish a Link. */
+        uint32_t reserved_4_4            : 1;
+        uint32_t ra                      : 1;       /**< Reset Assert
+                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
+                                                         state (downstream port only). */
+        uint32_t le                      : 1;       /**< Loopback Enable
+                                                         Turns on loopback. */
+        uint32_t sd                      : 1;       /**< Scramble Disable
+                                                         Turns off data scrambling. */
+        uint32_t omr                     : 1;       /**< Other Message Request
+                                                         When software writes a `1' to this bit, the PCI Express bus
+                                                         transmits the Message contained in the Other Message register. */
+#else
+        uint32_t omr                     : 1;
+        uint32_t sd                      : 1;
+        uint32_t le                      : 1;
+        uint32_t ra                      : 1;
+        uint32_t reserved_4_4            : 1;
+        uint32_t dllle                   : 1;
+        uint32_t reserved_6_6            : 1;
+        uint32_t flm                     : 1;
+        uint32_t reserved_8_15           : 8;
+        uint32_t lme                     : 6;
+        uint32_t reserved_22_24          : 3;
+        uint32_t eccrc                   : 1;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg452_s          cn52xx;
+    struct cvmx_pcieep_cfg452_s          cn52xxp1;
+    struct cvmx_pcieep_cfg452_s          cn56xx;
+    struct cvmx_pcieep_cfg452_s          cn56xxp1;
+} cvmx_pcieep_cfg452_t;
+
+
+/**
+ * cvmx_pcieep_cfg453
+ *
+ * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 0 config space
+ * (Lane Skew Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg453_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dlld                    : 1;       /**< Disable Lane-to-Lane Deskew
+                                                         Disables the internal Lane-to-Lane deskew logic. */
+        uint32_t reserved_26_30          : 5;
+        uint32_t ack_nak                 : 1;       /**< Ack/Nak Disable
+                                                         Prevents the PCI Express bus from sending Ack and Nak DLLPs. */
+        uint32_t fcd                     : 1;       /**< Flow Control Disable
+                                                         Prevents the PCI Express bus from sending FC DLLPs. */
+        uint32_t ilst                    : 24;      /**< Insert Lane Skew for Transmit
+                                                         Causes skew between lanes for test purposes. There are three
+                                                         bits per Lane. The value is in units of one symbol time. For
+                                                         example, the value 010b for a Lane forces a skew of two symbol
+                                                         times for that Lane. The maximum skew value for any Lane is 5
+                                                         symbol times. */
+#else
+        uint32_t ilst                    : 24;
+        uint32_t fcd                     : 1;
+        uint32_t ack_nak                 : 1;
+        uint32_t reserved_26_30          : 5;
+        uint32_t dlld                    : 1;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg453_s          cn52xx;
+    struct cvmx_pcieep_cfg453_s          cn52xxp1;
+    struct cvmx_pcieep_cfg453_s          cn56xx;
+    struct cvmx_pcieep_cfg453_s          cn56xxp1;
+} cvmx_pcieep_cfg453_t;
+
+
+/**
+ * cvmx_pcieep_cfg454
+ *
+ * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 0 config space
+ * (Symbol Number Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg454_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_29_31          : 3;
+        uint32_t tmfcwt                  : 5;       /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+        uint32_t tmanlt                  : 5;       /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+        uint32_t tmrt                    : 5;       /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+        uint32_t reserved_11_13          : 3;
+        uint32_t nskps                   : 3;       /**< Number of SKP Symbols */
+        uint32_t reserved_4_7            : 4;
+        uint32_t ntss                    : 4;       /**< Number of TS Symbols
+                                                         Sets the number of TS identifier symbols that are sent in TS1
+                                                         and TS2 ordered sets. */
+#else
+        uint32_t ntss                    : 4;
+        uint32_t reserved_4_7            : 4;
+        uint32_t nskps                   : 3;
+        uint32_t reserved_11_13          : 3;
+        uint32_t tmrt                    : 5;
+        uint32_t tmanlt                  : 5;
+        uint32_t tmfcwt                  : 5;
+        uint32_t reserved_29_31          : 3;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg454_s          cn52xx;
+    struct cvmx_pcieep_cfg454_s          cn52xxp1;
+    struct cvmx_pcieep_cfg454_s          cn56xx;
+    struct cvmx_pcieep_cfg454_s          cn56xxp1;
+} cvmx_pcieep_cfg454_t;
+
+
+/**
+ * cvmx_pcieep_cfg455
+ *
+ * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 0 config space
+ * (Symbol Timer Register/Filter Mask Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg455_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t m_cfg0_filt             : 1;       /**< Mask filtering of received Configuration Requests (RC mode only) */
+        uint32_t m_io_filt               : 1;       /**< Mask filtering of received I/O Requests (RC mode only) */
+        uint32_t msg_ctrl                : 1;       /**< Message Control
+                                                         The application must not change this field. */
+        uint32_t m_cpl_ecrc_filt         : 1;       /**< Mask ECRC error filtering for Completions */
+        uint32_t m_ecrc_filt             : 1;       /**< Mask ECRC error filtering */
+        uint32_t m_cpl_len_err           : 1;       /**< Mask Length mismatch error for received Completions */
+        uint32_t m_cpl_attr_err          : 1;       /**< Mask Attributes mismatch error for received Completions */
+        uint32_t m_cpl_tc_err            : 1;       /**< Mask Traffic Class mismatch error for received Completions */
+        uint32_t m_cpl_fun_err           : 1;       /**< Mask function mismatch error for received Completions */
+        uint32_t m_cpl_rid_err           : 1;       /**< Mask Requester ID mismatch error for received Completions */
+        uint32_t m_cpl_tag_err           : 1;       /**< Mask Tag error rules for received Completions */
+        uint32_t m_lk_filt               : 1;       /**< Mask Locked Request filtering */
+        uint32_t m_cfg1_filt             : 1;       /**< Mask Type 1 Configuration Request filtering */
+        uint32_t m_bar_match             : 1;       /**< Mask BAR match filtering */
+        uint32_t m_pois_filt             : 1;       /**< Mask poisoned TLP filtering */
+        uint32_t m_fun                   : 1;       /**< Mask function */
+        uint32_t dfcwt                   : 1;       /**< Disable FC Watchdog Timer */
+        uint32_t reserved_11_14          : 4;
+        uint32_t skpiv                   : 11;      /**< SKP Interval Value */
+#else
+        uint32_t skpiv                   : 11;
+        uint32_t reserved_11_14          : 4;
+        uint32_t dfcwt                   : 1;
+        uint32_t m_fun                   : 1;
+        uint32_t m_pois_filt             : 1;
+        uint32_t m_bar_match             : 1;
+        uint32_t m_cfg1_filt             : 1;
+        uint32_t m_lk_filt               : 1;
+        uint32_t m_cpl_tag_err           : 1;
+        uint32_t m_cpl_rid_err           : 1;
+        uint32_t m_cpl_fun_err           : 1;
+        uint32_t m_cpl_tc_err            : 1;
+        uint32_t m_cpl_attr_err          : 1;
+        uint32_t m_cpl_len_err           : 1;
+        uint32_t m_ecrc_filt             : 1;
+        uint32_t m_cpl_ecrc_filt         : 1;
+        uint32_t msg_ctrl                : 1;
+        uint32_t m_io_filt               : 1;
+        uint32_t m_cfg0_filt             : 1;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg455_s          cn52xx;
+    struct cvmx_pcieep_cfg455_s          cn52xxp1;
+    struct cvmx_pcieep_cfg455_s          cn56xx;
+    struct cvmx_pcieep_cfg455_s          cn56xxp1;
+} cvmx_pcieep_cfg455_t;
+
+
+/**
+ * cvmx_pcieep_cfg456
+ *
+ * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 0 config space
+ * (Filter Mask Register 2)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg456_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_2_31           : 30;
+        uint32_t m_vend1_drp             : 1;       /**< Mask Vendor MSG Type 1 dropped silently */
+        uint32_t m_vend0_drp             : 1;       /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+        uint32_t m_vend0_drp             : 1;
+        uint32_t m_vend1_drp             : 1;
+        uint32_t reserved_2_31           : 30;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg456_s          cn52xx;
+    struct cvmx_pcieep_cfg456_s          cn52xxp1;
+    struct cvmx_pcieep_cfg456_s          cn56xx;
+    struct cvmx_pcieep_cfg456_s          cn56xxp1;
+} cvmx_pcieep_cfg456_t;
+
+
+/**
+ * cvmx_pcieep_cfg458
+ *
+ * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 0 config space
+ * (Debug Register 0)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg458_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dbg_info_l32            : 32;      /**< Debug Info Lower 32 Bits */
+#else
+        uint32_t dbg_info_l32            : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg458_s          cn52xx;
+    struct cvmx_pcieep_cfg458_s          cn52xxp1;
+    struct cvmx_pcieep_cfg458_s          cn56xx;
+    struct cvmx_pcieep_cfg458_s          cn56xxp1;
+} cvmx_pcieep_cfg458_t;
+
+
+/**
+ * cvmx_pcieep_cfg459
+ *
+ * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 0 config space
+ * (Debug Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg459_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dbg_info_u32            : 32;      /**< Debug Info Upper 32 Bits */
+#else
+        uint32_t dbg_info_u32            : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg459_s          cn52xx;
+    struct cvmx_pcieep_cfg459_s          cn52xxp1;
+    struct cvmx_pcieep_cfg459_s          cn56xx;
+    struct cvmx_pcieep_cfg459_s          cn56xxp1;
+} cvmx_pcieep_cfg459_t;
+
+
+/**
+ * cvmx_pcieep_cfg460
+ *
+ * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 0 config space
+ * (Transmit Posted FC Credit Status)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg460_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t tphfcc                  : 8;       /**< Transmit Posted Header FC Credits
+                                                         The Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+        uint32_t tpdfcc                  : 12;      /**< Transmit Posted Data FC Credits
+                                                         The Posted Data credits advertised by the receiver at the other
+                                                         end of the Link, updated with each UpdateFC DLLP. */
+#else
+        uint32_t tpdfcc                  : 12;
+        uint32_t tphfcc                  : 8;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg460_s          cn52xx;
+    struct cvmx_pcieep_cfg460_s          cn52xxp1;
+    struct cvmx_pcieep_cfg460_s          cn56xx;
+    struct cvmx_pcieep_cfg460_s          cn56xxp1;
+} cvmx_pcieep_cfg460_t;
+
+
+/**
+ * cvmx_pcieep_cfg461
+ *
+ * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 0 config space
+ * (Transmit Non-Posted FC Credit Status)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg461_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t tchfcc                  : 8;       /**< Transmit Non-Posted Header FC Credits
+                                                         The Non-Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+        uint32_t tcdfcc                  : 12;      /**< Transmit Non-Posted Data FC Credits
+                                                         The Non-Posted Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+        uint32_t tcdfcc                  : 12;
+        uint32_t tchfcc                  : 8;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg461_s          cn52xx;
+    struct cvmx_pcieep_cfg461_s          cn52xxp1;
+    struct cvmx_pcieep_cfg461_s          cn56xx;
+    struct cvmx_pcieep_cfg461_s          cn56xxp1;
+} cvmx_pcieep_cfg461_t;
+
+
+/**
+ * cvmx_pcieep_cfg462
+ *
+ * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 0 config space
+ * (Transmit Completion FC Credit Status )
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg462_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t tchfcc                  : 8;       /**< Transmit Completion Header FC Credits
+                                                         The Completion Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+        uint32_t tcdfcc                  : 12;      /**< Transmit Completion Data FC Credits
+                                                         The Completion Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+        uint32_t tcdfcc                  : 12;
+        uint32_t tchfcc                  : 8;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg462_s          cn52xx;
+    struct cvmx_pcieep_cfg462_s          cn52xxp1;
+    struct cvmx_pcieep_cfg462_s          cn56xx;
+    struct cvmx_pcieep_cfg462_s          cn56xxp1;
+} cvmx_pcieep_cfg462_t;
+
+
+/**
+ * cvmx_pcieep_cfg463
+ *
+ * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 0 config space
+ * (Queue Status)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg463_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_3_31           : 29;
+        uint32_t rqne                    : 1;       /**< Received Queue Not Empty
+                                                         Indicates there is data in one or more of the receive buffers. */
+        uint32_t trbne                   : 1;       /**< Transmit Retry Buffer Not Empty
+                                                         Indicates that there is data in the transmit retry buffer. */
+        uint32_t rtlpfccnr               : 1;       /**< Received TLP FC Credits Not Returned
+                                                         Indicates that the PCI Express bus has sent a TLP but has not
+                                                         yet received an UpdateFC DLLP indicating that the credits for
+                                                         that TLP have been restored by the receiver at the other end of
+                                                         the Link. */
+#else
+        uint32_t rtlpfccnr               : 1;
+        uint32_t trbne                   : 1;
+        uint32_t rqne                    : 1;
+        uint32_t reserved_3_31           : 29;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg463_s          cn52xx;
+    struct cvmx_pcieep_cfg463_s          cn52xxp1;
+    struct cvmx_pcieep_cfg463_s          cn56xx;
+    struct cvmx_pcieep_cfg463_s          cn56xxp1;
+} cvmx_pcieep_cfg463_t;
+
+
+/**
+ * cvmx_pcieep_cfg464
+ *
+ * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 0 config space
+ * (VC Transmit Arbitration Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg464_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t wrr_vc3                 : 8;       /**< WRR Weight for VC3 */
+        uint32_t wrr_vc2                 : 8;       /**< WRR Weight for VC2 */
+        uint32_t wrr_vc1                 : 8;       /**< WRR Weight for VC1 */
+        uint32_t wrr_vc0                 : 8;       /**< WRR Weight for VC0 */
+#else
+        uint32_t wrr_vc0                 : 8;
+        uint32_t wrr_vc1                 : 8;
+        uint32_t wrr_vc2                 : 8;
+        uint32_t wrr_vc3                 : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg464_s          cn52xx;
+    struct cvmx_pcieep_cfg464_s          cn52xxp1;
+    struct cvmx_pcieep_cfg464_s          cn56xx;
+    struct cvmx_pcieep_cfg464_s          cn56xxp1;
+} cvmx_pcieep_cfg464_t;
+
+
+/**
+ * cvmx_pcieep_cfg465
+ *
+ * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of PCIE type 0 config space
+ * (VC Transmit Arbitration Register 2)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg465_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t wrr_vc7                 : 8;       /**< WRR Weight for VC7 */
+        uint32_t wrr_vc6                 : 8;       /**< WRR Weight for VC6 */
+        uint32_t wrr_vc5                 : 8;       /**< WRR Weight for VC5 */
+        uint32_t wrr_vc4                 : 8;       /**< WRR Weight for VC4 */
+#else
+        uint32_t wrr_vc4                 : 8;
+        uint32_t wrr_vc5                 : 8;
+        uint32_t wrr_vc6                 : 8;
+        uint32_t wrr_vc7                 : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg465_s          cn52xx;
+    struct cvmx_pcieep_cfg465_s          cn52xxp1;
+    struct cvmx_pcieep_cfg465_s          cn56xx;
+    struct cvmx_pcieep_cfg465_s          cn56xxp1;
+} cvmx_pcieep_cfg465_t;
+
+
+/**
+ * cvmx_pcieep_cfg466
+ *
+ * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 0 config space
+ * (VC0 Posted Receive Queue Control)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg466_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t rx_queue_order          : 1;       /**< VC Ordering for Receive Queues
+                                                         Determines the VC ordering rule for the receive queues, used
+                                                         only in the segmented-buffer configuration,
+                                                         writable through the DBI:
+                                                         o 1: Strict ordering, higher numbered VCs have higher priority
+                                                         o 0: Round robin
+                                                         However, the application must not change this field. */
+        uint32_t type_ordering           : 1;       /**< TLP Type Ordering for VC0
+                                                         Determines the TLP type ordering rule for VC0 receive queues,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through the DBI:
+                                                         o 1: Ordering of received TLPs follows the rules in
+                                                              PCI Express Base Specification, Revision 1.1
+                                                         o 0: Strict ordering for received TLPs: Posted, then
+                                                              Completion, then Non-Posted
+                                                         However, the application must not change this field. */
+        uint32_t reserved_24_29          : 6;
+        uint32_t queue_mode              : 3;       /**< VC0 Posted TLP Queue Mode
+                                                         The operating mode of the Posted receive queue for VC0, used
+                                                         only in the segmented-buffer configuration, writable through
+                                                         the DBI. However, the application must not change this field.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward */
+        uint32_t reserved_20_20          : 1;
+        uint32_t header_credits          : 8;       /**< VC0 Posted Header Credits
+                                                         The number of initial Posted header credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t data_credits            : 12;      /**< VC0 Posted Data Credits
+                                                         The number of initial Posted data credits for VC0, used for all
+                                                         receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_credits            : 12;
+        uint32_t header_credits          : 8;
+        uint32_t reserved_20_20          : 1;
+        uint32_t queue_mode              : 3;
+        uint32_t reserved_24_29          : 6;
+        uint32_t type_ordering           : 1;
+        uint32_t rx_queue_order          : 1;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg466_s          cn52xx;
+    struct cvmx_pcieep_cfg466_s          cn52xxp1;
+    struct cvmx_pcieep_cfg466_s          cn56xx;
+    struct cvmx_pcieep_cfg466_s          cn56xxp1;
+} cvmx_pcieep_cfg466_t;
+
+
+/**
+ * cvmx_pcieep_cfg467
+ *
+ * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 0 config space
+ * (VC0 Non-Posted Receive Queue Control)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg467_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t queue_mode              : 3;       /**< VC0 Non-Posted TLP Queue Mode
+                                                         The operating mode of the Non-Posted receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through the DBI. Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t header_credits          : 8;       /**< VC0 Non-Posted Header Credits
+                                                         The number of initial Non-Posted header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t data_credits            : 12;      /**< VC0 Non-Posted Data Credits
+                                                         The number of initial Non-Posted data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_credits            : 12;
+        uint32_t header_credits          : 8;
+        uint32_t reserved_20_20          : 1;
+        uint32_t queue_mode              : 3;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg467_s          cn52xx;
+    struct cvmx_pcieep_cfg467_s          cn52xxp1;
+    struct cvmx_pcieep_cfg467_s          cn56xx;
+    struct cvmx_pcieep_cfg467_s          cn56xxp1;
+} cvmx_pcieep_cfg467_t;
+
+
+/**
+ * cvmx_pcieep_cfg468
+ *
+ * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 0 config space
+ * (VC0 Completion Receive Queue Control)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg468_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t queue_mode              : 3;       /**< VC0 Completion TLP Queue Mode
+                                                         The operating mode of the Completion receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through the DBI. Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t header_credits          : 8;       /**< VC0 Completion Header Credits
+                                                         The number of initial Completion header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t data_credits            : 12;      /**< VC0 Completion Data Credits
+                                                         The number of initial Completion data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_credits            : 12;
+        uint32_t header_credits          : 8;
+        uint32_t reserved_20_20          : 1;
+        uint32_t queue_mode              : 3;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg468_s          cn52xx;
+    struct cvmx_pcieep_cfg468_s          cn52xxp1;
+    struct cvmx_pcieep_cfg468_s          cn56xx;
+    struct cvmx_pcieep_cfg468_s          cn56xxp1;
+} cvmx_pcieep_cfg468_t;
+
+
+/**
+ * cvmx_pcieep_cfg490
+ *
+ * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 0 config space
+ * (VC0 Posted Buffer Depth)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg490_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t header_depth            : 10;      /**< VC0 Posted Header Queue Depth
+                                                         Sets the number of entries in the Posted header queue for VC0
+                                                         when using the segmented-buffer configuration, writable through
+                                                         the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t reserved_14_15          : 2;
+        uint32_t data_depth              : 14;      /**< VC0 Posted Data Queue Depth
+                                                         Sets the number of entries in the Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_depth              : 14;
+        uint32_t reserved_14_15          : 2;
+        uint32_t header_depth            : 10;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg490_s          cn52xx;
+    struct cvmx_pcieep_cfg490_s          cn52xxp1;
+    struct cvmx_pcieep_cfg490_s          cn56xx;
+    struct cvmx_pcieep_cfg490_s          cn56xxp1;
+} cvmx_pcieep_cfg490_t;
+
+
+/**
+ * cvmx_pcieep_cfg491
+ *
+ * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 0 config space
+ * (VC0 Non-Posted Buffer Depth)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg491_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t header_depth            : 10;      /**< VC0 Non-Posted Header Queue Depth
+                                                         Sets the number of entries in the Non-Posted header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t reserved_14_15          : 2;
+        uint32_t data_depth              : 14;      /**< VC0 Non-Posted Data Queue Depth
+                                                         Sets the number of entries in the Non-Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_depth              : 14;
+        uint32_t reserved_14_15          : 2;
+        uint32_t header_depth            : 10;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg491_s          cn52xx;
+    struct cvmx_pcieep_cfg491_s          cn52xxp1;
+    struct cvmx_pcieep_cfg491_s          cn56xx;
+    struct cvmx_pcieep_cfg491_s          cn56xxp1;
+} cvmx_pcieep_cfg491_t;
+
+
+/**
+ * cvmx_pcieep_cfg492
+ *
+ * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 0 config space
+ * (VC0 Completion Buffer Depth)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg492_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t header_depth            : 10;      /**< VC0 Completion Header Queue Depth
+                                                         Sets the number of entries in the Completion header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t reserved_14_15          : 2;
+        uint32_t data_depth              : 14;      /**< VC0 Completion Data Queue Depth
+                                                         Sets the number of entries in the Completion data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_depth              : 14;
+        uint32_t reserved_14_15          : 2;
+        uint32_t header_depth            : 10;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg492_s          cn52xx;
+    struct cvmx_pcieep_cfg492_s          cn52xxp1;
+    struct cvmx_pcieep_cfg492_s          cn56xx;
+    struct cvmx_pcieep_cfg492_s          cn56xxp1;
+} cvmx_pcieep_cfg492_t;
+
+
+/**
+ * cvmx_pcieep_cfg516
+ *
+ * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 0 config space
+ * (PHY Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg516_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t phy_stat                : 32;      /**< PHY Status */
+#else
+        uint32_t phy_stat                : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg516_s          cn52xx;
+    struct cvmx_pcieep_cfg516_s          cn52xxp1;
+    struct cvmx_pcieep_cfg516_s          cn56xx;
+    struct cvmx_pcieep_cfg516_s          cn56xxp1;
+} cvmx_pcieep_cfg516_t;
+
+
+/**
+ * cvmx_pcieep_cfg517
+ *
+ * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 0 config space
+ * (PHY Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pcieep_cfg517_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t phy_ctrl                : 32;      /**< PHY Control */
+#else
+        uint32_t phy_ctrl                : 32;
+#endif
+    } s;
+    struct cvmx_pcieep_cfg517_s          cn52xx;
+    struct cvmx_pcieep_cfg517_s          cn52xxp1;
+    struct cvmx_pcieep_cfg517_s          cn56xx;
+    struct cvmx_pcieep_cfg517_s          cn56xxp1;
+} cvmx_pcieep_cfg517_t;
+
+
+/**
+ * cvmx_pcierc#_cfg000
+ *
+ * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg000_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t devid                   : 16;      /**< Device ID, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t vendid                  : 16;      /**< Vendor ID, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t vendid                  : 16;
+        uint32_t devid                   : 16;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg000_s         cn52xx;
+    struct cvmx_pciercx_cfg000_s         cn52xxp1;
+    struct cvmx_pciercx_cfg000_s         cn56xx;
+    struct cvmx_pciercx_cfg000_s         cn56xxp1;
+} cvmx_pciercx_cfg000_t;
+
+
+/**
+ * cvmx_pcierc#_cfg001
+ *
+ * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg001_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dpe                     : 1;       /**< Detected Parity Error */
+        uint32_t sse                     : 1;       /**< Signaled System Error */
+        uint32_t rma                     : 1;       /**< Received Master Abort */
+        uint32_t rta                     : 1;       /**< Received Target Abort */
+        uint32_t sta                     : 1;       /**< Signaled Target Abort */
+        uint32_t devt                    : 2;       /**< DEVSEL Timing
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
+        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t reserved_22_22          : 1;
+        uint32_t m66                     : 1;       /**< 66 MHz Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t cl                      : 1;       /**< Capabilities List
+                                                         Indicates presence of an extended capability item.
+                                                         Hardwired to 1. */
+        uint32_t i_stat                  : 1;       /**< INTx Status */
+        uint32_t reserved_11_18          : 8;
+        uint32_t i_dis                   : 1;       /**< INTx Assertion Disable */
+        uint32_t fbbe                    : 1;       /**< Fast Back-to-Back Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t see                     : 1;       /**< SERR# Enable */
+        uint32_t ids_wcc                 : 1;       /**< IDSEL Stepping/Wait Cycle Control
+                                                         Not applicable for PCI Express. Must be hardwired to 0 */
+        uint32_t per                     : 1;       /**< Parity Error Response */
+        uint32_t vps                     : 1;       /**< VGA Palette Snoop
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t mwice                   : 1;       /**< Memory Write and Invalidate
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t scse                    : 1;       /**< Special Cycle Enable
+                                                         Not applicable for PCI Express. Must be hardwired to 0. */
+        uint32_t me                      : 1;       /**< Bus Master Enable */
+        uint32_t msae                    : 1;       /**< Memory Space Enable */
+        uint32_t isae                    : 1;       /**< I/O Space Enable */
+#else
+        uint32_t isae                    : 1;
+        uint32_t msae                    : 1;
+        uint32_t me                      : 1;
+        uint32_t scse                    : 1;
+        uint32_t mwice                   : 1;
+        uint32_t vps                     : 1;
+        uint32_t per                     : 1;
+        uint32_t ids_wcc                 : 1;
+        uint32_t see                     : 1;
+        uint32_t fbbe                    : 1;
+        uint32_t i_dis                   : 1;
+        uint32_t reserved_11_18          : 8;
+        uint32_t i_stat                  : 1;
+        uint32_t cl                      : 1;
+        uint32_t m66                     : 1;
+        uint32_t reserved_22_22          : 1;
+        uint32_t fbb                     : 1;
+        uint32_t mdpe                    : 1;
+        uint32_t devt                    : 2;
+        uint32_t sta                     : 1;
+        uint32_t rta                     : 1;
+        uint32_t rma                     : 1;
+        uint32_t sse                     : 1;
+        uint32_t dpe                     : 1;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg001_s         cn52xx;
+    struct cvmx_pciercx_cfg001_s         cn52xxp1;
+    struct cvmx_pciercx_cfg001_s         cn56xx;
+    struct cvmx_pciercx_cfg001_s         cn56xxp1;
+} cvmx_pciercx_cfg001_t;
+
+
+/**
+ * cvmx_pcierc#_cfg002
+ *
+ * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg002_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t bcc                     : 8;       /**< Base Class Code, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t sc                      : 8;       /**< Subclass Code, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t pi                      : 8;       /**< Programming Interface, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t rid                     : 8;       /**< Revision ID, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t rid                     : 8;
+        uint32_t pi                      : 8;
+        uint32_t sc                      : 8;
+        uint32_t bcc                     : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg002_s         cn52xx;
+    struct cvmx_pciercx_cfg002_s         cn52xxp1;
+    struct cvmx_pciercx_cfg002_s         cn56xx;
+    struct cvmx_pciercx_cfg002_s         cn56xxp1;
+} cvmx_pciercx_cfg002_t;
+
+
+/**
+ * cvmx_pcierc#_cfg003
+ *
+ * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg003_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t bist                    : 8;       /**< The BIST register functions are not supported.
+                                                         All 8 bits of the BIST register are hardwired to 0. */
+        uint32_t mfd                     : 1;       /**< Multi Function Device
+                                                         The Multi Function Device bit is writable through the DBI.
+                                                         However, this is a single function device. Therefore, the
+                                                         application must not write a 1 to this bit. */
+        uint32_t chf                     : 7;       /**< Configuration Header Format
+                                                         Hardwired to 1. */
+        uint32_t lt                      : 8;       /**< Master Latency Timer
+                                                         Not applicable for PCI Express, hardwired to 0. */
+        uint32_t cls                     : 8;       /**< Cache Line Size
+                                                         The Cache Line Size register is RW for legacy compatibility
+                                                         purposes and is not applicable to PCI Express device
+                                                         functionality. */
+#else
+        uint32_t cls                     : 8;
+        uint32_t lt                      : 8;
+        uint32_t chf                     : 7;
+        uint32_t mfd                     : 1;
+        uint32_t bist                    : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg003_s         cn52xx;
+    struct cvmx_pciercx_cfg003_s         cn52xxp1;
+    struct cvmx_pciercx_cfg003_s         cn56xx;
+    struct cvmx_pciercx_cfg003_s         cn56xxp1;
+} cvmx_pciercx_cfg003_t;
+
+
+/**
+ * cvmx_pcierc#_cfg004
+ *
+ * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg004_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg004_s         cn52xx;
+    struct cvmx_pciercx_cfg004_s         cn52xxp1;
+    struct cvmx_pciercx_cfg004_s         cn56xx;
+    struct cvmx_pciercx_cfg004_s         cn56xxp1;
+} cvmx_pciercx_cfg004_t;
+
+
+/**
+ * cvmx_pcierc#_cfg005
+ *
+ * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg005_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg005_s         cn52xx;
+    struct cvmx_pciercx_cfg005_s         cn52xxp1;
+    struct cvmx_pciercx_cfg005_s         cn56xx;
+    struct cvmx_pciercx_cfg005_s         cn56xxp1;
+} cvmx_pciercx_cfg005_t;
+
+
+/**
+ * cvmx_pcierc#_cfg006
+ *
+ * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg006_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t slt                     : 8;       /**< Secondary Latency Timer
+                                                         Not applicable to PCI Express, hardwired to 0x00. */
+        uint32_t subbnum                 : 8;       /**< Subordinate Bus Number */
+        uint32_t sbnum                   : 8;       /**< Secondary Bus Number */
+        uint32_t pbnum                   : 8;       /**< Primary Bus Number */
+#else
+        uint32_t pbnum                   : 8;
+        uint32_t sbnum                   : 8;
+        uint32_t subbnum                 : 8;
+        uint32_t slt                     : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg006_s         cn52xx;
+    struct cvmx_pciercx_cfg006_s         cn52xxp1;
+    struct cvmx_pciercx_cfg006_s         cn56xx;
+    struct cvmx_pciercx_cfg006_s         cn56xxp1;
+} cvmx_pciercx_cfg006_t;
+
+
+/**
+ * cvmx_pcierc#_cfg007
+ *
+ * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg007_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dpe                     : 1;       /**< Detected Parity Error */
+        uint32_t sse                     : 1;       /**< Signaled System Error */
+        uint32_t rma                     : 1;       /**< Received Master Abort */
+        uint32_t rta                     : 1;       /**< Received Target Abort */
+        uint32_t sta                     : 1;       /**< Signaled Target Abort */
+        uint32_t devt                    : 2;       /**< DEVSEL Timing
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t mdpe                    : 1;       /**< Master Data Parity Error */
+        uint32_t fbb                     : 1;       /**< Fast Back-to-Back Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t reserved_22_22          : 1;
+        uint32_t m66                     : 1;       /**< 66 MHz Capable
+                                                         Not applicable for PCI Express. Hardwired to 0. */
+        uint32_t reserved_16_20          : 5;
+        uint32_t lio_limi                : 4;       /**< I/O Space Limit */
+        uint32_t reserved_9_11           : 3;
+        uint32_t io32b                   : 1;       /**< 32-Bit I/O Space */
+        uint32_t lio_base                : 4;       /**< I/O Space Base */
+        uint32_t reserved_1_3            : 3;
+        uint32_t io32a                   : 1;       /**< 32-Bit I/O Space
+                                                         o 0 = 16-bit I/O addressing
+                                                         o 1 = 32-bit I/O addressing
+                                                         This bit is writable through the DBI. When the application
+                                                         writes to this bit through the DBI, the same value is written
+                                                         to bit 8 of this register. */
+#else
+        uint32_t io32a                   : 1;
+        uint32_t reserved_1_3            : 3;
+        uint32_t lio_base                : 4;
+        uint32_t io32b                   : 1;
+        uint32_t reserved_9_11           : 3;
+        uint32_t lio_limi                : 4;
+        uint32_t reserved_16_20          : 5;
+        uint32_t m66                     : 1;
+        uint32_t reserved_22_22          : 1;
+        uint32_t fbb                     : 1;
+        uint32_t mdpe                    : 1;
+        uint32_t devt                    : 2;
+        uint32_t sta                     : 1;
+        uint32_t rta                     : 1;
+        uint32_t rma                     : 1;
+        uint32_t sse                     : 1;
+        uint32_t dpe                     : 1;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg007_s         cn52xx;
+    struct cvmx_pciercx_cfg007_s         cn52xxp1;
+    struct cvmx_pciercx_cfg007_s         cn56xx;
+    struct cvmx_pciercx_cfg007_s         cn56xxp1;
+} cvmx_pciercx_cfg007_t;
+
+
+/**
+ * cvmx_pcierc#_cfg008
+ *
+ * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg008_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ml_addr                 : 12;      /**< Memory Limit Address */
+        uint32_t reserved_16_19          : 4;
+        uint32_t mb_addr                 : 12;      /**< Memory Base Address */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t mb_addr                 : 12;
+        uint32_t reserved_16_19          : 4;
+        uint32_t ml_addr                 : 12;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg008_s         cn52xx;
+    struct cvmx_pciercx_cfg008_s         cn52xxp1;
+    struct cvmx_pciercx_cfg008_s         cn56xx;
+    struct cvmx_pciercx_cfg008_s         cn56xxp1;
+} cvmx_pciercx_cfg008_t;
+
+
+/**
+ * cvmx_pcierc#_cfg009
+ *
+ * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg009_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lmem_limit              : 12;      /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */
+        uint32_t reserved_17_19          : 3;
+        uint32_t mem64b                  : 1;       /**< 64-Bit Memory Addressing
+                                                         o 0 = 32-bit memory addressing
+                                                         o 1 = 64-bit memory addressing */
+        uint32_t lmem_base               : 12;      /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */
+        uint32_t reserved_1_3            : 3;
+        uint32_t mem64a                  : 1;       /**< 64-Bit Memory Addressing
+                                                         o 0 = 32-bit memory addressing
+                                                         o 1 = 64-bit memory addressing
+                                                         This bit is writable through the DBI. When the application
+                                                         writes to this bit through the DBI, the same value is written
+                                                         to bit 16 of this register. */
+#else
+        uint32_t mem64a                  : 1;
+        uint32_t reserved_1_3            : 3;
+        uint32_t lmem_base               : 12;
+        uint32_t mem64b                  : 1;
+        uint32_t reserved_17_19          : 3;
+        uint32_t lmem_limit              : 12;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg009_s         cn52xx;
+    struct cvmx_pciercx_cfg009_s         cn52xxp1;
+    struct cvmx_pciercx_cfg009_s         cn56xx;
+    struct cvmx_pciercx_cfg009_s         cn56xxp1;
+} cvmx_pciercx_cfg009_t;
+
+
+/**
+ * cvmx_pcierc#_cfg010
+ *
+ * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg010_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umem_base               : 32;      /**< Upper 32 Bits of Base Address of Prefetchable Memory Space
+                                                         Used only when 64-bit prefetchable memory addressing is
+                                                         enabled. */
+#else
+        uint32_t umem_base               : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg010_s         cn52xx;
+    struct cvmx_pciercx_cfg010_s         cn52xxp1;
+    struct cvmx_pciercx_cfg010_s         cn56xx;
+    struct cvmx_pciercx_cfg010_s         cn56xxp1;
+} cvmx_pciercx_cfg010_t;
+
+
+/**
+ * cvmx_pcierc#_cfg011
+ *
+ * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg011_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umem_limit              : 32;      /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space
+                                                         Used only when 64-bit prefetchable memory addressing is
+                                                         enabled. */
+#else
+        uint32_t umem_limit              : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg011_s         cn52xx;
+    struct cvmx_pciercx_cfg011_s         cn52xxp1;
+    struct cvmx_pciercx_cfg011_s         cn56xx;
+    struct cvmx_pciercx_cfg011_s         cn56xxp1;
+} cvmx_pciercx_cfg011_t;
+
+
+/**
+ * cvmx_pcierc#_cfg012
+ *
+ * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg012_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t uio_limit               : 16;      /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported
+                                                         for devices on the secondary side) */
+        uint32_t uio_base                : 16;      /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported
+                                                         for devices on the secondary side) */
+#else
+        uint32_t uio_base                : 16;
+        uint32_t uio_limit               : 16;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg012_s         cn52xx;
+    struct cvmx_pciercx_cfg012_s         cn52xxp1;
+    struct cvmx_pciercx_cfg012_s         cn56xx;
+    struct cvmx_pciercx_cfg012_s         cn56xxp1;
+} cvmx_pciercx_cfg012_t;
+
+
+/**
+ * cvmx_pcierc#_cfg013
+ *
+ * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg013_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_8_31           : 24;
+        uint32_t cp                      : 8;       /**< First Capability Pointer.
+                                                         Points to Power Management Capability structure by
+                                                         default, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t cp                      : 8;
+        uint32_t reserved_8_31           : 24;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg013_s         cn52xx;
+    struct cvmx_pciercx_cfg013_s         cn52xxp1;
+    struct cvmx_pciercx_cfg013_s         cn56xx;
+    struct cvmx_pciercx_cfg013_s         cn56xxp1;
+} cvmx_pciercx_cfg013_t;
+
+
+/**
+ * cvmx_pcierc#_cfg014
+ *
+ * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg014_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg014_s         cn52xx;
+    struct cvmx_pciercx_cfg014_s         cn52xxp1;
+    struct cvmx_pciercx_cfg014_s         cn56xx;
+    struct cvmx_pciercx_cfg014_s         cn56xxp1;
+} cvmx_pciercx_cfg014_t;
+
+
+/**
+ * cvmx_pcierc#_cfg015
+ *
+ * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg015_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_28_31          : 4;
+        uint32_t dtsees                  : 1;       /**< Discard Timer SERR Enable Status
+                                                         Not applicable to PCI Express, hardwired to 0. */
+        uint32_t dts                     : 1;       /**< Discard Timer Status
+                                                         Not applicable to PCI Express, hardwired to 0. */
+        uint32_t sdt                     : 1;       /**< Secondary Discard Timer
+                                                         Not applicable to PCI Express, hardwired to 0. */
+        uint32_t pdt                     : 1;       /**< Primary Discard Timer
+                                                         Not applicable to PCI Express, hardwired to 0. */
+        uint32_t fbbe                    : 1;       /**< Fast Back-to-Back Transactions Enable
+                                                         Not applicable to PCI Express, hardwired to 0. */
+        uint32_t sbrst                   : 1;       /**< Secondary Bus Reset
+                                                         Hot reset. Causes TS1s with the hot reset bit to be sent to
+                                                         the link partner. When set, SW should wait 2ms before
+                                                         clearing. The link partner normally responds by sending TS1s
+                                                         with the hot reset bit set, which will cause a link
+                                                         down event - refer to "PCIe Link-Down Reset in RC Mode"
+                                                         section. */
+        uint32_t mam                     : 1;       /**< Master Abort Mode
+                                                         Not applicable to PCI Express, hardwired to 0. */
+        uint32_t vga16d                  : 1;       /**< VGA 16-Bit Decode */
+        uint32_t vgae                    : 1;       /**< VGA Enable */
+        uint32_t isae                    : 1;       /**< ISA Enable */
+        uint32_t see                     : 1;       /**< SERR Enable */
+        uint32_t pere                    : 1;       /**< Parity Error Response Enable */
+        uint32_t inta                    : 8;       /**< Interrupt Pin
+                                                         Identifies the legacy interrupt Message that the device
+                                                         (or device function) uses.
+                                                         The Interrupt Pin register is writable through the DBI.
+                                                         In a single-function configuration, only INTA is used.
+                                                         Therefore, the application must not change this field. */
+        uint32_t il                      : 8;       /**< Interrupt Line */
+#else
+        uint32_t il                      : 8;
+        uint32_t inta                    : 8;
+        uint32_t pere                    : 1;
+        uint32_t see                     : 1;
+        uint32_t isae                    : 1;
+        uint32_t vgae                    : 1;
+        uint32_t vga16d                  : 1;
+        uint32_t mam                     : 1;
+        uint32_t sbrst                   : 1;
+        uint32_t fbbe                    : 1;
+        uint32_t pdt                     : 1;
+        uint32_t sdt                     : 1;
+        uint32_t dts                     : 1;
+        uint32_t dtsees                  : 1;
+        uint32_t reserved_28_31          : 4;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg015_s         cn52xx;
+    struct cvmx_pciercx_cfg015_s         cn52xxp1;
+    struct cvmx_pciercx_cfg015_s         cn56xx;
+    struct cvmx_pciercx_cfg015_s         cn56xxp1;
+} cvmx_pciercx_cfg015_t;
+
+
+/**
+ * cvmx_pcierc#_cfg016
+ *
+ * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space
+ * (Power Management Capability ID/
+ * Power Management Next Item Pointer/
+ * Power Management Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg016_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pmes                    : 5;       /**< PME_Support
+                                                         A value of 0 for any bit indicates that the
+                                                         device (or function) is not capable of generating PME Messages
+                                                         while in that power state:
+                                                         o Bit 11: If set, PME Messages can be generated from D0
+                                                         o Bit 12: If set, PME Messages can be generated from D1
+                                                         o Bit 13: If set, PME Messages can be generated from D2
+                                                         o Bit 14: If set, PME Messages can be generated from D3hot
+                                                         o Bit 15: If set, PME Messages can be generated from D3cold
+                                                         The PME_Support field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t d2s                     : 1;       /**< D2 Support, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t d1s                     : 1;       /**< D1 Support, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t auxc                    : 3;       /**< AUX Current, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t dsi                     : 1;       /**< Device Specific Initialization (DSI), writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t pme_clock               : 1;       /**< PME Clock, hardwired to 0 */
+        uint32_t pmsv                    : 3;       /**< Power Management Specification Version, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer
+                                                         Points to the MSI capabilities by default, writable
+                                                         through the DBI. */
+        uint32_t pmcid                   : 8;       /**< Power Management Capability ID */
+#else
+        uint32_t pmcid                   : 8;
+        uint32_t ncp                     : 8;
+        uint32_t pmsv                    : 3;
+        uint32_t pme_clock               : 1;
+        uint32_t reserved_20_20          : 1;
+        uint32_t dsi                     : 1;
+        uint32_t auxc                    : 3;
+        uint32_t d1s                     : 1;
+        uint32_t d2s                     : 1;
+        uint32_t pmes                    : 5;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg016_s         cn52xx;
+    struct cvmx_pciercx_cfg016_s         cn52xxp1;
+    struct cvmx_pciercx_cfg016_s         cn56xx;
+    struct cvmx_pciercx_cfg016_s         cn56xxp1;
+} cvmx_pciercx_cfg016_t;
+
+
+/**
+ * cvmx_pcierc#_cfg017
+ *
+ * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg017_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pmdia                   : 8;       /**< Data register for additional information (not supported) */
+        uint32_t bpccee                  : 1;       /**< Bus Power/Clock Control Enable, hardwired to 0 */
+        uint32_t bd3h                    : 1;       /**< B2/B3 Support, hardwired to 0 */
+        uint32_t reserved_16_21          : 6;
+        uint32_t pmess                   : 1;       /**< PME Status
+                                                         Indicates if a previously enabled PME event occurred or not. */
+        uint32_t pmedsia                 : 2;       /**< Data Scale (not supported) */
+        uint32_t pmds                    : 4;       /**< Data Select (not supported) */
+        uint32_t pmeens                  : 1;       /**< PME Enable
+                                                         A value of 1 indicates that the device is enabled to
+                                                         generate PME. */
+        uint32_t reserved_4_7            : 4;
+        uint32_t nsr                     : 1;       /**< No Soft Reset, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_2_2            : 1;
+        uint32_t ps                      : 2;       /**< Power State
+                                                         Controls the device power state:
+                                                           o 00b: D0
+                                                           o 01b: D1
+                                                           o 10b: D2
+                                                           o 11b: D3
+                                                         The written value is ignored if the specific state is
+                                                         not supported. */
+#else
+        uint32_t ps                      : 2;
+        uint32_t reserved_2_2            : 1;
+        uint32_t nsr                     : 1;
+        uint32_t reserved_4_7            : 4;
+        uint32_t pmeens                  : 1;
+        uint32_t pmds                    : 4;
+        uint32_t pmedsia                 : 2;
+        uint32_t pmess                   : 1;
+        uint32_t reserved_16_21          : 6;
+        uint32_t bd3h                    : 1;
+        uint32_t bpccee                  : 1;
+        uint32_t pmdia                   : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg017_s         cn52xx;
+    struct cvmx_pciercx_cfg017_s         cn52xxp1;
+    struct cvmx_pciercx_cfg017_s         cn56xx;
+    struct cvmx_pciercx_cfg017_s         cn56xxp1;
+} cvmx_pciercx_cfg017_t;
+
+
+/**
+ * cvmx_pcierc#_cfg020
+ *
+ * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space
+ * (MSI Capability ID/
+ *  MSI Next Item Pointer/
+ *  MSI Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg020_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t m64                     : 1;       /**< 64-bit Address Capable, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t mme                     : 3;       /**< Multiple Message Enabled
+                                                         Indicates that multiple Message mode is enabled by system
+                                                         software. The number of Messages enabled must be less than
+                                                         or equal to the Multiple Message Capable value. */
+        uint32_t mmc                     : 3;       /**< Multiple Message Capable, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t msien                   : 1;       /**< MSI Enabled
+                                                         When set, INTx must be disabled.
+                                                         This bit must never be set, as internal-MSI is not supported in
+                                                         RC mode. (Note that this has no effect on external MSI, which
+                                                         will be commonly used in RC mode.) */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer
+                                                         Points to PCI Express Capabilities by default,
+                                                         writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t msicid                  : 8;       /**< MSI Capability ID */
+#else
+        uint32_t msicid                  : 8;
+        uint32_t ncp                     : 8;
+        uint32_t msien                   : 1;
+        uint32_t mmc                     : 3;
+        uint32_t mme                     : 3;
+        uint32_t m64                     : 1;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg020_s         cn52xx;
+    struct cvmx_pciercx_cfg020_s         cn52xxp1;
+    struct cvmx_pciercx_cfg020_s         cn56xx;
+    struct cvmx_pciercx_cfg020_s         cn56xxp1;
+} cvmx_pciercx_cfg020_t;
+
+
+/**
+ * cvmx_pcierc#_cfg021
+ *
+ * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg021_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lmsi                    : 30;      /**< Lower 32-bit Address */
+        uint32_t reserved_0_1            : 2;
+#else
+        uint32_t reserved_0_1            : 2;
+        uint32_t lmsi                    : 30;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg021_s         cn52xx;
+    struct cvmx_pciercx_cfg021_s         cn52xxp1;
+    struct cvmx_pciercx_cfg021_s         cn56xx;
+    struct cvmx_pciercx_cfg021_s         cn56xxp1;
+} cvmx_pciercx_cfg021_t;
+
+
+/**
+ * cvmx_pcierc#_cfg022
+ *
+ * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg022_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t umsi                    : 32;      /**< Upper 32-bit Address */
+#else
+        uint32_t umsi                    : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg022_s         cn52xx;
+    struct cvmx_pciercx_cfg022_s         cn52xxp1;
+    struct cvmx_pciercx_cfg022_s         cn56xx;
+    struct cvmx_pciercx_cfg022_s         cn56xxp1;
+} cvmx_pciercx_cfg022_t;
+
+
+/**
+ * cvmx_pcierc#_cfg023
+ *
+ * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg023_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t msimd                   : 16;      /**< MSI Data
+                                                         Pattern assigned by system software, bits [4:0] are Or-ed with
+                                                         MSI_VECTOR to generate 32 MSI Messages per function. */
+#else
+        uint32_t msimd                   : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg023_s         cn52xx;
+    struct cvmx_pciercx_cfg023_s         cn52xxp1;
+    struct cvmx_pciercx_cfg023_s         cn56xx;
+    struct cvmx_pciercx_cfg023_s         cn56xxp1;
+} cvmx_pciercx_cfg023_t;
+
+
+/**
+ * cvmx_pcierc#_cfg028
+ *
+ * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space
+ * (PCI Express Capabilities List Register/
+ *  PCI Express Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg028_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t imn                     : 5;       /**< Interrupt Message Number
+                                                         Updated by hardware, writable through the DBI.
+                                                          However, the application must not change this field. */
+        uint32_t si                      : 1;       /**< Slot Implemented
+                                                         This bit is writable through the DBI. However, it must 0 for an
+                                                         Endpoint device. Therefore, the application must not write a
+                                                         1 to this bit. */
+        uint32_t dpt                     : 4;       /**< Device Port Type */
+        uint32_t pciecv                  : 4;       /**< PCI Express Capability Version */
+        uint32_t ncp                     : 8;       /**< Next Capability Pointer
+                                                         writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t pcieid                  : 8;       /**< PCIE Capability ID */
+#else
+        uint32_t pcieid                  : 8;
+        uint32_t ncp                     : 8;
+        uint32_t pciecv                  : 4;
+        uint32_t dpt                     : 4;
+        uint32_t si                      : 1;
+        uint32_t imn                     : 5;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg028_s         cn52xx;
+    struct cvmx_pciercx_cfg028_s         cn52xxp1;
+    struct cvmx_pciercx_cfg028_s         cn56xx;
+    struct cvmx_pciercx_cfg028_s         cn56xxp1;
+} cvmx_pciercx_cfg028_t;
+
+
+/**
+ * cvmx_pcierc#_cfg029
+ *
+ * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg029_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_28_31          : 4;
+        uint32_t cspls                   : 2;       /**< Captured Slot Power Limit Scale
+                                                         Not applicable for RC port, upstream port only. */
+        uint32_t csplv                   : 8;       /**< Captured Slot Power Limit Value
+                                                         Not applicable for RC port, upstream port only. */
+        uint32_t reserved_16_17          : 2;
+        uint32_t rber                    : 1;       /**< Role-Based Error Reporting, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_12_14          : 3;
+        uint32_t el1al                   : 3;       /**< Endpoint L1 Acceptable Latency, writable through the DBI
+                                                         Must be 0x0 for non-endpoint devices. */
+        uint32_t el0al                   : 3;       /**< Endpoint L0s Acceptable Latency, writable through the DBI
+                                                         Must be 0x0 for non-endpoint devices. */
+        uint32_t etfs                    : 1;       /**< Extended Tag Field Supported
+                                                         This bit is writable through the DBI. However, the application
+                                                         must not write a 1 to this bit. */
+        uint32_t pfs                     : 2;       /**< Phantom Function Supported
+                                                         This field is writable through the DBI. However, Phantom
+                                                         Function is not supported. Therefore, the application must not
+                                                         write any value other than 0x0 to this field. */
+        uint32_t mpss                    : 3;       /**< Max_Payload_Size Supported, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t mpss                    : 3;
+        uint32_t pfs                     : 2;
+        uint32_t etfs                    : 1;
+        uint32_t el0al                   : 3;
+        uint32_t el1al                   : 3;
+        uint32_t reserved_12_14          : 3;
+        uint32_t rber                    : 1;
+        uint32_t reserved_16_17          : 2;
+        uint32_t csplv                   : 8;
+        uint32_t cspls                   : 2;
+        uint32_t reserved_28_31          : 4;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg029_s         cn52xx;
+    struct cvmx_pciercx_cfg029_s         cn52xxp1;
+    struct cvmx_pciercx_cfg029_s         cn56xx;
+    struct cvmx_pciercx_cfg029_s         cn56xxp1;
+} cvmx_pciercx_cfg029_t;
+
+
+/**
+ * cvmx_pcierc#_cfg030
+ *
+ * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space
+ * (Device Control Register/Device Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg030_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_22_31          : 10;
+        uint32_t tp                      : 1;       /**< Transaction Pending
+                                                         Set to 1 when Non-Posted Requests are not yet completed
+                                                         and clear when they are completed. */
+        uint32_t ap_d                    : 1;       /**< Aux Power Detected
+                                                         Set to 1 if Aux power detected. */
+        uint32_t ur_d                    : 1;       /**< Unsupported Request Detected
+                                                         Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         UR_D occurs when we receive something we don't support.
+                                                         Unsupported requests are Nonfatal errors, so UR_D should
+                                                         cause NFE_D.  Receiving a  vendor defined message should
+                                                         cause an unsupported request. */
+        uint32_t fe_d                    : 1;       /**< Fatal Error Detected
+                                                         Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         FE_D is set if receive any of the errors in PCIE_CFG066 that
+                                                         has a severity set to Fatal.  Malformed TLP's generally fit
+                                                         into this category. */
+        uint32_t nfe_d                   : 1;       /**< Non-Fatal Error detected
+                                                         Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         NFE_D is set if we receive any of the errors in PCIE_CFG066
+                                                         that has a severity set to Nonfatal and does NOT meet Advisory
+                                                         Nonfatal criteria (PCIe 1.1 spec, Section 6.2.3.2.4), which
+                                                         most poisoned TLP's should be. */
+        uint32_t ce_d                    : 1;       /**< Correctable Error Detected
+                                                          Errors are logged in this register regardless of whether
+                                                          error reporting is enabled in the Device Control register.
+                                                         CE_D is set if we receive any of the errors in PCIE_CFG068
+                                                         for example a Replay Timer Timeout.  Also, it can be set if
+                                                         we get any of the errors in PCIE_CFG066 that has a severity
+                                                         set to Nonfatal and meets the Advisory Nonfatal criteria
+                                                         (PCIe 1.1 spec, Section 6.2.3.2.4), which most ECRC errors
+                                                         should be. */
+        uint32_t reserved_15_15          : 1;
+        uint32_t mrrs                    : 3;       /**< Max Read Request Size
+                                                          0 = 128B
+                                                          1 = 256B
+                                                          2 = 512B
+                                                          3 = 1024B
+                                                          4 = 2048B
+                                                          5 = 4096B
+                                                         Note: NPEI_CTL_STATUS2[MRRS] also must be set properly.
+                                                         NPEI_CTL_STATUS2[MRRS] must not exceed the
+                                                         desired max read request size. */
+        uint32_t ns_en                   : 1;       /**< Enable No Snoop */
+        uint32_t ap_en                   : 1;       /**< AUX Power PM Enable */
+        uint32_t pf_en                   : 1;       /**< Phantom Function Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         phantom functions. */
+        uint32_t etf_en                  : 1;       /**< Extended Tag Field Enable
+                                                         This bit should never be set - OCTEON requests never use
+                                                         extended tags. */
+        uint32_t mps                     : 3;       /**< Max Payload Size
+                                                          Legal values:
+                                                           0  = 128B
+                                                           1  = 256B
+                                                          Larger sizes not supported.
+                                                         Note: Both PCI Express Ports must be set to the same value
+                                                               for Peer-to-Peer to function properly.
+                                                         Note: NPEI_CTL_STATUS2[MPS] must also be set to the same
+                                                               value for proper functionality. */
+        uint32_t ro_en                   : 1;       /**< Enable Relaxed Ordering */
+        uint32_t ur_en                   : 1;       /**< Unsupported Request Reporting Enable */
+        uint32_t fe_en                   : 1;       /**< Fatal Error Reporting Enable */
+        uint32_t nfe_en                  : 1;       /**< Non-Fatal Error Reporting Enable */
+        uint32_t ce_en                   : 1;       /**< Correctable Error Reporting Enable */
+#else
+        uint32_t ce_en                   : 1;
+        uint32_t nfe_en                  : 1;
+        uint32_t fe_en                   : 1;
+        uint32_t ur_en                   : 1;
+        uint32_t ro_en                   : 1;
+        uint32_t mps                     : 3;
+        uint32_t etf_en                  : 1;
+        uint32_t pf_en                   : 1;
+        uint32_t ap_en                   : 1;
+        uint32_t ns_en                   : 1;
+        uint32_t mrrs                    : 3;
+        uint32_t reserved_15_15          : 1;
+        uint32_t ce_d                    : 1;
+        uint32_t nfe_d                   : 1;
+        uint32_t fe_d                    : 1;
+        uint32_t ur_d                    : 1;
+        uint32_t ap_d                    : 1;
+        uint32_t tp                      : 1;
+        uint32_t reserved_22_31          : 10;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg030_s         cn52xx;
+    struct cvmx_pciercx_cfg030_s         cn52xxp1;
+    struct cvmx_pciercx_cfg030_s         cn56xx;
+    struct cvmx_pciercx_cfg030_s         cn56xxp1;
+} cvmx_pciercx_cfg030_t;
+
+
+/**
+ * cvmx_pcierc#_cfg031
+ *
+ * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space
+ * (Link Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg031_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t pnum                    : 8;       /**< Port Number, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t reserved_22_23          : 2;
+        uint32_t lbnc                    : 1;       /**< Link Bandwith Notification Capability */
+        uint32_t dllarc                  : 1;       /**< Data Link Layer Active Reporting Capable
+                                                         Set to 1 for Root Complex devices and 0 for Endpoint devices. */
+        uint32_t sderc                   : 1;       /**< Surprise Down Error Reporting Capable
+                                                         Not supported, hardwired to 0x0. */
+        uint32_t cpm                     : 1;       /**< Clock Power Management
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t l1el                    : 3;       /**< L1 Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t l0el                    : 3;       /**< L0s Exit Latency
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t aslpms                  : 2;       /**< Active State Link PM Support
+                                                         The default value is the value you specify during hardware
+                                                         configuration, writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t mlw                     : 6;       /**< Maximum Link Width
+                                                         The default value is the value you specify during hardware
+                                                         configuration (x1, x4, x8, or x16), writable through the DBI.
+                                                         The SW needs to set this to 0x8 or 0x4 depending on the max
+                                                         number of lanes (QLM_CFG == 0 set to 0x8 else 0x4). */
+        uint32_t mls                     : 4;       /**< Maximum Link Speed
+                                                         Default value is 0x1 for 2.5 Gbps Link.
+                                                         This field is writable through the DBI. However, 0x1 is the
+                                                         only supported value. Therefore, the application must not write
+                                                         any value other than 0x1 to this field. */
+#else
+        uint32_t mls                     : 4;
+        uint32_t mlw                     : 6;
+        uint32_t aslpms                  : 2;
+        uint32_t l0el                    : 3;
+        uint32_t l1el                    : 3;
+        uint32_t cpm                     : 1;
+        uint32_t sderc                   : 1;
+        uint32_t dllarc                  : 1;
+        uint32_t lbnc                    : 1;
+        uint32_t reserved_22_23          : 2;
+        uint32_t pnum                    : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg031_s         cn52xx;
+    struct cvmx_pciercx_cfg031_s         cn52xxp1;
+    struct cvmx_pciercx_cfg031_s         cn56xx;
+    struct cvmx_pciercx_cfg031_s         cn56xxp1;
+} cvmx_pciercx_cfg031_t;
+
+
+/**
+ * cvmx_pcierc#_cfg032
+ *
+ * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space
+ * (Link Control Register/Link Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg032_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lab                     : 1;       /**< Link Autonomous Bandwidth Status */
+        uint32_t lbm                     : 1;       /**< Link Bandwidth Management Status */
+        uint32_t dlla                    : 1;       /**< Data Link Layer Active */
+        uint32_t scc                     : 1;       /**< Slot Clock Configuration
+                                                         Indicates that the component uses the same physical reference
+                                                         clock that the platform provides on the connector. The default
+                                                         value is the value you select during hardware configuration,
+                                                         writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t lt                      : 1;       /**< Link Training */
+        uint32_t reserved_26_26          : 1;
+        uint32_t nlw                     : 6;       /**< Negotiated Link Width
+                                                         Set automatically by hardware after Link initialization. */
+        uint32_t ls                      : 4;       /**< Link Speed
+                                                         The negotiated Link speed: 2.5 Gbps */
+        uint32_t reserved_12_15          : 4;
+        uint32_t lab_int_enb             : 1;       /**< Link Autonomous Bandwidth Interrupt Enable
+                                                         This interrupt is for Gen2 and is not supported. This bit should
+                                                         always be written to zero. */
+        uint32_t lbm_int_enb             : 1;       /**< Link Bandwidth Management Interrupt Enable
+                                                         This interrupt is for Gen2 and is not supported. This bit should
+                                                         always be written to zero. */
+        uint32_t hawd                    : 1;       /**< Hardware Autonomous Width Disable
+                                                         (Not Supported) */
+        uint32_t ecpm                    : 1;       /**< Enable Clock Power Management
+                                                         Hardwired to 0 if Clock Power Management is disabled in
+                                                         the Link Capabilities register. */
+        uint32_t es                      : 1;       /**< Extended Synch */
+        uint32_t ccc                     : 1;       /**< Common Clock Configuration */
+        uint32_t rl                      : 1;       /**< Retrain Link */
+        uint32_t ld                      : 1;       /**< Link Disable */
+        uint32_t rcb                     : 1;       /**< Read Completion Boundary (RCB), writable through the DBI
+                                                         However, the application must not change this field
+                                                         because an RCB of 64 bytes is not supported. */
+        uint32_t reserved_2_2            : 1;
+        uint32_t aslpc                   : 2;       /**< Active State Link PM Control */
+#else
+        uint32_t aslpc                   : 2;
+        uint32_t reserved_2_2            : 1;
+        uint32_t rcb                     : 1;
+        uint32_t ld                      : 1;
+        uint32_t rl                      : 1;
+        uint32_t ccc                     : 1;
+        uint32_t es                      : 1;
+        uint32_t ecpm                    : 1;
+        uint32_t hawd                    : 1;
+        uint32_t lbm_int_enb             : 1;
+        uint32_t lab_int_enb             : 1;
+        uint32_t reserved_12_15          : 4;
+        uint32_t ls                      : 4;
+        uint32_t nlw                     : 6;
+        uint32_t reserved_26_26          : 1;
+        uint32_t lt                      : 1;
+        uint32_t scc                     : 1;
+        uint32_t dlla                    : 1;
+        uint32_t lbm                     : 1;
+        uint32_t lab                     : 1;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg032_s         cn52xx;
+    struct cvmx_pciercx_cfg032_s         cn52xxp1;
+    struct cvmx_pciercx_cfg032_s         cn56xx;
+    struct cvmx_pciercx_cfg032_s         cn56xxp1;
+} cvmx_pciercx_cfg032_t;
+
+
+/**
+ * cvmx_pcierc#_cfg033
+ *
+ * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space
+ * (Slot Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg033_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ps_num                  : 13;      /**< Physical Slot Number, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t nccs                    : 1;       /**< No Command Complete Support, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t emip                    : 1;       /**< Electromechanical Interlock Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t sp_ls                   : 2;       /**< Slot Power Limit Scale, writable through the DBI. */
+        uint32_t sp_lv                   : 8;       /**< Slot Power Limit Value, writable through the DBI. */
+        uint32_t hp_c                    : 1;       /**< Hot-Plug Capable, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t hp_s                    : 1;       /**< Hot-Plug Surprise, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t pip                     : 1;       /**< Power Indicator Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t aip                     : 1;       /**< Attention Indicator Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t mrlsp                   : 1;       /**< MRL Sensor Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t pcp                     : 1;       /**< Power Controller Present, writable through the DBI
+                                                         However, the application must not change this field. */
+        uint32_t abp                     : 1;       /**< Attention Button Present, writable through the DBI
+                                                         However, the application must not change this field. */
+#else
+        uint32_t abp                     : 1;
+        uint32_t pcp                     : 1;
+        uint32_t mrlsp                   : 1;
+        uint32_t aip                     : 1;
+        uint32_t pip                     : 1;
+        uint32_t hp_s                    : 1;
+        uint32_t hp_c                    : 1;
+        uint32_t sp_lv                   : 8;
+        uint32_t sp_ls                   : 2;
+        uint32_t emip                    : 1;
+        uint32_t nccs                    : 1;
+        uint32_t ps_num                  : 13;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg033_s         cn52xx;
+    struct cvmx_pciercx_cfg033_s         cn52xxp1;
+    struct cvmx_pciercx_cfg033_s         cn56xx;
+    struct cvmx_pciercx_cfg033_s         cn56xxp1;
+} cvmx_pciercx_cfg033_t;
+
+
+/**
+ * cvmx_pcierc#_cfg034
+ *
+ * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space
+ * (Slot Control Register/Slot Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg034_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_25_31          : 7;
+        uint32_t dlls_c                  : 1;       /**< Data Link Layer State Changed */
+        uint32_t emis                    : 1;       /**< Electromechanical Interlock Status */
+        uint32_t pds                     : 1;       /**< Presence Detect State */
+        uint32_t mrlss                   : 1;       /**< MRL Sensor State */
+        uint32_t ccint_d                 : 1;       /**< Command Completed */
+        uint32_t pd_c                    : 1;       /**< Presence Detect Changed */
+        uint32_t mrls_c                  : 1;       /**< MRL Sensor Changed */
+        uint32_t pf_d                    : 1;       /**< Power Fault Detected */
+        uint32_t abp_d                   : 1;       /**< Attention Button Pressed */
+        uint32_t reserved_13_15          : 3;
+        uint32_t dlls_en                 : 1;       /**< Data Link Layer State Changed Enable */
+        uint32_t emic                    : 1;       /**< Electromechanical Interlock Control */
+        uint32_t pcc                     : 1;       /**< Power Controller Control */
+        uint32_t pic                     : 2;       /**< Power Indicator Control */
+        uint32_t aic                     : 2;       /**< Attention Indicator Control */
+        uint32_t hpint_en                : 1;       /**< Hot-Plug Interrupt Enable */
+        uint32_t ccint_en                : 1;       /**< Command Completed Interrupt Enable */
+        uint32_t pd_en                   : 1;       /**< Presence Detect Changed Enable */
+        uint32_t mrls_en                 : 1;       /**< MRL Sensor Changed Enable */
+        uint32_t pf_en                   : 1;       /**< Power Fault Detected Enable */
+        uint32_t abp_en                  : 1;       /**< Attention Button Pressed Enable */
+#else
+        uint32_t abp_en                  : 1;
+        uint32_t pf_en                   : 1;
+        uint32_t mrls_en                 : 1;
+        uint32_t pd_en                   : 1;
+        uint32_t ccint_en                : 1;
+        uint32_t hpint_en                : 1;
+        uint32_t aic                     : 2;
+        uint32_t pic                     : 2;
+        uint32_t pcc                     : 1;
+        uint32_t emic                    : 1;
+        uint32_t dlls_en                 : 1;
+        uint32_t reserved_13_15          : 3;
+        uint32_t abp_d                   : 1;
+        uint32_t pf_d                    : 1;
+        uint32_t mrls_c                  : 1;
+        uint32_t pd_c                    : 1;
+        uint32_t ccint_d                 : 1;
+        uint32_t mrlss                   : 1;
+        uint32_t pds                     : 1;
+        uint32_t emis                    : 1;
+        uint32_t dlls_c                  : 1;
+        uint32_t reserved_25_31          : 7;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg034_s         cn52xx;
+    struct cvmx_pciercx_cfg034_s         cn52xxp1;
+    struct cvmx_pciercx_cfg034_s         cn56xx;
+    struct cvmx_pciercx_cfg034_s         cn56xxp1;
+} cvmx_pciercx_cfg034_t;
+
+
+/**
+ * cvmx_pcierc#_cfg035
+ *
+ * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space
+ * (Root Control Register/Root Capabilities Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg035_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_17_31          : 15;
+        uint32_t crssv                   : 1;       /**< CRS Software Visibility
+                                                         Not supported, hardwired to 0x0. */
+        uint32_t reserved_5_15           : 11;
+        uint32_t crssve                  : 1;       /**< CRS Software Visibility Enable
+                                                         Not supported, hardwired to 0x0. */
+        uint32_t pmeie                   : 1;       /**< PME Interrupt Enable */
+        uint32_t sefee                   : 1;       /**< System Error on Fatal Error Enable */
+        uint32_t senfee                  : 1;       /**< System Error on Non-fatal Error Enable */
+        uint32_t secee                   : 1;       /**< System Error on Correctable Error Enable */
+#else
+        uint32_t secee                   : 1;
+        uint32_t senfee                  : 1;
+        uint32_t sefee                   : 1;
+        uint32_t pmeie                   : 1;
+        uint32_t crssve                  : 1;
+        uint32_t reserved_5_15           : 11;
+        uint32_t crssv                   : 1;
+        uint32_t reserved_17_31          : 15;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg035_s         cn52xx;
+    struct cvmx_pciercx_cfg035_s         cn52xxp1;
+    struct cvmx_pciercx_cfg035_s         cn56xx;
+    struct cvmx_pciercx_cfg035_s         cn56xxp1;
+} cvmx_pciercx_cfg035_t;
+
+
+/**
+ * cvmx_pcierc#_cfg036
+ *
+ * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space
+ * (Root Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg036_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_18_31          : 14;
+        uint32_t pme_pend                : 1;       /**< PME Pending */
+        uint32_t pme_stat                : 1;       /**< PME Status */
+        uint32_t pme_rid                 : 16;      /**< PME Requester ID */
+#else
+        uint32_t pme_rid                 : 16;
+        uint32_t pme_stat                : 1;
+        uint32_t pme_pend                : 1;
+        uint32_t reserved_18_31          : 14;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg036_s         cn52xx;
+    struct cvmx_pciercx_cfg036_s         cn52xxp1;
+    struct cvmx_pciercx_cfg036_s         cn56xx;
+    struct cvmx_pciercx_cfg036_s         cn56xxp1;
+} cvmx_pciercx_cfg036_t;
+
+
+/**
+ * cvmx_pcierc#_cfg037
+ *
+ * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space
+ * (Device Capabilities 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg037_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t ctds                    : 1;       /**< Completion Timeout Disable Supported */
+        uint32_t ctrs                    : 4;       /**< Completion Timeout Ranges Supported
+                                                         Value of 0 indicates that Completion Timeout Programming
+                                                         is not supported.
+                                                         Completion timeout is 16.7ms. */
+#else
+        uint32_t ctrs                    : 4;
+        uint32_t ctds                    : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg037_s         cn52xx;
+    struct cvmx_pciercx_cfg037_s         cn52xxp1;
+    struct cvmx_pciercx_cfg037_s         cn56xx;
+    struct cvmx_pciercx_cfg037_s         cn56xxp1;
+} cvmx_pciercx_cfg037_t;
+
+
+/**
+ * cvmx_pcierc#_cfg038
+ *
+ * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space
+ * (Device Control 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg038_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t ctd                     : 1;       /**< Completion Timeout Disable */
+        uint32_t ctv                     : 4;       /**< Completion Timeout Value
+                                                         Completion Timeout Programming is not supported
+                                                         Completion timeout is 16.7ms. */
+#else
+        uint32_t ctv                     : 4;
+        uint32_t ctd                     : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg038_s         cn52xx;
+    struct cvmx_pciercx_cfg038_s         cn52xxp1;
+    struct cvmx_pciercx_cfg038_s         cn56xx;
+    struct cvmx_pciercx_cfg038_s         cn56xxp1;
+} cvmx_pciercx_cfg038_t;
+
+
+/**
+ * cvmx_pcierc#_cfg039
+ *
+ * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space
+ * (Link Capabilities 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg039_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg039_s         cn52xx;
+    struct cvmx_pciercx_cfg039_s         cn52xxp1;
+    struct cvmx_pciercx_cfg039_s         cn56xx;
+    struct cvmx_pciercx_cfg039_s         cn56xxp1;
+} cvmx_pciercx_cfg039_t;
+
+
+/**
+ * cvmx_pcierc#_cfg040
+ *
+ * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space
+ * (Link Control 2 Register/Link Status 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg040_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg040_s         cn52xx;
+    struct cvmx_pciercx_cfg040_s         cn52xxp1;
+    struct cvmx_pciercx_cfg040_s         cn56xx;
+    struct cvmx_pciercx_cfg040_s         cn56xxp1;
+} cvmx_pciercx_cfg040_t;
+
+
+/**
+ * cvmx_pcierc#_cfg041
+ *
+ * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space
+ * (Slot Capabilities 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg041_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg041_s         cn52xx;
+    struct cvmx_pciercx_cfg041_s         cn52xxp1;
+    struct cvmx_pciercx_cfg041_s         cn56xx;
+    struct cvmx_pciercx_cfg041_s         cn56xxp1;
+} cvmx_pciercx_cfg041_t;
+
+
+/**
+ * cvmx_pcierc#_cfg042
+ *
+ * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space
+ * (Slot Control 2 Register/Slot Status 2 Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg042_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_0_31           : 32;
+#else
+        uint32_t reserved_0_31           : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg042_s         cn52xx;
+    struct cvmx_pciercx_cfg042_s         cn52xxp1;
+    struct cvmx_pciercx_cfg042_s         cn56xx;
+    struct cvmx_pciercx_cfg042_s         cn56xxp1;
+} cvmx_pciercx_cfg042_t;
+
+
+/**
+ * cvmx_pcierc#_cfg064
+ *
+ * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space
+ * (PCI Express Enhanced Capability Header)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg064_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t nco                     : 12;      /**< Next Capability Offset */
+        uint32_t cv                      : 4;       /**< Capability Version */
+        uint32_t pcieec                  : 16;      /**< PCIE Express Extended Capability */
+#else
+        uint32_t pcieec                  : 16;
+        uint32_t cv                      : 4;
+        uint32_t nco                     : 12;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg064_s         cn52xx;
+    struct cvmx_pciercx_cfg064_s         cn52xxp1;
+    struct cvmx_pciercx_cfg064_s         cn56xx;
+    struct cvmx_pciercx_cfg064_s         cn56xxp1;
+} cvmx_pciercx_cfg064_t;
+
+
+/**
+ * cvmx_pcierc#_cfg065
+ *
+ * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space
+ * (Uncorrectable Error Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg065_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t ures                    : 1;       /**< Unsupported Request Error Status */
+        uint32_t ecrces                  : 1;       /**< ECRC Error Status */
+        uint32_t mtlps                   : 1;       /**< Malformed TLP Status */
+        uint32_t ros                     : 1;       /**< Receiver Overflow Status */
+        uint32_t ucs                     : 1;       /**< Unexpected Completion Status */
+        uint32_t cas                     : 1;       /**< Completer Abort Status */
+        uint32_t cts                     : 1;       /**< Completion Timeout Status */
+        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Status */
+        uint32_t ptlps                   : 1;       /**< Poisoned TLP Status */
+        uint32_t reserved_6_11           : 6;
+        uint32_t sdes                    : 1;       /**< Surprise Down Error Status (not supported) */
+        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Status */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t dlpes                   : 1;
+        uint32_t sdes                    : 1;
+        uint32_t reserved_6_11           : 6;
+        uint32_t ptlps                   : 1;
+        uint32_t fcpes                   : 1;
+        uint32_t cts                     : 1;
+        uint32_t cas                     : 1;
+        uint32_t ucs                     : 1;
+        uint32_t ros                     : 1;
+        uint32_t mtlps                   : 1;
+        uint32_t ecrces                  : 1;
+        uint32_t ures                    : 1;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg065_s         cn52xx;
+    struct cvmx_pciercx_cfg065_s         cn52xxp1;
+    struct cvmx_pciercx_cfg065_s         cn56xx;
+    struct cvmx_pciercx_cfg065_s         cn56xxp1;
+} cvmx_pciercx_cfg065_t;
+
+
+/**
+ * cvmx_pcierc#_cfg066
+ *
+ * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space
+ * (Uncorrectable Error Mask Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg066_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t urem                    : 1;       /**< Unsupported Request Error Mask */
+        uint32_t ecrcem                  : 1;       /**< ECRC Error Mask */
+        uint32_t mtlpm                   : 1;       /**< Malformed TLP Mask */
+        uint32_t rom                     : 1;       /**< Receiver Overflow Mask */
+        uint32_t ucm                     : 1;       /**< Unexpected Completion Mask */
+        uint32_t cam                     : 1;       /**< Completer Abort Mask */
+        uint32_t ctm                     : 1;       /**< Completion Timeout Mask */
+        uint32_t fcpem                   : 1;       /**< Flow Control Protocol Error Mask */
+        uint32_t ptlpm                   : 1;       /**< Poisoned TLP Mask */
+        uint32_t reserved_6_11           : 6;
+        uint32_t sdem                    : 1;       /**< Surprise Down Error Mask (not supported) */
+        uint32_t dlpem                   : 1;       /**< Data Link Protocol Error Mask */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t dlpem                   : 1;
+        uint32_t sdem                    : 1;
+        uint32_t reserved_6_11           : 6;
+        uint32_t ptlpm                   : 1;
+        uint32_t fcpem                   : 1;
+        uint32_t ctm                     : 1;
+        uint32_t cam                     : 1;
+        uint32_t ucm                     : 1;
+        uint32_t rom                     : 1;
+        uint32_t mtlpm                   : 1;
+        uint32_t ecrcem                  : 1;
+        uint32_t urem                    : 1;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg066_s         cn52xx;
+    struct cvmx_pciercx_cfg066_s         cn52xxp1;
+    struct cvmx_pciercx_cfg066_s         cn56xx;
+    struct cvmx_pciercx_cfg066_s         cn56xxp1;
+} cvmx_pciercx_cfg066_t;
+
+
+/**
+ * cvmx_pcierc#_cfg067
+ *
+ * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space
+ * (Uncorrectable Error Severity Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg067_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t ures                    : 1;       /**< Unsupported Request Error Severity */
+        uint32_t ecrces                  : 1;       /**< ECRC Error Severity */
+        uint32_t mtlps                   : 1;       /**< Malformed TLP Severity */
+        uint32_t ros                     : 1;       /**< Receiver Overflow Severity */
+        uint32_t ucs                     : 1;       /**< Unexpected Completion Severity */
+        uint32_t cas                     : 1;       /**< Completer Abort Severity */
+        uint32_t cts                     : 1;       /**< Completion Timeout Severity */
+        uint32_t fcpes                   : 1;       /**< Flow Control Protocol Error Severity */
+        uint32_t ptlps                   : 1;       /**< Poisoned TLP Severity */
+        uint32_t reserved_6_11           : 6;
+        uint32_t sdes                    : 1;       /**< Surprise Down Error Severity (not supported) */
+        uint32_t dlpes                   : 1;       /**< Data Link Protocol Error Severity */
+        uint32_t reserved_0_3            : 4;
+#else
+        uint32_t reserved_0_3            : 4;
+        uint32_t dlpes                   : 1;
+        uint32_t sdes                    : 1;
+        uint32_t reserved_6_11           : 6;
+        uint32_t ptlps                   : 1;
+        uint32_t fcpes                   : 1;
+        uint32_t cts                     : 1;
+        uint32_t cas                     : 1;
+        uint32_t ucs                     : 1;
+        uint32_t ros                     : 1;
+        uint32_t mtlps                   : 1;
+        uint32_t ecrces                  : 1;
+        uint32_t ures                    : 1;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg067_s         cn52xx;
+    struct cvmx_pciercx_cfg067_s         cn52xxp1;
+    struct cvmx_pciercx_cfg067_s         cn56xx;
+    struct cvmx_pciercx_cfg067_s         cn56xxp1;
+} cvmx_pciercx_cfg067_t;
+
+
+/**
+ * cvmx_pcierc#_cfg068
+ *
+ * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space
+ * (Correctable Error Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg068_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_14_31          : 18;
+        uint32_t anfes                   : 1;       /**< Advisory Non-Fatal Error Status */
+        uint32_t rtts                    : 1;       /**< Replay Timer Timeout Status */
+        uint32_t reserved_9_11           : 3;
+        uint32_t rnrs                    : 1;       /**< REPLAY_NUM Rollover Status */
+        uint32_t bdllps                  : 1;       /**< Bad DLLP Status */
+        uint32_t btlps                   : 1;       /**< Bad TLP Status */
+        uint32_t reserved_1_5            : 5;
+        uint32_t res                     : 1;       /**< Receiver Error Status */
+#else
+        uint32_t res                     : 1;
+        uint32_t reserved_1_5            : 5;
+        uint32_t btlps                   : 1;
+        uint32_t bdllps                  : 1;
+        uint32_t rnrs                    : 1;
+        uint32_t reserved_9_11           : 3;
+        uint32_t rtts                    : 1;
+        uint32_t anfes                   : 1;
+        uint32_t reserved_14_31          : 18;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg068_s         cn52xx;
+    struct cvmx_pciercx_cfg068_s         cn52xxp1;
+    struct cvmx_pciercx_cfg068_s         cn56xx;
+    struct cvmx_pciercx_cfg068_s         cn56xxp1;
+} cvmx_pciercx_cfg068_t;
+
+
+/**
+ * cvmx_pcierc#_cfg069
+ *
+ * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space
+ * (Correctable Error Mask Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg069_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_14_31          : 18;
+        uint32_t anfem                   : 1;       /**< Advisory Non-Fatal Error Mask */
+        uint32_t rttm                    : 1;       /**< Replay Timer Timeout Mask */
+        uint32_t reserved_9_11           : 3;
+        uint32_t rnrm                    : 1;       /**< REPLAY_NUM Rollover Mask */
+        uint32_t bdllpm                  : 1;       /**< Bad DLLP Mask */
+        uint32_t btlpm                   : 1;       /**< Bad TLP Mask */
+        uint32_t reserved_1_5            : 5;
+        uint32_t rem                     : 1;       /**< Receiver Error Mask */
+#else
+        uint32_t rem                     : 1;
+        uint32_t reserved_1_5            : 5;
+        uint32_t btlpm                   : 1;
+        uint32_t bdllpm                  : 1;
+        uint32_t rnrm                    : 1;
+        uint32_t reserved_9_11           : 3;
+        uint32_t rttm                    : 1;
+        uint32_t anfem                   : 1;
+        uint32_t reserved_14_31          : 18;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg069_s         cn52xx;
+    struct cvmx_pciercx_cfg069_s         cn52xxp1;
+    struct cvmx_pciercx_cfg069_s         cn56xx;
+    struct cvmx_pciercx_cfg069_s         cn56xxp1;
+} cvmx_pciercx_cfg069_t;
+
+
+/**
+ * cvmx_pcierc#_cfg070
+ *
+ * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space
+ * (Advanced Capabilities and Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg070_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_9_31           : 23;
+        uint32_t ce                      : 1;       /**< ECRC Check Enable */
+        uint32_t cc                      : 1;       /**< ECRC Check Capable */
+        uint32_t ge                      : 1;       /**< ECRC Generation Enable */
+        uint32_t gc                      : 1;       /**< ECRC Generation Capability */
+        uint32_t fep                     : 5;       /**< First Error Pointer */
+#else
+        uint32_t fep                     : 5;
+        uint32_t gc                      : 1;
+        uint32_t ge                      : 1;
+        uint32_t cc                      : 1;
+        uint32_t ce                      : 1;
+        uint32_t reserved_9_31           : 23;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg070_s         cn52xx;
+    struct cvmx_pciercx_cfg070_s         cn52xxp1;
+    struct cvmx_pciercx_cfg070_s         cn56xx;
+    struct cvmx_pciercx_cfg070_s         cn56xxp1;
+} cvmx_pciercx_cfg070_t;
+
+
+/**
+ * cvmx_pcierc#_cfg071
+ *
+ * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 1)
+ * 
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg071_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword1                  : 32;      /**< Header Log Register (first DWORD) */
+#else
+        uint32_t dword1                  : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg071_s         cn52xx;
+    struct cvmx_pciercx_cfg071_s         cn52xxp1;
+    struct cvmx_pciercx_cfg071_s         cn56xx;
+    struct cvmx_pciercx_cfg071_s         cn56xxp1;
+} cvmx_pciercx_cfg071_t;
+
+
+/**
+ * cvmx_pcierc#_cfg072
+ *
+ * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 2)
+ * 
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg072_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword2                  : 32;      /**< Header Log Register (second DWORD) */
+#else
+        uint32_t dword2                  : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg072_s         cn52xx;
+    struct cvmx_pciercx_cfg072_s         cn52xxp1;
+    struct cvmx_pciercx_cfg072_s         cn56xx;
+    struct cvmx_pciercx_cfg072_s         cn56xxp1;
+} cvmx_pciercx_cfg072_t;
+
+
+/**
+ * cvmx_pcierc#_cfg073
+ *
+ * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 3)
+ * 
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg073_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword3                  : 32;      /**< Header Log Register (third DWORD) */
+#else
+        uint32_t dword3                  : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg073_s         cn52xx;
+    struct cvmx_pciercx_cfg073_s         cn52xxp1;
+    struct cvmx_pciercx_cfg073_s         cn56xx;
+    struct cvmx_pciercx_cfg073_s         cn56xxp1;
+} cvmx_pciercx_cfg073_t;
+
+
+/**
+ * cvmx_pcierc#_cfg074
+ *
+ * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space
+ *                  (Header Log Register 4)
+ * 
+ * The Header Log registers collect the header for the TLP corresponding to a detected error.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg074_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dword4                  : 32;      /**< Header Log Register (fourth DWORD) */
+#else
+        uint32_t dword4                  : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg074_s         cn52xx;
+    struct cvmx_pciercx_cfg074_s         cn52xxp1;
+    struct cvmx_pciercx_cfg074_s         cn56xx;
+    struct cvmx_pciercx_cfg074_s         cn56xxp1;
+} cvmx_pciercx_cfg074_t;
+
+
+/**
+ * cvmx_pcierc#_cfg075
+ *
+ * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space
+ * (Root Error Command Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg075_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_3_31           : 29;
+        uint32_t fere                    : 1;       /**< Fatal Error Reporting Enable */
+        uint32_t nfere                   : 1;       /**< Non-Fatal Error Reporting Enable */
+        uint32_t cere                    : 1;       /**< Correctable Error Reporting Enable */
+#else
+        uint32_t cere                    : 1;
+        uint32_t nfere                   : 1;
+        uint32_t fere                    : 1;
+        uint32_t reserved_3_31           : 29;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg075_s         cn52xx;
+    struct cvmx_pciercx_cfg075_s         cn52xxp1;
+    struct cvmx_pciercx_cfg075_s         cn56xx;
+    struct cvmx_pciercx_cfg075_s         cn56xxp1;
+} cvmx_pciercx_cfg075_t;
+
+
+/**
+ * cvmx_pcierc#_cfg076
+ *
+ * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space
+ * (Root Error Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg076_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t aeimn                   : 5;       /**< Advanced Error Interrupt Message Number,
+                                                         writable through the DBI */
+        uint32_t reserved_7_26           : 20;
+        uint32_t femr                    : 1;       /**< Fatal Error Messages Received */
+        uint32_t nfemr                   : 1;       /**< Non-Fatal Error Messages Received */
+        uint32_t fuf                     : 1;       /**< First Uncorrectable Fatal */
+        uint32_t multi_efnfr             : 1;       /**< Multiple ERR_FATAL/NONFATAL Received */
+        uint32_t efnfr                   : 1;       /**< ERR_FATAL/NONFATAL Received */
+        uint32_t multi_ecr               : 1;       /**< Multiple ERR_COR Received */
+        uint32_t ecr                     : 1;       /**< ERR_COR Received */
+#else
+        uint32_t ecr                     : 1;
+        uint32_t multi_ecr               : 1;
+        uint32_t efnfr                   : 1;
+        uint32_t multi_efnfr             : 1;
+        uint32_t fuf                     : 1;
+        uint32_t nfemr                   : 1;
+        uint32_t femr                    : 1;
+        uint32_t reserved_7_26           : 20;
+        uint32_t aeimn                   : 5;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg076_s         cn52xx;
+    struct cvmx_pciercx_cfg076_s         cn52xxp1;
+    struct cvmx_pciercx_cfg076_s         cn56xx;
+    struct cvmx_pciercx_cfg076_s         cn56xxp1;
+} cvmx_pciercx_cfg076_t;
+
+
+/**
+ * cvmx_pcierc#_cfg077
+ *
+ * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space
+ * (Error Source Identification Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg077_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t efnfsi                  : 16;      /**< ERR_FATAL/NONFATAL Source Identification */
+        uint32_t ecsi                    : 16;      /**< ERR_COR Source Identification */
+#else
+        uint32_t ecsi                    : 16;
+        uint32_t efnfsi                  : 16;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg077_s         cn52xx;
+    struct cvmx_pciercx_cfg077_s         cn52xxp1;
+    struct cvmx_pciercx_cfg077_s         cn56xx;
+    struct cvmx_pciercx_cfg077_s         cn56xxp1;
+} cvmx_pciercx_cfg077_t;
+
+
+/**
+ * cvmx_pcierc#_cfg448
+ *
+ * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space
+ * (Ack Latency Timer and Replay Timer Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg448_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t rtl                     : 16;      /**< Replay Time Limit
+                                                         The replay timer expires when it reaches this limit. The PCI
+                                                         Express bus initiates a replay upon reception of a Nak or when
+                                                         the replay timer expires.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+        uint32_t rtltl                   : 16;      /**< Round Trip Latency Time Limit
+                                                         The Ack/Nak latency timer expires when it reaches this limit.
+                                                         The default is then updated based on the Negotiated Link Width
+                                                         and Max_Payload_Size. */
+#else
+        uint32_t rtltl                   : 16;
+        uint32_t rtl                     : 16;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg448_s         cn52xx;
+    struct cvmx_pciercx_cfg448_s         cn52xxp1;
+    struct cvmx_pciercx_cfg448_s         cn56xx;
+    struct cvmx_pciercx_cfg448_s         cn56xxp1;
+} cvmx_pciercx_cfg448_t;
+
+
+/**
+ * cvmx_pcierc#_cfg449
+ *
+ * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space
+ * (Other Message Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg449_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t omr                     : 32;      /**< Other Message Register
+                                                         This register can be used for either of the following purposes:
+                                                         o To send a specific PCI Express Message, the application
+                                                           writes the payload of the Message into this register, then
+                                                           sets bit 0 of the Port Link Control Register to send the
+                                                           Message.
+                                                         o To store a corruption pattern for corrupting the LCRC on all
+                                                           TLPs, the application places a 32-bit corruption pattern into
+                                                           this register and enables this function by setting bit 25 of
+                                                           the Port Link Control Register. When enabled, the transmit
+                                                           LCRC result is XOR'd with this pattern before inserting
+                                                           it into the packet. */
+#else
+        uint32_t omr                     : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg449_s         cn52xx;
+    struct cvmx_pciercx_cfg449_s         cn52xxp1;
+    struct cvmx_pciercx_cfg449_s         cn56xx;
+    struct cvmx_pciercx_cfg449_s         cn56xxp1;
+} cvmx_pciercx_cfg449_t;
+
+
+/**
+ * cvmx_pcierc#_cfg450
+ *
+ * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space
+ * (Port Force Link Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg450_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t lpec                    : 8;       /**< Low Power Entrance Count
+                                                         The Power Management state will wait for this many clock cycles
+                                                         for the associated completion of a CfgWr to PCIE_CFG017 register
+                                                         Power State (PS) field register to go low-power. This register
+                                                         is intended for applications that do not let the PCI Express
+                                                         bus handle a completion for configuration request to the
+                                                         Power Management Control and Status (PCIE_CFG017) register. */
+        uint32_t reserved_22_23          : 2;
+        uint32_t link_state              : 6;       /**< Link State
+                                                         The Link state that the PCI Express Bus will be forced to
+                                                         when bit 15 (Force Link) is set.
+                                                         State encoding:
+                                                         o DETECT_QUIET              00h
+                                                         o DETECT_ACT                01h
+                                                         o POLL_ACTIVE               02h
+                                                         o POLL_COMPLIANCE           03h
+                                                         o POLL_CONFIG               04h
+                                                         o PRE_DETECT_QUIET          05h
+                                                         o DETECT_WAIT               06h
+                                                         o CFG_LINKWD_START          07h
+                                                         o CFG_LINKWD_ACEPT          08h
+                                                         o CFG_LANENUM_WAIT          09h
+                                                         o CFG_LANENUM_ACEPT         0Ah
+                                                         o CFG_COMPLETE              0Bh
+                                                         o CFG_IDLE                  0Ch
+                                                         o RCVRY_LOCK                0Dh
+                                                         o RCVRY_SPEED               0Eh
+                                                         o RCVRY_RCVRCFG             0Fh
+                                                         o RCVRY_IDLE                10h
+                                                         o L0                        11h
+                                                         o L0S                       12h
+                                                         o L123_SEND_EIDLE           13h
+                                                         o L1_IDLE                   14h
+                                                         o L2_IDLE                   15h
+                                                         o L2_WAKE                   16h
+                                                         o DISABLED_ENTRY            17h
+                                                         o DISABLED_IDLE             18h
+                                                         o DISABLED                  19h
+                                                         o LPBK_ENTRY                1Ah
+                                                         o LPBK_ACTIVE               1Bh
+                                                         o LPBK_EXIT                 1Ch
+                                                         o LPBK_EXIT_TIMEOUT         1Dh
+                                                         o HOT_RESET_ENTRY           1Eh
+                                                         o HOT_RESET                 1Fh */
+        uint32_t force_link              : 1;       /**< Force Link
+                                                         Forces the Link to the state specified by the Link State field.
+                                                         The Force Link pulse will trigger Link re-negotiation.
+                                                         * As the The Force Link is a pulse, writing a 1 to it does
+                                                           trigger the forced link state event, even thought reading it
+                                                           always returns a 0. */
+        uint32_t reserved_8_14           : 7;
+        uint32_t link_num                : 8;       /**< Link Number */
+#else
+        uint32_t link_num                : 8;
+        uint32_t reserved_8_14           : 7;
+        uint32_t force_link              : 1;
+        uint32_t link_state              : 6;
+        uint32_t reserved_22_23          : 2;
+        uint32_t lpec                    : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg450_s         cn52xx;
+    struct cvmx_pciercx_cfg450_s         cn52xxp1;
+    struct cvmx_pciercx_cfg450_s         cn56xx;
+    struct cvmx_pciercx_cfg450_s         cn56xxp1;
+} cvmx_pciercx_cfg450_t;
+
+
+/**
+ * cvmx_pcierc#_cfg451
+ *
+ * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space
+ * (Ack Frequency Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg451_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t l1el                    : 3;       /**< L1 Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 4 ms
+                                                         o 011: 8 ms
+                                                         o 100: 16 ms
+                                                         o 101: 32 ms
+                                                         o 110 or 111: 64 ms */
+        uint32_t l0el                    : 3;       /**< L0s Entrance Latency
+                                                         Values correspond to:
+                                                         o 000: 1 ms
+                                                         o 001: 2 ms
+                                                         o 010: 3 ms
+                                                         o 011: 4 ms
+                                                         o 100: 5 ms
+                                                         o 101: 6 ms
+                                                         o 110 or 111: 7 ms */
+        uint32_t n_fts_cc                : 8;       /**< N_FTS when common clock is used.
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                          Note: The core does not support a value of zero; a value of
+                                                                zero can cause the LTSSM to go into the recovery state
+                                                                when exiting from L0s. */
+        uint32_t n_fts                   : 8;       /**< N_FTS
+                                                         The number of Fast Training Sequence ordered sets to be
+                                                         transmitted when transitioning from L0s to L0. The maximum
+                                                         number of FTS ordered-sets that a component can request is 255.
+                                                         Note: The core does not support a value of zero; a value of
+                                                               zero can cause the LTSSM to go into the recovery state
+                                                               when exiting from L0s. */
+        uint32_t ack_freq                : 8;       /**< Ack Frequency
+                                                         The number of pending Ack's specified here (up to 255) before
+                                                         sending an Ack. */
+#else
+        uint32_t ack_freq                : 8;
+        uint32_t n_fts                   : 8;
+        uint32_t n_fts_cc                : 8;
+        uint32_t l0el                    : 3;
+        uint32_t l1el                    : 3;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg451_s         cn52xx;
+    struct cvmx_pciercx_cfg451_s         cn52xxp1;
+    struct cvmx_pciercx_cfg451_s         cn56xx;
+    struct cvmx_pciercx_cfg451_s         cn56xxp1;
+} cvmx_pciercx_cfg451_t;
+
+
+/**
+ * cvmx_pcierc#_cfg452
+ *
+ * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space
+ * (Port Link Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg452_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t eccrc                   : 1;       /**< Enable Corrupted CRC
+                                                         Causes corrupt LCRC for TLPs when set,
+                                                         using the pattern contained in the Other Message register.
+                                                         This is a test feature, not to be used in normal operation. */
+        uint32_t reserved_22_24          : 3;
+        uint32_t lme                     : 6;       /**< Link Mode Enable
+                                                         o 000001: x1
+                                                         o 000011: x2
+                                                         o 000111: x4
+                                                         o 001111: x8
+                                                         o 011111: x16 (not supported)
+                                                         o 111111: x32 (not supported)
+                                                         This field indicates the MAXIMUM number of lanes supported
+                                                         by the PCIe port. It is normally set to 0xF or 0x7 depending
+                                                         on the value of the QLM_CFG bits (0xF when QLM_CFG == 0
+                                                         otherwise 0x7). The value can be set less than 0xF or 0x7
+                                                         to limit the number of lanes the PCIe will attempt to use.
+                                                         The programming of this field needs to be done by SW BEFORE
+                                                         enabling the link. See also MLW.
+                                                         (Note: The value of this field does NOT indicate the number
+                                                          of lanes in use by the PCIe. LME sets the max number of lanes
+                                                          in the PCIe core that COULD be used. As per the PCIe specs,
+                                                          the PCIe core can negotiate a smaller link width, so all
+                                                          of x8, x4, x2, and x1 are supported when LME=0xF,
+                                                          for example.) */
+        uint32_t reserved_8_15           : 8;
+        uint32_t flm                     : 1;       /**< Fast Link Mode
+                                                         Sets all internal timers to fast mode for simulation purposes. */
+        uint32_t reserved_6_6            : 1;
+        uint32_t dllle                   : 1;       /**< DLL Link Enable
+                                                         Enables Link initialization. If DLL Link Enable = 0, the PCI
+                                                         Express bus does not transmit InitFC DLLPs and does not
+                                                         establish a Link. */
+        uint32_t reserved_4_4            : 1;
+        uint32_t ra                      : 1;       /**< Reset Assert
+                                                         Triggers a recovery and forces the LTSSM to the Hot Reset
+                                                         state (downstream port only). */
+        uint32_t le                      : 1;       /**< Loopback Enable
+                                                         Turns on loopback. */
+        uint32_t sd                      : 1;       /**< Scramble Disable
+                                                         Turns off data scrambling. */
+        uint32_t omr                     : 1;       /**< Other Message Request
+                                                         When software writes a `1' to this bit, the PCI Express bus
+                                                         transmits the Message contained in the Other Message register. */
+#else
+        uint32_t omr                     : 1;
+        uint32_t sd                      : 1;
+        uint32_t le                      : 1;
+        uint32_t ra                      : 1;
+        uint32_t reserved_4_4            : 1;
+        uint32_t dllle                   : 1;
+        uint32_t reserved_6_6            : 1;
+        uint32_t flm                     : 1;
+        uint32_t reserved_8_15           : 8;
+        uint32_t lme                     : 6;
+        uint32_t reserved_22_24          : 3;
+        uint32_t eccrc                   : 1;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg452_s         cn52xx;
+    struct cvmx_pciercx_cfg452_s         cn52xxp1;
+    struct cvmx_pciercx_cfg452_s         cn56xx;
+    struct cvmx_pciercx_cfg452_s         cn56xxp1;
+} cvmx_pciercx_cfg452_t;
+
+
+/**
+ * cvmx_pcierc#_cfg453
+ *
+ * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space
+ * (Lane Skew Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg453_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dlld                    : 1;       /**< Disable Lane-to-Lane Deskew
+                                                         Disables the internal Lane-to-Lane deskew logic. */
+        uint32_t reserved_26_30          : 5;
+        uint32_t ack_nak                 : 1;       /**< Ack/Nak Disable
+                                                         Prevents the PCI Express bus from sending Ack and Nak DLLPs. */
+        uint32_t fcd                     : 1;       /**< Flow Control Disable
+                                                         Prevents the PCI Express bus from sending FC DLLPs. */
+        uint32_t ilst                    : 24;      /**< Insert Lane Skew for Transmit (not supported for x16)
+                                                         Causes skew between lanes for test purposes. There are three
+                                                         bits per Lane. The value is in units of one symbol time. For
+                                                         example, the value 010b for a Lane forces a skew of two symbol
+                                                         times for that Lane. The maximum skew value for any Lane is 5
+                                                         symbol times. */
+#else
+        uint32_t ilst                    : 24;
+        uint32_t fcd                     : 1;
+        uint32_t ack_nak                 : 1;
+        uint32_t reserved_26_30          : 5;
+        uint32_t dlld                    : 1;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg453_s         cn52xx;
+    struct cvmx_pciercx_cfg453_s         cn52xxp1;
+    struct cvmx_pciercx_cfg453_s         cn56xx;
+    struct cvmx_pciercx_cfg453_s         cn56xxp1;
+} cvmx_pciercx_cfg453_t;
+
+
+/**
+ * cvmx_pcierc#_cfg454
+ *
+ * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space
+ * (Symbol Number Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg454_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_29_31          : 3;
+        uint32_t tmfcwt                  : 5;       /**< Timer Modifier for Flow Control Watchdog Timer
+                                                         Increases the timer value for the Flow Control watchdog timer,
+                                                         in increments of 16 clock cycles. */
+        uint32_t tmanlt                  : 5;       /**< Timer Modifier for Ack/Nak Latency Timer
+                                                         Increases the timer value for the Ack/Nak latency timer, in
+                                                         increments of 64 clock cycles. */
+        uint32_t tmrt                    : 5;       /**< Timer Modifier for Replay Timer
+                                                         Increases the timer value for the replay timer, in increments
+                                                         of 64 clock cycles. */
+        uint32_t reserved_11_13          : 3;
+        uint32_t nskps                   : 3;       /**< Number of SKP Symbols */
+        uint32_t reserved_4_7            : 4;
+        uint32_t ntss                    : 4;       /**< Number of TS Symbols
+                                                         Sets the number of TS identifier symbols that are sent in TS1
+                                                         and TS2 ordered sets. */
+#else
+        uint32_t ntss                    : 4;
+        uint32_t reserved_4_7            : 4;
+        uint32_t nskps                   : 3;
+        uint32_t reserved_11_13          : 3;
+        uint32_t tmrt                    : 5;
+        uint32_t tmanlt                  : 5;
+        uint32_t tmfcwt                  : 5;
+        uint32_t reserved_29_31          : 3;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg454_s         cn52xx;
+    struct cvmx_pciercx_cfg454_s         cn52xxp1;
+    struct cvmx_pciercx_cfg454_s         cn56xx;
+    struct cvmx_pciercx_cfg454_s         cn56xxp1;
+} cvmx_pciercx_cfg454_t;
+
+
+/**
+ * cvmx_pcierc#_cfg455
+ *
+ * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space
+ * (Symbol Timer Register/Filter Mask Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg455_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t m_cfg0_filt             : 1;       /**< Mask filtering of received Configuration Requests (RC mode only) */
+        uint32_t m_io_filt               : 1;       /**< Mask filtering of received I/O Requests (RC mode only) */
+        uint32_t msg_ctrl                : 1;       /**< Message Control
+                                                         The application must not change this field. */
+        uint32_t m_cpl_ecrc_filt         : 1;       /**< Mask ECRC error filtering for Completions */
+        uint32_t m_ecrc_filt             : 1;       /**< Mask ECRC error filtering */
+        uint32_t m_cpl_len_err           : 1;       /**< Mask Length mismatch error for received Completions */
+        uint32_t m_cpl_attr_err          : 1;       /**< Mask Attributes mismatch error for received Completions */
+        uint32_t m_cpl_tc_err            : 1;       /**< Mask Traffic Class mismatch error for received Completions */
+        uint32_t m_cpl_fun_err           : 1;       /**< Mask function mismatch error for received Completions */
+        uint32_t m_cpl_rid_err           : 1;       /**< Mask Requester ID mismatch error for received Completions */
+        uint32_t m_cpl_tag_err           : 1;       /**< Mask Tag error rules for received Completions */
+        uint32_t m_lk_filt               : 1;       /**< Mask Locked Request filtering */
+        uint32_t m_cfg1_filt             : 1;       /**< Mask Type 1 Configuration Request filtering */
+        uint32_t m_bar_match             : 1;       /**< Mask BAR match filtering */
+        uint32_t m_pois_filt             : 1;       /**< Mask poisoned TLP filtering */
+        uint32_t m_fun                   : 1;       /**< Mask function */
+        uint32_t dfcwt                   : 1;       /**< Disable FC Watchdog Timer */
+        uint32_t reserved_11_14          : 4;
+        uint32_t skpiv                   : 11;      /**< SKP Interval Value */
+#else
+        uint32_t skpiv                   : 11;
+        uint32_t reserved_11_14          : 4;
+        uint32_t dfcwt                   : 1;
+        uint32_t m_fun                   : 1;
+        uint32_t m_pois_filt             : 1;
+        uint32_t m_bar_match             : 1;
+        uint32_t m_cfg1_filt             : 1;
+        uint32_t m_lk_filt               : 1;
+        uint32_t m_cpl_tag_err           : 1;
+        uint32_t m_cpl_rid_err           : 1;
+        uint32_t m_cpl_fun_err           : 1;
+        uint32_t m_cpl_tc_err            : 1;
+        uint32_t m_cpl_attr_err          : 1;
+        uint32_t m_cpl_len_err           : 1;
+        uint32_t m_ecrc_filt             : 1;
+        uint32_t m_cpl_ecrc_filt         : 1;
+        uint32_t msg_ctrl                : 1;
+        uint32_t m_io_filt               : 1;
+        uint32_t m_cfg0_filt             : 1;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg455_s         cn52xx;
+    struct cvmx_pciercx_cfg455_s         cn52xxp1;
+    struct cvmx_pciercx_cfg455_s         cn56xx;
+    struct cvmx_pciercx_cfg455_s         cn56xxp1;
+} cvmx_pciercx_cfg455_t;
+
+
+/**
+ * cvmx_pcierc#_cfg456
+ *
+ * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space
+ * (Filter Mask Register 2)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg456_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_2_31           : 30;
+        uint32_t m_vend1_drp             : 1;       /**< Mask Vendor MSG Type 1 dropped silently */
+        uint32_t m_vend0_drp             : 1;       /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */
+#else
+        uint32_t m_vend0_drp             : 1;
+        uint32_t m_vend1_drp             : 1;
+        uint32_t reserved_2_31           : 30;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg456_s         cn52xx;
+    struct cvmx_pciercx_cfg456_s         cn52xxp1;
+    struct cvmx_pciercx_cfg456_s         cn56xx;
+    struct cvmx_pciercx_cfg456_s         cn56xxp1;
+} cvmx_pciercx_cfg456_t;
+
+
+/**
+ * cvmx_pcierc#_cfg458
+ *
+ * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space
+ * (Debug Register 0)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg458_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dbg_info_l32            : 32;      /**< The value on cxpl_debug_info[31:0]. */
+#else
+        uint32_t dbg_info_l32            : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg458_s         cn52xx;
+    struct cvmx_pciercx_cfg458_s         cn52xxp1;
+    struct cvmx_pciercx_cfg458_s         cn56xx;
+    struct cvmx_pciercx_cfg458_s         cn56xxp1;
+} cvmx_pciercx_cfg458_t;
+
+
+/**
+ * cvmx_pcierc#_cfg459
+ *
+ * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space
+ * (Debug Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg459_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dbg_info_u32            : 32;      /**< The value on cxpl_debug_info[63:32]. */
+#else
+        uint32_t dbg_info_u32            : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg459_s         cn52xx;
+    struct cvmx_pciercx_cfg459_s         cn52xxp1;
+    struct cvmx_pciercx_cfg459_s         cn56xx;
+    struct cvmx_pciercx_cfg459_s         cn56xxp1;
+} cvmx_pciercx_cfg459_t;
+
+
+/**
+ * cvmx_pcierc#_cfg460
+ *
+ * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space
+ * (Transmit Posted FC Credit Status)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg460_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t tphfcc                  : 8;       /**< Transmit Posted Header FC Credits
+                                                         The Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+        uint32_t tpdfcc                  : 12;      /**< Transmit Posted Data FC Credits
+                                                         The Posted Data credits advertised by the receiver at the other
+                                                         end of the Link, updated with each UpdateFC DLLP. */
+#else
+        uint32_t tpdfcc                  : 12;
+        uint32_t tphfcc                  : 8;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg460_s         cn52xx;
+    struct cvmx_pciercx_cfg460_s         cn52xxp1;
+    struct cvmx_pciercx_cfg460_s         cn56xx;
+    struct cvmx_pciercx_cfg460_s         cn56xxp1;
+} cvmx_pciercx_cfg460_t;
+
+
+/**
+ * cvmx_pcierc#_cfg461
+ *
+ * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space
+ * (Transmit Non-Posted FC Credit Status)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg461_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t tchfcc                  : 8;       /**< Transmit Non-Posted Header FC Credits
+                                                         The Non-Posted Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+        uint32_t tcdfcc                  : 12;      /**< Transmit Non-Posted Data FC Credits
+                                                         The Non-Posted Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+        uint32_t tcdfcc                  : 12;
+        uint32_t tchfcc                  : 8;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg461_s         cn52xx;
+    struct cvmx_pciercx_cfg461_s         cn52xxp1;
+    struct cvmx_pciercx_cfg461_s         cn56xx;
+    struct cvmx_pciercx_cfg461_s         cn56xxp1;
+} cvmx_pciercx_cfg461_t;
+
+
+/**
+ * cvmx_pcierc#_cfg462
+ *
+ * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space
+ * (Transmit Completion FC Credit Status )
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg462_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t tchfcc                  : 8;       /**< Transmit Completion Header FC Credits
+                                                         The Completion Header credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+        uint32_t tcdfcc                  : 12;      /**< Transmit Completion Data FC Credits
+                                                         The Completion Data credits advertised by the receiver at the
+                                                         other end of the Link, updated with each UpdateFC DLLP. */
+#else
+        uint32_t tcdfcc                  : 12;
+        uint32_t tchfcc                  : 8;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg462_s         cn52xx;
+    struct cvmx_pciercx_cfg462_s         cn52xxp1;
+    struct cvmx_pciercx_cfg462_s         cn56xx;
+    struct cvmx_pciercx_cfg462_s         cn56xxp1;
+} cvmx_pciercx_cfg462_t;
+
+
+/**
+ * cvmx_pcierc#_cfg463
+ *
+ * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space
+ * (Queue Status)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg463_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_3_31           : 29;
+        uint32_t rqne                    : 1;       /**< Received Queue Not Empty
+                                                         Indicates there is data in one or more of the receive buffers. */
+        uint32_t trbne                   : 1;       /**< Transmit Retry Buffer Not Empty
+                                                         Indicates that there is data in the transmit retry buffer. */
+        uint32_t rtlpfccnr               : 1;       /**< Received TLP FC Credits Not Returned
+                                                         Indicates that the PCI Express bus has sent a TLP but has not
+                                                         yet received an UpdateFC DLLP indicating that the credits for
+                                                         that TLP have been restored by the receiver at the other end of
+                                                         the Link. */
+#else
+        uint32_t rtlpfccnr               : 1;
+        uint32_t trbne                   : 1;
+        uint32_t rqne                    : 1;
+        uint32_t reserved_3_31           : 29;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg463_s         cn52xx;
+    struct cvmx_pciercx_cfg463_s         cn52xxp1;
+    struct cvmx_pciercx_cfg463_s         cn56xx;
+    struct cvmx_pciercx_cfg463_s         cn56xxp1;
+} cvmx_pciercx_cfg463_t;
+
+
+/**
+ * cvmx_pcierc#_cfg464
+ *
+ * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space
+ * (VC Transmit Arbitration Register 1)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg464_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t wrr_vc3                 : 8;       /**< WRR Weight for VC3 */
+        uint32_t wrr_vc2                 : 8;       /**< WRR Weight for VC2 */
+        uint32_t wrr_vc1                 : 8;       /**< WRR Weight for VC1 */
+        uint32_t wrr_vc0                 : 8;       /**< WRR Weight for VC0 */
+#else
+        uint32_t wrr_vc0                 : 8;
+        uint32_t wrr_vc1                 : 8;
+        uint32_t wrr_vc2                 : 8;
+        uint32_t wrr_vc3                 : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg464_s         cn52xx;
+    struct cvmx_pciercx_cfg464_s         cn52xxp1;
+    struct cvmx_pciercx_cfg464_s         cn56xx;
+    struct cvmx_pciercx_cfg464_s         cn56xxp1;
+} cvmx_pciercx_cfg464_t;
+
+
+/**
+ * cvmx_pcierc#_cfg465
+ *
+ * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space
+ * (VC Transmit Arbitration Register 2)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg465_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t wrr_vc7                 : 8;       /**< WRR Weight for VC7 */
+        uint32_t wrr_vc6                 : 8;       /**< WRR Weight for VC6 */
+        uint32_t wrr_vc5                 : 8;       /**< WRR Weight for VC5 */
+        uint32_t wrr_vc4                 : 8;       /**< WRR Weight for VC4 */
+#else
+        uint32_t wrr_vc4                 : 8;
+        uint32_t wrr_vc5                 : 8;
+        uint32_t wrr_vc6                 : 8;
+        uint32_t wrr_vc7                 : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg465_s         cn52xx;
+    struct cvmx_pciercx_cfg465_s         cn52xxp1;
+    struct cvmx_pciercx_cfg465_s         cn56xx;
+    struct cvmx_pciercx_cfg465_s         cn56xxp1;
+} cvmx_pciercx_cfg465_t;
+
+
+/**
+ * cvmx_pcierc#_cfg466
+ *
+ * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space
+ * (VC0 Posted Receive Queue Control)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg466_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t rx_queue_order          : 1;       /**< VC Ordering for Receive Queues
+                                                         Determines the VC ordering rule for the receive queues, used
+                                                         only in the segmented-buffer configuration,
+                                                         writable through the DBI:
+                                                         o 1: Strict ordering, higher numbered VCs have higher priority
+                                                         o 0: Round robin
+                                                         However, the application must not change this field. */
+        uint32_t type_ordering           : 1;       /**< TLP Type Ordering for VC0
+                                                         Determines the TLP type ordering rule for VC0 receive queues,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through the DBI:
+                                                         o 1: Ordering of received TLPs follows the rules in
+                                                              PCI Express Base Specification, Revision 1.1
+                                                         o 0: Strict ordering for received TLPs: Posted, then
+                                                              Completion, then Non-Posted
+                                                         However, the application must not change this field. */
+        uint32_t reserved_24_29          : 6;
+        uint32_t queue_mode              : 3;       /**< VC0 Posted TLP Queue Mode
+                                                         The operating mode of the Posted receive queue for VC0, used
+                                                         only in the segmented-buffer configuration, writable through
+                                                         the DBI. However, the application must not change this field.
+                                                         Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward */
+        uint32_t reserved_20_20          : 1;
+        uint32_t header_credits          : 8;       /**< VC0 Posted Header Credits
+                                                         The number of initial Posted header credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t data_credits            : 12;      /**< VC0 Posted Data Credits
+                                                         The number of initial Posted data credits for VC0, used for all
+                                                         receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_credits            : 12;
+        uint32_t header_credits          : 8;
+        uint32_t reserved_20_20          : 1;
+        uint32_t queue_mode              : 3;
+        uint32_t reserved_24_29          : 6;
+        uint32_t type_ordering           : 1;
+        uint32_t rx_queue_order          : 1;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg466_s         cn52xx;
+    struct cvmx_pciercx_cfg466_s         cn52xxp1;
+    struct cvmx_pciercx_cfg466_s         cn56xx;
+    struct cvmx_pciercx_cfg466_s         cn56xxp1;
+} cvmx_pciercx_cfg466_t;
+
+
+/**
+ * cvmx_pcierc#_cfg467
+ *
+ * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space
+ * (VC0 Non-Posted Receive Queue Control)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg467_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t queue_mode              : 3;       /**< VC0 Non-Posted TLP Queue Mode
+                                                         The operating mode of the Non-Posted receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through the DBI. Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t header_credits          : 8;       /**< VC0 Non-Posted Header Credits
+                                                         The number of initial Non-Posted header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t data_credits            : 12;      /**< VC0 Non-Posted Data Credits
+                                                         The number of initial Non-Posted data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_credits            : 12;
+        uint32_t header_credits          : 8;
+        uint32_t reserved_20_20          : 1;
+        uint32_t queue_mode              : 3;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg467_s         cn52xx;
+    struct cvmx_pciercx_cfg467_s         cn52xxp1;
+    struct cvmx_pciercx_cfg467_s         cn56xx;
+    struct cvmx_pciercx_cfg467_s         cn56xxp1;
+} cvmx_pciercx_cfg467_t;
+
+
+/**
+ * cvmx_pcierc#_cfg468
+ *
+ * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space
+ * (VC0 Completion Receive Queue Control)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg468_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_24_31          : 8;
+        uint32_t queue_mode              : 3;       /**< VC0 Completion TLP Queue Mode
+                                                         The operating mode of the Completion receive queue for VC0,
+                                                         used only in the segmented-buffer configuration, writable
+                                                         through the DBI. Only one bit can be set at a time:
+                                                         o Bit 23: Bypass
+                                                         o Bit 22: Cut-through
+                                                         o Bit 21: Store-and-forward
+                                                         However, the application must not change this field. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t header_credits          : 8;       /**< VC0 Completion Header Credits
+                                                         The number of initial Completion header credits for VC0, used
+                                                         for all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t data_credits            : 12;      /**< VC0 Completion Data Credits
+                                                         The number of initial Completion data credits for VC0, used for
+                                                         all receive queue buffer configurations.
+                                                         This field is writable through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_credits            : 12;
+        uint32_t header_credits          : 8;
+        uint32_t reserved_20_20          : 1;
+        uint32_t queue_mode              : 3;
+        uint32_t reserved_24_31          : 8;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg468_s         cn52xx;
+    struct cvmx_pciercx_cfg468_s         cn52xxp1;
+    struct cvmx_pciercx_cfg468_s         cn56xx;
+    struct cvmx_pciercx_cfg468_s         cn56xxp1;
+} cvmx_pciercx_cfg468_t;
+
+
+/**
+ * cvmx_pcierc#_cfg490
+ *
+ * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space
+ * (VC0 Posted Buffer Depth)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg490_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t header_depth            : 10;      /**< VC0 Posted Header Queue Depth
+                                                         Sets the number of entries in the Posted header queue for VC0
+                                                         when using the segmented-buffer configuration, writable through
+                                                         the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t reserved_14_15          : 2;
+        uint32_t data_depth              : 14;      /**< VC0 Posted Data Queue Depth
+                                                         Sets the number of entries in the Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_depth              : 14;
+        uint32_t reserved_14_15          : 2;
+        uint32_t header_depth            : 10;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg490_s         cn52xx;
+    struct cvmx_pciercx_cfg490_s         cn52xxp1;
+    struct cvmx_pciercx_cfg490_s         cn56xx;
+    struct cvmx_pciercx_cfg490_s         cn56xxp1;
+} cvmx_pciercx_cfg490_t;
+
+
+/**
+ * cvmx_pcierc#_cfg491
+ *
+ * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space
+ * (VC0 Non-Posted Buffer Depth)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg491_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t header_depth            : 10;      /**< VC0 Non-Posted Header Queue Depth
+                                                         Sets the number of entries in the Non-Posted header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t reserved_14_15          : 2;
+        uint32_t data_depth              : 14;      /**< VC0 Non-Posted Data Queue Depth
+                                                         Sets the number of entries in the Non-Posted data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_depth              : 14;
+        uint32_t reserved_14_15          : 2;
+        uint32_t header_depth            : 10;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg491_s         cn52xx;
+    struct cvmx_pciercx_cfg491_s         cn52xxp1;
+    struct cvmx_pciercx_cfg491_s         cn56xx;
+    struct cvmx_pciercx_cfg491_s         cn56xxp1;
+} cvmx_pciercx_cfg491_t;
+
+
+/**
+ * cvmx_pcierc#_cfg492
+ *
+ * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space
+ * (VC0 Completion Buffer Depth)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg492_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_26_31          : 6;
+        uint32_t header_depth            : 10;      /**< VC0 Completion Header Queue Depth
+                                                         Sets the number of entries in the Completion header queue for
+                                                         VC0 when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+        uint32_t reserved_14_15          : 2;
+        uint32_t data_depth              : 14;      /**< VC0 Completion Data Queue Depth
+                                                         Sets the number of entries in the Completion data queue for VC0
+                                                         when using the segmented-buffer configuration, writable
+                                                         through the DBI.
+                                                         However, the application must not change this field. */
+#else
+        uint32_t data_depth              : 14;
+        uint32_t reserved_14_15          : 2;
+        uint32_t header_depth            : 10;
+        uint32_t reserved_26_31          : 6;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg492_s         cn52xx;
+    struct cvmx_pciercx_cfg492_s         cn52xxp1;
+    struct cvmx_pciercx_cfg492_s         cn56xx;
+    struct cvmx_pciercx_cfg492_s         cn56xxp1;
+} cvmx_pciercx_cfg492_t;
+
+
+/**
+ * cvmx_pcierc#_cfg516
+ *
+ * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space
+ * (PHY Status Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg516_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t phy_stat                : 32;      /**< PHY Status */
+#else
+        uint32_t phy_stat                : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg516_s         cn52xx;
+    struct cvmx_pciercx_cfg516_s         cn52xxp1;
+    struct cvmx_pciercx_cfg516_s         cn56xx;
+    struct cvmx_pciercx_cfg516_s         cn56xxp1;
+} cvmx_pciercx_cfg516_t;
+
+
+/**
+ * cvmx_pcierc#_cfg517
+ *
+ * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space
+ * (PHY Control Register)
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_pciercx_cfg517_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t phy_ctrl                : 32;      /**< PHY Control */
+#else
+        uint32_t phy_ctrl                : 32;
+#endif
+    } s;
+    struct cvmx_pciercx_cfg517_s         cn52xx;
+    struct cvmx_pciercx_cfg517_s         cn52xxp1;
+    struct cvmx_pciercx_cfg517_s         cn56xx;
+    struct cvmx_pciercx_cfg517_s         cn56xxp1;
+} cvmx_pciercx_cfg517_t;
+
+
+/**
+ * cvmx_pcm#_dma_cfg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_dma_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t rdpend                  : 1;       /**< If 0, no L2C read responses pending
+                                                            1, L2C read responses are outstanding
+                                                         NOTE: When restarting after stopping a running TDM
+                                                         engine, software must wait for RDPEND to read 0
+                                                         before writing PCMn_TDM_CFG[ENABLE] to a 1 */
+        uint64_t reserved_54_62          : 9;
+        uint64_t rxslots                 : 10;      /**< Number of 8-bit slots to receive per frame
+                                                         (number of slots in a receive superframe) */
+        uint64_t reserved_42_43          : 2;
+        uint64_t txslots                 : 10;      /**< Number of 8-bit slots to transmit per frame
+                                                         (number of slots in a transmit superframe) */
+        uint64_t reserved_30_31          : 2;
+        uint64_t rxst                    : 10;      /**< Number of frame writes for interrupt */
+        uint64_t reserved_19_19          : 1;
+        uint64_t useldt                  : 1;       /**< If 0, use LDI command to read from L2C
+                                                         1, use LDT command to read from L2C */
+        uint64_t txrd                    : 10;      /**< Number of frame reads for interrupt */
+        uint64_t fetchsiz                : 4;       /**< FETCHSIZ+1 timeslots are read when threshold is
+                                                         reached. */
+        uint64_t thresh                  : 4;       /**< If number of bytes remaining in the DMA fifo is <=
+                                                         THRESH, initiate a fetch of timeslot data from the
+                                                         transmit memory region.
+                                                         NOTE: there are only 16B of buffer for each engine
+                                                         so the seetings for FETCHSIZ and THRESH must be
+                                                         such that the buffer will not be overrun:
+                                                         
+                                                         THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */
+#else
+        uint64_t thresh                  : 4;
+        uint64_t fetchsiz                : 4;
+        uint64_t txrd                    : 10;
+        uint64_t useldt                  : 1;
+        uint64_t reserved_19_19          : 1;
+        uint64_t rxst                    : 10;
+        uint64_t reserved_30_31          : 2;
+        uint64_t txslots                 : 10;
+        uint64_t reserved_42_43          : 2;
+        uint64_t rxslots                 : 10;
+        uint64_t reserved_54_62          : 9;
+        uint64_t rdpend                  : 1;
+#endif
+    } s;
+    struct cvmx_pcmx_dma_cfg_s           cn30xx;
+    struct cvmx_pcmx_dma_cfg_s           cn31xx;
+    struct cvmx_pcmx_dma_cfg_s           cn50xx;
+} cvmx_pcmx_dma_cfg_t;
+
+
+/**
+ * cvmx_pcm#_int_ena
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_int_ena_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rxovf                   : 1;       /**< Enable interrupt if RX byte overflows */
+        uint64_t txempty                 : 1;       /**< Enable interrupt on TX byte empty */
+        uint64_t txrd                    : 1;       /**< Enable DMA engine frame read interrupts */
+        uint64_t txwrap                  : 1;       /**< Enable TX region wrap interrupts */
+        uint64_t rxst                    : 1;       /**< Enable DMA engine frame store interrupts */
+        uint64_t rxwrap                  : 1;       /**< Enable RX region wrap interrupts */
+        uint64_t fsyncextra              : 1;       /**< Enable FSYNC extra interrupts
+                                                         NOTE: FSYNCEXTRA errors are defined as an FSYNC
+                                                         found in the "wrong" spot of a frame given the
+                                                         programming of PCMn_CLK_CFG[NUMSLOTS] and
+                                                         PCMn_CLK_CFG[EXTRABIT]. */
+        uint64_t fsyncmissed             : 1;       /**< Enable FSYNC missed interrupts
+                                                         NOTE: FSYNCMISSED errors are defined as an FSYNC
+                                                         missing from the correct spot in a frame given
+                                                         the programming of PCMn_CLK_CFG[NUMSLOTS] and
+                                                         PCMn_CLK_CFG[EXTRABIT]. */
+#else
+        uint64_t fsyncmissed             : 1;
+        uint64_t fsyncextra              : 1;
+        uint64_t rxwrap                  : 1;
+        uint64_t rxst                    : 1;
+        uint64_t txwrap                  : 1;
+        uint64_t txrd                    : 1;
+        uint64_t txempty                 : 1;
+        uint64_t rxovf                   : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pcmx_int_ena_s           cn30xx;
+    struct cvmx_pcmx_int_ena_s           cn31xx;
+    struct cvmx_pcmx_int_ena_s           cn50xx;
+} cvmx_pcmx_int_ena_t;
+
+
+/**
+ * cvmx_pcm#_int_sum
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rxovf                   : 1;       /**< RX byte overflowed */
+        uint64_t txempty                 : 1;       /**< TX byte was empty when sampled */
+        uint64_t txrd                    : 1;       /**< DMA engine frame read interrupt occurred */
+        uint64_t txwrap                  : 1;       /**< TX region wrap interrupt occurred */
+        uint64_t rxst                    : 1;       /**< DMA engine frame store interrupt occurred */
+        uint64_t rxwrap                  : 1;       /**< RX region wrap interrupt occurred */
+        uint64_t fsyncextra              : 1;       /**< FSYNC extra interrupt occurred */
+        uint64_t fsyncmissed             : 1;       /**< FSYNC missed interrupt occurred */
+#else
+        uint64_t fsyncmissed             : 1;
+        uint64_t fsyncextra              : 1;
+        uint64_t rxwrap                  : 1;
+        uint64_t rxst                    : 1;
+        uint64_t txwrap                  : 1;
+        uint64_t txrd                    : 1;
+        uint64_t txempty                 : 1;
+        uint64_t rxovf                   : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pcmx_int_sum_s           cn30xx;
+    struct cvmx_pcmx_int_sum_s           cn31xx;
+    struct cvmx_pcmx_int_sum_s           cn50xx;
+} cvmx_pcmx_int_sum_t;
+
+
+/**
+ * cvmx_pcm#_rxaddr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxaddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Address of the next write to the receive memory
+                                                         region */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_pcmx_rxaddr_s            cn30xx;
+    struct cvmx_pcmx_rxaddr_s            cn31xx;
+    struct cvmx_pcmx_rxaddr_s            cn50xx;
+} cvmx_pcmx_rxaddr_t;
+
+
+/**
+ * cvmx_pcm#_rxcnt
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxcnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt                     : 16;      /**< Number of superframes in receive memory region */
+#else
+        uint64_t cnt                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcmx_rxcnt_s             cn30xx;
+    struct cvmx_pcmx_rxcnt_s             cn31xx;
+    struct cvmx_pcmx_rxcnt_s             cn50xx;
+} cvmx_pcmx_rxcnt_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 63 to 0
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk0_s            cn30xx;
+    struct cvmx_pcmx_rxmsk0_s            cn31xx;
+    struct cvmx_pcmx_rxmsk0_s            cn50xx;
+} cvmx_pcmx_rxmsk0_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 127 to 64
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk1_s            cn30xx;
+    struct cvmx_pcmx_rxmsk1_s            cn31xx;
+    struct cvmx_pcmx_rxmsk1_s            cn50xx;
+} cvmx_pcmx_rxmsk1_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk2
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 191 to 128
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk2_s            cn30xx;
+    struct cvmx_pcmx_rxmsk2_s            cn31xx;
+    struct cvmx_pcmx_rxmsk2_s            cn50xx;
+} cvmx_pcmx_rxmsk2_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk3
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 255 to 192
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk3_s            cn30xx;
+    struct cvmx_pcmx_rxmsk3_s            cn31xx;
+    struct cvmx_pcmx_rxmsk3_s            cn50xx;
+} cvmx_pcmx_rxmsk3_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk4
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 319 to 256
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk4_s            cn30xx;
+    struct cvmx_pcmx_rxmsk4_s            cn31xx;
+    struct cvmx_pcmx_rxmsk4_s            cn50xx;
+} cvmx_pcmx_rxmsk4_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk5
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 383 to 320
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk5_s            cn30xx;
+    struct cvmx_pcmx_rxmsk5_s            cn31xx;
+    struct cvmx_pcmx_rxmsk5_s            cn50xx;
+} cvmx_pcmx_rxmsk5_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk6
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 447 to 384
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk6_s            cn30xx;
+    struct cvmx_pcmx_rxmsk6_s            cn31xx;
+    struct cvmx_pcmx_rxmsk6_s            cn50xx;
+} cvmx_pcmx_rxmsk6_t;
+
+
+/**
+ * cvmx_pcm#_rxmsk7
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxmsk7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Receive mask bits for slots 511 to 448
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_rxmsk7_s            cn30xx;
+    struct cvmx_pcmx_rxmsk7_s            cn31xx;
+    struct cvmx_pcmx_rxmsk7_s            cn50xx;
+} cvmx_pcmx_rxmsk7_t;
+
+
+/**
+ * cvmx_pcm#_rxstart
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_rxstart_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 33;      /**< Starting address for the receive memory region */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t addr                    : 33;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_pcmx_rxstart_s           cn30xx;
+    struct cvmx_pcmx_rxstart_s           cn31xx;
+    struct cvmx_pcmx_rxstart_s           cn50xx;
+} cvmx_pcmx_rxstart_t;
+
+
+/**
+ * cvmx_pcm#_tdm_cfg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_tdm_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t drvtim                  : 16;      /**< Number of ECLKs from start of bit time to stop
+                                                         driving last bit of timeslot (if not driving next
+                                                         timeslot) */
+        uint64_t samppt                  : 16;      /**< Number of ECLKs from start of bit time to sample
+                                                         data bit. */
+        uint64_t reserved_3_31           : 29;
+        uint64_t lsbfirst                : 1;       /**< If 0, shift/receive MSB first
+                                                         1, shift/receive LSB first */
+        uint64_t useclk1                 : 1;       /**< If 0, this PCM is based on BCLK/FSYNC0
+                                                         1, this PCM is based on BCLK/FSYNC1 */
+        uint64_t enable                  : 1;       /**< If 1, PCM is enabled, otherwise pins are GPIOs
+                                                         NOTE: when TDM is disabled by detection of an
+                                                         FSYNC error all transmission and reception is
+                                                         halted.  In addition, PCMn_TX/RXADDR are updated
+                                                         to point to the position at which the error was
+                                                         detected. */
+#else
+        uint64_t enable                  : 1;
+        uint64_t useclk1                 : 1;
+        uint64_t lsbfirst                : 1;
+        uint64_t reserved_3_31           : 29;
+        uint64_t samppt                  : 16;
+        uint64_t drvtim                  : 16;
+#endif
+    } s;
+    struct cvmx_pcmx_tdm_cfg_s           cn30xx;
+    struct cvmx_pcmx_tdm_cfg_s           cn31xx;
+    struct cvmx_pcmx_tdm_cfg_s           cn50xx;
+} cvmx_pcmx_tdm_cfg_t;
+
+
+/**
+ * cvmx_pcm#_tdm_dbg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_tdm_dbg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t debuginfo               : 64;      /**< Miscellaneous debug information */
+#else
+        uint64_t debuginfo               : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_tdm_dbg_s           cn30xx;
+    struct cvmx_pcmx_tdm_dbg_s           cn31xx;
+    struct cvmx_pcmx_tdm_dbg_s           cn50xx;
+} cvmx_pcmx_tdm_dbg_t;
+
+
+/**
+ * cvmx_pcm#_txaddr
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txaddr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 33;      /**< Address of the next read from the transmit memory
+                                                         region */
+        uint64_t fram                    : 3;       /**< Frame offset
+                                                         NOTE: this is used to extract the correct byte from
+                                                         each 64b word read from the transmit memory region */
+#else
+        uint64_t fram                    : 3;
+        uint64_t addr                    : 33;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_pcmx_txaddr_s            cn30xx;
+    struct cvmx_pcmx_txaddr_s            cn31xx;
+    struct cvmx_pcmx_txaddr_s            cn50xx;
+} cvmx_pcmx_txaddr_t;
+
+
+/**
+ * cvmx_pcm#_txcnt
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txcnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t cnt                     : 16;      /**< Number of superframes in transmit memory region */
+#else
+        uint64_t cnt                     : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcmx_txcnt_s             cn30xx;
+    struct cvmx_pcmx_txcnt_s             cn31xx;
+    struct cvmx_pcmx_txcnt_s             cn50xx;
+} cvmx_pcmx_txcnt_t;
+
+
+/**
+ * cvmx_pcm#_txmsk0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 63 to 0
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk0_s            cn30xx;
+    struct cvmx_pcmx_txmsk0_s            cn31xx;
+    struct cvmx_pcmx_txmsk0_s            cn50xx;
+} cvmx_pcmx_txmsk0_t;
+
+
+/**
+ * cvmx_pcm#_txmsk1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 127 to 64
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk1_s            cn30xx;
+    struct cvmx_pcmx_txmsk1_s            cn31xx;
+    struct cvmx_pcmx_txmsk1_s            cn50xx;
+} cvmx_pcmx_txmsk1_t;
+
+
+/**
+ * cvmx_pcm#_txmsk2
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 191 to 128
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk2_s            cn30xx;
+    struct cvmx_pcmx_txmsk2_s            cn31xx;
+    struct cvmx_pcmx_txmsk2_s            cn50xx;
+} cvmx_pcmx_txmsk2_t;
+
+
+/**
+ * cvmx_pcm#_txmsk3
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 255 to 192
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk3_s            cn30xx;
+    struct cvmx_pcmx_txmsk3_s            cn31xx;
+    struct cvmx_pcmx_txmsk3_s            cn50xx;
+} cvmx_pcmx_txmsk3_t;
+
+
+/**
+ * cvmx_pcm#_txmsk4
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 319 to 256
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk4_s            cn30xx;
+    struct cvmx_pcmx_txmsk4_s            cn31xx;
+    struct cvmx_pcmx_txmsk4_s            cn50xx;
+} cvmx_pcmx_txmsk4_t;
+
+
+/**
+ * cvmx_pcm#_txmsk5
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 383 to 320
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk5_s            cn30xx;
+    struct cvmx_pcmx_txmsk5_s            cn31xx;
+    struct cvmx_pcmx_txmsk5_s            cn50xx;
+} cvmx_pcmx_txmsk5_t;
+
+
+/**
+ * cvmx_pcm#_txmsk6
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 447 to 384
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk6_s            cn30xx;
+    struct cvmx_pcmx_txmsk6_s            cn31xx;
+    struct cvmx_pcmx_txmsk6_s            cn50xx;
+} cvmx_pcmx_txmsk6_t;
+
+
+/**
+ * cvmx_pcm#_txmsk7
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txmsk7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t mask                    : 64;      /**< Transmit mask bits for slots 511 to 448
+                                                         (1 means transmit, 0 means don't transmit) */
+#else
+        uint64_t mask                    : 64;
+#endif
+    } s;
+    struct cvmx_pcmx_txmsk7_s            cn30xx;
+    struct cvmx_pcmx_txmsk7_s            cn31xx;
+    struct cvmx_pcmx_txmsk7_s            cn50xx;
+} cvmx_pcmx_txmsk7_t;
+
+
+/**
+ * cvmx_pcm#_txstart
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcmx_txstart_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 33;      /**< Starting address for the transmit memory region */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t addr                    : 33;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_pcmx_txstart_s           cn30xx;
+    struct cvmx_pcmx_txstart_s           cn31xx;
+    struct cvmx_pcmx_txstart_s           cn50xx;
+} cvmx_pcmx_txstart_t;
+
+
+/**
+ * cvmx_pcm_clk#_cfg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcm_clkx_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fsyncgood               : 1;       /**< FSYNC status
+                                                         If 1, the last frame had a correctly positioned
+                                                               fsync pulse
+                                                         If 0, none/extra fsync pulse seen on most recent
+                                                               frame
+                                                         NOTE: this is intended for startup. the FSYNCEXTRA
+                                                         and FSYNCMISSING interrupts are intended for
+                                                         detecting loss of sync during normal operation. */
+        uint64_t reserved_48_62          : 15;
+        uint64_t fsyncsamp               : 16;      /**< Number of ECLKs from internal BCLK edge to
+                                                         sample FSYNC
+                                                         NOTE: used to sync to the start of a frame and to
+                                                         check for FSYNC errors. */
+        uint64_t reserved_26_31          : 6;
+        uint64_t fsynclen                : 5;       /**< Number of 1/2 BCLKs FSYNC is asserted for
+                                                         NOTE: only used when GEN==1 */
+        uint64_t fsyncloc                : 5;       /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
+                                                         bit 0.
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+        uint64_t numslots                : 10;      /**< Number of 8-bit slots in a frame
+                                                         NOTE: this, along with EXTRABIT and Fbclk
+                                                         determines FSYNC frequency when GEN == 1
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+        uint64_t extrabit                : 1;       /**< If 0, no frame bit
+                                                         If 1, add one extra bit time for frame bit
+                                                         NOTE: if GEN == 1, then FSYNC will be delayed one
+                                                         extra bit time.
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0
+                                                         NOTE: the extra bit comes from the LSB/MSB of the
+                                                         first byte of the frame in the transmit memory
+                                                         region.  LSB vs MSB is determined from the setting
+                                                         of PCMn_TDM_CFG[LSBFIRST]. */
+        uint64_t bitlen                  : 2;       /**< Number of BCLKs in a bit time.
+                                                         0 : 1 BCLK
+                                                         1 : 2 BCLKs
+                                                         2 : 4 BCLKs
+                                                         3 : operation undefined */
+        uint64_t bclkpol                 : 1;       /**< If 0, BCLK rise edge is start of bit time
+                                                         If 1, BCLK fall edge is start of bit time
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+        uint64_t fsyncpol                : 1;       /**< If 0, FSYNC idles low, asserts high
+                                                         If 1, FSYNC idles high, asserts low
+                                                         NOTE: also used to detect framing errors and
+                                                         therefore must have a correct value even if GEN==0 */
+        uint64_t ena                     : 1;       /**< If 0, Clock receiving logic is doing nothing
+                                                         1, Clock receiving logic is looking for sync */
+#else
+        uint64_t ena                     : 1;
+        uint64_t fsyncpol                : 1;
+        uint64_t bclkpol                 : 1;
+        uint64_t bitlen                  : 2;
+        uint64_t extrabit                : 1;
+        uint64_t numslots                : 10;
+        uint64_t fsyncloc                : 5;
+        uint64_t fsynclen                : 5;
+        uint64_t reserved_26_31          : 6;
+        uint64_t fsyncsamp               : 16;
+        uint64_t reserved_48_62          : 15;
+        uint64_t fsyncgood               : 1;
+#endif
+    } s;
+    struct cvmx_pcm_clkx_cfg_s           cn30xx;
+    struct cvmx_pcm_clkx_cfg_s           cn31xx;
+    struct cvmx_pcm_clkx_cfg_s           cn50xx;
+} cvmx_pcm_clkx_cfg_t;
+
+
+/**
+ * cvmx_pcm_clk#_dbg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcm_clkx_dbg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t debuginfo               : 64;      /**< Miscellaneous debug information */
+#else
+        uint64_t debuginfo               : 64;
+#endif
+    } s;
+    struct cvmx_pcm_clkx_dbg_s           cn30xx;
+    struct cvmx_pcm_clkx_dbg_s           cn31xx;
+    struct cvmx_pcm_clkx_dbg_s           cn50xx;
+} cvmx_pcm_clkx_dbg_t;
+
+
+/**
+ * cvmx_pcm_clk#_gen
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcm_clkx_gen_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t deltasamp               : 16;      /**< Signed number of ECLKs to move sampled BCLK edge
+                                                         NOTE: the complete number of ECLKs to move is:
+                                                                   NUMSAMP + 2 + 1 + DELTASAMP
+                                                               NUMSAMP to compensate for sampling delay
+                                                               + 2 to compensate for dual-rank synchronizer
+                                                               + 1 for uncertainity
+                                                               + DELTASAMP to CMA/debugging */
+        uint64_t numsamp                 : 16;      /**< Number of ECLK samples to detect BCLK change when
+                                                         receiving clock. */
+        uint64_t n                       : 32;      /**< Determines BCLK frequency when generating clock
+                                                         NOTE: Fbclk = Feclk * N / 2^32
+                                                               N = (Fbclk / Feclk) * 2^32
+                                                         NOTE: writing N == 0 stops the clock generator, and
+                                                               causes bclk and fsync to be RECEIVED */
+#else
+        uint64_t n                       : 32;
+        uint64_t numsamp                 : 16;
+        uint64_t deltasamp               : 16;
+#endif
+    } s;
+    struct cvmx_pcm_clkx_gen_s           cn30xx;
+    struct cvmx_pcm_clkx_gen_s           cn31xx;
+    struct cvmx_pcm_clkx_gen_s           cn50xx;
+} cvmx_pcm_clkx_gen_t;
+
+
+/**
+ * cvmx_pcs#_an#_adv_reg
+ *
+ * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification,
+ * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating
+ * that the chip cannot operate in the corresponding modes.
+ * 
+ * Bit [4] RM_FLT is a don't care when the selected mode is SGMII.
+ * 
+ * 
+ * 
+ * PCS_AN_ADV_REG = AN Advertisement Register4
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_anx_adv_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t np                      : 1;       /**< Always 0, no next page capability supported */
+        uint64_t reserved_14_14          : 1;
+        uint64_t rem_flt                 : 2;       /**< [<13>,<12>]
+                                                         0    0  Link OK  XMIT=DATA
+                                                         0    1  Link failure (loss of sync, XMIT!= DATA)
+                                                         1    0  local device Offline
+                                                         1    1  AN Error failure to complete AN
+                                                                 AN Error is set if resolution function
+                                                                 precludes operation with link partner */
+        uint64_t reserved_9_11           : 3;
+        uint64_t pause                   : 2;       /**< [<8>, <7>] Pause frame flow capability across link
+                                                                  Exchanged during Auto Negotiation
+                                                         0    0  No Pause
+                                                         0    1  Symmetric pause
+                                                         1    0  Asymmetric Pause
+                                                         1    1  Both symm and asymm pause to local device */
+        uint64_t hfd                     : 1;       /**< 1 means local device Half Duplex capable */
+        uint64_t fd                      : 1;       /**< 1 means local device Full Duplex capable */
+        uint64_t reserved_0_4            : 5;
+#else
+        uint64_t reserved_0_4            : 5;
+        uint64_t fd                      : 1;
+        uint64_t hfd                     : 1;
+        uint64_t pause                   : 2;
+        uint64_t reserved_9_11           : 3;
+        uint64_t rem_flt                 : 2;
+        uint64_t reserved_14_14          : 1;
+        uint64_t np                      : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_anx_adv_reg_s       cn52xx;
+    struct cvmx_pcsx_anx_adv_reg_s       cn52xxp1;
+    struct cvmx_pcsx_anx_adv_reg_s       cn56xx;
+    struct cvmx_pcsx_anx_adv_reg_s       cn56xxp1;
+} cvmx_pcsx_anx_adv_reg_t;
+
+
+/**
+ * cvmx_pcs#_an#_ext_st_reg
+ *
+ * NOTE:
+ * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1
+ * the an_results_reg is valid.
+ * 
+ * 
+ * PCS_AN_EXT_ST_REG = AN Extended Status Register15
+ * as per IEEE802.3 Clause 22
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_anx_ext_st_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t thou_xfd                : 1;       /**< 1 means PHY is 1000BASE-X Full Dup capable */
+        uint64_t thou_xhd                : 1;       /**< 1 means PHY is 1000BASE-X Half Dup capable */
+        uint64_t thou_tfd                : 1;       /**< 1 means PHY is 1000BASE-T Full Dup capable */
+        uint64_t thou_thd                : 1;       /**< 1 means PHY is 1000BASE-T Half Dup capable */
+        uint64_t reserved_0_11           : 12;
+#else
+        uint64_t reserved_0_11           : 12;
+        uint64_t thou_thd                : 1;
+        uint64_t thou_tfd                : 1;
+        uint64_t thou_xhd                : 1;
+        uint64_t thou_xfd                : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_anx_ext_st_reg_s    cn52xx;
+    struct cvmx_pcsx_anx_ext_st_reg_s    cn52xxp1;
+    struct cvmx_pcsx_anx_ext_st_reg_s    cn56xx;
+    struct cvmx_pcsx_anx_ext_st_reg_s    cn56xxp1;
+} cvmx_pcsx_anx_ext_st_reg_t;
+
+
+/**
+ * cvmx_pcs#_an#_lp_abil_reg
+ *
+ * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5
+ * as per IEEE802.3 Clause 37
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_anx_lp_abil_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t np                      : 1;       /**< 1=lp next page capable, 0=lp not next page capable */
+        uint64_t ack                     : 1;       /**< 1=Acknowledgement received */
+        uint64_t rem_flt                 : 2;       /**< [<13>,<12>] Link Partner's link status
+                                                         0    0  Link OK
+                                                         0    1  Offline
+                                                         1    0  Link failure
+                                                         1    1  AN Error */
+        uint64_t reserved_9_11           : 3;
+        uint64_t pause                   : 2;       /**< [<8>, <7>] Link Partner Pause setting
+                                                         0    0  No Pause
+                                                         0    1  Symmetric pause
+                                                         1    0  Asymmetric Pause
+                                                         1    1  Both symm and asymm pause to local device */
+        uint64_t hfd                     : 1;       /**< 1 means link partner Half Duplex capable */
+        uint64_t fd                      : 1;       /**< 1 means link partner Full Duplex capable */
+        uint64_t reserved_0_4            : 5;
+#else
+        uint64_t reserved_0_4            : 5;
+        uint64_t fd                      : 1;
+        uint64_t hfd                     : 1;
+        uint64_t pause                   : 2;
+        uint64_t reserved_9_11           : 3;
+        uint64_t rem_flt                 : 2;
+        uint64_t ack                     : 1;
+        uint64_t np                      : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_anx_lp_abil_reg_s   cn52xx;
+    struct cvmx_pcsx_anx_lp_abil_reg_s   cn52xxp1;
+    struct cvmx_pcsx_anx_lp_abil_reg_s   cn56xx;
+    struct cvmx_pcsx_anx_lp_abil_reg_s   cn56xxp1;
+} cvmx_pcsx_anx_lp_abil_reg_t;
+
+
+/**
+ * cvmx_pcs#_an#_results_reg
+ *
+ * PCS_AN_RESULTS_REG = AN Results Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_anx_results_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t pause                   : 2;       /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII)
+                                                         0    0  Disable Pause, TX and RX
+                                                         0    1  Enable pause frames RX only
+                                                         1    0  Enable Pause frames TX only
+                                                         1    1  Enable pause frames TX and RX */
+        uint64_t spd                     : 2;       /**< [<4>, <3>] Link Speed Selection
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  RSVD */
+        uint64_t an_cpt                  : 1;       /**< 1=AN Completed, 0=AN not completed or failed */
+        uint64_t dup                     : 1;       /**< 1=Full Duplex, 0=Half Duplex */
+        uint64_t link_ok                 : 1;       /**< 1=Link up(OK), 0=Link down */
+#else
+        uint64_t link_ok                 : 1;
+        uint64_t dup                     : 1;
+        uint64_t an_cpt                  : 1;
+        uint64_t spd                     : 2;
+        uint64_t pause                   : 2;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_pcsx_anx_results_reg_s   cn52xx;
+    struct cvmx_pcsx_anx_results_reg_s   cn52xxp1;
+    struct cvmx_pcsx_anx_results_reg_s   cn56xx;
+    struct cvmx_pcsx_anx_results_reg_s   cn56xxp1;
+} cvmx_pcsx_anx_results_reg_t;
+
+
+/**
+ * cvmx_pcs#_int#_en_reg
+ *
+ * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising
+ * 
+ * 
+ * PCS Interrupt Enable Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_intx_en_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t dup                     : 1;       /**< Enable duplex mode changed interrupt */
+        uint64_t sync_bad_en             : 1;       /**< Enable rx sync st machine in bad state interrupt */
+        uint64_t an_bad_en               : 1;       /**< Enable AN state machine bad state interrupt */
+        uint64_t rxlock_en               : 1;       /**< Enable rx code group sync/bit lock failure interrupt */
+        uint64_t rxbad_en                : 1;       /**< Enable rx state machine in bad state interrupt */
+        uint64_t rxerr_en                : 1;       /**< Enable RX error condition interrupt */
+        uint64_t txbad_en                : 1;       /**< Enable tx state machine in bad state interrupt */
+        uint64_t txfifo_en               : 1;       /**< Enable tx fifo overflow condition interrupt */
+        uint64_t txfifu_en               : 1;       /**< Enable tx fifo underflow condition intrrupt */
+        uint64_t an_err_en               : 1;       /**< Enable AN Error condition interrupt */
+        uint64_t xmit_en                 : 1;       /**< Enable XMIT variable state change interrupt */
+        uint64_t lnkspd_en               : 1;       /**< Enable Link Speed has changed interrupt */
+#else
+        uint64_t lnkspd_en               : 1;
+        uint64_t xmit_en                 : 1;
+        uint64_t an_err_en               : 1;
+        uint64_t txfifu_en               : 1;
+        uint64_t txfifo_en               : 1;
+        uint64_t txbad_en                : 1;
+        uint64_t rxerr_en                : 1;
+        uint64_t rxbad_en                : 1;
+        uint64_t rxlock_en               : 1;
+        uint64_t an_bad_en               : 1;
+        uint64_t sync_bad_en             : 1;
+        uint64_t dup                     : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_pcsx_intx_en_reg_s       cn52xx;
+    struct cvmx_pcsx_intx_en_reg_s       cn52xxp1;
+    struct cvmx_pcsx_intx_en_reg_s       cn56xx;
+    struct cvmx_pcsx_intx_en_reg_s       cn56xxp1;
+} cvmx_pcsx_intx_en_reg_t;
+
+
+/**
+ * cvmx_pcs#_int#_reg
+ *
+ * SGMII bit [12] is really a misnomer, it is a decode  of pi_qlm_cfg pins to indicate SGMII or 1000Base-X modes.
+ * 
+ * Note: MODE bit
+ * When MODE=1,  1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37.
+ * When MODE=0,  SGMII mode is selected and the following note will apply.
+ * Repeat note from SGM_AN_ADV register
+ * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
+ * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
+ * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
+ * 
+ * PCS Interrupt Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_intx_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t dup                     : 1;       /**< Set whenever Duplex mode changes on the link */
+        uint64_t sync_bad                : 1;       /**< Set by HW whenever rx sync st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+        uint64_t an_bad                  : 1;       /**< Set by HW whenever AN st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+        uint64_t rxlock                  : 1;       /**< Set by HW whenever code group Sync or bit lock
+                                                         failure occurs
+                                                         Cannot fire in loopback1 mode */
+        uint64_t rxbad                   : 1;       /**< Set by HW whenever rx st machine reaches a  bad
+                                                         state. Should never be set during normal operation */
+        uint64_t rxerr                   : 1;       /**< Set whenever RX receives a code group error in
+                                                         10 bit to 8 bit decode logic
+                                                         Cannot fire in loopback1 mode */
+        uint64_t txbad                   : 1;       /**< Set by HW whenever tx st machine reaches a bad
+                                                         state. Should never be set during normal operation */
+        uint64_t txfifo                  : 1;       /**< Set whenever HW detects a TX fifo overflow
+                                                         condition */
+        uint64_t txfifu                  : 1;       /**< Set whenever HW detects a TX fifo underflowflow
+                                                         condition */
+        uint64_t an_err                  : 1;       /**< AN Error, AN resolution function failed */
+        uint64_t xmit                    : 1;       /**< Set whenever HW detects a change in the XMIT
+                                                         variable. XMIT variable states are IDLE, CONFIG and
+                                                         DATA */
+        uint64_t lnkspd                  : 1;       /**< Set by HW whenever Link Speed has changed */
+#else
+        uint64_t lnkspd                  : 1;
+        uint64_t xmit                    : 1;
+        uint64_t an_err                  : 1;
+        uint64_t txfifu                  : 1;
+        uint64_t txfifo                  : 1;
+        uint64_t txbad                   : 1;
+        uint64_t rxerr                   : 1;
+        uint64_t rxbad                   : 1;
+        uint64_t rxlock                  : 1;
+        uint64_t an_bad                  : 1;
+        uint64_t sync_bad                : 1;
+        uint64_t dup                     : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_pcsx_intx_reg_s          cn52xx;
+    struct cvmx_pcsx_intx_reg_s          cn52xxp1;
+    struct cvmx_pcsx_intx_reg_s          cn56xx;
+    struct cvmx_pcsx_intx_reg_s          cn56xxp1;
+} cvmx_pcsx_intx_reg_t;
+
+
+/**
+ * cvmx_pcs#_link#_timer_count_reg
+ *
+ * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_linkx_timer_count_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t count                   : 16;      /**< (core clock period times 1024) times "COUNT" should
+                                                         be 1.6ms(SGMII)/10ms(otherwise) which is the link
+                                                         timer used in auto negotiation.
+                                                         Reset assums a 700MHz eclk for 1.6ms link timer */
+#else
+        uint64_t count                   : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
+    struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
+    struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
+    struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
+} cvmx_pcsx_linkx_timer_count_reg_t;
+
+
+/**
+ * cvmx_pcs#_log_anl#_reg
+ *
+ * PCS Logic Analyzer Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_log_anlx_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t lafifovfl               : 1;       /**< 1=logic analyser fif overflowed during packetization
+                                                         Write 1 to clear this bit */
+        uint64_t la_en                   : 1;       /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
+        uint64_t pkt_sz                  : 2;       /**< [<1>, <0>]  Logic Analyzer Packet Size
+                                                         0    0   Packet size 1k bytes
+                                                         0    1   Packet size 4k bytes
+                                                         1    0   Packet size 8k bytes
+                                                         1    1   Packet size 16k bytes */
+#else
+        uint64_t pkt_sz                  : 2;
+        uint64_t la_en                   : 1;
+        uint64_t lafifovfl               : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_pcsx_log_anlx_reg_s      cn52xx;
+    struct cvmx_pcsx_log_anlx_reg_s      cn52xxp1;
+    struct cvmx_pcsx_log_anlx_reg_s      cn56xx;
+    struct cvmx_pcsx_log_anlx_reg_s      cn56xxp1;
+} cvmx_pcsx_log_anlx_reg_t;
+
+
+/**
+ * cvmx_pcs#_misc#_ctl_reg
+ *
+ * SGMII Misc Control Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_miscx_ctl_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t sgmii                   : 1;       /**< 1=SGMII or 1000Base-X mode selected,
+                                                         0=XAUI or PCIE mode selected
+                                                         This bit represents pi_qlm1/3_cfg[1:0] pin status */
+        uint64_t gmxeno                  : 1;       /**< GMX Enable override. When set to 1, forces GMX to
+                                                         appear disabled. The enable/disable status of GMX
+                                                         is checked only at SOP of every packet. */
+        uint64_t loopbck2                : 1;       /**< Sets external loopback mode to return rx data back
+                                                         out via tx data path. 0=no loopback, 1=loopback */
+        uint64_t mac_phy                 : 1;       /**< 0=MAC, 1=PHY decides the tx_config_reg value to be
+                                                         sent during auto negotiation.
+                                                         See SGMII spec ENG-46158 from CISCO */
+        uint64_t mode                    : 1;       /**< 0=SGMII or 1= 1000 Base X */
+        uint64_t an_ovrd                 : 1;       /**< 0=disable, 1= enable over ride AN results
+                                                         Auto negotiation is allowed to happen but the
+                                                         results are ignored when set. Duplex and Link speed
+                                                         values are set from the pcs_mr_ctrl reg */
+        uint64_t samp_pt                 : 7;       /**< Byte# in elongated frames for 10/100Mb/s operation
+                                                         for data sampling on RX side in PCS.
+                                                         Recommended values are 0x5 for 100Mb/s operation
+                                                         and 0x32 for 10Mb/s operation.
+                                                         For 10Mb/s operaton this field should be set to a
+                                                         value less than 99 and greater than 0. If set out
+                                                         of this range a value of 50 will be used for actual
+                                                         sampling internally without affecting the CSR field
+                                                         For 100Mb/s operation this field should be set to a
+                                                         value less than 9 and greater than 0. If set out of
+                                                         this range a value of 5 will be used for actual
+                                                         sampling internally without affecting the CSR field */
+#else
+        uint64_t samp_pt                 : 7;
+        uint64_t an_ovrd                 : 1;
+        uint64_t mode                    : 1;
+        uint64_t mac_phy                 : 1;
+        uint64_t loopbck2                : 1;
+        uint64_t gmxeno                  : 1;
+        uint64_t sgmii                   : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_pcsx_miscx_ctl_reg_s     cn52xx;
+    struct cvmx_pcsx_miscx_ctl_reg_s     cn52xxp1;
+    struct cvmx_pcsx_miscx_ctl_reg_s     cn56xx;
+    struct cvmx_pcsx_miscx_ctl_reg_s     cn56xxp1;
+} cvmx_pcsx_miscx_ctl_reg_t;
+
+
+/**
+ * cvmx_pcs#_mr#_control_reg
+ *
+ * PCS_MR_CONTROL_REG = Control Register0
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_mrx_control_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t reset                   : 1;       /**< 1=SW Reset, the bit will return to 0 after pcs has
+                                                         been reset. Takes 32 eclk cycles to reset pcs */
+        uint64_t loopbck1                : 1;       /**< 0=normal operation, 1=loopback. The loopback mode
+                                                         will return(loopback) tx data from GMII tx back to
+                                                         GMII rx interface. The loopback happens in the pcs
+                                                         module. Auto Negotiation will be disabled even if
+                                                         the AN_EN bit is set, during loopback */
+        uint64_t spdlsb                  : 1;       /**< See bit 6 description */
+        uint64_t an_en                   : 1;       /**< 1=AN Enable, 0=AN Disable */
+        uint64_t pwr_dn                  : 1;       /**< 1=Power Down(HW reset), 0=Normal operation */
+        uint64_t reserved_10_10          : 1;
+        uint64_t rst_an                  : 1;       /**< If bit 12 is set and bit 3 of status reg is 1
+                                                         Auto Negotiation begins. Else,SW writes are ignored
+                                                         and this bit remians at 0. This bit clears itself
+                                                         to 0, when AN starts. */
+        uint64_t dup                     : 1;       /**< 1=full duplex, 0=half duplex; effective only if AN
+                                                         disabled. If status register bits [15:9] and and
+                                                         extended status reg bits [15:12] allow only one
+                                                         duplex mode|, this bit will correspond to that
+                                                         value and any attempt to write will be ignored. */
+        uint64_t coltst                  : 1;       /**< 1=enable COL signal test, 0=disable test
+                                                         During COL test, the COL signal will reflect the
+                                                         GMII TX_EN signal with less than 16BT delay */
+        uint64_t spdmsb                  : 1;       /**< [<6>, <13>]Link Speed effective only if AN disabled
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  RSVD */
+        uint64_t uni                     : 1;       /**< Unidirectional (Std 802.3-2005, Clause 66.2)
+                                                         This bit will override the AN_EN bit and disable
+                                                         auto-negotiation variable mr_an_enable, when set
+                                                         Used in both 1000Base-X and SGMII modes */
+        uint64_t reserved_0_4            : 5;
+#else
+        uint64_t reserved_0_4            : 5;
+        uint64_t uni                     : 1;
+        uint64_t spdmsb                  : 1;
+        uint64_t coltst                  : 1;
+        uint64_t dup                     : 1;
+        uint64_t rst_an                  : 1;
+        uint64_t reserved_10_10          : 1;
+        uint64_t pwr_dn                  : 1;
+        uint64_t an_en                   : 1;
+        uint64_t spdlsb                  : 1;
+        uint64_t loopbck1                : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_mrx_control_reg_s   cn52xx;
+    struct cvmx_pcsx_mrx_control_reg_s   cn52xxp1;
+    struct cvmx_pcsx_mrx_control_reg_s   cn56xx;
+    struct cvmx_pcsx_mrx_control_reg_s   cn56xxp1;
+} cvmx_pcsx_mrx_control_reg_t;
+
+
+/**
+ * cvmx_pcs#_mr#_status_reg
+ *
+ * NOTE:
+ * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results
+ * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set,
+ * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values
+ * from the pcs_mr_ctrl reg.
+ * 
+ *  PCS_MR_STATUS_REG = Status Register1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_mrx_status_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t hun_t4                  : 1;       /**< 1 means 100Base-T4 capable */
+        uint64_t hun_xfd                 : 1;       /**< 1 means 100Base-X Full Duplex */
+        uint64_t hun_xhd                 : 1;       /**< 1 means 100Base-X Half Duplex */
+        uint64_t ten_fd                  : 1;       /**< 1 means 10Mb/s Full Duplex */
+        uint64_t ten_hd                  : 1;       /**< 1 means 10Mb/s Half Duplex */
+        uint64_t hun_t2fd                : 1;       /**< 1 means 100Base-T2 Full Duplex */
+        uint64_t hun_t2hd                : 1;       /**< 1 means 100Base-T2 Half Duplex */
+        uint64_t ext_st                  : 1;       /**< 1 means extended status info in reg15 */
+        uint64_t reserved_7_7            : 1;
+        uint64_t prb_sup                 : 1;       /**< 1 means able to work without preamble bytes at the
+                                                         beginning of frames. 0 means not able to accept
+                                                         frames without preamble bytes preceding them. */
+        uint64_t an_cpt                  : 1;       /**< 1 means Auto Negotiation is complete and the
+                                                         contents of the an_results_reg are valid. */
+        uint64_t rm_flt                  : 1;       /**< Set to 1 when remote flt condition occurs. This bit
+                                                         implements a latching Hi behavior. It is cleared by
+                                                         SW read of this reg or when reset bit [15] in
+                                                         Control Reg is asserted.
+                                                         See an adv reg[13:12] for flt conditions */
+        uint64_t an_abil                 : 1;       /**< 1 means Auto Negotiation capable */
+        uint64_t lnk_st                  : 1;       /**< 1=link up, 0=link down. Set during AN process
+                                                         Set whenever XMIT=DATA. Latching Lo behavior when
+                                                         link goes down. Link down value of the bit stays
+                                                         low until SW reads the reg. */
+        uint64_t reserved_1_1            : 1;
+        uint64_t extnd                   : 1;       /**< Always 0, no extended capability regs present */
+#else
+        uint64_t extnd                   : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t lnk_st                  : 1;
+        uint64_t an_abil                 : 1;
+        uint64_t rm_flt                  : 1;
+        uint64_t an_cpt                  : 1;
+        uint64_t prb_sup                 : 1;
+        uint64_t reserved_7_7            : 1;
+        uint64_t ext_st                  : 1;
+        uint64_t hun_t2hd                : 1;
+        uint64_t hun_t2fd                : 1;
+        uint64_t ten_hd                  : 1;
+        uint64_t ten_fd                  : 1;
+        uint64_t hun_xhd                 : 1;
+        uint64_t hun_xfd                 : 1;
+        uint64_t hun_t4                  : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_mrx_status_reg_s    cn52xx;
+    struct cvmx_pcsx_mrx_status_reg_s    cn52xxp1;
+    struct cvmx_pcsx_mrx_status_reg_s    cn56xx;
+    struct cvmx_pcsx_mrx_status_reg_s    cn56xxp1;
+} cvmx_pcsx_mrx_status_reg_t;
+
+
+/**
+ * cvmx_pcs#_rx#_states_reg
+ *
+ * PCS_RX_STATES_REG = RX State Machines states register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_rxx_states_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t rx_bad                  : 1;       /**< Receive state machine in an illegal state */
+        uint64_t rx_st                   : 5;       /**< Receive state machine state */
+        uint64_t sync_bad                : 1;       /**< Receive synchronization SM in an illegal state */
+        uint64_t sync                    : 4;       /**< Receive synchronization SM state */
+        uint64_t an_bad                  : 1;       /**< Auto Negotiation state machine in an illegal state */
+        uint64_t an_st                   : 4;       /**< Auto Negotiation state machine state */
+#else
+        uint64_t an_st                   : 4;
+        uint64_t an_bad                  : 1;
+        uint64_t sync                    : 4;
+        uint64_t sync_bad                : 1;
+        uint64_t rx_st                   : 5;
+        uint64_t rx_bad                  : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_rxx_states_reg_s    cn52xx;
+    struct cvmx_pcsx_rxx_states_reg_s    cn52xxp1;
+    struct cvmx_pcsx_rxx_states_reg_s    cn56xx;
+    struct cvmx_pcsx_rxx_states_reg_s    cn56xxp1;
+} cvmx_pcsx_rxx_states_reg_t;
+
+
+/**
+ * cvmx_pcs#_rx#_sync_reg
+ *
+ * Note:
+ * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved.
+ * 
+ * 
+ *  PCS_RX_SYNC_REG = Code Group synchronization reg
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_rxx_sync_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t sync                    : 1;       /**< 1 means code group synchronization achieved */
+        uint64_t bit_lock                : 1;       /**< 1 means bit lock achieved */
+#else
+        uint64_t bit_lock                : 1;
+        uint64_t sync                    : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pcsx_rxx_sync_reg_s      cn52xx;
+    struct cvmx_pcsx_rxx_sync_reg_s      cn52xxp1;
+    struct cvmx_pcsx_rxx_sync_reg_s      cn56xx;
+    struct cvmx_pcsx_rxx_sync_reg_s      cn56xxp1;
+} cvmx_pcsx_rxx_sync_reg_t;
+
+
+/**
+ * cvmx_pcs#_sgm#_an_adv_reg
+ *
+ * SGMII AN Advertisement Register (sent out as tx_config_reg)
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_sgmx_an_adv_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t link                    : 1;       /**< Link status 1 Link Up, 0 Link Down */
+        uint64_t ack                     : 1;       /**< Auto negotiation ack */
+        uint64_t reserved_13_13          : 1;
+        uint64_t dup                     : 1;       /**< Duplex mode 1=full duplex, 0=half duplex */
+        uint64_t speed                   : 2;       /**< Link Speed
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  RSVD */
+        uint64_t reserved_1_9            : 9;
+        uint64_t one                     : 1;       /**< Always set to match tx_config_reg<0> */
+#else
+        uint64_t one                     : 1;
+        uint64_t reserved_1_9            : 9;
+        uint64_t speed                   : 2;
+        uint64_t dup                     : 1;
+        uint64_t reserved_13_13          : 1;
+        uint64_t ack                     : 1;
+        uint64_t link                    : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn52xx;
+    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn52xxp1;
+    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn56xx;
+    struct cvmx_pcsx_sgmx_an_adv_reg_s   cn56xxp1;
+} cvmx_pcsx_sgmx_an_adv_reg_t;
+
+
+/**
+ * cvmx_pcs#_sgm#_lp_adv_reg
+ *
+ * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
+ * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
+ * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
+ * 
+ * SGMII LP Advertisement Register (received as rx_config_reg)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_sgmx_lp_adv_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t link                    : 1;       /**< Link status 1 Link Up, 0 Link Down */
+        uint64_t reserved_13_14          : 2;
+        uint64_t dup                     : 1;       /**< Duplex mode 1=full duplex, 0=half duplex */
+        uint64_t speed                   : 2;       /**< Link Speed
+                                                         0    0  10Mb/s
+                                                         0    1  100Mb/s
+                                                         1    0  1000Mb/s
+                                                         1    1  RSVD */
+        uint64_t reserved_1_9            : 9;
+        uint64_t one                     : 1;       /**< Always set to match tx_config_reg<0> */
+#else
+        uint64_t one                     : 1;
+        uint64_t reserved_1_9            : 9;
+        uint64_t speed                   : 2;
+        uint64_t dup                     : 1;
+        uint64_t reserved_13_14          : 2;
+        uint64_t link                    : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn52xx;
+    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn52xxp1;
+    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn56xx;
+    struct cvmx_pcsx_sgmx_lp_adv_reg_s   cn56xxp1;
+} cvmx_pcsx_sgmx_lp_adv_reg_t;
+
+
+/**
+ * cvmx_pcs#_tx#_states_reg
+ *
+ * PCS_TX_STATES_REG = TX State Machines states register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_txx_states_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t xmit                    : 2;       /**< 0=undefined, 1=config, 2=idle, 3=data */
+        uint64_t tx_bad                  : 1;       /**< Xmit state machine in a bad state */
+        uint64_t ord_st                  : 4;       /**< Xmit ordered set state machine state */
+#else
+        uint64_t ord_st                  : 4;
+        uint64_t tx_bad                  : 1;
+        uint64_t xmit                    : 2;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_pcsx_txx_states_reg_s    cn52xx;
+    struct cvmx_pcsx_txx_states_reg_s    cn52xxp1;
+    struct cvmx_pcsx_txx_states_reg_s    cn56xx;
+    struct cvmx_pcsx_txx_states_reg_s    cn56xxp1;
+} cvmx_pcsx_txx_states_reg_t;
+
+
+/**
+ * cvmx_pcs#_tx_rx#_polarity_reg
+ *
+ * PCS_POLARITY_REG = TX_RX polarity reg
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsx_tx_rxx_polarity_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t rxovrd                  : 1;       /**< When 0, <2> determines polarity
+                                                         when 1, <1> determines polarity */
+        uint64_t autorxpl                : 1;       /**< Auto RX polarity detected. 1=inverted, 0=normal
+                                                         This bit always represents the correct rx polarity
+                                                         setting needed for successful rx path operartion,
+                                                         once a successful code group sync is obtained */
+        uint64_t rxplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
+        uint64_t txplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
+#else
+        uint64_t txplrt                  : 1;
+        uint64_t rxplrt                  : 1;
+        uint64_t autorxpl                : 1;
+        uint64_t rxovrd                  : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
+    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
+    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
+    struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
+} cvmx_pcsx_tx_rxx_polarity_reg_t;
+
+
+/**
+ * cvmx_pcsx#_10gbx_status_reg
+ *
+ * PCSX_10GBX_STATUS_REG = 10gbx_status_reg
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_10gbx_status_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t alignd                  : 1;       /**< 1=Lane alignment achieved, 0=Lanes not aligned */
+        uint64_t pattst                  : 1;       /**< Always at 0, no pattern testing capability */
+        uint64_t reserved_4_10           : 7;
+        uint64_t l3sync                  : 1;       /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */
+        uint64_t l2sync                  : 1;       /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */
+        uint64_t l1sync                  : 1;       /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */
+        uint64_t l0sync                  : 1;       /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */
+#else
+        uint64_t l0sync                  : 1;
+        uint64_t l1sync                  : 1;
+        uint64_t l2sync                  : 1;
+        uint64_t l3sync                  : 1;
+        uint64_t reserved_4_10           : 7;
+        uint64_t pattst                  : 1;
+        uint64_t alignd                  : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
+    struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
+    struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
+    struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
+} cvmx_pcsxx_10gbx_status_reg_t;
+
+
+/**
+ * cvmx_pcsx#_bist_status_reg
+ *
+ * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1
+ * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0].
+ * See pcs.csr  for sgmii/1000Base-X logic analyzer mode.
+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
+ * 
+ * 
+ *  PCSX Bist Status Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_bist_status_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t bist_status             : 1;       /**< 1=bist failure, 0=bisted memory ok or bist in progress
+                                                         pcsx.tx_sm.drf8x36m1_async_bist */
+#else
+        uint64_t bist_status             : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_pcsxx_bist_status_reg_s  cn52xx;
+    struct cvmx_pcsxx_bist_status_reg_s  cn52xxp1;
+    struct cvmx_pcsxx_bist_status_reg_s  cn56xx;
+    struct cvmx_pcsxx_bist_status_reg_s  cn56xxp1;
+} cvmx_pcsxx_bist_status_reg_t;
+
+
+/**
+ * cvmx_pcsx#_bit_lock_status_reg
+ *
+ * LN_SWAP for XAUI is to simplify interconnection layout between devices
+ * 
+ * 
+ * PCSX Bit Lock Status Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_bit_lock_status_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t bitlck3                 : 1;       /**< Receive Lane 3 bit lock status */
+        uint64_t bitlck2                 : 1;       /**< Receive Lane 2 bit lock status */
+        uint64_t bitlck1                 : 1;       /**< Receive Lane 1 bit lock status */
+        uint64_t bitlck0                 : 1;       /**< Receive Lane 0 bit lock status */
+#else
+        uint64_t bitlck0                 : 1;
+        uint64_t bitlck1                 : 1;
+        uint64_t bitlck2                 : 1;
+        uint64_t bitlck3                 : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
+    struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
+    struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
+    struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
+} cvmx_pcsxx_bit_lock_status_reg_t;
+
+
+/**
+ * cvmx_pcsx#_control1_reg
+ *
+ * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
+ * For normal operation(sgmii or 1000Base-X), this bit must be 0.
+ * See pcsx.csr for xaui logic analyzer mode.
+ * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
+ * 
+ * 
+ *  PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3
+ * 
+ * 
+ *  PCSX_CONTROL1_REG = Control Register1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_control1_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t reset                   : 1;       /**< 1=SW PCSX Reset, the bit will return to 0 after pcs
+                                                         has been reset. Takes 32 eclk cycles to reset pcs
+                                                         0=Normal operation */
+        uint64_t loopbck1                : 1;       /**< 0=normal operation, 1=internal loopback mode
+                                                         xgmii tx data received from gmx tx port is returned
+                                                         back into gmx, xgmii rx port. */
+        uint64_t spdsel1                 : 1;       /**< See bit 6 description */
+        uint64_t reserved_12_12          : 1;
+        uint64_t lo_pwr                  : 1;       /**< The status of this bit has no effect on operation
+                                                         of the PCS sublayer. */
+        uint64_t reserved_7_10           : 4;
+        uint64_t spdsel0                 : 1;       /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has
+                                                         no effect.
+                                                         [<6>, <13>]Link Speed selection
+                                                           1    1   Bits 5:2 select speed */
+        uint64_t spd                     : 4;       /**< Always select 10Gb/s, writes have no effect */
+        uint64_t reserved_0_1            : 2;
+#else
+        uint64_t reserved_0_1            : 2;
+        uint64_t spd                     : 4;
+        uint64_t spdsel0                 : 1;
+        uint64_t reserved_7_10           : 4;
+        uint64_t lo_pwr                  : 1;
+        uint64_t reserved_12_12          : 1;
+        uint64_t spdsel1                 : 1;
+        uint64_t loopbck1                : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsxx_control1_reg_s     cn52xx;
+    struct cvmx_pcsxx_control1_reg_s     cn52xxp1;
+    struct cvmx_pcsxx_control1_reg_s     cn56xx;
+    struct cvmx_pcsxx_control1_reg_s     cn56xxp1;
+} cvmx_pcsxx_control1_reg_t;
+
+
+/**
+ * cvmx_pcsx#_control2_reg
+ *
+ * PCSX_CONTROL2_REG = Control Register2
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_control2_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t type                    : 2;       /**< Always 2'b01, 10GBASE-X only supported */
+#else
+        uint64_t type                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pcsxx_control2_reg_s     cn52xx;
+    struct cvmx_pcsxx_control2_reg_s     cn52xxp1;
+    struct cvmx_pcsxx_control2_reg_s     cn56xx;
+    struct cvmx_pcsxx_control2_reg_s     cn56xxp1;
+} cvmx_pcsxx_control2_reg_t;
+
+
+/**
+ * cvmx_pcsx#_int_en_reg
+ *
+ * PCSX Interrupt Enable Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_int_en_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t algnlos_en              : 1;       /**< Enable ALGNLOS interrupt */
+        uint64_t synlos_en               : 1;       /**< Enable SYNLOS interrupt */
+        uint64_t bitlckls_en             : 1;       /**< Enable BITLCKLS interrupt */
+        uint64_t rxsynbad_en             : 1;       /**< Enable RXSYNBAD  interrupt */
+        uint64_t rxbad_en                : 1;       /**< Enable RXBAD  interrupt */
+        uint64_t txflt_en                : 1;       /**< Enable TXFLT   interrupt */
+#else
+        uint64_t txflt_en                : 1;
+        uint64_t rxbad_en                : 1;
+        uint64_t rxsynbad_en             : 1;
+        uint64_t bitlckls_en             : 1;
+        uint64_t synlos_en               : 1;
+        uint64_t algnlos_en              : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_pcsxx_int_en_reg_s       cn52xx;
+    struct cvmx_pcsxx_int_en_reg_s       cn52xxp1;
+    struct cvmx_pcsxx_int_en_reg_s       cn56xx;
+    struct cvmx_pcsxx_int_en_reg_s       cn56xxp1;
+} cvmx_pcsxx_int_en_reg_t;
+
+
+/**
+ * cvmx_pcsx#_int_reg
+ *
+ * PCSX Interrupt Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t algnlos                 : 1;       /**< Set when XAUI lanes lose alignment */
+        uint64_t synlos                  : 1;       /**< Set when Code group sync lost on 1 or more  lanes */
+        uint64_t bitlckls                : 1;       /**< Set when Bit lock lost on 1 or more xaui lanes */
+        uint64_t rxsynbad                : 1;       /**< Set when RX code grp sync st machine in bad state
+                                                         in one of the 4 xaui lanes */
+        uint64_t rxbad                   : 1;       /**< Set when RX state machine in bad state */
+        uint64_t txflt                   : 1;       /**< None defined at this time, always 0x0 */
+#else
+        uint64_t txflt                   : 1;
+        uint64_t rxbad                   : 1;
+        uint64_t rxsynbad                : 1;
+        uint64_t bitlckls                : 1;
+        uint64_t synlos                  : 1;
+        uint64_t algnlos                 : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_pcsxx_int_reg_s          cn52xx;
+    struct cvmx_pcsxx_int_reg_s          cn52xxp1;
+    struct cvmx_pcsxx_int_reg_s          cn56xx;
+    struct cvmx_pcsxx_int_reg_s          cn56xxp1;
+} cvmx_pcsxx_int_reg_t;
+
+
+/**
+ * cvmx_pcsx#_log_anl_reg
+ *
+ * PCSX Logic Analyzer Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_log_anl_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t enc_mode                : 1;       /**< 1=send xaui encoded data, 0=send xaui raw data to GMX
+                                                         See .../rtl/pcs/readme_logic_analyzer.txt for details */
+        uint64_t drop_ln                 : 2;       /**< xaui lane# to drop from logic analyzer packets
+                                                         [<5>, <4>]  Drop lane \#
+                                                          0    0   Drop lane 0 data
+                                                          0    1   Drop lane 1 data
+                                                          1    0   Drop lane 2 data
+                                                          1    1   Drop lane 3 data */
+        uint64_t lafifovfl               : 1;       /**< 1=logic analyser fif overflowed one or more times
+                                                         during packetization.
+                                                         Write 1 to clear this bit */
+        uint64_t la_en                   : 1;       /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
+        uint64_t pkt_sz                  : 2;       /**< [<1>, <0>]  Logic Analyzer Packet Size
+                                                         0    0   Packet size 1k bytes
+                                                         0    1   Packet size 4k bytes
+                                                         1    0   Packet size 8k bytes
+                                                         1    1   Packet size 16k bytes */
+#else
+        uint64_t pkt_sz                  : 2;
+        uint64_t la_en                   : 1;
+        uint64_t lafifovfl               : 1;
+        uint64_t drop_ln                 : 2;
+        uint64_t enc_mode                : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_pcsxx_log_anl_reg_s      cn52xx;
+    struct cvmx_pcsxx_log_anl_reg_s      cn52xxp1;
+    struct cvmx_pcsxx_log_anl_reg_s      cn56xx;
+    struct cvmx_pcsxx_log_anl_reg_s      cn56xxp1;
+} cvmx_pcsxx_log_anl_reg_t;
+
+
+/**
+ * cvmx_pcsx#_misc_ctl_reg
+ *
+ * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6>  ^  [4[RXPLRT<1>]];
+ * 
+ * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2>  ^  [4[TXPLRT<0>]];
+ * 
+ * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities
+ * 
+ * 
+ * 
+ * PCSX Misc Control Register
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_misc_ctl_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t tx_swap                 : 1;       /**< 0=do not swap xaui lanes going out to qlm's
+                                                         1=swap lanes 3 <-> 0   and   2 <-> 1 */
+        uint64_t rx_swap                 : 1;       /**< 0=do not swap xaui lanes coming in from qlm's
+                                                         1=swap lanes 3 <-> 0   and   2 <-> 1 */
+        uint64_t xaui                    : 1;       /**< 1=XAUI mode selected, 0=not XAUI mode selected
+                                                         This bit represents pi_qlm1/3_cfg[1:0] pin status */
+        uint64_t gmxeno                  : 1;       /**< GMX port enable override, GMX en/dis status is held
+                                                         during data packet reception. */
+#else
+        uint64_t gmxeno                  : 1;
+        uint64_t xaui                    : 1;
+        uint64_t rx_swap                 : 1;
+        uint64_t tx_swap                 : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_pcsxx_misc_ctl_reg_s     cn52xx;
+    struct cvmx_pcsxx_misc_ctl_reg_s     cn52xxp1;
+    struct cvmx_pcsxx_misc_ctl_reg_s     cn56xx;
+    struct cvmx_pcsxx_misc_ctl_reg_s     cn56xxp1;
+} cvmx_pcsxx_misc_ctl_reg_t;
+
+
+/**
+ * cvmx_pcsx#_rx_sync_states_reg
+ *
+ * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_rx_sync_states_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t sync3st                 : 4;       /**< Receive lane 3 code grp sync state machine state */
+        uint64_t sync2st                 : 4;       /**< Receive lane 2 code grp sync state machine state */
+        uint64_t sync1st                 : 4;       /**< Receive lane 1 code grp sync state machine state */
+        uint64_t sync0st                 : 4;       /**< Receive lane 0 code grp sync state machine state */
+#else
+        uint64_t sync0st                 : 4;
+        uint64_t sync1st                 : 4;
+        uint64_t sync2st                 : 4;
+        uint64_t sync3st                 : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
+    struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
+    struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
+    struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
+} cvmx_pcsxx_rx_sync_states_reg_t;
+
+
+/**
+ * cvmx_pcsx#_spd_abil_reg
+ *
+ * PCSX_SPD_ABIL_REG = Speed ability register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_spd_abil_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t tenpasst                : 1;       /**< Always 0, no 10PASS-TS/2BASE-TL capability support */
+        uint64_t tengb                   : 1;       /**< Always 1, 10Gb/s supported */
+#else
+        uint64_t tengb                   : 1;
+        uint64_t tenpasst                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pcsxx_spd_abil_reg_s     cn52xx;
+    struct cvmx_pcsxx_spd_abil_reg_s     cn52xxp1;
+    struct cvmx_pcsxx_spd_abil_reg_s     cn56xx;
+    struct cvmx_pcsxx_spd_abil_reg_s     cn56xxp1;
+} cvmx_pcsxx_spd_abil_reg_t;
+
+
+/**
+ * cvmx_pcsx#_status1_reg
+ *
+ * PCSX_STATUS1_REG = Status Register1
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_status1_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t flt                     : 1;       /**< 1=Fault condition detected, 0=No fault condition
+                                                         This bit is a logical OR of Status2 reg bits 11,10 */
+        uint64_t reserved_3_6            : 4;
+        uint64_t rcv_lnk                 : 1;       /**< 1=Receive Link up, 0=Receive Link down
+                                                         Latching Low version of r_10gbx_status_reg[12],
+                                                         Link down status continues until SW read. */
+        uint64_t lpable                  : 1;       /**< Always set to 1 for Low Power ablility indication */
+        uint64_t reserved_0_0            : 1;
+#else
+        uint64_t reserved_0_0            : 1;
+        uint64_t lpable                  : 1;
+        uint64_t rcv_lnk                 : 1;
+        uint64_t reserved_3_6            : 4;
+        uint64_t flt                     : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pcsxx_status1_reg_s      cn52xx;
+    struct cvmx_pcsxx_status1_reg_s      cn52xxp1;
+    struct cvmx_pcsxx_status1_reg_s      cn56xx;
+    struct cvmx_pcsxx_status1_reg_s      cn56xxp1;
+} cvmx_pcsxx_status1_reg_t;
+
+
+/**
+ * cvmx_pcsx#_status2_reg
+ *
+ * PCSX_STATUS2_REG = Status Register2
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_status2_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t dev                     : 2;       /**< Always at 2'b10, means a Device present at the addr */
+        uint64_t reserved_12_13          : 2;
+        uint64_t xmtflt                  : 1;       /**< 0=No xmit fault, 1=xmit fault. Implements latching
+                                                         High function until SW read. */
+        uint64_t rcvflt                  : 1;       /**< 0=No rcv fault, 1=rcv fault. Implements latching
+                                                         High function until SW read */
+        uint64_t reserved_3_9            : 7;
+        uint64_t tengb_w                 : 1;       /**< Always 0, no 10GBASE-W capability */
+        uint64_t tengb_x                 : 1;       /**< Always 1, 10GBASE-X capable */
+        uint64_t tengb_r                 : 1;       /**< Always 0, no 10GBASE-R capability */
+#else
+        uint64_t tengb_r                 : 1;
+        uint64_t tengb_x                 : 1;
+        uint64_t tengb_w                 : 1;
+        uint64_t reserved_3_9            : 7;
+        uint64_t rcvflt                  : 1;
+        uint64_t xmtflt                  : 1;
+        uint64_t reserved_12_13          : 2;
+        uint64_t dev                     : 2;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pcsxx_status2_reg_s      cn52xx;
+    struct cvmx_pcsxx_status2_reg_s      cn52xxp1;
+    struct cvmx_pcsxx_status2_reg_s      cn56xx;
+    struct cvmx_pcsxx_status2_reg_s      cn56xxp1;
+} cvmx_pcsxx_status2_reg_t;
+
+
+/**
+ * cvmx_pcsx#_tx_rx_polarity_reg
+ *
+ * PCSX_POLARITY_REG = TX_RX polarity reg
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_tx_rx_polarity_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t xor_rxplrt              : 4;       /**< Per lane RX polarity control */
+        uint64_t xor_txplrt              : 4;       /**< Per lane TX polarity control */
+        uint64_t rxplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
+        uint64_t txplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
+#else
+        uint64_t txplrt                  : 1;
+        uint64_t rxplrt                  : 1;
+        uint64_t xor_txplrt              : 4;
+        uint64_t xor_rxplrt              : 4;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
+    struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t rxplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
+        uint64_t txplrt                  : 1;       /**< 1 is inverted polarity, 0 is normal polarity */
+#else
+        uint64_t txplrt                  : 1;
+        uint64_t rxplrt                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn52xxp1;
+    struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
+    struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
+} cvmx_pcsxx_tx_rx_polarity_reg_t;
+
+
+/**
+ * cvmx_pcsx#_tx_rx_states_reg
+ *
+ * PCSX_TX_RX_STATES_REG = Transmit Receive States Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pcsxx_tx_rx_states_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t term_err                : 1;       /**< 1=Check end function detected error in packet
+                                                         terminate ||T|| column or the one after it */
+        uint64_t syn3bad                 : 1;       /**< 1=lane 3 code grp sync state machine in bad state */
+        uint64_t syn2bad                 : 1;       /**< 1=lane 2 code grp sync state machine in bad state */
+        uint64_t syn1bad                 : 1;       /**< 1=lane 1 code grp sync state machine in bad state */
+        uint64_t syn0bad                 : 1;       /**< 1=lane 0 code grp sync state machine in bad state */
+        uint64_t rxbad                   : 1;       /**< 1=Rcv state machine in a bad state, HW malfunction */
+        uint64_t algn_st                 : 3;       /**< Lane alignment state machine state state */
+        uint64_t rx_st                   : 2;       /**< Receive state machine state state */
+        uint64_t tx_st                   : 3;       /**< Transmit state machine state state */
+#else
+        uint64_t tx_st                   : 3;
+        uint64_t rx_st                   : 2;
+        uint64_t algn_st                 : 3;
+        uint64_t rxbad                   : 1;
+        uint64_t syn0bad                 : 1;
+        uint64_t syn1bad                 : 1;
+        uint64_t syn2bad                 : 1;
+        uint64_t syn3bad                 : 1;
+        uint64_t term_err                : 1;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
+    struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t syn3bad                 : 1;       /**< 1=lane 3 code grp sync state machine in bad state */
+        uint64_t syn2bad                 : 1;       /**< 1=lane 2 code grp sync state machine in bad state */
+        uint64_t syn1bad                 : 1;       /**< 1=lane 1 code grp sync state machine in bad state */
+        uint64_t syn0bad                 : 1;       /**< 1=lane 0 code grp sync state machine in bad state */
+        uint64_t rxbad                   : 1;       /**< 1=Rcv state machine in a bad state, HW malfunction */
+        uint64_t algn_st                 : 3;       /**< Lane alignment state machine state state */
+        uint64_t rx_st                   : 2;       /**< Receive state machine state state */
+        uint64_t tx_st                   : 3;       /**< Transmit state machine state state */
+#else
+        uint64_t tx_st                   : 3;
+        uint64_t rx_st                   : 2;
+        uint64_t algn_st                 : 3;
+        uint64_t rxbad                   : 1;
+        uint64_t syn0bad                 : 1;
+        uint64_t syn1bad                 : 1;
+        uint64_t syn2bad                 : 1;
+        uint64_t syn3bad                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn52xxp1;
+    struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
+    struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
+} cvmx_pcsxx_tx_rx_states_reg_t;
+
+
+/**
+ * cvmx_pesc#_bist_status
+ *
+ * PESC_BIST_STATUS = PESC Bist Status
+ * 
+ * Contains the diffrent interrupt summary bits of the PESC.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t rqdata5                 : 1;       /**< Rx Queue Data Memory5. */
+        uint64_t ctlp_or                 : 1;       /**< C-TLP Order Fifo. */
+        uint64_t ntlp_or                 : 1;       /**< N-TLP Order Fifo. */
+        uint64_t ptlp_or                 : 1;       /**< P-TLP Order Fifo. */
+        uint64_t retry                   : 1;       /**< Retry Buffer. */
+        uint64_t rqdata0                 : 1;       /**< Rx Queue Data Memory0. */
+        uint64_t rqdata1                 : 1;       /**< Rx Queue Data Memory1. */
+        uint64_t rqdata2                 : 1;       /**< Rx Queue Data Memory2. */
+        uint64_t rqdata3                 : 1;       /**< Rx Queue Data Memory3. */
+        uint64_t rqdata4                 : 1;       /**< Rx Queue Data Memory4. */
+        uint64_t rqhdr1                  : 1;       /**< Rx Queue Header1. */
+        uint64_t rqhdr0                  : 1;       /**< Rx Queue Header0. */
+        uint64_t sot                     : 1;       /**< SOT Buffer. */
+#else
+        uint64_t sot                     : 1;
+        uint64_t rqhdr0                  : 1;
+        uint64_t rqhdr1                  : 1;
+        uint64_t rqdata4                 : 1;
+        uint64_t rqdata3                 : 1;
+        uint64_t rqdata2                 : 1;
+        uint64_t rqdata1                 : 1;
+        uint64_t rqdata0                 : 1;
+        uint64_t retry                   : 1;
+        uint64_t ptlp_or                 : 1;
+        uint64_t ntlp_or                 : 1;
+        uint64_t ctlp_or                 : 1;
+        uint64_t rqdata5                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_pescx_bist_status_s      cn52xx;
+    struct cvmx_pescx_bist_status_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t ctlp_or                 : 1;       /**< C-TLP Order Fifo. */
+        uint64_t ntlp_or                 : 1;       /**< N-TLP Order Fifo. */
+        uint64_t ptlp_or                 : 1;       /**< P-TLP Order Fifo. */
+        uint64_t retry                   : 1;       /**< Retry Buffer. */
+        uint64_t rqdata0                 : 1;       /**< Rx Queue Data Memory0. */
+        uint64_t rqdata1                 : 1;       /**< Rx Queue Data Memory1. */
+        uint64_t rqdata2                 : 1;       /**< Rx Queue Data Memory2. */
+        uint64_t rqdata3                 : 1;       /**< Rx Queue Data Memory3. */
+        uint64_t rqdata4                 : 1;       /**< Rx Queue Data Memory4. */
+        uint64_t rqhdr1                  : 1;       /**< Rx Queue Header1. */
+        uint64_t rqhdr0                  : 1;       /**< Rx Queue Header0. */
+        uint64_t sot                     : 1;       /**< SOT Buffer. */
+#else
+        uint64_t sot                     : 1;
+        uint64_t rqhdr0                  : 1;
+        uint64_t rqhdr1                  : 1;
+        uint64_t rqdata4                 : 1;
+        uint64_t rqdata3                 : 1;
+        uint64_t rqdata2                 : 1;
+        uint64_t rqdata1                 : 1;
+        uint64_t rqdata0                 : 1;
+        uint64_t retry                   : 1;
+        uint64_t ptlp_or                 : 1;
+        uint64_t ntlp_or                 : 1;
+        uint64_t ctlp_or                 : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn52xxp1;
+    struct cvmx_pescx_bist_status_s      cn56xx;
+    struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
+} cvmx_pescx_bist_status_t;
+
+
+/**
+ * cvmx_pesc#_bist_status2
+ *
+ * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
+ * 
+ * Results from BIST runs of PESC's memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_bist_status2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t cto_p2e                 : 1;       /**< BIST Status for the cto_p2e_fifo */
+        uint64_t e2p_cpl                 : 1;       /**< BIST Status for the e2p_cpl_fifo */
+        uint64_t e2p_n                   : 1;       /**< BIST Status for the e2p_n_fifo */
+        uint64_t e2p_p                   : 1;       /**< BIST Status for the e2p_p_fifo */
+        uint64_t e2p_rsl                 : 1;       /**< BIST Status for the e2p_rsl__fifo */
+        uint64_t dbg_p2e                 : 1;       /**< BIST Status for the dbg_p2e_fifo */
+        uint64_t peai_p2e                : 1;       /**< BIST Status for the peai__pesc_fifo */
+        uint64_t rsl_p2e                 : 1;       /**< BIST Status for the rsl_p2e_fifo */
+        uint64_t pef_tpf1                : 1;       /**< BIST Status for the pef_tlp_p_fifo1 */
+        uint64_t pef_tpf0                : 1;       /**< BIST Status for the pef_tlp_p_fifo0 */
+        uint64_t pef_tnf                 : 1;       /**< BIST Status for the pef_tlp_n_fifo */
+        uint64_t pef_tcf1                : 1;       /**< BIST Status for the pef_tlp_cpl_fifo1 */
+        uint64_t pef_tc0                 : 1;       /**< BIST Status for the pef_tlp_cpl_fifo0 */
+        uint64_t ppf                     : 1;       /**< BIST Status for the ppf_fifo */
+#else
+        uint64_t ppf                     : 1;
+        uint64_t pef_tc0                 : 1;
+        uint64_t pef_tcf1                : 1;
+        uint64_t pef_tnf                 : 1;
+        uint64_t pef_tpf0                : 1;
+        uint64_t pef_tpf1                : 1;
+        uint64_t rsl_p2e                 : 1;
+        uint64_t peai_p2e                : 1;
+        uint64_t dbg_p2e                 : 1;
+        uint64_t e2p_rsl                 : 1;
+        uint64_t e2p_p                   : 1;
+        uint64_t e2p_n                   : 1;
+        uint64_t e2p_cpl                 : 1;
+        uint64_t cto_p2e                 : 1;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_pescx_bist_status2_s     cn52xx;
+    struct cvmx_pescx_bist_status2_s     cn52xxp1;
+    struct cvmx_pescx_bist_status2_s     cn56xx;
+    struct cvmx_pescx_bist_status2_s     cn56xxp1;
+} cvmx_pescx_bist_status2_t;
+
+
+/**
+ * cvmx_pesc#_cfg_rd
+ *
+ * PESC_CFG_RD = PESC Configuration Read
+ * 
+ * Allows read access to the configuration in the PCIe Core.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_cfg_rd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 32;      /**< Data. */
+        uint64_t addr                    : 32;      /**< Address to read. A write to this register
+                                                         starts a read operation. */
+#else
+        uint64_t addr                    : 32;
+        uint64_t data                    : 32;
+#endif
+    } s;
+    struct cvmx_pescx_cfg_rd_s           cn52xx;
+    struct cvmx_pescx_cfg_rd_s           cn52xxp1;
+    struct cvmx_pescx_cfg_rd_s           cn56xx;
+    struct cvmx_pescx_cfg_rd_s           cn56xxp1;
+} cvmx_pescx_cfg_rd_t;
+
+
+/**
+ * cvmx_pesc#_cfg_wr
+ *
+ * PESC_CFG_WR = PESC Configuration Write
+ * 
+ * Allows write access to the configuration in the PCIe Core.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_cfg_wr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 32;      /**< Data to write. A write to this register starts
+                                                         a write operation. */
+        uint64_t addr                    : 32;      /**< Address to write. A write to this register starts
+                                                         a write operation. */
+#else
+        uint64_t addr                    : 32;
+        uint64_t data                    : 32;
+#endif
+    } s;
+    struct cvmx_pescx_cfg_wr_s           cn52xx;
+    struct cvmx_pescx_cfg_wr_s           cn52xxp1;
+    struct cvmx_pescx_cfg_wr_s           cn56xx;
+    struct cvmx_pescx_cfg_wr_s           cn56xxp1;
+} cvmx_pescx_cfg_wr_t;
+
+
+/**
+ * cvmx_pesc#_cpl_lut_valid
+ *
+ * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid
+ * 
+ * Bit set for outstanding tag read.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_cpl_lut_valid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t tag                     : 32;      /**< Bit vector set cooresponds to an outstanding tag
+                                                         expecting a completion. */
+#else
+        uint64_t tag                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pescx_cpl_lut_valid_s    cn52xx;
+    struct cvmx_pescx_cpl_lut_valid_s    cn52xxp1;
+    struct cvmx_pescx_cpl_lut_valid_s    cn56xx;
+    struct cvmx_pescx_cpl_lut_valid_s    cn56xxp1;
+} cvmx_pescx_cpl_lut_valid_t;
+
+
+/**
+ * cvmx_pesc#_ctl_status
+ *
+ * PESC_CTL_STATUS = PESC Control Status
+ * 
+ * General control and status of the PESC.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t dnum                    : 5;       /**< Primary bus device number. */
+        uint64_t pbus                    : 8;       /**< Primary bus number. */
+        uint64_t qlm_cfg                 : 2;       /**< The QLM configuration pad bits. */
+        uint64_t lane_swp                : 1;       /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1'
+                                                         enables LANE SWAP. THis bit has no effect on PEDC0.
+                                                         This bit should be set before enabling PEDC1. */
+        uint64_t pm_xtoff                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
+        uint64_t pm_xpme                 : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_pme port. EP mode. */
+        uint64_t ob_p_cmd                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
+        uint64_t reserved_7_8            : 2;
+        uint64_t nf_ecrc                 : 1;       /**< Do not forward peer-to-peer ECRC TLPs. */
+        uint64_t dly_one                 : 1;       /**< When set the output client state machines will
+                                                         wait one cycle before starting a new TLP out. */
+        uint64_t lnk_enb                 : 1;       /**< When set '1' the link is enabled when '0' the
+                                                         link is disabled. This bit only is active when in
+                                                         RC mode. */
+        uint64_t ro_ctlp                 : 1;       /**< When set '1' C-TLPs that have the RO bit set will
+                                                         not wait for P-TLPs that normaly would be sent
+                                                         first. */
+        uint64_t reserved_2_2            : 1;
+        uint64_t inv_ecrc                : 1;       /**< When '1' causes the LSB of the ECRC to be inverted. */
+        uint64_t inv_lcrc                : 1;       /**< When '1' causes the LSB of the LCRC to be inverted. */
+#else
+        uint64_t inv_lcrc                : 1;
+        uint64_t inv_ecrc                : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t ro_ctlp                 : 1;
+        uint64_t lnk_enb                 : 1;
+        uint64_t dly_one                 : 1;
+        uint64_t nf_ecrc                 : 1;
+        uint64_t reserved_7_8            : 2;
+        uint64_t ob_p_cmd                : 1;
+        uint64_t pm_xpme                 : 1;
+        uint64_t pm_xtoff                : 1;
+        uint64_t lane_swp                : 1;
+        uint64_t qlm_cfg                 : 2;
+        uint64_t pbus                    : 8;
+        uint64_t dnum                    : 5;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_pescx_ctl_status_s       cn52xx;
+    struct cvmx_pescx_ctl_status_s       cn52xxp1;
+    struct cvmx_pescx_ctl_status_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t dnum                    : 5;       /**< Primary bus device number. */
+        uint64_t pbus                    : 8;       /**< Primary bus number. */
+        uint64_t qlm_cfg                 : 2;       /**< The QLM configuration pad bits. */
+        uint64_t reserved_12_12          : 1;
+        uint64_t pm_xtoff                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_turnoff port. RC mode. */
+        uint64_t pm_xpme                 : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core pm_xmt_pme port. EP mode. */
+        uint64_t ob_p_cmd                : 1;       /**< When WRITTEN with a '1' a single cycle pulse is
+                                                         to the PCIe core outband_pwrup_cmd port. EP mode. */
+        uint64_t reserved_7_8            : 2;
+        uint64_t nf_ecrc                 : 1;       /**< Do not forward peer-to-peer ECRC TLPs. */
+        uint64_t dly_one                 : 1;       /**< When set the output client state machines will
+                                                         wait one cycle before starting a new TLP out. */
+        uint64_t lnk_enb                 : 1;       /**< When set '1' the link is enabled when '0' the
+                                                         link is disabled. This bit only is active when in
+                                                         RC mode. */
+        uint64_t ro_ctlp                 : 1;       /**< When set '1' C-TLPs that have the RO bit set will
+                                                         not wait for P-TLPs that normaly would be sent
+                                                         first. */
+        uint64_t reserved_2_2            : 1;
+        uint64_t inv_ecrc                : 1;       /**< When '1' causes the LSB of the ECRC to be inverted. */
+        uint64_t inv_lcrc                : 1;       /**< When '1' causes the LSB of the LCRC to be inverted. */
+#else
+        uint64_t inv_lcrc                : 1;
+        uint64_t inv_ecrc                : 1;
+        uint64_t reserved_2_2            : 1;
+        uint64_t ro_ctlp                 : 1;
+        uint64_t lnk_enb                 : 1;
+        uint64_t dly_one                 : 1;
+        uint64_t nf_ecrc                 : 1;
+        uint64_t reserved_7_8            : 2;
+        uint64_t ob_p_cmd                : 1;
+        uint64_t pm_xpme                 : 1;
+        uint64_t pm_xtoff                : 1;
+        uint64_t reserved_12_12          : 1;
+        uint64_t qlm_cfg                 : 2;
+        uint64_t pbus                    : 8;
+        uint64_t dnum                    : 5;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn56xx;
+    struct cvmx_pescx_ctl_status_cn56xx  cn56xxp1;
+} cvmx_pescx_ctl_status_t;
+
+
+/**
+ * cvmx_pesc#_ctl_status2
+ *
+ * Below are in PESC
+ * 
+ *                  PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register
+ * 
+ * Results from BIST runs of PESC's memories.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_ctl_status2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t pclk_run                : 1;       /**< When the pce_clk is running this bit will be '1'.
+                                                         Writing a '1' to this location will cause the
+                                                         bit to be cleared, but if the pce_clk is running
+                                                         this bit will be re-set. */
+        uint64_t pcierst                 : 1;       /**< Set to '1' when PCIe is in reset. */
+#else
+        uint64_t pcierst                 : 1;
+        uint64_t pclk_run                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pescx_ctl_status2_s      cn52xx;
+    struct cvmx_pescx_ctl_status2_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t pcierst                 : 1;       /**< Set to '1' when PCIe is in reset. */
+#else
+        uint64_t pcierst                 : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } cn52xxp1;
+    struct cvmx_pescx_ctl_status2_s      cn56xx;
+    struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
+} cvmx_pescx_ctl_status2_t;
+
+
+/**
+ * cvmx_pesc#_dbg_info
+ *
+ * PESC(0..1)_DBG_INFO = PESC Debug Information
+ * 
+ * General debug info.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_dbg_info_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t ecrc_e                  : 1;       /**< Received a ECRC error.
+                                                         radm_ecrc_err */
+        uint64_t rawwpp                  : 1;       /**< Received a write with poisoned payload
+                                                         radm_rcvd_wreq_poisoned */
+        uint64_t racpp                   : 1;       /**< Received a completion with poisoned payload
+                                                         radm_rcvd_cpl_poisoned */
+        uint64_t ramtlp                  : 1;       /**< Received a malformed TLP
+                                                         radm_mlf_tlp_err */
+        uint64_t rarwdns                 : 1;       /**< Recieved a request which device does not support
+                                                         radm_rcvd_ur_req */
+        uint64_t caar                    : 1;       /**< Completer aborted a request
+                                                         radm_rcvd_ca_req
+                                                         This bit will never be set because Octeon does
+                                                         not generate Completer Aborts. */
+        uint64_t racca                   : 1;       /**< Received a completion with CA status
+                                                         radm_rcvd_cpl_ca */
+        uint64_t racur                   : 1;       /**< Received a completion with UR status
+                                                         radm_rcvd_cpl_ur */
+        uint64_t rauc                    : 1;       /**< Received an unexpected completion
+                                                         radm_unexp_cpl_err */
+        uint64_t rqo                     : 1;       /**< Receive queue overflow. Normally happens only when
+                                                         flow control advertisements are ignored
+                                                         radm_qoverflow */
+        uint64_t fcuv                    : 1;       /**< Flow Control Update Violation (opt. checks)
+                                                         int_xadm_fc_prot_err */
+        uint64_t rpe                     : 1;       /**< When the PHY reports 8B/10B decode error
+                                                         (RxStatus = 3b100) or disparity error
+                                                         (RxStatus = 3b111), the signal rmlh_rcvd_err will
+                                                         be asserted.
+                                                         rmlh_rcvd_err */
+        uint64_t fcpvwt                  : 1;       /**< Flow Control Protocol Violation (Watchdog Timer)
+                                                         rtlh_fc_prot_err */
+        uint64_t dpeoosd                 : 1;       /**< DLLP protocol error (out of sequence DLLP)
+                                                         rdlh_prot_err */
+        uint64_t rtwdle                  : 1;       /**< Received TLP with DataLink Layer Error
+                                                         rdlh_bad_tlp_err */
+        uint64_t rdwdle                  : 1;       /**< Received DLLP with DataLink Layer Error
+                                                         rdlh_bad_dllp_err */
+        uint64_t mre                     : 1;       /**< Max Retries Exceeded
+                                                         xdlh_replay_num_rlover_err */
+        uint64_t rte                     : 1;       /**< Replay Timer Expired
+                                                         xdlh_replay_timeout_err
+                                                         This bit is set when the REPLAY_TIMER expires in
+                                                         the PCIE core. The probability of this bit being
+                                                         set will increase with the traffic load. */
+        uint64_t acto                    : 1;       /**< A Completion Timeout Occured
+                                                         pedc_radm_cpl_timeout */
+        uint64_t rvdm                    : 1;       /**< Received Vendor-Defined Message
+                                                         pedc_radm_vendor_msg */
+        uint64_t rumep                   : 1;       /**< Received Unlock Message (EP Mode Only)
+                                                         pedc_radm_msg_unlock */
+        uint64_t rptamrc                 : 1;       /**< Received PME Turnoff Acknowledge Message
+                                                         (RC Mode only)
+                                                         pedc_radm_pm_to_ack */
+        uint64_t rpmerc                  : 1;       /**< Received PME Message (RC Mode only)
+                                                         pedc_radm_pm_pme */
+        uint64_t rfemrc                  : 1;       /**< Received Fatal Error Message (RC Mode only)
+                                                         pedc_radm_fatal_err
+                                                         Bit set when a message with ERR_FATAL is set. */
+        uint64_t rnfemrc                 : 1;       /**< Received Non-Fatal Error Message (RC Mode only)
+                                                         pedc_radm_nonfatal_err */
+        uint64_t rcemrc                  : 1;       /**< Received Correctable Error Message (RC Mode only)
+                                                         pedc_radm_correctable_err */
+        uint64_t rpoison                 : 1;       /**< Received Poisoned TLP
+                                                         pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
+        uint64_t recrce                  : 1;       /**< Received ECRC Error
+                                                         pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
+        uint64_t rtlplle                 : 1;       /**< Received TLP has link layer error
+                                                         pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
+        uint64_t rtlpmal                 : 1;       /**< Received TLP is malformed or a message.
+                                                         pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
+                                                         If the core receives a MSG (or Vendor Message)
+                                                         this bit will be set. */
+        uint64_t spoison                 : 1;       /**< Poisoned TLP sent
+                                                         peai__client0_tlp_ep & peai__client0_tlp_hv */
+#else
+        uint64_t spoison                 : 1;
+        uint64_t rtlpmal                 : 1;
+        uint64_t rtlplle                 : 1;
+        uint64_t recrce                  : 1;
+        uint64_t rpoison                 : 1;
+        uint64_t rcemrc                  : 1;
+        uint64_t rnfemrc                 : 1;
+        uint64_t rfemrc                  : 1;
+        uint64_t rpmerc                  : 1;
+        uint64_t rptamrc                 : 1;
+        uint64_t rumep                   : 1;
+        uint64_t rvdm                    : 1;
+        uint64_t acto                    : 1;
+        uint64_t rte                     : 1;
+        uint64_t mre                     : 1;
+        uint64_t rdwdle                  : 1;
+        uint64_t rtwdle                  : 1;
+        uint64_t dpeoosd                 : 1;
+        uint64_t fcpvwt                  : 1;
+        uint64_t rpe                     : 1;
+        uint64_t fcuv                    : 1;
+        uint64_t rqo                     : 1;
+        uint64_t rauc                    : 1;
+        uint64_t racur                   : 1;
+        uint64_t racca                   : 1;
+        uint64_t caar                    : 1;
+        uint64_t rarwdns                 : 1;
+        uint64_t ramtlp                  : 1;
+        uint64_t racpp                   : 1;
+        uint64_t rawwpp                  : 1;
+        uint64_t ecrc_e                  : 1;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_pescx_dbg_info_s         cn52xx;
+    struct cvmx_pescx_dbg_info_s         cn52xxp1;
+    struct cvmx_pescx_dbg_info_s         cn56xx;
+    struct cvmx_pescx_dbg_info_s         cn56xxp1;
+} cvmx_pescx_dbg_info_t;
+
+
+/**
+ * cvmx_pesc#_dbg_info_en
+ *
+ * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable
+ * 
+ * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_dbg_info_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t ecrc_e                  : 1;       /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */
+        uint64_t rawwpp                  : 1;       /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */
+        uint64_t racpp                   : 1;       /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */
+        uint64_t ramtlp                  : 1;       /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */
+        uint64_t rarwdns                 : 1;       /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */
+        uint64_t caar                    : 1;       /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */
+        uint64_t racca                   : 1;       /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */
+        uint64_t racur                   : 1;       /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */
+        uint64_t rauc                    : 1;       /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */
+        uint64_t rqo                     : 1;       /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */
+        uint64_t fcuv                    : 1;       /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */
+        uint64_t rpe                     : 1;       /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */
+        uint64_t fcpvwt                  : 1;       /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */
+        uint64_t dpeoosd                 : 1;       /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */
+        uint64_t rtwdle                  : 1;       /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */
+        uint64_t rdwdle                  : 1;       /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */
+        uint64_t mre                     : 1;       /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */
+        uint64_t rte                     : 1;       /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */
+        uint64_t acto                    : 1;       /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */
+        uint64_t rvdm                    : 1;       /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */
+        uint64_t rumep                   : 1;       /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */
+        uint64_t rptamrc                 : 1;       /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */
+        uint64_t rpmerc                  : 1;       /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */
+        uint64_t rfemrc                  : 1;       /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */
+        uint64_t rnfemrc                 : 1;       /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */
+        uint64_t rcemrc                  : 1;       /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */
+        uint64_t rpoison                 : 1;       /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */
+        uint64_t recrce                  : 1;       /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */
+        uint64_t rtlplle                 : 1;       /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */
+        uint64_t rtlpmal                 : 1;       /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */
+        uint64_t spoison                 : 1;       /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */
+#else
+        uint64_t spoison                 : 1;
+        uint64_t rtlpmal                 : 1;
+        uint64_t rtlplle                 : 1;
+        uint64_t recrce                  : 1;
+        uint64_t rpoison                 : 1;
+        uint64_t rcemrc                  : 1;
+        uint64_t rnfemrc                 : 1;
+        uint64_t rfemrc                  : 1;
+        uint64_t rpmerc                  : 1;
+        uint64_t rptamrc                 : 1;
+        uint64_t rumep                   : 1;
+        uint64_t rvdm                    : 1;
+        uint64_t acto                    : 1;
+        uint64_t rte                     : 1;
+        uint64_t mre                     : 1;
+        uint64_t rdwdle                  : 1;
+        uint64_t rtwdle                  : 1;
+        uint64_t dpeoosd                 : 1;
+        uint64_t fcpvwt                  : 1;
+        uint64_t rpe                     : 1;
+        uint64_t fcuv                    : 1;
+        uint64_t rqo                     : 1;
+        uint64_t rauc                    : 1;
+        uint64_t racur                   : 1;
+        uint64_t racca                   : 1;
+        uint64_t caar                    : 1;
+        uint64_t rarwdns                 : 1;
+        uint64_t ramtlp                  : 1;
+        uint64_t racpp                   : 1;
+        uint64_t rawwpp                  : 1;
+        uint64_t ecrc_e                  : 1;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_pescx_dbg_info_en_s      cn52xx;
+    struct cvmx_pescx_dbg_info_en_s      cn52xxp1;
+    struct cvmx_pescx_dbg_info_en_s      cn56xx;
+    struct cvmx_pescx_dbg_info_en_s      cn56xxp1;
+} cvmx_pescx_dbg_info_en_t;
+
+
+/**
+ * cvmx_pesc#_diag_status
+ *
+ * PESC_DIAG_STATUS = PESC Diagnostic Status
+ * 
+ * Selection control for the cores diagnostic bus.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_diag_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t pm_dst                  : 1;       /**< Current power management DSTATE. */
+        uint64_t pm_stat                 : 1;       /**< Power Management Status. */
+        uint64_t pm_en                   : 1;       /**< Power Management Event Enable. */
+        uint64_t aux_en                  : 1;       /**< Auxilary Power Enable. */
+#else
+        uint64_t aux_en                  : 1;
+        uint64_t pm_en                   : 1;
+        uint64_t pm_stat                 : 1;
+        uint64_t pm_dst                  : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_pescx_diag_status_s      cn52xx;
+    struct cvmx_pescx_diag_status_s      cn52xxp1;
+    struct cvmx_pescx_diag_status_s      cn56xx;
+    struct cvmx_pescx_diag_status_s      cn56xxp1;
+} cvmx_pescx_diag_status_t;
+
+
+/**
+ * cvmx_pesc#_p2n_bar0_start
+ *
+ * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start
+ * 
+ * The starting address for addresses to forwarded to the NPEI in RC Mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_p2n_bar0_start_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 50;      /**< The starting address of the 16KB address space that
+                                                         is the BAR0 address space. */
+        uint64_t reserved_0_13           : 14;
+#else
+        uint64_t reserved_0_13           : 14;
+        uint64_t addr                    : 50;
+#endif
+    } s;
+    struct cvmx_pescx_p2n_bar0_start_s   cn52xx;
+    struct cvmx_pescx_p2n_bar0_start_s   cn52xxp1;
+    struct cvmx_pescx_p2n_bar0_start_s   cn56xx;
+    struct cvmx_pescx_p2n_bar0_start_s   cn56xxp1;
+} cvmx_pescx_p2n_bar0_start_t;
+
+
+/**
+ * cvmx_pesc#_p2n_bar1_start
+ *
+ * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start
+ * 
+ * The starting address for addresses to forwarded to the NPEI in RC Mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_p2n_bar1_start_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 38;      /**< The starting address of the 64KB address space
+                                                         that is the BAR1 address space. */
+        uint64_t reserved_0_25           : 26;
+#else
+        uint64_t reserved_0_25           : 26;
+        uint64_t addr                    : 38;
+#endif
+    } s;
+    struct cvmx_pescx_p2n_bar1_start_s   cn52xx;
+    struct cvmx_pescx_p2n_bar1_start_s   cn52xxp1;
+    struct cvmx_pescx_p2n_bar1_start_s   cn56xx;
+    struct cvmx_pescx_p2n_bar1_start_s   cn56xxp1;
+} cvmx_pescx_p2n_bar1_start_t;
+
+
+/**
+ * cvmx_pesc#_p2n_bar2_start
+ *
+ * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start
+ * 
+ * The starting address for addresses to forwarded to the NPEI in RC Mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_p2n_bar2_start_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 25;      /**< The starting address of the 2^39 address space
+                                                         that is the BAR2 address space. */
+        uint64_t reserved_0_38           : 39;
+#else
+        uint64_t reserved_0_38           : 39;
+        uint64_t addr                    : 25;
+#endif
+    } s;
+    struct cvmx_pescx_p2n_bar2_start_s   cn52xx;
+    struct cvmx_pescx_p2n_bar2_start_s   cn52xxp1;
+    struct cvmx_pescx_p2n_bar2_start_s   cn56xx;
+    struct cvmx_pescx_p2n_bar2_start_s   cn56xxp1;
+} cvmx_pescx_p2n_bar2_start_t;
+
+
+/**
+ * cvmx_pesc#_p2p_bar#_end
+ *
+ * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End
+ * 
+ * The ending address for addresses to forwarded to the PCIe peer port.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_p2p_barx_end_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 52;      /**< The ending address of the address window created
+                                                         this field and the PESC_P2P_BAR0_START[63:12]
+                                                         field. The full 64-bits of address are created by:
+                                                         [ADDR[63:12], 12'b0]. */
+        uint64_t reserved_0_11           : 12;
+#else
+        uint64_t reserved_0_11           : 12;
+        uint64_t addr                    : 52;
+#endif
+    } s;
+    struct cvmx_pescx_p2p_barx_end_s     cn52xx;
+    struct cvmx_pescx_p2p_barx_end_s     cn52xxp1;
+    struct cvmx_pescx_p2p_barx_end_s     cn56xx;
+    struct cvmx_pescx_p2p_barx_end_s     cn56xxp1;
+} cvmx_pescx_p2p_barx_end_t;
+
+
+/**
+ * cvmx_pesc#_p2p_bar#_start
+ *
+ * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start
+ * 
+ * The starting address and enable for addresses to forwarded to the PCIe peer port.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_p2p_barx_start_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t addr                    : 52;      /**< The starting address of the address window created
+                                                         this field and the PESC_P2P_BAR0_END[63:12] field.
+                                                         The full 64-bits of address are created by:
+                                                         [ADDR[63:12], 12'b0]. */
+        uint64_t reserved_0_11           : 12;
+#else
+        uint64_t reserved_0_11           : 12;
+        uint64_t addr                    : 52;
+#endif
+    } s;
+    struct cvmx_pescx_p2p_barx_start_s   cn52xx;
+    struct cvmx_pescx_p2p_barx_start_s   cn52xxp1;
+    struct cvmx_pescx_p2p_barx_start_s   cn56xx;
+    struct cvmx_pescx_p2p_barx_start_s   cn56xxp1;
+} cvmx_pescx_p2p_barx_start_t;
+
+
+/**
+ * cvmx_pesc#_tlp_credits
+ *
+ * PESC_TLP_CREDITS = PESC TLP Credits
+ * 
+ * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are
+ * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pescx_tlp_credits_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pescx_tlp_credits_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t peai_ppf                : 8;       /**< TLP credits for Completion TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+        uint64_t pesc_cpl                : 8;       /**< TLP credits for Completion TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+        uint64_t pesc_np                 : 8;       /**< TLP credits for Non-Posted TLPs in the Peer.
+                                                         Legal values are 0x4 to 0x10. */
+        uint64_t pesc_p                  : 8;       /**< TLP credits for Posted TLPs in the Peer.
+                                                         Legal values are 0x24 to 0x80. */
+        uint64_t npei_cpl                : 8;       /**< TLP credits for Completion TLPs in the NPEI.
+                                                         Legal values are 0x24 to 0x80. */
+        uint64_t npei_np                 : 8;       /**< TLP credits for Non-Posted TLPs in the NPEI.
+                                                         Legal values are 0x4 to 0x10. */
+        uint64_t npei_p                  : 8;       /**< TLP credits for Posted TLPs in the NPEI.
+                                                         Legal values are 0x24 to 0x80. */
+#else
+        uint64_t npei_p                  : 8;
+        uint64_t npei_np                 : 8;
+        uint64_t npei_cpl                : 8;
+        uint64_t pesc_p                  : 8;
+        uint64_t pesc_np                 : 8;
+        uint64_t pesc_cpl                : 8;
+        uint64_t peai_ppf                : 8;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } cn52xx;
+    struct cvmx_pescx_tlp_credits_cn52xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t peai_ppf                : 8;       /**< TLP credits in core clk pre-buffer that holds TLPs
+                                                         being sent from PCIe Core to NPEI or PEER. */
+        uint64_t pesc_cpl                : 5;       /**< TLP credits for Completion TLPs in the Peer. */
+        uint64_t pesc_np                 : 5;       /**< TLP credits for Non-Posted TLPs in the Peer. */
+        uint64_t pesc_p                  : 5;       /**< TLP credits for Posted TLPs in the Peer. */
+        uint64_t npei_cpl                : 5;       /**< TLP credits for Completion TLPs in the NPEI. */
+        uint64_t npei_np                 : 5;       /**< TLP credits for Non-Posted TLPs in the NPEI. */
+        uint64_t npei_p                  : 5;       /**< TLP credits for Posted TLPs in the NPEI. */
+#else
+        uint64_t npei_p                  : 5;
+        uint64_t npei_np                 : 5;
+        uint64_t npei_cpl                : 5;
+        uint64_t pesc_p                  : 5;
+        uint64_t pesc_np                 : 5;
+        uint64_t pesc_cpl                : 5;
+        uint64_t peai_ppf                : 8;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } cn52xxp1;
+    struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
+    struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
+} cvmx_pescx_tlp_credits_t;
+
+
+/**
+ * cvmx_pip_bck_prs
+ *
+ * PIP_BCK_PRS = PIP's Back Pressure Register
+ * 
+ * When to assert backpressure based on the todo list filling up
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_bck_prs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bckprs                  : 1;       /**< PIP is currently asserting backpressure to IOB
+                                                         Backpressure from PIP will assert when the
+                                                         entries to the todo list exceed HIWATER.
+                                                         Backpressure will be held until the todo entries
+                                                         is less than or equal to LOWATER. */
+        uint64_t reserved_13_62          : 50;
+        uint64_t hiwater                 : 5;       /**< Water mark in the todo list to assert backpressure
+                                                         Legal values are 1-26.  A 0 value will deadlock
+                                                         the machine.  A value > 26, will trash memory */
+        uint64_t reserved_5_7            : 3;
+        uint64_t lowater                 : 5;       /**< Water mark in the todo list to release backpressure
+                                                         The LOWATER value should be < HIWATER. */
+#else
+        uint64_t lowater                 : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t hiwater                 : 5;
+        uint64_t reserved_13_62          : 50;
+        uint64_t bckprs                  : 1;
+#endif
+    } s;
+    struct cvmx_pip_bck_prs_s            cn38xx;
+    struct cvmx_pip_bck_prs_s            cn38xxp2;
+    struct cvmx_pip_bck_prs_s            cn56xx;
+    struct cvmx_pip_bck_prs_s            cn56xxp1;
+    struct cvmx_pip_bck_prs_s            cn58xx;
+    struct cvmx_pip_bck_prs_s            cn58xxp1;
+} cvmx_pip_bck_prs_t;
+
+
+/**
+ * cvmx_pip_bist_status
+ *
+ * PIP_BIST_STATUS = PIP's BIST Results
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t bist                    : 18;      /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+        uint64_t bist                    : 18;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_pip_bist_status_s        cn30xx;
+    struct cvmx_pip_bist_status_s        cn31xx;
+    struct cvmx_pip_bist_status_s        cn38xx;
+    struct cvmx_pip_bist_status_s        cn38xxp2;
+    struct cvmx_pip_bist_status_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t bist                    : 17;      /**< BIST Results.
+                                                         HW sets a bit in BIST for for memory that fails
+                                                         BIST. */
+#else
+        uint64_t bist                    : 17;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn50xx;
+    struct cvmx_pip_bist_status_s        cn52xx;
+    struct cvmx_pip_bist_status_s        cn52xxp1;
+    struct cvmx_pip_bist_status_s        cn56xx;
+    struct cvmx_pip_bist_status_s        cn56xxp1;
+    struct cvmx_pip_bist_status_s        cn58xx;
+    struct cvmx_pip_bist_status_s        cn58xxp1;
+} cvmx_pip_bist_status_t;
+
+
+/**
+ * cvmx_pip_crc_ctl#
+ *
+ * PIP_CRC_CTL = PIP CRC Control Register
+ * 
+ * Controls datapath reflection when calculating CRC
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_crc_ctlx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t invres                  : 1;       /**< Invert the result */
+        uint64_t reflect                 : 1;       /**< Reflect the bits in each byte.
+                                                          Byte order does not change.
+                                                         - 0: CRC is calculated MSB to LSB
+                                                         - 1: CRC is calculated LSB to MSB */
+#else
+        uint64_t reflect                 : 1;
+        uint64_t invres                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pip_crc_ctlx_s           cn38xx;
+    struct cvmx_pip_crc_ctlx_s           cn38xxp2;
+    struct cvmx_pip_crc_ctlx_s           cn58xx;
+    struct cvmx_pip_crc_ctlx_s           cn58xxp1;
+} cvmx_pip_crc_ctlx_t;
+
+
+/**
+ * cvmx_pip_crc_iv#
+ *
+ * PIP_CRC_IV = PIP CRC IV Register
+ * 
+ * Determines the IV used by the CRC algorithm
+ *
+ * Notes:
+ * * PIP_CRC_IV
+ * PIP_CRC_IV controls the initial state of the CRC algorithm.  Octane can
+ * support a wide range of CRC algorithms and as such, the IV must be
+ * carefully constructed to meet the specific algorithm.  The code below
+ * determines the value to program into Octane based on the algorthim's IV
+ * and width.  In the case of Octane, the width should always be 32.
+ * 
+ * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for
+ * ports 16-31.
+ * 
+ *  unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
+ *  [
+ *    int i;
+ *    int doit;
+ *    unsigned int current_val = algorithm_iv;
+ * 
+ *    for(i = 0; i < w; i++) [
+ *      doit = current_val & 0x1;
+ * 
+ *      if(doit) current_val ^= poly;
+ *      assert(!(current_val & 0x1));
+ * 
+ *      current_val = (current_val >> 1) | (doit << (w-1));
+ *    ]
+ * 
+ *    return current_val;
+ *  ]
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_crc_ivx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iv                      : 32;      /**< IV used by the CRC algorithm.  Default is FCS32. */
+#else
+        uint64_t iv                      : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pip_crc_ivx_s            cn38xx;
+    struct cvmx_pip_crc_ivx_s            cn38xxp2;
+    struct cvmx_pip_crc_ivx_s            cn58xx;
+    struct cvmx_pip_crc_ivx_s            cn58xxp1;
+} cvmx_pip_crc_ivx_t;
+
+
+/**
+ * cvmx_pip_dec_ipsec#
+ *
+ * PIP_DEC_IPSEC = UDP or TCP ports to watch for DEC IPSEC
+ * 
+ * PIP sets the dec_ipsec based on TCP or UDP destination port.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_dec_ipsecx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t tcp                     : 1;       /**< This DPRT should be used for TCP packets */
+        uint64_t udp                     : 1;       /**< This DPRT should be used for UDP packets */
+        uint64_t dprt                    : 16;      /**< UDP or TCP destination port to match on */
+#else
+        uint64_t dprt                    : 16;
+        uint64_t udp                     : 1;
+        uint64_t tcp                     : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_pip_dec_ipsecx_s         cn30xx;
+    struct cvmx_pip_dec_ipsecx_s         cn31xx;
+    struct cvmx_pip_dec_ipsecx_s         cn38xx;
+    struct cvmx_pip_dec_ipsecx_s         cn38xxp2;
+    struct cvmx_pip_dec_ipsecx_s         cn50xx;
+    struct cvmx_pip_dec_ipsecx_s         cn52xx;
+    struct cvmx_pip_dec_ipsecx_s         cn52xxp1;
+    struct cvmx_pip_dec_ipsecx_s         cn56xx;
+    struct cvmx_pip_dec_ipsecx_s         cn56xxp1;
+    struct cvmx_pip_dec_ipsecx_s         cn58xx;
+    struct cvmx_pip_dec_ipsecx_s         cn58xxp1;
+} cvmx_pip_dec_ipsecx_t;
+
+
+/**
+ * cvmx_pip_dsa_src_grp
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_dsa_src_grp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t map15                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map14                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map13                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map12                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map11                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map10                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map9                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map8                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map7                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map6                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map5                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map4                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map3                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map2                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map1                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map0                    : 4;       /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP
+                                                         (56xx pass2 only) */
+#else
+        uint64_t map0                    : 4;
+        uint64_t map1                    : 4;
+        uint64_t map2                    : 4;
+        uint64_t map3                    : 4;
+        uint64_t map4                    : 4;
+        uint64_t map5                    : 4;
+        uint64_t map6                    : 4;
+        uint64_t map7                    : 4;
+        uint64_t map8                    : 4;
+        uint64_t map9                    : 4;
+        uint64_t map10                   : 4;
+        uint64_t map11                   : 4;
+        uint64_t map12                   : 4;
+        uint64_t map13                   : 4;
+        uint64_t map14                   : 4;
+        uint64_t map15                   : 4;
+#endif
+    } s;
+    struct cvmx_pip_dsa_src_grp_s        cn52xx;
+    struct cvmx_pip_dsa_src_grp_s        cn52xxp1;
+    struct cvmx_pip_dsa_src_grp_s        cn56xx;
+} cvmx_pip_dsa_src_grp_t;
+
+
+/**
+ * cvmx_pip_dsa_vid_grp
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_dsa_vid_grp_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t map15                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map14                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map13                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map12                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map11                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map10                   : 4;       /**< DSA Group Algorithm */
+        uint64_t map9                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map8                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map7                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map6                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map5                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map4                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map3                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map2                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map1                    : 4;       /**< DSA Group Algorithm */
+        uint64_t map0                    : 4;       /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP
+                                                         (56xx pass2 only) */
+#else
+        uint64_t map0                    : 4;
+        uint64_t map1                    : 4;
+        uint64_t map2                    : 4;
+        uint64_t map3                    : 4;
+        uint64_t map4                    : 4;
+        uint64_t map5                    : 4;
+        uint64_t map6                    : 4;
+        uint64_t map7                    : 4;
+        uint64_t map8                    : 4;
+        uint64_t map9                    : 4;
+        uint64_t map10                   : 4;
+        uint64_t map11                   : 4;
+        uint64_t map12                   : 4;
+        uint64_t map13                   : 4;
+        uint64_t map14                   : 4;
+        uint64_t map15                   : 4;
+#endif
+    } s;
+    struct cvmx_pip_dsa_vid_grp_s        cn52xx;
+    struct cvmx_pip_dsa_vid_grp_s        cn52xxp1;
+    struct cvmx_pip_dsa_vid_grp_s        cn56xx;
+} cvmx_pip_dsa_vid_grp_t;
+
+
+/**
+ * cvmx_pip_frm_len_chk#
+ *
+ * Notes:
+ * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, and PKO loopback ports.
+ * PIP_FRM_LEN_CHK1 is used for PCI RAW packets.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_frm_len_chkx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t maxlen                  : 16;      /**< Byte count for Max-sized frame check
+                                                         Failing packets set the MAXERR interrupt and are
+                                                         optionally sent with opcode==MAXERR
+                                                         The effective MAXLEN used by HW is
+                                                         PIP_FRM_LEN_CHK[MAXLEN] + 4*VV + 4*VS */
+        uint64_t minlen                  : 16;      /**< Byte count for Min-sized frame check
+                                                         Failing packets set the MINERR interrupt and are
+                                                         optionally sent with opcode==MINERR */
+#else
+        uint64_t minlen                  : 16;
+        uint64_t maxlen                  : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pip_frm_len_chkx_s       cn50xx;
+    struct cvmx_pip_frm_len_chkx_s       cn52xx;
+    struct cvmx_pip_frm_len_chkx_s       cn52xxp1;
+    struct cvmx_pip_frm_len_chkx_s       cn56xx;
+    struct cvmx_pip_frm_len_chkx_s       cn56xxp1;
+} cvmx_pip_frm_len_chkx_t;
+
+
+/**
+ * cvmx_pip_gbl_cfg
+ *
+ * PIP_GBL_CFG = PIP's Global Config Register
+ * 
+ * Global config information that applies to all ports.
+ *
+ * Notes:
+ * * IP6_UDP
+ * IPv4 allows optional UDP checksum by sending the all 0's patterns.  IPv6
+ * outlaws this and the spec says to always check UDP checksum.  This mode
+ * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's
+ * pattern will cause a UDP checksum pass.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_gbl_cfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_19_63          : 45;
+        uint64_t tag_syn                 : 1;       /**< Do not include src_crc for TCP/SYN&!ACK packets
+                                                         0 = include src_crc
+                                                         1 = tag hash is dst_crc for TCP/SYN&!ACK packets */
+        uint64_t ip6_udp                 : 1;       /**< IPv6/UDP checksum is not optional
+                                                         0 = Allow optional checksum code
+                                                         1 = Do not allow optional checksum code */
+        uint64_t max_l2                  : 1;       /**< Config bit to choose the largest L2 frame size
+                                                         Chooses the value of the L2 Type/Length field
+                                                         to classify the frame as length.
+                                                         0 = 1500 / 0x5dc
+                                                         1 = 1535 / 0x5ff */
+        uint64_t reserved_11_15          : 5;
+        uint64_t raw_shf                 : 3;       /**< RAW Packet shift amount
+                                                         Number of bytes to pad a packet that has been
+                                                         received on a PCI RAW port. */
+        uint64_t reserved_3_7            : 5;
+        uint64_t nip_shf                 : 3;       /**< Non-IP shift amount
+                                                         Number of bytes to pad a packet that has been
+                                                         classified as not IP. */
+#else
+        uint64_t nip_shf                 : 3;
+        uint64_t reserved_3_7            : 5;
+        uint64_t raw_shf                 : 3;
+        uint64_t reserved_11_15          : 5;
+        uint64_t max_l2                  : 1;
+        uint64_t ip6_udp                 : 1;
+        uint64_t tag_syn                 : 1;
+        uint64_t reserved_19_63          : 45;
+#endif
+    } s;
+    struct cvmx_pip_gbl_cfg_s            cn30xx;
+    struct cvmx_pip_gbl_cfg_s            cn31xx;
+    struct cvmx_pip_gbl_cfg_s            cn38xx;
+    struct cvmx_pip_gbl_cfg_s            cn38xxp2;
+    struct cvmx_pip_gbl_cfg_s            cn50xx;
+    struct cvmx_pip_gbl_cfg_s            cn52xx;
+    struct cvmx_pip_gbl_cfg_s            cn52xxp1;
+    struct cvmx_pip_gbl_cfg_s            cn56xx;
+    struct cvmx_pip_gbl_cfg_s            cn56xxp1;
+    struct cvmx_pip_gbl_cfg_s            cn58xx;
+    struct cvmx_pip_gbl_cfg_s            cn58xxp1;
+} cvmx_pip_gbl_cfg_t;
+
+
+/**
+ * cvmx_pip_gbl_ctl
+ *
+ * PIP_GBL_CTL = PIP's Global Control Register
+ * 
+ * Global control information.  These are the global checker enables for
+ * IPv4/IPv6 and TCP/UDP parsing.  The enables effect all ports.
+ *
+ * Notes:
+ * The following text describes the conditions in which each checker will
+ * assert and flag an exception.  By disabling the checker, the exception will
+ * not be flagged and the packet will be parsed as best it can.  Note, by
+ * disabling conditions, packets can be parsed incorrectly (.i.e. IP_MAL and
+ * L4_MAL could cause bits to be seen in the wrong place.  IP_CHK and L4_CHK
+ * means that the packet was corrupted).
+ * 
+ * * IP_CHK
+ *   Indicates that an IPv4 packet contained an IPv4 header checksum
+ *   violations.  Only applies to packets classified as IPv4.
+ * 
+ * * IP_MAL
+ *   Indicates that the packet was malformed.  Malformed packets are defined as
+ *   packets that are not long enough to cover the IP header or not long enough
+ *   to cover the length in the IP header.
+ * 
+ * * IP_HOP
+ *   Indicates that the IPv4 TTL field or IPv6 HOP field is zero.
+ * 
+ * * IP4_OPTS
+ *   Indicates the presence of IPv4 options.  It is set when the length != 5.
+ *   This only applies to packets classified as IPv4.
+ * 
+ * * IP6_EEXT
+ *   Indicate the presence of IPv6 early extension headers.  These bits only
+ *   apply to packets classified as IPv6.  Bit 0 will flag early extensions
+ *   when next_header is any one of the following...
+ * 
+ *         - hop-by-hop (0)
+ *         - destination (60)
+ *         - routing (43)
+ * 
+ *   Bit 1 will flag early extentions when next_header is NOT any of the
+ *   following...
+ * 
+ *         - TCP (6)
+ *         - UDP (17)
+ *         - fragmentation (44)
+ *         - ICMP (58)
+ *         - IPSEC ESP (50)
+ *         - IPSEC AH (51)
+ *         - IPCOMP
+ * 
+ * * L4_MAL
+ *   Indicates that a TCP or UDP packet is not long enough to cover the TCP or
+ *   UDP header.
+ * 
+ * * L4_PRT
+ *   Indicates that a TCP or UDP packet has an illegal port number - either the
+ *   source or destination port is zero.
+ * 
+ * * L4_CHK
+ *   Indicates that a packet classified as either TCP or UDP contains an L4
+ *   checksum failure
+ * 
+ * * L4_LEN
+ *   Indicates that the TCP or UDP length does not match the the IP length.
+ * 
+ * * TCP_FLAG
+ *   Indicates any of the following conditions...
+ * 
+ *         [URG, ACK, PSH, RST, SYN, FIN] : tcp_flag
+ *         6'b000001: (FIN only)
+ *         6'b000000: (0)
+ *         6'bxxx1x1: (RST+FIN+*)
+ *         6'b1xxx1x: (URG+SYN+*)
+ *         6'bxxx11x: (RST+SYN+*)
+ *         6'bxxxx11: (SYN+FIN+*)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_gbl_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t dsa_grp_tvid            : 1;       /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP
+                                                         (56xx pass2 only) */
+        uint64_t dsa_grp_scmd            : 1;       /**< DSA Group Algorithm
+                                                         Use the DSA source id to compute GRP when the
+                                                         DSA tag command to TO_CPU
+                                                         (56xx pass2 only) */
+        uint64_t dsa_grp_sid             : 1;       /**< DSA Group Algorithm
+                                                         Use the DSA VLAN id to compute GRP
+                                                         (56xx pass2 only) */
+        uint64_t reserved_21_23          : 3;
+        uint64_t ring_en                 : 1;       /**< Enable PCIe ring information in WQE */
+        uint64_t reserved_17_19          : 3;
+        uint64_t ignrs                   : 1;       /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Only applies to the packet interface prts (0-31)
+                                                         (PASS2 only) */
+        uint64_t vs_wqe                  : 1;       /**< Which VLAN CFI and ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN
+                                                         (PASS2 only) */
+        uint64_t vs_qos                  : 1;       /**< Which VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN
+                                                         (PASS2 only) */
+        uint64_t l2_mal                  : 1;       /**< Enable L2 malformed packet check */
+        uint64_t tcp_flag                : 1;       /**< Enable TCP flags checks */
+        uint64_t l4_len                  : 1;       /**< Enable TCP/UDP length check */
+        uint64_t l4_chk                  : 1;       /**< Enable TCP/UDP checksum check */
+        uint64_t l4_prt                  : 1;       /**< Enable TCP/UDP illegal port check */
+        uint64_t l4_mal                  : 1;       /**< Enable TCP/UDP malformed packet check */
+        uint64_t reserved_6_7            : 2;
+        uint64_t ip6_eext                : 2;       /**< Enable IPv6 early extension headers */
+        uint64_t ip4_opts                : 1;       /**< Enable IPv4 options check */
+        uint64_t ip_hop                  : 1;       /**< Enable TTL (IPv4) / hop (IPv6) check */
+        uint64_t ip_mal                  : 1;       /**< Enable malformed check */
+        uint64_t ip_chk                  : 1;       /**< Enable IPv4 header checksum check */
+#else
+        uint64_t ip_chk                  : 1;
+        uint64_t ip_mal                  : 1;
+        uint64_t ip_hop                  : 1;
+        uint64_t ip4_opts                : 1;
+        uint64_t ip6_eext                : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t l4_mal                  : 1;
+        uint64_t l4_prt                  : 1;
+        uint64_t l4_chk                  : 1;
+        uint64_t l4_len                  : 1;
+        uint64_t tcp_flag                : 1;
+        uint64_t l2_mal                  : 1;
+        uint64_t vs_qos                  : 1;
+        uint64_t vs_wqe                  : 1;
+        uint64_t ignrs                   : 1;
+        uint64_t reserved_17_19          : 3;
+        uint64_t ring_en                 : 1;
+        uint64_t reserved_21_23          : 3;
+        uint64_t dsa_grp_sid             : 1;
+        uint64_t dsa_grp_scmd            : 1;
+        uint64_t dsa_grp_tvid            : 1;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } s;
+    struct cvmx_pip_gbl_ctl_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t ignrs                   : 1;       /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Only applies to the packet interface prts (0-31) */
+        uint64_t vs_wqe                  : 1;       /**< Which VLAN CFI and ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+        uint64_t vs_qos                  : 1;       /**< Which VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+        uint64_t l2_mal                  : 1;       /**< Enable L2 malformed packet check */
+        uint64_t tcp_flag                : 1;       /**< Enable TCP flags checks */
+        uint64_t l4_len                  : 1;       /**< Enable TCP/UDP length check */
+        uint64_t l4_chk                  : 1;       /**< Enable TCP/UDP checksum check */
+        uint64_t l4_prt                  : 1;       /**< Enable TCP/UDP illegal port check */
+        uint64_t l4_mal                  : 1;       /**< Enable TCP/UDP malformed packet check */
+        uint64_t reserved_6_7            : 2;
+        uint64_t ip6_eext                : 2;       /**< Enable IPv6 early extension headers */
+        uint64_t ip4_opts                : 1;       /**< Enable IPv4 options check */
+        uint64_t ip_hop                  : 1;       /**< Enable TTL (IPv4) / hop (IPv6) check */
+        uint64_t ip_mal                  : 1;       /**< Enable malformed check */
+        uint64_t ip_chk                  : 1;       /**< Enable IPv4 header checksum check */
+#else
+        uint64_t ip_chk                  : 1;
+        uint64_t ip_mal                  : 1;
+        uint64_t ip_hop                  : 1;
+        uint64_t ip4_opts                : 1;
+        uint64_t ip6_eext                : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t l4_mal                  : 1;
+        uint64_t l4_prt                  : 1;
+        uint64_t l4_chk                  : 1;
+        uint64_t l4_len                  : 1;
+        uint64_t tcp_flag                : 1;
+        uint64_t l2_mal                  : 1;
+        uint64_t vs_qos                  : 1;
+        uint64_t vs_wqe                  : 1;
+        uint64_t ignrs                   : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn30xx;
+    struct cvmx_pip_gbl_ctl_cn30xx       cn31xx;
+    struct cvmx_pip_gbl_ctl_cn30xx       cn38xx;
+    struct cvmx_pip_gbl_ctl_cn30xx       cn38xxp2;
+    struct cvmx_pip_gbl_ctl_cn30xx       cn50xx;
+    struct cvmx_pip_gbl_ctl_s            cn52xx;
+    struct cvmx_pip_gbl_ctl_s            cn52xxp1;
+    struct cvmx_pip_gbl_ctl_s            cn56xx;
+    struct cvmx_pip_gbl_ctl_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t ring_en                 : 1;       /**< Enable PCIe ring information in WQE */
+        uint64_t reserved_17_19          : 3;
+        uint64_t ignrs                   : 1;       /**< Ignore the PKT_INST_HDR[RS] bit when set
+                                                         Only applies to the packet interface prts (0-31) */
+        uint64_t vs_wqe                  : 1;       /**< Which VLAN CFI and ID to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+        uint64_t vs_qos                  : 1;       /**< Which VLAN priority to use when VLAN Stacking
+                                                         0=use the 1st (network order) VLAN
+                                                         1=use the 2nd (network order) VLAN */
+        uint64_t l2_mal                  : 1;       /**< Enable L2 malformed packet check */
+        uint64_t tcp_flag                : 1;       /**< Enable TCP flags checks */
+        uint64_t l4_len                  : 1;       /**< Enable TCP/UDP length check */
+        uint64_t l4_chk                  : 1;       /**< Enable TCP/UDP checksum check */
+        uint64_t l4_prt                  : 1;       /**< Enable TCP/UDP illegal port check */
+        uint64_t l4_mal                  : 1;       /**< Enable TCP/UDP malformed packet check */
+        uint64_t reserved_6_7            : 2;
+        uint64_t ip6_eext                : 2;       /**< Enable IPv6 early extension headers */
+        uint64_t ip4_opts                : 1;       /**< Enable IPv4 options check */
+        uint64_t ip_hop                  : 1;       /**< Enable TTL (IPv4) / hop (IPv6) check */
+        uint64_t ip_mal                  : 1;       /**< Enable malformed check */
+        uint64_t ip_chk                  : 1;       /**< Enable IPv4 header checksum check */
+#else
+        uint64_t ip_chk                  : 1;
+        uint64_t ip_mal                  : 1;
+        uint64_t ip_hop                  : 1;
+        uint64_t ip4_opts                : 1;
+        uint64_t ip6_eext                : 2;
+        uint64_t reserved_6_7            : 2;
+        uint64_t l4_mal                  : 1;
+        uint64_t l4_prt                  : 1;
+        uint64_t l4_chk                  : 1;
+        uint64_t l4_len                  : 1;
+        uint64_t tcp_flag                : 1;
+        uint64_t l2_mal                  : 1;
+        uint64_t vs_qos                  : 1;
+        uint64_t vs_wqe                  : 1;
+        uint64_t ignrs                   : 1;
+        uint64_t reserved_17_19          : 3;
+        uint64_t ring_en                 : 1;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } cn56xxp1;
+    struct cvmx_pip_gbl_ctl_cn30xx       cn58xx;
+    struct cvmx_pip_gbl_ctl_cn30xx       cn58xxp1;
+} cvmx_pip_gbl_ctl_t;
+
+
+/**
+ * cvmx_pip_hg_pri_qos
+ *
+ * Notes:
+ * This register controls accesses to the HG_QOS_TABLE.  To write an entry of
+ * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level,
+ * UP_QOS=1.  To read an entry of the table, write PIP_HG_PRI_QOS with
+ * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read
+ * PIP_HG_PRI_QOS.  The table data will be in PIP_HG_PRI_QOS[QOS].
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_hg_pri_qos_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t up_qos                  : 1;       /**< When written to '1', updates the entry in the
+                                                         HG_QOS_TABLE as specified by PRI to a value of
+                                                         QOS as follows
+                                                         HG_QOS_TABLE[PRI] = QOS */
+        uint64_t reserved_11_11          : 1;
+        uint64_t qos                     : 3;       /**< QOS Map level to priority
+                                                         (56xx pass2 only) */
+        uint64_t reserved_6_7            : 2;
+        uint64_t pri                     : 6;       /**< The priority level from HiGig header
+                                                         HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]]
+                                                         HiGig2       PRI = [DP[1:0], TC[3:0]]
+                                                         (56xx pass2 only) */
+#else
+        uint64_t pri                     : 6;
+        uint64_t reserved_6_7            : 2;
+        uint64_t qos                     : 3;
+        uint64_t reserved_11_11          : 1;
+        uint64_t up_qos                  : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_pip_hg_pri_qos_s         cn52xx;
+    struct cvmx_pip_hg_pri_qos_s         cn52xxp1;
+    struct cvmx_pip_hg_pri_qos_s         cn56xx;
+} cvmx_pip_hg_pri_qos_t;
+
+
+/**
+ * cvmx_pip_int_en
+ *
+ * PIP_INT_EN = PIP's Interrupt Enable Register
+ * 
+ * Determines if hardward should raise an interrupt to software
+ * when an exception event occurs.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t punyerr                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_pip_int_en_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow
+                                                         (not used in O2P) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure
+                                                         (not used in O2P) */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
+                                                         (not used in O2P) */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn30xx;
+    struct cvmx_pip_int_en_cn30xx        cn31xx;
+    struct cvmx_pip_int_en_cn30xx        cn38xx;
+    struct cvmx_pip_int_en_cn30xx        cn38xxp2;
+    struct cvmx_pip_int_en_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn50xx;
+    struct cvmx_pip_int_en_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t punyerr                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn52xx;
+    struct cvmx_pip_int_en_cn52xx        cn52xxp1;
+    struct cvmx_pip_int_en_s             cn56xx;
+    struct cvmx_pip_int_en_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
+                                                         (Disabled in 56xx) */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xxp1;
+    struct cvmx_pip_int_en_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+        uint64_t reserved_9_11           : 3;
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t punyerr                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn58xx;
+    struct cvmx_pip_int_en_cn30xx        cn58xxp1;
+} cvmx_pip_int_en_t;
+
+
+/**
+ * cvmx_pip_int_reg
+ *
+ * PIP_INT_REG = PIP's Interrupt Register
+ * 
+ * Any exception event that occurs is captured in the PIP_INT_REG.
+ * PIP_INT_REG will set the exception bit regardless of the value
+ * of PIP_INT_EN.  PIP_INT_EN only controls if an interrupt is
+ * raised to software.
+ *
+ * Notes:
+ * * TODOOVR
+ *   The PIP Todo list stores packets that have been received and require work
+ *   queue entry generation.
+ * 
+ * * SKPRUNT
+ *   If a packet size is less then the amount programmed in the per port
+ *   skippers, then there will be nothing to parse and the entire packet will
+ *   basically be skipped over.  This is probably not what the user desired, so
+ *   there is an indication to software.
+ * 
+ * * BADTAG
+ *   A tag is considered bad when it is resued by a new packet before it was
+ *   released by PIP.  PIP considers a tag released by one of two methods.
+ *   . QOS dropped so that it is released over the pip__ipd_release bus.
+ *   . WorkQ entry is validated by the pip__ipd_done signal
+ * 
+ * * PRTNXA
+ *   If PIP receives a packet that is not in the valid port range, the port
+ *   processed will be mapped into the valid port space (the mapping is
+ *   currently unpredictable) and the PRTNXA bit will be set.  PRTNXA will be
+ *   set for packets received under the following conditions:
+ * 
+ *   * packet ports (ports 0-31)
+ *     - GMX_INF_MODE[TYPE]==0 (SGMII), received port is 4-31
+ *     - GMX_INF_MODE[TYPE]==1 (XAUI),  received port is 1-31
+ *   * upper ports (pci and loopback ports 32-63)
+ *     - received port is 40-47 or 52-63
+ * 
+ * * BCKPRS
+ *   PIP can assert backpressure to the receive logic when the todo list
+ *   exceeds a high-water mark.  When this
+ *   occurs, PIP can raise an interrupt to software.
+ * 
+ * * PKTDRP
+ *   PIP can drop packets based on QOS results received from IPD.  If the QOS
+ *   algorithm decides to drop a packet, PIP will assert an interrupt.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t punyerr                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_pip_int_reg_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow
+                                                         (not used in O2P) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure
+                                                         (not used in O2P) */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
+                                                         (not used in O2P) */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn30xx;
+    struct cvmx_pip_int_reg_cn30xx       cn31xx;
+    struct cvmx_pip_int_reg_cn30xx       cn38xx;
+    struct cvmx_pip_int_reg_cn30xx       cn38xxp2;
+    struct cvmx_pip_int_reg_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn50xx;
+    struct cvmx_pip_int_reg_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t reserved_1_1            : 1;
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t reserved_1_1            : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t punyerr                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn52xx;
+    struct cvmx_pip_int_reg_cn52xx       cn52xxp1;
+    struct cvmx_pip_int_reg_s            cn56xx;
+    struct cvmx_pip_int_reg_cn56xxp1
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t lenerr                  : 1;       /**< Frame was received with length error */
+        uint64_t maxerr                  : 1;       /**< Frame was received with length > max_length */
+        uint64_t minerr                  : 1;       /**< Frame was received with length < min_length */
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC
+                                                         (Disabled in 56xx) */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t minerr                  : 1;
+        uint64_t maxerr                  : 1;
+        uint64_t lenerr                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } cn56xxp1;
+    struct cvmx_pip_int_reg_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t punyerr                 : 1;       /**< Frame was received with length <=4B when CRC
+                                                         stripping in IPD is enable */
+        uint64_t reserved_9_11           : 3;
+        uint64_t beperr                  : 1;       /**< Parity Error in back end memory */
+        uint64_t feperr                  : 1;       /**< Parity Error in front end memory */
+        uint64_t todoovr                 : 1;       /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */
+        uint64_t skprunt                 : 1;       /**< Packet was engulfed by skipper
+                                                         This interrupt can occur with received PARTIAL
+                                                         packets that are truncated to SKIP bytes or
+                                                         smaller. */
+        uint64_t badtag                  : 1;       /**< A bad tag was sent from IPD */
+        uint64_t prtnxa                  : 1;       /**< Non-existent port */
+        uint64_t bckprs                  : 1;       /**< PIP asserted backpressure */
+        uint64_t crcerr                  : 1;       /**< PIP calculated bad CRC */
+        uint64_t pktdrp                  : 1;       /**< Packet Dropped due to QOS */
+#else
+        uint64_t pktdrp                  : 1;
+        uint64_t crcerr                  : 1;
+        uint64_t bckprs                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t badtag                  : 1;
+        uint64_t skprunt                 : 1;
+        uint64_t todoovr                 : 1;
+        uint64_t feperr                  : 1;
+        uint64_t beperr                  : 1;
+        uint64_t reserved_9_11           : 3;
+        uint64_t punyerr                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } cn58xx;
+    struct cvmx_pip_int_reg_cn30xx       cn58xxp1;
+} cvmx_pip_int_reg_t;
+
+
+/**
+ * cvmx_pip_ip_offset
+ *
+ * PIP_IP_OFFSET = Location of the IP in the workQ entry
+ * 
+ * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires
+ *
+ * Notes:
+ * In normal configurations, OFFSET must be set in the 0..4 range to allow the
+ * entire IP and TCP/UDP headers to be buffered in HW and calculate the L4
+ * checksum for TCP/UDP packets.
+ * 
+ * The MAX value of OFFSET is determined by the the types of packets that can
+ * be sent to PIP as follows...
+ * 
+ * Packet Type              MAX OFFSET
+ * IPv4/TCP/UDP             7
+ * IPv6/TCP/UDP             5
+ * IPv6/without L4 parsing  6
+ * 
+ * If the L4 can be ignored, then the MAX OFFSET for IPv6 packets can increase
+ * to 6.  Here are the following programming restrictions for IPv6 packets and
+ * OFFSET==6:
+ * 
+ *  . PIP_GBL_CTL[TCP_FLAG] == 0
+ *  . PIP_GBL_CTL[L4_LEN]   == 0
+ *  . PIP_GBL_CTL[L4_CHK]   == 0
+ *  . PIP_GBL_CTL[L4_PRT]   == 0
+ *  . PIP_GBL_CTL[L4_MAL]   == 0
+ *  . PIP_DEC_IPSEC[TCP]    == 0
+ *  . PIP_DEC_IPSEC[UDP]    == 0
+ *  . PIP_PRT_TAG[IP6_DPRT] == 0
+ *  . PIP_PRT_TAG[IP6_SPRT] == 0
+ *  . PIP_PRT_TAG[TCP6_TAG] == 0
+ *  . PIP_GBL_CFG[TAG_SYN]  == 0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_ip_offset_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t offset                  : 3;       /**< Number of 8B ticks to include in workQ entry
+                                                          prior to IP data
+                                                         - 0:  0 Bytes / IP start at WORD4 of workQ entry
+                                                         - 1:  8 Bytes / IP start at WORD5 of workQ entry
+                                                         - 2: 16 Bytes / IP start at WORD6 of workQ entry
+                                                         - 3: 24 Bytes / IP start at WORD7 of workQ entry
+                                                         - 4: 32 Bytes / IP start at WORD8 of workQ entry
+                                                         - 5: 40 Bytes / IP start at WORD9 of workQ entry
+                                                         - 6: 48 Bytes / IP start at WORD10 of workQ entry
+                                                         - 7: 56 Bytes / IP start at WORD11 of workQ entry */
+#else
+        uint64_t offset                  : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_pip_ip_offset_s          cn30xx;
+    struct cvmx_pip_ip_offset_s          cn31xx;
+    struct cvmx_pip_ip_offset_s          cn38xx;
+    struct cvmx_pip_ip_offset_s          cn38xxp2;
+    struct cvmx_pip_ip_offset_s          cn50xx;
+    struct cvmx_pip_ip_offset_s          cn52xx;
+    struct cvmx_pip_ip_offset_s          cn52xxp1;
+    struct cvmx_pip_ip_offset_s          cn56xx;
+    struct cvmx_pip_ip_offset_s          cn56xxp1;
+    struct cvmx_pip_ip_offset_s          cn58xx;
+    struct cvmx_pip_ip_offset_s          cn58xxp1;
+} cvmx_pip_ip_offset_t;
+
+
+/**
+ * cvmx_pip_prt_cfg#
+ *
+ * PIP_PRT_CFGX = Per port config information
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_prt_cfgx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_53_63          : 11;
+        uint64_t pad_len                 : 1;       /**< When set, disables the length check for pkts with
+                                                         padding in the client data */
+        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
+        uint64_t lenerr_en               : 1;       /**< L2 length error check enable
+                                                         Frame was received with length error */
+        uint64_t maxerr_en               : 1;       /**< Max frame error check enable
+                                                         Frame was received with length > max_length */
+        uint64_t minerr_en               : 1;       /**< Min frame error check enable
+                                                         Frame was received with length < min_length */
+        uint64_t grp_wat_47              : 4;       /**< GRP Watcher enable
+                                                         (Watchers 4-7) */
+        uint64_t qos_wat_47              : 4;       /**< QOS Watcher enable
+                                                         (Watchers 4-7) */
+        uint64_t reserved_37_39          : 3;
+        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm
+                                                         (PASS2 only) */
+        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash
+                                                         (PASS2 only) */
+        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size
+                                                         (PASS2 only) */
+        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35)
+                                                         (PASS2 only) */
+        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable
+                                                         (PASS2 only) */
+        uint64_t hg_qos                  : 1;       /**< When set, uses the HiGig priority bits as a
+                                                         lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS)
+                                                         to determine the QOS value
+                                                         HG_QOS must not be set when HIGIG_EN=0
+                                                         (56xx pass2 only) */
+        uint64_t qos                     : 3;       /**< Default QOS level of the port */
+        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
+        uint64_t qos_vsel                : 1;       /**< Which QOS in PIP_QOS_VLAN to use
+                                                         0 = PIP_QOS_VLAN[QOS]
+                                                         1 = PIP_QOS_VLAN[QOS1]
+                                                         (56xx pass2 only) */
+        uint64_t qos_vod                 : 1;       /**< QOS VLAN over Diffserv
+                                                         if VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
+        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
+        uint64_t reserved_13_15          : 3;
+        uint64_t crc_en                  : 1;       /**< CRC Checking enabled (for ports 0-31 only) */
+        uint64_t higig_en                : 1;       /**< Enable HiGig parsing
+                                                         Should not be set for PCIe ports (ports 32-35)
+                                                         When HIGIG_EN=1:
+                                                          DSA_EN field below must be zero
+                                                          SKIP field below is both Skip I size and the
+                                                            size of the HiGig* header (12 or 16 bytes)
+                                                         (56xx pass2 only) */
+        uint64_t dsa_en                  : 1;       /**< Enable DSA tag parsing
+                                                         When DSA_EN=1:
+                                                          HIGIG_EN field above must be zero
+                                                          SKIP field below is size of DSA tag (4, 8, or
+                                                            12 bytes) rather than the size of Skip I
+                                                          total SKIP (Skip I + header + Skip II
+                                                            must be zero
+                                                          INST_HDR field above must be zero (non-PCIe
+                                                            ports)
+                                                          For PCIe ports, NPEI_PKT*_INSTR_HDR[USE_IHDR]
+                                                            and PCIE_INST_HDR[R] should be clear
+                                                          MODE field below must be "skip to L2"
+                                                         (56xx pass2 only) */
+        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+        uint64_t skip                    : 7;
+        uint64_t reserved_7_7            : 1;
+        cvmx_pip_port_parse_mode_t mode  : 2;
+        uint64_t dsa_en                  : 1;
+        uint64_t higig_en                : 1;
+        uint64_t crc_en                  : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t qos_vlan                : 1;
+        uint64_t qos_diff                : 1;
+        uint64_t qos_vod                 : 1;
+        uint64_t qos_vsel                : 1;
+        uint64_t qos_wat                 : 4;
+        uint64_t qos                     : 3;
+        uint64_t hg_qos                  : 1;
+        uint64_t grp_wat                 : 4;
+        uint64_t inst_hdr                : 1;
+        uint64_t dyn_rs                  : 1;
+        uint64_t tag_inc                 : 2;
+        uint64_t rawdrp                  : 1;
+        uint64_t reserved_37_39          : 3;
+        uint64_t qos_wat_47              : 4;
+        uint64_t grp_wat_47              : 4;
+        uint64_t minerr_en               : 1;
+        uint64_t maxerr_en               : 1;
+        uint64_t lenerr_en               : 1;
+        uint64_t vlan_len                : 1;
+        uint64_t pad_len                 : 1;
+        uint64_t reserved_53_63          : 11;
+#endif
+    } s;
+    struct cvmx_pip_prt_cfgx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size */
+        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35) */
+        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable */
+        uint64_t reserved_27_27          : 1;
+        uint64_t qos                     : 3;       /**< Default QOS level of the port */
+        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
+        uint64_t reserved_18_19          : 2;
+        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
+        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
+        uint64_t reserved_10_15          : 6;
+        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+        uint64_t skip                    : 7;
+        uint64_t reserved_7_7            : 1;
+        cvmx_pip_port_parse_mode_t mode  : 2;
+        uint64_t reserved_10_15          : 6;
+        uint64_t qos_vlan                : 1;
+        uint64_t qos_diff                : 1;
+        uint64_t reserved_18_19          : 2;
+        uint64_t qos_wat                 : 4;
+        uint64_t qos                     : 3;
+        uint64_t reserved_27_27          : 1;
+        uint64_t grp_wat                 : 4;
+        uint64_t inst_hdr                : 1;
+        uint64_t dyn_rs                  : 1;
+        uint64_t tag_inc                 : 2;
+        uint64_t rawdrp                  : 1;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } cn30xx;
+    struct cvmx_pip_prt_cfgx_cn30xx      cn31xx;
+    struct cvmx_pip_prt_cfgx_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm
+                                                         (PASS2 only) */
+        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash
+                                                         (PASS2 only) */
+        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size
+                                                         (PASS2 only) */
+        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35)
+                                                         (PASS2 only) */
+        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable
+                                                         (PASS2 only) */
+        uint64_t reserved_27_27          : 1;
+        uint64_t qos                     : 3;       /**< Default QOS level of the port */
+        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
+        uint64_t reserved_18_19          : 2;
+        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
+        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
+        uint64_t reserved_13_15          : 3;
+        uint64_t crc_en                  : 1;       /**< CRC Checking enabled (for ports 0-31 only) */
+        uint64_t reserved_10_11          : 2;
+        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+        uint64_t skip                    : 7;
+        uint64_t reserved_7_7            : 1;
+        cvmx_pip_port_parse_mode_t mode  : 2;
+        uint64_t reserved_10_11          : 2;
+        uint64_t crc_en                  : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t qos_vlan                : 1;
+        uint64_t qos_diff                : 1;
+        uint64_t reserved_18_19          : 2;
+        uint64_t qos_wat                 : 4;
+        uint64_t qos                     : 3;
+        uint64_t reserved_27_27          : 1;
+        uint64_t grp_wat                 : 4;
+        uint64_t inst_hdr                : 1;
+        uint64_t dyn_rs                  : 1;
+        uint64_t tag_inc                 : 2;
+        uint64_t rawdrp                  : 1;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } cn38xx;
+    struct cvmx_pip_prt_cfgx_cn38xx      cn38xxp2;
+    struct cvmx_pip_prt_cfgx_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_53_63          : 11;
+        uint64_t pad_len                 : 1;       /**< When set, disables the length check for pkts with
+                                                         padding in the client data */
+        uint64_t vlan_len                : 1;       /**< When set, disables the length check for VLAN pkts */
+        uint64_t lenerr_en               : 1;       /**< L2 length error check enable
+                                                         Frame was received with length error */
+        uint64_t maxerr_en               : 1;       /**< Max frame error check enable
+                                                         Frame was received with length > max_length */
+        uint64_t minerr_en               : 1;       /**< Min frame error check enable
+                                                         Frame was received with length < min_length */
+        uint64_t grp_wat_47              : 4;       /**< GRP Watcher enable
+                                                         (Watchers 4-7) */
+        uint64_t qos_wat_47              : 4;       /**< QOS Watcher enable
+                                                         (Watchers 4-7) */
+        uint64_t reserved_37_39          : 3;
+        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm */
+        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash */
+        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size */
+        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35) */
+        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable */
+        uint64_t reserved_27_27          : 1;
+        uint64_t qos                     : 3;       /**< Default QOS level of the port */
+        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable
+                                                         (Watchers 0-3) */
+        uint64_t reserved_19_19          : 1;
+        uint64_t qos_vod                 : 1;       /**< QOS VLAN over Diffserv
+                                                         if VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
+        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
+        uint64_t reserved_13_15          : 3;
+        uint64_t crc_en                  : 1;       /**< CRC Checking enabled
+                                                         (Disabled in 5020) */
+        uint64_t reserved_10_11          : 2;
+        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+        uint64_t skip                    : 7;
+        uint64_t reserved_7_7            : 1;
+        cvmx_pip_port_parse_mode_t mode  : 2;
+        uint64_t reserved_10_11          : 2;
+        uint64_t crc_en                  : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t qos_vlan                : 1;
+        uint64_t qos_diff                : 1;
+        uint64_t qos_vod                 : 1;
+        uint64_t reserved_19_19          : 1;
+        uint64_t qos_wat                 : 4;
+        uint64_t qos                     : 3;
+        uint64_t reserved_27_27          : 1;
+        uint64_t grp_wat                 : 4;
+        uint64_t inst_hdr                : 1;
+        uint64_t dyn_rs                  : 1;
+        uint64_t tag_inc                 : 2;
+        uint64_t rawdrp                  : 1;
+        uint64_t reserved_37_39          : 3;
+        uint64_t qos_wat_47              : 4;
+        uint64_t grp_wat_47              : 4;
+        uint64_t minerr_en               : 1;
+        uint64_t maxerr_en               : 1;
+        uint64_t lenerr_en               : 1;
+        uint64_t vlan_len                : 1;
+        uint64_t pad_len                 : 1;
+        uint64_t reserved_53_63          : 11;
+#endif
+    } cn50xx;
+    struct cvmx_pip_prt_cfgx_s           cn52xx;
+    struct cvmx_pip_prt_cfgx_s           cn52xxp1;
+    struct cvmx_pip_prt_cfgx_s           cn56xx;
+    struct cvmx_pip_prt_cfgx_cn50xx      cn56xxp1;
+    struct cvmx_pip_prt_cfgx_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t rawdrp                  : 1;       /**< Allow the IPD to RED drop a packet.
+                                                         Normally, IPD will never drop a packet that PIP
+                                                         indicates is RAW.
+                                                         0=never drop RAW packets based on RED algorithm
+                                                         1=allow RAW packet drops based on RED algorithm
+                                                         (PASS2 only) */
+        uint64_t tag_inc                 : 2;       /**< Which of the 4 PIP_TAG_INC to use when
+                                                         calculating mask tag hash
+                                                         (PASS2 only) */
+        uint64_t dyn_rs                  : 1;       /**< Dynamically calculate RS based on pkt size
+                                                         (PASS2 only) */
+        uint64_t inst_hdr                : 1;       /**< 8-byte INST_HDR is present on all packets
+                                                         (not for PCI prts, 32-35)
+                                                         (PASS2 only) */
+        uint64_t grp_wat                 : 4;       /**< GRP Watcher enable
+                                                         (PASS2 only) */
+        uint64_t reserved_27_27          : 1;
+        uint64_t qos                     : 3;       /**< Default QOS level of the port */
+        uint64_t qos_wat                 : 4;       /**< QOS Watcher enable */
+        uint64_t reserved_19_19          : 1;
+        uint64_t qos_vod                 : 1;       /**< QOS VLAN over Diffserv
+                                                         if VLAN exists, it is used
+                                                         else if IP exists, Diffserv is used
+                                                         else the per port default is used
+                                                         Watchers are still highest priority */
+        uint64_t qos_diff                : 1;       /**< QOS Diffserv */
+        uint64_t qos_vlan                : 1;       /**< QOS VLAN */
+        uint64_t reserved_13_15          : 3;
+        uint64_t crc_en                  : 1;       /**< CRC Checking enabled (for ports 0-31 only) */
+        uint64_t reserved_10_11          : 2;
+        cvmx_pip_port_parse_mode_t mode  : 2;       /**< Parse Mode
+                                                         0 = no packet inspection (Uninterpreted)
+                                                         1 = L2 parsing / skip to L2
+                                                         2 = IP parsing / skip to L3
+                                                         3 = PCI Raw (illegal for software to set) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t skip                    : 7;       /**< Optional Skip I amount for packets.  Does not
+                                                         apply to packets on PCI ports when a PKT_INST_HDR
+                                                         is present.  See section 7.2.7 - Legal Skip
+                                                         Values for further details. */
+#else
+        uint64_t skip                    : 7;
+        uint64_t reserved_7_7            : 1;
+        cvmx_pip_port_parse_mode_t mode  : 2;
+        uint64_t reserved_10_11          : 2;
+        uint64_t crc_en                  : 1;
+        uint64_t reserved_13_15          : 3;
+        uint64_t qos_vlan                : 1;
+        uint64_t qos_diff                : 1;
+        uint64_t qos_vod                 : 1;
+        uint64_t reserved_19_19          : 1;
+        uint64_t qos_wat                 : 4;
+        uint64_t qos                     : 3;
+        uint64_t reserved_27_27          : 1;
+        uint64_t grp_wat                 : 4;
+        uint64_t inst_hdr                : 1;
+        uint64_t dyn_rs                  : 1;
+        uint64_t tag_inc                 : 2;
+        uint64_t rawdrp                  : 1;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } cn58xx;
+    struct cvmx_pip_prt_cfgx_cn58xx      cn58xxp1;
+} cvmx_pip_prt_cfgx_t;
+
+
+/**
+ * cvmx_pip_prt_tag#
+ *
+ * PIP_PRT_TAGX = Per port config information
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_prt_tagx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t grptagbase              : 4;       /**< Offset to use when computing group from tag bits
+                                                         when GRPTAG is set.
+                                                         (PASS2 only) */
+        uint64_t grptagmask              : 4;       /**< Which bits of the tag to exclude when computing
+                                                         group when GRPTAG is set.
+                                                         (PASS2 only) */
+        uint64_t grptag                  : 1;       /**< When set, use the lower bit of the tag to compute
+                                                         the group in the work queue entry
+                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE
+                                                         (PASS2 only) */
+        uint64_t grptag_mskip            : 1;       /**< When set, GRPTAG will be used regardless if the
+                                                         packet IS_IP. */
+        uint64_t tag_mode                : 2;       /**< Which tag algorithm to use
+                                                         0 = always use tuple tag algorithm
+                                                         1 = always use mask tag algorithm
+                                                         2 = if packet is IP, use tuple else use mask
+                                                         3 = tuple XOR mask
+                                                         (PASS2 only) */
+        uint64_t inc_vs                  : 2;       /**< determines the VLAN ID (VID) to be included in
+                                                         tuple tag when VLAN stacking is detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID (VLAN0) in hash
+                                                         2 = include VID (VLAN1) in hash
+                                                         3 = include VID ([VLAN0,VLAN1]) in hash
+                                                         (PASS2 only) */
+        uint64_t inc_vlan                : 1;       /**< when set, the VLAN ID is included in tuple tag
+                                                         when VLAN stacking is not detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID in hash
+                                                         (PASS2 only) */
+        uint64_t inc_prt_flag            : 1;       /**< sets whether the port is included in tuple tag */
+        uint64_t ip6_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv6 packets */
+        uint64_t ip4_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv4 */
+        uint64_t ip6_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv6 packets */
+        uint64_t ip4_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv4 */
+        uint64_t ip6_nxth_flag           : 1;       /**< sets whether ipv6 includes next header in tuple
+                                                         tag hash */
+        uint64_t ip4_pctl_flag           : 1;       /**< sets whether ipv4 includes protocol in tuple
+                                                         tag hash */
+        uint64_t ip6_dst_flag            : 1;       /**< sets whether ipv6 includes dst address in tuple
+                                                         tag hash */
+        uint64_t ip4_dst_flag            : 1;       /**< sets whether ipv4 includes dst address in tuple
+                                                         tag hash */
+        uint64_t ip6_src_flag            : 1;       /**< sets whether ipv6 includes src address in tuple
+                                                         tag hash */
+        uint64_t ip4_src_flag            : 1;       /**< sets whether ipv4 includes src address in tuple
+                                                         tag hash */
+        cvmx_pow_tag_type_t tcp6_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv6)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t tcp4_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv4)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t ip6_tag_type : 2;       /**< sets whether IPv6 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t ip4_tag_type : 2;       /**< sets whether IPv4 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t non_tag_type : 2;       /**< sets whether non-IP packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        uint64_t grp                     : 4;       /**< 4-bit value indicating the group to schedule to */
+#else
+        uint64_t grp                     : 4;
+        cvmx_pow_tag_type_t non_tag_type : 2;
+        cvmx_pow_tag_type_t ip4_tag_type : 2;
+        cvmx_pow_tag_type_t ip6_tag_type : 2;
+        cvmx_pow_tag_type_t tcp4_tag_type : 2;
+        cvmx_pow_tag_type_t tcp6_tag_type : 2;
+        uint64_t ip4_src_flag            : 1;
+        uint64_t ip6_src_flag            : 1;
+        uint64_t ip4_dst_flag            : 1;
+        uint64_t ip6_dst_flag            : 1;
+        uint64_t ip4_pctl_flag           : 1;
+        uint64_t ip6_nxth_flag           : 1;
+        uint64_t ip4_sprt_flag           : 1;
+        uint64_t ip6_sprt_flag           : 1;
+        uint64_t ip4_dprt_flag           : 1;
+        uint64_t ip6_dprt_flag           : 1;
+        uint64_t inc_prt_flag            : 1;
+        uint64_t inc_vlan                : 1;
+        uint64_t inc_vs                  : 2;
+        uint64_t tag_mode                : 2;
+        uint64_t grptag_mskip            : 1;
+        uint64_t grptag                  : 1;
+        uint64_t grptagmask              : 4;
+        uint64_t grptagbase              : 4;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_pip_prt_tagx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t grptagbase              : 4;       /**< Offset to use when computing group from tag bits
+                                                         when GRPTAG is set. */
+        uint64_t grptagmask              : 4;       /**< Which bits of the tag to exclude when computing
+                                                         group when GRPTAG is set. */
+        uint64_t grptag                  : 1;       /**< When set, use the lower bit of the tag to compute
+                                                         the group in the work queue entry
+                                                         GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */
+        uint64_t reserved_30_30          : 1;
+        uint64_t tag_mode                : 2;       /**< Which tag algorithm to use
+                                                         0 = always use tuple tag algorithm
+                                                         1 = always use mask tag algorithm
+                                                         2 = if packet is IP, use tuple else use mask
+                                                         3 = tuple XOR mask */
+        uint64_t inc_vs                  : 2;       /**< determines the VLAN ID (VID) to be included in
+                                                         tuple tag when VLAN stacking is detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID (VLAN0) in hash
+                                                         2 = include VID (VLAN1) in hash
+                                                         3 = include VID ([VLAN0,VLAN1]) in hash */
+        uint64_t inc_vlan                : 1;       /**< when set, the VLAN ID is included in tuple tag
+                                                         when VLAN stacking is not detected
+                                                         0 = do not include VID in tuple tag generation
+                                                         1 = include VID in hash */
+        uint64_t inc_prt_flag            : 1;       /**< sets whether the port is included in tuple tag */
+        uint64_t ip6_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv6 packets */
+        uint64_t ip4_dprt_flag           : 1;       /**< sets whether the TCP/UDP dst port is
+                                                         included in tuple tag for IPv4 */
+        uint64_t ip6_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv6 packets */
+        uint64_t ip4_sprt_flag           : 1;       /**< sets whether the TCP/UDP src port is
+                                                         included in tuple tag for IPv4 */
+        uint64_t ip6_nxth_flag           : 1;       /**< sets whether ipv6 includes next header in tuple
+                                                         tag hash */
+        uint64_t ip4_pctl_flag           : 1;       /**< sets whether ipv4 includes protocol in tuple
+                                                         tag hash */
+        uint64_t ip6_dst_flag            : 1;       /**< sets whether ipv6 includes dst address in tuple
+                                                         tag hash */
+        uint64_t ip4_dst_flag            : 1;       /**< sets whether ipv4 includes dst address in tuple
+                                                         tag hash */
+        uint64_t ip6_src_flag            : 1;       /**< sets whether ipv6 includes src address in tuple
+                                                         tag hash */
+        uint64_t ip4_src_flag            : 1;       /**< sets whether ipv4 includes src address in tuple
+                                                         tag hash */
+        cvmx_pow_tag_type_t tcp6_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv6)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t tcp4_tag_type : 2;      /**< sets the tag_type of a TCP packet (IPv4)
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t ip6_tag_type : 2;       /**< sets whether IPv6 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t ip4_tag_type : 2;       /**< sets whether IPv4 packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        cvmx_pow_tag_type_t non_tag_type : 2;       /**< sets whether non-IP packet tag type
+                                                         0 = ordered tags
+                                                         1 = atomic tags
+                                                         2 = Null tags */
+        uint64_t grp                     : 4;       /**< 4-bit value indicating the group to schedule to */
+#else
+        uint64_t grp                     : 4;
+        cvmx_pow_tag_type_t non_tag_type : 2;
+        cvmx_pow_tag_type_t ip4_tag_type : 2;
+        cvmx_pow_tag_type_t ip6_tag_type : 2;
+        cvmx_pow_tag_type_t tcp4_tag_type : 2;
+        cvmx_pow_tag_type_t tcp6_tag_type : 2;
+        uint64_t ip4_src_flag            : 1;
+        uint64_t ip6_src_flag            : 1;
+        uint64_t ip4_dst_flag            : 1;
+        uint64_t ip6_dst_flag            : 1;
+        uint64_t ip4_pctl_flag           : 1;
+        uint64_t ip6_nxth_flag           : 1;
+        uint64_t ip4_sprt_flag           : 1;
+        uint64_t ip6_sprt_flag           : 1;
+        uint64_t ip4_dprt_flag           : 1;
+        uint64_t ip6_dprt_flag           : 1;
+        uint64_t inc_prt_flag            : 1;
+        uint64_t inc_vlan                : 1;
+        uint64_t inc_vs                  : 2;
+        uint64_t tag_mode                : 2;
+        uint64_t reserved_30_30          : 1;
+        uint64_t grptag                  : 1;
+        uint64_t grptagmask              : 4;
+        uint64_t grptagbase              : 4;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } cn30xx;
+    struct cvmx_pip_prt_tagx_cn30xx      cn31xx;
+    struct cvmx_pip_prt_tagx_cn30xx      cn38xx;
+    struct cvmx_pip_prt_tagx_cn30xx      cn38xxp2;
+    struct cvmx_pip_prt_tagx_s           cn50xx;
+    struct cvmx_pip_prt_tagx_s           cn52xx;
+    struct cvmx_pip_prt_tagx_s           cn52xxp1;
+    struct cvmx_pip_prt_tagx_s           cn56xx;
+    struct cvmx_pip_prt_tagx_s           cn56xxp1;
+    struct cvmx_pip_prt_tagx_s           cn58xx;
+    struct cvmx_pip_prt_tagx_s           cn58xxp1;
+} cvmx_pip_prt_tagx_t;
+
+
+/**
+ * cvmx_pip_qos_diff#
+ *
+ * PIP_QOS_DIFFX = QOS Diffserv Tables
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_qos_diffx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t qos                     : 3;       /**< Diffserv QOS level */
+#else
+        uint64_t qos                     : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_pip_qos_diffx_s          cn30xx;
+    struct cvmx_pip_qos_diffx_s          cn31xx;
+    struct cvmx_pip_qos_diffx_s          cn38xx;
+    struct cvmx_pip_qos_diffx_s          cn38xxp2;
+    struct cvmx_pip_qos_diffx_s          cn50xx;
+    struct cvmx_pip_qos_diffx_s          cn52xx;
+    struct cvmx_pip_qos_diffx_s          cn52xxp1;
+    struct cvmx_pip_qos_diffx_s          cn56xx;
+    struct cvmx_pip_qos_diffx_s          cn56xxp1;
+    struct cvmx_pip_qos_diffx_s          cn58xx;
+    struct cvmx_pip_qos_diffx_s          cn58xxp1;
+} cvmx_pip_qos_diffx_t;
+
+
+/**
+ * cvmx_pip_qos_vlan#
+ *
+ * PIP_QOS_VLANX = QOS VLAN Tables
+ * 
+ * If the PIP indentifies a packet to be DSA/VLAN tagged, then the QOS
+ * can be set based on the DSA/VLAN user priority.  These eight register
+ * comprise the QOS values for all DSA/VLAN user priority values.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_qos_vlanx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t qos1                    : 3;       /**< DSA/VLAN QOS level
+                                                         Selected when PIP_PRT_CFGx[QOS_VSEL] = 1
+                                                         (56xx pass2 only) */
+        uint64_t reserved_3_3            : 1;
+        uint64_t qos                     : 3;       /**< VLAN QOS level */
+#else
+        uint64_t qos                     : 3;
+        uint64_t reserved_3_3            : 1;
+        uint64_t qos1                    : 3;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_pip_qos_vlanx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t qos                     : 3;       /**< VLAN QOS level */
+#else
+        uint64_t qos                     : 3;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn31xx;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn38xx;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn38xxp2;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn50xx;
+    struct cvmx_pip_qos_vlanx_s          cn52xx;
+    struct cvmx_pip_qos_vlanx_s          cn52xxp1;
+    struct cvmx_pip_qos_vlanx_s          cn56xx;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn56xxp1;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn58xx;
+    struct cvmx_pip_qos_vlanx_cn30xx     cn58xxp1;
+} cvmx_pip_qos_vlanx_t;
+
+
+/**
+ * cvmx_pip_qos_watch#
+ *
+ * PIP_QOS_WATCHX = QOS Watcher Tables
+ * 
+ * Sets up the Configuration CSRs for the four QOS Watchers.
+ * Each Watcher can be set to look for a specific protocol,
+ * TCP/UDP destination port, or Ethertype to override the
+ * default QOS value.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_qos_watchx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t mask                    : 16;      /**< Mask off a range of values (PASS2 only) */
+        uint64_t reserved_28_31          : 4;
+        uint64_t grp                     : 4;       /**< The GRP number of the watcher (PASS2 only) */
+        uint64_t reserved_23_23          : 1;
+        uint64_t qos                     : 3;       /**< The QOS level of the watcher */
+        uint64_t reserved_19_19          : 1;
+        cvmx_pip_qos_watch_types match_type : 3;    /**< The field for the watcher match against
+                                                         0 = disable across all ports
+                                                         1 = protocol (ipv4)
+                                                           = next_header (ipv6)
+                                                         2 = TCP destination port
+                                                         3 = UDP destination port */
+        uint64_t match_value             : 16;      /**< The value to watch for */
+#else
+        uint64_t match_value             : 16;
+        cvmx_pip_qos_watch_types match_type : 3;
+        uint64_t reserved_19_19          : 1;
+        uint64_t qos                     : 3;
+        uint64_t reserved_23_23          : 1;
+        uint64_t grp                     : 4;
+        uint64_t reserved_28_31          : 4;
+        uint64_t mask                    : 16;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_pip_qos_watchx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t mask                    : 16;      /**< Mask off a range of values */
+        uint64_t reserved_28_31          : 4;
+        uint64_t grp                     : 4;       /**< The GRP number of the watcher */
+        uint64_t reserved_23_23          : 1;
+        uint64_t qos                     : 3;       /**< The QOS level of the watcher */
+        uint64_t reserved_18_19          : 2;
+        cvmx_pip_qos_watch_types match_type : 2;    /**< The field for the watcher match against
+                                                         0 = disable across all ports
+                                                         1 = protocol (ipv4)
+                                                           = next_header (ipv6)
+                                                         2 = TCP destination port
+                                                         3 = UDP destination port */
+        uint64_t match_value             : 16;      /**< The value to watch for */
+#else
+        uint64_t match_value             : 16;
+        cvmx_pip_qos_watch_types match_type : 2;
+        uint64_t reserved_18_19          : 2;
+        uint64_t qos                     : 3;
+        uint64_t reserved_23_23          : 1;
+        uint64_t grp                     : 4;
+        uint64_t reserved_28_31          : 4;
+        uint64_t mask                    : 16;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } cn30xx;
+    struct cvmx_pip_qos_watchx_cn30xx    cn31xx;
+    struct cvmx_pip_qos_watchx_cn30xx    cn38xx;
+    struct cvmx_pip_qos_watchx_cn30xx    cn38xxp2;
+    struct cvmx_pip_qos_watchx_s         cn50xx;
+    struct cvmx_pip_qos_watchx_s         cn52xx;
+    struct cvmx_pip_qos_watchx_s         cn52xxp1;
+    struct cvmx_pip_qos_watchx_s         cn56xx;
+    struct cvmx_pip_qos_watchx_s         cn56xxp1;
+    struct cvmx_pip_qos_watchx_cn30xx    cn58xx;
+    struct cvmx_pip_qos_watchx_cn30xx    cn58xxp1;
+} cvmx_pip_qos_watchx_t;
+
+
+/**
+ * cvmx_pip_raw_word
+ *
+ * PIP_RAW_WORD = The RAW Word2 of the workQ entry.
+ * 
+ * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_raw_word_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_56_63          : 8;
+        uint64_t word                    : 56;      /**< Word2 of the workQ entry
+                                                         The 8-bit bufs field is still set by HW (IPD) */
+#else
+        uint64_t word                    : 56;
+        uint64_t reserved_56_63          : 8;
+#endif
+    } s;
+    struct cvmx_pip_raw_word_s           cn30xx;
+    struct cvmx_pip_raw_word_s           cn31xx;
+    struct cvmx_pip_raw_word_s           cn38xx;
+    struct cvmx_pip_raw_word_s           cn38xxp2;
+    struct cvmx_pip_raw_word_s           cn50xx;
+    struct cvmx_pip_raw_word_s           cn52xx;
+    struct cvmx_pip_raw_word_s           cn52xxp1;
+    struct cvmx_pip_raw_word_s           cn56xx;
+    struct cvmx_pip_raw_word_s           cn56xxp1;
+    struct cvmx_pip_raw_word_s           cn58xx;
+    struct cvmx_pip_raw_word_s           cn58xxp1;
+} cvmx_pip_raw_word_t;
+
+
+/**
+ * cvmx_pip_sft_rst
+ *
+ * PIP_SFT_RST = PIP Soft Reset
+ * 
+ * When written to a '1', resets the pip block
+ *
+ * Notes:
+ * When RST is set to a '1' by SW, PIP will get a short reset pulse (3 cycles
+ * in duration).  Although this will reset much of PIP's internal state, some
+ * CSRs will not reset.
+ * 
+ * . PIP_BIST_STATUS
+ * . PIP_STAT0_PRT*
+ * . PIP_STAT1_PRT*
+ * . PIP_STAT2_PRT*
+ * . PIP_STAT3_PRT*
+ * . PIP_STAT4_PRT*
+ * . PIP_STAT5_PRT*
+ * . PIP_STAT6_PRT*
+ * . PIP_STAT7_PRT*
+ * . PIP_STAT8_PRT*
+ * . PIP_STAT9_PRT*
+ * . PIP_STAT_INB_PKTS*
+ * . PIP_STAT_INB_OCTS*
+ * . PIP_STAT_INB_ERRS*
+ * . PIP_TAG_INC*
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_sft_rst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rst                     : 1;       /**< Soft Reset */
+#else
+        uint64_t rst                     : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_pip_sft_rst_s            cn30xx;
+    struct cvmx_pip_sft_rst_s            cn31xx;
+    struct cvmx_pip_sft_rst_s            cn38xx;
+    struct cvmx_pip_sft_rst_s            cn50xx;
+    struct cvmx_pip_sft_rst_s            cn52xx;
+    struct cvmx_pip_sft_rst_s            cn52xxp1;
+    struct cvmx_pip_sft_rst_s            cn56xx;
+    struct cvmx_pip_sft_rst_s            cn56xxp1;
+    struct cvmx_pip_sft_rst_s            cn58xx;
+    struct cvmx_pip_sft_rst_s            cn58xxp1;
+} cvmx_pip_sft_rst_t;
+
+
+/**
+ * cvmx_pip_stat0_prt#
+ *
+ * PIP Statistics Counters
+ * 
+ * Note: special stat counter behavior
+ * 
+ * 1) Read and write operations must arbitrate for the statistics resources
+ *     along with the packet engines which are incrementing the counters.
+ *     In order to not drop packet information, the packet HW is always a
+ *     higher priority and the CSR requests will only be satisified when
+ *     there are idle cycles.  This can potentially cause long delays if the
+ *     system becomes full.
+ * 
+ * 2) stat counters can be cleared in two ways.  If PIP_STAT_CTL[RDCLR] is
+ *     set, then all read accesses will clear the register.  In addition,
+ *     any write to a stats register will also reset the register to zero.
+ *     Please note that the clearing operations must obey rule \#1 above.
+ * 
+ * 3) all counters are wrapping - software must ensure they are read periodically
+ * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat0_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t drp_pkts                : 32;      /**< Inbound packets marked to be dropped by the IPD
+                                                         QOS widget per port */
+        uint64_t drp_octs                : 32;      /**< Inbound octets marked to be dropped by the IPD
+                                                         QOS widget per port */
+#else
+        uint64_t drp_octs                : 32;
+        uint64_t drp_pkts                : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat0_prtx_s         cn30xx;
+    struct cvmx_pip_stat0_prtx_s         cn31xx;
+    struct cvmx_pip_stat0_prtx_s         cn38xx;
+    struct cvmx_pip_stat0_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat0_prtx_s         cn50xx;
+    struct cvmx_pip_stat0_prtx_s         cn52xx;
+    struct cvmx_pip_stat0_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat0_prtx_s         cn56xx;
+    struct cvmx_pip_stat0_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat0_prtx_s         cn58xx;
+    struct cvmx_pip_stat0_prtx_s         cn58xxp1;
+} cvmx_pip_stat0_prtx_t;
+
+
+/**
+ * cvmx_pip_stat1_prt#
+ *
+ * PIP_STAT1_PRTX = PIP_STAT_OCTS
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat1_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t octs                    : 48;      /**< Number of octets received by PIP (good and bad) */
+#else
+        uint64_t octs                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_pip_stat1_prtx_s         cn30xx;
+    struct cvmx_pip_stat1_prtx_s         cn31xx;
+    struct cvmx_pip_stat1_prtx_s         cn38xx;
+    struct cvmx_pip_stat1_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat1_prtx_s         cn50xx;
+    struct cvmx_pip_stat1_prtx_s         cn52xx;
+    struct cvmx_pip_stat1_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat1_prtx_s         cn56xx;
+    struct cvmx_pip_stat1_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat1_prtx_s         cn58xx;
+    struct cvmx_pip_stat1_prtx_s         cn58xxp1;
+} cvmx_pip_stat1_prtx_t;
+
+
+/**
+ * cvmx_pip_stat2_prt#
+ *
+ * PIP_STAT2_PRTX = PIP_STAT_PKTS     / PIP_STAT_RAW
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat2_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t pkts                    : 32;      /**< Number of packets processed by PIP */
+        uint64_t raw                     : 32;      /**< RAWFULL + RAWSCH Packets without an L1/L2 error
+                                                         received by PIP per port */
+#else
+        uint64_t raw                     : 32;
+        uint64_t pkts                    : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat2_prtx_s         cn30xx;
+    struct cvmx_pip_stat2_prtx_s         cn31xx;
+    struct cvmx_pip_stat2_prtx_s         cn38xx;
+    struct cvmx_pip_stat2_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat2_prtx_s         cn50xx;
+    struct cvmx_pip_stat2_prtx_s         cn52xx;
+    struct cvmx_pip_stat2_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat2_prtx_s         cn56xx;
+    struct cvmx_pip_stat2_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat2_prtx_s         cn58xx;
+    struct cvmx_pip_stat2_prtx_s         cn58xxp1;
+} cvmx_pip_stat2_prtx_t;
+
+
+/**
+ * cvmx_pip_stat3_prt#
+ *
+ * PIP_STAT3_PRTX = PIP_STAT_BCST     / PIP_STAT_MCST
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat3_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bcst                    : 32;      /**< Number of indentified L2 broadcast packets
+                                                         Does not include multicast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+        uint64_t mcst                    : 32;      /**< Number of indentified L2 multicast packets
+                                                         Does not include broadcast packets
+                                                         Only includes packets whose parse mode is
+                                                         SKIP_TO_L2. */
+#else
+        uint64_t mcst                    : 32;
+        uint64_t bcst                    : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat3_prtx_s         cn30xx;
+    struct cvmx_pip_stat3_prtx_s         cn31xx;
+    struct cvmx_pip_stat3_prtx_s         cn38xx;
+    struct cvmx_pip_stat3_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat3_prtx_s         cn50xx;
+    struct cvmx_pip_stat3_prtx_s         cn52xx;
+    struct cvmx_pip_stat3_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat3_prtx_s         cn56xx;
+    struct cvmx_pip_stat3_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat3_prtx_s         cn58xx;
+    struct cvmx_pip_stat3_prtx_s         cn58xxp1;
+} cvmx_pip_stat3_prtx_t;
+
+
+/**
+ * cvmx_pip_stat4_prt#
+ *
+ * PIP_STAT4_PRTX = PIP_STAT_HIST1    / PIP_STAT_HIST0
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat4_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t h65to127                : 32;      /**< Number of 65-127B packets */
+        uint64_t h64                     : 32;      /**< Number of 1-64B packets */
+#else
+        uint64_t h64                     : 32;
+        uint64_t h65to127                : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat4_prtx_s         cn30xx;
+    struct cvmx_pip_stat4_prtx_s         cn31xx;
+    struct cvmx_pip_stat4_prtx_s         cn38xx;
+    struct cvmx_pip_stat4_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat4_prtx_s         cn50xx;
+    struct cvmx_pip_stat4_prtx_s         cn52xx;
+    struct cvmx_pip_stat4_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat4_prtx_s         cn56xx;
+    struct cvmx_pip_stat4_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat4_prtx_s         cn58xx;
+    struct cvmx_pip_stat4_prtx_s         cn58xxp1;
+} cvmx_pip_stat4_prtx_t;
+
+
+/**
+ * cvmx_pip_stat5_prt#
+ *
+ * PIP_STAT5_PRTX = PIP_STAT_HIST3    / PIP_STAT_HIST2
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat5_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t h256to511               : 32;      /**< Number of 256-511B packets */
+        uint64_t h128to255               : 32;      /**< Number of 128-255B packets */
+#else
+        uint64_t h128to255               : 32;
+        uint64_t h256to511               : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat5_prtx_s         cn30xx;
+    struct cvmx_pip_stat5_prtx_s         cn31xx;
+    struct cvmx_pip_stat5_prtx_s         cn38xx;
+    struct cvmx_pip_stat5_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat5_prtx_s         cn50xx;
+    struct cvmx_pip_stat5_prtx_s         cn52xx;
+    struct cvmx_pip_stat5_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat5_prtx_s         cn56xx;
+    struct cvmx_pip_stat5_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat5_prtx_s         cn58xx;
+    struct cvmx_pip_stat5_prtx_s         cn58xxp1;
+} cvmx_pip_stat5_prtx_t;
+
+
+/**
+ * cvmx_pip_stat6_prt#
+ *
+ * PIP_STAT6_PRTX = PIP_STAT_HIST5    / PIP_STAT_HIST4
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat6_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t h1024to1518             : 32;      /**< Number of 1024-1518B packets */
+        uint64_t h512to1023              : 32;      /**< Number of 512-1023B packets */
+#else
+        uint64_t h512to1023              : 32;
+        uint64_t h1024to1518             : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat6_prtx_s         cn30xx;
+    struct cvmx_pip_stat6_prtx_s         cn31xx;
+    struct cvmx_pip_stat6_prtx_s         cn38xx;
+    struct cvmx_pip_stat6_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat6_prtx_s         cn50xx;
+    struct cvmx_pip_stat6_prtx_s         cn52xx;
+    struct cvmx_pip_stat6_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat6_prtx_s         cn56xx;
+    struct cvmx_pip_stat6_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat6_prtx_s         cn58xx;
+    struct cvmx_pip_stat6_prtx_s         cn58xxp1;
+} cvmx_pip_stat6_prtx_t;
+
+
+/**
+ * cvmx_pip_stat7_prt#
+ *
+ * PIP_STAT7_PRTX = PIP_STAT_FCS      / PIP_STAT_HIST6
+ *
+ *
+ * Notes:
+ * FCS is not checked on the PCI ports 32..35.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat7_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fcs                     : 32;      /**< Number of packets with FCS or Align opcode errors */
+        uint64_t h1519                   : 32;      /**< Number of 1519-max packets */
+#else
+        uint64_t h1519                   : 32;
+        uint64_t fcs                     : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat7_prtx_s         cn30xx;
+    struct cvmx_pip_stat7_prtx_s         cn31xx;
+    struct cvmx_pip_stat7_prtx_s         cn38xx;
+    struct cvmx_pip_stat7_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat7_prtx_s         cn50xx;
+    struct cvmx_pip_stat7_prtx_s         cn52xx;
+    struct cvmx_pip_stat7_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat7_prtx_s         cn56xx;
+    struct cvmx_pip_stat7_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat7_prtx_s         cn58xx;
+    struct cvmx_pip_stat7_prtx_s         cn58xxp1;
+} cvmx_pip_stat7_prtx_t;
+
+
+/**
+ * cvmx_pip_stat8_prt#
+ *
+ * PIP_STAT8_PRTX = PIP_STAT_FRAG     / PIP_STAT_UNDER
+ *
+ *
+ * Notes:
+ * FCS is not checked on the PCI ports 32..35.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat8_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t frag                    : 32;      /**< Number of packets with length < min and FCS error */
+        uint64_t undersz                 : 32;      /**< Number of packets with length < min */
+#else
+        uint64_t undersz                 : 32;
+        uint64_t frag                    : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat8_prtx_s         cn30xx;
+    struct cvmx_pip_stat8_prtx_s         cn31xx;
+    struct cvmx_pip_stat8_prtx_s         cn38xx;
+    struct cvmx_pip_stat8_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat8_prtx_s         cn50xx;
+    struct cvmx_pip_stat8_prtx_s         cn52xx;
+    struct cvmx_pip_stat8_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat8_prtx_s         cn56xx;
+    struct cvmx_pip_stat8_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat8_prtx_s         cn58xx;
+    struct cvmx_pip_stat8_prtx_s         cn58xxp1;
+} cvmx_pip_stat8_prtx_t;
+
+
+/**
+ * cvmx_pip_stat9_prt#
+ *
+ * PIP_STAT9_PRTX = PIP_STAT_JABBER   / PIP_STAT_OVER
+ *
+ *
+ * Notes:
+ * FCS is not checked on the PCI ports 32..35.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat9_prtx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t jabber                  : 32;      /**< Number of packets with length > max and FCS error */
+        uint64_t oversz                  : 32;      /**< Number of packets with length > max */
+#else
+        uint64_t oversz                  : 32;
+        uint64_t jabber                  : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat9_prtx_s         cn30xx;
+    struct cvmx_pip_stat9_prtx_s         cn31xx;
+    struct cvmx_pip_stat9_prtx_s         cn38xx;
+    struct cvmx_pip_stat9_prtx_s         cn38xxp2;
+    struct cvmx_pip_stat9_prtx_s         cn50xx;
+    struct cvmx_pip_stat9_prtx_s         cn52xx;
+    struct cvmx_pip_stat9_prtx_s         cn52xxp1;
+    struct cvmx_pip_stat9_prtx_s         cn56xx;
+    struct cvmx_pip_stat9_prtx_s         cn56xxp1;
+    struct cvmx_pip_stat9_prtx_s         cn58xx;
+    struct cvmx_pip_stat9_prtx_s         cn58xxp1;
+} cvmx_pip_stat9_prtx_t;
+
+
+/**
+ * cvmx_pip_stat_ctl
+ *
+ * PIP_STAT_CTL = PIP's Stat Control Register
+ * 
+ * Controls how the PIP statistics counters are handled.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t rdclr                   : 1;       /**< Stat registers are read and clear
+                                                         0 = stat registers hold value when read
+                                                         1 = stat registers are cleared when read */
+#else
+        uint64_t rdclr                   : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_pip_stat_ctl_s           cn30xx;
+    struct cvmx_pip_stat_ctl_s           cn31xx;
+    struct cvmx_pip_stat_ctl_s           cn38xx;
+    struct cvmx_pip_stat_ctl_s           cn38xxp2;
+    struct cvmx_pip_stat_ctl_s           cn50xx;
+    struct cvmx_pip_stat_ctl_s           cn52xx;
+    struct cvmx_pip_stat_ctl_s           cn52xxp1;
+    struct cvmx_pip_stat_ctl_s           cn56xx;
+    struct cvmx_pip_stat_ctl_s           cn56xxp1;
+    struct cvmx_pip_stat_ctl_s           cn58xx;
+    struct cvmx_pip_stat_ctl_s           cn58xxp1;
+} cvmx_pip_stat_ctl_t;
+
+
+/**
+ * cvmx_pip_stat_inb_errs#
+ *
+ * PIP_STAT_INB_ERRSX = Inbound error packets received by PIP per port
+ * 
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat_inb_errsx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t errs                    : 16;      /**< Number of packets with GMX/SPX/PCI errors
+                                                         received by PIP */
+#else
+        uint64_t errs                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pip_stat_inb_errsx_s     cn30xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn31xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn38xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn38xxp2;
+    struct cvmx_pip_stat_inb_errsx_s     cn50xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn52xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn52xxp1;
+    struct cvmx_pip_stat_inb_errsx_s     cn56xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn56xxp1;
+    struct cvmx_pip_stat_inb_errsx_s     cn58xx;
+    struct cvmx_pip_stat_inb_errsx_s     cn58xxp1;
+} cvmx_pip_stat_inb_errsx_t;
+
+
+/**
+ * cvmx_pip_stat_inb_octs#
+ *
+ * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port
+ * 
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat_inb_octsx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t octs                    : 48;      /**< Total number of octets from all packets received
+                                                         by PIP */
+#else
+        uint64_t octs                    : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_pip_stat_inb_octsx_s     cn30xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn31xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn38xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn38xxp2;
+    struct cvmx_pip_stat_inb_octsx_s     cn50xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn52xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn52xxp1;
+    struct cvmx_pip_stat_inb_octsx_s     cn56xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn56xxp1;
+    struct cvmx_pip_stat_inb_octsx_s     cn58xx;
+    struct cvmx_pip_stat_inb_octsx_s     cn58xxp1;
+} cvmx_pip_stat_inb_octsx_t;
+
+
+/**
+ * cvmx_pip_stat_inb_pkts#
+ *
+ * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port
+ * 
+ * Inbound stats collect all data sent to PIP from all packet interfaces.
+ * Its the raw counts of everything that comes into the block.  The counts
+ * will reflect all error packets and packets dropped by the PKI RED engine.
+ * These counts are intended for system debug, but could convey useful
+ * information in production systems.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_stat_inb_pktsx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pkts                    : 32;      /**< Number of packets without GMX/SPX/PCI errors
+                                                         received by PIP */
+#else
+        uint64_t pkts                    : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pip_stat_inb_pktsx_s     cn30xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn31xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn38xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn38xxp2;
+    struct cvmx_pip_stat_inb_pktsx_s     cn50xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn52xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn52xxp1;
+    struct cvmx_pip_stat_inb_pktsx_s     cn56xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn56xxp1;
+    struct cvmx_pip_stat_inb_pktsx_s     cn58xx;
+    struct cvmx_pip_stat_inb_pktsx_s     cn58xxp1;
+} cvmx_pip_stat_inb_pktsx_t;
+
+
+/**
+ * cvmx_pip_tag_inc#
+ *
+ * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm
+ * 
+ * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_tag_incx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t en                      : 8;       /**< Which bytes to include in mask tag algorithm
+                                                         Broken into 4, 16-entry masks to cover 128B
+                                                         PIP_PRT_CFG[TAG_INC] selects 1 of 4 to use
+                                                         registers  0-15 map to PIP_PRT_CFG[TAG_INC] == 0
+                                                         registers 16-31 map to PIP_PRT_CFG[TAG_INC] == 1
+                                                         registers 32-47 map to PIP_PRT_CFG[TAG_INC] == 2
+                                                         registers 48-63 map to PIP_PRT_CFG[TAG_INC] == 3
+                                                         [7] coresponds to the MSB of the 8B word
+                                                         [0] coresponds to the LSB of the 8B word
+                                                         (PASS2 only) */
+#else
+        uint64_t en                      : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pip_tag_incx_s           cn30xx;
+    struct cvmx_pip_tag_incx_s           cn31xx;
+    struct cvmx_pip_tag_incx_s           cn38xx;
+    struct cvmx_pip_tag_incx_s           cn38xxp2;
+    struct cvmx_pip_tag_incx_s           cn50xx;
+    struct cvmx_pip_tag_incx_s           cn52xx;
+    struct cvmx_pip_tag_incx_s           cn52xxp1;
+    struct cvmx_pip_tag_incx_s           cn56xx;
+    struct cvmx_pip_tag_incx_s           cn56xxp1;
+    struct cvmx_pip_tag_incx_s           cn58xx;
+    struct cvmx_pip_tag_incx_s           cn58xxp1;
+} cvmx_pip_tag_incx_t;
+
+
+/**
+ * cvmx_pip_tag_mask
+ *
+ * PIP_TAG_MASK = Mask bit in the tag generation
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_tag_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mask                    : 16;      /**< When set, MASK clears individual bits of lower 16
+                                                         bits of the computed tag.  Does not effect RAW
+                                                         or INSTR HDR packets. */
+#else
+        uint64_t mask                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pip_tag_mask_s           cn30xx;
+    struct cvmx_pip_tag_mask_s           cn31xx;
+    struct cvmx_pip_tag_mask_s           cn38xx;
+    struct cvmx_pip_tag_mask_s           cn38xxp2;
+    struct cvmx_pip_tag_mask_s           cn50xx;
+    struct cvmx_pip_tag_mask_s           cn52xx;
+    struct cvmx_pip_tag_mask_s           cn52xxp1;
+    struct cvmx_pip_tag_mask_s           cn56xx;
+    struct cvmx_pip_tag_mask_s           cn56xxp1;
+    struct cvmx_pip_tag_mask_s           cn58xx;
+    struct cvmx_pip_tag_mask_s           cn58xxp1;
+} cvmx_pip_tag_mask_t;
+
+
+/**
+ * cvmx_pip_tag_secret
+ *
+ * PIP_TAG_SECRET = Initial value in tag generation
+ * 
+ * The source and destination IV's provide a mechanism for each Octeon to be unique.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_tag_secret_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t dst                     : 16;      /**< Secret for the destination tuple tag CRC calc */
+        uint64_t src                     : 16;      /**< Secret for the source tuple tag CRC calc */
+#else
+        uint64_t src                     : 16;
+        uint64_t dst                     : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pip_tag_secret_s         cn30xx;
+    struct cvmx_pip_tag_secret_s         cn31xx;
+    struct cvmx_pip_tag_secret_s         cn38xx;
+    struct cvmx_pip_tag_secret_s         cn38xxp2;
+    struct cvmx_pip_tag_secret_s         cn50xx;
+    struct cvmx_pip_tag_secret_s         cn52xx;
+    struct cvmx_pip_tag_secret_s         cn52xxp1;
+    struct cvmx_pip_tag_secret_s         cn56xx;
+    struct cvmx_pip_tag_secret_s         cn56xxp1;
+    struct cvmx_pip_tag_secret_s         cn58xx;
+    struct cvmx_pip_tag_secret_s         cn58xxp1;
+} cvmx_pip_tag_secret_t;
+
+
+/**
+ * cvmx_pip_todo_entry
+ *
+ * PIP_TODO_ENTRY = Head entry of the Todo list (debug only)
+ * 
+ * Summary of the current packet that has completed and waiting to be processed
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pip_todo_entry_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t val                     : 1;       /**< Entry is valid */
+        uint64_t reserved_62_62          : 1;
+        uint64_t entry                   : 62;      /**< Todo list entry summary */
+#else
+        uint64_t entry                   : 62;
+        uint64_t reserved_62_62          : 1;
+        uint64_t val                     : 1;
+#endif
+    } s;
+    struct cvmx_pip_todo_entry_s         cn30xx;
+    struct cvmx_pip_todo_entry_s         cn31xx;
+    struct cvmx_pip_todo_entry_s         cn38xx;
+    struct cvmx_pip_todo_entry_s         cn38xxp2;
+    struct cvmx_pip_todo_entry_s         cn50xx;
+    struct cvmx_pip_todo_entry_s         cn52xx;
+    struct cvmx_pip_todo_entry_s         cn52xxp1;
+    struct cvmx_pip_todo_entry_s         cn56xx;
+    struct cvmx_pip_todo_entry_s         cn56xxp1;
+    struct cvmx_pip_todo_entry_s         cn58xx;
+    struct cvmx_pip_todo_entry_s         cn58xxp1;
+} cvmx_pip_todo_entry_t;
+
+
+/**
+ * cvmx_pko_mem_count0
+ *
+ * Notes:
+ * Total number of packets seen by PKO, per port
+ * A write to this address will clear the entry whose index is specified as COUNT[5:0].
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_count0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t count                   : 32;      /**< Total number of packets seen by PKO */
+#else
+        uint64_t count                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pko_mem_count0_s         cn30xx;
+    struct cvmx_pko_mem_count0_s         cn31xx;
+    struct cvmx_pko_mem_count0_s         cn38xx;
+    struct cvmx_pko_mem_count0_s         cn38xxp2;
+    struct cvmx_pko_mem_count0_s         cn50xx;
+    struct cvmx_pko_mem_count0_s         cn52xx;
+    struct cvmx_pko_mem_count0_s         cn52xxp1;
+    struct cvmx_pko_mem_count0_s         cn56xx;
+    struct cvmx_pko_mem_count0_s         cn56xxp1;
+    struct cvmx_pko_mem_count0_s         cn58xx;
+    struct cvmx_pko_mem_count0_s         cn58xxp1;
+} cvmx_pko_mem_count0_t;
+
+
+/**
+ * cvmx_pko_mem_count1
+ *
+ * Notes:
+ * Total number of bytes seen by PKO, per port
+ * A write to this address will clear the entry whose index is specified as COUNT[5:0].
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_count1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t count                   : 48;      /**< Total number of bytes seen by PKO */
+#else
+        uint64_t count                   : 48;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_pko_mem_count1_s         cn30xx;
+    struct cvmx_pko_mem_count1_s         cn31xx;
+    struct cvmx_pko_mem_count1_s         cn38xx;
+    struct cvmx_pko_mem_count1_s         cn38xxp2;
+    struct cvmx_pko_mem_count1_s         cn50xx;
+    struct cvmx_pko_mem_count1_s         cn52xx;
+    struct cvmx_pko_mem_count1_s         cn52xxp1;
+    struct cvmx_pko_mem_count1_s         cn56xx;
+    struct cvmx_pko_mem_count1_s         cn56xxp1;
+    struct cvmx_pko_mem_count1_s         cn58xx;
+    struct cvmx_pko_mem_count1_s         cn58xxp1;
+} cvmx_pko_mem_count1_t;
+
+
+/**
+ * cvmx_pko_mem_debug0
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.cmnd[63:0]
+ * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fau                     : 28;      /**< Fetch and add command words */
+        uint64_t cmd                     : 14;      /**< Command word */
+        uint64_t segs                    : 6;       /**< Number of segments/gather size */
+        uint64_t size                    : 16;      /**< Packet length in bytes */
+#else
+        uint64_t size                    : 16;
+        uint64_t segs                    : 6;
+        uint64_t cmd                     : 14;
+        uint64_t fau                     : 28;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug0_s         cn30xx;
+    struct cvmx_pko_mem_debug0_s         cn31xx;
+    struct cvmx_pko_mem_debug0_s         cn38xx;
+    struct cvmx_pko_mem_debug0_s         cn38xxp2;
+    struct cvmx_pko_mem_debug0_s         cn50xx;
+    struct cvmx_pko_mem_debug0_s         cn52xx;
+    struct cvmx_pko_mem_debug0_s         cn52xxp1;
+    struct cvmx_pko_mem_debug0_s         cn56xx;
+    struct cvmx_pko_mem_debug0_s         cn56xxp1;
+    struct cvmx_pko_mem_debug0_s         cn58xx;
+    struct cvmx_pko_mem_debug0_s         cn58xxp1;
+} cvmx_pko_mem_debug0_t;
+
+
+/**
+ * cvmx_pko_mem_debug1
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.curr[63:0]
+ * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t size                    : 16;      /**< Size in bytes */
+        uint64_t ptr                     : 40;      /**< Data pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug1_s         cn30xx;
+    struct cvmx_pko_mem_debug1_s         cn31xx;
+    struct cvmx_pko_mem_debug1_s         cn38xx;
+    struct cvmx_pko_mem_debug1_s         cn38xxp2;
+    struct cvmx_pko_mem_debug1_s         cn50xx;
+    struct cvmx_pko_mem_debug1_s         cn52xx;
+    struct cvmx_pko_mem_debug1_s         cn52xxp1;
+    struct cvmx_pko_mem_debug1_s         cn56xx;
+    struct cvmx_pko_mem_debug1_s         cn56xxp1;
+    struct cvmx_pko_mem_debug1_s         cn58xx;
+    struct cvmx_pko_mem_debug1_s         cn58xxp1;
+} cvmx_pko_mem_debug1_t;
+
+
+/**
+ * cvmx_pko_mem_debug10
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs1, pko.dat.ptr.ptrs2
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug10_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug10_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fau                     : 28;      /**< Fetch and add command words */
+        uint64_t cmd                     : 14;      /**< Command word */
+        uint64_t segs                    : 6;       /**< Number of segments/gather size */
+        uint64_t size                    : 16;      /**< Packet length in bytes */
+#else
+        uint64_t size                    : 16;
+        uint64_t segs                    : 6;
+        uint64_t cmd                     : 14;
+        uint64_t fau                     : 28;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug10_cn30xx   cn31xx;
+    struct cvmx_pko_mem_debug10_cn30xx   cn38xx;
+    struct cvmx_pko_mem_debug10_cn30xx   cn38xxp2;
+    struct cvmx_pko_mem_debug10_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t ptrs1                   : 17;      /**< Internal state */
+        uint64_t reserved_17_31          : 15;
+        uint64_t ptrs2                   : 17;      /**< Internal state */
+#else
+        uint64_t ptrs2                   : 17;
+        uint64_t reserved_17_31          : 15;
+        uint64_t ptrs1                   : 17;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug10_cn50xx   cn52xx;
+    struct cvmx_pko_mem_debug10_cn50xx   cn52xxp1;
+    struct cvmx_pko_mem_debug10_cn50xx   cn56xx;
+    struct cvmx_pko_mem_debug10_cn50xx   cn56xxp1;
+    struct cvmx_pko_mem_debug10_cn50xx   cn58xx;
+    struct cvmx_pko_mem_debug10_cn50xx   cn58xxp1;
+} cvmx_pko_mem_debug10_t;
+
+
+/**
+ * cvmx_pko_mem_debug11
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.out.sta.state[22:0]
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug11_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t size                    : 16;      /**< Size in bytes */
+        uint64_t reserved_0_39           : 40;
+#else
+        uint64_t reserved_0_39           : 40;
+        uint64_t size                    : 16;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug11_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t size                    : 16;      /**< Size in bytes */
+        uint64_t ptr                     : 40;      /**< Data pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug11_cn30xx   cn31xx;
+    struct cvmx_pko_mem_debug11_cn30xx   cn38xx;
+    struct cvmx_pko_mem_debug11_cn30xx   cn38xxp2;
+    struct cvmx_pko_mem_debug11_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t maj                     : 1;       /**< Internal state */
+        uint64_t uid                     : 3;       /**< Internal state */
+        uint64_t sop                     : 1;       /**< Internal state */
+        uint64_t len                     : 1;       /**< Internal state */
+        uint64_t chk                     : 1;       /**< Internal state */
+        uint64_t cnt                     : 13;      /**< Internal state */
+        uint64_t mod                     : 3;       /**< Internal state */
+#else
+        uint64_t mod                     : 3;
+        uint64_t cnt                     : 13;
+        uint64_t chk                     : 1;
+        uint64_t len                     : 1;
+        uint64_t sop                     : 1;
+        uint64_t uid                     : 3;
+        uint64_t maj                     : 1;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug11_cn50xx   cn52xx;
+    struct cvmx_pko_mem_debug11_cn50xx   cn52xxp1;
+    struct cvmx_pko_mem_debug11_cn50xx   cn56xx;
+    struct cvmx_pko_mem_debug11_cn50xx   cn56xxp1;
+    struct cvmx_pko_mem_debug11_cn50xx   cn58xx;
+    struct cvmx_pko_mem_debug11_cn50xx   cn58xxp1;
+} cvmx_pko_mem_debug11_t;
+
+
+/**
+ * cvmx_pko_mem_debug12
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.out.ctl.cmnd[63:0]
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug12_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug12_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< WorkQ data or Store0 pointer */
+#else
+        uint64_t data                    : 64;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug12_cn30xx   cn31xx;
+    struct cvmx_pko_mem_debug12_cn30xx   cn38xx;
+    struct cvmx_pko_mem_debug12_cn30xx   cn38xxp2;
+    struct cvmx_pko_mem_debug12_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t fau                     : 28;      /**< Fetch and add command words */
+        uint64_t cmd                     : 14;      /**< Command word */
+        uint64_t segs                    : 6;       /**< Number of segments/gather size */
+        uint64_t size                    : 16;      /**< Packet length in bytes */
+#else
+        uint64_t size                    : 16;
+        uint64_t segs                    : 6;
+        uint64_t cmd                     : 14;
+        uint64_t fau                     : 28;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug12_cn50xx   cn52xx;
+    struct cvmx_pko_mem_debug12_cn50xx   cn52xxp1;
+    struct cvmx_pko_mem_debug12_cn50xx   cn56xx;
+    struct cvmx_pko_mem_debug12_cn50xx   cn56xxp1;
+    struct cvmx_pko_mem_debug12_cn50xx   cn58xx;
+    struct cvmx_pko_mem_debug12_cn50xx   cn58xxp1;
+} cvmx_pko_mem_debug12_t;
+
+
+/**
+ * cvmx_pko_mem_debug13
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.out.ctl.head[63:0]
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug13_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t reserved_0_55           : 56;
+#else
+        uint64_t reserved_0_55           : 56;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug13_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_51_63          : 13;
+        uint64_t widx                    : 17;      /**< PDB widx */
+        uint64_t ridx2                   : 17;      /**< PDB ridx2 */
+        uint64_t widx2                   : 17;      /**< PDB widx2 */
+#else
+        uint64_t widx2                   : 17;
+        uint64_t ridx2                   : 17;
+        uint64_t widx                    : 17;
+        uint64_t reserved_51_63          : 13;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug13_cn30xx   cn31xx;
+    struct cvmx_pko_mem_debug13_cn30xx   cn38xx;
+    struct cvmx_pko_mem_debug13_cn30xx   cn38xxp2;
+    struct cvmx_pko_mem_debug13_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t size                    : 16;      /**< Size in bytes */
+        uint64_t ptr                     : 40;      /**< Data pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug13_cn50xx   cn52xx;
+    struct cvmx_pko_mem_debug13_cn50xx   cn52xxp1;
+    struct cvmx_pko_mem_debug13_cn50xx   cn56xx;
+    struct cvmx_pko_mem_debug13_cn50xx   cn56xxp1;
+    struct cvmx_pko_mem_debug13_cn50xx   cn58xx;
+    struct cvmx_pko_mem_debug13_cn50xx   cn58xxp1;
+} cvmx_pko_mem_debug13_t;
+
+
+/**
+ * cvmx_pko_mem_debug14
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.prt.psb.save[63:0]
+ * This CSR is a memory of 120 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug14_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug14_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t ridx                    : 17;      /**< PDB ridx */
+#else
+        uint64_t ridx                    : 17;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug14_cn30xx   cn31xx;
+    struct cvmx_pko_mem_debug14_cn30xx   cn38xx;
+    struct cvmx_pko_mem_debug14_cn30xx   cn38xxp2;
+    struct cvmx_pko_mem_debug14_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Command words */
+#else
+        uint64_t data                    : 64;
+#endif
+    } cn52xx;
+    struct cvmx_pko_mem_debug14_cn52xx   cn52xxp1;
+    struct cvmx_pko_mem_debug14_cn52xx   cn56xx;
+    struct cvmx_pko_mem_debug14_cn52xx   cn56xxp1;
+} cvmx_pko_mem_debug14_t;
+
+
+/**
+ * cvmx_pko_mem_debug2
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.head[63:0]
+ * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t size                    : 16;      /**< Size in bytes */
+        uint64_t ptr                     : 40;      /**< Data pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug2_s         cn30xx;
+    struct cvmx_pko_mem_debug2_s         cn31xx;
+    struct cvmx_pko_mem_debug2_s         cn38xx;
+    struct cvmx_pko_mem_debug2_s         cn38xxp2;
+    struct cvmx_pko_mem_debug2_s         cn50xx;
+    struct cvmx_pko_mem_debug2_s         cn52xx;
+    struct cvmx_pko_mem_debug2_s         cn52xxp1;
+    struct cvmx_pko_mem_debug2_s         cn56xx;
+    struct cvmx_pko_mem_debug2_s         cn56xxp1;
+    struct cvmx_pko_mem_debug2_s         cn58xx;
+    struct cvmx_pko_mem_debug2_s         cn58xxp1;
+} cvmx_pko_mem_debug2_t;
+
+
+/**
+ * cvmx_pko_mem_debug3
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.resp[63:0]
+ * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug3_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t i                       : 1;       /**< "I"  value used for free operation */
+        uint64_t back                    : 4;       /**< Back value used for free operation */
+        uint64_t pool                    : 3;       /**< Pool value used for free operation */
+        uint64_t size                    : 16;      /**< Size in bytes */
+        uint64_t ptr                     : 40;      /**< Data pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t pool                    : 3;
+        uint64_t back                    : 4;
+        uint64_t i                       : 1;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug3_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug3_cn30xx    cn38xx;
+    struct cvmx_pko_mem_debug3_cn30xx    cn38xxp2;
+    struct cvmx_pko_mem_debug3_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< WorkQ data or Store0 pointer */
+#else
+        uint64_t data                    : 64;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug3_cn50xx    cn52xx;
+    struct cvmx_pko_mem_debug3_cn50xx    cn52xxp1;
+    struct cvmx_pko_mem_debug3_cn50xx    cn56xx;
+    struct cvmx_pko_mem_debug3_cn50xx    cn56xxp1;
+    struct cvmx_pko_mem_debug3_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug3_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug3_t;
+
+
+/**
+ * cvmx_pko_mem_debug4
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.state[63:0]
+ * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug4_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< WorkQ data or Store0 pointer */
+#else
+        uint64_t data                    : 64;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug4_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug4_cn30xx    cn38xx;
+    struct cvmx_pko_mem_debug4_cn30xx    cn38xxp2;
+    struct cvmx_pko_mem_debug4_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t cmnd_segs               : 3;       /**< Internal state */
+        uint64_t cmnd_siz                : 16;      /**< Internal state */
+        uint64_t cmnd_off                : 6;       /**< Internal state */
+        uint64_t uid                     : 3;       /**< Internal state */
+        uint64_t dread_sop               : 1;       /**< Internal state */
+        uint64_t init_dwrite             : 1;       /**< Internal state */
+        uint64_t chk_once                : 1;       /**< Internal state */
+        uint64_t chk_mode                : 1;       /**< Internal state */
+        uint64_t active                  : 1;       /**< Internal state */
+        uint64_t static_p                : 1;       /**< Internal state */
+        uint64_t qos                     : 3;       /**< Internal state */
+        uint64_t qcb_ridx                : 5;       /**< Internal state */
+        uint64_t qid_off_max             : 4;       /**< Internal state */
+        uint64_t qid_off                 : 4;       /**< Internal state */
+        uint64_t qid_base                : 8;       /**< Internal state */
+        uint64_t wait                    : 1;       /**< Internal state */
+        uint64_t minor                   : 2;       /**< Internal state */
+        uint64_t major                   : 3;       /**< Internal state */
+#else
+        uint64_t major                   : 3;
+        uint64_t minor                   : 2;
+        uint64_t wait                    : 1;
+        uint64_t qid_base                : 8;
+        uint64_t qid_off                 : 4;
+        uint64_t qid_off_max             : 4;
+        uint64_t qcb_ridx                : 5;
+        uint64_t qos                     : 3;
+        uint64_t static_p                : 1;
+        uint64_t active                  : 1;
+        uint64_t chk_mode                : 1;
+        uint64_t chk_once                : 1;
+        uint64_t init_dwrite             : 1;
+        uint64_t dread_sop               : 1;
+        uint64_t uid                     : 3;
+        uint64_t cmnd_off                : 6;
+        uint64_t cmnd_siz                : 16;
+        uint64_t cmnd_segs               : 3;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug4_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t curr_siz                : 8;       /**< Internal state */
+        uint64_t curr_off                : 16;      /**< Internal state */
+        uint64_t cmnd_segs               : 6;       /**< Internal state */
+        uint64_t cmnd_siz                : 16;      /**< Internal state */
+        uint64_t cmnd_off                : 6;       /**< Internal state */
+        uint64_t uid                     : 2;       /**< Internal state */
+        uint64_t dread_sop               : 1;       /**< Internal state */
+        uint64_t init_dwrite             : 1;       /**< Internal state */
+        uint64_t chk_once                : 1;       /**< Internal state */
+        uint64_t chk_mode                : 1;       /**< Internal state */
+        uint64_t wait                    : 1;       /**< Internal state */
+        uint64_t minor                   : 2;       /**< Internal state */
+        uint64_t major                   : 3;       /**< Internal state */
+#else
+        uint64_t major                   : 3;
+        uint64_t minor                   : 2;
+        uint64_t wait                    : 1;
+        uint64_t chk_mode                : 1;
+        uint64_t chk_once                : 1;
+        uint64_t init_dwrite             : 1;
+        uint64_t dread_sop               : 1;
+        uint64_t uid                     : 2;
+        uint64_t cmnd_off                : 6;
+        uint64_t cmnd_siz                : 16;
+        uint64_t cmnd_segs               : 6;
+        uint64_t curr_off                : 16;
+        uint64_t curr_siz                : 8;
+#endif
+    } cn52xx;
+    struct cvmx_pko_mem_debug4_cn52xx    cn52xxp1;
+    struct cvmx_pko_mem_debug4_cn52xx    cn56xx;
+    struct cvmx_pko_mem_debug4_cn52xx    cn56xxp1;
+    struct cvmx_pko_mem_debug4_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug4_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug4_t;
+
+
+/**
+ * cvmx_pko_mem_debug5
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.state[127:64]
+ * This CSR is a memory of 10 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug5_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dwri_mod                : 1;       /**< Dwrite mod */
+        uint64_t dwri_sop                : 1;       /**< Dwrite sop needed */
+        uint64_t dwri_len                : 1;       /**< Dwrite len */
+        uint64_t dwri_cnt                : 13;      /**< Dwrite count */
+        uint64_t cmnd_siz                : 16;      /**< Copy of cmnd.size */
+        uint64_t uid                     : 1;       /**< UID */
+        uint64_t xfer_wor                : 1;       /**< Transfer work needed */
+        uint64_t xfer_dwr                : 1;       /**< Transfer dwrite needed */
+        uint64_t cbuf_fre                : 1;       /**< Cbuf needs free */
+        uint64_t reserved_27_27          : 1;
+        uint64_t chk_mode                : 1;       /**< Checksum mode */
+        uint64_t active                  : 1;       /**< Port is active */
+        uint64_t qos                     : 3;       /**< Current QOS round */
+        uint64_t qcb_ridx                : 5;       /**< Buffer read  index for QCB */
+        uint64_t qid_off                 : 3;       /**< Offset to be added to QID_BASE for current queue */
+        uint64_t qid_base                : 7;       /**< Absolute QID of the queue array base = &QUEUES[0] */
+        uint64_t wait                    : 1;       /**< State wait when set */
+        uint64_t minor                   : 2;       /**< State minor code */
+        uint64_t major                   : 4;       /**< State major code */
+#else
+        uint64_t major                   : 4;
+        uint64_t minor                   : 2;
+        uint64_t wait                    : 1;
+        uint64_t qid_base                : 7;
+        uint64_t qid_off                 : 3;
+        uint64_t qcb_ridx                : 5;
+        uint64_t qos                     : 3;
+        uint64_t active                  : 1;
+        uint64_t chk_mode                : 1;
+        uint64_t reserved_27_27          : 1;
+        uint64_t cbuf_fre                : 1;
+        uint64_t xfer_dwr                : 1;
+        uint64_t xfer_wor                : 1;
+        uint64_t uid                     : 1;
+        uint64_t cmnd_siz                : 16;
+        uint64_t dwri_cnt                : 13;
+        uint64_t dwri_len                : 1;
+        uint64_t dwri_sop                : 1;
+        uint64_t dwri_mod                : 1;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug5_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug5_cn30xx    cn38xx;
+    struct cvmx_pko_mem_debug5_cn30xx    cn38xxp2;
+    struct cvmx_pko_mem_debug5_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t curr_ptr                : 29;      /**< Internal state */
+        uint64_t curr_siz                : 16;      /**< Internal state */
+        uint64_t curr_off                : 16;      /**< Internal state */
+        uint64_t cmnd_segs               : 3;       /**< Internal state */
+#else
+        uint64_t cmnd_segs               : 3;
+        uint64_t curr_off                : 16;
+        uint64_t curr_siz                : 16;
+        uint64_t curr_ptr                : 29;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug5_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_54_63          : 10;
+        uint64_t nxt_inflt               : 6;       /**< Internal state */
+        uint64_t curr_ptr                : 40;      /**< Internal state */
+        uint64_t curr_siz                : 8;       /**< Internal state */
+#else
+        uint64_t curr_siz                : 8;
+        uint64_t curr_ptr                : 40;
+        uint64_t nxt_inflt               : 6;
+        uint64_t reserved_54_63          : 10;
+#endif
+    } cn52xx;
+    struct cvmx_pko_mem_debug5_cn52xx    cn52xxp1;
+    struct cvmx_pko_mem_debug5_cn52xx    cn56xx;
+    struct cvmx_pko_mem_debug5_cn52xx    cn56xxp1;
+    struct cvmx_pko_mem_debug5_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug5_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug5_t;
+
+
+/**
+ * cvmx_pko_mem_debug6
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko_prt_psb.port[63:0]
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t qid_offres              : 4;       /**< Internal state */
+        uint64_t qid_offths              : 4;       /**< Internal state */
+        uint64_t preempter               : 1;       /**< Internal state */
+        uint64_t preemptee               : 1;       /**< Internal state */
+        uint64_t preempted               : 1;       /**< Internal state */
+        uint64_t active                  : 1;       /**< Internal state */
+        uint64_t statc                   : 1;       /**< Internal state */
+        uint64_t qos                     : 3;       /**< Internal state */
+        uint64_t qcb_ridx                : 5;       /**< Internal state */
+        uint64_t qid_offmax              : 4;       /**< Internal state */
+        uint64_t reserved_0_11           : 12;
+#else
+        uint64_t reserved_0_11           : 12;
+        uint64_t qid_offmax              : 4;
+        uint64_t qcb_ridx                : 5;
+        uint64_t qos                     : 3;
+        uint64_t statc                   : 1;
+        uint64_t active                  : 1;
+        uint64_t preempted               : 1;
+        uint64_t preemptee               : 1;
+        uint64_t preempter               : 1;
+        uint64_t qid_offths              : 4;
+        uint64_t qid_offres              : 4;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug6_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t qid_offm                : 3;       /**< Qid offset max */
+        uint64_t static_p                : 1;       /**< Static port when set */
+        uint64_t work_min                : 3;       /**< Work minor */
+        uint64_t dwri_chk                : 1;       /**< Dwrite checksum mode */
+        uint64_t dwri_uid                : 1;       /**< Dwrite UID */
+        uint64_t dwri_mod                : 2;       /**< Dwrite mod */
+#else
+        uint64_t dwri_mod                : 2;
+        uint64_t dwri_uid                : 1;
+        uint64_t dwri_chk                : 1;
+        uint64_t work_min                : 3;
+        uint64_t static_p                : 1;
+        uint64_t qid_offm                : 3;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug6_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug6_cn30xx    cn38xx;
+    struct cvmx_pko_mem_debug6_cn30xx    cn38xxp2;
+    struct cvmx_pko_mem_debug6_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t curr_ptr                : 11;      /**< Internal state */
+#else
+        uint64_t curr_ptr                : 11;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug6_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_37_63          : 27;
+        uint64_t qid_offres              : 4;       /**< Internal state */
+        uint64_t qid_offths              : 4;       /**< Internal state */
+        uint64_t preempter               : 1;       /**< Internal state */
+        uint64_t preemptee               : 1;       /**< Internal state */
+        uint64_t preempted               : 1;       /**< Internal state */
+        uint64_t active                  : 1;       /**< Internal state */
+        uint64_t statc                   : 1;       /**< Internal state */
+        uint64_t qos                     : 3;       /**< Internal state */
+        uint64_t qcb_ridx                : 5;       /**< Internal state */
+        uint64_t qid_offmax              : 4;       /**< Internal state */
+        uint64_t qid_off                 : 4;       /**< Internal state */
+        uint64_t qid_base                : 8;       /**< Internal state */
+#else
+        uint64_t qid_base                : 8;
+        uint64_t qid_off                 : 4;
+        uint64_t qid_offmax              : 4;
+        uint64_t qcb_ridx                : 5;
+        uint64_t qos                     : 3;
+        uint64_t statc                   : 1;
+        uint64_t active                  : 1;
+        uint64_t preempted               : 1;
+        uint64_t preemptee               : 1;
+        uint64_t preempter               : 1;
+        uint64_t qid_offths              : 4;
+        uint64_t qid_offres              : 4;
+        uint64_t reserved_37_63          : 27;
+#endif
+    } cn52xx;
+    struct cvmx_pko_mem_debug6_cn52xx    cn52xxp1;
+    struct cvmx_pko_mem_debug6_cn52xx    cn56xx;
+    struct cvmx_pko_mem_debug6_cn52xx    cn56xxp1;
+    struct cvmx_pko_mem_debug6_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug6_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug6_t;
+
+
+/**
+ * cvmx_pko_mem_debug7
+ *
+ * Notes:
+ * Internal per-queue state intended for debug use only - pko_prt_qsb.state[63:0]
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t qos                     : 5;       /**< QOS mask to enable the queue when set */
+        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
+        uint64_t reserved_0_57           : 58;
+#else
+        uint64_t reserved_0_57           : 58;
+        uint64_t tail                    : 1;
+        uint64_t qos                     : 5;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug7_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_58_63          : 6;
+        uint64_t dwb                     : 9;       /**< Calculated DWB count used for free operation */
+        uint64_t start                   : 33;      /**< Calculated start address used for free operation */
+        uint64_t size                    : 16;      /**< Packet length in bytes */
+#else
+        uint64_t size                    : 16;
+        uint64_t start                   : 33;
+        uint64_t dwb                     : 9;
+        uint64_t reserved_58_63          : 6;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug7_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug7_cn30xx    cn38xx;
+    struct cvmx_pko_mem_debug7_cn30xx    cn38xxp2;
+    struct cvmx_pko_mem_debug7_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t qos                     : 5;       /**< QOS mask to enable the queue when set */
+        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
+        uint64_t buf_siz                 : 13;      /**< Command buffer remaining size in words */
+        uint64_t buf_ptr                 : 33;      /**< Command word pointer */
+        uint64_t qcb_widx                : 6;       /**< Buffer write index for QCB */
+        uint64_t qcb_ridx                : 6;       /**< Buffer read  index for QCB */
+#else
+        uint64_t qcb_ridx                : 6;
+        uint64_t qcb_widx                : 6;
+        uint64_t buf_ptr                 : 33;
+        uint64_t buf_siz                 : 13;
+        uint64_t tail                    : 1;
+        uint64_t qos                     : 5;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug7_cn50xx    cn52xx;
+    struct cvmx_pko_mem_debug7_cn50xx    cn52xxp1;
+    struct cvmx_pko_mem_debug7_cn50xx    cn56xx;
+    struct cvmx_pko_mem_debug7_cn50xx    cn56xxp1;
+    struct cvmx_pko_mem_debug7_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug7_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug7_t;
+
+
+/**
+ * cvmx_pko_mem_debug8
+ *
+ * Notes:
+ * Internal per-queue state intended for debug use only - pko_prt_qsb.state[91:64]
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug8_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_59_63          : 5;
+        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
+        uint64_t buf_siz                 : 13;      /**< Command buffer remaining size in words */
+        uint64_t reserved_0_44           : 45;
+#else
+        uint64_t reserved_0_44           : 45;
+        uint64_t buf_siz                 : 13;
+        uint64_t tail                    : 1;
+        uint64_t reserved_59_63          : 5;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug8_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t qos                     : 5;       /**< QOS mask to enable the queue when set */
+        uint64_t tail                    : 1;       /**< This queue is the last (tail) in the queue array */
+        uint64_t buf_siz                 : 13;      /**< Command buffer remaining size in words */
+        uint64_t buf_ptr                 : 33;      /**< Command word pointer */
+        uint64_t qcb_widx                : 6;       /**< Buffer write index for QCB */
+        uint64_t qcb_ridx                : 6;       /**< Buffer read  index for QCB */
+#else
+        uint64_t qcb_ridx                : 6;
+        uint64_t qcb_widx                : 6;
+        uint64_t buf_ptr                 : 33;
+        uint64_t buf_siz                 : 13;
+        uint64_t tail                    : 1;
+        uint64_t qos                     : 5;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug8_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug8_cn30xx    cn38xx;
+    struct cvmx_pko_mem_debug8_cn30xx    cn38xxp2;
+    struct cvmx_pko_mem_debug8_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t doorbell                : 20;      /**< Doorbell count */
+        uint64_t reserved_6_7            : 2;
+        uint64_t static_p                : 1;       /**< Static priority */
+        uint64_t s_tail                  : 1;       /**< Static tail */
+        uint64_t static_q                : 1;       /**< Static priority */
+        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
+#else
+        uint64_t qos                     : 3;
+        uint64_t static_q                : 1;
+        uint64_t s_tail                  : 1;
+        uint64_t static_p                : 1;
+        uint64_t reserved_6_7            : 2;
+        uint64_t doorbell                : 20;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug8_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t preempter               : 1;       /**< Preempter */
+        uint64_t doorbell                : 20;      /**< Doorbell count */
+        uint64_t reserved_7_7            : 1;
+        uint64_t preemptee               : 1;       /**< Preemptee */
+        uint64_t static_p                : 1;       /**< Static priority */
+        uint64_t s_tail                  : 1;       /**< Static tail */
+        uint64_t static_q                : 1;       /**< Static priority */
+        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
+#else
+        uint64_t qos                     : 3;
+        uint64_t static_q                : 1;
+        uint64_t s_tail                  : 1;
+        uint64_t static_p                : 1;
+        uint64_t preemptee               : 1;
+        uint64_t reserved_7_7            : 1;
+        uint64_t doorbell                : 20;
+        uint64_t preempter               : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn52xx;
+    struct cvmx_pko_mem_debug8_cn52xx    cn52xxp1;
+    struct cvmx_pko_mem_debug8_cn52xx    cn56xx;
+    struct cvmx_pko_mem_debug8_cn52xx    cn56xxp1;
+    struct cvmx_pko_mem_debug8_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug8_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug8_t;
+
+
+/**
+ * cvmx_pko_mem_debug9
+ *
+ * Notes:
+ * Internal per-port state intended for debug use only - pko.dat.ptr.ptrs0, pko.dat.ptr.ptrs3
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_debug9_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t ptrs0                   : 17;      /**< Internal state */
+        uint64_t reserved_0_31           : 32;
+#else
+        uint64_t reserved_0_31           : 32;
+        uint64_t ptrs0                   : 17;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } s;
+    struct cvmx_pko_mem_debug9_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t doorbell                : 20;      /**< Doorbell count */
+        uint64_t reserved_5_7            : 3;
+        uint64_t s_tail                  : 1;       /**< reads as zero (S_TAIL cannot be read) */
+        uint64_t static_q                : 1;       /**< reads as zero (STATIC_Q cannot be read) */
+        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
+#else
+        uint64_t qos                     : 3;
+        uint64_t static_q                : 1;
+        uint64_t s_tail                  : 1;
+        uint64_t reserved_5_7            : 3;
+        uint64_t doorbell                : 20;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn30xx;
+    struct cvmx_pko_mem_debug9_cn30xx    cn31xx;
+    struct cvmx_pko_mem_debug9_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t doorbell                : 20;      /**< Doorbell count */
+        uint64_t reserved_6_7            : 2;
+        uint64_t static_p                : 1;       /**< Static priority (port) */
+        uint64_t s_tail                  : 1;       /**< Static tail */
+        uint64_t static_q                : 1;       /**< Static priority */
+        uint64_t qos                     : 3;       /**< QOS mask to enable the queue when set */
+#else
+        uint64_t qos                     : 3;
+        uint64_t static_q                : 1;
+        uint64_t s_tail                  : 1;
+        uint64_t static_p                : 1;
+        uint64_t reserved_6_7            : 2;
+        uint64_t doorbell                : 20;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn38xx;
+    struct cvmx_pko_mem_debug9_cn38xx    cn38xxp2;
+    struct cvmx_pko_mem_debug9_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_49_63          : 15;
+        uint64_t ptrs0                   : 17;      /**< Internal state */
+        uint64_t reserved_17_31          : 15;
+        uint64_t ptrs3                   : 17;      /**< Internal state */
+#else
+        uint64_t ptrs3                   : 17;
+        uint64_t reserved_17_31          : 15;
+        uint64_t ptrs0                   : 17;
+        uint64_t reserved_49_63          : 15;
+#endif
+    } cn50xx;
+    struct cvmx_pko_mem_debug9_cn50xx    cn52xx;
+    struct cvmx_pko_mem_debug9_cn50xx    cn52xxp1;
+    struct cvmx_pko_mem_debug9_cn50xx    cn56xx;
+    struct cvmx_pko_mem_debug9_cn50xx    cn56xxp1;
+    struct cvmx_pko_mem_debug9_cn50xx    cn58xx;
+    struct cvmx_pko_mem_debug9_cn50xx    cn58xxp1;
+} cvmx_pko_mem_debug9_t;
+
+
+/**
+ * cvmx_pko_mem_port_ptrs
+ *
+ * Notes:
+ * Sets the port to engine mapping, per port.  Ports marked as static priority need not be contiguous,
+ * but they must be the lowest numbered PIDs mapped to this EID and must have QOS_MASK=0xff.  If EID==8
+ * or EID==9, then PID[1:0] is used to direct the packet to the correct port on that interface.
+ * EID==15 can be used for unused PKO-internal ports.
+ * BP_PORT==63 means that the PKO-internal port is not backpressured.
+ * BP_PORTs are assumed to belong to an interface as follows:
+ *   36 <= BP_PORT < 40 -> loopback   interface
+ *   32 <= BP_PORT < 36 -> PCIe       interface
+ *   0  <= BP_PORT < 16 -> SGMII/Xaui interface 0
+ * The reset configuration is the following:
+ *   PID EID(ext port) BP_PORT QOS_MASK STATIC_P
+ *   -------------------------------------------
+ *     0   0( 0)             0     0xff        0
+ *     1   1( 1)             1     0xff        0
+ *     2   2( 2)             2     0xff        0
+ *     3   3( 3)             3     0xff        0
+ *     4   0( 0)             4     0xff        0
+ *     5   1( 1)             5     0xff        0
+ *     6   2( 2)             6     0xff        0
+ *     7   3( 3)             7     0xff        0
+ *     8   0( 0)             8     0xff        0
+ *     9   1( 1)             9     0xff        0
+ *    10   2( 2)            10     0xff        0
+ *    11   3( 3)            11     0xff        0
+ *    12   0( 0)            12     0xff        0
+ *    13   1( 1)            13     0xff        0
+ *    14   2( 2)            14     0xff        0
+ *    15   3( 3)            15     0xff        0
+ *   -------------------------------------------
+ *    16   0( 0)             0     0xff        0
+ *    17   1( 1)             1     0xff        0
+ *    18   2( 2)             2     0xff        0
+ *    19   3( 3)             3     0xff        0
+ *    20   0( 0)             4     0xff        0
+ *    21   1( 1)             5     0xff        0
+ *    22   2( 2)             6     0xff        0
+ *    23   3( 3)             7     0xff        0
+ *    24   0( 0)             8     0xff        0
+ *    25   1( 1)             9     0xff        0
+ *    26   2( 2)            10     0xff        0
+ *    27   3( 3)            11     0xff        0
+ *    28   0( 0)            12     0xff        0
+ *    29   1( 1)            13     0xff        0
+ *    30   2( 2)            14     0xff        0
+ *    31   3( 3)            15     0xff        0
+ *   -------------------------------------------
+ *    32   8(32)            32     0xff        0
+ *    33   8(33)            33     0xff        0
+ *    34   8(34)            34     0xff        0
+ *    35   8(35)            35     0xff        0
+ *   -------------------------------------------
+ *    36   9(36)            36     0xff        0
+ *    37   9(37)            37     0xff        0
+ *    38   9(38)            38     0xff        0
+ *    39   9(39)            39     0xff        0
+ * 
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_port_ptrs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_62_63          : 2;
+        uint64_t static_p                : 1;       /**< Set if this PID has static priority */
+        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
+        uint64_t reserved_16_52          : 37;
+        uint64_t bp_port                 : 6;       /**< PID listens to BP_PORT for per-packet backpressure
+                                                         Legal BP_PORTs: 0-39, 63 (63 means no BP) */
+        uint64_t eid                     : 4;       /**< Engine ID to which this port is mapped
+                                                         Legal EIDs: 0-9, 15 (15 only if port not used) */
+        uint64_t pid                     : 6;       /**< Port ID[5:0] */
+#else
+        uint64_t pid                     : 6;
+        uint64_t eid                     : 4;
+        uint64_t bp_port                 : 6;
+        uint64_t reserved_16_52          : 37;
+        uint64_t qos_mask                : 8;
+        uint64_t static_p                : 1;
+        uint64_t reserved_62_63          : 2;
+#endif
+    } s;
+    struct cvmx_pko_mem_port_ptrs_s      cn52xx;
+    struct cvmx_pko_mem_port_ptrs_s      cn52xxp1;
+    struct cvmx_pko_mem_port_ptrs_s      cn56xx;
+    struct cvmx_pko_mem_port_ptrs_s      cn56xxp1;
+} cvmx_pko_mem_port_ptrs_t;
+
+
+/**
+ * cvmx_pko_mem_port_qos
+ *
+ * Notes:
+ * Sets the QOS mask, per port.  These QOS_MASK bits are logically and physically the same QOS_MASK
+ * bits in PKO_MEM_PORT_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
+ * operation without affecting any other port state.  The engine to which port PID is mapped is engine
+ * EID.  Note that the port to engine mapping must be the same as was previously programmed via the
+ * PKO_MEM_PORT_PTRS CSR.
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_port_qos_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_61_63          : 3;
+        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
+        uint64_t reserved_10_52          : 43;
+        uint64_t eid                     : 4;       /**< Engine ID to which this port is mapped
+                                                         Legal EIDs: 0-9 */
+        uint64_t pid                     : 6;       /**< Port ID[5:0] */
+#else
+        uint64_t pid                     : 6;
+        uint64_t eid                     : 4;
+        uint64_t reserved_10_52          : 43;
+        uint64_t qos_mask                : 8;
+        uint64_t reserved_61_63          : 3;
+#endif
+    } s;
+    struct cvmx_pko_mem_port_qos_s       cn52xx;
+    struct cvmx_pko_mem_port_qos_s       cn52xxp1;
+    struct cvmx_pko_mem_port_qos_s       cn56xx;
+    struct cvmx_pko_mem_port_qos_s       cn56xxp1;
+} cvmx_pko_mem_port_qos_t;
+
+
+/**
+ * cvmx_pko_mem_port_rate0
+ *
+ * Notes:
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_port_rate0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_51_63          : 13;
+        uint64_t rate_word               : 19;      /**< Rate limiting adder per 8 byte */
+        uint64_t rate_pkt                : 24;      /**< Rate limiting adder per packet */
+        uint64_t reserved_6_7            : 2;
+        uint64_t pid                     : 6;       /**< Port ID[5:0] */
+#else
+        uint64_t pid                     : 6;
+        uint64_t reserved_6_7            : 2;
+        uint64_t rate_pkt                : 24;
+        uint64_t rate_word               : 19;
+        uint64_t reserved_51_63          : 13;
+#endif
+    } s;
+    struct cvmx_pko_mem_port_rate0_s     cn52xx;
+    struct cvmx_pko_mem_port_rate0_s     cn52xxp1;
+    struct cvmx_pko_mem_port_rate0_s     cn56xx;
+    struct cvmx_pko_mem_port_rate0_s     cn56xxp1;
+} cvmx_pko_mem_port_rate0_t;
+
+
+/**
+ * cvmx_pko_mem_port_rate1
+ *
+ * Notes:
+ * Writing PKO_MEM_PORT_RATE1[PID,RATE_LIM] has the side effect of setting the corresponding
+ * accumulator to zero.
+ * This CSR is a memory of 40 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_port_rate1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rate_lim                : 24;      /**< Rate limiting accumulator limit */
+        uint64_t reserved_6_7            : 2;
+        uint64_t pid                     : 6;       /**< Port ID[5:0] */
+#else
+        uint64_t pid                     : 6;
+        uint64_t reserved_6_7            : 2;
+        uint64_t rate_lim                : 24;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pko_mem_port_rate1_s     cn52xx;
+    struct cvmx_pko_mem_port_rate1_s     cn52xxp1;
+    struct cvmx_pko_mem_port_rate1_s     cn56xx;
+    struct cvmx_pko_mem_port_rate1_s     cn56xxp1;
+} cvmx_pko_mem_port_rate1_t;
+
+
+/**
+ * cvmx_pko_mem_queue_ptrs
+ *
+ * Notes:
+ * Sets the queue to port mapping and the initial command buffer pointer, per queue
+ * Each queue may map to at most one port.  No more than 16 queues may map to a port.  The set of
+ * queues that is mapped to a port must be a contiguous array of queues.  The port to which queue QID
+ * is mapped is port PID.  The index of queue QID in port PID's queue list is IDX.  The last queue in
+ * port PID's queue array must have its TAIL bit set.  Unused queues must be mapped to port 63.
+ * STATIC_Q marks queue QID as having static priority.  STATIC_P marks the port PID to which QID is
+ * mapped as having at least one queue with static priority.  If any QID that maps to PID has static
+ * priority, then all QID that map to PID must have STATIC_P set.  Queues marked as static priority
+ * must be contiguous and begin at IDX 0.  The last queue that is marked as having static priority
+ * must have its S_TAIL bit set.
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_queue_ptrs_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t s_tail                  : 1;       /**< Set if this QID is the tail of the static queues */
+        uint64_t static_p                : 1;       /**< Set if any QID in this PID has static priority */
+        uint64_t static_q                : 1;       /**< Set if this QID has static priority */
+        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
+        uint64_t buf_ptr                 : 36;      /**< Command buffer pointer, <23:17> MBZ */
+        uint64_t tail                    : 1;       /**< Set if this QID is the tail of the queue array */
+        uint64_t index                   : 3;       /**< Index[2:0] (distance from head) in the queue array */
+        uint64_t port                    : 6;       /**< Port ID to which this queue is mapped */
+        uint64_t queue                   : 7;       /**< Queue ID[6:0] */
+#else
+        uint64_t queue                   : 7;
+        uint64_t port                    : 6;
+        uint64_t index                   : 3;
+        uint64_t tail                    : 1;
+        uint64_t buf_ptr                 : 36;
+        uint64_t qos_mask                : 8;
+        uint64_t static_q                : 1;
+        uint64_t static_p                : 1;
+        uint64_t s_tail                  : 1;
+#endif
+    } s;
+    struct cvmx_pko_mem_queue_ptrs_s     cn30xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn31xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn38xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn38xxp2;
+    struct cvmx_pko_mem_queue_ptrs_s     cn50xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn52xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn52xxp1;
+    struct cvmx_pko_mem_queue_ptrs_s     cn56xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn56xxp1;
+    struct cvmx_pko_mem_queue_ptrs_s     cn58xx;
+    struct cvmx_pko_mem_queue_ptrs_s     cn58xxp1;
+} cvmx_pko_mem_queue_ptrs_t;
+
+
+/**
+ * cvmx_pko_mem_queue_qos
+ *
+ * Notes:
+ * Sets the QOS mask, per queue.  These QOS_MASK bits are logically and physically the same QOS_MASK
+ * bits in PKO_MEM_QUEUE_PTRS.  This CSR address allows the QOS_MASK bits to be written during PKO
+ * operation without affecting any other queue state.  The port to which queue QID is mapped is port
+ * PID.  Note that the queue to port mapping must be the same as was previously programmed via the
+ * PKO_MEM_QUEUE_PTRS CSR.
+ * This CSR is a memory of 256 entries, and thus, the PKO_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_mem_queue_qos_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_61_63          : 3;
+        uint64_t qos_mask                : 8;       /**< Mask to control priority across 8 QOS rounds */
+        uint64_t reserved_13_52          : 40;
+        uint64_t pid                     : 6;       /**< Port ID to which this queue is mapped */
+        uint64_t qid                     : 7;       /**< Queue ID */
+#else
+        uint64_t qid                     : 7;
+        uint64_t pid                     : 6;
+        uint64_t reserved_13_52          : 40;
+        uint64_t qos_mask                : 8;
+        uint64_t reserved_61_63          : 3;
+#endif
+    } s;
+    struct cvmx_pko_mem_queue_qos_s      cn30xx;
+    struct cvmx_pko_mem_queue_qos_s      cn31xx;
+    struct cvmx_pko_mem_queue_qos_s      cn38xx;
+    struct cvmx_pko_mem_queue_qos_s      cn38xxp2;
+    struct cvmx_pko_mem_queue_qos_s      cn50xx;
+    struct cvmx_pko_mem_queue_qos_s      cn52xx;
+    struct cvmx_pko_mem_queue_qos_s      cn52xxp1;
+    struct cvmx_pko_mem_queue_qos_s      cn56xx;
+    struct cvmx_pko_mem_queue_qos_s      cn56xxp1;
+    struct cvmx_pko_mem_queue_qos_s      cn58xx;
+    struct cvmx_pko_mem_queue_qos_s      cn58xxp1;
+} cvmx_pko_mem_queue_qos_t;
+
+
+/**
+ * cvmx_pko_reg_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_bist_result_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_pko_reg_bist_result_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_27_63          : 37;
+        uint64_t psb2                    : 5;       /**< BiST result of the PSB   memories (0=pass, !0=fail) */
+        uint64_t count                   : 1;       /**< BiST result of the COUNT memories (0=pass, !0=fail) */
+        uint64_t rif                     : 1;       /**< BiST result of the RIF   memories (0=pass, !0=fail) */
+        uint64_t wif                     : 1;       /**< BiST result of the WIF   memories (0=pass, !0=fail) */
+        uint64_t ncb                     : 1;       /**< BiST result of the NCB   memories (0=pass, !0=fail) */
+        uint64_t out                     : 1;       /**< BiST result of the OUT   memories (0=pass, !0=fail) */
+        uint64_t crc                     : 1;       /**< BiST result of the CRC   memories (0=pass, !0=fail) */
+        uint64_t chk                     : 1;       /**< BiST result of the CHK   memories (0=pass, !0=fail) */
+        uint64_t qsb                     : 2;       /**< BiST result of the QSB   memories (0=pass, !0=fail) */
+        uint64_t qcb                     : 2;       /**< BiST result of the QCB   memories (0=pass, !0=fail) */
+        uint64_t pdb                     : 4;       /**< BiST result of the PDB   memories (0=pass, !0=fail) */
+        uint64_t psb                     : 7;       /**< BiST result of the PSB   memories (0=pass, !0=fail) */
+#else
+        uint64_t psb                     : 7;
+        uint64_t pdb                     : 4;
+        uint64_t qcb                     : 2;
+        uint64_t qsb                     : 2;
+        uint64_t chk                     : 1;
+        uint64_t crc                     : 1;
+        uint64_t out                     : 1;
+        uint64_t ncb                     : 1;
+        uint64_t wif                     : 1;
+        uint64_t rif                     : 1;
+        uint64_t count                   : 1;
+        uint64_t psb2                    : 5;
+        uint64_t reserved_27_63          : 37;
+#endif
+    } cn30xx;
+    struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
+    struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
+    struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
+    struct cvmx_pko_reg_bist_result_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_33_63          : 31;
+        uint64_t csr                     : 1;       /**< BiST result of CSR      memories (0=pass, !0=fail) */
+        uint64_t iob                     : 1;       /**< BiST result of IOB      memories (0=pass, !0=fail) */
+        uint64_t out_crc                 : 1;       /**< BiST result of OUT_CRC  memories (0=pass, !0=fail) */
+        uint64_t out_ctl                 : 3;       /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
+        uint64_t out_sta                 : 1;       /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
+        uint64_t out_wif                 : 1;       /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
+        uint64_t prt_chk                 : 3;       /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
+        uint64_t prt_nxt                 : 1;       /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
+        uint64_t prt_psb                 : 6;       /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+        uint64_t ncb_inb                 : 2;       /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
+        uint64_t prt_qcb                 : 2;       /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
+        uint64_t prt_qsb                 : 3;       /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
+        uint64_t dat_dat                 : 4;       /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
+        uint64_t dat_ptr                 : 4;       /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
+#else
+        uint64_t dat_ptr                 : 4;
+        uint64_t dat_dat                 : 4;
+        uint64_t prt_qsb                 : 3;
+        uint64_t prt_qcb                 : 2;
+        uint64_t ncb_inb                 : 2;
+        uint64_t prt_psb                 : 6;
+        uint64_t prt_nxt                 : 1;
+        uint64_t prt_chk                 : 3;
+        uint64_t out_wif                 : 1;
+        uint64_t out_sta                 : 1;
+        uint64_t out_ctl                 : 3;
+        uint64_t out_crc                 : 1;
+        uint64_t iob                     : 1;
+        uint64_t csr                     : 1;
+        uint64_t reserved_33_63          : 31;
+#endif
+    } cn50xx;
+    struct cvmx_pko_reg_bist_result_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_35_63          : 29;
+        uint64_t csr                     : 1;       /**< BiST result of CSR      memories (0=pass, !0=fail) */
+        uint64_t iob                     : 1;       /**< BiST result of IOB      memories (0=pass, !0=fail) */
+        uint64_t out_dat                 : 1;       /**< BiST result of OUT_DAT  memories (0=pass, !0=fail) */
+        uint64_t out_ctl                 : 3;       /**< BiST result of OUT_CTL  memories (0=pass, !0=fail) */
+        uint64_t out_sta                 : 1;       /**< BiST result of OUT_STA  memories (0=pass, !0=fail) */
+        uint64_t out_wif                 : 1;       /**< BiST result of OUT_WIF  memories (0=pass, !0=fail) */
+        uint64_t prt_chk                 : 3;       /**< BiST result of PRT_CHK  memories (0=pass, !0=fail) */
+        uint64_t prt_nxt                 : 1;       /**< BiST result of PRT_NXT  memories (0=pass, !0=fail) */
+        uint64_t prt_psb                 : 8;       /**< BiST result of PRT_PSB  memories (0=pass, !0=fail) */
+        uint64_t ncb_inb                 : 2;       /**< BiST result of NCB_INB  memories (0=pass, !0=fail) */
+        uint64_t prt_qcb                 : 2;       /**< BiST result of PRT_QCB  memories (0=pass, !0=fail) */
+        uint64_t prt_qsb                 : 3;       /**< BiST result of PRT_QSB  memories (0=pass, !0=fail) */
+        uint64_t prt_ctl                 : 2;       /**< BiST result of PRT_CTL  memories (0=pass, !0=fail) */
+        uint64_t dat_dat                 : 2;       /**< BiST result of DAT_DAT  memories (0=pass, !0=fail) */
+        uint64_t dat_ptr                 : 4;       /**< BiST result of DAT_PTR  memories (0=pass, !0=fail) */
+#else
+        uint64_t dat_ptr                 : 4;
+        uint64_t dat_dat                 : 2;
+        uint64_t prt_ctl                 : 2;
+        uint64_t prt_qsb                 : 3;
+        uint64_t prt_qcb                 : 2;
+        uint64_t ncb_inb                 : 2;
+        uint64_t prt_psb                 : 8;
+        uint64_t prt_nxt                 : 1;
+        uint64_t prt_chk                 : 3;
+        uint64_t out_wif                 : 1;
+        uint64_t out_sta                 : 1;
+        uint64_t out_ctl                 : 3;
+        uint64_t out_dat                 : 1;
+        uint64_t iob                     : 1;
+        uint64_t csr                     : 1;
+        uint64_t reserved_35_63          : 29;
+#endif
+    } cn52xx;
+    struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
+    struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
+    struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
+    struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
+    struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
+} cvmx_pko_reg_bist_result_t;
+
+
+/**
+ * cvmx_pko_reg_cmd_buf
+ *
+ * Notes:
+ * Sets the command buffer parameters
+ * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
+ * lists to be used when freeing command buffer segments.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_cmd_buf_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_23_63          : 41;
+        uint64_t pool                    : 3;       /**< Free list used to free command buffer segments */
+        uint64_t reserved_13_19          : 7;
+        uint64_t size                    : 13;      /**< Number of uint64s per command buffer segment */
+#else
+        uint64_t size                    : 13;
+        uint64_t reserved_13_19          : 7;
+        uint64_t pool                    : 3;
+        uint64_t reserved_23_63          : 41;
+#endif
+    } s;
+    struct cvmx_pko_reg_cmd_buf_s        cn30xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn31xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn38xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn38xxp2;
+    struct cvmx_pko_reg_cmd_buf_s        cn50xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn52xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn52xxp1;
+    struct cvmx_pko_reg_cmd_buf_s        cn56xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn56xxp1;
+    struct cvmx_pko_reg_cmd_buf_s        cn58xx;
+    struct cvmx_pko_reg_cmd_buf_s        cn58xxp1;
+} cvmx_pko_reg_cmd_buf_t;
+
+
+/**
+ * cvmx_pko_reg_crc_ctl#
+ *
+ * Notes:
+ * Controls datapath reflection when calculating CRC
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_crc_ctlx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t invres                  : 1;       /**< Invert the result */
+        uint64_t refin                   : 1;       /**< Reflect the bits in each byte.
+                                                          Byte order does not change.
+                                                         - 0: CRC is calculated MSB to LSB
+                                                         - 1: CRC is calculated MLB to MSB */
+#else
+        uint64_t refin                   : 1;
+        uint64_t invres                  : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pko_reg_crc_ctlx_s       cn38xx;
+    struct cvmx_pko_reg_crc_ctlx_s       cn38xxp2;
+    struct cvmx_pko_reg_crc_ctlx_s       cn58xx;
+    struct cvmx_pko_reg_crc_ctlx_s       cn58xxp1;
+} cvmx_pko_reg_crc_ctlx_t;
+
+
+/**
+ * cvmx_pko_reg_crc_enable
+ *
+ * Notes:
+ * Enables CRC for the GMX ports.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_crc_enable_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t enable                  : 32;      /**< Mask for ports 31-0 to enable CRC
+                                                         Mask bit==0 means CRC not enabled
+                                                         Mask bit==1 means CRC     enabled
+                                                         Note that CRC should be enabled only when using SPI4.2 */
+#else
+        uint64_t enable                  : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pko_reg_crc_enable_s     cn38xx;
+    struct cvmx_pko_reg_crc_enable_s     cn38xxp2;
+    struct cvmx_pko_reg_crc_enable_s     cn58xx;
+    struct cvmx_pko_reg_crc_enable_s     cn58xxp1;
+} cvmx_pko_reg_crc_enable_t;
+
+
+/**
+ * cvmx_pko_reg_crc_iv#
+ *
+ * Notes:
+ * Determines the IV used by the CRC algorithm
+ * * PKO_CRC_IV
+ *  PKO_CRC_IV controls the initial state of the CRC algorithm.  Octane can
+ *  support a wide range of CRC algorithms and as such, the IV must be
+ *  carefully constructed to meet the specific algorithm.  The code below
+ *  determines the value to program into Octane based on the algorthim's IV
+ *  and width.  In the case of Octane, the width should always be 32.
+ * 
+ *  PKO_CRC_IV0 sets the IV for ports 0-15 while PKO_CRC_IV1 sets the IV for
+ *  ports 16-31.
+ * 
+ *   @verbatim
+ *   unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w)
+ *   [
+ *     int i;
+ *     int doit;
+ *     unsigned int current_val = algorithm_iv;
+ * 
+ *     for(i = 0; i < w; i++) [
+ *       doit = current_val & 0x1;
+ * 
+ *       if(doit) current_val ^= poly;
+ *       assert(!(current_val & 0x1));
+ * 
+ *       current_val = (current_val >> 1) | (doit << (w-1));
+ *     ]
+ * 
+ *     return current_val;
+ *   ]
+ *   @endverbatim
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_crc_ivx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iv                      : 32;      /**< IV used by the CRC algorithm.  Default is FCS32. */
+#else
+        uint64_t iv                      : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pko_reg_crc_ivx_s        cn38xx;
+    struct cvmx_pko_reg_crc_ivx_s        cn38xxp2;
+    struct cvmx_pko_reg_crc_ivx_s        cn58xx;
+    struct cvmx_pko_reg_crc_ivx_s        cn58xxp1;
+} cvmx_pko_reg_crc_ivx_t;
+
+
+/**
+ * cvmx_pko_reg_debug0
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_debug0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t asserts                 : 64;      /**< Various assertion checks */
+#else
+        uint64_t asserts                 : 64;
+#endif
+    } s;
+    struct cvmx_pko_reg_debug0_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t asserts                 : 17;      /**< Various assertion checks */
+#else
+        uint64_t asserts                 : 17;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn30xx;
+    struct cvmx_pko_reg_debug0_cn30xx    cn31xx;
+    struct cvmx_pko_reg_debug0_cn30xx    cn38xx;
+    struct cvmx_pko_reg_debug0_cn30xx    cn38xxp2;
+    struct cvmx_pko_reg_debug0_s         cn50xx;
+    struct cvmx_pko_reg_debug0_s         cn52xx;
+    struct cvmx_pko_reg_debug0_s         cn52xxp1;
+    struct cvmx_pko_reg_debug0_s         cn56xx;
+    struct cvmx_pko_reg_debug0_s         cn56xxp1;
+    struct cvmx_pko_reg_debug0_s         cn58xx;
+    struct cvmx_pko_reg_debug0_s         cn58xxp1;
+} cvmx_pko_reg_debug0_t;
+
+
+/**
+ * cvmx_pko_reg_debug1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_debug1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t asserts                 : 64;      /**< Various assertion checks */
+#else
+        uint64_t asserts                 : 64;
+#endif
+    } s;
+    struct cvmx_pko_reg_debug1_s         cn50xx;
+    struct cvmx_pko_reg_debug1_s         cn52xx;
+    struct cvmx_pko_reg_debug1_s         cn52xxp1;
+    struct cvmx_pko_reg_debug1_s         cn56xx;
+    struct cvmx_pko_reg_debug1_s         cn56xxp1;
+    struct cvmx_pko_reg_debug1_s         cn58xx;
+    struct cvmx_pko_reg_debug1_s         cn58xxp1;
+} cvmx_pko_reg_debug1_t;
+
+
+/**
+ * cvmx_pko_reg_debug2
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_debug2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t asserts                 : 64;      /**< Various assertion checks */
+#else
+        uint64_t asserts                 : 64;
+#endif
+    } s;
+    struct cvmx_pko_reg_debug2_s         cn50xx;
+    struct cvmx_pko_reg_debug2_s         cn52xx;
+    struct cvmx_pko_reg_debug2_s         cn52xxp1;
+    struct cvmx_pko_reg_debug2_s         cn56xx;
+    struct cvmx_pko_reg_debug2_s         cn56xxp1;
+    struct cvmx_pko_reg_debug2_s         cn58xx;
+    struct cvmx_pko_reg_debug2_s         cn58xxp1;
+} cvmx_pko_reg_debug2_t;
+
+
+/**
+ * cvmx_pko_reg_debug3
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_debug3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t asserts                 : 64;      /**< Various assertion checks */
+#else
+        uint64_t asserts                 : 64;
+#endif
+    } s;
+    struct cvmx_pko_reg_debug3_s         cn50xx;
+    struct cvmx_pko_reg_debug3_s         cn52xx;
+    struct cvmx_pko_reg_debug3_s         cn52xxp1;
+    struct cvmx_pko_reg_debug3_s         cn56xx;
+    struct cvmx_pko_reg_debug3_s         cn56xxp1;
+    struct cvmx_pko_reg_debug3_s         cn58xx;
+    struct cvmx_pko_reg_debug3_s         cn58xxp1;
+} cvmx_pko_reg_debug3_t;
+
+
+/**
+ * cvmx_pko_reg_engine_inflight
+ *
+ * Notes:
+ * Sets the maximum number of inflight packets, per engine.  Values greater than 4 are illegal.
+ * Setting an engine's value to 0 effectively stops the engine.
+ * Note that engines 4-7 do not exist
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_engine_inflight_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t engine9                 : 4;       /**< Maximum number of inflight packets for engine9 */
+        uint64_t engine8                 : 4;       /**< Maximum number of inflight packets for engine8 */
+        uint64_t engine7                 : 4;       /**< Maximum number of inflight packets for engine7 */
+        uint64_t engine6                 : 4;       /**< Maximum number of inflight packets for engine6 */
+        uint64_t engine5                 : 4;       /**< Maximum number of inflight packets for engine5 */
+        uint64_t engine4                 : 4;       /**< Maximum number of inflight packets for engine4 */
+        uint64_t engine3                 : 4;       /**< Maximum number of inflight packets for engine3 */
+        uint64_t engine2                 : 4;       /**< Maximum number of inflight packets for engine2 */
+        uint64_t engine1                 : 4;       /**< Maximum number of inflight packets for engine1 */
+        uint64_t engine0                 : 4;       /**< Maximum number of inflight packets for engine0 */
+#else
+        uint64_t engine0                 : 4;
+        uint64_t engine1                 : 4;
+        uint64_t engine2                 : 4;
+        uint64_t engine3                 : 4;
+        uint64_t engine4                 : 4;
+        uint64_t engine5                 : 4;
+        uint64_t engine6                 : 4;
+        uint64_t engine7                 : 4;
+        uint64_t engine8                 : 4;
+        uint64_t engine9                 : 4;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_pko_reg_engine_inflight_s cn52xx;
+    struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
+    struct cvmx_pko_reg_engine_inflight_s cn56xx;
+    struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
+} cvmx_pko_reg_engine_inflight_t;
+
+
+/**
+ * cvmx_pko_reg_engine_thresh
+ *
+ * Notes:
+ * When not enabled, packet data may be sent as soon as it is written into PKO's internal buffers.
+ * When enabled and the packet fits entirely in the PKO's internal buffer, none of the packet data will
+ * be sent until all of it has been written into the PKO's internal buffer.  Note that a packet is
+ * considered to fit entirely only if the packet's size is <= BUFFER_SIZE-8.  When enabled and the
+ * packet does not fit entirely in the PKO's internal buffer, none of the packet data will be sent until
+ * at least BUFFER_SIZE-256 bytes of the packet have been written into the PKO's internal buffer
+ * (note that BUFFER_SIZE is a function of PKO_REG_GMX_PORT_MODE above)
+ * Note that engines 4-7 do not exist, so MASK<7:4> MBZ
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_engine_thresh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t mask                    : 10;      /**< Mask[n]=0 disables packet send threshold for engine n
+                                                         Mask[n]=1 enables  packet send threshold for engine n  $PR       NS */
+#else
+        uint64_t mask                    : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_pko_reg_engine_thresh_s  cn52xx;
+    struct cvmx_pko_reg_engine_thresh_s  cn52xxp1;
+    struct cvmx_pko_reg_engine_thresh_s  cn56xx;
+    struct cvmx_pko_reg_engine_thresh_s  cn56xxp1;
+} cvmx_pko_reg_engine_thresh_t;
+
+
+/**
+ * cvmx_pko_reg_error
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_error_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t currzero                : 1;       /**< A packet data pointer has size=0 */
+        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
+        uint64_t parity                  : 1;       /**< Read parity error at port data buffer */
+#else
+        uint64_t parity                  : 1;
+        uint64_t doorbell                : 1;
+        uint64_t currzero                : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_pko_reg_error_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
+        uint64_t parity                  : 1;       /**< Read parity error at port data buffer */
+#else
+        uint64_t parity                  : 1;
+        uint64_t doorbell                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn30xx;
+    struct cvmx_pko_reg_error_cn30xx     cn31xx;
+    struct cvmx_pko_reg_error_cn30xx     cn38xx;
+    struct cvmx_pko_reg_error_cn30xx     cn38xxp2;
+    struct cvmx_pko_reg_error_s          cn50xx;
+    struct cvmx_pko_reg_error_s          cn52xx;
+    struct cvmx_pko_reg_error_s          cn52xxp1;
+    struct cvmx_pko_reg_error_s          cn56xx;
+    struct cvmx_pko_reg_error_s          cn56xxp1;
+    struct cvmx_pko_reg_error_s          cn58xx;
+    struct cvmx_pko_reg_error_s          cn58xxp1;
+} cvmx_pko_reg_error_t;
+
+
+/**
+ * cvmx_pko_reg_flags
+ *
+ * Notes:
+ * When set, ENA_PKO enables the PKO picker and places the PKO in normal operation.  When set, ENA_DWB
+ * enables the use of DontWriteBacks during the buffer freeing operations.  When not set, STORE_BE inverts
+ * bits[2:0] of the STORE0 byte write address.  When set, RESET causes a 4-cycle reset pulse to the
+ * entire box.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_flags_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t reset                   : 1;       /**< Reset oneshot pulse */
+        uint64_t store_be                : 1;       /**< Force STORE0 byte write address to big endian */
+        uint64_t ena_dwb                 : 1;       /**< Set to enable DontWriteBacks */
+        uint64_t ena_pko                 : 1;       /**< Set to enable the PKO picker */
+#else
+        uint64_t ena_pko                 : 1;
+        uint64_t ena_dwb                 : 1;
+        uint64_t store_be                : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_pko_reg_flags_s          cn30xx;
+    struct cvmx_pko_reg_flags_s          cn31xx;
+    struct cvmx_pko_reg_flags_s          cn38xx;
+    struct cvmx_pko_reg_flags_s          cn38xxp2;
+    struct cvmx_pko_reg_flags_s          cn50xx;
+    struct cvmx_pko_reg_flags_s          cn52xx;
+    struct cvmx_pko_reg_flags_s          cn52xxp1;
+    struct cvmx_pko_reg_flags_s          cn56xx;
+    struct cvmx_pko_reg_flags_s          cn56xxp1;
+    struct cvmx_pko_reg_flags_s          cn58xx;
+    struct cvmx_pko_reg_flags_s          cn58xxp1;
+} cvmx_pko_reg_flags_t;
+
+
+/**
+ * cvmx_pko_reg_gmx_port_mode
+ *
+ * Notes:
+ * The system has a total of 4 + 0 + 4 + 4 ports and 4 + 0 + 1 + 1 engines (GM0 + GM1 + PCI + LOOP).
+ * This CSR sets the number of GMX0 ports and amount of local storage per engine.
+ * It has no effect on the number of ports or amount of local storage per engine for
+ * PCI or LOOP.  When all GMX ports are used (MODE0=2), each GMX engine has 2.5kB of local
+ * storage.  Increasing the value of MODEn by 1 decreases the number of GMX ports by a power of 2 and
+ * increases the local storage per PKO GMX engine by a power of 2.
+ * Modes 0 and 1 are illegal and, if selected, are treated as mode 2.
+ * 
+ * MODE[n] GM[0] PCI   LOOP  GM[0]                      PCI            LOOP
+ *         ports ports ports storage/engine             storage/engine storage/engine
+ * 0       4     4     4       2.5kB                    2.5kB          2.5kB
+ * 1       4     4     4       2.5kB                    2.5kB          2.5kB
+ * 2       4     4     4       2.5kB                    2.5kB          2.5kB
+ * 3       2     4     4       5.0kB                    2.5kB          2.5kB
+ * 4       1     4     4      10.0kB                    2.5kB          2.5kB
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_gmx_port_mode_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t mode1                   : 3;       /**< # of GM1 ports = 16 >> MODE1, 0 <= MODE1 <= 5 */
+        uint64_t mode0                   : 3;       /**< # of GM0 ports = 16 >> MODE0, 0 <= MODE0 <= 5 */
+#else
+        uint64_t mode0                   : 3;
+        uint64_t mode1                   : 3;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn30xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn31xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn38xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn38xxp2;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn50xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn52xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn52xxp1;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn56xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn56xxp1;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn58xx;
+    struct cvmx_pko_reg_gmx_port_mode_s  cn58xxp1;
+} cvmx_pko_reg_gmx_port_mode_t;
+
+
+/**
+ * cvmx_pko_reg_int_mask
+ *
+ * Notes:
+ * When a mask bit is set, the corresponding interrupt is enabled.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_int_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t currzero                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[2] above */
+        uint64_t doorbell                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
+        uint64_t parity                  : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
+#else
+        uint64_t parity                  : 1;
+        uint64_t doorbell                : 1;
+        uint64_t currzero                : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_pko_reg_int_mask_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t doorbell                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
+        uint64_t parity                  : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[0] above */
+#else
+        uint64_t parity                  : 1;
+        uint64_t doorbell                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } cn30xx;
+    struct cvmx_pko_reg_int_mask_cn30xx  cn31xx;
+    struct cvmx_pko_reg_int_mask_cn30xx  cn38xx;
+    struct cvmx_pko_reg_int_mask_cn30xx  cn38xxp2;
+    struct cvmx_pko_reg_int_mask_s       cn50xx;
+    struct cvmx_pko_reg_int_mask_s       cn52xx;
+    struct cvmx_pko_reg_int_mask_s       cn52xxp1;
+    struct cvmx_pko_reg_int_mask_s       cn56xx;
+    struct cvmx_pko_reg_int_mask_s       cn56xxp1;
+    struct cvmx_pko_reg_int_mask_s       cn58xx;
+    struct cvmx_pko_reg_int_mask_s       cn58xxp1;
+} cvmx_pko_reg_int_mask_t;
+
+
+/**
+ * cvmx_pko_reg_queue_mode
+ *
+ * Notes:
+ * Sets the number of queues and amount of local storage per queue
+ * The system has a total of 256 queues and (256*8) words of local command storage.  This CSR sets the
+ * number of queues that are used.  Increasing the value of MODE by 1 decreases the number of queues
+ * by a power of 2 and increases the local storage per queue by a power of 2.
+ * MODEn queues storage/queue
+ * 0     256     64B ( 8 words)
+ * 1     128    128B (16 words)
+ * 2      64    256B (32 words)
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_queue_mode_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t mode                    : 2;       /**< # of queues = 256 >> MODE, 0 <= MODE <=2 */
+#else
+        uint64_t mode                    : 2;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pko_reg_queue_mode_s     cn30xx;
+    struct cvmx_pko_reg_queue_mode_s     cn31xx;
+    struct cvmx_pko_reg_queue_mode_s     cn38xx;
+    struct cvmx_pko_reg_queue_mode_s     cn38xxp2;
+    struct cvmx_pko_reg_queue_mode_s     cn50xx;
+    struct cvmx_pko_reg_queue_mode_s     cn52xx;
+    struct cvmx_pko_reg_queue_mode_s     cn52xxp1;
+    struct cvmx_pko_reg_queue_mode_s     cn56xx;
+    struct cvmx_pko_reg_queue_mode_s     cn56xxp1;
+    struct cvmx_pko_reg_queue_mode_s     cn58xx;
+    struct cvmx_pko_reg_queue_mode_s     cn58xxp1;
+} cvmx_pko_reg_queue_mode_t;
+
+
+/**
+ * cvmx_pko_reg_queue_ptrs1
+ *
+ * Notes:
+ * This CSR is used with PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS to allow access to queues 128-255
+ * and to allow up mapping of up to 16 queues per port.  When programming queues 128-255, the
+ * programming sequence must first write PKO_REG_QUEUE_PTRS1 and then write PKO_MEM_QUEUE_PTRS or
+ * PKO_MEM_QUEUE_QOS for each queue.
+ * See the descriptions of PKO_MEM_QUEUE_PTRS and PKO_MEM_QUEUE_QOS for further explanation of queue
+ * programming.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_queue_ptrs1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t idx3                    : 1;       /**< [3] of Index (distance from head) in the queue array */
+        uint64_t qid7                    : 1;       /**< [7] of Queue ID */
+#else
+        uint64_t qid7                    : 1;
+        uint64_t idx3                    : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn50xx;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn52xx;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn52xxp1;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn56xx;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn56xxp1;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn58xx;
+    struct cvmx_pko_reg_queue_ptrs1_s    cn58xxp1;
+} cvmx_pko_reg_queue_ptrs1_t;
+
+
+/**
+ * cvmx_pko_reg_read_idx
+ *
+ * Notes:
+ * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
+ * as memories.  The names of these CSRs begin with the prefix "PKO_MEM_".
+ * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
+ * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
+ * contents of a CSR memory can be read with consecutive CSR read commands.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pko_reg_read_idx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t inc                     : 8;       /**< Increment to add to current index for next index */
+        uint64_t index                   : 8;       /**< Index to use for next memory CSR read */
+#else
+        uint64_t index                   : 8;
+        uint64_t inc                     : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_pko_reg_read_idx_s       cn30xx;
+    struct cvmx_pko_reg_read_idx_s       cn31xx;
+    struct cvmx_pko_reg_read_idx_s       cn38xx;
+    struct cvmx_pko_reg_read_idx_s       cn38xxp2;
+    struct cvmx_pko_reg_read_idx_s       cn50xx;
+    struct cvmx_pko_reg_read_idx_s       cn52xx;
+    struct cvmx_pko_reg_read_idx_s       cn52xxp1;
+    struct cvmx_pko_reg_read_idx_s       cn56xx;
+    struct cvmx_pko_reg_read_idx_s       cn56xxp1;
+    struct cvmx_pko_reg_read_idx_s       cn58xx;
+    struct cvmx_pko_reg_read_idx_s       cn58xxp1;
+} cvmx_pko_reg_read_idx_t;
+
+
+/**
+ * cvmx_pow_bist_stat
+ *
+ * POW_BIST_STAT = POW BIST Status Register
+ * 
+ * Contains the BIST status for the POW memories ('0' = pass, '1' = fail).
+ * 
+ * Also contains the BIST status for the PP's.  Each bit in the PP field is the OR of all BIST
+ * results for the corresponding physical PP ('0' = pass, '1' = fail).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_bist_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pp                      : 16;      /**< Physical PP BIST status */
+        uint64_t reserved_0_15           : 16;
+#else
+        uint64_t reserved_0_15           : 16;
+        uint64_t pp                      : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_bist_stat_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t pp                      : 1;       /**< Physical PP BIST status */
+        uint64_t reserved_9_15           : 7;
+        uint64_t cam                     : 1;       /**< POW CAM BIST status */
+        uint64_t nbt1                    : 1;       /**< NCB transmitter memory 1 BIST status */
+        uint64_t nbt0                    : 1;       /**< NCB transmitter memory 0 BIST status */
+        uint64_t index                   : 1;       /**< Index memory BIST status */
+        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
+        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
+        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
+        uint64_t pend                    : 1;       /**< Pending switch memory BIST status */
+        uint64_t adr                     : 1;       /**< Address memory BIST status */
+#else
+        uint64_t adr                     : 1;
+        uint64_t pend                    : 1;
+        uint64_t nbr0                    : 1;
+        uint64_t nbr1                    : 1;
+        uint64_t fidx                    : 1;
+        uint64_t index                   : 1;
+        uint64_t nbt0                    : 1;
+        uint64_t nbt1                    : 1;
+        uint64_t cam                     : 1;
+        uint64_t reserved_9_15           : 7;
+        uint64_t pp                      : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn30xx;
+    struct cvmx_pow_bist_stat_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t pp                      : 2;       /**< Physical PP BIST status */
+        uint64_t reserved_9_15           : 7;
+        uint64_t cam                     : 1;       /**< POW CAM BIST status */
+        uint64_t nbt1                    : 1;       /**< NCB transmitter memory 1 BIST status */
+        uint64_t nbt0                    : 1;       /**< NCB transmitter memory 0 BIST status */
+        uint64_t index                   : 1;       /**< Index memory BIST status */
+        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
+        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
+        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
+        uint64_t pend                    : 1;       /**< Pending switch memory BIST status */
+        uint64_t adr                     : 1;       /**< Address memory BIST status */
+#else
+        uint64_t adr                     : 1;
+        uint64_t pend                    : 1;
+        uint64_t nbr0                    : 1;
+        uint64_t nbr1                    : 1;
+        uint64_t fidx                    : 1;
+        uint64_t index                   : 1;
+        uint64_t nbt0                    : 1;
+        uint64_t nbt1                    : 1;
+        uint64_t cam                     : 1;
+        uint64_t reserved_9_15           : 7;
+        uint64_t pp                      : 2;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn31xx;
+    struct cvmx_pow_bist_stat_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t pp                      : 16;      /**< Physical PP BIST status */
+        uint64_t reserved_10_15          : 6;
+        uint64_t cam                     : 1;       /**< POW CAM BIST status */
+        uint64_t nbt                     : 1;       /**< NCB transmitter memory BIST status */
+        uint64_t index                   : 1;       /**< Index memory BIST status */
+        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
+        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
+        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
+        uint64_t pend1                   : 1;       /**< Pending switch memory 1 BIST status */
+        uint64_t pend0                   : 1;       /**< Pending switch memory 0 BIST status */
+        uint64_t adr1                    : 1;       /**< Address memory 1 BIST status */
+        uint64_t adr0                    : 1;       /**< Address memory 0 BIST status */
+#else
+        uint64_t adr0                    : 1;
+        uint64_t adr1                    : 1;
+        uint64_t pend0                   : 1;
+        uint64_t pend1                   : 1;
+        uint64_t nbr0                    : 1;
+        uint64_t nbr1                    : 1;
+        uint64_t fidx                    : 1;
+        uint64_t index                   : 1;
+        uint64_t nbt                     : 1;
+        uint64_t cam                     : 1;
+        uint64_t reserved_10_15          : 6;
+        uint64_t pp                      : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } cn38xx;
+    struct cvmx_pow_bist_stat_cn38xx     cn38xxp2;
+    struct cvmx_pow_bist_stat_cn31xx     cn50xx;
+    struct cvmx_pow_bist_stat_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t pp                      : 4;       /**< Physical PP BIST status */
+        uint64_t reserved_9_15           : 7;
+        uint64_t cam                     : 1;       /**< POW CAM BIST status */
+        uint64_t nbt1                    : 1;       /**< NCB transmitter memory 1 BIST status */
+        uint64_t nbt0                    : 1;       /**< NCB transmitter memory 0 BIST status */
+        uint64_t index                   : 1;       /**< Index memory BIST status */
+        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
+        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
+        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
+        uint64_t pend                    : 1;       /**< Pending switch memory BIST status */
+        uint64_t adr                     : 1;       /**< Address memory BIST status */
+#else
+        uint64_t adr                     : 1;
+        uint64_t pend                    : 1;
+        uint64_t nbr0                    : 1;
+        uint64_t nbr1                    : 1;
+        uint64_t fidx                    : 1;
+        uint64_t index                   : 1;
+        uint64_t nbt0                    : 1;
+        uint64_t nbt1                    : 1;
+        uint64_t cam                     : 1;
+        uint64_t reserved_9_15           : 7;
+        uint64_t pp                      : 4;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn52xx;
+    struct cvmx_pow_bist_stat_cn52xx     cn52xxp1;
+    struct cvmx_pow_bist_stat_cn56xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t pp                      : 12;      /**< Physical PP BIST status */
+        uint64_t reserved_10_15          : 6;
+        uint64_t cam                     : 1;       /**< POW CAM BIST status */
+        uint64_t nbt                     : 1;       /**< NCB transmitter memory BIST status */
+        uint64_t index                   : 1;       /**< Index memory BIST status */
+        uint64_t fidx                    : 1;       /**< Forward index memory BIST status */
+        uint64_t nbr1                    : 1;       /**< NCB receiver memory 1 BIST status */
+        uint64_t nbr0                    : 1;       /**< NCB receiver memory 0 BIST status */
+        uint64_t pend1                   : 1;       /**< Pending switch memory 1 BIST status */
+        uint64_t pend0                   : 1;       /**< Pending switch memory 0 BIST status */
+        uint64_t adr1                    : 1;       /**< Address memory 1 BIST status */
+        uint64_t adr0                    : 1;       /**< Address memory 0 BIST status */
+#else
+        uint64_t adr0                    : 1;
+        uint64_t adr1                    : 1;
+        uint64_t pend0                   : 1;
+        uint64_t pend1                   : 1;
+        uint64_t nbr0                    : 1;
+        uint64_t nbr1                    : 1;
+        uint64_t fidx                    : 1;
+        uint64_t index                   : 1;
+        uint64_t nbt                     : 1;
+        uint64_t cam                     : 1;
+        uint64_t reserved_10_15          : 6;
+        uint64_t pp                      : 12;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn56xx;
+    struct cvmx_pow_bist_stat_cn56xx     cn56xxp1;
+    struct cvmx_pow_bist_stat_cn38xx     cn58xx;
+    struct cvmx_pow_bist_stat_cn38xx     cn58xxp1;
+} cvmx_pow_bist_stat_t;
+
+
+/**
+ * cvmx_pow_ds_pc
+ *
+ * POW_DS_PC = POW De-Schedule Performance Counter
+ * 
+ * Counts the number of de-schedule requests.  Write to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_ds_pc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ds_pc                   : 32;      /**< De-schedule performance counter */
+#else
+        uint64_t ds_pc                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_ds_pc_s              cn30xx;
+    struct cvmx_pow_ds_pc_s              cn31xx;
+    struct cvmx_pow_ds_pc_s              cn38xx;
+    struct cvmx_pow_ds_pc_s              cn38xxp2;
+    struct cvmx_pow_ds_pc_s              cn50xx;
+    struct cvmx_pow_ds_pc_s              cn52xx;
+    struct cvmx_pow_ds_pc_s              cn52xxp1;
+    struct cvmx_pow_ds_pc_s              cn56xx;
+    struct cvmx_pow_ds_pc_s              cn56xxp1;
+    struct cvmx_pow_ds_pc_s              cn58xx;
+    struct cvmx_pow_ds_pc_s              cn58xxp1;
+} cvmx_pow_ds_pc_t;
+
+
+/**
+ * cvmx_pow_ecc_err
+ *
+ * POW_ECC_ERR = POW ECC Error Register
+ * 
+ * Contains the single and double error bits and the corresponding interrupt enables for the ECC-
+ * protected POW index memory.  Also contains the syndrome value in the event of an ECC error.
+ * 
+ * Also contains the remote pointer error bit and interrupt enable.  RPE is set when the POW detected
+ * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail pointer
+ * for the L2/DRAM input queue did not match the last entry on the the list).   This is caused by
+ * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad work
+ * queue entries.
+ * 
+ * This register also contains the illegal operation error bits and the corresponding interrupt
+ * enables as follows:
+ * 
+ *  <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state
+ *  <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state
+ *  <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC
+ *  <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL
+ *  <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL
+ *  <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending
+ *  <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending
+ *  <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending
+ *  <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending
+ *  <9> Received illegal opcode
+ * <10> Received ADD_WORK with tag specified as NULL_NULL
+ * <11> Received DBG load from PP with DBG load pending
+ * <12> Received CSR load from PP with CSR load pending
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_ecc_err_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_45_63          : 19;
+        uint64_t iop_ie                  : 13;      /**< Illegal operation interrupt enables */
+        uint64_t reserved_29_31          : 3;
+        uint64_t iop                     : 13;      /**< Illegal operation errors */
+        uint64_t reserved_14_15          : 2;
+        uint64_t rpe_ie                  : 1;       /**< Remote pointer error interrupt enable */
+        uint64_t rpe                     : 1;       /**< Remote pointer error */
+        uint64_t reserved_9_11           : 3;
+        uint64_t syn                     : 5;       /**< Syndrome value (only valid when DBE or SBE is set) */
+        uint64_t dbe_ie                  : 1;       /**< Double bit error interrupt enable */
+        uint64_t sbe_ie                  : 1;       /**< Single bit error interrupt enable */
+        uint64_t dbe                     : 1;       /**< Double bit error */
+        uint64_t sbe                     : 1;       /**< Single bit error */
+#else
+        uint64_t sbe                     : 1;
+        uint64_t dbe                     : 1;
+        uint64_t sbe_ie                  : 1;
+        uint64_t dbe_ie                  : 1;
+        uint64_t syn                     : 5;
+        uint64_t reserved_9_11           : 3;
+        uint64_t rpe                     : 1;
+        uint64_t rpe_ie                  : 1;
+        uint64_t reserved_14_15          : 2;
+        uint64_t iop                     : 13;
+        uint64_t reserved_29_31          : 3;
+        uint64_t iop_ie                  : 13;
+        uint64_t reserved_45_63          : 19;
+#endif
+    } s;
+    struct cvmx_pow_ecc_err_s            cn30xx;
+    struct cvmx_pow_ecc_err_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t rpe_ie                  : 1;       /**< Remote pointer error interrupt enable */
+        uint64_t rpe                     : 1;       /**< Remote pointer error */
+        uint64_t reserved_9_11           : 3;
+        uint64_t syn                     : 5;       /**< Syndrome value (only valid when DBE or SBE is set) */
+        uint64_t dbe_ie                  : 1;       /**< Double bit error interrupt enable */
+        uint64_t sbe_ie                  : 1;       /**< Single bit error interrupt enable */
+        uint64_t dbe                     : 1;       /**< Double bit error */
+        uint64_t sbe                     : 1;       /**< Single bit error */
+#else
+        uint64_t sbe                     : 1;
+        uint64_t dbe                     : 1;
+        uint64_t sbe_ie                  : 1;
+        uint64_t dbe_ie                  : 1;
+        uint64_t syn                     : 5;
+        uint64_t reserved_9_11           : 3;
+        uint64_t rpe                     : 1;
+        uint64_t rpe_ie                  : 1;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } cn31xx;
+    struct cvmx_pow_ecc_err_s            cn38xx;
+    struct cvmx_pow_ecc_err_cn31xx       cn38xxp2;
+    struct cvmx_pow_ecc_err_s            cn50xx;
+    struct cvmx_pow_ecc_err_s            cn52xx;
+    struct cvmx_pow_ecc_err_s            cn52xxp1;
+    struct cvmx_pow_ecc_err_s            cn56xx;
+    struct cvmx_pow_ecc_err_s            cn56xxp1;
+    struct cvmx_pow_ecc_err_s            cn58xx;
+    struct cvmx_pow_ecc_err_s            cn58xxp1;
+} cvmx_pow_ecc_err_t;
+
+
+/**
+ * cvmx_pow_int_ctl
+ *
+ * POW_INT_CTL = POW Internal Control Register
+ * 
+ * Contains POW internal control values (for internal use, not typically for customer use):
+ * 
+ * PFR_DIS = Disable high-performance pre-fetch reset mode.
+ * 
+ * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less
+ * than or equal to this value.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_int_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t pfr_dis                 : 1;       /**< High-perf pre-fetch reset mode disable */
+        uint64_t nbr_thr                 : 5;       /**< NBR busy threshold */
+#else
+        uint64_t nbr_thr                 : 5;
+        uint64_t pfr_dis                 : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_pow_int_ctl_s            cn30xx;
+    struct cvmx_pow_int_ctl_s            cn31xx;
+    struct cvmx_pow_int_ctl_s            cn38xx;
+    struct cvmx_pow_int_ctl_s            cn38xxp2;
+    struct cvmx_pow_int_ctl_s            cn50xx;
+    struct cvmx_pow_int_ctl_s            cn52xx;
+    struct cvmx_pow_int_ctl_s            cn52xxp1;
+    struct cvmx_pow_int_ctl_s            cn56xx;
+    struct cvmx_pow_int_ctl_s            cn56xxp1;
+    struct cvmx_pow_int_ctl_s            cn58xx;
+    struct cvmx_pow_int_ctl_s            cn58xxp1;
+} cvmx_pow_int_ctl_t;
+
+
+/**
+ * cvmx_pow_iq_cnt#
+ *
+ * POW_IQ_CNTX = POW Input Queue Count Register (1 per QOS level)
+ * 
+ * Contains a read-only count of the number of work queue entries for each QOS level.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_iq_cntx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iq_cnt                  : 32;      /**< Input queue count for QOS level X */
+#else
+        uint64_t iq_cnt                  : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_iq_cntx_s            cn30xx;
+    struct cvmx_pow_iq_cntx_s            cn31xx;
+    struct cvmx_pow_iq_cntx_s            cn38xx;
+    struct cvmx_pow_iq_cntx_s            cn38xxp2;
+    struct cvmx_pow_iq_cntx_s            cn50xx;
+    struct cvmx_pow_iq_cntx_s            cn52xx;
+    struct cvmx_pow_iq_cntx_s            cn52xxp1;
+    struct cvmx_pow_iq_cntx_s            cn56xx;
+    struct cvmx_pow_iq_cntx_s            cn56xxp1;
+    struct cvmx_pow_iq_cntx_s            cn58xx;
+    struct cvmx_pow_iq_cntx_s            cn58xxp1;
+} cvmx_pow_iq_cntx_t;
+
+
+/**
+ * cvmx_pow_iq_com_cnt
+ *
+ * POW_IQ_COM_CNT = POW Input Queue Combined Count Register
+ * 
+ * Contains a read-only count of the total number of work queue entries in all QOS levels.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_iq_com_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iq_cnt                  : 32;      /**< Input queue combined count */
+#else
+        uint64_t iq_cnt                  : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_iq_com_cnt_s         cn30xx;
+    struct cvmx_pow_iq_com_cnt_s         cn31xx;
+    struct cvmx_pow_iq_com_cnt_s         cn38xx;
+    struct cvmx_pow_iq_com_cnt_s         cn38xxp2;
+    struct cvmx_pow_iq_com_cnt_s         cn50xx;
+    struct cvmx_pow_iq_com_cnt_s         cn52xx;
+    struct cvmx_pow_iq_com_cnt_s         cn52xxp1;
+    struct cvmx_pow_iq_com_cnt_s         cn56xx;
+    struct cvmx_pow_iq_com_cnt_s         cn56xxp1;
+    struct cvmx_pow_iq_com_cnt_s         cn58xx;
+    struct cvmx_pow_iq_com_cnt_s         cn58xxp1;
+} cvmx_pow_iq_com_cnt_t;
+
+
+/**
+ * cvmx_pow_iq_int
+ *
+ * POW_IQ_INT = POW Input Queue Interrupt Register
+ * 
+ * Contains the bits (1 per QOS level) that can trigger the input queue interrupt.  An IQ_INT bit
+ * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_iq_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t iq_int                  : 8;       /**< Input queue interrupt bits */
+#else
+        uint64_t iq_int                  : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pow_iq_int_s             cn52xx;
+    struct cvmx_pow_iq_int_s             cn52xxp1;
+    struct cvmx_pow_iq_int_s             cn56xx;
+    struct cvmx_pow_iq_int_s             cn56xxp1;
+} cvmx_pow_iq_int_t;
+
+
+/**
+ * cvmx_pow_iq_int_en
+ *
+ * POW_IQ_INT_EN = POW Input Queue Interrupt Enable Register
+ * 
+ * Contains the bits (1 per QOS level) that enable the input queue interrupt.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_iq_int_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t int_en                  : 8;       /**< Input queue interrupt enable bits */
+#else
+        uint64_t int_en                  : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pow_iq_int_en_s          cn52xx;
+    struct cvmx_pow_iq_int_en_s          cn52xxp1;
+    struct cvmx_pow_iq_int_en_s          cn56xx;
+    struct cvmx_pow_iq_int_en_s          cn56xxp1;
+} cvmx_pow_iq_int_en_t;
+
+
+/**
+ * cvmx_pow_iq_thr#
+ *
+ * POW_IQ_THRX = POW Input Queue Threshold Register (1 per QOS level)
+ * 
+ * Threshold value for triggering input queue interrupts.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_iq_thrx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iq_thr                  : 32;      /**< Input queue threshold for QOS level X */
+#else
+        uint64_t iq_thr                  : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_iq_thrx_s            cn52xx;
+    struct cvmx_pow_iq_thrx_s            cn52xxp1;
+    struct cvmx_pow_iq_thrx_s            cn56xx;
+    struct cvmx_pow_iq_thrx_s            cn56xxp1;
+} cvmx_pow_iq_thrx_t;
+
+
+/**
+ * cvmx_pow_nos_cnt
+ *
+ * POW_NOS_CNT = POW No-schedule Count Register
+ * 
+ * Contains the number of work queue entries on the no-schedule list.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_nos_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t nos_cnt                 : 12;      /**< # of work queue entries on the no-schedule list */
+#else
+        uint64_t nos_cnt                 : 12;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_pow_nos_cnt_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t nos_cnt                 : 7;       /**< # of work queue entries on the no-schedule list */
+#else
+        uint64_t nos_cnt                 : 7;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } cn30xx;
+    struct cvmx_pow_nos_cnt_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t nos_cnt                 : 9;       /**< # of work queue entries on the no-schedule list */
+#else
+        uint64_t nos_cnt                 : 9;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } cn31xx;
+    struct cvmx_pow_nos_cnt_s            cn38xx;
+    struct cvmx_pow_nos_cnt_s            cn38xxp2;
+    struct cvmx_pow_nos_cnt_cn31xx       cn50xx;
+    struct cvmx_pow_nos_cnt_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t nos_cnt                 : 10;      /**< # of work queue entries on the no-schedule list */
+#else
+        uint64_t nos_cnt                 : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } cn52xx;
+    struct cvmx_pow_nos_cnt_cn52xx       cn52xxp1;
+    struct cvmx_pow_nos_cnt_s            cn56xx;
+    struct cvmx_pow_nos_cnt_s            cn56xxp1;
+    struct cvmx_pow_nos_cnt_s            cn58xx;
+    struct cvmx_pow_nos_cnt_s            cn58xxp1;
+} cvmx_pow_nos_cnt_t;
+
+
+/**
+ * cvmx_pow_nw_tim
+ *
+ * POW_NW_TIM = POW New Work Timer Period Register
+ * 
+ * Sets the minimum period for a new work request timeout.  Period is specified in n-1 notation
+ * where the increment value is 1024 clock cycles.  Thus, a value of 0x0 in this register translates
+ * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc...  Note: the
+ * maximum period for a new work request timeout is 2 times the minimum period.  Note: the new work
+ * request timeout counter is reset when this register is written.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_nw_tim_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_10_63          : 54;
+        uint64_t nw_tim                  : 10;      /**< New work timer period */
+#else
+        uint64_t nw_tim                  : 10;
+        uint64_t reserved_10_63          : 54;
+#endif
+    } s;
+    struct cvmx_pow_nw_tim_s             cn30xx;
+    struct cvmx_pow_nw_tim_s             cn31xx;
+    struct cvmx_pow_nw_tim_s             cn38xx;
+    struct cvmx_pow_nw_tim_s             cn38xxp2;
+    struct cvmx_pow_nw_tim_s             cn50xx;
+    struct cvmx_pow_nw_tim_s             cn52xx;
+    struct cvmx_pow_nw_tim_s             cn52xxp1;
+    struct cvmx_pow_nw_tim_s             cn56xx;
+    struct cvmx_pow_nw_tim_s             cn56xxp1;
+    struct cvmx_pow_nw_tim_s             cn58xx;
+    struct cvmx_pow_nw_tim_s             cn58xxp1;
+} cvmx_pow_nw_tim_t;
+
+
+/**
+ * cvmx_pow_pf_rst_msk
+ *
+ * POW_PF_RST_MSK = POW Prefetch Reset Mask
+ * 
+ * Resets the work prefetch engine when work is stored in an internal buffer (either when the add
+ * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level
+ * (1 bit per QOS level).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_pf_rst_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t rst_msk                 : 8;       /**< Prefetch engine reset mask */
+#else
+        uint64_t rst_msk                 : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_pow_pf_rst_msk_s         cn50xx;
+    struct cvmx_pow_pf_rst_msk_s         cn52xx;
+    struct cvmx_pow_pf_rst_msk_s         cn52xxp1;
+    struct cvmx_pow_pf_rst_msk_s         cn56xx;
+    struct cvmx_pow_pf_rst_msk_s         cn56xxp1;
+    struct cvmx_pow_pf_rst_msk_s         cn58xx;
+    struct cvmx_pow_pf_rst_msk_s         cn58xxp1;
+} cvmx_pow_pf_rst_msk_t;
+
+
+/**
+ * cvmx_pow_pp_grp_msk#
+ *
+ * POW_PP_GRP_MSKX = POW PP Group Mask Register (1 per PP)
+ * 
+ * Selects which group(s) a PP belongs to.  A '1' in any bit position sets the PP's membership in
+ * the corresponding group.  A value of 0x0 will prevent the PP from receiving new work.  Note:
+ * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order to
+ * maximize POW performance.
+ * 
+ * Also contains the QOS level priorities for each PP.  0x0 is highest priority, and 0x7 the lowest.
+ * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level.
+ * Priority values 0x8 through 0xe are reserved and should not be used.  For a given PP, priorities
+ * should begin at 0x0 and remain contiguous throughout the range.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_pp_grp_mskx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t qos7_pri                : 4;       /**< PPX priority for QOS level 7 */
+        uint64_t qos6_pri                : 4;       /**< PPX priority for QOS level 6 */
+        uint64_t qos5_pri                : 4;       /**< PPX priority for QOS level 5 */
+        uint64_t qos4_pri                : 4;       /**< PPX priority for QOS level 4 */
+        uint64_t qos3_pri                : 4;       /**< PPX priority for QOS level 3 */
+        uint64_t qos2_pri                : 4;       /**< PPX priority for QOS level 2 */
+        uint64_t qos1_pri                : 4;       /**< PPX priority for QOS level 1 */
+        uint64_t qos0_pri                : 4;       /**< PPX priority for QOS level 0 */
+        uint64_t grp_msk                 : 16;      /**< PPX group mask */
+#else
+        uint64_t grp_msk                 : 16;
+        uint64_t qos0_pri                : 4;
+        uint64_t qos1_pri                : 4;
+        uint64_t qos2_pri                : 4;
+        uint64_t qos3_pri                : 4;
+        uint64_t qos4_pri                : 4;
+        uint64_t qos5_pri                : 4;
+        uint64_t qos6_pri                : 4;
+        uint64_t qos7_pri                : 4;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_pow_pp_grp_mskx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t grp_msk                 : 16;      /**< PPX group mask */
+#else
+        uint64_t grp_msk                 : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn30xx;
+    struct cvmx_pow_pp_grp_mskx_cn30xx   cn31xx;
+    struct cvmx_pow_pp_grp_mskx_cn30xx   cn38xx;
+    struct cvmx_pow_pp_grp_mskx_cn30xx   cn38xxp2;
+    struct cvmx_pow_pp_grp_mskx_s        cn50xx;
+    struct cvmx_pow_pp_grp_mskx_s        cn52xx;
+    struct cvmx_pow_pp_grp_mskx_s        cn52xxp1;
+    struct cvmx_pow_pp_grp_mskx_s        cn56xx;
+    struct cvmx_pow_pp_grp_mskx_s        cn56xxp1;
+    struct cvmx_pow_pp_grp_mskx_s        cn58xx;
+    struct cvmx_pow_pp_grp_mskx_s        cn58xxp1;
+} cvmx_pow_pp_grp_mskx_t;
+
+
+/**
+ * cvmx_pow_qos_rnd#
+ *
+ * POW_QOS_RNDX = POW QOS Issue Round Register (4 rounds per register x 8 registers = 32 rounds)
+ * 
+ * Contains the round definitions for issuing new work.  Each round consists of 8 bits with each bit
+ * corresponding to a QOS level.  There are 4 rounds contained in each register for a total of 32
+ * rounds.  The issue logic traverses through the rounds sequentially (lowest round to highest round)
+ * in an attempt to find new work for each PP.  Within each round, the issue logic traverses through
+ * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a clear
+ * bit in the round mask.  Note: setting a QOS level to all zeroes in all issue round registers will
+ * prevent work from being issued from that QOS level.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_qos_rndx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t rnd_p3                  : 8;       /**< Round mask for round Xx4+3 */
+        uint64_t rnd_p2                  : 8;       /**< Round mask for round Xx4+2 */
+        uint64_t rnd_p1                  : 8;       /**< Round mask for round Xx4+1 */
+        uint64_t rnd                     : 8;       /**< Round mask for round Xx4 */
+#else
+        uint64_t rnd                     : 8;
+        uint64_t rnd_p1                  : 8;
+        uint64_t rnd_p2                  : 8;
+        uint64_t rnd_p3                  : 8;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_qos_rndx_s           cn30xx;
+    struct cvmx_pow_qos_rndx_s           cn31xx;
+    struct cvmx_pow_qos_rndx_s           cn38xx;
+    struct cvmx_pow_qos_rndx_s           cn38xxp2;
+    struct cvmx_pow_qos_rndx_s           cn50xx;
+    struct cvmx_pow_qos_rndx_s           cn52xx;
+    struct cvmx_pow_qos_rndx_s           cn52xxp1;
+    struct cvmx_pow_qos_rndx_s           cn56xx;
+    struct cvmx_pow_qos_rndx_s           cn56xxp1;
+    struct cvmx_pow_qos_rndx_s           cn58xx;
+    struct cvmx_pow_qos_rndx_s           cn58xxp1;
+} cvmx_pow_qos_rndx_t;
+
+
+/**
+ * cvmx_pow_qos_thr#
+ *
+ * POW_QOS_THRX = POW QOS Threshold Register (1 per QOS level)
+ * 
+ * Contains the thresholds for allocating POW internal storage buffers.  If the number of remaining
+ * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers for
+ * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries
+ * will be buffered externally rather than internally.  This register also contains a read-only count
+ * of the current number of free buffers (FREE_CNT), the number of internal buffers currently
+ * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list
+ * (DES_CNT) (which is not the same as the total number of de-scheduled buffers).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_qos_thrx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t des_cnt                 : 12;      /**< # of buffers on de-schedule list */
+        uint64_t buf_cnt                 : 12;      /**< # of internal buffers allocated to QOS level X */
+        uint64_t free_cnt                : 12;      /**< # of total free buffers */
+        uint64_t reserved_23_23          : 1;
+        uint64_t max_thr                 : 11;      /**< Max threshold for QOS level X */
+        uint64_t reserved_11_11          : 1;
+        uint64_t min_thr                 : 11;      /**< Min threshold for QOS level X */
+#else
+        uint64_t min_thr                 : 11;
+        uint64_t reserved_11_11          : 1;
+        uint64_t max_thr                 : 11;
+        uint64_t reserved_23_23          : 1;
+        uint64_t free_cnt                : 12;
+        uint64_t buf_cnt                 : 12;
+        uint64_t des_cnt                 : 12;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } s;
+    struct cvmx_pow_qos_thrx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_55_63          : 9;
+        uint64_t des_cnt                 : 7;       /**< # of buffers on de-schedule list */
+        uint64_t reserved_43_47          : 5;
+        uint64_t buf_cnt                 : 7;       /**< # of internal buffers allocated to QOS level X */
+        uint64_t reserved_31_35          : 5;
+        uint64_t free_cnt                : 7;       /**< # of total free buffers */
+        uint64_t reserved_18_23          : 6;
+        uint64_t max_thr                 : 6;       /**< Max threshold for QOS level X */
+        uint64_t reserved_6_11           : 6;
+        uint64_t min_thr                 : 6;       /**< Min threshold for QOS level X */
+#else
+        uint64_t min_thr                 : 6;
+        uint64_t reserved_6_11           : 6;
+        uint64_t max_thr                 : 6;
+        uint64_t reserved_18_23          : 6;
+        uint64_t free_cnt                : 7;
+        uint64_t reserved_31_35          : 5;
+        uint64_t buf_cnt                 : 7;
+        uint64_t reserved_43_47          : 5;
+        uint64_t des_cnt                 : 7;
+        uint64_t reserved_55_63          : 9;
+#endif
+    } cn30xx;
+    struct cvmx_pow_qos_thrx_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_57_63          : 7;
+        uint64_t des_cnt                 : 9;       /**< # of buffers on de-schedule list */
+        uint64_t reserved_45_47          : 3;
+        uint64_t buf_cnt                 : 9;       /**< # of internal buffers allocated to QOS level X */
+        uint64_t reserved_33_35          : 3;
+        uint64_t free_cnt                : 9;       /**< # of total free buffers */
+        uint64_t reserved_20_23          : 4;
+        uint64_t max_thr                 : 8;       /**< Max threshold for QOS level X */
+        uint64_t reserved_8_11           : 4;
+        uint64_t min_thr                 : 8;       /**< Min threshold for QOS level X */
+#else
+        uint64_t min_thr                 : 8;
+        uint64_t reserved_8_11           : 4;
+        uint64_t max_thr                 : 8;
+        uint64_t reserved_20_23          : 4;
+        uint64_t free_cnt                : 9;
+        uint64_t reserved_33_35          : 3;
+        uint64_t buf_cnt                 : 9;
+        uint64_t reserved_45_47          : 3;
+        uint64_t des_cnt                 : 9;
+        uint64_t reserved_57_63          : 7;
+#endif
+    } cn31xx;
+    struct cvmx_pow_qos_thrx_s           cn38xx;
+    struct cvmx_pow_qos_thrx_s           cn38xxp2;
+    struct cvmx_pow_qos_thrx_cn31xx      cn50xx;
+    struct cvmx_pow_qos_thrx_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_58_63          : 6;
+        uint64_t des_cnt                 : 10;      /**< # of buffers on de-schedule list */
+        uint64_t reserved_46_47          : 2;
+        uint64_t buf_cnt                 : 10;      /**< # of internal buffers allocated to QOS level X */
+        uint64_t reserved_34_35          : 2;
+        uint64_t free_cnt                : 10;      /**< # of total free buffers */
+        uint64_t reserved_21_23          : 3;
+        uint64_t max_thr                 : 9;       /**< Max threshold for QOS level X */
+        uint64_t reserved_9_11           : 3;
+        uint64_t min_thr                 : 9;       /**< Min threshold for QOS level X */
+#else
+        uint64_t min_thr                 : 9;
+        uint64_t reserved_9_11           : 3;
+        uint64_t max_thr                 : 9;
+        uint64_t reserved_21_23          : 3;
+        uint64_t free_cnt                : 10;
+        uint64_t reserved_34_35          : 2;
+        uint64_t buf_cnt                 : 10;
+        uint64_t reserved_46_47          : 2;
+        uint64_t des_cnt                 : 10;
+        uint64_t reserved_58_63          : 6;
+#endif
+    } cn52xx;
+    struct cvmx_pow_qos_thrx_cn52xx      cn52xxp1;
+    struct cvmx_pow_qos_thrx_s           cn56xx;
+    struct cvmx_pow_qos_thrx_s           cn56xxp1;
+    struct cvmx_pow_qos_thrx_s           cn58xx;
+    struct cvmx_pow_qos_thrx_s           cn58xxp1;
+} cvmx_pow_qos_thrx_t;
+
+
+/**
+ * cvmx_pow_ts_pc
+ *
+ * POW_TS_PC = POW Tag Switch Performance Counter
+ * 
+ * Counts the number of tag switch requests.  Write to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_ts_pc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ts_pc                   : 32;      /**< Tag switch performance counter */
+#else
+        uint64_t ts_pc                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_ts_pc_s              cn30xx;
+    struct cvmx_pow_ts_pc_s              cn31xx;
+    struct cvmx_pow_ts_pc_s              cn38xx;
+    struct cvmx_pow_ts_pc_s              cn38xxp2;
+    struct cvmx_pow_ts_pc_s              cn50xx;
+    struct cvmx_pow_ts_pc_s              cn52xx;
+    struct cvmx_pow_ts_pc_s              cn52xxp1;
+    struct cvmx_pow_ts_pc_s              cn56xx;
+    struct cvmx_pow_ts_pc_s              cn56xxp1;
+    struct cvmx_pow_ts_pc_s              cn58xx;
+    struct cvmx_pow_ts_pc_s              cn58xxp1;
+} cvmx_pow_ts_pc_t;
+
+
+/**
+ * cvmx_pow_wa_com_pc
+ *
+ * POW_WA_COM_PC = POW Work Add Combined Performance Counter
+ * 
+ * Counts the number of add new work requests for all QOS levels.  Write to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_wa_com_pc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t wa_pc                   : 32;      /**< Work add combined performance counter */
+#else
+        uint64_t wa_pc                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_wa_com_pc_s          cn30xx;
+    struct cvmx_pow_wa_com_pc_s          cn31xx;
+    struct cvmx_pow_wa_com_pc_s          cn38xx;
+    struct cvmx_pow_wa_com_pc_s          cn38xxp2;
+    struct cvmx_pow_wa_com_pc_s          cn50xx;
+    struct cvmx_pow_wa_com_pc_s          cn52xx;
+    struct cvmx_pow_wa_com_pc_s          cn52xxp1;
+    struct cvmx_pow_wa_com_pc_s          cn56xx;
+    struct cvmx_pow_wa_com_pc_s          cn56xxp1;
+    struct cvmx_pow_wa_com_pc_s          cn58xx;
+    struct cvmx_pow_wa_com_pc_s          cn58xxp1;
+} cvmx_pow_wa_com_pc_t;
+
+
+/**
+ * cvmx_pow_wa_pc#
+ *
+ * POW_WA_PCX = POW Work Add Performance Counter (1 per QOS level)
+ * 
+ * Counts the number of add new work requests for each QOS level.  Write to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_wa_pcx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t wa_pc                   : 32;      /**< Work add performance counter for QOS level X */
+#else
+        uint64_t wa_pc                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_wa_pcx_s             cn30xx;
+    struct cvmx_pow_wa_pcx_s             cn31xx;
+    struct cvmx_pow_wa_pcx_s             cn38xx;
+    struct cvmx_pow_wa_pcx_s             cn38xxp2;
+    struct cvmx_pow_wa_pcx_s             cn50xx;
+    struct cvmx_pow_wa_pcx_s             cn52xx;
+    struct cvmx_pow_wa_pcx_s             cn52xxp1;
+    struct cvmx_pow_wa_pcx_s             cn56xx;
+    struct cvmx_pow_wa_pcx_s             cn56xxp1;
+    struct cvmx_pow_wa_pcx_s             cn58xx;
+    struct cvmx_pow_wa_pcx_s             cn58xxp1;
+} cvmx_pow_wa_pcx_t;
+
+
+/**
+ * cvmx_pow_wq_int
+ *
+ * POW_WQ_INT = POW Work Queue Interrupt Register
+ * 
+ * Contains the bits (1 per group) that set work queue interrupts and are used to clear these
+ * interrupts.  Also contains the input queue interrupt temporary disable bits (1 per group).  For
+ * more information regarding this register, see the interrupt section.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_wq_int_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t iq_dis                  : 16;      /**< Input queue interrupt temporary disable mask
+                                                         Corresponding WQ_INT<*> bit cannot be set due to
+                                                         IQ_CNT/IQ_THR check when this bit is set.
+                                                         Corresponding IQ_DIS bit is cleared by HW whenever:
+                                                          - POW_WQ_INT_CNT*[IQ_CNT] is zero, or
+                                                          - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
+                                                            counter POW_WQ_INT_PC[PC]==0 */
+        uint64_t wq_int                  : 16;      /**< Work queue interrupt bits
+                                                         Corresponding WQ_INT bit is set by HW whenever:
+                                                          - POW_WQ_INT_CNT*[IQ_CNT] >=
+                                                            POW_WQ_INT_THR*[IQ_THR] and the threshold
+                                                            interrupt is not disabled.
+                                                            IQ_DIS<*>==1 disables the interrupt.
+                                                            POW_WQ_INT_THR*[IQ_THR]==0 disables the int.
+                                                          - POW_WQ_INT_CNT*[DS_CNT] >=
+                                                            POW_WQ_INT_THR*[DS_THR] and the threshold
+                                                            interrupt is not disabled
+                                                            POW_WQ_INT_THR*[DS_THR]==0 disables the int.
+                                                          - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
+                                                            counter POW_WQ_INT_PC[PC]==0 and
+                                                            POW_WQ_INT_THR*[TC_EN]==1 and at least one of:
+                                                            - POW_WQ_INT_CNT*[IQ_CNT] > 0
+                                                            - POW_WQ_INT_CNT*[DS_CNT] > 0 */
+#else
+        uint64_t wq_int                  : 16;
+        uint64_t iq_dis                  : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_wq_int_s             cn30xx;
+    struct cvmx_pow_wq_int_s             cn31xx;
+    struct cvmx_pow_wq_int_s             cn38xx;
+    struct cvmx_pow_wq_int_s             cn38xxp2;
+    struct cvmx_pow_wq_int_s             cn50xx;
+    struct cvmx_pow_wq_int_s             cn52xx;
+    struct cvmx_pow_wq_int_s             cn52xxp1;
+    struct cvmx_pow_wq_int_s             cn56xx;
+    struct cvmx_pow_wq_int_s             cn56xxp1;
+    struct cvmx_pow_wq_int_s             cn58xx;
+    struct cvmx_pow_wq_int_s             cn58xxp1;
+} cvmx_pow_wq_int_t;
+
+
+/**
+ * cvmx_pow_wq_int_cnt#
+ *
+ * POW_WQ_INT_CNTX = POW Work Queue Interrupt Count Register (1 per group)
+ * 
+ * Contains a read-only copy of the counts used to trigger work queue interrupts.  For more
+ * information regarding this register, see the interrupt section.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_wq_int_cntx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+        uint64_t ds_cnt                  : 12;      /**< De-schedule executable count for group X */
+        uint64_t iq_cnt                  : 12;      /**< Input queue executable count for group X */
+#else
+        uint64_t iq_cnt                  : 12;
+        uint64_t ds_cnt                  : 12;
+        uint64_t tc_cnt                  : 4;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } s;
+    struct cvmx_pow_wq_int_cntx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+        uint64_t reserved_19_23          : 5;
+        uint64_t ds_cnt                  : 7;       /**< De-schedule executable count for group X */
+        uint64_t reserved_7_11           : 5;
+        uint64_t iq_cnt                  : 7;       /**< Input queue executable count for group X */
+#else
+        uint64_t iq_cnt                  : 7;
+        uint64_t reserved_7_11           : 5;
+        uint64_t ds_cnt                  : 7;
+        uint64_t reserved_19_23          : 5;
+        uint64_t tc_cnt                  : 4;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn30xx;
+    struct cvmx_pow_wq_int_cntx_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+        uint64_t reserved_21_23          : 3;
+        uint64_t ds_cnt                  : 9;       /**< De-schedule executable count for group X */
+        uint64_t reserved_9_11           : 3;
+        uint64_t iq_cnt                  : 9;       /**< Input queue executable count for group X */
+#else
+        uint64_t iq_cnt                  : 9;
+        uint64_t reserved_9_11           : 3;
+        uint64_t ds_cnt                  : 9;
+        uint64_t reserved_21_23          : 3;
+        uint64_t tc_cnt                  : 4;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn31xx;
+    struct cvmx_pow_wq_int_cntx_s        cn38xx;
+    struct cvmx_pow_wq_int_cntx_s        cn38xxp2;
+    struct cvmx_pow_wq_int_cntx_cn31xx   cn50xx;
+    struct cvmx_pow_wq_int_cntx_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_28_63          : 36;
+        uint64_t tc_cnt                  : 4;       /**< Time counter current value for group X
+                                                         HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
+                                                          - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
+                                                            corresponding POW_WQ_INT_CNT*[DS_CNT]==0
+                                                          - corresponding POW_WQ_INT[WQ_INT<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT[IQ_DIS<*>] is written
+                                                            with a 1 by SW
+                                                          - corresponding POW_WQ_INT_THR* is written by SW
+                                                          - TC_CNT==1 and periodic counter
+                                                            POW_WQ_INT_PC[PC]==0
+                                                         Otherwise, HW decrements TC_CNT whenever the
+                                                         periodic counter POW_WQ_INT_PC[PC]==0.
+                                                         TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
+        uint64_t reserved_22_23          : 2;
+        uint64_t ds_cnt                  : 10;      /**< De-schedule executable count for group X */
+        uint64_t reserved_10_11          : 2;
+        uint64_t iq_cnt                  : 10;      /**< Input queue executable count for group X */
+#else
+        uint64_t iq_cnt                  : 10;
+        uint64_t reserved_10_11          : 2;
+        uint64_t ds_cnt                  : 10;
+        uint64_t reserved_22_23          : 2;
+        uint64_t tc_cnt                  : 4;
+        uint64_t reserved_28_63          : 36;
+#endif
+    } cn52xx;
+    struct cvmx_pow_wq_int_cntx_cn52xx   cn52xxp1;
+    struct cvmx_pow_wq_int_cntx_s        cn56xx;
+    struct cvmx_pow_wq_int_cntx_s        cn56xxp1;
+    struct cvmx_pow_wq_int_cntx_s        cn58xx;
+    struct cvmx_pow_wq_int_cntx_s        cn58xxp1;
+} cvmx_pow_wq_int_cntx_t;
+
+
+/**
+ * cvmx_pow_wq_int_pc
+ *
+ * POW_WQ_INT_PC = POW Work Queue Interrupt Periodic Counter Register
+ * 
+ * Contains the threshold value for the work queue interrupt periodic counter and also a read-only
+ * copy of the periodic counter.  For more information regarding this register, see the interrupt
+ * section.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_wq_int_pc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_60_63          : 4;
+        uint64_t pc                      : 28;      /**< Work queue interrupt periodic counter */
+        uint64_t reserved_28_31          : 4;
+        uint64_t pc_thr                  : 20;      /**< Work queue interrupt periodic counter threshold */
+        uint64_t reserved_0_7            : 8;
+#else
+        uint64_t reserved_0_7            : 8;
+        uint64_t pc_thr                  : 20;
+        uint64_t reserved_28_31          : 4;
+        uint64_t pc                      : 28;
+        uint64_t reserved_60_63          : 4;
+#endif
+    } s;
+    struct cvmx_pow_wq_int_pc_s          cn30xx;
+    struct cvmx_pow_wq_int_pc_s          cn31xx;
+    struct cvmx_pow_wq_int_pc_s          cn38xx;
+    struct cvmx_pow_wq_int_pc_s          cn38xxp2;
+    struct cvmx_pow_wq_int_pc_s          cn50xx;
+    struct cvmx_pow_wq_int_pc_s          cn52xx;
+    struct cvmx_pow_wq_int_pc_s          cn52xxp1;
+    struct cvmx_pow_wq_int_pc_s          cn56xx;
+    struct cvmx_pow_wq_int_pc_s          cn56xxp1;
+    struct cvmx_pow_wq_int_pc_s          cn58xx;
+    struct cvmx_pow_wq_int_pc_s          cn58xxp1;
+} cvmx_pow_wq_int_pc_t;
+
+
+/**
+ * cvmx_pow_wq_int_thr#
+ *
+ * POW_WQ_INT_THRX = POW Work Queue Interrupt Threshold Register (1 per group)
+ * 
+ * Contains the thresholds for enabling and setting work queue interrupts.  For more information
+ * regarding this register, see the interrupt section.
+ * 
+ * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are
+ * therefore not available for incoming work queue entries.  Additionally, any PP that is not in the
+ * NULL_NULL state consumes a buffer.  Thus in a 4 PP system, it is not advisable to set either
+ * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504.  Doing so may prevent the interrupt from
+ * ever triggering.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_wq_int_thrx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+        uint64_t reserved_23_23          : 1;
+        uint64_t ds_thr                  : 11;      /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+        uint64_t reserved_11_11          : 1;
+        uint64_t iq_thr                  : 11;      /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+        uint64_t iq_thr                  : 11;
+        uint64_t reserved_11_11          : 1;
+        uint64_t ds_thr                  : 11;
+        uint64_t reserved_23_23          : 1;
+        uint64_t tc_thr                  : 4;
+        uint64_t tc_en                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } s;
+    struct cvmx_pow_wq_int_thrx_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+        uint64_t reserved_18_23          : 6;
+        uint64_t ds_thr                  : 6;       /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+        uint64_t reserved_6_11           : 6;
+        uint64_t iq_thr                  : 6;       /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+        uint64_t iq_thr                  : 6;
+        uint64_t reserved_6_11           : 6;
+        uint64_t ds_thr                  : 6;
+        uint64_t reserved_18_23          : 6;
+        uint64_t tc_thr                  : 4;
+        uint64_t tc_en                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn30xx;
+    struct cvmx_pow_wq_int_thrx_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+        uint64_t reserved_20_23          : 4;
+        uint64_t ds_thr                  : 8;       /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+        uint64_t reserved_8_11           : 4;
+        uint64_t iq_thr                  : 8;       /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+        uint64_t iq_thr                  : 8;
+        uint64_t reserved_8_11           : 4;
+        uint64_t ds_thr                  : 8;
+        uint64_t reserved_20_23          : 4;
+        uint64_t tc_thr                  : 4;
+        uint64_t tc_en                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn31xx;
+    struct cvmx_pow_wq_int_thrx_s        cn38xx;
+    struct cvmx_pow_wq_int_thrx_s        cn38xxp2;
+    struct cvmx_pow_wq_int_thrx_cn31xx   cn50xx;
+    struct cvmx_pow_wq_int_thrx_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_29_63          : 35;
+        uint64_t tc_en                   : 1;       /**< Time counter interrupt enable for group X
+                                                         TC_EN must be zero when TC_THR==0 */
+        uint64_t tc_thr                  : 4;       /**< Time counter interrupt threshold for group X
+                                                         When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
+        uint64_t reserved_21_23          : 3;
+        uint64_t ds_thr                  : 9;       /**< De-schedule count threshold for group X
+                                                         DS_THR==0 disables the threshold interrupt */
+        uint64_t reserved_9_11           : 3;
+        uint64_t iq_thr                  : 9;       /**< Input queue count threshold for group X
+                                                         IQ_THR==0 disables the threshold interrupt */
+#else
+        uint64_t iq_thr                  : 9;
+        uint64_t reserved_9_11           : 3;
+        uint64_t ds_thr                  : 9;
+        uint64_t reserved_21_23          : 3;
+        uint64_t tc_thr                  : 4;
+        uint64_t tc_en                   : 1;
+        uint64_t reserved_29_63          : 35;
+#endif
+    } cn52xx;
+    struct cvmx_pow_wq_int_thrx_cn52xx   cn52xxp1;
+    struct cvmx_pow_wq_int_thrx_s        cn56xx;
+    struct cvmx_pow_wq_int_thrx_s        cn56xxp1;
+    struct cvmx_pow_wq_int_thrx_s        cn58xx;
+    struct cvmx_pow_wq_int_thrx_s        cn58xxp1;
+} cvmx_pow_wq_int_thrx_t;
+
+
+/**
+ * cvmx_pow_ws_pc#
+ *
+ * POW_WS_PCX = POW Work Schedule Performance Counter (1 per group)
+ * 
+ * Counts the number of work schedules for each group.  Write to clear.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_pow_ws_pcx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t ws_pc                   : 32;      /**< Work schedule performance counter for group X */
+#else
+        uint64_t ws_pc                   : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_pow_ws_pcx_s             cn30xx;
+    struct cvmx_pow_ws_pcx_s             cn31xx;
+    struct cvmx_pow_ws_pcx_s             cn38xx;
+    struct cvmx_pow_ws_pcx_s             cn38xxp2;
+    struct cvmx_pow_ws_pcx_s             cn50xx;
+    struct cvmx_pow_ws_pcx_s             cn52xx;
+    struct cvmx_pow_ws_pcx_s             cn52xxp1;
+    struct cvmx_pow_ws_pcx_s             cn56xx;
+    struct cvmx_pow_ws_pcx_s             cn56xxp1;
+    struct cvmx_pow_ws_pcx_s             cn58xx;
+    struct cvmx_pow_ws_pcx_s             cn58xxp1;
+} cvmx_pow_ws_pcx_t;
+
+
+/**
+ * cvmx_rad_mem_debug0
+ *
+ * Notes:
+ * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_mem_debug0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t iword                   : 64;      /**< IWord */
+#else
+        uint64_t iword                   : 64;
+#endif
+    } s;
+    struct cvmx_rad_mem_debug0_s         cn52xx;
+    struct cvmx_rad_mem_debug0_s         cn52xxp1;
+    struct cvmx_rad_mem_debug0_s         cn56xx;
+    struct cvmx_rad_mem_debug0_s         cn56xxp1;
+} cvmx_rad_mem_debug0_t;
+
+
+/**
+ * cvmx_rad_mem_debug1
+ *
+ * Notes:
+ * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_mem_debug1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t p_dat                   : 64;      /**< P data */
+#else
+        uint64_t p_dat                   : 64;
+#endif
+    } s;
+    struct cvmx_rad_mem_debug1_s         cn52xx;
+    struct cvmx_rad_mem_debug1_s         cn52xxp1;
+    struct cvmx_rad_mem_debug1_s         cn56xx;
+    struct cvmx_rad_mem_debug1_s         cn56xxp1;
+} cvmx_rad_mem_debug1_t;
+
+
+/**
+ * cvmx_rad_mem_debug2
+ *
+ * Notes:
+ * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.  A read of any entry that has not been
+ * previously written is illegal and will result in unpredictable CSR read data.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_mem_debug2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t q_dat                   : 64;      /**< Q data */
+#else
+        uint64_t q_dat                   : 64;
+#endif
+    } s;
+    struct cvmx_rad_mem_debug2_s         cn52xx;
+    struct cvmx_rad_mem_debug2_s         cn52xxp1;
+    struct cvmx_rad_mem_debug2_s         cn56xx;
+    struct cvmx_rad_mem_debug2_s         cn56xxp1;
+} cvmx_rad_mem_debug2_t;
+
+
+/**
+ * cvmx_rad_reg_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_bist_result_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t sta                     : 1;       /**< BiST result of the STA     memories */
+        uint64_t ncb_oub                 : 1;       /**< BiST result of the NCB_OUB memories */
+        uint64_t ncb_inb                 : 2;       /**< BiST result of the NCB_INB memories */
+        uint64_t dat                     : 2;       /**< BiST result of the DAT     memories */
+#else
+        uint64_t dat                     : 2;
+        uint64_t ncb_inb                 : 2;
+        uint64_t ncb_oub                 : 1;
+        uint64_t sta                     : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_rad_reg_bist_result_s    cn52xx;
+    struct cvmx_rad_reg_bist_result_s    cn52xxp1;
+    struct cvmx_rad_reg_bist_result_s    cn56xx;
+    struct cvmx_rad_reg_bist_result_s    cn56xxp1;
+} cvmx_rad_reg_bist_result_t;
+
+
+/**
+ * cvmx_rad_reg_cmd_buf
+ *
+ * Notes:
+ * Sets the command buffer parameters
+ * The size of the command buffer segments is measured in uint64s.  The pool specifies 1 of 8 free
+ * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
+ * pointer each time that the command buffer segment is exhausted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_cmd_buf_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_58_63          : 6;
+        uint64_t dwb                     : 9;       /**< Number of DontWriteBacks */
+        uint64_t pool                    : 3;       /**< Free list used to free command buffer segments */
+        uint64_t size                    : 13;      /**< Number of uint64s per command buffer segment */
+        uint64_t ptr                     : 33;      /**< Initial command buffer pointer[39:7] (128B-aligned) */
+#else
+        uint64_t ptr                     : 33;
+        uint64_t size                    : 13;
+        uint64_t pool                    : 3;
+        uint64_t dwb                     : 9;
+        uint64_t reserved_58_63          : 6;
+#endif
+    } s;
+    struct cvmx_rad_reg_cmd_buf_s        cn52xx;
+    struct cvmx_rad_reg_cmd_buf_s        cn52xxp1;
+    struct cvmx_rad_reg_cmd_buf_s        cn56xx;
+    struct cvmx_rad_reg_cmd_buf_s        cn56xxp1;
+} cvmx_rad_reg_cmd_buf_t;
+
+
+/**
+ * cvmx_rad_reg_ctl
+ *
+ * Notes:
+ * MAX_READ is a throttle to control NCB usage.  Values >8 are illegal.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t max_read                : 4;       /**< Maximum number of outstanding data read commands */
+        uint64_t store_le                : 1;       /**< Force STORE0 byte write address to little endian */
+        uint64_t reset                   : 1;       /**< Reset oneshot pulse (lasts for 4 cycles) */
+#else
+        uint64_t reset                   : 1;
+        uint64_t store_le                : 1;
+        uint64_t max_read                : 4;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_rad_reg_ctl_s            cn52xx;
+    struct cvmx_rad_reg_ctl_s            cn52xxp1;
+    struct cvmx_rad_reg_ctl_s            cn56xx;
+    struct cvmx_rad_reg_ctl_s            cn56xxp1;
+} cvmx_rad_reg_ctl_t;
+
+
+/**
+ * cvmx_rad_reg_debug0
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_57_63          : 7;
+        uint64_t loop                    : 25;      /**< Loop offset */
+        uint64_t reserved_22_31          : 10;
+        uint64_t iridx                   : 6;       /**< IWords read index */
+        uint64_t reserved_14_15          : 2;
+        uint64_t iwidx                   : 6;       /**< IWords write index */
+        uint64_t owordqv                 : 1;       /**< Valid for OWORDQ */
+        uint64_t owordpv                 : 1;       /**< Valid for OWORDP */
+        uint64_t commit                  : 1;       /**< Waiting for write commit */
+        uint64_t state                   : 5;       /**< Main state */
+#else
+        uint64_t state                   : 5;
+        uint64_t commit                  : 1;
+        uint64_t owordpv                 : 1;
+        uint64_t owordqv                 : 1;
+        uint64_t iwidx                   : 6;
+        uint64_t reserved_14_15          : 2;
+        uint64_t iridx                   : 6;
+        uint64_t reserved_22_31          : 10;
+        uint64_t loop                    : 25;
+        uint64_t reserved_57_63          : 7;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug0_s         cn52xx;
+    struct cvmx_rad_reg_debug0_s         cn52xxp1;
+    struct cvmx_rad_reg_debug0_s         cn56xx;
+    struct cvmx_rad_reg_debug0_s         cn56xxp1;
+} cvmx_rad_reg_debug0_t;
+
+
+/**
+ * cvmx_rad_reg_debug1
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t cword                   : 64;      /**< CWord */
+#else
+        uint64_t cword                   : 64;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug1_s         cn52xx;
+    struct cvmx_rad_reg_debug1_s         cn52xxp1;
+    struct cvmx_rad_reg_debug1_s         cn56xx;
+    struct cvmx_rad_reg_debug1_s         cn56xxp1;
+} cvmx_rad_reg_debug1_t;
+
+
+/**
+ * cvmx_rad_reg_debug10
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug10_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t flags                   : 8;       /**< OCTL flags */
+        uint64_t size                    : 16;      /**< OCTL size (bytes) */
+        uint64_t ptr                     : 40;      /**< OCTL pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t flags                   : 8;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug10_s        cn52xx;
+    struct cvmx_rad_reg_debug10_s        cn52xxp1;
+    struct cvmx_rad_reg_debug10_s        cn56xx;
+    struct cvmx_rad_reg_debug10_s        cn56xxp1;
+} cvmx_rad_reg_debug10_t;
+
+
+/**
+ * cvmx_rad_reg_debug11
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug11_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t q                       : 1;       /**< OCTL q flag */
+        uint64_t p                       : 1;       /**< OCTL p flag */
+        uint64_t wc                      : 1;       /**< OCTL write commit flag */
+        uint64_t eod                     : 1;       /**< OCTL eod flag */
+        uint64_t sod                     : 1;       /**< OCTL sod flag */
+        uint64_t index                   : 8;       /**< OCTL index */
+#else
+        uint64_t index                   : 8;
+        uint64_t sod                     : 1;
+        uint64_t eod                     : 1;
+        uint64_t wc                      : 1;
+        uint64_t p                       : 1;
+        uint64_t q                       : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug11_s        cn52xx;
+    struct cvmx_rad_reg_debug11_s        cn52xxp1;
+    struct cvmx_rad_reg_debug11_s        cn56xx;
+    struct cvmx_rad_reg_debug11_s        cn56xxp1;
+} cvmx_rad_reg_debug11_t;
+
+
+/**
+ * cvmx_rad_reg_debug12
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug12_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t asserts                 : 15;      /**< Various assertion checks */
+#else
+        uint64_t asserts                 : 15;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug12_s        cn52xx;
+    struct cvmx_rad_reg_debug12_s        cn52xxp1;
+    struct cvmx_rad_reg_debug12_s        cn56xx;
+    struct cvmx_rad_reg_debug12_s        cn56xxp1;
+} cvmx_rad_reg_debug12_t;
+
+
+/**
+ * cvmx_rad_reg_debug2
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t owordp                  : 64;      /**< OWordP */
+#else
+        uint64_t owordp                  : 64;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug2_s         cn52xx;
+    struct cvmx_rad_reg_debug2_s         cn52xxp1;
+    struct cvmx_rad_reg_debug2_s         cn56xx;
+    struct cvmx_rad_reg_debug2_s         cn56xxp1;
+} cvmx_rad_reg_debug2_t;
+
+
+/**
+ * cvmx_rad_reg_debug3
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t owordq                  : 64;      /**< OWordQ */
+#else
+        uint64_t owordq                  : 64;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug3_s         cn52xx;
+    struct cvmx_rad_reg_debug3_s         cn52xxp1;
+    struct cvmx_rad_reg_debug3_s         cn56xx;
+    struct cvmx_rad_reg_debug3_s         cn56xxp1;
+} cvmx_rad_reg_debug3_t;
+
+
+/**
+ * cvmx_rad_reg_debug4
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t rword                   : 64;      /**< RWord */
+#else
+        uint64_t rword                   : 64;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug4_s         cn52xx;
+    struct cvmx_rad_reg_debug4_s         cn52xxp1;
+    struct cvmx_rad_reg_debug4_s         cn56xx;
+    struct cvmx_rad_reg_debug4_s         cn56xxp1;
+} cvmx_rad_reg_debug4_t;
+
+
+/**
+ * cvmx_rad_reg_debug5
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_53_63          : 11;
+        uint64_t niropc7                 : 3;       /**< NCBI ropc (stage7 grant) */
+        uint64_t nirque7                 : 2;       /**< NCBI rque (stage7 grant) */
+        uint64_t nirval7                 : 5;       /**< NCBI rval (stage7 grant) */
+        uint64_t niropc6                 : 3;       /**< NCBI ropc (stage6 arb) */
+        uint64_t nirque6                 : 2;       /**< NCBI rque (stage6 arb) */
+        uint64_t nirarb6                 : 1;       /**< NCBI rarb (stage6 arb) */
+        uint64_t nirval6                 : 5;       /**< NCBI rval (stage6 arb) */
+        uint64_t niridx1                 : 4;       /**< NCBI ridx1 */
+        uint64_t niwidx1                 : 4;       /**< NCBI widx1 */
+        uint64_t niridx0                 : 4;       /**< NCBI ridx0 */
+        uint64_t niwidx0                 : 4;       /**< NCBI widx0 */
+        uint64_t wccreds                 : 2;       /**< WC credits */
+        uint64_t fpacreds                : 2;       /**< POW credits */
+        uint64_t reserved_10_11          : 2;
+        uint64_t powcreds                : 2;       /**< POW credits */
+        uint64_t n1creds                 : 4;       /**< NCBI1 credits */
+        uint64_t n0creds                 : 4;       /**< NCBI0 credits */
+#else
+        uint64_t n0creds                 : 4;
+        uint64_t n1creds                 : 4;
+        uint64_t powcreds                : 2;
+        uint64_t reserved_10_11          : 2;
+        uint64_t fpacreds                : 2;
+        uint64_t wccreds                 : 2;
+        uint64_t niwidx0                 : 4;
+        uint64_t niridx0                 : 4;
+        uint64_t niwidx1                 : 4;
+        uint64_t niridx1                 : 4;
+        uint64_t nirval6                 : 5;
+        uint64_t nirarb6                 : 1;
+        uint64_t nirque6                 : 2;
+        uint64_t niropc6                 : 3;
+        uint64_t nirval7                 : 5;
+        uint64_t nirque7                 : 2;
+        uint64_t niropc7                 : 3;
+        uint64_t reserved_53_63          : 11;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug5_s         cn52xx;
+    struct cvmx_rad_reg_debug5_s         cn52xxp1;
+    struct cvmx_rad_reg_debug5_s         cn56xx;
+    struct cvmx_rad_reg_debug5_s         cn56xxp1;
+} cvmx_rad_reg_debug5_t;
+
+
+/**
+ * cvmx_rad_reg_debug6
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t cnt                     : 8;       /**< CCTL count[7:0] (bytes) */
+        uint64_t size                    : 16;      /**< CCTL size (bytes) */
+        uint64_t ptr                     : 40;      /**< CCTL pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t cnt                     : 8;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug6_s         cn52xx;
+    struct cvmx_rad_reg_debug6_s         cn52xxp1;
+    struct cvmx_rad_reg_debug6_s         cn56xx;
+    struct cvmx_rad_reg_debug6_s         cn56xxp1;
+} cvmx_rad_reg_debug6_t;
+
+
+/**
+ * cvmx_rad_reg_debug7
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t cnt                     : 15;      /**< CCTL count[22:8] (bytes) */
+#else
+        uint64_t cnt                     : 15;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug7_s         cn52xx;
+    struct cvmx_rad_reg_debug7_s         cn52xxp1;
+    struct cvmx_rad_reg_debug7_s         cn56xx;
+    struct cvmx_rad_reg_debug7_s         cn56xxp1;
+} cvmx_rad_reg_debug7_t;
+
+
+/**
+ * cvmx_rad_reg_debug8
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug8_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t flags                   : 8;       /**< ICTL flags */
+        uint64_t size                    : 16;      /**< ICTL size (bytes) */
+        uint64_t ptr                     : 40;      /**< ICTL pointer */
+#else
+        uint64_t ptr                     : 40;
+        uint64_t size                    : 16;
+        uint64_t flags                   : 8;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug8_s         cn52xx;
+    struct cvmx_rad_reg_debug8_s         cn52xxp1;
+    struct cvmx_rad_reg_debug8_s         cn56xx;
+    struct cvmx_rad_reg_debug8_s         cn56xxp1;
+} cvmx_rad_reg_debug8_t;
+
+
+/**
+ * cvmx_rad_reg_debug9
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_debug9_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t eod                     : 1;       /**< ICTL eod flag */
+        uint64_t ini                     : 1;       /**< ICTL init flag */
+        uint64_t q                       : 1;       /**< ICTL q enable */
+        uint64_t p                       : 1;       /**< ICTL p enable */
+        uint64_t mul                     : 8;       /**< ICTL multiplier */
+        uint64_t index                   : 8;       /**< ICTL index */
+#else
+        uint64_t index                   : 8;
+        uint64_t mul                     : 8;
+        uint64_t p                       : 1;
+        uint64_t q                       : 1;
+        uint64_t ini                     : 1;
+        uint64_t eod                     : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_rad_reg_debug9_s         cn52xx;
+    struct cvmx_rad_reg_debug9_s         cn52xxp1;
+    struct cvmx_rad_reg_debug9_s         cn56xx;
+    struct cvmx_rad_reg_debug9_s         cn56xxp1;
+} cvmx_rad_reg_debug9_t;
+
+
+/**
+ * cvmx_rad_reg_error
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_error_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
+#else
+        uint64_t doorbell                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_rad_reg_error_s          cn52xx;
+    struct cvmx_rad_reg_error_s          cn52xxp1;
+    struct cvmx_rad_reg_error_s          cn56xx;
+    struct cvmx_rad_reg_error_s          cn56xxp1;
+} cvmx_rad_reg_error_t;
+
+
+/**
+ * cvmx_rad_reg_int_mask
+ *
+ * Notes:
+ * When a mask bit is set, the corresponding interrupt is enabled.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_int_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t doorbell                : 1;       /**< Bit mask corresponding to RAD_REG_ERROR[0] above */
+#else
+        uint64_t doorbell                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_rad_reg_int_mask_s       cn52xx;
+    struct cvmx_rad_reg_int_mask_s       cn52xxp1;
+    struct cvmx_rad_reg_int_mask_s       cn56xx;
+    struct cvmx_rad_reg_int_mask_s       cn56xxp1;
+} cvmx_rad_reg_int_mask_t;
+
+
+/**
+ * cvmx_rad_reg_polynomial
+ *
+ * Notes:
+ * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_polynomial_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t coeffs                  : 8;       /**< coefficients of GF(2^8) irreducible polynomial */
+#else
+        uint64_t coeffs                  : 8;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_rad_reg_polynomial_s     cn52xx;
+    struct cvmx_rad_reg_polynomial_s     cn52xxp1;
+    struct cvmx_rad_reg_polynomial_s     cn56xx;
+    struct cvmx_rad_reg_polynomial_s     cn56xxp1;
+} cvmx_rad_reg_polynomial_t;
+
+
+/**
+ * cvmx_rad_reg_read_idx
+ *
+ * Notes:
+ * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
+ * as memories.  The names of these CSRs begin with the prefix "RAD_MEM_".
+ * IDX[15:0] is the read index.  INC[15:0] is an increment that is added to IDX[15:0] after any CSR read.
+ * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
+ * contents of a CSR memory can be read with consecutive CSR read commands.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rad_reg_read_idx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t inc                     : 16;      /**< Increment to add to current index for next index */
+        uint64_t index                   : 16;      /**< Index to use for next memory CSR read */
+#else
+        uint64_t index                   : 16;
+        uint64_t inc                     : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_rad_reg_read_idx_s       cn52xx;
+    struct cvmx_rad_reg_read_idx_s       cn52xxp1;
+    struct cvmx_rad_reg_read_idx_s       cn56xx;
+    struct cvmx_rad_reg_read_idx_s       cn56xxp1;
+} cvmx_rad_reg_read_idx_t;
+
+
+/**
+ * cvmx_rnm_bist_status
+ *
+ * RNM_BIST_STATUS = RNM's BIST Status Register
+ * 
+ * The RNM's Memory Bist Status register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rnm_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t rrc                     : 1;       /**< Status of RRC block bist. */
+        uint64_t mem                     : 1;       /**< Status of MEM block bist. */
+#else
+        uint64_t mem                     : 1;
+        uint64_t rrc                     : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_rnm_bist_status_s        cn30xx;
+    struct cvmx_rnm_bist_status_s        cn31xx;
+    struct cvmx_rnm_bist_status_s        cn38xx;
+    struct cvmx_rnm_bist_status_s        cn38xxp2;
+    struct cvmx_rnm_bist_status_s        cn50xx;
+    struct cvmx_rnm_bist_status_s        cn52xx;
+    struct cvmx_rnm_bist_status_s        cn52xxp1;
+    struct cvmx_rnm_bist_status_s        cn56xx;
+    struct cvmx_rnm_bist_status_s        cn56xxp1;
+    struct cvmx_rnm_bist_status_s        cn58xx;
+    struct cvmx_rnm_bist_status_s        cn58xxp1;
+} cvmx_rnm_bist_status_t;
+
+
+/**
+ * cvmx_rnm_ctl_status
+ *
+ * RNM_CTL_STATUS = RNM's Control/Status Register
+ * 
+ * The RNM's interrupt enable register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_rnm_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t ent_sel                 : 4;       /**< ? */
+        uint64_t exp_ent                 : 1;       /**< Exported entropy enable for random number generator */
+        uint64_t rng_rst                 : 1;       /**< Reset RNG as core reset. */
+        uint64_t rnm_rst                 : 1;       /**< Reset the RNM as core reset except for register
+                                                         logic. */
+        uint64_t rng_en                  : 1;       /**< Enable the output of the RNG. */
+        uint64_t ent_en                  : 1;       /**< Entropy enable for random number generator. */
+#else
+        uint64_t ent_en                  : 1;
+        uint64_t rng_en                  : 1;
+        uint64_t rnm_rst                 : 1;
+        uint64_t rng_rst                 : 1;
+        uint64_t exp_ent                 : 1;
+        uint64_t ent_sel                 : 4;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_rnm_ctl_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t rng_rst                 : 1;       /**< Reset RNG as core reset. */
+        uint64_t rnm_rst                 : 1;       /**< Reset the RNM as core reset except for register
+                                                         logic. */
+        uint64_t rng_en                  : 1;       /**< Enable the output of the RNG. */
+        uint64_t ent_en                  : 1;       /**< Entropy enable for random number generator. */
+#else
+        uint64_t ent_en                  : 1;
+        uint64_t rng_en                  : 1;
+        uint64_t rnm_rst                 : 1;
+        uint64_t rng_rst                 : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } cn30xx;
+    struct cvmx_rnm_ctl_status_cn30xx    cn31xx;
+    struct cvmx_rnm_ctl_status_cn30xx    cn38xx;
+    struct cvmx_rnm_ctl_status_cn30xx    cn38xxp2;
+    struct cvmx_rnm_ctl_status_s         cn50xx;
+    struct cvmx_rnm_ctl_status_s         cn52xx;
+    struct cvmx_rnm_ctl_status_s         cn52xxp1;
+    struct cvmx_rnm_ctl_status_s         cn56xx;
+    struct cvmx_rnm_ctl_status_s         cn56xxp1;
+    struct cvmx_rnm_ctl_status_s         cn58xx;
+    struct cvmx_rnm_ctl_status_s         cn58xxp1;
+} cvmx_rnm_ctl_status_t;
+
+
+/**
+ * cvmx_smi#_clk
+ *
+ * SMI_CLK = Clock Control Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_smix_clk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_25_63          : 39;
+        uint64_t mode                    : 1;       /**< IEEE operating mode
+                                                         0=Clause 22 complient
+                                                         1=Clause 45 complient */
+        uint64_t reserved_21_23          : 3;
+        uint64_t sample_hi               : 5;       /**< When to sample read data (extended bits) */
+        uint64_t sample_mode             : 1;       /**< Read Data sampling mode
+                                                         According to the 802.3 spec, on reads, the STA
+                                                         transitions MDC and the PHY drives MDIO with
+                                                         some delay relative to that edge.  This is edge1.
+                                                         The STA then samples MDIO on the next rising edge
+                                                         of MDC.  This is edge2. Octeon can sample the
+                                                         read data relative to either edge.
+                                                          0=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge2
+                                                          1=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge1 */
+        uint64_t reserved_14_14          : 1;
+        uint64_t clk_idle                : 1;       /**< Do not toggle MDC on idle cycles */
+        uint64_t preamble                : 1;       /**< Send PREAMBLE on SMI transacton */
+        uint64_t sample                  : 4;       /**< When to sample read data
+                                                         (number of eclks after the rising edge of mdc)
+                                                         ( [SAMPLE_HI,SAMPLE] > 1 )
+                                                         ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */
+        uint64_t phase                   : 8;       /**< MDC Clock Phase
+                                                         (number of eclks that make up an mdc phase)
+                                                         (PHASE > 2) */
+#else
+        uint64_t phase                   : 8;
+        uint64_t sample                  : 4;
+        uint64_t preamble                : 1;
+        uint64_t clk_idle                : 1;
+        uint64_t reserved_14_14          : 1;
+        uint64_t sample_mode             : 1;
+        uint64_t sample_hi               : 5;
+        uint64_t reserved_21_23          : 3;
+        uint64_t mode                    : 1;
+        uint64_t reserved_25_63          : 39;
+#endif
+    } s;
+    struct cvmx_smix_clk_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_21_63          : 43;
+        uint64_t sample_hi               : 5;       /**< When to sample read data (extended bits) */
+        uint64_t sample_mode             : 1;       /**< Read Data sampling mode
+                                                         According to the 802.3 spec, on reads, the STA
+                                                         transitions MDC and the PHY drives MDIO with
+                                                         some delay relative to that edge.  This is edge1.
+                                                         The STA then samples MDIO on the next rising edge
+                                                         of MDC.  This is edge2. Octeon can sample the
+                                                         read data relative to either edge.
+                                                          0=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge2
+                                                          1=[SAMPLE_HI,SAMPLE] specify the sample time
+                                                            relative to edge1 */
+        uint64_t reserved_14_14          : 1;
+        uint64_t clk_idle                : 1;       /**< Do not toggle MDC on idle cycles */
+        uint64_t preamble                : 1;       /**< Send PREAMBLE on SMI transacton */
+        uint64_t sample                  : 4;       /**< When to sample read data
+                                                         (number of eclks after the rising edge of mdc)
+                                                         ( [SAMPLE_HI,SAMPLE] > 1 )
+                                                         ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */
+        uint64_t phase                   : 8;       /**< MDC Clock Phase
+                                                         (number of eclks that make up an mdc phase)
+                                                         (PHASE > 2) */
+#else
+        uint64_t phase                   : 8;
+        uint64_t sample                  : 4;
+        uint64_t preamble                : 1;
+        uint64_t clk_idle                : 1;
+        uint64_t reserved_14_14          : 1;
+        uint64_t sample_mode             : 1;
+        uint64_t sample_hi               : 5;
+        uint64_t reserved_21_63          : 43;
+#endif
+    } cn30xx;
+    struct cvmx_smix_clk_cn30xx          cn31xx;
+    struct cvmx_smix_clk_cn30xx          cn38xx;
+    struct cvmx_smix_clk_cn30xx          cn38xxp2;
+    struct cvmx_smix_clk_s               cn50xx;
+    struct cvmx_smix_clk_s               cn52xx;
+    struct cvmx_smix_clk_s               cn52xxp1;
+    struct cvmx_smix_clk_s               cn56xx;
+    struct cvmx_smix_clk_s               cn56xxp1;
+    struct cvmx_smix_clk_cn30xx          cn58xx;
+    struct cvmx_smix_clk_cn30xx          cn58xxp1;
+} cvmx_smix_clk_t;
+
+
+/**
+ * cvmx_smi#_cmd
+ *
+ * SMI_CMD = Force a Read/Write command to the PHY
+ *
+ *
+ * Notes:
+ * Writes to this register will create SMI xactions.  Software will poll on (depending on the xaction type).
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_smix_cmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t phy_op                  : 2;       /**< PHY Opcode
+                                                         0=write
+                                                         1=read */
+        uint64_t reserved_13_15          : 3;
+        uint64_t phy_adr                 : 5;       /**< PHY Address */
+        uint64_t reserved_5_7            : 3;
+        uint64_t reg_adr                 : 5;       /**< PHY Register Offset */
+#else
+        uint64_t reg_adr                 : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t phy_adr                 : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t phy_op                  : 2;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_smix_cmd_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t phy_op                  : 1;       /**< PHY Opcode
+                                                         0=write
+                                                         1=read */
+        uint64_t reserved_13_15          : 3;
+        uint64_t phy_adr                 : 5;       /**< PHY Address */
+        uint64_t reserved_5_7            : 3;
+        uint64_t reg_adr                 : 5;       /**< PHY Register Offset */
+#else
+        uint64_t reg_adr                 : 5;
+        uint64_t reserved_5_7            : 3;
+        uint64_t phy_adr                 : 5;
+        uint64_t reserved_13_15          : 3;
+        uint64_t phy_op                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } cn30xx;
+    struct cvmx_smix_cmd_cn30xx          cn31xx;
+    struct cvmx_smix_cmd_cn30xx          cn38xx;
+    struct cvmx_smix_cmd_cn30xx          cn38xxp2;
+    struct cvmx_smix_cmd_s               cn50xx;
+    struct cvmx_smix_cmd_s               cn52xx;
+    struct cvmx_smix_cmd_s               cn52xxp1;
+    struct cvmx_smix_cmd_s               cn56xx;
+    struct cvmx_smix_cmd_s               cn56xxp1;
+    struct cvmx_smix_cmd_cn30xx          cn58xx;
+    struct cvmx_smix_cmd_cn30xx          cn58xxp1;
+} cvmx_smix_cmd_t;
+
+
+/**
+ * cvmx_smi#_en
+ *
+ * SMI_EN = Enable the SMI interface
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_smix_en_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t en                      : 1;       /**< Interface enable
+                                                         0=SMI Interface is down / no transactions, no MDC
+                                                         1=SMI Interface is up */
+#else
+        uint64_t en                      : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_smix_en_s                cn30xx;
+    struct cvmx_smix_en_s                cn31xx;
+    struct cvmx_smix_en_s                cn38xx;
+    struct cvmx_smix_en_s                cn38xxp2;
+    struct cvmx_smix_en_s                cn50xx;
+    struct cvmx_smix_en_s                cn52xx;
+    struct cvmx_smix_en_s                cn52xxp1;
+    struct cvmx_smix_en_s                cn56xx;
+    struct cvmx_smix_en_s                cn56xxp1;
+    struct cvmx_smix_en_s                cn58xx;
+    struct cvmx_smix_en_s                cn58xxp1;
+} cvmx_smix_en_t;
+
+
+/**
+ * cvmx_smi#_rd_dat
+ *
+ * SMI_RD_DAT = SMI Read Data
+ *
+ *
+ * Notes:
+ * VAL will assert when the read xaction completes.  A read to this register
+ * will clear VAL.  PENDING indicates that an SMI RD transaction is in flight.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_smix_rd_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t pending                 : 1;       /**< Read Xaction Pending */
+        uint64_t val                     : 1;       /**< Read Data Valid */
+        uint64_t dat                     : 16;      /**< Read Data */
+#else
+        uint64_t dat                     : 16;
+        uint64_t val                     : 1;
+        uint64_t pending                 : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_smix_rd_dat_s            cn30xx;
+    struct cvmx_smix_rd_dat_s            cn31xx;
+    struct cvmx_smix_rd_dat_s            cn38xx;
+    struct cvmx_smix_rd_dat_s            cn38xxp2;
+    struct cvmx_smix_rd_dat_s            cn50xx;
+    struct cvmx_smix_rd_dat_s            cn52xx;
+    struct cvmx_smix_rd_dat_s            cn52xxp1;
+    struct cvmx_smix_rd_dat_s            cn56xx;
+    struct cvmx_smix_rd_dat_s            cn56xxp1;
+    struct cvmx_smix_rd_dat_s            cn58xx;
+    struct cvmx_smix_rd_dat_s            cn58xxp1;
+} cvmx_smix_rd_dat_t;
+
+
+/**
+ * cvmx_smi#_wr_dat
+ *
+ * SMI_WR_DAT = SMI Write Data
+ *
+ *
+ * Notes:
+ * VAL will assert when the write xaction completes.  A read to this register
+ * will clear VAL.  PENDING indicates that an SMI WR transaction is in flight.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_smix_wr_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t pending                 : 1;       /**< Write Xaction Pending */
+        uint64_t val                     : 1;       /**< Write Data Valid */
+        uint64_t dat                     : 16;      /**< Write Data */
+#else
+        uint64_t dat                     : 16;
+        uint64_t val                     : 1;
+        uint64_t pending                 : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } s;
+    struct cvmx_smix_wr_dat_s            cn30xx;
+    struct cvmx_smix_wr_dat_s            cn31xx;
+    struct cvmx_smix_wr_dat_s            cn38xx;
+    struct cvmx_smix_wr_dat_s            cn38xxp2;
+    struct cvmx_smix_wr_dat_s            cn50xx;
+    struct cvmx_smix_wr_dat_s            cn52xx;
+    struct cvmx_smix_wr_dat_s            cn52xxp1;
+    struct cvmx_smix_wr_dat_s            cn56xx;
+    struct cvmx_smix_wr_dat_s            cn56xxp1;
+    struct cvmx_smix_wr_dat_s            cn58xx;
+    struct cvmx_smix_wr_dat_s            cn58xxp1;
+} cvmx_smix_wr_dat_t;
+
+
+/**
+ * cvmx_spx#_bckprs_cnt
+ *
+ * Notes:
+ * The back pressure watcher counts the number of cycles in which the spi
+ * receiver receives data once the TPA for a particular port has been
+ * deasserted.  The desired port to watch can be selected with the
+ * SPX_TPA_SEL[PRTSEL] field.
+ * 
+ * This register can be cleared by simply writting all 1's to it.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_bckprs_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Number of cycles when back-pressure is received */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_spxx_bckprs_cnt_s        cn38xx;
+    struct cvmx_spxx_bckprs_cnt_s        cn38xxp2;
+    struct cvmx_spxx_bckprs_cnt_s        cn58xx;
+    struct cvmx_spxx_bckprs_cnt_s        cn58xxp1;
+} cvmx_spxx_bckprs_cnt_t;
+
+
+/**
+ * cvmx_spx#_bist_stat
+ *
+ * Notes:
+ * Bist results encoding
+ * - 0: good (or bist in progress/never run)
+ * - 1: bad
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_bist_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t stat2                   : 1;       /**< Bist Results/No Repair (Tx calendar table)
+                                                         (spx.stx.cal.calendar) */
+        uint64_t stat1                   : 1;       /**< Bist Results/No Repair (Rx calendar table)
+                                                         (spx.srx.spi4.cal.calendar) */
+        uint64_t stat0                   : 1;       /**< Bist Results/No Repair (Spi4 receive datapath FIFO)
+                                                         (spx.srx.spi4.dat.dpr) */
+#else
+        uint64_t stat0                   : 1;
+        uint64_t stat1                   : 1;
+        uint64_t stat2                   : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_spxx_bist_stat_s         cn38xx;
+    struct cvmx_spxx_bist_stat_s         cn38xxp2;
+    struct cvmx_spxx_bist_stat_s         cn58xx;
+    struct cvmx_spxx_bist_stat_s         cn58xxp1;
+} cvmx_spxx_bist_stat_t;
+
+
+/**
+ * cvmx_spx#_clk_ctl
+ *
+ * Notes:
+ * * SRXDLCK
+ *   When asserted, this bit locks the Spi4 receive DLLs.  This bit also
+ *   acts as the Spi4 receiver reset and must be asserted before the
+ *   training sequences are used to initialize the interface.  This bit
+ *   only applies to the receiver interface.
+ * 
+ * * RCVTRN
+ *   Once the SRXDLCK bit is asserted and the DLLs have locked and the
+ *   system has been programmed, software should assert this bit in order
+ *   to start looking for valid training sequence and synchronize the
+ *   interface. This bit only applies to the receiver interface.
+ * 
+ * * DRPTRN
+ *   The Spi4 receiver can either convert training packets into NOPs or
+ *   drop them entirely.  Dropping ticks allows the interface to deskew
+ *   periodically if the dclk and eclk ratios are close. This bit only
+ *   applies to the receiver interface.
+ * 
+ * * SNDTRN
+ *   When software sets this bit, it indicates that the Spi4 transmit
+ *   interface has been setup and has seen the calendare status.  Once the
+ *   transmitter begins sending training data, the receiving device is free
+ *   to start traversing the calendar table to synch the link.
+ * 
+ * * STATRCV
+ *   This bit determines which status clock edge to sample the status
+ *   channel in Spi4 mode.  Since the status channel is in the opposite
+ *   direction to the datapath, the STATRCV actually effects the
+ *   transmitter/TX block.
+ * 
+ * * STATDRV
+ *   This bit determines which status clock edge to drive the status
+ *   channel in Spi4 mode.  Since the status channel is in the opposite
+ *   direction to the datapath, the STATDRV actually effects the
+ *   receiver/RX block.
+ * 
+ * * RUNBIST
+ *   RUNBIST will beginning BIST/BISR in all the SPX compilied memories.
+ *   These memories are...
+ * 
+ *       * spx.srx.spi4.dat.dpr        // FIFO Spi4 to IMX
+ *       * spx.stx.cal.calendar        // Spi4 TX calendar table
+ *       * spx.srx.spi4.cal.calendar   // Spi4 RX calendar table
+ * 
+ *   RUNBIST must never be asserted when the interface is enabled.
+ *   Furthmore, setting RUNBIST at any other time is destructive and can
+ *   cause data and configuration corruption.  The entire interface must be
+ *   reconfigured when this bit is set.
+ * 
+ * * CLKDLY
+ *   Static clock positioning mostly intended for use in quarter clocking
+ *   schemes.  The delay window is not large enough for slow clock freq,
+ *   therefore clock and data must be statically positioned with CSRs.  By
+ *   changing the clock position relative to the data bits, we give the
+ *   system a wider window.
+ * 
+ * * SEETRN
+ *   In systems in which no training data is sent to N2 or N2 cannot
+ *   correctly sample the training data, software may pulse this bit by
+ *   writing a '1' followed by a '0' in order to correctly set the
+ *   receivers state.  The receive data bus should be idle at this time
+ *   (only NOPs on the bus).  If N2 cannot see at least on training
+ *   sequence, the data bus will not send any data to the core.  The
+ *   interface will hang.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_clk_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t seetrn                  : 1;       /**< Force the Spi4 receive into seeing a traing
+                                                         sequence */
+        uint64_t reserved_12_15          : 4;
+        uint64_t clkdly                  : 5;       /**< Set the spx__clkdly lines to this value to
+                                                         control the delay on the incoming dclk
+                                                         (spx__clkdly) */
+        uint64_t runbist                 : 1;       /**< Write this bit to begin BIST testing in SPX */
+        uint64_t statdrv                 : 1;       /**< Spi4 status channel drive mode
+                                                         - 1: Drive STAT on posedge of SCLK
+                                                         - 0: Drive STAT on negedge of SCLK */
+        uint64_t statrcv                 : 1;       /**< Spi4 status channel sample mode
+                                                         - 1: Sample STAT on posedge of SCLK
+                                                         - 0: Sample STAT on negedge of SCLK */
+        uint64_t sndtrn                  : 1;       /**< Start sending training patterns on the Spi4
+                                                         Tx Interface */
+        uint64_t drptrn                  : 1;       /**< Drop blocks of training packets */
+        uint64_t rcvtrn                  : 1;       /**< Write this bit once the DLL is locked to sync
+                                                         on the training seqeunce */
+        uint64_t srxdlck                 : 1;       /**< Write this bit to lock the Spi4 receive DLL */
+#else
+        uint64_t srxdlck                 : 1;
+        uint64_t rcvtrn                  : 1;
+        uint64_t drptrn                  : 1;
+        uint64_t sndtrn                  : 1;
+        uint64_t statrcv                 : 1;
+        uint64_t statdrv                 : 1;
+        uint64_t runbist                 : 1;
+        uint64_t clkdly                  : 5;
+        uint64_t reserved_12_15          : 4;
+        uint64_t seetrn                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_spxx_clk_ctl_s           cn38xx;
+    struct cvmx_spxx_clk_ctl_s           cn38xxp2;
+    struct cvmx_spxx_clk_ctl_s           cn58xx;
+    struct cvmx_spxx_clk_ctl_s           cn58xxp1;
+} cvmx_spxx_clk_ctl_t;
+
+
+/**
+ * cvmx_spx#_clk_stat
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_clk_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_11_63          : 53;
+        uint64_t stxcal                  : 1;       /**< The transistion from Sync to Calendar on status
+                                                         channel */
+        uint64_t reserved_9_9            : 1;
+        uint64_t srxtrn                  : 1;       /**< Saw a good data training sequence */
+        uint64_t s4clk1                  : 1;       /**< Saw '1' on Spi4 transmit status forward clk input */
+        uint64_t s4clk0                  : 1;       /**< Saw '0' on Spi4 transmit status forward clk input */
+        uint64_t d4clk1                  : 1;       /**< Saw '1' on Spi4 receive data forward clk input */
+        uint64_t d4clk0                  : 1;       /**< Saw '0' on Spi4 receive data forward clk input */
+        uint64_t reserved_0_3            : 4;
+#else
+        uint64_t reserved_0_3            : 4;
+        uint64_t d4clk0                  : 1;
+        uint64_t d4clk1                  : 1;
+        uint64_t s4clk0                  : 1;
+        uint64_t s4clk1                  : 1;
+        uint64_t srxtrn                  : 1;
+        uint64_t reserved_9_9            : 1;
+        uint64_t stxcal                  : 1;
+        uint64_t reserved_11_63          : 53;
+#endif
+    } s;
+    struct cvmx_spxx_clk_stat_s          cn38xx;
+    struct cvmx_spxx_clk_stat_s          cn38xxp2;
+    struct cvmx_spxx_clk_stat_s          cn58xx;
+    struct cvmx_spxx_clk_stat_s          cn58xxp1;
+} cvmx_spxx_clk_stat_t;
+
+
+/**
+ * cvmx_spx#_dbg_deskew_ctl
+ *
+ * Notes:
+ * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
+ * that Spec for more details.
+ * 
+ *   The basic idea is to allow software to disable the auto-deskew widgets
+ *   and make any adjustments by hand.  These steps should only be taken
+ *   once the RCVTRN bit is set and before any real traffic is sent on the
+ *   Spi4 bus.  Great care should be taken when messing with these bits as
+ *   improper programmings can cause catestrophic or intermitent problems.
+ * 
+ *   The params we have to test are the MUX tap selects and the XCV delay
+ *   tap selects.
+ * 
+ *   For the muxes, we can set each tap to a random value and then read
+ *   back the taps.  To write...
+ * 
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_CTL[OFFSET]   = mux tap value (2-bits)
+ *    SPXX_DBG_DESKEW_CTL[MUX]      = go bit
+ * 
+ *   Notice this can all happen with a single CSR write.  To read, first
+ *   set the bit you to look at with the SPXX_DBG_DESKEW_CTL[BITSEL], then
+ *   simply read SPXX_DBG_DESKEW_STATE[MUXSEL]...
+ * 
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_STATE[MUXSEL] = 2-bit value
+ * 
+ *   For the xcv delay taps, the CSR controls increment and decrement the
+ *   5-bit count value in the XCV.  This is a saturating counter, so it
+ *   will not wrap when decrementing below zero or incrementing above 31.
+ * 
+ *   To write...
+ * 
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_CTL[OFFSET]   = tap value increment or decrement amount (5-bits)
+ *    SPXX_DBG_DESKEW_CTL[INC|DEC]  = go bit
+ * 
+ *   These values are copied in SPX, so that they can be read back by
+ *   software by a similar mechanism to the MUX selects...
+ * 
+ *    SPXX_DBG_DESKEW_CTL[BITSEL]   = bit to set
+ *    SPXX_DBG_DESKEW_STATE[OFFSET] = 5-bit value
+ * 
+ *   In addition, there is a reset bit that sets all the state back to the
+ *   default/starting value of 0x10.
+ * 
+ *    SPXX_DBG_DESKEW_CTL[CLRDLY]   = 1
+ * 
+ * SINGLE STEP TRAINING MODE (WILMA)
+ *     Debug feature that will enable the user to single-step the debug
+ *     logic to watch initial movement and trends by putting the training
+ *     machine in single step mode.
+ * 
+ * * SPX*_DBG_DESKEW_CTL[SSTEP]
+ *        This will put the training control logic into single step mode.  We
+ *        will not deskew in this scenario and will require the TX device to
+ *        send continuous training sequences.
+ * 
+ *        It is required that SRX*_COM_CTL[INF_EN] be clear so that suspect
+ *        data does not flow into the chip.
+ * 
+ *        Deasserting SPX*_DBG_DESKEW_CTL[SSTEP] will attempt to deskew as per
+ *        the normal definition.  Single step mode is for debug only.  Special
+ *        care must be given to correctly deskew the interface if normal
+ *        operation is desired.
+ * 
+ * * SPX*_DBG_DESKEW_CTL[SSTEP_GO]
+ *        Each write of '1' to SSTEP_GO will go through a single training
+ *        iteration and will perform...
+ * 
+ *        - DLL update, if SPX*_DBG_DESKEW_CTL[DLLDIS] is clear
+ *        - coarse update, if SPX*_TRN4_CTL[MUX_EN] is set
+ *        - single fine update, if SPX*_TRN4_CTL[MACRO_EN] is set and an edge
+ *       was detected after walked +/- SPX*_TRN4_CTL[MAXDIST] taps.
+ * 
+ *        Writes to this register have no effect if the interface is not in
+ *        SSTEP mode (SPX*_DBG_DESKEW_CTL[SSTEP]).
+ * 
+ *        The WILMA mode will be cleared at the final state transition, so
+ *        that software can set SPX*_DBG_DESKEW_CTL[SSTEP] and
+ *        SPX*_DBG_DESKEW_CTL[SSTEP_GO] before setting SPX*_CLK_CTL[RCVTRN]
+ *        and the machine will go through the initial iteration and stop -
+ *        waiting for another SPX*_DBG_DESKEW_CTL[SSTEP_GO] or an interface
+ *        enable.
+ * 
+ * * SPX*_DBG_DESKEW_CTL[FALL8]
+ *   Determines how many pattern matches are required during training
+ *   operations to fallout of training and begin processing the normal data
+ *   stream.  The default value is 10 pattern matches.  The pattern that is
+ *   used is dependent on the SPX*_DBG_DESKEW_CTL[FALLNOP] CSR which
+ *   determines between non-training packets (the default) and NOPs.
+ * 
+ * * SPX*_DBG_DESKEW_CTL[FALLNOP]
+ *   Determines the pattern that is required during training operations to
+ *   fallout of training and begin processing the normal data stream.  The
+ *   default value is to match against non-training data.  Setting this
+ *   bit, changes the behavior to watch for NOPs packet instead.
+ * 
+ *   This bit should not be changed dynamically while the link is
+ *   operational.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_dbg_deskew_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_30_63          : 34;
+        uint64_t fallnop                 : 1;       /**< Training fallout on NOP matches instead of
+                                                         non-training matches.
+                                                         (spx_csr__spi4_fallout_nop) */
+        uint64_t fall8                   : 1;       /**< Training fallout at 8 pattern matches instead of 10
+                                                         (spx_csr__spi4_fallout_8_match) */
+        uint64_t reserved_26_27          : 2;
+        uint64_t sstep_go                : 1;       /**< Single Step Training Sequence
+                                                         (spx_csr__spi4_single_step_go) */
+        uint64_t sstep                   : 1;       /**< Single Step Training Mode
+                                                         (spx_csr__spi4_single_step_mode) */
+        uint64_t reserved_22_23          : 2;
+        uint64_t clrdly                  : 1;       /**< Resets the offset control in the XCV
+                                                         (spx_csr__spi4_dll_clr_dly) */
+        uint64_t dec                     : 1;       /**< Decrement the offset by OFFSET for the Spi4
+                                                         bit selected by BITSEL
+                                                         (spx_csr__spi4_dbg_trn_dec) */
+        uint64_t inc                     : 1;       /**< Increment the offset by OFFSET for the Spi4
+                                                         bit selected by BITSEL
+                                                         (spx_csr__spi4_dbg_trn_inc) */
+        uint64_t mux                     : 1;       /**< Set the mux select tap for the Spi4 bit
+                                                         selected by BITSEL
+                                                         (spx_csr__spi4_dbg_trn_mux) */
+        uint64_t offset                  : 5;       /**< Adds or subtracts (Based on INC or DEC) the
+                                                         offset to Spi4 bit BITSEL.
+                                                         (spx_csr__spi4_dbg_trn_offset) */
+        uint64_t bitsel                  : 5;       /**< Select the Spi4 CTL or DAT bit
+                                                         15-0 : Spi4 DAT[15:0]
+                                                         16   : Spi4 CTL
+                                                         - 31-17: Invalid
+                                                         (spx_csr__spi4_dbg_trn_bitsel) */
+        uint64_t offdly                  : 6;       /**< Set the spx__offset lines to this value when
+                                                         not in macro sequence
+                                                         (spx_csr__spi4_mac_offdly) */
+        uint64_t dllfrc                  : 1;       /**< Force the Spi4 RX DLL to update
+                                                         (spx_csr__spi4_dll_force) */
+        uint64_t dlldis                  : 1;       /**< Disable sending the update signal to the Spi4
+                                                         RX DLL when set
+                                                         (spx_csr__spi4_dll_trn_en) */
+#else
+        uint64_t dlldis                  : 1;
+        uint64_t dllfrc                  : 1;
+        uint64_t offdly                  : 6;
+        uint64_t bitsel                  : 5;
+        uint64_t offset                  : 5;
+        uint64_t mux                     : 1;
+        uint64_t inc                     : 1;
+        uint64_t dec                     : 1;
+        uint64_t clrdly                  : 1;
+        uint64_t reserved_22_23          : 2;
+        uint64_t sstep                   : 1;
+        uint64_t sstep_go                : 1;
+        uint64_t reserved_26_27          : 2;
+        uint64_t fall8                   : 1;
+        uint64_t fallnop                 : 1;
+        uint64_t reserved_30_63          : 34;
+#endif
+    } s;
+    struct cvmx_spxx_dbg_deskew_ctl_s    cn38xx;
+    struct cvmx_spxx_dbg_deskew_ctl_s    cn38xxp2;
+    struct cvmx_spxx_dbg_deskew_ctl_s    cn58xx;
+    struct cvmx_spxx_dbg_deskew_ctl_s    cn58xxp1;
+} cvmx_spxx_dbg_deskew_ctl_t;
+
+
+/**
+ * cvmx_spx#_dbg_deskew_state
+ *
+ * Notes:
+ * These bits are meant as a backdoor to control Spi4 per-bit deskew.  See
+ * that Spec for more details.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_dbg_deskew_state_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t testres                 : 1;       /**< Training Test Mode Result
+                                                         (srx_spi4__test_mode_result) */
+        uint64_t unxterm                 : 1;       /**< Unexpected training terminiation
+                                                         (srx_spi4__top_unxexp_trn_term) */
+        uint64_t muxsel                  : 2;       /**< The mux select value of the bit selected by
+                                                         SPX_DBG_DESKEW_CTL[BITSEL]
+                                                         (srx_spi4__trn_mux_sel) */
+        uint64_t offset                  : 5;       /**< The counter value of the bit selected by
+                                                         SPX_DBG_DESKEW_CTL[BITSEL]
+                                                         (srx_spi4__xcv_tap_select) */
+#else
+        uint64_t offset                  : 5;
+        uint64_t muxsel                  : 2;
+        uint64_t unxterm                 : 1;
+        uint64_t testres                 : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_spxx_dbg_deskew_state_s  cn38xx;
+    struct cvmx_spxx_dbg_deskew_state_s  cn38xxp2;
+    struct cvmx_spxx_dbg_deskew_state_s  cn58xx;
+    struct cvmx_spxx_dbg_deskew_state_s  cn58xxp1;
+} cvmx_spxx_dbg_deskew_state_t;
+
+
+/**
+ * cvmx_spx#_drv_ctl
+ *
+ * Notes:
+ * These bits all come from Duke - he will provide documentation and
+ * explanation.  I'll just butcher it.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_drv_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_0_63           : 64;
+#else
+        uint64_t reserved_0_63           : 64;
+#endif
+    } s;
+    struct cvmx_spxx_drv_ctl_cn38xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t stx4ncmp                : 4;       /**< Duke (spx__spi4_tx_nctl_comp) */
+        uint64_t stx4pcmp                : 4;       /**< Duke (spx__spi4_tx_pctl_comp) */
+        uint64_t srx4cmp                 : 8;       /**< Duke (spx__spi4_rx_rctl_comp) */
+#else
+        uint64_t srx4cmp                 : 8;
+        uint64_t stx4pcmp                : 4;
+        uint64_t stx4ncmp                : 4;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn38xx;
+    struct cvmx_spxx_drv_ctl_cn38xx      cn38xxp2;
+    struct cvmx_spxx_drv_ctl_cn58xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t stx4ncmp                : 4;       /**< Duke (spx__spi4_tx_nctl_comp) */
+        uint64_t stx4pcmp                : 4;       /**< Duke (spx__spi4_tx_pctl_comp) */
+        uint64_t reserved_10_15          : 6;
+        uint64_t srx4cmp                 : 10;      /**< Duke (spx__spi4_rx_rctl_comp) */
+#else
+        uint64_t srx4cmp                 : 10;
+        uint64_t reserved_10_15          : 6;
+        uint64_t stx4pcmp                : 4;
+        uint64_t stx4ncmp                : 4;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } cn58xx;
+    struct cvmx_spxx_drv_ctl_cn58xx      cn58xxp1;
+} cvmx_spxx_drv_ctl_t;
+
+
+/**
+ * cvmx_spx#_err_ctl
+ *
+ * SPX_ERR_CTL - Spi error control register
+ *
+ *
+ * Notes:
+ * * DIPPAY, DIPCLS, PRTNXA
+ * These bits control whether or not the packet's ERR bit is set when any of
+ * the these error is detected.  If the corresponding error's bit is clear,
+ * the packet ERR will be set.  If the error bit is set, the SPX will simply
+ * pass through the ERR bit without modifying it in anyway - the error bit
+ * may or may not have been set by the transmitter device.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_err_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t prtnxa                  : 1;       /**< Spi4 - set the ERR bit on packets in which the
+                                                         port is out-of-range */
+        uint64_t dipcls                  : 1;       /**< Spi4 DIPERR on closing control words cause the
+                                                         ERR bit to be set */
+        uint64_t dippay                  : 1;       /**< Spi4 DIPERR on payload control words cause the
+                                                         ERR bit to be set */
+        uint64_t reserved_4_5            : 2;
+        uint64_t errcnt                  : 4;       /**< Number of Dip4 errors before bringing down the
+                                                         interface */
+#else
+        uint64_t errcnt                  : 4;
+        uint64_t reserved_4_5            : 2;
+        uint64_t dippay                  : 1;
+        uint64_t dipcls                  : 1;
+        uint64_t prtnxa                  : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_spxx_err_ctl_s           cn38xx;
+    struct cvmx_spxx_err_ctl_s           cn38xxp2;
+    struct cvmx_spxx_err_ctl_s           cn58xx;
+    struct cvmx_spxx_err_ctl_s           cn58xxp1;
+} cvmx_spxx_err_ctl_t;
+
+
+/**
+ * cvmx_spx#_int_dat
+ *
+ * SPX_INT_DAT - Interrupt Data Register
+ *
+ *
+ * Notes:
+ * Note: The SPX_INT_DAT[MUL] bit is set when multiple errors have been
+ * detected that would set any of the data fields: PRT, RSVOP, and CALBNK.
+ * 
+ * The following errors will cause MUL to assert for PRT conflicts.
+ * - ABNORM
+ * - APERR
+ * - DPERR
+ * 
+ * The following errors will cause MUL to assert for RSVOP conflicts.
+ * - RSVERR
+ * 
+ * The following errors will cause MUL to assert for CALBNK conflicts.
+ * - CALERR
+ * 
+ * The following errors will cause MUL to assert if multiple interrupts are
+ * asserted.
+ * - TPAOVR
+ * 
+ * The MUL bit will be cleared once all outstanding errors have been
+ * cleared by software (not just MUL errors - all errors).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_int_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t mul                     : 1;       /**< Multiple errors have occured */
+        uint64_t reserved_14_30          : 17;
+        uint64_t calbnk                  : 2;       /**< Spi4 Calendar table parity error bank */
+        uint64_t rsvop                   : 4;       /**< Spi4 reserved control word */
+        uint64_t prt                     : 8;       /**< Port associated with error */
+#else
+        uint64_t prt                     : 8;
+        uint64_t rsvop                   : 4;
+        uint64_t calbnk                  : 2;
+        uint64_t reserved_14_30          : 17;
+        uint64_t mul                     : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_spxx_int_dat_s           cn38xx;
+    struct cvmx_spxx_int_dat_s           cn38xxp2;
+    struct cvmx_spxx_int_dat_s           cn58xx;
+    struct cvmx_spxx_int_dat_s           cn58xxp1;
+} cvmx_spxx_int_dat_t;
+
+
+/**
+ * cvmx_spx#_int_msk
+ *
+ * SPX_INT_MSK - Interrupt Mask Register
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_int_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t calerr                  : 1;       /**< Spi4 Calendar table parity error */
+        uint64_t syncerr                 : 1;       /**< Consecutive Spi4 DIP4 errors have exceeded
+                                                         SPX_ERR_CTL[ERRCNT] */
+        uint64_t diperr                  : 1;       /**< Spi4 DIP4 error */
+        uint64_t tpaovr                  : 1;       /**< Selected port has hit TPA overflow */
+        uint64_t rsverr                  : 1;       /**< Spi4 reserved control word detected */
+        uint64_t drwnng                  : 1;       /**< Spi4 receive FIFO drowning/overflow */
+        uint64_t clserr                  : 1;       /**< Spi4 packet closed on non-16B alignment without EOP */
+        uint64_t spiovr                  : 1;       /**< Spi async FIFO overflow (Spi3 or Spi4) */
+        uint64_t reserved_2_3            : 2;
+        uint64_t abnorm                  : 1;       /**< Abnormal packet termination (ERR bit) */
+        uint64_t prtnxa                  : 1;       /**< Port out of range */
+#else
+        uint64_t prtnxa                  : 1;
+        uint64_t abnorm                  : 1;
+        uint64_t reserved_2_3            : 2;
+        uint64_t spiovr                  : 1;
+        uint64_t clserr                  : 1;
+        uint64_t drwnng                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t tpaovr                  : 1;
+        uint64_t diperr                  : 1;
+        uint64_t syncerr                 : 1;
+        uint64_t calerr                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_spxx_int_msk_s           cn38xx;
+    struct cvmx_spxx_int_msk_s           cn38xxp2;
+    struct cvmx_spxx_int_msk_s           cn58xx;
+    struct cvmx_spxx_int_msk_s           cn58xxp1;
+} cvmx_spxx_int_msk_t;
+
+
+/**
+ * cvmx_spx#_int_reg
+ *
+ * SPX_INT_REG - Interrupt Register
+ *
+ *
+ * Notes:
+ * * PRTNXA
+ *   This error indicates that the port on the Spi bus was not a valid port
+ *   for the system.  Spi4 accesses occur on payload control bit-times. The
+ *   SRX can be configured with the exact number of ports available (by
+ *   SRX_COM_CTL[PRTS] register).  Any Spi access to anthing outside the range
+ *   of 0 .. (SRX_COM_CTL[PRTS] - 1) is considered an error.  The offending
+ *   port is logged in SPX_INT_DAT[PRT] if there are no pending interrupts in
+ *   SPX_INT_REG that require SPX_INT_DAT[PRT].
+ * 
+ *   SRX will not drop the packet with the bogus port address.  Instead, the
+ *   port will be mapped into the supported port range.  The remapped address
+ *   in simply...
+ * 
+ *            Address = [ interfaceId, ADR[3:0] ]
+ * 
+ *   If the SPX detects that a PRTNXA error has occured, the packet will
+ *   have its ERR bit set (or'ed in with the ERR bit from the transmitter)
+ *   if the SPX_ERR_CTL[PRTNXA] bit is clear.
+ * 
+ *   In Spi4 mode, SPX will generate an interrupt for every 8B data burst
+ *   associated with the invalid address.  The SPX_INT_DAT[MUL] bit will never
+ *   be set.
+ * 
+ * * ABNORM
+ *   This bit simply indicates that a given packet had abnormal terminiation.
+ *   In Spi4 mode, this means that packet completed with an EOPS[1:0] code of
+ *   2'b01.  This error can also be thought of as the application specific
+ *   error (as mentioned in the Spi4 spec).  The offending port is logged in
+ *   SPX_INT_DAT[PRT] if there are no pending interrupts in SPX_INT_REG that
+ *   require SPX_INT_DAT[PRT].
+ * 
+ *   The ABNORM error is only raised when the ERR bit that comes from the
+ *   Spi interface is set.  It will never assert if any internal condition
+ *   causes the ERR bit to assert (e.g. PRTNXA or DPERR).
+ * 
+ * * SPIOVR
+ *   This error indicates that the FIFOs that manage the async crossing from
+ *   the Spi clocks to the core clock domains have overflowed.  This is a
+ *   fatal error and can cause much data/control corruption since ticks will
+ *   be dropped and reordered.  This is purely a function of clock ratios and
+ *   correct system ratios should make this an impossible condition.
+ * 
+ * * CLSERR
+ *   This is a Spi4 error that indicates that a given data transfer burst
+ *   that did not terminate with an EOP, did not end with the 16B alignment
+ *   as per the Spi4 spec.  The offending port cannot be logged since the
+ *   block does not know the streamm terminated until the port switches.
+ *   At that time, that packet has already been pushed down the pipe.
+ * 
+ *   The CLSERR bit does not actually check the Spi4 burst - just how data
+ *   is accumulated for the downstream logic.  Bursts that are separted by
+ *   idles or training will still be merged into accumulated transfers and
+ *   will not fire the CLSERR condition.  The checker is really checking
+ *   non-8B aligned, non-EOP data ticks that are sent downstream.  These
+ *   ticks are what will really mess up the core.
+ * 
+ *   This is an expensive fix, so we'll probably let it ride.  We never
+ *   claim to check Spi4 protocol anyway.
+ * 
+ * * DRWNNG
+ *   This error indicates that the Spi4 FIFO that services the GMX has
+ *   overflowed.  Like the SPIOVR error condition, correct system ratios
+ *   should make this an impossible condition.
+ * 
+ * * RSVERR
+ *   This Spi4 error indicates that the Spi4 receiver has seen a reserve
+ *   control packet.  A reserve control packet is an invalid combiniation
+ *   of bits on DAT[15:12].  Basically this is DAT[15] == 1'b0 and DAT[12]
+ *   == 1'b1 (an SOP without a payload command).  The RSVERR indicates an
+ *   error has occured and SPX_INT_DAT[RSVOP] holds the first reserved
+ *   opcode and will be set if there are no pending interrupts in
+ *   SPX_INT_REG that require SPX_INT_DAT[RSVOP].
+ * 
+ * * TPAOVR
+ *   This bit indicates that the TPA Watcher has flagged an event.  See the
+ *   TPA Watcher for a more detailed discussion.
+ * 
+ * * DIPERR
+ *   This bit indicates that the Spi4 receiver has encountered a DIP4
+ *   miscompare on the datapath.  A DIPERR can occur in an IDLE or a
+ *   control word that frames a data burst.  If the DIPERR occurs on a
+ *   framing word there are three cases.
+ * 
+ *   1) DIPERR occurs at the end of a data burst.  The previous packet is
+ *      marked with the ERR bit to be processed later if
+ *      SPX_ERR_CTL[DIPCLS] is clear.
+ *   2) DIPERR occurs on a payload word.  The subsequent packet is marked
+ *      with the ERR bit to be processed later if SPX_ERR_CTL[DIPPAY] is
+ *      clear.
+ *   3) DIPERR occurs on a control word that closes on packet and is a
+ *      payload for another packet.  In this case, both packets will have
+ *      their ERR bit marked depending on the respective values of
+ *      SPX_ERR_CTL[DIPCLS] and SPX_ERR_CTL[DIPPAY] as discussed above.
+ * 
+ * * SYNCERR
+ *   This bit indicates that the Spi4 receiver has encountered
+ *   SPX_ERR_CTL[ERRCNT] consecutive Spi4 DIP4 errors and the interface
+ *   should be synched.
+ * 
+ * * CALERR
+ *   This bit indicates that the Spi4 calendar table encountered a parity
+ *   error.  This error bit is associated with the calendar table on the RX
+ *   interface - the interface that receives the Spi databus.  Parity errors
+ *   can occur during normal operation when the calendar table is constantly
+ *   being read for the port information, or during initialization time, when
+ *   the user has access.  Since the calendar table is split into two banks,
+ *   SPX_INT_DAT[CALBNK] indicates which banks have taken a parity error.
+ *   CALBNK[1] indicates the error occured in the upper bank, while CALBNK[0]
+ *   indicates that the error occured in the lower bank.  SPX_INT_DAT[CALBNK]
+ *   will be set if there are no pending interrupts in SPX_INT_REG that
+ *   require SPX_INT_DAT[CALBNK].
+ * 
+ * * SPF
+ *   This bit indicates that a Spi fatal error has occurred.  A fatal error
+ *   is defined as any error condition for which the corresponding
+ *   SPX_INT_SYNC bit is set.  Therefore, conservative systems can halt the
+ *   interface on any error condition although this is not strictly
+ *   necessary.  Some error are much more fatal in nature than others.
+ * 
+ *   PRTNXA, SPIOVR, CLSERR, DRWNNG, DIPERR, CALERR, and SYNCERR are examples
+ *   of fatal error for different reasons - usually because multiple port
+ *   streams could be effected.  ABNORM, RSVERR, and TPAOVR are conditions
+ *   that are contained to a single packet which allows the interface to drop
+ *   a single packet and remain up and stable.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t spf                     : 1;       /**< Spi interface down */
+        uint64_t reserved_12_30          : 19;
+        uint64_t calerr                  : 1;       /**< Spi4 Calendar table parity error */
+        uint64_t syncerr                 : 1;       /**< Consecutive Spi4 DIP4 errors have exceeded
+                                                         SPX_ERR_CTL[ERRCNT] */
+        uint64_t diperr                  : 1;       /**< Spi4 DIP4 error */
+        uint64_t tpaovr                  : 1;       /**< Selected port has hit TPA overflow */
+        uint64_t rsverr                  : 1;       /**< Spi4 reserved control word detected */
+        uint64_t drwnng                  : 1;       /**< Spi4 receive FIFO drowning/overflow */
+        uint64_t clserr                  : 1;       /**< Spi4 packet closed on non-16B alignment without EOP */
+        uint64_t spiovr                  : 1;       /**< Spi async FIFO overflow */
+        uint64_t reserved_2_3            : 2;
+        uint64_t abnorm                  : 1;       /**< Abnormal packet termination (ERR bit) */
+        uint64_t prtnxa                  : 1;       /**< Port out of range */
+#else
+        uint64_t prtnxa                  : 1;
+        uint64_t abnorm                  : 1;
+        uint64_t reserved_2_3            : 2;
+        uint64_t spiovr                  : 1;
+        uint64_t clserr                  : 1;
+        uint64_t drwnng                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t tpaovr                  : 1;
+        uint64_t diperr                  : 1;
+        uint64_t syncerr                 : 1;
+        uint64_t calerr                  : 1;
+        uint64_t reserved_12_30          : 19;
+        uint64_t spf                     : 1;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_spxx_int_reg_s           cn38xx;
+    struct cvmx_spxx_int_reg_s           cn38xxp2;
+    struct cvmx_spxx_int_reg_s           cn58xx;
+    struct cvmx_spxx_int_reg_s           cn58xxp1;
+} cvmx_spxx_int_reg_t;
+
+
+/**
+ * cvmx_spx#_int_sync
+ *
+ * SPX_INT_SYNC - Interrupt Sync Register
+ *
+ *
+ * Notes:
+ * This mask set indicates which exception condition should cause the
+ * SPX_INT_REG[SPF] bit to assert
+ * 
+ * It is recommended that software set the PRTNXA, SPIOVR, CLSERR, DRWNNG,
+ * DIPERR, CALERR, and SYNCERR errors as synchronization events.  Software is
+ * free to synchronize the bus on other conditions, but this is the minimum
+ * recommended set.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_int_sync_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_12_63          : 52;
+        uint64_t calerr                  : 1;       /**< Spi4 Calendar table parity error */
+        uint64_t syncerr                 : 1;       /**< Consecutive Spi4 DIP4 errors have exceeded
+                                                         SPX_ERR_CTL[ERRCNT] */
+        uint64_t diperr                  : 1;       /**< Spi4 DIP4 error */
+        uint64_t tpaovr                  : 1;       /**< Selected port has hit TPA overflow */
+        uint64_t rsverr                  : 1;       /**< Spi4 reserved control word detected */
+        uint64_t drwnng                  : 1;       /**< Spi4 receive FIFO drowning/overflow */
+        uint64_t clserr                  : 1;       /**< Spi4 packet closed on non-16B alignment without EOP */
+        uint64_t spiovr                  : 1;       /**< Spi async FIFO overflow (Spi3 or Spi4) */
+        uint64_t reserved_2_3            : 2;
+        uint64_t abnorm                  : 1;       /**< Abnormal packet termination (ERR bit) */
+        uint64_t prtnxa                  : 1;       /**< Port out of range */
+#else
+        uint64_t prtnxa                  : 1;
+        uint64_t abnorm                  : 1;
+        uint64_t reserved_2_3            : 2;
+        uint64_t spiovr                  : 1;
+        uint64_t clserr                  : 1;
+        uint64_t drwnng                  : 1;
+        uint64_t rsverr                  : 1;
+        uint64_t tpaovr                  : 1;
+        uint64_t diperr                  : 1;
+        uint64_t syncerr                 : 1;
+        uint64_t calerr                  : 1;
+        uint64_t reserved_12_63          : 52;
+#endif
+    } s;
+    struct cvmx_spxx_int_sync_s          cn38xx;
+    struct cvmx_spxx_int_sync_s          cn38xxp2;
+    struct cvmx_spxx_int_sync_s          cn58xx;
+    struct cvmx_spxx_int_sync_s          cn58xxp1;
+} cvmx_spxx_int_sync_t;
+
+
+/**
+ * cvmx_spx#_tpa_acc
+ *
+ * SPX_TPA_ACC - TPA watcher byte accumulator
+ *
+ *
+ * Notes:
+ * This field allows the user to access the TPA watcher accumulator counter.
+ * This register reflects the number of bytes sent to IMX once the port
+ * specified by SPX_TPA_SEL[PRTSEL] has lost its TPA.  The SPX_INT_REG[TPAOVR]
+ * bit is asserted when CNT >= SPX_TPA_MAX[MAX].  The CNT will continue to
+ * increment until the TPA for the port is asserted.  At that point the CNT
+ * value is frozen until software clears the interrupt bit.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_tpa_acc_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< TPA watcher accumulate count */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_spxx_tpa_acc_s           cn38xx;
+    struct cvmx_spxx_tpa_acc_s           cn38xxp2;
+    struct cvmx_spxx_tpa_acc_s           cn58xx;
+    struct cvmx_spxx_tpa_acc_s           cn58xxp1;
+} cvmx_spxx_tpa_acc_t;
+
+
+/**
+ * cvmx_spx#_tpa_max
+ *
+ * SPX_TPA_MAX - TPA watcher assertion threshold
+ *
+ *
+ * Notes:
+ * The TPA watcher has the ability to notify the system with an interrupt when
+ * too much data has been received on loss of TPA.  The user sets the
+ * SPX_TPA_MAX[MAX] register and when the watcher has accumulated that many
+ * ticks, then the interrupt is conditionally raised (based on interrupt mask
+ * bits).  This feature will be disabled if the programmed count is zero.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_tpa_max_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t max                     : 32;      /**< TPA watcher TPA threshold */
+#else
+        uint64_t max                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_spxx_tpa_max_s           cn38xx;
+    struct cvmx_spxx_tpa_max_s           cn38xxp2;
+    struct cvmx_spxx_tpa_max_s           cn58xx;
+    struct cvmx_spxx_tpa_max_s           cn58xxp1;
+} cvmx_spxx_tpa_max_t;
+
+
+/**
+ * cvmx_spx#_tpa_sel
+ *
+ * SPX_TPA_SEL - TPA watcher port selector
+ *
+ *
+ * Notes:
+ * The TPA Watcher is primarily a debug vehicle used to help initial bringup
+ * of a system.  The TPA watcher counts bytes that roll in from the Spi
+ * interface.  The user programs the Spi port to watch using
+ * SPX_TPA_SEL[PRTSEL].  Once the TPA is deasserted for that port, the watcher
+ * begins to count the data ticks that have been delivered to the inbound
+ * datapath (and eventually to the IOB).  The result is that we can derive
+ * turn-around times of the other device by watching how much data was sent
+ * after a loss of TPA through the SPX_TPA_ACC[CNT] register.  An optional
+ * interrupt may be raised as well.  See SPX_TPA_MAX for further information.
+ * 
+ * TPA's can be deasserted for a number of reasons...
+ * 
+ * 1) IPD indicates backpressure
+ * 2) The GMX inbound FIFO is filling up and should BP
+ * 3) User has out an override on the TPA wires
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_tpa_sel_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t prtsel                  : 4;       /**< TPA watcher port select */
+#else
+        uint64_t prtsel                  : 4;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_spxx_tpa_sel_s           cn38xx;
+    struct cvmx_spxx_tpa_sel_s           cn38xxp2;
+    struct cvmx_spxx_tpa_sel_s           cn58xx;
+    struct cvmx_spxx_tpa_sel_s           cn58xxp1;
+} cvmx_spxx_tpa_sel_t;
+
+
+/**
+ * cvmx_spx#_trn4_ctl
+ *
+ * Notes:
+ * These bits are controls for the Spi4 RX bit deskew logic.  See that Spec
+ * for further details.
+ * 
+ * * BOOT_BIT
+ *   On the initial training synchronization sequence, the hardware has the
+ *   BOOT_BIT set which means that it will continueously perform macro
+ *   operations.  Once the BOOT_BIT is cleared, the macro machine will finish
+ *   the macro operation is working on and then return to the idle state.
+ *   Subsequent training sequences will only go through a single macro
+ *   operation in order to do slight deskews.
+ * 
+ * * JITTER
+ *   Minimum value is 1.  This parameter must be set for Spi4 mode using
+ *   auto-bit deskew.  Regardless of the original intent, this field must be
+ *   set non-zero for deskew to function correctly.
+ * 
+ *   The thought is the JITTER range is no longer required since the macro
+ *   machine was enhanced to understand about edge direction.  Originally
+ *   these bits were intended to compensate for clock jitter.
+ * 
+ *   dly:    this is the intrinsic delay of each delay element
+ *              tap currently, it is 70ps-110ps.
+ *   jitter: amount of jitter we expect in the system (~200ps)
+ *   j:      number of taps to account for jitter
+ * 
+ *   j = ((jitter / dly) + 1)
+ * 
+ * * TRNTEST
+ *   This mode is used to test systems to make sure that the bit deskew
+ *   parameters have been correctly setup.  After configuration, software can
+ *   set the TRNTEST mode bit.  This should be done before SRX_COM_CTL[ST_EN]
+ *   is set such that we can be sure that the TX device is simply sending
+ *   continuous training patterns.
+ * 
+ *   The test mode samples every incoming bit-time and makes sure that it is
+ *   either a training control or a training data packet.  If any other data
+ *   is observed, then SPX_DBG_DESKEW_STATE[TESTRES] will assert signaling a
+ *   test failure.
+ * 
+ *   Software must clear TRNTEST before training is terminated.
+ * 
+ * * Example Spi4 RX init flow...
+ * 
+ * 1) set the CLKDLY lines (SPXX_CLK_CTL[CLKDLY])
+ *    - these bits must be set before the DLL can successfully lock
+ * 
+ * 2) set the SRXDLCK (SPXX_CLK_CTL[SRXDLCK])
+ *    - this is the DLL lock bit which also acts as a block reset
+ * 
+ * 3) wait for the DLLs lock
+ * 
+ * 4) set any desired fields in SPXX_DBG_DESKEW_CTL
+ *    - This register has only one field that most users will care about.
+ *      When set, DLLDIS will disable sending update pulses to the Spi4 RX
+ *      DLLs.  This pulse allows the DLL to adjust to clock variations over
+ *      time.  In general, it is desired behavior.
+ * 
+ * 5) set fields in SPXX_TRN4_CTL
+ *    - These fields deal with the MUX training sequence
+ *      * MUX_EN
+ *        This is the enable bit for the mux select.  The MUX select will
+ *        run in the training sequence between the DLL and the Macro
+ *        sequence when enabled.  Once the MUX selects are selected, the
+ *        entire macro sequence must be rerun.  The expectation is that
+ *        this is only run at boot time and this is bit cleared at/around
+ *        step \#8.
+ *    - These fields deal with the Macro training sequence
+ *      * MACRO_EN
+ *        This is the enable bit for the macro sequence.  Macro sequences
+ *        will run after the DLL and MUX training sequences.  Each macro
+ *        sequence can move the offset by one value.
+ *      * MAXDIST
+ *        This is how far we will search for an edge.  Example...
+ * 
+ *           dly:    this is the intrinsic delay of each delay element
+ *                   tap currently, it is 70ps-110ps.
+ *           U:      bit time period in time units.
+ * 
+ *           MAXDIST = MIN(16, ((bit_time / 2) / dly)
+ * 
+ *           Each MAXDIST iteration consists of an edge detect in the early
+ *           and late (+/-) directions in an attempt to center the data.  This
+ *           requires two training transistions, the control/data and
+ *           data/control transistions which comprise a training sequence.
+ *           Therefore, the number of training sequences required for a single
+ *           macro operation is simply MAXDIST.
+ * 
+ * 6) set the RCVTRN go bit (SPXX_CLK_CTL[RCVTRN])
+ *    - this bit synchs on the first valid complete training cycle and
+ *      starts to process the training packets
+ * 
+ * 6b) This is where software could manually set the controls as opposed to
+ *     letting the hardware do it.  See the SPXX_DBG_DESKEW_CTL register
+ *        description for more detail.
+ * 
+ * 7) the TX device must continue to send training packets for the initial
+ *    time period.
+ *    - this can be determined by...
+ * 
+ *      DLL: one training sequence for the DLL adjustment (regardless of enable/disable)
+ *      MUX: one training sequence for the Flop MUX taps (regardless of enable/disable)
+ *      INIT_SEQUENCES: max number of taps that we must move
+ * 
+ *         INIT_SEQUENCES = MIN(16, ((bit_time / 2) / dly))
+ * 
+ *         INIT_TRN = DLL + MUX + ROUNDUP((INIT_SEQUENCES * (MAXDIST + 2)))
+ * 
+ * 
+ *    - software can either wait a fixed amount of time based on the clock
+ *      frequencies or poll the SPXX_CLK_STAT[SRXTRN] register.  Each
+ *      assertion of SRXTRN means that at least one training sequence has
+ *      been received.  Software can poll, clear, and repeat on this bit to
+ *      eventually count all required transistions.
+ * 
+ *      int cnt = 0;
+ *      while (cnt < INIT_TRN) [
+ *             if (SPXX_CLK_STAT[SRXTRN]) [
+ *                cnt++;
+ *                SPXX_CLK_STAT[SRXTRN] = 0;
+ *             ]
+ *      ]
+ * 
+ *   - subsequent training sequences will normally move the taps only
+ *     one position, so the ALPHA equation becomes...
+ * 
+ *     MAC   = (MAXDIST == 0) ? 1 : ROUNDUP((1 * (MAXDIST + 2))) + 1
+ * 
+ *        ALPHA = DLL + MUX + MAC
+ * 
+ *     ergo, MAXDIST simplifies to...
+ * 
+ *        ALPHA = (MAXDIST == 0) ? 3 : MAXDIST + 5
+ * 
+ *        DLL and MUX and MAC will always require at least a training sequence
+ *        each - even if disabled.  If the macro sequence is enabled, an
+ *        additional training sequenece at the end is necessary.  The extra
+ *        sequence allows for all training state to be cleared before resuming
+ *        normal operation.
+ * 
+ * 8) after the recevier gets enough training sequences in order to achieve
+ *    deskew lock, set SPXX_TRN4_CTL[CLR_BOOT]
+ *    - this disables the continuous macro sequences and puts into into one
+ *      macro sequnence per training operation
+ *    - optionally, the machine can choose to fall out of training if
+ *      enough NOPs follow the training operation (require at least 32 NOPs
+ *      to follow the training sequence).
+ * 
+ *    There must be at least MAXDIST + 3 training sequences after the
+ *    SPXX_TRN4_CTL[CLR_BOOT] is set or sufficient NOPs from the TX device.
+ * 
+ * 9) the TX device continues to send training sequences until the RX
+ *    device sends a calendar transistion.  This is controlled by
+ *    SRXX_COM_CTL[ST_EN].  Other restrictions require other Spi parameters
+ *    (e.g. the calendar table) to be setup before this bit can be enabled.
+ *    Once the entire interface is properly programmed, software writes
+ *    SRXX_COM_CTL[INF_EN].  At this point, the Spi4 packets will begin to
+ *    be sent into the N2K core and processed by the chip.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spxx_trn4_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_13_63          : 51;
+        uint64_t trntest                 : 1;       /**< Training Test Mode
+                                                         This bit is only for initial bringup
+                                                         (spx_csr__spi4_trn_test_mode) */
+        uint64_t jitter                  : 3;       /**< Accounts for jitter when the macro sequence is
+                                                         locking.  The value is how many consecutive
+                                                         transititions before declaring en edge.  Minimum
+                                                         value is 1.  This parameter must be set for Spi4
+                                                         mode using auto-bit deskew.
+                                                         (spx_csr__spi4_mac_jitter) */
+        uint64_t clr_boot                : 1;       /**< Clear the macro boot sequence mode bit
+                                                         (spx_csr__spi4_mac_clr_boot) */
+        uint64_t set_boot                : 1;       /**< Enable the macro boot sequence mode bit
+                                                         (spx_csr__spi4_mac_set_boot) */
+        uint64_t maxdist                 : 5;       /**< This field defines how far from center the
+                                                         deskew logic will search in a single macro
+                                                          sequence (spx_csr__spi4_mac_iters) */
+        uint64_t macro_en                : 1;       /**< Allow the macro sequence to center the sample
+                                                         point in the data window through hardware
+                                                         (spx_csr__spi4_mac_trn_en) */
+        uint64_t mux_en                  : 1;       /**< Enable the hardware machine that selects the
+                                                         proper coarse FLOP selects
+                                                         (spx_csr__spi4_mux_trn_en) */
+#else
+        uint64_t mux_en                  : 1;
+        uint64_t macro_en                : 1;
+        uint64_t maxdist                 : 5;
+        uint64_t set_boot                : 1;
+        uint64_t clr_boot                : 1;
+        uint64_t jitter                  : 3;
+        uint64_t trntest                 : 1;
+        uint64_t reserved_13_63          : 51;
+#endif
+    } s;
+    struct cvmx_spxx_trn4_ctl_s          cn38xx;
+    struct cvmx_spxx_trn4_ctl_s          cn38xxp2;
+    struct cvmx_spxx_trn4_ctl_s          cn58xx;
+    struct cvmx_spxx_trn4_ctl_s          cn58xxp1;
+} cvmx_spxx_trn4_ctl_t;
+
+
+/**
+ * cvmx_spx0_pll_bw_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spx0_pll_bw_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t bw_ctl                  : 5;       /**< Core PLL bandwidth control */
+#else
+        uint64_t bw_ctl                  : 5;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_spx0_pll_bw_ctl_s        cn38xx;
+    struct cvmx_spx0_pll_bw_ctl_s        cn38xxp2;
+} cvmx_spx0_pll_bw_ctl_t;
+
+
+/**
+ * cvmx_spx0_pll_setting
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_spx0_pll_setting_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t setting                 : 17;      /**< Core PLL setting */
+#else
+        uint64_t setting                 : 17;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_spx0_pll_setting_s       cn38xx;
+    struct cvmx_spx0_pll_setting_s       cn38xxp2;
+} cvmx_spx0_pll_setting_t;
+
+
+/**
+ * cvmx_srx#_com_ctl
+ *
+ * SRX_COM_CTL - Spi receive common control
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * Both the calendar table and the LEN and M parameters must be completely
+ * setup before writing the Interface enable (INF_EN) and Status channel
+ * enabled (ST_EN) asserted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_srxx_com_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t prts                    : 4;       /**< Number of ports in the receiver (write: ports - 1)
+                                                         - 0:  1 port
+                                                         - 1:  2 ports
+                                                         - 2:  3 ports
+                                                          - ...
+                                                          - 15: 16 ports */
+        uint64_t st_en                   : 1;       /**< Status channel enabled
+                                                         This is to allow configs without a status channel.
+                                                         This bit should not be modified once the
+                                                         interface is enabled. */
+        uint64_t reserved_1_2            : 2;
+        uint64_t inf_en                  : 1;       /**< Interface enable
+                                                         The master switch that enables the entire
+                                                         interface. SRX will not validiate any data until
+                                                         this bit is set. This bit should not be modified
+                                                         once the interface is enabled. */
+#else
+        uint64_t inf_en                  : 1;
+        uint64_t reserved_1_2            : 2;
+        uint64_t st_en                   : 1;
+        uint64_t prts                    : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_srxx_com_ctl_s           cn38xx;
+    struct cvmx_srxx_com_ctl_s           cn38xxp2;
+    struct cvmx_srxx_com_ctl_s           cn58xx;
+    struct cvmx_srxx_com_ctl_s           cn58xxp1;
+} cvmx_srxx_com_ctl_t;
+
+
+/**
+ * cvmx_srx#_ign_rx_full
+ *
+ * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure
+ *
+ *
+ * Notes:
+ * * IGNORE
+ * If a device can not or should not assert backpressure, then setting DROP
+ * will force STARVING status on the status channel for all ports.  This
+ * eliminates any back pressure from N2.
+ * 
+ * This implies that it's ok drop packets when the FIFOS fill up.
+ * 
+ * A side effect of this mode is that the TPA Watcher will effectively be
+ * disabled.  Since the DROP mode forces all TPA lines asserted, the TPA
+ * Watcher will never find a cycle where the TPA for the selected port is
+ * deasserted in order to increment its count.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_srxx_ign_rx_full_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t ignore                  : 16;      /**< This port should ignore backpressure hints from
+                                                          GMX when the RX FIFO fills up
+                                                         - 0: Use GMX backpressure
+                                                         - 1: Ignore GMX backpressure */
+#else
+        uint64_t ignore                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_srxx_ign_rx_full_s       cn38xx;
+    struct cvmx_srxx_ign_rx_full_s       cn38xxp2;
+    struct cvmx_srxx_ign_rx_full_s       cn58xx;
+    struct cvmx_srxx_ign_rx_full_s       cn58xxp1;
+} cvmx_srxx_ign_rx_full_t;
+
+
+/**
+ * cvmx_srx#_spi4_cal#
+ *
+ * specify the RSL base addresses for the block
+ * SRX_SPI4_CAL - Spi4 Calender table
+ * direct_calendar_write / direct_calendar_read
+ *
+ * Notes:
+ * There are 32 calendar table CSR's, each containing 4 entries for a
+ *     total of 128 entries.  In the above definition...
+ * 
+ *           n = calendar table offset * 4
+ * 
+ *        Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
+ *        (with n == 0).  Offset 0x10 is the 16th entry in the calendar table
+ *        and would contain entries (16*4) = 64, 65, 66, and 67.
+ * 
+ * Restrictions:
+ *          Calendar table entry accesses (read or write) can only occur
+ *          if the interface is disabled.  All other accesses will be
+ *          unpredictable.
+ * 
+ *          Both the calendar table and the LEN and M parameters must be
+ *          completely setup before writing the Interface enable (INF_EN) and
+ *          Status channel enabled (ST_EN) asserted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_srxx_spi4_calx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t oddpar                  : 1;       /**< Odd parity over SRX_SPI4_CAL[15:0]
+                                                         (^SRX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
+        uint64_t prt3                    : 4;       /**< Status for port n+3 */
+        uint64_t prt2                    : 4;       /**< Status for port n+2 */
+        uint64_t prt1                    : 4;       /**< Status for port n+1 */
+        uint64_t prt0                    : 4;       /**< Status for port n+0 */
+#else
+        uint64_t prt0                    : 4;
+        uint64_t prt1                    : 4;
+        uint64_t prt2                    : 4;
+        uint64_t prt3                    : 4;
+        uint64_t oddpar                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_srxx_spi4_calx_s         cn38xx;
+    struct cvmx_srxx_spi4_calx_s         cn38xxp2;
+    struct cvmx_srxx_spi4_calx_s         cn58xx;
+    struct cvmx_srxx_spi4_calx_s         cn58xxp1;
+} cvmx_srxx_spi4_calx_t;
+
+
+/**
+ * cvmx_srx#_spi4_stat
+ *
+ * SRX_SPI4_STAT - Spi4 status channel control
+ *
+ *
+ * Notes:
+ * Restrictions:
+ *    Both the calendar table and the LEN and M parameters must be
+ *    completely setup before writing the Interface enable (INF_EN) and
+ *    Status channel enabled (ST_EN) asserted.
+ * 
+ * Current rev only supports LVTTL status IO
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_srxx_spi4_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t m                       : 8;       /**< CALENDAR_M (from spi4.2 spec) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t len                     : 7;       /**< CALENDAR_LEN (from spi4.2 spec) */
+#else
+        uint64_t len                     : 7;
+        uint64_t reserved_7_7            : 1;
+        uint64_t m                       : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_srxx_spi4_stat_s         cn38xx;
+    struct cvmx_srxx_spi4_stat_s         cn38xxp2;
+    struct cvmx_srxx_spi4_stat_s         cn58xx;
+    struct cvmx_srxx_spi4_stat_s         cn58xxp1;
+} cvmx_srxx_spi4_stat_t;
+
+
+/**
+ * cvmx_srx#_sw_tick_ctl
+ *
+ * SRX_SW_TICK_CTL - Create a software tick of Spi4 data.  A write to this register will create a data tick.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_srxx_sw_tick_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t eop                     : 1;       /**< SW Tick EOP
+                                                         (PASS3 only) */
+        uint64_t sop                     : 1;       /**< SW Tick SOP
+                                                         (PASS3 only) */
+        uint64_t mod                     : 4;       /**< SW Tick MOD - valid byte count
+                                                         (PASS3 only) */
+        uint64_t opc                     : 4;       /**< SW Tick ERR - packet had an error
+                                                         (PASS3 only) */
+        uint64_t adr                     : 4;       /**< SW Tick port address
+                                                         (PASS3 only) */
+#else
+        uint64_t adr                     : 4;
+        uint64_t opc                     : 4;
+        uint64_t mod                     : 4;
+        uint64_t sop                     : 1;
+        uint64_t eop                     : 1;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_srxx_sw_tick_ctl_s       cn38xx;
+    struct cvmx_srxx_sw_tick_ctl_s       cn58xx;
+    struct cvmx_srxx_sw_tick_ctl_s       cn58xxp1;
+} cvmx_srxx_sw_tick_ctl_t;
+
+
+/**
+ * cvmx_srx#_sw_tick_dat
+ *
+ * SRX_SW_TICK_DAT - Create a software tick of Spi4 data
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_srxx_sw_tick_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t dat                     : 64;      /**< Data tick when SRX_SW_TICK_CTL is written
+                                                         (PASS3 only) */
+#else
+        uint64_t dat                     : 64;
+#endif
+    } s;
+    struct cvmx_srxx_sw_tick_dat_s       cn38xx;
+    struct cvmx_srxx_sw_tick_dat_s       cn58xx;
+    struct cvmx_srxx_sw_tick_dat_s       cn58xxp1;
+} cvmx_srxx_sw_tick_dat_t;
+
+
+/**
+ * cvmx_stx#_arb_ctl
+ *
+ * STX_ARB_CTL - Spi transmit arbitration control
+ *
+ *
+ * Notes:
+ * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
+ * parameter will have to be adjusted.  Please see the
+ * STX_SPI4_DAT[MAX_T] section for additional information.  In
+ * addition, the min_burst can only be guaranteed on the initial data
+ * burst of a given packet (i.e. the first data burst which contains
+ * the SOP tick).  All subsequent bursts could be truncated by training
+ * sequences at any point during transmission and could be arbitrarily
+ * small.  This mode is only for use in Spi4 mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_arb_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t mintrn                  : 1;       /**< Hold off training cycles until STX_MIN_BST[MINB]
+                                                         is satisfied */
+        uint64_t reserved_4_4            : 1;
+        uint64_t igntpa                  : 1;       /**< User switch to ignore any TPA information from the
+                                                         Spi interface. This CSR forces all TPA terms to
+                                                         be masked out.  It is only intended as backdoor
+                                                         or debug feature. */
+        uint64_t reserved_0_2            : 3;
+#else
+        uint64_t reserved_0_2            : 3;
+        uint64_t igntpa                  : 1;
+        uint64_t reserved_4_4            : 1;
+        uint64_t mintrn                  : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_stxx_arb_ctl_s           cn38xx;
+    struct cvmx_stxx_arb_ctl_s           cn38xxp2;
+    struct cvmx_stxx_arb_ctl_s           cn58xx;
+    struct cvmx_stxx_arb_ctl_s           cn58xxp1;
+} cvmx_stxx_arb_ctl_t;
+
+
+/**
+ * cvmx_stx#_bckprs_cnt
+ *
+ * Notes:
+ * This register reports the total number of cycles (STX data clks -
+ * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA
+ * or is otherwise receiving backpressure.
+ * 
+ * In Spi4 mode, this is defined as a loss of TPA which is indicated when
+ * the receiving device reports SATISFIED for the given port.  The calendar
+ * status is brought into N2 on the spi4_tx*_sclk and synchronized into the
+ * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk
+ * clock (internally, this the stx_clk).  The counter will update on the
+ * rising edge in which backpressure is reported.
+ * 
+ * This register will be cleared when software writes all '1's to
+ * the STX_BCKPRS_CNT.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_bckprs_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Number of cycles when back-pressure is received
+                                                         for port defined in STX_STAT_CTL[BCKPRS] */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_stxx_bckprs_cnt_s        cn38xx;
+    struct cvmx_stxx_bckprs_cnt_s        cn38xxp2;
+    struct cvmx_stxx_bckprs_cnt_s        cn58xx;
+    struct cvmx_stxx_bckprs_cnt_s        cn58xxp1;
+} cvmx_stxx_bckprs_cnt_t;
+
+
+/**
+ * cvmx_stx#_com_ctl
+ *
+ * STX_COM_CTL - TX Common Control Register
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * Both the calendar table and the LEN and M parameters must be
+ * completely setup before writing the Interface enable (INF_EN) and
+ * Status channel enabled (ST_EN) asserted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_com_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t st_en                   : 1;       /**< Status channel enabled */
+        uint64_t reserved_1_2            : 2;
+        uint64_t inf_en                  : 1;       /**< Interface enable */
+#else
+        uint64_t inf_en                  : 1;
+        uint64_t reserved_1_2            : 2;
+        uint64_t st_en                   : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_stxx_com_ctl_s           cn38xx;
+    struct cvmx_stxx_com_ctl_s           cn38xxp2;
+    struct cvmx_stxx_com_ctl_s           cn58xx;
+    struct cvmx_stxx_com_ctl_s           cn58xxp1;
+} cvmx_stxx_com_ctl_t;
+
+
+/**
+ * cvmx_stx#_dip_cnt
+ *
+ * Notes:
+ * * DIPMAX
+ *   This counts the number of consecutive DIP2 states in which the the
+ *   received DIP2 is bad.  The expected range is 1-15 cycles with the
+ *   value of 0 meaning disabled.
+ * 
+ * * FRMMAX
+ *   This counts the number of consecutive unexpected framing patterns (11)
+ *   states.  The expected range is 1-15 cycles with the value of 0 meaning
+ *   disabled.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_dip_cnt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t frmmax                  : 4;       /**< Number of consecutive unexpected framing patterns
+                                                         before loss of sync */
+        uint64_t dipmax                  : 4;       /**< Number of consecutive DIP2 error before loss
+                                                         of sync */
+#else
+        uint64_t dipmax                  : 4;
+        uint64_t frmmax                  : 4;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_stxx_dip_cnt_s           cn38xx;
+    struct cvmx_stxx_dip_cnt_s           cn38xxp2;
+    struct cvmx_stxx_dip_cnt_s           cn58xx;
+    struct cvmx_stxx_dip_cnt_s           cn58xxp1;
+} cvmx_stxx_dip_cnt_t;
+
+
+/**
+ * cvmx_stx#_ign_cal
+ *
+ * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_ign_cal_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t igntpa                  : 16;      /**< Ignore Calendar Status from Spi4 Status Channel
+                                                          per Spi4 port
+                                                         - 0: Use the status channel info
+                                                         - 1: Grant the given port MAX_BURST1 credits */
+#else
+        uint64_t igntpa                  : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_stxx_ign_cal_s           cn38xx;
+    struct cvmx_stxx_ign_cal_s           cn38xxp2;
+    struct cvmx_stxx_ign_cal_s           cn58xx;
+    struct cvmx_stxx_ign_cal_s           cn58xxp1;
+} cvmx_stxx_ign_cal_t;
+
+
+/**
+ * cvmx_stx#_int_msk
+ *
+ * Notes:
+ * If the bit is enabled, then the coresponding exception condition will
+ * result in an interrupt to the system.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_int_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t frmerr                  : 1;       /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
+        uint64_t unxfrm                  : 1;       /**< Unexpected framing sequence */
+        uint64_t nosync                  : 1;       /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
+        uint64_t diperr                  : 1;       /**< DIP2 error on the Spi4 Status channel */
+        uint64_t datovr                  : 1;       /**< Spi4 FIFO overflow error */
+        uint64_t ovrbst                  : 1;       /**< Transmit packet burst too big */
+        uint64_t calpar1                 : 1;       /**< STX Calendar Table Parity Error Bank1 */
+        uint64_t calpar0                 : 1;       /**< STX Calendar Table Parity Error Bank0 */
+#else
+        uint64_t calpar0                 : 1;
+        uint64_t calpar1                 : 1;
+        uint64_t ovrbst                  : 1;
+        uint64_t datovr                  : 1;
+        uint64_t diperr                  : 1;
+        uint64_t nosync                  : 1;
+        uint64_t unxfrm                  : 1;
+        uint64_t frmerr                  : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_stxx_int_msk_s           cn38xx;
+    struct cvmx_stxx_int_msk_s           cn38xxp2;
+    struct cvmx_stxx_int_msk_s           cn58xx;
+    struct cvmx_stxx_int_msk_s           cn58xxp1;
+} cvmx_stxx_int_msk_t;
+
+
+/**
+ * cvmx_stx#_int_reg
+ *
+ * Notes:
+ * * CALPAR0
+ *   This bit indicates that the Spi4 calendar table encountered a parity
+ *   error on bank0 of the calendar table memory.  This error bit is
+ *   associated with the calendar table on the TX interface - the interface
+ *   that drives the Spi databus.  The calendar table is used in Spi4 mode
+ *   when using the status channel.  Parity errors can occur during normal
+ *   operation when the calendar table is constantly being read for the port
+ *   information, or during initialization time, when the user has access.
+ *   This errors will force the the status channel to the reset state and
+ *   begin driving training sequences.  The status channel will also reset.
+ *   Software must follow the init sequence to resynch the interface.  This
+ *   includes toggling INF_EN which will cancel all outstanding accumulated
+ *   credits.
+ * 
+ * * CALPAR1
+ *   Identical to CALPAR0 except that it indicates that the error occured
+ *   on bank1 (instead of bank0).
+ * 
+ * * OVRBST
+ *   STX can track upto a 512KB data burst.  Any packet larger than that is
+ *   illegal and will cause confusion in the STX state machine.  BMI is
+ *   responsible for throwing away these out of control packets from the
+ *   input and the Execs should never generate them on the output.  This is
+ *   a fatal error and should have STX_INT_SYNC[OVRBST] set.
+ * 
+ * * DATOVR
+ *   FIFO where the Spi4 data ramps upto its transmit frequency has
+ *   overflowed.  This is a fatal error and should have
+ *   STX_INT_SYNC[DATOVR] set.
+ * 
+ * * DIPERR
+ *   This bit will fire if any DIP2 error is caught by the Spi4 status
+ *   channel.
+ * 
+ * * NOSYNC
+ *   This bit indicates that the number of consecutive DIP2 errors exceeds
+ *   STX_DIP_CNT[MAXDIP] and that the interface should be taken down.  The
+ *   datapath will be notified and send continuous training sequences until
+ *   software resynchronizes the interface.  This error condition should
+ *   have STX_INT_SYNC[NOSYNC] set.
+ * 
+ * * UNXFRM
+ *   Unexpected framing data was seen on the status channel.
+ * 
+ * * FRMERR
+ *   This bit indicates that the number of consecutive unexpected framing
+ *   sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken
+ *   down.  The datapath will be notified and send continuous training
+ *   sequences until software resynchronizes the interface.  This error
+ *   condition should have STX_INT_SYNC[FRMERR] set.
+ * 
+ * * SYNCERR
+ *   Indicates that an exception marked in STX_INT_SYNC has occured and the
+ *   TX datapath is disabled.  It is recommended that the OVRBST, DATOVR,
+ *   NOSYNC, and FRMERR error conditions all have their bits set in the
+ *   STX_INT_SYNC register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_int_reg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t syncerr                 : 1;       /**< Interface encountered a fatal error */
+        uint64_t frmerr                  : 1;       /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
+        uint64_t unxfrm                  : 1;       /**< Unexpected framing sequence */
+        uint64_t nosync                  : 1;       /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
+        uint64_t diperr                  : 1;       /**< DIP2 error on the Spi4 Status channel */
+        uint64_t datovr                  : 1;       /**< Spi4 FIFO overflow error */
+        uint64_t ovrbst                  : 1;       /**< Transmit packet burst too big */
+        uint64_t calpar1                 : 1;       /**< STX Calendar Table Parity Error Bank1 */
+        uint64_t calpar0                 : 1;       /**< STX Calendar Table Parity Error Bank0 */
+#else
+        uint64_t calpar0                 : 1;
+        uint64_t calpar1                 : 1;
+        uint64_t ovrbst                  : 1;
+        uint64_t datovr                  : 1;
+        uint64_t diperr                  : 1;
+        uint64_t nosync                  : 1;
+        uint64_t unxfrm                  : 1;
+        uint64_t frmerr                  : 1;
+        uint64_t syncerr                 : 1;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_stxx_int_reg_s           cn38xx;
+    struct cvmx_stxx_int_reg_s           cn38xxp2;
+    struct cvmx_stxx_int_reg_s           cn58xx;
+    struct cvmx_stxx_int_reg_s           cn58xxp1;
+} cvmx_stxx_int_reg_t;
+
+
+/**
+ * cvmx_stx#_int_sync
+ *
+ * Notes:
+ * If the bit is enabled, then the coresponding exception condition is flagged
+ * to be fatal.  In Spi4 mode, the exception condition will result in a loss
+ * of sync condition on the Spi4 interface and the datapath will send
+ * continuous traing sequences.
+ * 
+ * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and
+ * FRMERR errors as synchronization events.  Software is free to
+ * synchronize the bus on other conditions, but this is the minimum
+ * recommended set.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_int_sync_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_8_63           : 56;
+        uint64_t frmerr                  : 1;       /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
+        uint64_t unxfrm                  : 1;       /**< Unexpected framing sequence */
+        uint64_t nosync                  : 1;       /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
+        uint64_t diperr                  : 1;       /**< DIP2 error on the Spi4 Status channel */
+        uint64_t datovr                  : 1;       /**< Spi4 FIFO overflow error */
+        uint64_t ovrbst                  : 1;       /**< Transmit packet burst too big */
+        uint64_t calpar1                 : 1;       /**< STX Calendar Table Parity Error Bank1 */
+        uint64_t calpar0                 : 1;       /**< STX Calendar Table Parity Error Bank0 */
+#else
+        uint64_t calpar0                 : 1;
+        uint64_t calpar1                 : 1;
+        uint64_t ovrbst                  : 1;
+        uint64_t datovr                  : 1;
+        uint64_t diperr                  : 1;
+        uint64_t nosync                  : 1;
+        uint64_t unxfrm                  : 1;
+        uint64_t frmerr                  : 1;
+        uint64_t reserved_8_63           : 56;
+#endif
+    } s;
+    struct cvmx_stxx_int_sync_s          cn38xx;
+    struct cvmx_stxx_int_sync_s          cn38xxp2;
+    struct cvmx_stxx_int_sync_s          cn58xx;
+    struct cvmx_stxx_int_sync_s          cn58xxp1;
+} cvmx_stxx_int_sync_t;
+
+
+/**
+ * cvmx_stx#_min_bst
+ *
+ * STX_MIN_BST - Min Burst to enforce when inserting training sequence
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_min_bst_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_9_63           : 55;
+        uint64_t minb                    : 9;       /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates
+                                                         the number of 8B blocks to send before inserting
+                                                         a training sequence.  Normally MINB will be set
+                                                         to GMX_TX_SPI_THRESH[THRESH].  MINB should always
+                                                         be set to an even number (ie. multiple of 16B) */
+#else
+        uint64_t minb                    : 9;
+        uint64_t reserved_9_63           : 55;
+#endif
+    } s;
+    struct cvmx_stxx_min_bst_s           cn38xx;
+    struct cvmx_stxx_min_bst_s           cn38xxp2;
+    struct cvmx_stxx_min_bst_s           cn58xx;
+    struct cvmx_stxx_min_bst_s           cn58xxp1;
+} cvmx_stxx_min_bst_t;
+
+
+/**
+ * cvmx_stx#_spi4_cal#
+ *
+ * specify the RSL base addresses for the block
+ * STX_SPI4_CAL - Spi4 Calender table
+ * direct_calendar_write / direct_calendar_read
+ *
+ * Notes:
+ * There are 32 calendar table CSR's, each containing 4 entries for a
+ *     total of 128 entries.  In the above definition...
+ * 
+ *           n = calendar table offset * 4
+ * 
+ *        Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
+ *        (with n == 0).  Offset 0x10 is the 16th entry in the calendar table
+ *        and would contain entries (16*4) = 64, 65, 66, and 67.
+ * 
+ * Restrictions:
+ *        Calendar table entry accesses (read or write) can only occur
+ *        if the interface is disabled.  All other accesses will be
+ *        unpredictable.
+ * 
+ *     Both the calendar table and the LEN and M parameters must be
+ *     completely setup before writing the Interface enable (INF_EN) and
+ *     Status channel enabled (ST_EN) asserted.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_spi4_calx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t oddpar                  : 1;       /**< Odd parity over STX_SPI4_CAL[15:0]
+                                                         (^STX_SPI4_CAL[16:0] === 1'b1)                  |   $NS       NS */
+        uint64_t prt3                    : 4;       /**< Status for port n+3 */
+        uint64_t prt2                    : 4;       /**< Status for port n+2 */
+        uint64_t prt1                    : 4;       /**< Status for port n+1 */
+        uint64_t prt0                    : 4;       /**< Status for port n+0 */
+#else
+        uint64_t prt0                    : 4;
+        uint64_t prt1                    : 4;
+        uint64_t prt2                    : 4;
+        uint64_t prt3                    : 4;
+        uint64_t oddpar                  : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_stxx_spi4_calx_s         cn38xx;
+    struct cvmx_stxx_spi4_calx_s         cn38xxp2;
+    struct cvmx_stxx_spi4_calx_s         cn58xx;
+    struct cvmx_stxx_spi4_calx_s         cn58xxp1;
+} cvmx_stxx_spi4_calx_t;
+
+
+/**
+ * cvmx_stx#_spi4_dat
+ *
+ * STX_SPI4_DAT - Spi4 datapath channel control register
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * * DATA_MAX_T must be in MOD 4 cycles
+ * 
+ * * DATA_MAX_T must at least 0x20
+ * 
+ * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce
+ * 
+ * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall
+ *   waiting for min bursts to complete.  In the worst case, this will
+ *   add the entire min burst transmission time to the interval between
+ *   trainging sequence.  The observed MAX_T on the Spi4 bus will be...
+ * 
+ *                STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4)
+ * 
+ *      If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
+ *      parameter will have to be adjusted.  Please see the
+ *      STX_SPI4_DAT[MAX_T] section for additional information.  In
+ *      addition, the min_burst can only be guaranteed on the initial data
+ *      burst of a given packet (i.e. the first data burst which contains
+ *      the SOP tick).  All subsequent bursts could be truncated by training
+ *      sequences at any point during transmission and could be arbitrarily
+ *      small.  This mode is only for use in Spi4 mode.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_spi4_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t alpha                   : 16;      /**< alpha (from spi4.2 spec) */
+        uint64_t max_t                   : 16;      /**< DATA_MAX_T (from spi4.2 spec) */
+#else
+        uint64_t max_t                   : 16;
+        uint64_t alpha                   : 16;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_stxx_spi4_dat_s          cn38xx;
+    struct cvmx_stxx_spi4_dat_s          cn38xxp2;
+    struct cvmx_stxx_spi4_dat_s          cn58xx;
+    struct cvmx_stxx_spi4_dat_s          cn58xxp1;
+} cvmx_stxx_spi4_dat_t;
+
+
+/**
+ * cvmx_stx#_spi4_stat
+ *
+ * STX_SPI4_STAT - Spi4 status channel control register
+ *
+ *
+ * Notes:
+ * Restrictions:
+ * Both the calendar table and the LEN and M parameters must be
+ * completely setup before writing the Interface enable (INF_EN) and
+ * Status channel enabled (ST_EN) asserted.
+ * 
+ * The calendar table will only be enabled when LEN > 0.
+ * 
+ * Current rev will only support LVTTL status IO.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_spi4_stat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t m                       : 8;       /**< CALENDAR_M (from spi4.2 spec) */
+        uint64_t reserved_7_7            : 1;
+        uint64_t len                     : 7;       /**< CALENDAR_LEN (from spi4.2 spec) */
+#else
+        uint64_t len                     : 7;
+        uint64_t reserved_7_7            : 1;
+        uint64_t m                       : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_stxx_spi4_stat_s         cn38xx;
+    struct cvmx_stxx_spi4_stat_s         cn38xxp2;
+    struct cvmx_stxx_spi4_stat_s         cn58xx;
+    struct cvmx_stxx_spi4_stat_s         cn58xxp1;
+} cvmx_stxx_spi4_stat_t;
+
+
+/**
+ * cvmx_stx#_stat_bytes_hi
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_stat_bytes_hi_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Number of bytes sent (CNT[63:32]) */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_stxx_stat_bytes_hi_s     cn38xx;
+    struct cvmx_stxx_stat_bytes_hi_s     cn38xxp2;
+    struct cvmx_stxx_stat_bytes_hi_s     cn58xx;
+    struct cvmx_stxx_stat_bytes_hi_s     cn58xxp1;
+} cvmx_stxx_stat_bytes_hi_t;
+
+
+/**
+ * cvmx_stx#_stat_bytes_lo
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_stat_bytes_lo_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Number of bytes sent (CNT[31:0]) */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_stxx_stat_bytes_lo_s     cn38xx;
+    struct cvmx_stxx_stat_bytes_lo_s     cn38xxp2;
+    struct cvmx_stxx_stat_bytes_lo_s     cn58xx;
+    struct cvmx_stxx_stat_bytes_lo_s     cn58xxp1;
+} cvmx_stxx_stat_bytes_lo_t;
+
+
+/**
+ * cvmx_stx#_stat_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_stat_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_5_63           : 59;
+        uint64_t clr                     : 1;       /**< Clear all statistics counters
+                                                         - STX_STAT_PKT_XMT
+                                                         - STX_STAT_BYTES_HI
+                                                         - STX_STAT_BYTES_LO */
+        uint64_t bckprs                  : 4;       /**< The selected port for STX_BCKPRS_CNT */
+#else
+        uint64_t bckprs                  : 4;
+        uint64_t clr                     : 1;
+        uint64_t reserved_5_63           : 59;
+#endif
+    } s;
+    struct cvmx_stxx_stat_ctl_s          cn38xx;
+    struct cvmx_stxx_stat_ctl_s          cn38xxp2;
+    struct cvmx_stxx_stat_ctl_s          cn58xx;
+    struct cvmx_stxx_stat_ctl_s          cn58xxp1;
+} cvmx_stxx_stat_ctl_t;
+
+
+/**
+ * cvmx_stx#_stat_pkt_xmt
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_stxx_stat_pkt_xmt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t cnt                     : 32;      /**< Number of packets sent */
+#else
+        uint64_t cnt                     : 32;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_stxx_stat_pkt_xmt_s      cn38xx;
+    struct cvmx_stxx_stat_pkt_xmt_s      cn38xxp2;
+    struct cvmx_stxx_stat_pkt_xmt_s      cn58xx;
+    struct cvmx_stxx_stat_pkt_xmt_s      cn58xxp1;
+} cvmx_stxx_stat_pkt_xmt_t;
+
+
+/**
+ * cvmx_tim_mem_debug0
+ *
+ * Notes:
+ * Internal per-ring state intended for debug use only - tim.ctl[47:0]
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_mem_debug0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t ena                     : 1;       /**< Ring timer enable */
+        uint64_t reserved_46_46          : 1;
+        uint64_t count                   : 22;      /**< Time offset for the ring
+                                                         Set to INTERVAL and counts down by 1 every 1024
+                                                         cycles when ENA==1. The HW forces a bucket
+                                                         traversal (and resets COUNT to INTERVAL) whenever
+                                                         the decrement would cause COUNT to go negative.
+                                                         COUNT is unpredictable whenever ENA==0.
+                                                         COUNT is reset to INTERVAL whenever TIM_MEM_RING1
+                                                         is written for the ring. */
+        uint64_t reserved_22_23          : 2;
+        uint64_t interval                : 22;      /**< Timer interval - 1 */
+#else
+        uint64_t interval                : 22;
+        uint64_t reserved_22_23          : 2;
+        uint64_t count                   : 22;
+        uint64_t reserved_46_46          : 1;
+        uint64_t ena                     : 1;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_tim_mem_debug0_s         cn30xx;
+    struct cvmx_tim_mem_debug0_s         cn31xx;
+    struct cvmx_tim_mem_debug0_s         cn38xx;
+    struct cvmx_tim_mem_debug0_s         cn38xxp2;
+    struct cvmx_tim_mem_debug0_s         cn50xx;
+    struct cvmx_tim_mem_debug0_s         cn52xx;
+    struct cvmx_tim_mem_debug0_s         cn52xxp1;
+    struct cvmx_tim_mem_debug0_s         cn56xx;
+    struct cvmx_tim_mem_debug0_s         cn56xxp1;
+    struct cvmx_tim_mem_debug0_s         cn58xx;
+    struct cvmx_tim_mem_debug0_s         cn58xxp1;
+} cvmx_tim_mem_debug0_t;
+
+
+/**
+ * cvmx_tim_mem_debug1
+ *
+ * Notes:
+ * Internal per-ring state intended for debug use only - tim.sta[63:0]
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_mem_debug1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t bucket                  : 13;      /**< Current bucket[12:0]
+                                                         Reset to 0 whenever TIM_MEM_RING0 is written for
+                                                         the ring. Incremented (modulo BSIZE) once per
+                                                         bucket traversal.
+                                                         See TIM_MEM_DEBUG2[BUCKET]. */
+        uint64_t base                    : 31;      /**< Pointer[35:5] to bucket[0] */
+        uint64_t bsize                   : 20;      /**< Number of buckets - 1 */
+#else
+        uint64_t bsize                   : 20;
+        uint64_t base                    : 31;
+        uint64_t bucket                  : 13;
+#endif
+    } s;
+    struct cvmx_tim_mem_debug1_s         cn30xx;
+    struct cvmx_tim_mem_debug1_s         cn31xx;
+    struct cvmx_tim_mem_debug1_s         cn38xx;
+    struct cvmx_tim_mem_debug1_s         cn38xxp2;
+    struct cvmx_tim_mem_debug1_s         cn50xx;
+    struct cvmx_tim_mem_debug1_s         cn52xx;
+    struct cvmx_tim_mem_debug1_s         cn52xxp1;
+    struct cvmx_tim_mem_debug1_s         cn56xx;
+    struct cvmx_tim_mem_debug1_s         cn56xxp1;
+    struct cvmx_tim_mem_debug1_s         cn58xx;
+    struct cvmx_tim_mem_debug1_s         cn58xxp1;
+} cvmx_tim_mem_debug1_t;
+
+
+/**
+ * cvmx_tim_mem_debug2
+ *
+ * Notes:
+ * Internal per-ring state intended for debug use only - tim.sta[95:64]
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_mem_debug2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_24_63          : 40;
+        uint64_t cpool                   : 3;       /**< Free list used to free chunks */
+        uint64_t csize                   : 13;      /**< Number of words per chunk */
+        uint64_t reserved_7_7            : 1;
+        uint64_t bucket                  : 7;       /**< Current bucket[19:13]
+                                                         See TIM_MEM_DEBUG1[BUCKET]. */
+#else
+        uint64_t bucket                  : 7;
+        uint64_t reserved_7_7            : 1;
+        uint64_t csize                   : 13;
+        uint64_t cpool                   : 3;
+        uint64_t reserved_24_63          : 40;
+#endif
+    } s;
+    struct cvmx_tim_mem_debug2_s         cn30xx;
+    struct cvmx_tim_mem_debug2_s         cn31xx;
+    struct cvmx_tim_mem_debug2_s         cn38xx;
+    struct cvmx_tim_mem_debug2_s         cn38xxp2;
+    struct cvmx_tim_mem_debug2_s         cn50xx;
+    struct cvmx_tim_mem_debug2_s         cn52xx;
+    struct cvmx_tim_mem_debug2_s         cn52xxp1;
+    struct cvmx_tim_mem_debug2_s         cn56xx;
+    struct cvmx_tim_mem_debug2_s         cn56xxp1;
+    struct cvmx_tim_mem_debug2_s         cn58xx;
+    struct cvmx_tim_mem_debug2_s         cn58xxp1;
+} cvmx_tim_mem_debug2_t;
+
+
+/**
+ * cvmx_tim_mem_ring0
+ *
+ * Notes:
+ * TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring.
+ * Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is
+ * readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].)
+ * BASE is a 32-byte aligned pointer[35:0].  Only pointer[35:5] are stored because pointer[4:0] = 0.
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_mem_ring0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_55_63          : 9;
+        uint64_t first_bucket            : 31;      /**< Pointer[35:5] to bucket[0] */
+        uint64_t num_buckets             : 20;      /**< Number of buckets - 1 */
+        uint64_t ring                    : 4;       /**< Ring ID */
+#else
+        uint64_t ring                    : 4;
+        uint64_t num_buckets             : 20;
+        uint64_t first_bucket            : 31;
+        uint64_t reserved_55_63          : 9;
+#endif
+    } s;
+    struct cvmx_tim_mem_ring0_s          cn30xx;
+    struct cvmx_tim_mem_ring0_s          cn31xx;
+    struct cvmx_tim_mem_ring0_s          cn38xx;
+    struct cvmx_tim_mem_ring0_s          cn38xxp2;
+    struct cvmx_tim_mem_ring0_s          cn50xx;
+    struct cvmx_tim_mem_ring0_s          cn52xx;
+    struct cvmx_tim_mem_ring0_s          cn52xxp1;
+    struct cvmx_tim_mem_ring0_s          cn56xx;
+    struct cvmx_tim_mem_ring0_s          cn56xxp1;
+    struct cvmx_tim_mem_ring0_s          cn58xx;
+    struct cvmx_tim_mem_ring0_s          cn58xxp1;
+} cvmx_tim_mem_ring0_t;
+
+
+/**
+ * cvmx_tim_mem_ring1
+ *
+ * Notes:
+ * After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring
+ * if it was pending or active prior to the transition. (SW must delay to ensure the completion
+ * of the traversal before reprogramming the ring.)
+ * Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value.
+ * (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].)
+ * CSIZE must be at least 16.  It is illegal to program CSIZE to a value that is less than 16.
+ * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any
+ * CSR read operations to this address can be performed.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_mem_ring1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_43_63          : 21;
+        uint64_t enable                  : 1;       /**< Ring timer enable
+                                                         When clear, the ring is disabled and TIM
+                                                         will not traverse any new buckets for the ring. */
+        uint64_t pool                    : 3;       /**< Free list used to free chunks */
+        uint64_t words_per_chunk         : 13;      /**< Number of words per chunk */
+        uint64_t interval                : 22;      /**< Timer interval - 1, measured in 1024 cycle ticks */
+        uint64_t ring                    : 4;       /**< Ring ID */
+#else
+        uint64_t ring                    : 4;
+        uint64_t interval                : 22;
+        uint64_t words_per_chunk         : 13;
+        uint64_t pool                    : 3;
+        uint64_t enable                  : 1;
+        uint64_t reserved_43_63          : 21;
+#endif
+    } s;
+    struct cvmx_tim_mem_ring1_s          cn30xx;
+    struct cvmx_tim_mem_ring1_s          cn31xx;
+    struct cvmx_tim_mem_ring1_s          cn38xx;
+    struct cvmx_tim_mem_ring1_s          cn38xxp2;
+    struct cvmx_tim_mem_ring1_s          cn50xx;
+    struct cvmx_tim_mem_ring1_s          cn52xx;
+    struct cvmx_tim_mem_ring1_s          cn52xxp1;
+    struct cvmx_tim_mem_ring1_s          cn56xx;
+    struct cvmx_tim_mem_ring1_s          cn56xxp1;
+    struct cvmx_tim_mem_ring1_s          cn58xx;
+    struct cvmx_tim_mem_ring1_s          cn58xxp1;
+} cvmx_tim_mem_ring1_t;
+
+
+/**
+ * cvmx_tim_reg_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_reg_bist_result_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t sta                     : 2;       /**< BiST result of the STA   memories (0=pass, !0=fail) */
+        uint64_t ncb                     : 1;       /**< BiST result of the NCB   memories (0=pass, !0=fail) */
+        uint64_t ctl                     : 1;       /**< BiST result of the CTL   memories (0=pass, !0=fail) */
+#else
+        uint64_t ctl                     : 1;
+        uint64_t ncb                     : 1;
+        uint64_t sta                     : 2;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_tim_reg_bist_result_s    cn30xx;
+    struct cvmx_tim_reg_bist_result_s    cn31xx;
+    struct cvmx_tim_reg_bist_result_s    cn38xx;
+    struct cvmx_tim_reg_bist_result_s    cn38xxp2;
+    struct cvmx_tim_reg_bist_result_s    cn50xx;
+    struct cvmx_tim_reg_bist_result_s    cn52xx;
+    struct cvmx_tim_reg_bist_result_s    cn52xxp1;
+    struct cvmx_tim_reg_bist_result_s    cn56xx;
+    struct cvmx_tim_reg_bist_result_s    cn56xxp1;
+    struct cvmx_tim_reg_bist_result_s    cn58xx;
+    struct cvmx_tim_reg_bist_result_s    cn58xxp1;
+} cvmx_tim_reg_bist_result_t;
+
+
+/**
+ * cvmx_tim_reg_error
+ *
+ * Notes:
+ * A ring is in error if its interval has elapsed more than once without having been serviced.
+ * During a CSR write to this register, the write data is used as a mask to clear the selected mask
+ * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_reg_error_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mask                    : 16;      /**< Bit mask indicating the rings in error */
+#else
+        uint64_t mask                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_tim_reg_error_s          cn30xx;
+    struct cvmx_tim_reg_error_s          cn31xx;
+    struct cvmx_tim_reg_error_s          cn38xx;
+    struct cvmx_tim_reg_error_s          cn38xxp2;
+    struct cvmx_tim_reg_error_s          cn50xx;
+    struct cvmx_tim_reg_error_s          cn52xx;
+    struct cvmx_tim_reg_error_s          cn52xxp1;
+    struct cvmx_tim_reg_error_s          cn56xx;
+    struct cvmx_tim_reg_error_s          cn56xxp1;
+    struct cvmx_tim_reg_error_s          cn58xx;
+    struct cvmx_tim_reg_error_s          cn58xxp1;
+} cvmx_tim_reg_error_t;
+
+
+/**
+ * cvmx_tim_reg_flags
+ *
+ * Notes:
+ * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all
+ * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.)
+ * When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there
+ * are no more new bucket traversals (for any ring).
+ * 
+ * If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may
+ * have been previous ones. If there are ring bucket traversals that were already pending but
+ * not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet)
+ * during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until
+ * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete
+ * after the 1->0 ENA_TIM transition, though.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_reg_flags_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t reset                   : 1;       /**< Reset oneshot pulse for free-running structures */
+        uint64_t enable_dwb              : 1;       /**< Enables non-zero DonwWriteBacks when set
+                                                         When set, enables the use of
+                                                         DontWriteBacks during the buffer freeing
+                                                         operations. */
+        uint64_t enable_timers           : 1;       /**< Enables the TIM section when set
+                                                         When set, TIM is in normal operation.
+                                                         When clear, time is effectively stopped for all
+                                                         rings in TIM. */
+#else
+        uint64_t enable_timers           : 1;
+        uint64_t enable_dwb              : 1;
+        uint64_t reset                   : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_tim_reg_flags_s          cn30xx;
+    struct cvmx_tim_reg_flags_s          cn31xx;
+    struct cvmx_tim_reg_flags_s          cn38xx;
+    struct cvmx_tim_reg_flags_s          cn38xxp2;
+    struct cvmx_tim_reg_flags_s          cn50xx;
+    struct cvmx_tim_reg_flags_s          cn52xx;
+    struct cvmx_tim_reg_flags_s          cn52xxp1;
+    struct cvmx_tim_reg_flags_s          cn56xx;
+    struct cvmx_tim_reg_flags_s          cn56xxp1;
+    struct cvmx_tim_reg_flags_s          cn58xx;
+    struct cvmx_tim_reg_flags_s          cn58xxp1;
+} cvmx_tim_reg_flags_t;
+
+
+/**
+ * cvmx_tim_reg_int_mask
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ * When mask bit is set, the interrupt is enabled.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_reg_int_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t mask                    : 16;      /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */
+#else
+        uint64_t mask                    : 16;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_tim_reg_int_mask_s       cn30xx;
+    struct cvmx_tim_reg_int_mask_s       cn31xx;
+    struct cvmx_tim_reg_int_mask_s       cn38xx;
+    struct cvmx_tim_reg_int_mask_s       cn38xxp2;
+    struct cvmx_tim_reg_int_mask_s       cn50xx;
+    struct cvmx_tim_reg_int_mask_s       cn52xx;
+    struct cvmx_tim_reg_int_mask_s       cn52xxp1;
+    struct cvmx_tim_reg_int_mask_s       cn56xx;
+    struct cvmx_tim_reg_int_mask_s       cn56xxp1;
+    struct cvmx_tim_reg_int_mask_s       cn58xx;
+    struct cvmx_tim_reg_int_mask_s       cn58xxp1;
+} cvmx_tim_reg_int_mask_t;
+
+
+/**
+ * cvmx_tim_reg_read_idx
+ *
+ * Notes:
+ * Provides the read index during a CSR read operation to any of the CSRs that are physically stored
+ * as memories.  The names of these CSRs begin with the prefix "TIM_MEM_".
+ * IDX[7:0] is the read index.  INC[7:0] is an increment that is added to IDX[7:0] after any CSR read.
+ * The intended use is to initially write this CSR such that IDX=0 and INC=1.  Then, the entire
+ * contents of a CSR memory can be read with consecutive CSR read commands.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tim_reg_read_idx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t inc                     : 8;       /**< Increment to add to current index for next index */
+        uint64_t index                   : 8;       /**< Index to use for next memory CSR read */
+#else
+        uint64_t index                   : 8;
+        uint64_t inc                     : 8;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } s;
+    struct cvmx_tim_reg_read_idx_s       cn30xx;
+    struct cvmx_tim_reg_read_idx_s       cn31xx;
+    struct cvmx_tim_reg_read_idx_s       cn38xx;
+    struct cvmx_tim_reg_read_idx_s       cn38xxp2;
+    struct cvmx_tim_reg_read_idx_s       cn50xx;
+    struct cvmx_tim_reg_read_idx_s       cn52xx;
+    struct cvmx_tim_reg_read_idx_s       cn52xxp1;
+    struct cvmx_tim_reg_read_idx_s       cn56xx;
+    struct cvmx_tim_reg_read_idx_s       cn56xxp1;
+    struct cvmx_tim_reg_read_idx_s       cn58xx;
+    struct cvmx_tim_reg_read_idx_s       cn58xxp1;
+} cvmx_tim_reg_read_idx_t;
+
+
+/**
+ * cvmx_tra_bist_status
+ *
+ * TRA_BIST_STATUS = Trace Buffer BiST Status
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t tcf                     : 1;       /**< Bist Results for TCF memory
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t tdf1                    : 1;       /**< Bist Results for TDF memory 1
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+        uint64_t tdf0                    : 1;       /**< Bist Results for TCF memory 0
+                                                         - 0: GOOD (or bist in progress/never run)
+                                                         - 1: BAD */
+#else
+        uint64_t tdf0                    : 1;
+        uint64_t tdf1                    : 1;
+        uint64_t tcf                     : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } s;
+    struct cvmx_tra_bist_status_s        cn31xx;
+    struct cvmx_tra_bist_status_s        cn38xx;
+    struct cvmx_tra_bist_status_s        cn38xxp2;
+    struct cvmx_tra_bist_status_s        cn52xx;
+    struct cvmx_tra_bist_status_s        cn52xxp1;
+    struct cvmx_tra_bist_status_s        cn56xx;
+    struct cvmx_tra_bist_status_s        cn56xxp1;
+    struct cvmx_tra_bist_status_s        cn58xx;
+    struct cvmx_tra_bist_status_s        cn58xxp1;
+} cvmx_tra_bist_status_t;
+
+
+/**
+ * cvmx_tra_ctl
+ *
+ * TRA_CTL = Trace Buffer Control
+ * 
+ * Description:
+ *
+ * Notes:
+ * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1).
+ * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_15_63          : 49;
+        uint64_t ignore_o                : 1;       /**< Ignore overflow during wrap mode
+                                                         If set and wrapping mode is enabled, then tracing
+                                                         will not stop at the overflow condition.  Each
+                                                         write during an overflow will overwrite the
+                                                         oldest, unread entry and the read pointer is
+                                                         incremented by one entry.  This bit has no effect
+                                                         if WRAP=0. */
+        uint64_t mcd0_ena                : 1;       /**< MCD0 enable
+                                                         If set and any PP sends the MCD0 signal, the
+                                                         tracing is disabled. */
+        uint64_t mcd0_thr                : 1;       /**< MCD0_threshold
+                                                         At a fill threshold event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_THR == 1). */
+        uint64_t mcd0_trg                : 1;       /**< MCD0_trigger
+                                                         At an end trigger event, sends an MCD0
+                                                         wire pulse that can cause cores to enter debug
+                                                         mode, if enabled.  This MCD0 wire pulse will not
+                                                         occur while (TRA_INT_STATUS.MCD0_TRG == 1). */
+        uint64_t ciu_thr                 : 1;       /**< CIU_threshold
+                                                         When set during a fill threshold event,
+                                                         TRA_INT_STATUS[CIU_THR] is set, which can cause
+                                                         core interrupts, if enabled. */
+        uint64_t ciu_trg                 : 1;       /**< CIU_trigger
+                                                         When set during an end trigger event,
+                                                         TRA_INT_STATUS[CIU_TRG] is set, which can cause
+                                                         core interrupts, if enabled. */
+        uint64_t full_thr                : 2;       /**< Full Threshhold
+                                                         0=none
+                                                         1=1/2 full
+                                                         2=3/4 full
+                                                         3=4/4 full */
+        uint64_t time_grn                : 3;       /**< Timestamp granularity
+                                                         granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */
+        uint64_t trig_ctl                : 2;       /**< Trigger Control
+                                                         Note: trigger events are written to the trace
+                                                         0=no triggers
+                                                         1=trigger0=start trigger, trigger1=stop trigger
+                                                         2=(trigger0 || trigger1)=start trigger
+                                                         3=(trigger0 || trigger1)=stop trigger */
+        uint64_t wrap                    : 1;       /**< Wrap mode
+                                                         When WRAP=0, the trace buffer will disable itself
+                                                         after having logged 1024 entries.  When WRAP=1,
+                                                         the trace buffer will never disable itself.
+                                                         In this case, tracing may or may not be
+                                                         temporarily suspended during the overflow
+                                                         condition (see IGNORE_O above).
+                                                         0=do not wrap
+                                                         1=wrap */
+        uint64_t ena                     : 1;       /**< Enable Trace
+                                                         Master enable.  Tracing only happens when ENA=1.
+                                                         When ENA changes from 0 to 1, the read and write
+                                                         pointers are reset to 0x00 to begin a new trace.
+                                                         The MCD0 event may set ENA=0 (see MCD0_ENA
+                                                         above).  When using triggers, tracing occurs only
+                                                         between start and stop triggers (including the
+                                                         triggers themselves).
+                                                         0=disable
+                                                         1=enable */
+#else
+        uint64_t ena                     : 1;
+        uint64_t wrap                    : 1;
+        uint64_t trig_ctl                : 2;
+        uint64_t time_grn                : 3;
+        uint64_t full_thr                : 2;
+        uint64_t ciu_trg                 : 1;
+        uint64_t ciu_thr                 : 1;
+        uint64_t mcd0_trg                : 1;
+        uint64_t mcd0_thr                : 1;
+        uint64_t mcd0_ena                : 1;
+        uint64_t ignore_o                : 1;
+        uint64_t reserved_15_63          : 49;
+#endif
+    } s;
+    struct cvmx_tra_ctl_s                cn31xx;
+    struct cvmx_tra_ctl_s                cn38xx;
+    struct cvmx_tra_ctl_s                cn38xxp2;
+    struct cvmx_tra_ctl_s                cn52xx;
+    struct cvmx_tra_ctl_s                cn52xxp1;
+    struct cvmx_tra_ctl_s                cn56xx;
+    struct cvmx_tra_ctl_s                cn56xxp1;
+    struct cvmx_tra_ctl_s                cn58xx;
+    struct cvmx_tra_ctl_s                cn58xxp1;
+} cvmx_tra_ctl_t;
+
+
+/**
+ * cvmx_tra_cycles_since
+ *
+ * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers
+ * 
+ * Description:
+ *
+ * Notes:
+ * This CSR is obsolete.  Use TRA_CYCLES_SINCE1 instead.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_cycles_since_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t cycles                  : 48;      /**< Cycles since the last entry was written */
+        uint64_t rptr                    : 8;       /**< Read pointer */
+        uint64_t wptr                    : 8;       /**< Write pointer */
+#else
+        uint64_t wptr                    : 8;
+        uint64_t rptr                    : 8;
+        uint64_t cycles                  : 48;
+#endif
+    } s;
+    struct cvmx_tra_cycles_since_s       cn31xx;
+    struct cvmx_tra_cycles_since_s       cn38xx;
+    struct cvmx_tra_cycles_since_s       cn38xxp2;
+    struct cvmx_tra_cycles_since_s       cn52xx;
+    struct cvmx_tra_cycles_since_s       cn52xxp1;
+    struct cvmx_tra_cycles_since_s       cn56xx;
+    struct cvmx_tra_cycles_since_s       cn56xxp1;
+    struct cvmx_tra_cycles_since_s       cn58xx;
+    struct cvmx_tra_cycles_since_s       cn58xxp1;
+} cvmx_tra_cycles_since_t;
+
+
+/**
+ * cvmx_tra_cycles_since1
+ *
+ * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_cycles_since1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t cycles                  : 40;      /**< Cycles since the last entry was written */
+        uint64_t reserved_22_23          : 2;
+        uint64_t rptr                    : 10;      /**< Read pointer */
+        uint64_t reserved_10_11          : 2;
+        uint64_t wptr                    : 10;      /**< Write pointer */
+#else
+        uint64_t wptr                    : 10;
+        uint64_t reserved_10_11          : 2;
+        uint64_t rptr                    : 10;
+        uint64_t reserved_22_23          : 2;
+        uint64_t cycles                  : 40;
+#endif
+    } s;
+    struct cvmx_tra_cycles_since1_s      cn52xx;
+    struct cvmx_tra_cycles_since1_s      cn52xxp1;
+    struct cvmx_tra_cycles_since1_s      cn56xx;
+    struct cvmx_tra_cycles_since1_s      cn56xxp1;
+    struct cvmx_tra_cycles_since1_s      cn58xx;
+    struct cvmx_tra_cycles_since1_s      cn58xxp1;
+} cvmx_tra_cycles_since1_t;
+
+
+/**
+ * cvmx_tra_filt_adr_adr
+ *
+ * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_filt_adr_adr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t adr                     : 36;      /**< Unmasked Address
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+        uint64_t adr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_tra_filt_adr_adr_s       cn31xx;
+    struct cvmx_tra_filt_adr_adr_s       cn38xx;
+    struct cvmx_tra_filt_adr_adr_s       cn38xxp2;
+    struct cvmx_tra_filt_adr_adr_s       cn52xx;
+    struct cvmx_tra_filt_adr_adr_s       cn52xxp1;
+    struct cvmx_tra_filt_adr_adr_s       cn56xx;
+    struct cvmx_tra_filt_adr_adr_s       cn56xxp1;
+    struct cvmx_tra_filt_adr_adr_s       cn58xx;
+    struct cvmx_tra_filt_adr_adr_s       cn58xxp1;
+} cvmx_tra_filt_adr_adr_t;
+
+
+/**
+ * cvmx_tra_filt_adr_msk
+ *
+ * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_filt_adr_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t adr                     : 36;      /**< Address Mask
+                                                         The combination of TRA_FILT_ADR_ADR and
+                                                         TRA_FILT_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_FILT_CMD[IOBDMA]
+                                                         is set, TRA_FILT_ADR_MSK must be zero to
+                                                         guarantee that any IOBDMAs enter the trace. */
+#else
+        uint64_t adr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_tra_filt_adr_msk_s       cn31xx;
+    struct cvmx_tra_filt_adr_msk_s       cn38xx;
+    struct cvmx_tra_filt_adr_msk_s       cn38xxp2;
+    struct cvmx_tra_filt_adr_msk_s       cn52xx;
+    struct cvmx_tra_filt_adr_msk_s       cn52xxp1;
+    struct cvmx_tra_filt_adr_msk_s       cn56xx;
+    struct cvmx_tra_filt_adr_msk_s       cn56xxp1;
+    struct cvmx_tra_filt_adr_msk_s       cn58xx;
+    struct cvmx_tra_filt_adr_msk_s       cn58xxp1;
+} cvmx_tra_filt_adr_msk_t;
+
+
+/**
+ * cvmx_tra_filt_cmd
+ *
+ * TRA_FILT_CMD = Trace Buffer Filter Command Mask
+ * 
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * enter the trace.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_filt_cmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t saa                     : 1;       /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+        uint64_t stt                     : 1;       /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stp                     : 1;       /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stc                     : 1;       /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stf                     : 1;       /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+        uint64_t dwb                     : 1;
+        uint64_t pl2                     : 1;
+        uint64_t psl1                    : 1;
+        uint64_t ldd                     : 1;
+        uint64_t ldi                     : 1;
+        uint64_t ldt                     : 1;
+        uint64_t stf                     : 1;
+        uint64_t stc                     : 1;
+        uint64_t stp                     : 1;
+        uint64_t stt                     : 1;
+        uint64_t iobld8                  : 1;
+        uint64_t iobld16                 : 1;
+        uint64_t iobld32                 : 1;
+        uint64_t iobld64                 : 1;
+        uint64_t iobst                   : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t saa                     : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_tra_filt_cmd_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+        uint64_t stt                     : 1;       /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stp                     : 1;       /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stc                     : 1;       /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stf                     : 1;       /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+        uint64_t dwb                     : 1;
+        uint64_t pl2                     : 1;
+        uint64_t psl1                    : 1;
+        uint64_t ldd                     : 1;
+        uint64_t ldi                     : 1;
+        uint64_t ldt                     : 1;
+        uint64_t stf                     : 1;
+        uint64_t stc                     : 1;
+        uint64_t stp                     : 1;
+        uint64_t stt                     : 1;
+        uint64_t iobld8                  : 1;
+        uint64_t iobld16                 : 1;
+        uint64_t iobld32                 : 1;
+        uint64_t iobld64                 : 1;
+        uint64_t iobst                   : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn31xx;
+    struct cvmx_tra_filt_cmd_cn31xx      cn38xx;
+    struct cvmx_tra_filt_cmd_cn31xx      cn38xxp2;
+    struct cvmx_tra_filt_cmd_s           cn52xx;
+    struct cvmx_tra_filt_cmd_s           cn52xxp1;
+    struct cvmx_tra_filt_cmd_s           cn56xx;
+    struct cvmx_tra_filt_cmd_s           cn56xxp1;
+    struct cvmx_tra_filt_cmd_s           cn58xx;
+    struct cvmx_tra_filt_cmd_s           cn58xxp1;
+} cvmx_tra_filt_cmd_t;
+
+
+/**
+ * cvmx_tra_filt_did
+ *
+ * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_filt_did_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t illegal                 : 19;      /**< Illegal destinations */
+        uint64_t pow                     : 1;       /**< Enable tracing of requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+        uint64_t illegal2                : 3;       /**< Illegal destinations */
+        uint64_t rng                     : 1;       /**< Enable tracing of requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+        uint64_t zip                     : 1;       /**< Enable tracing of requests to ZIP
+                                                         (doorbell stores are legal) */
+        uint64_t dfa                     : 1;       /**< Enable tracing of requests to DFA
+                                                         (CSR's and operations are legal) */
+        uint64_t fpa                     : 1;       /**< Enable tracing of requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+        uint64_t key                     : 1;       /**< Enable tracing of requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+        uint64_t pci                     : 1;       /**< Enable tracing of requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+        uint64_t illegal3                : 2;       /**< Illegal destinations */
+        uint64_t mio                     : 1;       /**< Enable tracing of CIU and GPIO CSR's */
+#else
+        uint64_t mio                     : 1;
+        uint64_t illegal3                : 2;
+        uint64_t pci                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t rng                     : 1;
+        uint64_t illegal2                : 3;
+        uint64_t pow                     : 1;
+        uint64_t illegal                 : 19;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_tra_filt_did_s           cn31xx;
+    struct cvmx_tra_filt_did_s           cn38xx;
+    struct cvmx_tra_filt_did_s           cn38xxp2;
+    struct cvmx_tra_filt_did_s           cn52xx;
+    struct cvmx_tra_filt_did_s           cn52xxp1;
+    struct cvmx_tra_filt_did_s           cn56xx;
+    struct cvmx_tra_filt_did_s           cn56xxp1;
+    struct cvmx_tra_filt_did_s           cn58xx;
+    struct cvmx_tra_filt_did_s           cn58xxp1;
+} cvmx_tra_filt_did_t;
+
+
+/**
+ * cvmx_tra_filt_sid
+ *
+ * TRA_FILT_SID = Trace Buffer Filter SourceId Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_filt_sid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t dwb                     : 1;       /**< Enable tracing of requests from the IOB DWB engine */
+        uint64_t iobreq                  : 1;       /**< Enable tracing of requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+        uint64_t pko                     : 1;       /**< Enable tracing of read requests from PKO */
+        uint64_t pki                     : 1;       /**< Enable tracing of write requests from PIP/IPD */
+        uint64_t pp                      : 16;      /**< Enable tracing from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+        uint64_t pp                      : 16;
+        uint64_t pki                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t iobreq                  : 1;
+        uint64_t dwb                     : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_tra_filt_sid_s           cn31xx;
+    struct cvmx_tra_filt_sid_s           cn38xx;
+    struct cvmx_tra_filt_sid_s           cn38xxp2;
+    struct cvmx_tra_filt_sid_s           cn52xx;
+    struct cvmx_tra_filt_sid_s           cn52xxp1;
+    struct cvmx_tra_filt_sid_s           cn56xx;
+    struct cvmx_tra_filt_sid_s           cn56xxp1;
+    struct cvmx_tra_filt_sid_s           cn58xx;
+    struct cvmx_tra_filt_sid_s           cn58xxp1;
+} cvmx_tra_filt_sid_t;
+
+
+/**
+ * cvmx_tra_int_status
+ *
+ * TRA_INT_STATUS = Trace Buffer Interrupt Status
+ * 
+ * Description:
+ *
+ * Notes:
+ * During a CSR write to this register, the write data is used as a mask to clear the selected status
+ * bits (status'[3:0] = status[3:0] & ~write_data[3:0]).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_int_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_4_63           : 60;
+        uint64_t mcd0_thr                : 1;       /**< MCD0 full threshold interrupt status
+                                                         0=trace buffer did not generate MCD0 wire pulse
+                                                         1=trace buffer did     generate MCD0 wire pulse
+                                                           and prevents additional MCD0_THR MCD0 wire pulses */
+        uint64_t mcd0_trg                : 1;       /**< MCD0 end trigger interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt
+                                                           and prevents additional MCD0_TRG MCD0 wire pulses */
+        uint64_t ciu_thr                 : 1;       /**< CIU full threshold interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt */
+        uint64_t ciu_trg                 : 1;       /**< CIU end trigger interrupt status
+                                                         0=trace buffer did not generate interrupt
+                                                         1=trace buffer did     generate interrupt */
+#else
+        uint64_t ciu_trg                 : 1;
+        uint64_t ciu_thr                 : 1;
+        uint64_t mcd0_trg                : 1;
+        uint64_t mcd0_thr                : 1;
+        uint64_t reserved_4_63           : 60;
+#endif
+    } s;
+    struct cvmx_tra_int_status_s         cn31xx;
+    struct cvmx_tra_int_status_s         cn38xx;
+    struct cvmx_tra_int_status_s         cn38xxp2;
+    struct cvmx_tra_int_status_s         cn52xx;
+    struct cvmx_tra_int_status_s         cn52xxp1;
+    struct cvmx_tra_int_status_s         cn56xx;
+    struct cvmx_tra_int_status_s         cn56xxp1;
+    struct cvmx_tra_int_status_s         cn58xx;
+    struct cvmx_tra_int_status_s         cn58xxp1;
+} cvmx_tra_int_status_t;
+
+
+/**
+ * cvmx_tra_read_dat
+ *
+ * TRA_READ_DAT = Trace Buffer Read Data
+ * 
+ * Description:
+ *
+ * Notes:
+ * This CSR is a memory of 1024 entries.  When the trace was enabled, the read pointer was set to entry
+ * 0 by hardware.  Each read to this address increments the read pointer.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_read_dat_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t data                    : 64;      /**< Trace buffer data for current entry */
+#else
+        uint64_t data                    : 64;
+#endif
+    } s;
+    struct cvmx_tra_read_dat_s           cn31xx;
+    struct cvmx_tra_read_dat_s           cn38xx;
+    struct cvmx_tra_read_dat_s           cn38xxp2;
+    struct cvmx_tra_read_dat_s           cn52xx;
+    struct cvmx_tra_read_dat_s           cn52xxp1;
+    struct cvmx_tra_read_dat_s           cn56xx;
+    struct cvmx_tra_read_dat_s           cn56xxp1;
+    struct cvmx_tra_read_dat_s           cn58xx;
+    struct cvmx_tra_read_dat_s           cn58xxp1;
+} cvmx_tra_read_dat_t;
+
+
+/**
+ * cvmx_tra_trig0_adr_adr
+ *
+ * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig0_adr_adr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t adr                     : 36;      /**< Unmasked Address
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+        uint64_t adr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_tra_trig0_adr_adr_s      cn31xx;
+    struct cvmx_tra_trig0_adr_adr_s      cn38xx;
+    struct cvmx_tra_trig0_adr_adr_s      cn38xxp2;
+    struct cvmx_tra_trig0_adr_adr_s      cn52xx;
+    struct cvmx_tra_trig0_adr_adr_s      cn52xxp1;
+    struct cvmx_tra_trig0_adr_adr_s      cn56xx;
+    struct cvmx_tra_trig0_adr_adr_s      cn56xxp1;
+    struct cvmx_tra_trig0_adr_adr_s      cn58xx;
+    struct cvmx_tra_trig0_adr_adr_s      cn58xxp1;
+} cvmx_tra_trig0_adr_adr_t;
+
+
+/**
+ * cvmx_tra_trig0_adr_msk
+ *
+ * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig0_adr_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t adr                     : 36;      /**< Address Mask
+                                                         The combination of TRA_TRIG0_ADR_ADR and
+                                                         TRA_TRIG0_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG0_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG0_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+        uint64_t adr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_tra_trig0_adr_msk_s      cn31xx;
+    struct cvmx_tra_trig0_adr_msk_s      cn38xx;
+    struct cvmx_tra_trig0_adr_msk_s      cn38xxp2;
+    struct cvmx_tra_trig0_adr_msk_s      cn52xx;
+    struct cvmx_tra_trig0_adr_msk_s      cn52xxp1;
+    struct cvmx_tra_trig0_adr_msk_s      cn56xx;
+    struct cvmx_tra_trig0_adr_msk_s      cn56xxp1;
+    struct cvmx_tra_trig0_adr_msk_s      cn58xx;
+    struct cvmx_tra_trig0_adr_msk_s      cn58xxp1;
+} cvmx_tra_trig0_adr_msk_t;
+
+
+/**
+ * cvmx_tra_trig0_cmd
+ *
+ * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask
+ * 
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * are recognized as triggers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig0_cmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t saa                     : 1;       /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+        uint64_t stt                     : 1;       /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stp                     : 1;       /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stc                     : 1;       /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stf                     : 1;       /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+        uint64_t dwb                     : 1;
+        uint64_t pl2                     : 1;
+        uint64_t psl1                    : 1;
+        uint64_t ldd                     : 1;
+        uint64_t ldi                     : 1;
+        uint64_t ldt                     : 1;
+        uint64_t stf                     : 1;
+        uint64_t stc                     : 1;
+        uint64_t stp                     : 1;
+        uint64_t stt                     : 1;
+        uint64_t iobld8                  : 1;
+        uint64_t iobld16                 : 1;
+        uint64_t iobld32                 : 1;
+        uint64_t iobld64                 : 1;
+        uint64_t iobst                   : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t saa                     : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_tra_trig0_cmd_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+        uint64_t stt                     : 1;       /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stp                     : 1;       /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stc                     : 1;       /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stf                     : 1;       /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+        uint64_t dwb                     : 1;
+        uint64_t pl2                     : 1;
+        uint64_t psl1                    : 1;
+        uint64_t ldd                     : 1;
+        uint64_t ldi                     : 1;
+        uint64_t ldt                     : 1;
+        uint64_t stf                     : 1;
+        uint64_t stc                     : 1;
+        uint64_t stp                     : 1;
+        uint64_t stt                     : 1;
+        uint64_t iobld8                  : 1;
+        uint64_t iobld16                 : 1;
+        uint64_t iobld32                 : 1;
+        uint64_t iobld64                 : 1;
+        uint64_t iobst                   : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn31xx;
+    struct cvmx_tra_trig0_cmd_cn31xx     cn38xx;
+    struct cvmx_tra_trig0_cmd_cn31xx     cn38xxp2;
+    struct cvmx_tra_trig0_cmd_s          cn52xx;
+    struct cvmx_tra_trig0_cmd_s          cn52xxp1;
+    struct cvmx_tra_trig0_cmd_s          cn56xx;
+    struct cvmx_tra_trig0_cmd_s          cn56xxp1;
+    struct cvmx_tra_trig0_cmd_s          cn58xx;
+    struct cvmx_tra_trig0_cmd_s          cn58xxp1;
+} cvmx_tra_trig0_cmd_t;
+
+
+/**
+ * cvmx_tra_trig0_did
+ *
+ * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig0_did_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t illegal                 : 19;      /**< Illegal destinations */
+        uint64_t pow                     : 1;       /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+        uint64_t illegal2                : 3;       /**< Illegal destinations */
+        uint64_t rng                     : 1;       /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+        uint64_t zip                     : 1;       /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+        uint64_t dfa                     : 1;       /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+        uint64_t fpa                     : 1;       /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+        uint64_t key                     : 1;       /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+        uint64_t pci                     : 1;       /**< Enable triggering on requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+        uint64_t illegal3                : 2;       /**< Illegal destinations */
+        uint64_t mio                     : 1;       /**< Enable triggering on CIU and GPIO CSR's */
+#else
+        uint64_t mio                     : 1;
+        uint64_t illegal3                : 2;
+        uint64_t pci                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t rng                     : 1;
+        uint64_t illegal2                : 3;
+        uint64_t pow                     : 1;
+        uint64_t illegal                 : 19;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_tra_trig0_did_s          cn31xx;
+    struct cvmx_tra_trig0_did_s          cn38xx;
+    struct cvmx_tra_trig0_did_s          cn38xxp2;
+    struct cvmx_tra_trig0_did_s          cn52xx;
+    struct cvmx_tra_trig0_did_s          cn52xxp1;
+    struct cvmx_tra_trig0_did_s          cn56xx;
+    struct cvmx_tra_trig0_did_s          cn56xxp1;
+    struct cvmx_tra_trig0_did_s          cn58xx;
+    struct cvmx_tra_trig0_did_s          cn58xxp1;
+} cvmx_tra_trig0_did_t;
+
+
+/**
+ * cvmx_tra_trig0_sid
+ *
+ * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig0_sid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t dwb                     : 1;       /**< Enable triggering on requests from the IOB DWB engine */
+        uint64_t iobreq                  : 1;       /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+        uint64_t pko                     : 1;       /**< Enable triggering on read requests from PKO */
+        uint64_t pki                     : 1;       /**< Enable triggering on write requests from PIP/IPD */
+        uint64_t pp                      : 16;      /**< Enable triggering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+        uint64_t pp                      : 16;
+        uint64_t pki                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t iobreq                  : 1;
+        uint64_t dwb                     : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_tra_trig0_sid_s          cn31xx;
+    struct cvmx_tra_trig0_sid_s          cn38xx;
+    struct cvmx_tra_trig0_sid_s          cn38xxp2;
+    struct cvmx_tra_trig0_sid_s          cn52xx;
+    struct cvmx_tra_trig0_sid_s          cn52xxp1;
+    struct cvmx_tra_trig0_sid_s          cn56xx;
+    struct cvmx_tra_trig0_sid_s          cn56xxp1;
+    struct cvmx_tra_trig0_sid_s          cn58xx;
+    struct cvmx_tra_trig0_sid_s          cn58xxp1;
+} cvmx_tra_trig0_sid_t;
+
+
+/**
+ * cvmx_tra_trig1_adr_adr
+ *
+ * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig1_adr_adr_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t adr                     : 36;      /**< Unmasked Address
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches */
+#else
+        uint64_t adr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_tra_trig1_adr_adr_s      cn31xx;
+    struct cvmx_tra_trig1_adr_adr_s      cn38xx;
+    struct cvmx_tra_trig1_adr_adr_s      cn38xxp2;
+    struct cvmx_tra_trig1_adr_adr_s      cn52xx;
+    struct cvmx_tra_trig1_adr_adr_s      cn52xxp1;
+    struct cvmx_tra_trig1_adr_adr_s      cn56xx;
+    struct cvmx_tra_trig1_adr_adr_s      cn56xxp1;
+    struct cvmx_tra_trig1_adr_adr_s      cn58xx;
+    struct cvmx_tra_trig1_adr_adr_s      cn58xxp1;
+} cvmx_tra_trig1_adr_adr_t;
+
+
+/**
+ * cvmx_tra_trig1_adr_msk
+ *
+ * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig1_adr_msk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t adr                     : 36;      /**< Address Mask
+                                                         The combination of TRA_TRIG1_ADR_ADR and
+                                                         TRA_TRIG1_ADR_MSK is a masked address to
+                                                         enable tracing of only those commands whose
+                                                         masked address matches.  When a mask bit is not
+                                                         set, the corresponding address bits are assumed
+                                                         to match.  Also, note that IOBDMAs do not have
+                                                         proper addresses, so when TRA_TRIG1_CMD[IOBDMA]
+                                                         is set, TRA_FILT_TRIG1_MSK must be zero to
+                                                         guarantee that any IOBDMAs are recognized as
+                                                         triggers. */
+#else
+        uint64_t adr                     : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_tra_trig1_adr_msk_s      cn31xx;
+    struct cvmx_tra_trig1_adr_msk_s      cn38xx;
+    struct cvmx_tra_trig1_adr_msk_s      cn38xxp2;
+    struct cvmx_tra_trig1_adr_msk_s      cn52xx;
+    struct cvmx_tra_trig1_adr_msk_s      cn52xxp1;
+    struct cvmx_tra_trig1_adr_msk_s      cn56xx;
+    struct cvmx_tra_trig1_adr_msk_s      cn56xxp1;
+    struct cvmx_tra_trig1_adr_msk_s      cn58xx;
+    struct cvmx_tra_trig1_adr_msk_s      cn58xxp1;
+} cvmx_tra_trig1_adr_msk_t;
+
+
+/**
+ * cvmx_tra_trig1_cmd
+ *
+ * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask
+ * 
+ * Description:
+ *
+ * Notes:
+ * Note that the trace buffer does not do proper IOBDMA address compares.  Thus, if IOBDMA is set, then
+ * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs
+ * are recognized as triggers.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig1_cmd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_17_63          : 47;
+        uint64_t saa                     : 1;       /**< Enable SAA     tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+        uint64_t stt                     : 1;       /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stp                     : 1;       /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stc                     : 1;       /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stf                     : 1;       /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+        uint64_t dwb                     : 1;
+        uint64_t pl2                     : 1;
+        uint64_t psl1                    : 1;
+        uint64_t ldd                     : 1;
+        uint64_t ldi                     : 1;
+        uint64_t ldt                     : 1;
+        uint64_t stf                     : 1;
+        uint64_t stc                     : 1;
+        uint64_t stp                     : 1;
+        uint64_t stt                     : 1;
+        uint64_t iobld8                  : 1;
+        uint64_t iobld16                 : 1;
+        uint64_t iobld32                 : 1;
+        uint64_t iobld64                 : 1;
+        uint64_t iobst                   : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t saa                     : 1;
+        uint64_t reserved_17_63          : 47;
+#endif
+    } s;
+    struct cvmx_tra_trig1_cmd_cn31xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_16_63          : 48;
+        uint64_t iobdma                  : 1;       /**< Enable IOBDMA  tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobst                   : 1;       /**< Enable IOBST   tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld64                 : 1;       /**< Enable IOBLD64 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld32                 : 1;       /**< Enable IOBLD32 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld16                 : 1;       /**< Enable IOBLD16 tracing
+                                                         0=disable, 1=enable */
+        uint64_t iobld8                  : 1;       /**< Enable IOBLD8  tracing
+                                                         0=disable, 1=enable */
+        uint64_t stt                     : 1;       /**< Enable STT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stp                     : 1;       /**< Enable STP     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stc                     : 1;       /**< Enable STC     tracing
+                                                         0=disable, 1=enable */
+        uint64_t stf                     : 1;       /**< Enable STF     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldt                     : 1;       /**< Enable LDT     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldi                     : 1;       /**< Enable LDI     tracing
+                                                         0=disable, 1=enable */
+        uint64_t ldd                     : 1;       /**< Enable LDD     tracing
+                                                         0=disable, 1=enable */
+        uint64_t psl1                    : 1;       /**< Enable PSL1    tracing
+                                                         0=disable, 1=enable */
+        uint64_t pl2                     : 1;       /**< Enable PL2     tracing
+                                                         0=disable, 1=enable */
+        uint64_t dwb                     : 1;       /**< Enable DWB     tracing
+                                                         0=disable, 1=enable */
+#else
+        uint64_t dwb                     : 1;
+        uint64_t pl2                     : 1;
+        uint64_t psl1                    : 1;
+        uint64_t ldd                     : 1;
+        uint64_t ldi                     : 1;
+        uint64_t ldt                     : 1;
+        uint64_t stf                     : 1;
+        uint64_t stc                     : 1;
+        uint64_t stp                     : 1;
+        uint64_t stt                     : 1;
+        uint64_t iobld8                  : 1;
+        uint64_t iobld16                 : 1;
+        uint64_t iobld32                 : 1;
+        uint64_t iobld64                 : 1;
+        uint64_t iobst                   : 1;
+        uint64_t iobdma                  : 1;
+        uint64_t reserved_16_63          : 48;
+#endif
+    } cn31xx;
+    struct cvmx_tra_trig1_cmd_cn31xx     cn38xx;
+    struct cvmx_tra_trig1_cmd_cn31xx     cn38xxp2;
+    struct cvmx_tra_trig1_cmd_s          cn52xx;
+    struct cvmx_tra_trig1_cmd_s          cn52xxp1;
+    struct cvmx_tra_trig1_cmd_s          cn56xx;
+    struct cvmx_tra_trig1_cmd_s          cn56xxp1;
+    struct cvmx_tra_trig1_cmd_s          cn58xx;
+    struct cvmx_tra_trig1_cmd_s          cn58xxp1;
+} cvmx_tra_trig1_cmd_t;
+
+
+/**
+ * cvmx_tra_trig1_did
+ *
+ * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig1_did_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_32_63          : 32;
+        uint64_t illegal                 : 19;      /**< Illegal destinations */
+        uint64_t pow                     : 1;       /**< Enable triggering on requests to POW
+                                                         (get work, add work, status/memory/index
+                                                         loads, NULLRd loads, CSR's) */
+        uint64_t illegal2                : 3;       /**< Illegal destinations */
+        uint64_t rng                     : 1;       /**< Enable triggering on requests to RNG
+                                                         (loads/IOBDMA's are legal) */
+        uint64_t zip                     : 1;       /**< Enable triggering on requests to ZIP
+                                                         (doorbell stores are legal) */
+        uint64_t dfa                     : 1;       /**< Enable triggering on requests to DFA
+                                                         (CSR's and operations are legal) */
+        uint64_t fpa                     : 1;       /**< Enable triggering on requests to FPA
+                                                         (alloc's (loads/IOBDMA's), frees (stores) are legal) */
+        uint64_t key                     : 1;       /**< Enable triggering on requests to KEY memory
+                                                         (loads/IOBDMA's/stores are legal) */
+        uint64_t pci                     : 1;       /**< Enable triggering on requests to PCI and RSL-type
+                                                         CSR's (RSL CSR's, PCI bus operations, PCI
+                                                         CSR's) */
+        uint64_t illegal3                : 2;       /**< Illegal destinations */
+        uint64_t mio                     : 1;       /**< Enable triggering on CIU and GPIO CSR's */
+#else
+        uint64_t mio                     : 1;
+        uint64_t illegal3                : 2;
+        uint64_t pci                     : 1;
+        uint64_t key                     : 1;
+        uint64_t fpa                     : 1;
+        uint64_t dfa                     : 1;
+        uint64_t zip                     : 1;
+        uint64_t rng                     : 1;
+        uint64_t illegal2                : 3;
+        uint64_t pow                     : 1;
+        uint64_t illegal                 : 19;
+        uint64_t reserved_32_63          : 32;
+#endif
+    } s;
+    struct cvmx_tra_trig1_did_s          cn31xx;
+    struct cvmx_tra_trig1_did_s          cn38xx;
+    struct cvmx_tra_trig1_did_s          cn38xxp2;
+    struct cvmx_tra_trig1_did_s          cn52xx;
+    struct cvmx_tra_trig1_did_s          cn52xxp1;
+    struct cvmx_tra_trig1_did_s          cn56xx;
+    struct cvmx_tra_trig1_did_s          cn56xxp1;
+    struct cvmx_tra_trig1_did_s          cn58xx;
+    struct cvmx_tra_trig1_did_s          cn58xxp1;
+} cvmx_tra_trig1_did_t;
+
+
+/**
+ * cvmx_tra_trig1_sid
+ *
+ * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask
+ * 
+ * Description:
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_tra_trig1_sid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t dwb                     : 1;       /**< Enable triggering on requests from the IOB DWB engine */
+        uint64_t iobreq                  : 1;       /**< Enable triggering on requests from FPA,TIM,DFA,
+                                                         PCI,ZIP,POW, and PKO (writes) */
+        uint64_t pko                     : 1;       /**< Enable triggering on read requests from PKO */
+        uint64_t pki                     : 1;       /**< Enable triggering on write requests from PIP/IPD */
+        uint64_t pp                      : 16;      /**< Enable trigering from PP[N] with matching SourceID
+                                                         0=disable, 1=enableper bit N where  0<=N<=15 */
+#else
+        uint64_t pp                      : 16;
+        uint64_t pki                     : 1;
+        uint64_t pko                     : 1;
+        uint64_t iobreq                  : 1;
+        uint64_t dwb                     : 1;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_tra_trig1_sid_s          cn31xx;
+    struct cvmx_tra_trig1_sid_s          cn38xx;
+    struct cvmx_tra_trig1_sid_s          cn38xxp2;
+    struct cvmx_tra_trig1_sid_s          cn52xx;
+    struct cvmx_tra_trig1_sid_s          cn52xxp1;
+    struct cvmx_tra_trig1_sid_s          cn56xx;
+    struct cvmx_tra_trig1_sid_s          cn56xxp1;
+    struct cvmx_tra_trig1_sid_s          cn58xx;
+    struct cvmx_tra_trig1_sid_s          cn58xxp1;
+} cvmx_tra_trig1_sid_t;
+
+
+/**
+ * cvmx_usbc#_daint
+ *
+ * Device All Endpoints Interrupt Register (DAINT)
+ * 
+ * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register
+ * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints
+ * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively).
+ * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16
+ * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt
+ * bits are used. Bits in this register are set and cleared when the application sets and clears
+ * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_daint_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t outepint                : 16;      /**< OUT Endpoint Interrupt Bits (OutEPInt)
+                                                         One bit per OUT endpoint:
+                                                         Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */
+        uint32_t inepint                 : 16;      /**< IN Endpoint Interrupt Bits (InEpInt)
+                                                         One bit per IN Endpoint:
+                                                         Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */
+#else
+        uint32_t inepint                 : 16;
+        uint32_t outepint                : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_daint_s            cn30xx;
+    struct cvmx_usbcx_daint_s            cn31xx;
+    struct cvmx_usbcx_daint_s            cn50xx;
+    struct cvmx_usbcx_daint_s            cn52xx;
+    struct cvmx_usbcx_daint_s            cn52xxp1;
+    struct cvmx_usbcx_daint_s            cn56xx;
+    struct cvmx_usbcx_daint_s            cn56xxp1;
+} cvmx_usbcx_daint_t;
+
+
+/**
+ * cvmx_usbc#_daintmsk
+ *
+ * Device All Endpoints Interrupt Mask Register (DAINTMSK)
+ * 
+ * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register
+ * to interrupt the application when an event occurs on a device endpoint. However, the Device
+ * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set.
+ * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_daintmsk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t outepmsk                : 16;      /**< OUT EP Interrupt Mask Bits (OutEpMsk)
+                                                         One per OUT Endpoint:
+                                                         Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */
+        uint32_t inepmsk                 : 16;      /**< IN EP Interrupt Mask Bits (InEpMsk)
+                                                         One bit per IN Endpoint:
+                                                         Bit 0 for IN EP 0, bit 15 for IN EP 15 */
+#else
+        uint32_t inepmsk                 : 16;
+        uint32_t outepmsk                : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_daintmsk_s         cn30xx;
+    struct cvmx_usbcx_daintmsk_s         cn31xx;
+    struct cvmx_usbcx_daintmsk_s         cn50xx;
+    struct cvmx_usbcx_daintmsk_s         cn52xx;
+    struct cvmx_usbcx_daintmsk_s         cn52xxp1;
+    struct cvmx_usbcx_daintmsk_s         cn56xx;
+    struct cvmx_usbcx_daintmsk_s         cn56xxp1;
+} cvmx_usbcx_daintmsk_t;
+
+
+/**
+ * cvmx_usbc#_dcfg
+ *
+ * Device Configuration Register (DCFG)
+ * 
+ * This register configures the core in Device mode after power-on or after certain control
+ * commands or enumeration. Do not make changes to this register after initial programming.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dcfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_23_31          : 9;
+        uint32_t epmiscnt                : 5;       /**< IN Endpoint Mismatch Count (EPMisCnt)
+                                                         The application programs this filed with a count that determines
+                                                         when the core generates an Endpoint Mismatch interrupt
+                                                         (GINTSTS.EPMis). The core loads this value into an internal
+                                                         counter and decrements it. The counter is reloaded whenever
+                                                         there is a match or when the counter expires. The width of this
+                                                         counter depends on the depth of the Token Queue. */
+        uint32_t reserved_13_17          : 5;
+        uint32_t perfrint                : 2;       /**< Periodic Frame Interval (PerFrInt)
+                                                         Indicates the time within a (micro)frame at which the application
+                                                         must be notified using the End Of Periodic Frame Interrupt. This
+                                                         can be used to determine if all the isochronous traffic for that
+                                                         (micro)frame is complete.
+                                                         * 2'b00: 80% of the (micro)frame interval
+                                                         * 2'b01: 85%
+                                                         * 2'b10: 90%
+                                                         * 2'b11: 95% */
+        uint32_t devaddr                 : 7;       /**< Device Address (DevAddr)
+                                                         The application must program this field after every SetAddress
+                                                         control command. */
+        uint32_t reserved_3_3            : 1;
+        uint32_t nzstsouthshk            : 1;       /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
+                                                         The application can use this field to select the handshake the
+                                                         core sends on receiving a nonzero-length data packet during
+                                                         the OUT transaction of a control transfer's Status stage.
+                                                         * 1'b1: Send a STALL handshake on a nonzero-length status
+                                                                 OUT transaction and do not send the received OUT packet to
+                                                                 the application.
+                                                         * 1'b0: Send the received OUT packet to the application (zero-
+                                                                 length or nonzero-length) and send a handshake based on
+                                                                 the NAK and STALL bits for the endpoint in the Device
+                                                                 Endpoint Control register. */
+        uint32_t devspd                  : 2;       /**< Device Speed (DevSpd)
+                                                         Indicates the speed at which the application requires the core to
+                                                         enumerate, or the maximum speed the application can support.
+                                                         However, the actual bus speed is determined only after the
+                                                         chirp sequence is completed, and is based on the speed of the
+                                                         USB host to which the core is connected. See "Device
+                                                         Initialization" on page 249 for details.
+                                                         * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
+                                                         * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
+                                                         * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
+                                                                  you select 6 MHz LS mode, you must do a soft reset.
+                                                         * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */
+#else
+        uint32_t devspd                  : 2;
+        uint32_t nzstsouthshk            : 1;
+        uint32_t reserved_3_3            : 1;
+        uint32_t devaddr                 : 7;
+        uint32_t perfrint                : 2;
+        uint32_t reserved_13_17          : 5;
+        uint32_t epmiscnt                : 5;
+        uint32_t reserved_23_31          : 9;
+#endif
+    } s;
+    struct cvmx_usbcx_dcfg_s             cn30xx;
+    struct cvmx_usbcx_dcfg_s             cn31xx;
+    struct cvmx_usbcx_dcfg_s             cn50xx;
+    struct cvmx_usbcx_dcfg_s             cn52xx;
+    struct cvmx_usbcx_dcfg_s             cn52xxp1;
+    struct cvmx_usbcx_dcfg_s             cn56xx;
+    struct cvmx_usbcx_dcfg_s             cn56xxp1;
+} cvmx_usbcx_dcfg_t;
+
+
+/**
+ * cvmx_usbc#_dctl
+ *
+ * Device Control Register (DCTL)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_12_31          : 20;
+        uint32_t pwronprgdone            : 1;       /**< Power-On Programming Done (PWROnPrgDone)
+                                                         The application uses this bit to indicate that register
+                                                         programming is completed after a wake-up from Power Down
+                                                         mode. For more information, see "Device Mode Suspend and
+                                                         Resume With Partial Power-Down" on page 357. */
+        uint32_t cgoutnak                : 1;       /**< Clear Global OUT NAK (CGOUTNak)
+                                                         A write to this field clears the Global OUT NAK. */
+        uint32_t sgoutnak                : 1;       /**< Set Global OUT NAK (SGOUTNak)
+                                                         A write to this field sets the Global OUT NAK.
+                                                         The application uses this bit to send a NAK handshake on all
+                                                         OUT endpoints.
+                                                         The application should set the this bit only after making sure
+                                                         that the Global OUT NAK Effective bit in the Core Interrupt
+                                                         Register (GINTSTS.GOUTNakEff) is cleared. */
+        uint32_t cgnpinnak               : 1;       /**< Clear Global Non-Periodic IN NAK (CGNPInNak)
+                                                         A write to this field clears the Global Non-Periodic IN NAK. */
+        uint32_t sgnpinnak               : 1;       /**< Set Global Non-Periodic IN NAK (SGNPInNak)
+                                                         A write to this field sets the Global Non-Periodic IN NAK.The
+                                                         application uses this bit to send a NAK handshake on all non-
+                                                         periodic IN endpoints. The core can also set this bit when a
+                                                         timeout condition is detected on a non-periodic endpoint.
+                                                         The application should set this bit only after making sure that
+                                                         the Global IN NAK Effective bit in the Core Interrupt Register
+                                                         (GINTSTS.GINNakEff) is cleared. */
+        uint32_t tstctl                  : 3;       /**< Test Control (TstCtl)
+                                                         * 3'b000: Test mode disabled
+                                                         * 3'b001: Test_J mode
+                                                         * 3'b010: Test_K mode
+                                                         * 3'b011: Test_SE0_NAK mode
+                                                         * 3'b100: Test_Packet mode
+                                                         * 3'b101: Test_Force_Enable
+                                                         * Others: Reserved */
+        uint32_t goutnaksts              : 1;       /**< Global OUT NAK Status (GOUTNakSts)
+                                                         * 1'b0: A handshake is sent based on the FIFO Status and the
+                                                                 NAK and STALL bit settings.
+                                                         * 1'b1: No data is written to the RxFIFO, irrespective of space
+                                                                 availability. Sends a NAK handshake on all packets, except
+                                                                 on SETUP transactions. All isochronous OUT packets are
+                                                                 dropped. */
+        uint32_t gnpinnaksts             : 1;       /**< Global Non-Periodic IN NAK Status (GNPINNakSts)
+                                                         * 1'b0: A handshake is sent out based on the data availability
+                                                                 in the transmit FIFO.
+                                                         * 1'b1: A NAK handshake is sent out on all non-periodic IN
+                                                                 endpoints, irrespective of the data availability in the transmit
+                                                                 FIFO. */
+        uint32_t sftdiscon               : 1;       /**< Soft Disconnect (SftDiscon)
+                                                         The application uses this bit to signal the O2P USB core to do a
+                                                         soft disconnect. As long as this bit is set, the host will not see
+                                                         that the device is connected, and the device will not receive
+                                                         signals on the USB. The core stays in the disconnected state
+                                                         until the application clears this bit.
+                                                         The minimum duration for which the core must keep this bit set
+                                                         is specified in Minimum Duration for Soft Disconnect  .
+                                                         * 1'b0: Normal operation. When this bit is cleared after a soft
+                                                         disconnect, the core drives the phy_opmode_o signal on the
+                                                         UTMI+ to 2'b00, which generates a device connect event to
+                                                         the USB host. When the device is reconnected, the USB host
+                                                         restarts device enumeration.
+                                                         * 1'b1: The core drives the phy_opmode_o signal on the
+                                                         UTMI+ to 2'b01, which generates a device disconnect event
+                                                         to the USB host. */
+        uint32_t rmtwkupsig              : 1;       /**< Remote Wakeup Signaling (RmtWkUpSig)
+                                                         When the application sets this bit, the core initiates remote
+                                                         signaling to wake up the USB host.The application must set this
+                                                         bit to get the core out of Suspended state and must clear this bit
+                                                         after the core comes out of Suspended state. */
+#else
+        uint32_t rmtwkupsig              : 1;
+        uint32_t sftdiscon               : 1;
+        uint32_t gnpinnaksts             : 1;
+        uint32_t goutnaksts              : 1;
+        uint32_t tstctl                  : 3;
+        uint32_t sgnpinnak               : 1;
+        uint32_t cgnpinnak               : 1;
+        uint32_t sgoutnak                : 1;
+        uint32_t cgoutnak                : 1;
+        uint32_t pwronprgdone            : 1;
+        uint32_t reserved_12_31          : 20;
+#endif
+    } s;
+    struct cvmx_usbcx_dctl_s             cn30xx;
+    struct cvmx_usbcx_dctl_s             cn31xx;
+    struct cvmx_usbcx_dctl_s             cn50xx;
+    struct cvmx_usbcx_dctl_s             cn52xx;
+    struct cvmx_usbcx_dctl_s             cn52xxp1;
+    struct cvmx_usbcx_dctl_s             cn56xx;
+    struct cvmx_usbcx_dctl_s             cn56xxp1;
+} cvmx_usbcx_dctl_t;
+
+
+/**
+ * cvmx_usbc#_diepctl#
+ *
+ * Device IN Endpoint-n Control Register (DIEPCTLn)
+ * 
+ * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_diepctlx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t epena                   : 1;       /**< Endpoint Enable (EPEna)
+                                                         Indicates that data is ready to be transmitted on the endpoint.
+                                                         The core clears this bit before setting any of the following
+                                                         interrupts on this endpoint:
+                                                         * Endpoint Disabled
+                                                         * Transfer Completed */
+        uint32_t epdis                   : 1;       /**< Endpoint Disable (EPDis)
+                                                         The application sets this bit to stop transmitting data on an
+                                                         endpoint, even before the transfer for that endpoint is complete.
+                                                         The application must wait for the Endpoint Disabled interrupt
+                                                         before treating the endpoint as disabled. The core clears this bit
+                                                         before setting the Endpoint Disabled Interrupt. The application
+                                                         should set this bit only if Endpoint Enable is already set for this
+                                                         endpoint. */
+        uint32_t setd1pid                : 1;       /**< For Interrupt/BULK enpoints:
+                                                          Set DATA1 PID (SetD1PID)
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA1.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetOddFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to odd (micro)frame. */
+        uint32_t setd0pid                : 1;       /**< For Interrupt/BULK enpoints:
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA0.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetEvenFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to even (micro)frame. */
+        uint32_t snak                    : 1;       /**< Set NAK (SNAK)
+                                                         A write to this bit sets the NAK bit for the endpoint.
+                                                         Using this bit, the application can control the transmission of
+                                                         NAK handshakes on an endpoint. The core can also set this bit
+                                                         for an endpoint after a SETUP packet is received on the
+                                                         endpoint. */
+        uint32_t cnak                    : 1;       /**< Clear NAK (CNAK)
+                                                         A write to this bit clears the NAK bit for the endpoint. */
+        uint32_t txfnum                  : 4;       /**< TxFIFO Number (TxFNum)
+                                                         Non-periodic endpoints must set this bit to zero.  Periodic
+                                                         endpoints must map this to the corresponding Periodic TxFIFO
+                                                         number.
+                                                         * 4'h0: Non-Periodic TxFIFO
+                                                         * Others: Specified Periodic TxFIFO number */
+        uint32_t stall                   : 1;       /**< STALL Handshake (Stall)
+                                                         For non-control, non-isochronous endpoints:
+                                                          The application sets this bit to stall all tokens from the USB host
+                                                          to this endpoint.  If a NAK bit, Global Non-Periodic IN NAK, or
+                                                          Global OUT NAK is set along with this bit, the STALL bit takes
+                                                          priority.  Only the application can clear this bit, never the core.
+                                                         For control endpoints:
+                                                          The application can only set this bit, and the core clears it, when
+                                                          a SETUP token i received for this endpoint.  If a NAK bit, Global
+                                                          Non-Periodic IN NAK, or Global OUT NAK is set along with this
+                                                          bit, the STALL bit takes priority.  Irrespective of this bit's setting,
+                                                          the core always responds to SETUP data packets with an ACK handshake. */
+        uint32_t reserved_20_20          : 1;
+        uint32_t eptype                  : 2;       /**< Endpoint Type (EPType)
+                                                         This is the transfer type supported by this logical endpoint.
+                                                         * 2'b00: Control
+                                                         * 2'b01: Isochronous
+                                                         * 2'b10: Bulk
+                                                         * 2'b11: Interrupt */
+        uint32_t naksts                  : 1;       /**< NAK Status (NAKSts)
+                                                         Indicates the following:
+                                                         * 1'b0: The core is transmitting non-NAK handshakes based
+                                                                 on the FIFO status
+                                                         * 1'b1: The core is transmitting NAK handshakes on this
+                                                                 endpoint.
+                                                         When either the application or the core sets this bit:
+                                                         * For non-isochronous IN endpoints: The core stops
+                                                           transmitting any data on an IN endpoint, even if data is
+                                                           available in the TxFIFO.
+                                                         * For isochronous IN endpoints: The core sends out a zero-
+                                                           length data packet, even if data is available in the TxFIFO.
+                                                         Irrespective of this bit's setting, the core always responds to
+                                                         SETUP data packets with an ACK handshake. */
+        uint32_t dpid                    : 1;       /**< For interrupt/bulk IN and OUT endpoints:
+                                                          Endpoint Data PID (DPID)
+                                                          Contains the PID of the packet to be received or transmitted on
+                                                          this endpoint.  The application should program the PID of the first
+                                                          packet to be received or transmitted on this endpoint, after the
+                                                          endpoint is activated.  Applications use the SetD1PID and
+                                                          SetD0PID fields of this register to program either DATA0 or
+                                                          DATA1 PID.
+                                                          * 1'b0: DATA0
+                                                          * 1'b1: DATA1
+                                                         For isochronous IN and OUT endpoints:
+                                                          Even/Odd (Micro)Frame (EO_FrNum)
+                                                          Indicates the (micro)frame number in which the core transmits/
+                                                          receives isochronous data for this endpoint.  The application
+                                                          should program the even/odd (micro) frame number in which it
+                                                          intends to transmit/receive isochronous data for this endpoint
+                                                          using the SetEvnFr and SetOddFr fields in this register.
+                                                          * 1'b0: Even (micro)frame
+                                                          * 1'b1: Odd (micro)frame */
+        uint32_t usbactep                : 1;       /**< USB Active Endpoint (USBActEP)
+                                                         Indicates whether this endpoint is active in the current
+                                                         configuration and interface.  The core clears this bit for all
+                                                         endpoints (other than EP 0) after detecting a USB reset.  After
+                                                         receiving the SetConfiguration and SetInterface commands, the
+                                                         application must program endpoint registers accordingly and set
+                                                         this bit. */
+        uint32_t nextep                  : 4;       /**< Next Endpoint (NextEp)
+                                                         Applies to non-periodic IN endpoints only.
+                                                         Indicates the endpoint number to be fetched after the data for
+                                                         the current endpoint is fetched. The core can access this field,
+                                                         even when the Endpoint Enable (EPEna) bit is not set. This
+                                                         field is not valid in Slave mode. */
+        uint32_t mps                     : 11;      /**< Maximum Packet Size (MPS)
+                                                         Applies to IN and OUT endpoints.
+                                                         The application must program this field with the maximum
+                                                         packet size for the current logical endpoint.  This value is in
+                                                         bytes. */
+#else
+        uint32_t mps                     : 11;
+        uint32_t nextep                  : 4;
+        uint32_t usbactep                : 1;
+        uint32_t dpid                    : 1;
+        uint32_t naksts                  : 1;
+        uint32_t eptype                  : 2;
+        uint32_t reserved_20_20          : 1;
+        uint32_t stall                   : 1;
+        uint32_t txfnum                  : 4;
+        uint32_t cnak                    : 1;
+        uint32_t snak                    : 1;
+        uint32_t setd0pid                : 1;
+        uint32_t setd1pid                : 1;
+        uint32_t epdis                   : 1;
+        uint32_t epena                   : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_diepctlx_s         cn30xx;
+    struct cvmx_usbcx_diepctlx_s         cn31xx;
+    struct cvmx_usbcx_diepctlx_s         cn50xx;
+    struct cvmx_usbcx_diepctlx_s         cn52xx;
+    struct cvmx_usbcx_diepctlx_s         cn52xxp1;
+    struct cvmx_usbcx_diepctlx_s         cn56xx;
+    struct cvmx_usbcx_diepctlx_s         cn56xxp1;
+} cvmx_usbcx_diepctlx_t;
+
+
+/**
+ * cvmx_usbc#_diepint#
+ *
+ * Device Endpoint-n Interrupt Register (DIEPINTn)
+ * 
+ * This register indicates the status of an endpoint with respect to
+ * USB- and AHB-related events. The application must read this register
+ * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
+ * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt,
+ * respectively) is set. Before the application can read this register,
+ * it must first read the Device All Endpoints Interrupt (DAINT) register
+ * to get the exact endpoint number for the Device Endpoint-n Interrupt
+ * register. The application must clear the appropriate bit in this register
+ * to clear the corresponding bits in the DAINT and GINTSTS registers.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_diepintx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_7_31           : 25;
+        uint32_t inepnakeff              : 1;       /**< IN Endpoint NAK Effective (INEPNakEff)
+                                                         Applies to periodic IN endpoints only.
+                                                         Indicates that the IN endpoint NAK bit set by the application has
+                                                         taken effect in the core. This bit can be cleared when the
+                                                         application clears the IN endpoint NAK by writing to
+                                                         DIEPCTLn.CNAK.
+                                                         This interrupt indicates that the core has sampled the NAK bit
+                                                         set (either by the application or by the core).
+                                                         This interrupt does not necessarily mean that a NAK handshake
+                                                         is sent on the USB. A STALL bit takes priority over a NAK bit. */
+        uint32_t intknepmis              : 1;       /**< IN Token Received with EP Mismatch (INTknEPMis)
+                                                         Applies to non-periodic IN endpoints only.
+                                                         Indicates that the data in the top of the non-periodic TxFIFO
+                                                         belongs to an endpoint other than the one for which the IN
+                                                         token was received. This interrupt is asserted on the endpoint
+                                                         for which the IN token was received. */
+        uint32_t intkntxfemp             : 1;       /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp)
+                                                         Applies only to non-periodic IN endpoints.
+                                                         Indicates that an IN token was received when the associated
+                                                         TxFIFO (periodic/non-periodic) was empty. This interrupt is
+                                                         asserted on the endpoint for which the IN token was received. */
+        uint32_t timeout                 : 1;       /**< Timeout Condition (TimeOUT)
+                                                         Applies to non-isochronous IN endpoints only.
+                                                         Indicates that the core has detected a timeout condition on the
+                                                         USB for the last IN token on this endpoint. */
+        uint32_t ahberr                  : 1;       /**< AHB Error (AHBErr)
+                                                         This is generated only in Internal DMA mode when there is an
+                                                         AHB error during an AHB read/write. The application can read
+                                                         the corresponding endpoint DMA address register to get the
+                                                         error address. */
+        uint32_t epdisbld                : 1;       /**< Endpoint Disabled Interrupt (EPDisbld)
+                                                         This bit indicates that the endpoint is disabled per the
+                                                         application's request. */
+        uint32_t xfercompl               : 1;       /**< Transfer Completed Interrupt (XferCompl)
+                                                         Indicates that the programmed transfer is complete on the AHB
+                                                         as well as on the USB, for this endpoint. */
+#else
+        uint32_t xfercompl               : 1;
+        uint32_t epdisbld                : 1;
+        uint32_t ahberr                  : 1;
+        uint32_t timeout                 : 1;
+        uint32_t intkntxfemp             : 1;
+        uint32_t intknepmis              : 1;
+        uint32_t inepnakeff              : 1;
+        uint32_t reserved_7_31           : 25;
+#endif
+    } s;
+    struct cvmx_usbcx_diepintx_s         cn30xx;
+    struct cvmx_usbcx_diepintx_s         cn31xx;
+    struct cvmx_usbcx_diepintx_s         cn50xx;
+    struct cvmx_usbcx_diepintx_s         cn52xx;
+    struct cvmx_usbcx_diepintx_s         cn52xxp1;
+    struct cvmx_usbcx_diepintx_s         cn56xx;
+    struct cvmx_usbcx_diepintx_s         cn56xxp1;
+} cvmx_usbcx_diepintx_t;
+
+
+/**
+ * cvmx_usbc#_diepmsk
+ *
+ * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK)
+ * 
+ * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers
+ * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
+ * for a specific status in the DIEPINTn register can be masked by writing to the corresponding
+ * bit in this register. Status bits are masked by default.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_diepmsk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_7_31           : 25;
+        uint32_t inepnakeffmsk           : 1;       /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
+        uint32_t intknepmismsk           : 1;       /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
+        uint32_t intkntxfempmsk          : 1;       /**< IN Token Received When TxFIFO Empty Mask
+                                                         (INTknTXFEmpMsk) */
+        uint32_t timeoutmsk              : 1;       /**< Timeout Condition Mask (TimeOUTMsk)
+                                                         (Non-isochronous endpoints) */
+        uint32_t ahberrmsk               : 1;       /**< AHB Error Mask (AHBErrMsk) */
+        uint32_t epdisbldmsk             : 1;       /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
+        uint32_t xfercomplmsk            : 1;       /**< Transfer Completed Interrupt Mask (XferComplMsk) */
+#else
+        uint32_t xfercomplmsk            : 1;
+        uint32_t epdisbldmsk             : 1;
+        uint32_t ahberrmsk               : 1;
+        uint32_t timeoutmsk              : 1;
+        uint32_t intkntxfempmsk          : 1;
+        uint32_t intknepmismsk           : 1;
+        uint32_t inepnakeffmsk           : 1;
+        uint32_t reserved_7_31           : 25;
+#endif
+    } s;
+    struct cvmx_usbcx_diepmsk_s          cn30xx;
+    struct cvmx_usbcx_diepmsk_s          cn31xx;
+    struct cvmx_usbcx_diepmsk_s          cn50xx;
+    struct cvmx_usbcx_diepmsk_s          cn52xx;
+    struct cvmx_usbcx_diepmsk_s          cn52xxp1;
+    struct cvmx_usbcx_diepmsk_s          cn56xx;
+    struct cvmx_usbcx_diepmsk_s          cn56xxp1;
+} cvmx_usbcx_diepmsk_t;
+
+
+/**
+ * cvmx_usbc#_dieptsiz#
+ *
+ * Device Endpoint-n Transfer Size Register (DIEPTSIZn)
+ * 
+ * The application must modify this register before enabling the endpoint.
+ * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna),
+ * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
+ * This register is used only for endpoints other than Endpoint 0.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dieptsizx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_31_31          : 1;
+        uint32_t mc                      : 2;       /**< Multi Count (MC)
+                                                         Applies to IN endpoints only.
+                                                         For periodic IN endpoints, this field indicates the number of
+                                                         packets that must be transmitted per microframe on the USB.
+                                                         The core uses this field to calculate the data PID for
+                                                         isochronous IN endpoints.
+                                                         * 2'b01: 1 packet
+                                                         * 2'b10: 2 packets
+                                                         * 2'b11: 3 packets
+                                                         For non-periodic IN endpoints, this field is valid only in Internal
+                                                         DMA mode. It specifies the number of packets the core should
+                                                         fetch for an IN endpoint before it switches to the endpoint
+                                                         pointed to by the Next Endpoint field of the Device Endpoint-n
+                                                         Control register (DIEPCTLn.NextEp) */
+        uint32_t pktcnt                  : 10;      /**< Packet Count (PktCnt)
+                                                         Indicates the total number of USB packets that constitute the
+                                                         Transfer Size amount of data for this endpoint.
+                                                         IN Endpoints: This field is decremented every time a packet
+                                                         (maximum size or short packet) is read from the TxFIFO. */
+        uint32_t xfersize                : 19;      /**< Transfer Size (XferSize)
+                                                         This field contains the transfer size in bytes for the current
+                                                         endpoint.
+                                                         The core only interrupts the application after it has exhausted
+                                                         the transfer size amount of data. The transfer size can be set to
+                                                         the maximum packet size of the endpoint, to be interrupted at
+                                                         the end of each packet.
+                                                         IN Endpoints: The core decrements this field every time a
+                                                         packet from the external memory is written to the TxFIFO. */
+#else
+        uint32_t xfersize                : 19;
+        uint32_t pktcnt                  : 10;
+        uint32_t mc                      : 2;
+        uint32_t reserved_31_31          : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_dieptsizx_s        cn30xx;
+    struct cvmx_usbcx_dieptsizx_s        cn31xx;
+    struct cvmx_usbcx_dieptsizx_s        cn50xx;
+    struct cvmx_usbcx_dieptsizx_s        cn52xx;
+    struct cvmx_usbcx_dieptsizx_s        cn52xxp1;
+    struct cvmx_usbcx_dieptsizx_s        cn56xx;
+    struct cvmx_usbcx_dieptsizx_s        cn56xxp1;
+} cvmx_usbcx_dieptsizx_t;
+
+
+/**
+ * cvmx_usbc#_doepctl#
+ *
+ * Device OUT Endpoint-n Control Register (DOEPCTLn)
+ * 
+ * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_doepctlx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t epena                   : 1;       /**< Endpoint Enable (EPEna)
+                                                         Indicates that the application has allocated the memory tp start
+                                                         receiving data from the USB.
+                                                         The core clears this bit before setting any of the following
+                                                         interrupts on this endpoint:
+                                                         * SETUP Phase Done
+                                                         * Endpoint Disabled
+                                                         * Transfer Completed
+                                                         For control OUT endpoints in DMA mode, this bit must be set
+                                                         to be able to transfer SETUP data packets in memory. */
+        uint32_t epdis                   : 1;       /**< Endpoint Disable (EPDis)
+                                                         The application sets this bit to stop transmitting data on an
+                                                         endpoint, even before the transfer for that endpoint is complete.
+                                                         The application must wait for the Endpoint Disabled interrupt
+                                                         before treating the endpoint as disabled. The core clears this bit
+                                                         before setting the Endpoint Disabled Interrupt. The application
+                                                         should set this bit only if Endpoint Enable is already set for this
+                                                         endpoint. */
+        uint32_t setd1pid                : 1;       /**< For Interrupt/BULK enpoints:
+                                                          Set DATA1 PID (SetD1PID)
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA1.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetOddFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to odd (micro)frame. */
+        uint32_t setd0pid                : 1;       /**< For Interrupt/BULK enpoints:
+                                                          Writing to this field sets the Endpoint Data Pid (DPID) field in
+                                                          this register to DATA0.
+                                                         For Isochronous endpoints:
+                                                          Set Odd (micro)frame (SetEvenFr)
+                                                          Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
+                                                          field to even (micro)frame. */
+        uint32_t snak                    : 1;       /**< Set NAK (SNAK)
+                                                         A write to this bit sets the NAK bit for the endpoint.
+                                                         Using this bit, the application can control the transmission of
+                                                         NAK handshakes on an endpoint. The core can also set this bit
+                                                         for an endpoint after a SETUP packet is received on the
+                                                         endpoint. */
+        uint32_t cnak                    : 1;       /**< Clear NAK (CNAK)
+                                                         A write to this bit clears the NAK bit for the endpoint. */
+        uint32_t reserved_22_25          : 4;
+        uint32_t stall                   : 1;       /**< STALL Handshake (Stall)
+                                                         For non-control, non-isochronous endpoints:
+                                                          The application sets this bit to stall all tokens from the USB host
+                                                          to this endpoint.  If a NAK bit, Global Non-Periodic IN NAK, or
+                                                          Global OUT NAK is set along with this bit, the STALL bit takes
+                                                          priority.  Only the application can clear this bit, never the core.
+                                                         For control endpoints:
+                                                          The application can only set this bit, and the core clears it, when
+                                                          a SETUP token i received for this endpoint.  If a NAK bit, Global
+                                                          Non-Periodic IN NAK, or Global OUT NAK is set along with this
+                                                          bit, the STALL bit takes priority.  Irrespective of this bit's setting,
+                                                          the core always responds to SETUP data packets with an ACK handshake. */
+        uint32_t snp                     : 1;       /**< Snoop Mode (Snp)
+                                                         This bit configures the endpoint to Snoop mode.  In Snoop mode,
+                                                         the core does not check the correctness of OUT packets before
+                                                         transferring them to application memory. */
+        uint32_t eptype                  : 2;       /**< Endpoint Type (EPType)
+                                                         This is the transfer type supported by this logical endpoint.
+                                                         * 2'b00: Control
+                                                         * 2'b01: Isochronous
+                                                         * 2'b10: Bulk
+                                                         * 2'b11: Interrupt */
+        uint32_t naksts                  : 1;       /**< NAK Status (NAKSts)
+                                                         Indicates the following:
+                                                         * 1'b0: The core is transmitting non-NAK handshakes based
+                                                                 on the FIFO status
+                                                         * 1'b1: The core is transmitting NAK handshakes on this
+                                                                 endpoint.
+                                                         When either the application or the core sets this bit:
+                                                         * The core stops receiving any data on an OUT endpoint, even
+                                                           if there is space in the RxFIFO to accomodate the incoming
+                                                           packet. */
+        uint32_t dpid                    : 1;       /**< For interrupt/bulk IN and OUT endpoints:
+                                                          Endpoint Data PID (DPID)
+                                                          Contains the PID of the packet to be received or transmitted on
+                                                          this endpoint.  The application should program the PID of the first
+                                                          packet to be received or transmitted on this endpoint, after the
+                                                          endpoint is activated.  Applications use the SetD1PID and
+                                                          SetD0PID fields of this register to program either DATA0 or
+                                                          DATA1 PID.
+                                                          * 1'b0: DATA0
+                                                          * 1'b1: DATA1
+                                                         For isochronous IN and OUT endpoints:
+                                                          Even/Odd (Micro)Frame (EO_FrNum)
+                                                          Indicates the (micro)frame number in which the core transmits/
+                                                          receives isochronous data for this endpoint.  The application
+                                                          should program the even/odd (micro) frame number in which it
+                                                          intends to transmit/receive isochronous data for this endpoint
+                                                          using the SetEvnFr and SetOddFr fields in this register.
+                                                          * 1'b0: Even (micro)frame
+                                                          * 1'b1: Odd (micro)frame */
+        uint32_t usbactep                : 1;       /**< USB Active Endpoint (USBActEP)
+                                                         Indicates whether this endpoint is active in the current
+                                                         configuration and interface.  The core clears this bit for all
+                                                         endpoints (other than EP 0) after detecting a USB reset.  After
+                                                         receiving the SetConfiguration and SetInterface commands, the
+                                                         application must program endpoint registers accordingly and set
+                                                         this bit. */
+        uint32_t reserved_11_14          : 4;
+        uint32_t mps                     : 11;      /**< Maximum Packet Size (MPS)
+                                                         Applies to IN and OUT endpoints.
+                                                         The application must program this field with the maximum
+                                                         packet size for the current logical endpoint.  This value is in
+                                                         bytes. */
+#else
+        uint32_t mps                     : 11;
+        uint32_t reserved_11_14          : 4;
+        uint32_t usbactep                : 1;
+        uint32_t dpid                    : 1;
+        uint32_t naksts                  : 1;
+        uint32_t eptype                  : 2;
+        uint32_t snp                     : 1;
+        uint32_t stall                   : 1;
+        uint32_t reserved_22_25          : 4;
+        uint32_t cnak                    : 1;
+        uint32_t snak                    : 1;
+        uint32_t setd0pid                : 1;
+        uint32_t setd1pid                : 1;
+        uint32_t epdis                   : 1;
+        uint32_t epena                   : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_doepctlx_s         cn30xx;
+    struct cvmx_usbcx_doepctlx_s         cn31xx;
+    struct cvmx_usbcx_doepctlx_s         cn50xx;
+    struct cvmx_usbcx_doepctlx_s         cn52xx;
+    struct cvmx_usbcx_doepctlx_s         cn52xxp1;
+    struct cvmx_usbcx_doepctlx_s         cn56xx;
+    struct cvmx_usbcx_doepctlx_s         cn56xxp1;
+} cvmx_usbcx_doepctlx_t;
+
+
+/**
+ * cvmx_usbc#_doepint#
+ *
+ * Device Endpoint-n Interrupt Register (DOEPINTn)
+ * 
+ * This register indicates the status of an endpoint with respect to USB- and AHB-related events.
+ * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints
+ * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively)
+ * is set. Before the application can read this register, it must first read the Device All
+ * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n
+ * Interrupt register. The application must clear the appropriate bit in this register to clear the
+ * corresponding bits in the DAINT and GINTSTS registers.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_doepintx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t outtknepdis             : 1;       /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis)
+                                                         Applies only to control OUT endpoints.
+                                                         Indicates that an OUT token was received when the endpoint
+                                                         was not yet enabled. This interrupt is asserted on the endpoint
+                                                         for which the OUT token was received. */
+        uint32_t setup                   : 1;       /**< SETUP Phase Done (SetUp)
+                                                         Applies to control OUT endpoints only.
+                                                         Indicates that the SETUP phase for the control endpoint is
+                                                         complete and no more back-to-back SETUP packets were
+                                                         received for the current control transfer. On this interrupt, the
+                                                         application can decode the received SETUP data packet. */
+        uint32_t ahberr                  : 1;       /**< AHB Error (AHBErr)
+                                                         This is generated only in Internal DMA mode when there is an
+                                                         AHB error during an AHB read/write. The application can read
+                                                         the corresponding endpoint DMA address register to get the
+                                                         error address. */
+        uint32_t epdisbld                : 1;       /**< Endpoint Disabled Interrupt (EPDisbld)
+                                                         This bit indicates that the endpoint is disabled per the
+                                                         application's request. */
+        uint32_t xfercompl               : 1;       /**< Transfer Completed Interrupt (XferCompl)
+                                                         Indicates that the programmed transfer is complete on the AHB
+                                                         as well as on the USB, for this endpoint. */
+#else
+        uint32_t xfercompl               : 1;
+        uint32_t epdisbld                : 1;
+        uint32_t ahberr                  : 1;
+        uint32_t setup                   : 1;
+        uint32_t outtknepdis             : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_usbcx_doepintx_s         cn30xx;
+    struct cvmx_usbcx_doepintx_s         cn31xx;
+    struct cvmx_usbcx_doepintx_s         cn50xx;
+    struct cvmx_usbcx_doepintx_s         cn52xx;
+    struct cvmx_usbcx_doepintx_s         cn52xxp1;
+    struct cvmx_usbcx_doepintx_s         cn56xx;
+    struct cvmx_usbcx_doepintx_s         cn56xxp1;
+} cvmx_usbcx_doepintx_t;
+
+
+/**
+ * cvmx_usbc#_doepmsk
+ *
+ * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK)
+ * 
+ * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers
+ * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt
+ * for a specific status in the DOEPINTn register can be masked by writing into the
+ * corresponding bit in this register. Status bits are masked by default.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_doepmsk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t outtknepdismsk          : 1;       /**< OUT Token Received when Endpoint Disabled Mask
+                                                         (OUTTknEPdisMsk)
+                                                         Applies to control OUT endpoints only. */
+        uint32_t setupmsk                : 1;       /**< SETUP Phase Done Mask (SetUPMsk)
+                                                         Applies to control endpoints only. */
+        uint32_t ahberrmsk               : 1;       /**< AHB Error (AHBErrMsk) */
+        uint32_t epdisbldmsk             : 1;       /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
+        uint32_t xfercomplmsk            : 1;       /**< Transfer Completed Interrupt Mask (XferComplMsk) */
+#else
+        uint32_t xfercomplmsk            : 1;
+        uint32_t epdisbldmsk             : 1;
+        uint32_t ahberrmsk               : 1;
+        uint32_t setupmsk                : 1;
+        uint32_t outtknepdismsk          : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_usbcx_doepmsk_s          cn30xx;
+    struct cvmx_usbcx_doepmsk_s          cn31xx;
+    struct cvmx_usbcx_doepmsk_s          cn50xx;
+    struct cvmx_usbcx_doepmsk_s          cn52xx;
+    struct cvmx_usbcx_doepmsk_s          cn52xxp1;
+    struct cvmx_usbcx_doepmsk_s          cn56xx;
+    struct cvmx_usbcx_doepmsk_s          cn56xxp1;
+} cvmx_usbcx_doepmsk_t;
+
+
+/**
+ * cvmx_usbc#_doeptsiz#
+ *
+ * Device Endpoint-n Transfer Size Register (DOEPTSIZn)
+ * 
+ * The application must modify this register before enabling the endpoint.
+ * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
+ * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application
+ * can only read this register once the core has cleared the Endpoint Enable bit.
+ * This register is used only for endpoints other than Endpoint 0.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_doeptsizx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_31_31          : 1;
+        uint32_t mc                      : 2;       /**< Multi Count (MC)
+                                                         Received Data PID (RxDPID)
+                                                         Applies to isochronous OUT endpoints only.
+                                                         This is the data PID received in the last packet for this endpoint.
+                                                         2'b00: DATA0
+                                                         2'b01: DATA1
+                                                         2'b10: DATA2
+                                                         2'b11: MDATA
+                                                         SETUP Packet Count (SUPCnt)
+                                                         Applies to control OUT Endpoints only.
+                                                         This field specifies the number of back-to-back SETUP data
+                                                         packets the endpoint can receive.
+                                                         2'b01: 1 packet
+                                                         2'b10: 2 packets
+                                                         2'b11: 3 packets */
+        uint32_t pktcnt                  : 10;      /**< Packet Count (PktCnt)
+                                                         Indicates the total number of USB packets that constitute the
+                                                         Transfer Size amount of data for this endpoint.
+                                                         OUT Endpoints: This field is decremented every time a
+                                                         packet (maximum size or short packet) is written to the
+                                                         RxFIFO. */
+        uint32_t xfersize                : 19;      /**< Transfer Size (XferSize)
+                                                         This field contains the transfer size in bytes for the current
+                                                         endpoint.
+                                                         The core only interrupts the application after it has exhausted
+                                                         the transfer size amount of data. The transfer size can be set to
+                                                         the maximum packet size of the endpoint, to be interrupted at
+                                                         the end of each packet.
+                                                         OUT Endpoints: The core decrements this field every time a
+                                                         packet is read from the RxFIFO and written to the external
+                                                         memory. */
+#else
+        uint32_t xfersize                : 19;
+        uint32_t pktcnt                  : 10;
+        uint32_t mc                      : 2;
+        uint32_t reserved_31_31          : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_doeptsizx_s        cn30xx;
+    struct cvmx_usbcx_doeptsizx_s        cn31xx;
+    struct cvmx_usbcx_doeptsizx_s        cn50xx;
+    struct cvmx_usbcx_doeptsizx_s        cn52xx;
+    struct cvmx_usbcx_doeptsizx_s        cn52xxp1;
+    struct cvmx_usbcx_doeptsizx_s        cn56xx;
+    struct cvmx_usbcx_doeptsizx_s        cn56xxp1;
+} cvmx_usbcx_doeptsizx_t;
+
+
+/**
+ * cvmx_usbc#_dptxfsiz#
+ *
+ * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ)
+ * 
+ * This register holds the memory start address of each periodic TxFIFO to implemented
+ * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
+ * This register is repeated for each periodic FIFO instantiated.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dptxfsizx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dptxfsize               : 16;      /**< Device Periodic TxFIFO Size (DPTxFSize)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 4
+                                                         * Maximum value is 768 */
+        uint32_t dptxfstaddr             : 16;      /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr)
+                                                         Holds the start address in the RAM for this periodic FIFO. */
+#else
+        uint32_t dptxfstaddr             : 16;
+        uint32_t dptxfsize               : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_dptxfsizx_s        cn30xx;
+    struct cvmx_usbcx_dptxfsizx_s        cn31xx;
+    struct cvmx_usbcx_dptxfsizx_s        cn50xx;
+    struct cvmx_usbcx_dptxfsizx_s        cn52xx;
+    struct cvmx_usbcx_dptxfsizx_s        cn52xxp1;
+    struct cvmx_usbcx_dptxfsizx_s        cn56xx;
+    struct cvmx_usbcx_dptxfsizx_s        cn56xxp1;
+} cvmx_usbcx_dptxfsizx_t;
+
+
+/**
+ * cvmx_usbc#_dsts
+ *
+ * Device Status Register (DSTS)
+ * 
+ * This register indicates the status of the core with respect to USB-related events.
+ * It must be read on interrupts from Device All Interrupts (DAINT) register.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dsts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_22_31          : 10;
+        uint32_t soffn                   : 14;      /**< Frame or Microframe Number of the Received SOF (SOFFN)
+                                                         When the core is operating at high speed, this field contains a
+                                                         microframe number. When the core is operating at full or low
+                                                         speed, this field contains a frame number. */
+        uint32_t reserved_4_7            : 4;
+        uint32_t errticerr               : 1;       /**< Erratic Error (ErrticErr)
+                                                         The core sets this bit to report any erratic errors
+                                                         (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at
+                                                         least 2 ms, due to PHY error) seen on the UTMI+.
+                                                         Due to erratic errors, the O2P USB core goes into Suspended
+                                                         state and an interrupt is generated to the application with Early
+                                                         Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
+                                                         If the early suspend is asserted due to an erratic error, the
+                                                         application can only perform a soft disconnect recover. */
+        uint32_t enumspd                 : 2;       /**< Enumerated Speed (EnumSpd)
+                                                         Indicates the speed at which the O2P USB core has come up
+                                                         after speed detection through a chirp sequence.
+                                                         * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
+                                                         * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
+                                                         * 2'b10: Low speed (PHY clock is running at 6 MHz)
+                                                         * 2'b11: Full speed (PHY clock is running at 48 MHz)
+                                                         Low speed is not supported for devices using a UTMI+ PHY. */
+        uint32_t suspsts                 : 1;       /**< Suspend Status (SuspSts)
+                                                         In Device mode, this bit is set as long as a Suspend condition is
+                                                         detected on the USB. The core enters the Suspended state
+                                                         when there is no activity on the phy_line_state_i signal for an
+                                                         extended period of time. The core comes out of the suspend:
+                                                         * When there is any activity on the phy_line_state_i signal
+                                                         * When the application writes to the Remote Wakeup Signaling
+                                                           bit in the Device Control register (DCTL.RmtWkUpSig). */
+#else
+        uint32_t suspsts                 : 1;
+        uint32_t enumspd                 : 2;
+        uint32_t errticerr               : 1;
+        uint32_t reserved_4_7            : 4;
+        uint32_t soffn                   : 14;
+        uint32_t reserved_22_31          : 10;
+#endif
+    } s;
+    struct cvmx_usbcx_dsts_s             cn30xx;
+    struct cvmx_usbcx_dsts_s             cn31xx;
+    struct cvmx_usbcx_dsts_s             cn50xx;
+    struct cvmx_usbcx_dsts_s             cn52xx;
+    struct cvmx_usbcx_dsts_s             cn52xxp1;
+    struct cvmx_usbcx_dsts_s             cn56xx;
+    struct cvmx_usbcx_dsts_s             cn56xxp1;
+} cvmx_usbcx_dsts_t;
+
+
+/**
+ * cvmx_usbc#_dtknqr1
+ *
+ * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1)
+ * 
+ * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token
+ * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number.
+ * A read from this register returns the first 5 endpoint entries of the IN Token Sequence
+ * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest
+ * token is discarded.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dtknqr1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t eptkn                   : 24;      /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 5
+                                                         * Bits [27:24]: Endpoint number of Token 4
+                                                         - .......
+                                                         * Bits [15:12]: Endpoint number of Token 1
+                                                         * Bits [11:8]: Endpoint number of Token 0 */
+        uint32_t wrapbit                 : 1;       /**< Wrap Bit (WrapBit)
+                                                         This bit is set when the write pointer wraps. It is cleared when
+                                                         the learning queue is cleared. */
+        uint32_t reserved_5_6            : 2;
+        uint32_t intknwptr               : 5;       /**< IN Token Queue Write Pointer (INTknWPtr) */
+#else
+        uint32_t intknwptr               : 5;
+        uint32_t reserved_5_6            : 2;
+        uint32_t wrapbit                 : 1;
+        uint32_t eptkn                   : 24;
+#endif
+    } s;
+    struct cvmx_usbcx_dtknqr1_s          cn30xx;
+    struct cvmx_usbcx_dtknqr1_s          cn31xx;
+    struct cvmx_usbcx_dtknqr1_s          cn50xx;
+    struct cvmx_usbcx_dtknqr1_s          cn52xx;
+    struct cvmx_usbcx_dtknqr1_s          cn52xxp1;
+    struct cvmx_usbcx_dtknqr1_s          cn56xx;
+    struct cvmx_usbcx_dtknqr1_s          cn56xxp1;
+} cvmx_usbcx_dtknqr1_t;
+
+
+/**
+ * cvmx_usbc#_dtknqr2
+ *
+ * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2)
+ * 
+ * A read from this register returns the next 8 endpoint entries of the learning queue.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dtknqr2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t eptkn                   : 32;      /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 13
+                                                         * Bits [27:24]: Endpoint number of Token 12
+                                                         - .......
+                                                         * Bits [7:4]: Endpoint number of Token 7
+                                                         * Bits [3:0]: Endpoint number of Token 6 */
+#else
+        uint32_t eptkn                   : 32;
+#endif
+    } s;
+    struct cvmx_usbcx_dtknqr2_s          cn30xx;
+    struct cvmx_usbcx_dtknqr2_s          cn31xx;
+    struct cvmx_usbcx_dtknqr2_s          cn50xx;
+    struct cvmx_usbcx_dtknqr2_s          cn52xx;
+    struct cvmx_usbcx_dtknqr2_s          cn52xxp1;
+    struct cvmx_usbcx_dtknqr2_s          cn56xx;
+    struct cvmx_usbcx_dtknqr2_s          cn56xxp1;
+} cvmx_usbcx_dtknqr2_t;
+
+
+/**
+ * cvmx_usbc#_dtknqr3
+ *
+ * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3)
+ * 
+ * A read from this register returns the next 8 endpoint entries of the learning queue.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dtknqr3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t eptkn                   : 32;      /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 21
+                                                         * Bits [27:24]: Endpoint number of Token 20
+                                                         - .......
+                                                         * Bits [7:4]: Endpoint number of Token 15
+                                                         * Bits [3:0]: Endpoint number of Token 14 */
+#else
+        uint32_t eptkn                   : 32;
+#endif
+    } s;
+    struct cvmx_usbcx_dtknqr3_s          cn30xx;
+    struct cvmx_usbcx_dtknqr3_s          cn31xx;
+    struct cvmx_usbcx_dtknqr3_s          cn50xx;
+    struct cvmx_usbcx_dtknqr3_s          cn52xx;
+    struct cvmx_usbcx_dtknqr3_s          cn52xxp1;
+    struct cvmx_usbcx_dtknqr3_s          cn56xx;
+    struct cvmx_usbcx_dtknqr3_s          cn56xxp1;
+} cvmx_usbcx_dtknqr3_t;
+
+
+/**
+ * cvmx_usbc#_dtknqr4
+ *
+ * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4)
+ * 
+ * A read from this register returns the last 8 endpoint entries of the learning queue.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_dtknqr4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t eptkn                   : 32;      /**< Endpoint Token (EPTkn)
+                                                         Four bits per token represent the endpoint number of the token:
+                                                         * Bits [31:28]: Endpoint number of Token 29
+                                                         * Bits [27:24]: Endpoint number of Token 28
+                                                         - .......
+                                                         * Bits [7:4]: Endpoint number of Token 23
+                                                         * Bits [3:0]: Endpoint number of Token 22 */
+#else
+        uint32_t eptkn                   : 32;
+#endif
+    } s;
+    struct cvmx_usbcx_dtknqr4_s          cn30xx;
+    struct cvmx_usbcx_dtknqr4_s          cn31xx;
+    struct cvmx_usbcx_dtknqr4_s          cn50xx;
+    struct cvmx_usbcx_dtknqr4_s          cn52xx;
+    struct cvmx_usbcx_dtknqr4_s          cn52xxp1;
+    struct cvmx_usbcx_dtknqr4_s          cn56xx;
+    struct cvmx_usbcx_dtknqr4_s          cn56xxp1;
+} cvmx_usbcx_dtknqr4_t;
+
+
+/**
+ * cvmx_usbc#_gahbcfg
+ *
+ * Core AHB Configuration Register (GAHBCFG)
+ * 
+ * This register can be used to configure the core after power-on or a change in mode of operation.
+ * This register mainly contains AHB system-related configuration parameters. The AHB is the processor
+ * interface to the O2P USB core. In general, software need not know about this interface except to
+ * program the values as specified.
+ * 
+ * The application must program this register as part of the O2P USB core initialization.
+ * Do not change this register after the initial programming.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gahbcfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_9_31           : 23;
+        uint32_t ptxfemplvl              : 1;       /**< Periodic TxFIFO Empty Level (PTxFEmpLvl)
+                                                         Software should set this bit to 0x1.
+                                                         Indicates when the Periodic TxFIFO Empty Interrupt bit in the
+                                                         Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
+                                                         bit is used only in Slave mode.
+                                                         * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
+                                                           TxFIFO is half empty
+                                                         * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
+                                                           TxFIFO is completely empty */
+        uint32_t nptxfemplvl             : 1;       /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
+                                                         Software should set this bit to 0x1.
+                                                         Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
+                                                         the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
+                                                         This bit is used only in Slave mode.
+                                                         * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
+                                                            Periodic TxFIFO is half empty
+                                                         * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
+                                                            Periodic TxFIFO is completely empty */
+        uint32_t reserved_6_6            : 1;
+        uint32_t dmaen                   : 1;       /**< DMA Enable (DMAEn)
+                                                         * 1'b0: Core operates in Slave mode
+                                                         * 1'b1: Core operates in a DMA mode */
+        uint32_t hbstlen                 : 4;       /**< Burst Length/Type (HBstLen)
+                                                         This field has not effect and should be left as 0x0. */
+        uint32_t glblintrmsk             : 1;       /**< Global Interrupt Mask (GlblIntrMsk)
+                                                         Software should set this field to 0x1.
+                                                         The application uses this bit to mask  or unmask the interrupt
+                                                         line assertion to itself. Irrespective of this bit's setting, the
+                                                         interrupt status registers are updated by the core.
+                                                         * 1'b0: Mask the interrupt assertion to the application.
+                                                         * 1'b1: Unmask the interrupt assertion to the application. */
+#else
+        uint32_t glblintrmsk             : 1;
+        uint32_t hbstlen                 : 4;
+        uint32_t dmaen                   : 1;
+        uint32_t reserved_6_6            : 1;
+        uint32_t nptxfemplvl             : 1;
+        uint32_t ptxfemplvl              : 1;
+        uint32_t reserved_9_31           : 23;
+#endif
+    } s;
+    struct cvmx_usbcx_gahbcfg_s          cn30xx;
+    struct cvmx_usbcx_gahbcfg_s          cn31xx;
+    struct cvmx_usbcx_gahbcfg_s          cn50xx;
+    struct cvmx_usbcx_gahbcfg_s          cn52xx;
+    struct cvmx_usbcx_gahbcfg_s          cn52xxp1;
+    struct cvmx_usbcx_gahbcfg_s          cn56xx;
+    struct cvmx_usbcx_gahbcfg_s          cn56xxp1;
+} cvmx_usbcx_gahbcfg_t;
+
+
+/**
+ * cvmx_usbc#_ghwcfg1
+ *
+ * User HW Config1 Register (GHWCFG1)
+ * 
+ * This register contains the logical endpoint direction(s) of the O2P USB core.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_ghwcfg1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t epdir                   : 32;      /**< Endpoint Direction (epdir)
+                                                         Two bits per endpoint represent the direction.
+                                                         * 2'b00: BIDIR (IN and OUT) endpoint
+                                                         * 2'b01: IN endpoint
+                                                         * 2'b10: OUT endpoint
+                                                         * 2'b11: Reserved
+                                                         Bits [31:30]: Endpoint 15 direction
+                                                         Bits [29:28]: Endpoint 14 direction
+                                                         - ...
+                                                         Bits [3:2]: Endpoint 1 direction
+                                                         Bits[1:0]: Endpoint 0 direction (always BIDIR) */
+#else
+        uint32_t epdir                   : 32;
+#endif
+    } s;
+    struct cvmx_usbcx_ghwcfg1_s          cn30xx;
+    struct cvmx_usbcx_ghwcfg1_s          cn31xx;
+    struct cvmx_usbcx_ghwcfg1_s          cn50xx;
+    struct cvmx_usbcx_ghwcfg1_s          cn52xx;
+    struct cvmx_usbcx_ghwcfg1_s          cn52xxp1;
+    struct cvmx_usbcx_ghwcfg1_s          cn56xx;
+    struct cvmx_usbcx_ghwcfg1_s          cn56xxp1;
+} cvmx_usbcx_ghwcfg1_t;
+
+
+/**
+ * cvmx_usbc#_ghwcfg2
+ *
+ * User HW Config2 Register (GHWCFG2)
+ * 
+ * This register contains configuration options of the O2P USB core.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_ghwcfg2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_31_31          : 1;
+        uint32_t tknqdepth               : 5;       /**< Device Mode IN Token Sequence Learning Queue Depth
+                                                         (TknQDepth)
+                                                         Range: 0-30 */
+        uint32_t ptxqdepth               : 2;       /**< Host Mode Periodic Request Queue Depth (PTxQDepth)
+                                                         * 2'b00: 2
+                                                         * 2'b01: 4
+                                                         * 2'b10: 8
+                                                         * Others: Reserved */
+        uint32_t nptxqdepth              : 2;       /**< Non-Periodic Request Queue Depth (NPTxQDepth)
+                                                         * 2'b00: 2
+                                                         * 2'b01: 4
+                                                         * 2'b10: 8
+                                                         * Others: Reserved */
+        uint32_t reserved_20_21          : 2;
+        uint32_t dynfifosizing           : 1;       /**< Dynamic FIFO Sizing Enabled (DynFifoSizing)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+        uint32_t periosupport            : 1;       /**< Periodic OUT Channels Supported in Host Mode
+                                                         (PerioSupport)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+        uint32_t numhstchnl              : 4;       /**< Number of Host Channels (NumHstChnl)
+                                                         Indicates the number of host channels supported by the core in
+                                                         Host mode. The range of this field is 0-15: 0 specifies 1
+                                                         channel, 15 specifies 16 channels. */
+        uint32_t numdeveps               : 4;       /**< Number of Device Endpoints (NumDevEps)
+                                                         Indicates the number of device endpoints supported by the core
+                                                         in Device mode in addition to control endpoint 0. The range of
+                                                         this field is 1-15. */
+        uint32_t fsphytype               : 2;       /**< Full-Speed PHY Interface Type (FSPhyType)
+                                                         * 2'b00: Full-speed interface not supported
+                                                         * 2'b01: Dedicated full-speed interface
+                                                         * 2'b10: FS pins shared with UTMI+ pins
+                                                         * 2'b11: FS pins shared with ULPI pins */
+        uint32_t hsphytype               : 2;       /**< High-Speed PHY Interface Type (HSPhyType)
+                                                         * 2'b00: High-Speed interface not supported
+                                                         * 2'b01: UTMI+
+                                                         * 2'b10: ULPI
+                                                         * 2'b11: UTMI+ and ULPI */
+        uint32_t singpnt                 : 1;       /**< Point-to-Point (SingPnt)
+                                                         * 1'b0: Multi-point application
+                                                         * 1'b1: Single-point application */
+        uint32_t otgarch                 : 2;       /**< Architecture (OtgArch)
+                                                         * 2'b00: Slave-Only
+                                                         * 2'b01: External DMA
+                                                         * 2'b10: Internal DMA
+                                                         * Others: Reserved */
+        uint32_t otgmode                 : 3;       /**< Mode of Operation (OtgMode)
+                                                         * 3'b000: HNP- and SRP-Capable OTG (Host & Device)
+                                                         * 3'b001: SRP-Capable OTG (Host & Device)
+                                                         * 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
+                                                         Device)
+                                                         * 3'b011: SRP-Capable Device
+                                                         * 3'b100: Non-OTG Device
+                                                         * 3'b101: SRP-Capable Host
+                                                         * 3'b110: Non-OTG Host
+                                                         * Others: Reserved */
+#else
+        uint32_t otgmode                 : 3;
+        uint32_t otgarch                 : 2;
+        uint32_t singpnt                 : 1;
+        uint32_t hsphytype               : 2;
+        uint32_t fsphytype               : 2;
+        uint32_t numdeveps               : 4;
+        uint32_t numhstchnl              : 4;
+        uint32_t periosupport            : 1;
+        uint32_t dynfifosizing           : 1;
+        uint32_t reserved_20_21          : 2;
+        uint32_t nptxqdepth              : 2;
+        uint32_t ptxqdepth               : 2;
+        uint32_t tknqdepth               : 5;
+        uint32_t reserved_31_31          : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_ghwcfg2_s          cn30xx;
+    struct cvmx_usbcx_ghwcfg2_s          cn31xx;
+    struct cvmx_usbcx_ghwcfg2_s          cn50xx;
+    struct cvmx_usbcx_ghwcfg2_s          cn52xx;
+    struct cvmx_usbcx_ghwcfg2_s          cn52xxp1;
+    struct cvmx_usbcx_ghwcfg2_s          cn56xx;
+    struct cvmx_usbcx_ghwcfg2_s          cn56xxp1;
+} cvmx_usbcx_ghwcfg2_t;
+
+
+/**
+ * cvmx_usbc#_ghwcfg3
+ *
+ * User HW Config3 Register (GHWCFG3)
+ * 
+ * This register contains the configuration options of the O2P USB core.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_ghwcfg3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dfifodepth              : 16;      /**< DFIFO Depth (DfifoDepth)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 32
+                                                         * Maximum value is 32768 */
+        uint32_t reserved_13_15          : 3;
+        uint32_t ahbphysync              : 1;       /**< AHB and PHY Synchronous (AhbPhySync)
+                                                         Indicates whether AHB and PHY clocks are synchronous to
+                                                         each other.
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes
+                                                         This bit is tied to 1. */
+        uint32_t rsttype                 : 1;       /**< Reset Style for Clocked always Blocks in RTL (RstType)
+                                                         * 1'b0: Asynchronous reset is used in the core
+                                                         * 1'b1: Synchronous reset is used in the core */
+        uint32_t optfeature              : 1;       /**< Optional Features Removed (OptFeature)
+                                                         Indicates whether the User ID register, GPIO interface ports,
+                                                         and SOF toggle and counter ports were removed for gate count
+                                                         optimization. */
+        uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support
+                                                         * 1'b0: Vendor Control Interface is not available on the core.
+                                                         * 1'b1: Vendor Control Interface is available. */
+        uint32_t i2c_selection           : 1;       /**< I2C Selection
+                                                         * 1'b0: I2C Interface is not available on the core.
+                                                         * 1'b1: I2C Interface is available on the core. */
+        uint32_t otgen                   : 1;       /**< OTG Function Enabled (OtgEn)
+                                                         The application uses this bit to indicate the O2P USB core's
+                                                         OTG capabilities.
+                                                         * 1'b0: Not OTG capable
+                                                         * 1'b1: OTG Capable */
+        uint32_t pktsizewidth            : 3;       /**< Width of Packet Size Counters (PktSizeWidth)
+                                                         * 3'b000: 4 bits
+                                                         * 3'b001: 5 bits
+                                                         * 3'b010: 6 bits
+                                                         * 3'b011: 7 bits
+                                                         * 3'b100: 8 bits
+                                                         * 3'b101: 9 bits
+                                                         * 3'b110: 10 bits
+                                                         * Others: Reserved */
+        uint32_t xfersizewidth           : 4;       /**< Width of Transfer Size Counters (XferSizeWidth)
+                                                         * 4'b0000: 11 bits
+                                                         * 4'b0001: 12 bits
+                                                         - ...
+                                                         * 4'b1000: 19 bits
+                                                         * Others: Reserved */
+#else
+        uint32_t xfersizewidth           : 4;
+        uint32_t pktsizewidth            : 3;
+        uint32_t otgen                   : 1;
+        uint32_t i2c_selection           : 1;
+        uint32_t vendor_control_interface_support : 1;
+        uint32_t optfeature              : 1;
+        uint32_t rsttype                 : 1;
+        uint32_t ahbphysync              : 1;
+        uint32_t reserved_13_15          : 3;
+        uint32_t dfifodepth              : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_ghwcfg3_s          cn30xx;
+    struct cvmx_usbcx_ghwcfg3_s          cn31xx;
+    struct cvmx_usbcx_ghwcfg3_s          cn50xx;
+    struct cvmx_usbcx_ghwcfg3_s          cn52xx;
+    struct cvmx_usbcx_ghwcfg3_s          cn52xxp1;
+    struct cvmx_usbcx_ghwcfg3_s          cn56xx;
+    struct cvmx_usbcx_ghwcfg3_s          cn56xxp1;
+} cvmx_usbcx_ghwcfg3_t;
+
+
+/**
+ * cvmx_usbc#_ghwcfg4
+ *
+ * User HW Config4 Register (GHWCFG4)
+ * 
+ * This register contains the configuration options of the O2P USB core.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_ghwcfg4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_30_31          : 2;
+        uint32_t numdevmodinend          : 4;       /**< Enable dedicatd transmit FIFO for device IN endpoints. */
+        uint32_t endedtrfifo             : 1;       /**< Enable dedicatd transmit FIFO for device IN endpoints. */
+        uint32_t sessendfltr             : 1;       /**< "session_end" Filter Enabled (SessEndFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t bvalidfltr              : 1;       /**< "b_valid" Filter Enabled (BValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t avalidfltr              : 1;       /**< "a_valid" Filter Enabled (AValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t vbusvalidfltr           : 1;       /**< "vbus_valid" Filter Enabled (VBusValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t iddgfltr                : 1;       /**< "iddig" Filter Enable (IddgFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t numctleps               : 4;       /**< Number of Device Mode Control Endpoints in Addition to
+                                                         Endpoint 0 (NumCtlEps)
+                                                         Range: 1-15 */
+        uint32_t phydatawidth            : 2;       /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
+                                                         (PhyDataWidth)
+                                                         When a ULPI PHY is used, an internal wrapper converts ULPI
+                                                         to UTMI+.
+                                                         * 2'b00: 8 bits
+                                                         * 2'b01: 16 bits
+                                                         * 2'b10: 8/16 bits, software selectable
+                                                         * Others: Reserved */
+        uint32_t reserved_6_13           : 8;
+        uint32_t ahbfreq                 : 1;       /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+        uint32_t enablepwropt            : 1;       /**< Enable Power Optimization? (EnablePwrOpt)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+        uint32_t numdevperioeps          : 4;       /**< Number of Device Mode Periodic IN Endpoints
+                                                         (NumDevPerioEps)
+                                                         Range: 0-15 */
+#else
+        uint32_t numdevperioeps          : 4;
+        uint32_t enablepwropt            : 1;
+        uint32_t ahbfreq                 : 1;
+        uint32_t reserved_6_13           : 8;
+        uint32_t phydatawidth            : 2;
+        uint32_t numctleps               : 4;
+        uint32_t iddgfltr                : 1;
+        uint32_t vbusvalidfltr           : 1;
+        uint32_t avalidfltr              : 1;
+        uint32_t bvalidfltr              : 1;
+        uint32_t sessendfltr             : 1;
+        uint32_t endedtrfifo             : 1;
+        uint32_t numdevmodinend          : 4;
+        uint32_t reserved_30_31          : 2;
+#endif
+    } s;
+    struct cvmx_usbcx_ghwcfg4_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_25_31          : 7;
+        uint32_t sessendfltr             : 1;       /**< "session_end" Filter Enabled (SessEndFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t bvalidfltr              : 1;       /**< "b_valid" Filter Enabled (BValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t avalidfltr              : 1;       /**< "a_valid" Filter Enabled (AValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t vbusvalidfltr           : 1;       /**< "vbus_valid" Filter Enabled (VBusValidFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t iddgfltr                : 1;       /**< "iddig" Filter Enable (IddgFltr)
+                                                         * 1'b0: No filter
+                                                         * 1'b1: Filter */
+        uint32_t numctleps               : 4;       /**< Number of Device Mode Control Endpoints in Addition to
+                                                         Endpoint 0 (NumCtlEps)
+                                                         Range: 1-15 */
+        uint32_t phydatawidth            : 2;       /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
+                                                         (PhyDataWidth)
+                                                         When a ULPI PHY is used, an internal wrapper converts ULPI
+                                                         to UTMI+.
+                                                         * 2'b00: 8 bits
+                                                         * 2'b01: 16 bits
+                                                         * 2'b10: 8/16 bits, software selectable
+                                                         * Others: Reserved */
+        uint32_t reserved_6_13           : 8;
+        uint32_t ahbfreq                 : 1;       /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+        uint32_t enablepwropt            : 1;       /**< Enable Power Optimization? (EnablePwrOpt)
+                                                         * 1'b0: No
+                                                         * 1'b1: Yes */
+        uint32_t numdevperioeps          : 4;       /**< Number of Device Mode Periodic IN Endpoints
+                                                         (NumDevPerioEps)
+                                                         Range: 0-15 */
+#else
+        uint32_t numdevperioeps          : 4;
+        uint32_t enablepwropt            : 1;
+        uint32_t ahbfreq                 : 1;
+        uint32_t reserved_6_13           : 8;
+        uint32_t phydatawidth            : 2;
+        uint32_t numctleps               : 4;
+        uint32_t iddgfltr                : 1;
+        uint32_t vbusvalidfltr           : 1;
+        uint32_t avalidfltr              : 1;
+        uint32_t bvalidfltr              : 1;
+        uint32_t sessendfltr             : 1;
+        uint32_t reserved_25_31          : 7;
+#endif
+    } cn30xx;
+    struct cvmx_usbcx_ghwcfg4_cn30xx     cn31xx;
+    struct cvmx_usbcx_ghwcfg4_s          cn50xx;
+    struct cvmx_usbcx_ghwcfg4_s          cn52xx;
+    struct cvmx_usbcx_ghwcfg4_s          cn52xxp1;
+    struct cvmx_usbcx_ghwcfg4_s          cn56xx;
+    struct cvmx_usbcx_ghwcfg4_s          cn56xxp1;
+} cvmx_usbcx_ghwcfg4_t;
+
+
+/**
+ * cvmx_usbc#_gintmsk
+ *
+ * Core Interrupt Mask Register (GINTMSK)
+ * 
+ * This register works with the Core Interrupt register to interrupt the application.
+ * When an interrupt bit is masked, the interrupt associated with that bit will not be generated.
+ * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
+ * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gintmsk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t wkupintmsk              : 1;       /**< Resume/Remote Wakeup Detected Interrupt Mask
+                                                         (WkUpIntMsk) */
+        uint32_t sessreqintmsk           : 1;       /**< Session Request/New Session Detected Interrupt Mask
+                                                         (SessReqIntMsk) */
+        uint32_t disconnintmsk           : 1;       /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */
+        uint32_t conidstschngmsk         : 1;       /**< Connector ID Status Change Mask (ConIDStsChngMsk) */
+        uint32_t reserved_27_27          : 1;
+        uint32_t ptxfempmsk              : 1;       /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */
+        uint32_t hchintmsk               : 1;       /**< Host Channels Interrupt Mask (HChIntMsk) */
+        uint32_t prtintmsk               : 1;       /**< Host Port Interrupt Mask (PrtIntMsk) */
+        uint32_t reserved_23_23          : 1;
+        uint32_t fetsuspmsk              : 1;       /**< Data Fetch Suspended Mask (FetSuspMsk) */
+        uint32_t incomplpmsk             : 1;       /**< Incomplete Periodic Transfer Mask (incomplPMsk)
+                                                         Incomplete Isochronous OUT Transfer Mask
+                                                         (incompISOOUTMsk) */
+        uint32_t incompisoinmsk          : 1;       /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */
+        uint32_t oepintmsk               : 1;       /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */
+        uint32_t inepintmsk              : 1;       /**< IN Endpoints Interrupt Mask (INEPIntMsk) */
+        uint32_t epmismsk                : 1;       /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */
+        uint32_t reserved_16_16          : 1;
+        uint32_t eopfmsk                 : 1;       /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */
+        uint32_t isooutdropmsk           : 1;       /**< Isochronous OUT Packet Dropped Interrupt Mask
+                                                         (ISOOutDropMsk) */
+        uint32_t enumdonemsk             : 1;       /**< Enumeration Done Mask (EnumDoneMsk) */
+        uint32_t usbrstmsk               : 1;       /**< USB Reset Mask (USBRstMsk) */
+        uint32_t usbsuspmsk              : 1;       /**< USB Suspend Mask (USBSuspMsk) */
+        uint32_t erlysuspmsk             : 1;       /**< Early Suspend Mask (ErlySuspMsk) */
+        uint32_t i2cint                  : 1;       /**< I2C Interrupt Mask (I2CINT) */
+        uint32_t ulpickintmsk            : 1;       /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk)
+                                                         I2C Carkit Interrupt Mask (I2CCKINTMsk) */
+        uint32_t goutnakeffmsk           : 1;       /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */
+        uint32_t ginnakeffmsk            : 1;       /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */
+        uint32_t nptxfempmsk             : 1;       /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */
+        uint32_t rxflvlmsk               : 1;       /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */
+        uint32_t sofmsk                  : 1;       /**< Start of (micro)Frame Mask (SofMsk) */
+        uint32_t otgintmsk               : 1;       /**< OTG Interrupt Mask (OTGIntMsk) */
+        uint32_t modemismsk              : 1;       /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */
+        uint32_t reserved_0_0            : 1;
+#else
+        uint32_t reserved_0_0            : 1;
+        uint32_t modemismsk              : 1;
+        uint32_t otgintmsk               : 1;
+        uint32_t sofmsk                  : 1;
+        uint32_t rxflvlmsk               : 1;
+        uint32_t nptxfempmsk             : 1;
+        uint32_t ginnakeffmsk            : 1;
+        uint32_t goutnakeffmsk           : 1;
+        uint32_t ulpickintmsk            : 1;
+        uint32_t i2cint                  : 1;
+        uint32_t erlysuspmsk             : 1;
+        uint32_t usbsuspmsk              : 1;
+        uint32_t usbrstmsk               : 1;
+        uint32_t enumdonemsk             : 1;
+        uint32_t isooutdropmsk           : 1;
+        uint32_t eopfmsk                 : 1;
+        uint32_t reserved_16_16          : 1;
+        uint32_t epmismsk                : 1;
+        uint32_t inepintmsk              : 1;
+        uint32_t oepintmsk               : 1;
+        uint32_t incompisoinmsk          : 1;
+        uint32_t incomplpmsk             : 1;
+        uint32_t fetsuspmsk              : 1;
+        uint32_t reserved_23_23          : 1;
+        uint32_t prtintmsk               : 1;
+        uint32_t hchintmsk               : 1;
+        uint32_t ptxfempmsk              : 1;
+        uint32_t reserved_27_27          : 1;
+        uint32_t conidstschngmsk         : 1;
+        uint32_t disconnintmsk           : 1;
+        uint32_t sessreqintmsk           : 1;
+        uint32_t wkupintmsk              : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_gintmsk_s          cn30xx;
+    struct cvmx_usbcx_gintmsk_s          cn31xx;
+    struct cvmx_usbcx_gintmsk_s          cn50xx;
+    struct cvmx_usbcx_gintmsk_s          cn52xx;
+    struct cvmx_usbcx_gintmsk_s          cn52xxp1;
+    struct cvmx_usbcx_gintmsk_s          cn56xx;
+    struct cvmx_usbcx_gintmsk_s          cn56xxp1;
+} cvmx_usbcx_gintmsk_t;
+
+
+/**
+ * cvmx_usbc#_gintsts
+ *
+ * Core Interrupt Register (GINTSTS)
+ * 
+ * This register interrupts the application for system-level events in the current mode of operation
+ * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode,
+ * while others are valid in Device mode only. This register also indicates the current mode of operation.
+ * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
+ * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
+ * interrupts, FIFO interrupt conditions are cleared automatically.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gintsts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t wkupint                 : 1;       /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt)
+                                                         In Device mode, this interrupt is asserted when a resume is
+                                                         detected on the USB. In Host mode, this interrupt is asserted
+                                                         when a remote wakeup is detected on the USB.
+                                                         For more information on how to use this interrupt, see "Partial
+                                                         Power-Down and Clock Gating Programming Model" on
+                                                         page 353. */
+        uint32_t sessreqint              : 1;       /**< Session Request/New Session Detected Interrupt (SessReqInt)
+                                                         In Host mode, this interrupt is asserted when a session request
+                                                         is detected from the device. In Device mode, this interrupt is
+                                                         asserted when the utmiotg_bvalid signal goes high.
+                                                         For more information on how to use this interrupt, see "Partial
+                                                         Power-Down and Clock Gating Programming Model" on
+                                                         page 353. */
+        uint32_t disconnint              : 1;       /**< Disconnect Detected Interrupt (DisconnInt)
+                                                         Asserted when a device disconnect is detected. */
+        uint32_t conidstschng            : 1;       /**< Connector ID Status Change (ConIDStsChng)
+                                                         The core sets this bit when there is a change in connector ID
+                                                         status. */
+        uint32_t reserved_27_27          : 1;
+        uint32_t ptxfemp                 : 1;       /**< Periodic TxFIFO Empty (PTxFEmp)
+                                                         Asserted when the Periodic Transmit FIFO is either half or
+                                                         completely empty and there is space for at least one entry to be
+                                                         written in the Periodic Request Queue. The half or completely
+                                                         empty status is determined by the Periodic TxFIFO Empty Level
+                                                         bit in the Core AHB Configuration register
+                                                         (GAHBCFG.PTxFEmpLvl). */
+        uint32_t hchint                  : 1;       /**< Host Channels Interrupt (HChInt)
+                                                         The core sets this bit to indicate that an interrupt is pending on
+                                                         one of the channels of the core (in Host mode). The application
+                                                         must read the Host All Channels Interrupt (HAINT) register to
+                                                         determine the exact number of the channel on which the
+                                                         interrupt occurred, and then read the corresponding Host
+                                                         Channel-n Interrupt (HCINTn) register to determine the exact
+                                                         cause of the interrupt. The application must clear the
+                                                         appropriate status bit in the HCINTn register to clear this bit. */
+        uint32_t prtint                  : 1;       /**< Host Port Interrupt (PrtInt)
+                                                         The core sets this bit to indicate a change in port status of one
+                                                         of the O2P USB core ports in Host mode. The application must
+                                                         read the Host Port Control and Status (HPRT) register to
+                                                         determine the exact event that caused this interrupt. The
+                                                         application must clear the appropriate status bit in the Host Port
+                                                         Control and Status register to clear this bit. */
+        uint32_t reserved_23_23          : 1;
+        uint32_t fetsusp                 : 1;       /**< Data Fetch Suspended (FetSusp)
+                                                         This interrupt is valid only in DMA mode. This interrupt indicates
+                                                         that the core has stopped fetching data for IN endpoints due to
+                                                         the unavailability of TxFIFO space or Request Queue space.
+                                                         This interrupt is used by the application for an endpoint
+                                                         mismatch algorithm. */
+        uint32_t incomplp                : 1;       /**< Incomplete Periodic Transfer (incomplP)
+                                                         In Host mode, the core sets this interrupt bit when there are
+                                                         incomplete periodic transactions still pending which are
+                                                         scheduled for the current microframe.
+                                                         Incomplete Isochronous OUT Transfer (incompISOOUT)
+                                                         The Device mode, the core sets this interrupt to indicate that
+                                                         there is at least one isochronous OUT endpoint on which the
+                                                         transfer is not completed in the current microframe. This
+                                                         interrupt is asserted along with the End of Periodic Frame
+                                                         Interrupt (EOPF) bit in this register. */
+        uint32_t incompisoin             : 1;       /**< Incomplete Isochronous IN Transfer (incompISOIN)
+                                                         The core sets this interrupt to indicate that there is at least one
+                                                         isochronous IN endpoint on which the transfer is not completed
+                                                         in the current microframe. This interrupt is asserted along with
+                                                         the End of Periodic Frame Interrupt (EOPF) bit in this register. */
+        uint32_t oepint                  : 1;       /**< OUT Endpoints Interrupt (OEPInt)
+                                                         The core sets this bit to indicate that an interrupt is pending on
+                                                         one of the OUT endpoints of the core (in Device mode). The
+                                                         application must read the Device All Endpoints Interrupt
+                                                         (DAINT) register to determine the exact number of the OUT
+                                                         endpoint on which the interrupt occurred, and then read the
+                                                         corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
+                                                         register to determine the exact cause of the interrupt. The
+                                                         application must clear the appropriate status bit in the
+                                                         corresponding DOEPINTn register to clear this bit. */
+        uint32_t iepint                  : 1;       /**< IN Endpoints Interrupt (IEPInt)
+                                                         The core sets this bit to indicate that an interrupt is pending on
+                                                         one of the IN endpoints of the core (in Device mode). The
+                                                         application must read the Device All Endpoints Interrupt
+                                                         (DAINT) register to determine the exact number of the IN
+                                                         endpoint on which the interrupt occurred, and then read the
+                                                         corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
+                                                         register to determine the exact cause of the interrupt. The
+                                                         application must clear the appropriate status bit in the
+                                                         corresponding DIEPINTn register to clear this bit. */
+        uint32_t epmis                   : 1;       /**< Endpoint Mismatch Interrupt (EPMis)
+                                                         Indicates that an IN token has been received for a non-periodic
+                                                         endpoint, but the data for another endpoint is present in the top
+                                                         of the Non-Periodic Transmit FIFO and the IN endpoint
+                                                         mismatch count programmed by the application has expired. */
+        uint32_t reserved_16_16          : 1;
+        uint32_t eopf                    : 1;       /**< End of Periodic Frame Interrupt (EOPF)
+                                                         Indicates that the period specified in the Periodic Frame Interval
+                                                         field of the Device Configuration register (DCFG.PerFrInt) has
+                                                         been reached in the current microframe. */
+        uint32_t isooutdrop              : 1;       /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
+                                                         The core sets this bit when it fails to write an isochronous OUT
+                                                         packet into the RxFIFO because the RxFIFO doesn't have
+                                                         enough space to accommodate a maximum packet size packet
+                                                         for the isochronous OUT endpoint. */
+        uint32_t enumdone                : 1;       /**< Enumeration Done (EnumDone)
+                                                         The core sets this bit to indicate that speed enumeration is
+                                                         complete. The application must read the Device Status (DSTS)
+                                                         register to obtain the enumerated speed. */
+        uint32_t usbrst                  : 1;       /**< USB Reset (USBRst)
+                                                         The core sets this bit to indicate that a reset is detected on the
+                                                         USB. */
+        uint32_t usbsusp                 : 1;       /**< USB Suspend (USBSusp)
+                                                         The core sets this bit to indicate that a suspend was detected
+                                                         on the USB. The core enters the Suspended state when there
+                                                         is no activity on the phy_line_state_i signal for an extended
+                                                         period of time. */
+        uint32_t erlysusp                : 1;       /**< Early Suspend (ErlySusp)
+                                                         The core sets this bit to indicate that an Idle state has been
+                                                         detected on the USB for 3 ms. */
+        uint32_t i2cint                  : 1;       /**< I2C Interrupt (I2CINT)
+                                                         This bit is always 0x0. */
+        uint32_t ulpickint               : 1;       /**< ULPI Carkit Interrupt (ULPICKINT)
+                                                         This bit is always 0x0. */
+        uint32_t goutnakeff              : 1;       /**< Global OUT NAK Effective (GOUTNakEff)
+                                                         Indicates that the Set Global OUT NAK bit in the Device Control
+                                                         register (DCTL.SGOUTNak), set by the application, has taken
+                                                         effect in the core. This bit can be cleared by writing the Clear
+                                                         Global OUT NAK bit in the Device Control register
+                                                         (DCTL.CGOUTNak). */
+        uint32_t ginnakeff               : 1;       /**< Global IN Non-Periodic NAK Effective (GINNakEff)
+                                                         Indicates that the Set Global Non-Periodic IN NAK bit in the
+                                                         Device Control register (DCTL.SGNPInNak), set by the
+                                                         application, has taken effect in the core. That is, the core has
+                                                         sampled the Global IN NAK bit set by the application. This bit
+                                                         can be cleared by clearing the Clear Global Non-Periodic IN
+                                                         NAK bit in the Device Control register (DCTL.CGNPInNak).
+                                                         This interrupt does not necessarily mean that a NAK handshake
+                                                         is sent out on the USB. The STALL bit takes precedence over
+                                                         the NAK bit. */
+        uint32_t nptxfemp                : 1;       /**< Non-Periodic TxFIFO Empty (NPTxFEmp)
+                                                         This interrupt is asserted when the Non-Periodic TxFIFO is
+                                                         either half or completely empty, and there is space for at least
+                                                         one entry to be written to the Non-Periodic Transmit Request
+                                                         Queue. The half or completely empty status is determined by
+                                                         the Non-Periodic TxFIFO Empty Level bit in the Core AHB
+                                                         Configuration register (GAHBCFG.NPTxFEmpLvl). */
+        uint32_t rxflvl                  : 1;       /**< RxFIFO Non-Empty (RxFLvl)
+                                                         Indicates that there is at least one packet pending to be read
+                                                         from the RxFIFO. */
+        uint32_t sof                     : 1;       /**< Start of (micro)Frame (Sof)
+                                                         In Host mode, the core sets this bit to indicate that an SOF
+                                                         (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
+                                                         USB. The application must write a 1 to this bit to clear the
+                                                         interrupt.
+                                                         In Device mode, in the core sets this bit to indicate that an SOF
+                                                         token has been received on the USB. The application can read
+                                                         the Device Status register to get the current (micro)frame
+                                                         number. This interrupt is seen only when the core is operating
+                                                         at either HS or FS. */
+        uint32_t otgint                  : 1;       /**< OTG Interrupt (OTGInt)
+                                                         The core sets this bit to indicate an OTG protocol event. The
+                                                         application must read the OTG Interrupt Status (GOTGINT)
+                                                         register to determine the exact event that caused this interrupt.
+                                                         The application must clear the appropriate status bit in the
+                                                         GOTGINT register to clear this bit. */
+        uint32_t modemis                 : 1;       /**< Mode Mismatch Interrupt (ModeMis)
+                                                         The core sets this bit when the application is trying to access:
+                                                         * A Host mode register, when the core is operating in Device
+                                                         mode
+                                                         * A Device mode register, when the core is operating in Host
+                                                           mode
+                                                           The register access is completed on the AHB with an OKAY
+                                                           response, but is ignored by the core internally and doesn't
+                                                         affect the operation of the core. */
+        uint32_t curmod                  : 1;       /**< Current Mode of Operation (CurMod)
+                                                         Indicates the current mode of operation.
+                                                         * 1'b0: Device mode
+                                                         * 1'b1: Host mode */
+#else
+        uint32_t curmod                  : 1;
+        uint32_t modemis                 : 1;
+        uint32_t otgint                  : 1;
+        uint32_t sof                     : 1;
+        uint32_t rxflvl                  : 1;
+        uint32_t nptxfemp                : 1;
+        uint32_t ginnakeff               : 1;
+        uint32_t goutnakeff              : 1;
+        uint32_t ulpickint               : 1;
+        uint32_t i2cint                  : 1;
+        uint32_t erlysusp                : 1;
+        uint32_t usbsusp                 : 1;
+        uint32_t usbrst                  : 1;
+        uint32_t enumdone                : 1;
+        uint32_t isooutdrop              : 1;
+        uint32_t eopf                    : 1;
+        uint32_t reserved_16_16          : 1;
+        uint32_t epmis                   : 1;
+        uint32_t iepint                  : 1;
+        uint32_t oepint                  : 1;
+        uint32_t incompisoin             : 1;
+        uint32_t incomplp                : 1;
+        uint32_t fetsusp                 : 1;
+        uint32_t reserved_23_23          : 1;
+        uint32_t prtint                  : 1;
+        uint32_t hchint                  : 1;
+        uint32_t ptxfemp                 : 1;
+        uint32_t reserved_27_27          : 1;
+        uint32_t conidstschng            : 1;
+        uint32_t disconnint              : 1;
+        uint32_t sessreqint              : 1;
+        uint32_t wkupint                 : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_gintsts_s          cn30xx;
+    struct cvmx_usbcx_gintsts_s          cn31xx;
+    struct cvmx_usbcx_gintsts_s          cn50xx;
+    struct cvmx_usbcx_gintsts_s          cn52xx;
+    struct cvmx_usbcx_gintsts_s          cn52xxp1;
+    struct cvmx_usbcx_gintsts_s          cn56xx;
+    struct cvmx_usbcx_gintsts_s          cn56xxp1;
+} cvmx_usbcx_gintsts_t;
+
+
+/**
+ * cvmx_usbc#_gnptxfsiz
+ *
+ * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
+ * 
+ * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gnptxfsiz_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t nptxfdep                : 16;      /**< Non-Periodic TxFIFO Depth (NPTxFDep)
+                                                         This value is in terms of 32-bit words.
+                                                         Minimum value is 16
+                                                         Maximum value is 32768 */
+        uint32_t nptxfstaddr             : 16;      /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
+                                                         This field contains the memory start address for Non-Periodic
+                                                         Transmit FIFO RAM. */
+#else
+        uint32_t nptxfstaddr             : 16;
+        uint32_t nptxfdep                : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_gnptxfsiz_s        cn30xx;
+    struct cvmx_usbcx_gnptxfsiz_s        cn31xx;
+    struct cvmx_usbcx_gnptxfsiz_s        cn50xx;
+    struct cvmx_usbcx_gnptxfsiz_s        cn52xx;
+    struct cvmx_usbcx_gnptxfsiz_s        cn52xxp1;
+    struct cvmx_usbcx_gnptxfsiz_s        cn56xx;
+    struct cvmx_usbcx_gnptxfsiz_s        cn56xxp1;
+} cvmx_usbcx_gnptxfsiz_t;
+
+
+/**
+ * cvmx_usbc#_gnptxsts
+ *
+ * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
+ * 
+ * This read-only register contains the free space information for the Non-Periodic TxFIFO and
+ * the Non-Periodic Transmit Request Queue
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gnptxsts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_31_31          : 1;
+        uint32_t nptxqtop                : 7;       /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
+                                                         Entry in the Non-Periodic Tx Request Queue that is currently
+                                                         being processed by the MAC.
+                                                         * Bits [30:27]: Channel/endpoint number
+                                                         * Bits [26:25]:
+                                                           - 2'b00: IN/OUT token
+                                                           - 2'b01: Zero-length transmit packet (device IN/host OUT)
+                                                           - 2'b10: PING/CSPLIT token
+                                                           - 2'b11: Channel halt command
+                                                         * Bit [24]: Terminate (last entry for selected channel/endpoint) */
+        uint32_t nptxqspcavail           : 8;       /**< Non-Periodic Transmit Request Queue Space Available
+                                                         (NPTxQSpcAvail)
+                                                         Indicates the amount of free space available in the Non-
+                                                         Periodic Transmit Request Queue. This queue holds both IN
+                                                         and OUT requests in Host mode. Device mode has only IN
+                                                         requests.
+                                                         * 8'h0: Non-Periodic Transmit Request Queue is full
+                                                         * 8'h1: 1 location available
+                                                         * 8'h2: 2 locations available
+                                                         * n: n locations available (0..8)
+                                                         * Others: Reserved */
+        uint32_t nptxfspcavail           : 16;      /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
+                                                         Indicates the amount of free space available in the Non-
+                                                         Periodic TxFIFO.
+                                                         Values are in terms of 32-bit words.
+                                                         * 16'h0: Non-Periodic TxFIFO is full
+                                                         * 16'h1: 1 word available
+                                                         * 16'h2: 2 words available
+                                                         * 16'hn: n words available (where 0..32768)
+                                                         * 16'h8000: 32768 words available
+                                                         * Others: Reserved */
+#else
+        uint32_t nptxfspcavail           : 16;
+        uint32_t nptxqspcavail           : 8;
+        uint32_t nptxqtop                : 7;
+        uint32_t reserved_31_31          : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_gnptxsts_s         cn30xx;
+    struct cvmx_usbcx_gnptxsts_s         cn31xx;
+    struct cvmx_usbcx_gnptxsts_s         cn50xx;
+    struct cvmx_usbcx_gnptxsts_s         cn52xx;
+    struct cvmx_usbcx_gnptxsts_s         cn52xxp1;
+    struct cvmx_usbcx_gnptxsts_s         cn56xx;
+    struct cvmx_usbcx_gnptxsts_s         cn56xxp1;
+} cvmx_usbcx_gnptxsts_t;
+
+
+/**
+ * cvmx_usbc#_gotgctl
+ *
+ * OTG Control and Status Register (GOTGCTL)
+ * 
+ * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.:
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gotgctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t bsesvld                 : 1;       /**< B-Session Valid (BSesVld)
+                                                         Valid only when O2P USB core is configured as a USB device.
+                                                         Indicates the Device mode transceiver status.
+                                                         * 1'b0: B-session is not valid.
+                                                         * 1'b1: B-session is valid. */
+        uint32_t asesvld                 : 1;       /**< A-Session Valid (ASesVld)
+                                                         Valid only when O2P USB core is configured as a USB host.
+                                                         Indicates the Host mode transceiver status.
+                                                         * 1'b0: A-session is not valid
+                                                         * 1'b1: A-session is valid */
+        uint32_t dbnctime                : 1;       /**< Long/Short Debounce Time (DbncTime)
+                                                         In the present version of the core this bit will only read as '0'. */
+        uint32_t conidsts                : 1;       /**< Connector ID Status (ConIDSts)
+                                                         Indicates the connector ID status on a connect event.
+                                                         * 1'b0: The O2P USB core is in A-device mode
+                                                         * 1'b1: The O2P USB core is in B-device mode */
+        uint32_t reserved_12_15          : 4;
+        uint32_t devhnpen                : 1;       /**< Device HNP Enabled (DevHNPEn)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+        uint32_t hstsethnpen             : 1;       /**< Host Set HNP Enable (HstSetHNPEn)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+        uint32_t hnpreq                  : 1;       /**< HNP Request (HNPReq)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+        uint32_t hstnegscs               : 1;       /**< Host Negotiation Success (HstNegScs)
+                                                         Since O2P USB core is not HNP capable this bit is 0x0. */
+        uint32_t reserved_2_7            : 6;
+        uint32_t sesreq                  : 1;       /**< Session Request (SesReq)
+                                                         Since O2P USB core is not SRP capable this bit is 0x0. */
+        uint32_t sesreqscs               : 1;       /**< Session Request Success (SesReqScs)
+                                                         Since O2P USB core is not SRP capable this bit is 0x0. */
+#else
+        uint32_t sesreqscs               : 1;
+        uint32_t sesreq                  : 1;
+        uint32_t reserved_2_7            : 6;
+        uint32_t hstnegscs               : 1;
+        uint32_t hnpreq                  : 1;
+        uint32_t hstsethnpen             : 1;
+        uint32_t devhnpen                : 1;
+        uint32_t reserved_12_15          : 4;
+        uint32_t conidsts                : 1;
+        uint32_t dbnctime                : 1;
+        uint32_t asesvld                 : 1;
+        uint32_t bsesvld                 : 1;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_usbcx_gotgctl_s          cn30xx;
+    struct cvmx_usbcx_gotgctl_s          cn31xx;
+    struct cvmx_usbcx_gotgctl_s          cn50xx;
+    struct cvmx_usbcx_gotgctl_s          cn52xx;
+    struct cvmx_usbcx_gotgctl_s          cn52xxp1;
+    struct cvmx_usbcx_gotgctl_s          cn56xx;
+    struct cvmx_usbcx_gotgctl_s          cn56xxp1;
+} cvmx_usbcx_gotgctl_t;
+
+
+/**
+ * cvmx_usbc#_gotgint
+ *
+ * OTG Interrupt Register (GOTGINT)
+ * 
+ * The application reads this register whenever there is an OTG interrupt and clears the bits in this register
+ * to clear the OTG interrupt. It is shown in Interrupt .:
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gotgint_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_20_31          : 12;
+        uint32_t dbncedone               : 1;       /**< Debounce Done (DbnceDone)
+                                                         In the present version of the code this bit is tied to '0'. */
+        uint32_t adevtoutchg             : 1;       /**< A-Device Timeout Change (ADevTOUTChg)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+        uint32_t hstnegdet               : 1;       /**< Host Negotiation Detected (HstNegDet)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+        uint32_t reserved_10_16          : 7;
+        uint32_t hstnegsucstschng        : 1;       /**< Host Negotiation Success Status Change (HstNegSucStsChng)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+        uint32_t sesreqsucstschng        : 1;       /**< Session Request Success Status Change
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+        uint32_t reserved_3_7            : 5;
+        uint32_t sesenddet               : 1;       /**< Session End Detected (SesEndDet)
+                                                         Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
+        uint32_t reserved_0_1            : 2;
+#else
+        uint32_t reserved_0_1            : 2;
+        uint32_t sesenddet               : 1;
+        uint32_t reserved_3_7            : 5;
+        uint32_t sesreqsucstschng        : 1;
+        uint32_t hstnegsucstschng        : 1;
+        uint32_t reserved_10_16          : 7;
+        uint32_t hstnegdet               : 1;
+        uint32_t adevtoutchg             : 1;
+        uint32_t dbncedone               : 1;
+        uint32_t reserved_20_31          : 12;
+#endif
+    } s;
+    struct cvmx_usbcx_gotgint_s          cn30xx;
+    struct cvmx_usbcx_gotgint_s          cn31xx;
+    struct cvmx_usbcx_gotgint_s          cn50xx;
+    struct cvmx_usbcx_gotgint_s          cn52xx;
+    struct cvmx_usbcx_gotgint_s          cn52xxp1;
+    struct cvmx_usbcx_gotgint_s          cn56xx;
+    struct cvmx_usbcx_gotgint_s          cn56xxp1;
+} cvmx_usbcx_gotgint_t;
+
+
+/**
+ * cvmx_usbc#_grstctl
+ *
+ * Core Reset Register (GRSTCTL)
+ * 
+ * The application uses this register to reset various hardware features inside the core.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_grstctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ahbidle                 : 1;       /**< AHB Master Idle (AHBIdle)
+                                                         Indicates that the AHB Master State Machine is in the IDLE
+                                                         condition. */
+        uint32_t dmareq                  : 1;       /**< DMA Request Signal (DMAReq)
+                                                         Indicates that the DMA request is in progress. Used for debug. */
+        uint32_t reserved_11_29          : 19;
+        uint32_t txfnum                  : 5;       /**< TxFIFO Number (TxFNum)
+                                                         This is the FIFO number that must be flushed using the TxFIFO
+                                                         Flush bit. This field must not be changed until the core clears
+                                                         the TxFIFO Flush bit.
+                                                         * 5'h0: Non-Periodic TxFIFO flush
+                                                         * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
+                                                         TxFIFO flush in Host mode
+                                                         * 5'h2: Periodic TxFIFO 2 flush in Device mode
+                                                         - ...
+                                                         * 5'hF: Periodic TxFIFO 15 flush in Device mode
+                                                         * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
+                                                         core */
+        uint32_t txfflsh                 : 1;       /**< TxFIFO Flush (TxFFlsh)
+                                                         This bit selectively flushes a single or all transmit FIFOs, but
+                                                         cannot do so if the core is in the midst of a transaction.
+                                                         The application must only write this bit after checking that the
+                                                         core is neither writing to the TxFIFO nor reading from the
+                                                         TxFIFO.
+                                                         The application must wait until the core clears this bit before
+                                                         performing any operations. This bit takes 8 clocks (of phy_clk or
+                                                         hclk, whichever is slower) to clear. */
+        uint32_t rxfflsh                 : 1;       /**< RxFIFO Flush (RxFFlsh)
+                                                         The application can flush the entire RxFIFO using this bit, but
+                                                         must first ensure that the core is not in the middle of a
+                                                         transaction.
+                                                         The application must only write to this bit after checking that the
+                                                         core is neither reading from the RxFIFO nor writing to the
+                                                         RxFIFO.
+                                                         The application must wait until the bit is cleared before
+                                                         performing any other operations. This bit will take 8 clocks
+                                                         (slowest of PHY or AHB clock) to clear. */
+        uint32_t intknqflsh              : 1;       /**< IN Token Sequence Learning Queue Flush (INTknQFlsh)
+                                                         The application writes this bit to flush the IN Token Sequence
+                                                         Learning Queue. */
+        uint32_t frmcntrrst              : 1;       /**< Host Frame Counter Reset (FrmCntrRst)
+                                                         The application writes this bit to reset the (micro)frame number
+                                                         counter inside the core. When the (micro)frame counter is reset,
+                                                         the subsequent SOF sent out by the core will have a
+                                                         (micro)frame number of 0. */
+        uint32_t hsftrst                 : 1;       /**< HClk Soft Reset (HSftRst)
+                                                         The application uses this bit to flush the control logic in the AHB
+                                                         Clock domain. Only AHB Clock Domain pipelines are reset.
+                                                         * FIFOs are not flushed with this bit.
+                                                         * All state machines in the AHB clock domain are reset to the
+                                                           Idle state after terminating the transactions on the AHB,
+                                                           following the protocol.
+                                                         * CSR control bits used by the AHB clock domain state
+                                                           machines are cleared.
+                                                         * To clear this interrupt, status mask bits that control the
+                                                           interrupt status and are generated by the AHB clock domain
+                                                           state machine are cleared.
+                                                         * Because interrupt status bits are not cleared, the application
+                                                           can get the status of any core events that occurred after it set
+                                                           this bit.
+                                                           This is a self-clearing bit that the core clears after all necessary
+                                                           logic is reset in the core. This may take several clocks,
+                                                           depending on the core's current state. */
+        uint32_t csftrst                 : 1;       /**< Core Soft Reset (CSftRst)
+                                                         Resets the hclk and phy_clock domains as follows:
+                                                         * Clears the interrupts and all the CSR registers except the
+                                                           following register bits:
+                                                           - PCGCCTL.RstPdwnModule
+                                                           - PCGCCTL.GateHclk
+                                                           - PCGCCTL.PwrClmp
+                                                           - PCGCCTL.StopPPhyLPwrClkSelclk
+                                                           - GUSBCFG.PhyLPwrClkSel
+                                                           - GUSBCFG.DDRSel
+                                                           - GUSBCFG.PHYSel
+                                                           - GUSBCFG.FSIntf
+                                                           - GUSBCFG.ULPI_UTMI_Sel
+                                                           - GUSBCFG.PHYIf
+                                                           - HCFG.FSLSPclkSel
+                                                           - DCFG.DevSpd
+                                                         * All module state machines (except the AHB Slave Unit) are
+                                                           reset to the IDLE state, and all the transmit FIFOs and the
+                                                           receive FIFO are flushed.
+                                                         * Any transactions on the AHB Master are terminated as soon
+                                                           as possible, after gracefully completing the last data phase of
+                                                           an AHB transfer. Any transactions on the USB are terminated
+                                                           immediately.
+                                                           The application can write to this bit any time it wants to reset
+                                                           the core. This is a self-clearing bit and the core clears this bit
+                                                           after all the necessary logic is reset in the core, which may take
+                                                           several clocks, depending on the current state of the core.
+                                                           Once this bit is cleared software should wait at least 3 PHY
+                                                           clocks before doing any access to the PHY domain
+                                                           (synchronization delay). Software should also should check that
+                                                           bit 31 of this register is 1 (AHB Master is IDLE) before starting
+                                                           any operation.
+                                                           Typically software reset is used during software development
+                                                           and also when you dynamically change the PHY selection bits
+                                                           in the USB configuration registers listed above. When you
+                                                           change the PHY, the corresponding clock for the PHY is
+                                                           selected and used in the PHY domain. Once a new clock is
+                                                           selected, the PHY domain has to be reset for proper operation. */
+#else
+        uint32_t csftrst                 : 1;
+        uint32_t hsftrst                 : 1;
+        uint32_t frmcntrrst              : 1;
+        uint32_t intknqflsh              : 1;
+        uint32_t rxfflsh                 : 1;
+        uint32_t txfflsh                 : 1;
+        uint32_t txfnum                  : 5;
+        uint32_t reserved_11_29          : 19;
+        uint32_t dmareq                  : 1;
+        uint32_t ahbidle                 : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_grstctl_s          cn30xx;
+    struct cvmx_usbcx_grstctl_s          cn31xx;
+    struct cvmx_usbcx_grstctl_s          cn50xx;
+    struct cvmx_usbcx_grstctl_s          cn52xx;
+    struct cvmx_usbcx_grstctl_s          cn52xxp1;
+    struct cvmx_usbcx_grstctl_s          cn56xx;
+    struct cvmx_usbcx_grstctl_s          cn56xxp1;
+} cvmx_usbcx_grstctl_t;
+
+
+/**
+ * cvmx_usbc#_grxfsiz
+ *
+ * Receive FIFO Size Register (GRXFSIZ)
+ * 
+ * The application can program the RAM size that must be allocated to the RxFIFO.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_grxfsiz_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t rxfdep                  : 16;      /**< RxFIFO Depth (RxFDep)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 16
+                                                         * Maximum value is 32768 */
+#else
+        uint32_t rxfdep                  : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_grxfsiz_s          cn30xx;
+    struct cvmx_usbcx_grxfsiz_s          cn31xx;
+    struct cvmx_usbcx_grxfsiz_s          cn50xx;
+    struct cvmx_usbcx_grxfsiz_s          cn52xx;
+    struct cvmx_usbcx_grxfsiz_s          cn52xxp1;
+    struct cvmx_usbcx_grxfsiz_s          cn56xx;
+    struct cvmx_usbcx_grxfsiz_s          cn56xxp1;
+} cvmx_usbcx_grxfsiz_t;
+
+
+/**
+ * cvmx_usbc#_grxstspd
+ *
+ * Receive Status Debug Read Register, Device Mode (GRXSTSPD)
+ * 
+ * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
+ * This Description is only valid when the core is in Device Mode.  For Host Mode use USBC_GRXSTSPH instead.
+ * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_grxstspd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_25_31          : 7;
+        uint32_t fn                      : 4;       /**< Frame Number (FN)
+                                                         This is the least significant 4 bits of the (micro)frame number in
+                                                         which the packet is received on the USB.  This field is supported
+                                                         only when the isochronous OUT endpoints are supported. */
+        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0001: Glogal OUT NAK (triggers an interrupt)
+                                                         * 4'b0010: OUT data packet received
+                                                         * 4'b0100: SETUP transaction completed (triggers an interrupt)
+                                                         * 4'b0110: SETUP data packet received
+                                                         * Others: Reserved */
+        uint32_t dpid                    : 2;       /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received data packet */
+        uint32_t epnum                   : 4;       /**< Endpoint Number (EPNum)
+                                                         Indicates the endpoint number to which the current received
+                                                         packet belongs. */
+#else
+        uint32_t epnum                   : 4;
+        uint32_t bcnt                    : 11;
+        uint32_t dpid                    : 2;
+        uint32_t pktsts                  : 4;
+        uint32_t fn                      : 4;
+        uint32_t reserved_25_31          : 7;
+#endif
+    } s;
+    struct cvmx_usbcx_grxstspd_s         cn30xx;
+    struct cvmx_usbcx_grxstspd_s         cn31xx;
+    struct cvmx_usbcx_grxstspd_s         cn50xx;
+    struct cvmx_usbcx_grxstspd_s         cn52xx;
+    struct cvmx_usbcx_grxstspd_s         cn52xxp1;
+    struct cvmx_usbcx_grxstspd_s         cn56xx;
+    struct cvmx_usbcx_grxstspd_s         cn56xxp1;
+} cvmx_usbcx_grxstspd_t;
+
+
+/**
+ * cvmx_usbc#_grxstsph
+ *
+ * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
+ * 
+ * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
+ * This Description is only valid when the core is in Host Mode.  For Device Mode use USBC_GRXSTSPD instead.
+ * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_grxstsph_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0010: IN data packet received
+                                                         * 4'b0011: IN transfer completed (triggers an interrupt)
+                                                         * 4'b0101: Data toggle error (triggers an interrupt)
+                                                         * 4'b0111: Channel halted (triggers an interrupt)
+                                                         * Others: Reserved */
+        uint32_t dpid                    : 2;       /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received IN data packet */
+        uint32_t chnum                   : 4;       /**< Channel Number (ChNum)
+                                                         Indicates the channel number to which the current received
+                                                         packet belongs. */
+#else
+        uint32_t chnum                   : 4;
+        uint32_t bcnt                    : 11;
+        uint32_t dpid                    : 2;
+        uint32_t pktsts                  : 4;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_usbcx_grxstsph_s         cn30xx;
+    struct cvmx_usbcx_grxstsph_s         cn31xx;
+    struct cvmx_usbcx_grxstsph_s         cn50xx;
+    struct cvmx_usbcx_grxstsph_s         cn52xx;
+    struct cvmx_usbcx_grxstsph_s         cn52xxp1;
+    struct cvmx_usbcx_grxstsph_s         cn56xx;
+    struct cvmx_usbcx_grxstsph_s         cn56xxp1;
+} cvmx_usbcx_grxstsph_t;
+
+
+/**
+ * cvmx_usbc#_grxstsrd
+ *
+ * Receive Status Debug Read Register, Device Mode (GRXSTSRD)
+ * 
+ * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
+ * This Description is only valid when the core is in Device Mode.  For Host Mode use USBC_GRXSTSRH instead.
+ * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_grxstsrd_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_25_31          : 7;
+        uint32_t fn                      : 4;       /**< Frame Number (FN)
+                                                         This is the least significant 4 bits of the (micro)frame number in
+                                                         which the packet is received on the USB.  This field is supported
+                                                         only when the isochronous OUT endpoints are supported. */
+        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0001: Glogal OUT NAK (triggers an interrupt)
+                                                         * 4'b0010: OUT data packet received
+                                                         * 4'b0100: SETUP transaction completed (triggers an interrupt)
+                                                         * 4'b0110: SETUP data packet received
+                                                         * Others: Reserved */
+        uint32_t dpid                    : 2;       /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received data packet */
+        uint32_t epnum                   : 4;       /**< Endpoint Number (EPNum)
+                                                         Indicates the endpoint number to which the current received
+                                                         packet belongs. */
+#else
+        uint32_t epnum                   : 4;
+        uint32_t bcnt                    : 11;
+        uint32_t dpid                    : 2;
+        uint32_t pktsts                  : 4;
+        uint32_t fn                      : 4;
+        uint32_t reserved_25_31          : 7;
+#endif
+    } s;
+    struct cvmx_usbcx_grxstsrd_s         cn30xx;
+    struct cvmx_usbcx_grxstsrd_s         cn31xx;
+    struct cvmx_usbcx_grxstsrd_s         cn50xx;
+    struct cvmx_usbcx_grxstsrd_s         cn52xx;
+    struct cvmx_usbcx_grxstsrd_s         cn52xxp1;
+    struct cvmx_usbcx_grxstsrd_s         cn56xx;
+    struct cvmx_usbcx_grxstsrd_s         cn56xxp1;
+} cvmx_usbcx_grxstsrd_t;
+
+
+/**
+ * cvmx_usbc#_grxstsrh
+ *
+ * Receive Status Debug Read Register, Host Mode (GRXSTSRH)
+ * 
+ * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
+ * This Description is only valid when the core is in Host Mode.  For Device Mode use USBC_GRXSTSRD instead.
+ * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
+ *       The offset difference shown in this document is for software clarity and is actually ignored by the
+ *       hardware.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_grxstsrh_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_21_31          : 11;
+        uint32_t pktsts                  : 4;       /**< Packet Status (PktSts)
+                                                         Indicates the status of the received packet
+                                                         * 4'b0010: IN data packet received
+                                                         * 4'b0011: IN transfer completed (triggers an interrupt)
+                                                         * 4'b0101: Data toggle error (triggers an interrupt)
+                                                         * 4'b0111: Channel halted (triggers an interrupt)
+                                                         * Others: Reserved */
+        uint32_t dpid                    : 2;       /**< Data PID (DPID)
+                                                         * 2'b00: DATA0
+                                                         * 2'b10: DATA1
+                                                         * 2'b01: DATA2
+                                                         * 2'b11: MDATA */
+        uint32_t bcnt                    : 11;      /**< Byte Count (BCnt)
+                                                         Indicates the byte count of the received IN data packet */
+        uint32_t chnum                   : 4;       /**< Channel Number (ChNum)
+                                                         Indicates the channel number to which the current received
+                                                         packet belongs. */
+#else
+        uint32_t chnum                   : 4;
+        uint32_t bcnt                    : 11;
+        uint32_t dpid                    : 2;
+        uint32_t pktsts                  : 4;
+        uint32_t reserved_21_31          : 11;
+#endif
+    } s;
+    struct cvmx_usbcx_grxstsrh_s         cn30xx;
+    struct cvmx_usbcx_grxstsrh_s         cn31xx;
+    struct cvmx_usbcx_grxstsrh_s         cn50xx;
+    struct cvmx_usbcx_grxstsrh_s         cn52xx;
+    struct cvmx_usbcx_grxstsrh_s         cn52xxp1;
+    struct cvmx_usbcx_grxstsrh_s         cn56xx;
+    struct cvmx_usbcx_grxstsrh_s         cn56xxp1;
+} cvmx_usbcx_grxstsrh_t;
+
+
+/**
+ * cvmx_usbc#_gsnpsid
+ *
+ * Synopsys ID Register (GSNPSID)
+ * 
+ * This is a read-only register that contains the release number of the core being used.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gsnpsid_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t synopsysid              : 32;      /**< 0x4F54\<version\>A, release number of the core being used.
+                                                         0x4F54220A => pass1.x,  0x4F54240A => pass2.x */
+#else
+        uint32_t synopsysid              : 32;
+#endif
+    } s;
+    struct cvmx_usbcx_gsnpsid_s          cn30xx;
+    struct cvmx_usbcx_gsnpsid_s          cn31xx;
+    struct cvmx_usbcx_gsnpsid_s          cn50xx;
+    struct cvmx_usbcx_gsnpsid_s          cn52xx;
+    struct cvmx_usbcx_gsnpsid_s          cn52xxp1;
+    struct cvmx_usbcx_gsnpsid_s          cn56xx;
+    struct cvmx_usbcx_gsnpsid_s          cn56xxp1;
+} cvmx_usbcx_gsnpsid_t;
+
+
+/**
+ * cvmx_usbc#_gusbcfg
+ *
+ * Core USB Configuration Register (GUSBCFG)
+ * 
+ * This register can be used to configure the core after power-on or a changing to Host mode or Device mode.
+ * It contains USB and USB-PHY related configuration parameters. The application must program this register
+ * before starting any transactions on either the AHB or the USB.
+ * Do not make changes to this register after the initial programming.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_gusbcfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_17_31          : 15;
+        uint32_t otgi2csel               : 1;       /**< UTMIFS or I2C Interface Select (OtgI2CSel)
+                                                         This bit is always 0x0. */
+        uint32_t phylpwrclksel           : 1;       /**< PHY Low-Power Clock Select (PhyLPwrClkSel)
+                                                         Software should set this bit to 0x0.
+                                                         Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
+                                                         FS and LS modes, the PHY can usually operate on a 48-MHz
+                                                         clock to save power.
+                                                         * 1'b0: 480-MHz Internal PLL clock
+                                                         * 1'b1: 48-MHz External Clock
+                                                         In 480 MHz mode, the UTMI interface operates at either 60 or
+                                                         30-MHz, depending upon whether 8- or 16-bit data width is
+                                                         selected. In 48-MHz mode, the UTMI interface operates at 48
+                                                         MHz in FS mode and at either 48 or 6 MHz in LS mode
+                                                         (depending on the PHY vendor).
+                                                         This bit drives the utmi_fsls_low_power core output signal, and
+                                                         is valid only for UTMI+ PHYs. */
+        uint32_t reserved_14_14          : 1;
+        uint32_t usbtrdtim               : 4;       /**< USB Turnaround Time (USBTrdTim)
+                                                         Sets the turnaround time in PHY clocks.
+                                                         Specifies the response time for a MAC request to the Packet
+                                                         FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
+                                                         This must be programmed to 0x5. */
+        uint32_t hnpcap                  : 1;       /**< HNP-Capable (HNPCap)
+                                                         This bit is always 0x0. */
+        uint32_t srpcap                  : 1;       /**< SRP-Capable (SRPCap)
+                                                         This bit is always 0x0. */
+        uint32_t ddrsel                  : 1;       /**< ULPI DDR Select (DDRSel)
+                                                         Software should set this bit to 0x0. */
+        uint32_t physel                  : 1;       /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
+                                                         Software should set this bit to 0x0. */
+        uint32_t fsintf                  : 1;       /**< Full-Speed Serial Interface Select (FSIntf)
+                                                         Software should set this bit to 0x0. */
+        uint32_t ulpi_utmi_sel           : 1;       /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel)
+                                                         This bit is always 0x0. */
+        uint32_t phyif                   : 1;       /**< PHY Interface (PHYIf)
+                                                         This bit is always 0x1. */
+        uint32_t toutcal                 : 3;       /**< HS/FS Timeout Calibration (TOutCal)
+                                                         The number of PHY clocks that the application programs in this
+                                                         field is added to the high-speed/full-speed interpacket timeout
+                                                         duration in the core to account for any additional delays
+                                                         introduced by the PHY. This may be required, since the delay
+                                                         introduced by the PHY in generating the linestate condition may
+                                                         vary from one PHY to another.
+                                                         The USB standard timeout value for high-speed operation is
+                                                         736 to 816 (inclusive) bit times. The USB standard timeout
+                                                         value for full-speed operation is 16 to 18 (inclusive) bit times.
+                                                         The application must program this field based on the speed of
+                                                         enumeration. The number of bit times added per PHY clock are:
+                                                         High-speed operation:
+                                                         * One 30-MHz PHY clock = 16 bit times
+                                                         * One 60-MHz PHY clock = 8 bit times
+                                                         Full-speed operation:
+                                                         * One 30-MHz PHY clock = 0.4 bit times
+                                                         * One 60-MHz PHY clock = 0.2 bit times
+                                                         * One 48-MHz PHY clock = 0.25 bit times */
+#else
+        uint32_t toutcal                 : 3;
+        uint32_t phyif                   : 1;
+        uint32_t ulpi_utmi_sel           : 1;
+        uint32_t fsintf                  : 1;
+        uint32_t physel                  : 1;
+        uint32_t ddrsel                  : 1;
+        uint32_t srpcap                  : 1;
+        uint32_t hnpcap                  : 1;
+        uint32_t usbtrdtim               : 4;
+        uint32_t reserved_14_14          : 1;
+        uint32_t phylpwrclksel           : 1;
+        uint32_t otgi2csel               : 1;
+        uint32_t reserved_17_31          : 15;
+#endif
+    } s;
+    struct cvmx_usbcx_gusbcfg_s          cn30xx;
+    struct cvmx_usbcx_gusbcfg_s          cn31xx;
+    struct cvmx_usbcx_gusbcfg_s          cn50xx;
+    struct cvmx_usbcx_gusbcfg_s          cn52xx;
+    struct cvmx_usbcx_gusbcfg_s          cn52xxp1;
+    struct cvmx_usbcx_gusbcfg_s          cn56xx;
+    struct cvmx_usbcx_gusbcfg_s          cn56xxp1;
+} cvmx_usbcx_gusbcfg_t;
+
+
+/**
+ * cvmx_usbc#_haint
+ *
+ * Host All Channels Interrupt Register (HAINT)
+ * 
+ * When a significant event occurs on a channel, the Host All Channels Interrupt register
+ * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt
+ * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per
+ * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
+ * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_haint_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t haint                   : 16;      /**< Channel Interrupts (HAINT)
+                                                         One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */
+#else
+        uint32_t haint                   : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_haint_s            cn30xx;
+    struct cvmx_usbcx_haint_s            cn31xx;
+    struct cvmx_usbcx_haint_s            cn50xx;
+    struct cvmx_usbcx_haint_s            cn52xx;
+    struct cvmx_usbcx_haint_s            cn52xxp1;
+    struct cvmx_usbcx_haint_s            cn56xx;
+    struct cvmx_usbcx_haint_s            cn56xxp1;
+} cvmx_usbcx_haint_t;
+
+
+/**
+ * cvmx_usbc#_haintmsk
+ *
+ * Host All Channels Interrupt Mask Register (HAINTMSK)
+ * 
+ * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt
+ * register to interrupt the application when an event occurs on a channel. There is one
+ * interrupt mask bit per channel, up to a maximum of 16 bits.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_haintmsk_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t haintmsk                : 16;      /**< Channel Interrupt Mask (HAINTMsk)
+                                                         One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */
+#else
+        uint32_t haintmsk                : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_haintmsk_s         cn30xx;
+    struct cvmx_usbcx_haintmsk_s         cn31xx;
+    struct cvmx_usbcx_haintmsk_s         cn50xx;
+    struct cvmx_usbcx_haintmsk_s         cn52xx;
+    struct cvmx_usbcx_haintmsk_s         cn52xxp1;
+    struct cvmx_usbcx_haintmsk_s         cn56xx;
+    struct cvmx_usbcx_haintmsk_s         cn56xxp1;
+} cvmx_usbcx_haintmsk_t;
+
+
+/**
+ * cvmx_usbc#_hcchar#
+ *
+ * Host Channel-n Characteristics Register (HCCHAR)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hccharx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t chena                   : 1;       /**< Channel Enable (ChEna)
+                                                         This field is set by the application and cleared by the OTG host.
+                                                         * 1'b0: Channel disabled
+                                                         * 1'b1: Channel enabled */
+        uint32_t chdis                   : 1;       /**< Channel Disable (ChDis)
+                                                         The application sets this bit to stop transmitting/receiving data
+                                                         on a channel, even before the transfer for that channel is
+                                                         complete. The application must wait for the Channel Disabled
+                                                         interrupt before treating the channel as disabled. */
+        uint32_t oddfrm                  : 1;       /**< Odd Frame (OddFrm)
+                                                         This field is set (reset) by the application to indicate that the
+                                                         OTG host must perform a transfer in an odd (micro)frame. This
+                                                         field is applicable for only periodic (isochronous and interrupt)
+                                                         transactions.
+                                                         * 1'b0: Even (micro)frame
+                                                         * 1'b1: Odd (micro)frame */
+        uint32_t devaddr                 : 7;       /**< Device Address (DevAddr)
+                                                         This field selects the specific device serving as the data source
+                                                         or sink. */
+        uint32_t ec                      : 2;       /**< Multi Count (MC) / Error Count (EC)
+                                                         When the Split Enable bit of the Host Channel-n Split Control
+                                                         register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
+                                                         to the host the number of transactions that should be executed
+                                                         per microframe for this endpoint.
+                                                         * 2'b00: Reserved. This field yields undefined results.
+                                                         * 2'b01: 1 transaction
+                                                         * 2'b10: 2 transactions to be issued for this endpoint per
+                                                                  microframe
+                                                         * 2'b11: 3 transactions to be issued for this endpoint per
+                                                                  microframe
+                                                         When HCSPLTn.SpltEna is set (1'b1), this field indicates the
+                                                         number of immediate retries to be performed for a periodic split
+                                                         transactions on transaction errors. This field must be set to at
+                                                         least 2'b01. */
+        uint32_t eptype                  : 2;       /**< Endpoint Type (EPType)
+                                                         Indicates the transfer type selected.
+                                                         * 2'b00: Control
+                                                         * 2'b01: Isochronous
+                                                         * 2'b10: Bulk
+                                                         * 2'b11: Interrupt */
+        uint32_t lspddev                 : 1;       /**< Low-Speed Device (LSpdDev)
+                                                         This field is set by the application to indicate that this channel is
+                                                         communicating to a low-speed device. */
+        uint32_t reserved_16_16          : 1;
+        uint32_t epdir                   : 1;       /**< Endpoint Direction (EPDir)
+                                                         Indicates whether the transaction is IN or OUT.
+                                                         * 1'b0: OUT
+                                                         * 1'b1: IN */
+        uint32_t epnum                   : 4;       /**< Endpoint Number (EPNum)
+                                                         Indicates the endpoint number on the device serving as the
+                                                         data source or sink. */
+        uint32_t mps                     : 11;      /**< Maximum Packet Size (MPS)
+                                                         Indicates the maximum packet size of the associated endpoint. */
+#else
+        uint32_t mps                     : 11;
+        uint32_t epnum                   : 4;
+        uint32_t epdir                   : 1;
+        uint32_t reserved_16_16          : 1;
+        uint32_t lspddev                 : 1;
+        uint32_t eptype                  : 2;
+        uint32_t ec                      : 2;
+        uint32_t devaddr                 : 7;
+        uint32_t oddfrm                  : 1;
+        uint32_t chdis                   : 1;
+        uint32_t chena                   : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_hccharx_s          cn30xx;
+    struct cvmx_usbcx_hccharx_s          cn31xx;
+    struct cvmx_usbcx_hccharx_s          cn50xx;
+    struct cvmx_usbcx_hccharx_s          cn52xx;
+    struct cvmx_usbcx_hccharx_s          cn52xxp1;
+    struct cvmx_usbcx_hccharx_s          cn56xx;
+    struct cvmx_usbcx_hccharx_s          cn56xxp1;
+} cvmx_usbcx_hccharx_t;
+
+
+/**
+ * cvmx_usbc#_hcfg
+ *
+ * Host Configuration Register (HCFG)
+ * 
+ * This register configures the core after power-on. Do not make changes to this register after initializing the host.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hcfg_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_3_31           : 29;
+        uint32_t fslssupp                : 1;       /**< FS- and LS-Only Support (FSLSSupp)
+                                                         The application uses this bit to control the core's enumeration
+                                                         speed. Using this bit, the application can make the core
+                                                         enumerate as a FS host, even if the connected device supports
+                                                         HS traffic. Do not make changes to this field after initial
+                                                         programming.
+                                                         * 1'b0: HS/FS/LS, based on the maximum speed supported by
+                                                           the connected device
+                                                         * 1'b1: FS/LS-only, even if the connected device can support HS */
+        uint32_t fslspclksel             : 2;       /**< FS/LS PHY Clock Select (FSLSPclkSel)
+                                                         When the core is in FS Host mode
+                                                         * 2'b00: PHY clock is running at 30/60 MHz
+                                                         * 2'b01: PHY clock is running at 48 MHz
+                                                         * Others: Reserved
+                                                         When the core is in LS Host mode
+                                                         * 2'b00: PHY clock is running at 30/60 MHz. When the
+                                                                  UTMI+/ULPI PHY Low Power mode is not selected, use
+                                                                  30/60 MHz.
+                                                         * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
+                                                                  PHY Low Power mode is selected, use 48MHz if the PHY
+                                                                  supplies a 48 MHz clock during LS mode.
+                                                         * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
+                                                                  use 6 MHz when the UTMI+ PHY Low Power mode is
+                                                                  selected and the PHY supplies a 6 MHz clock during LS
+                                                                  mode. If you select a 6 MHz clock during LS mode, you must
+                                                                  do a soft reset.
+                                                         * 2'b11: Reserved */
+#else
+        uint32_t fslspclksel             : 2;
+        uint32_t fslssupp                : 1;
+        uint32_t reserved_3_31           : 29;
+#endif
+    } s;
+    struct cvmx_usbcx_hcfg_s             cn30xx;
+    struct cvmx_usbcx_hcfg_s             cn31xx;
+    struct cvmx_usbcx_hcfg_s             cn50xx;
+    struct cvmx_usbcx_hcfg_s             cn52xx;
+    struct cvmx_usbcx_hcfg_s             cn52xxp1;
+    struct cvmx_usbcx_hcfg_s             cn56xx;
+    struct cvmx_usbcx_hcfg_s             cn56xxp1;
+} cvmx_usbcx_hcfg_t;
+
+
+/**
+ * cvmx_usbc#_hcint#
+ *
+ * Host Channel-n Interrupt Register (HCINT)
+ * 
+ * This register indicates the status of a channel with respect to USB- and AHB-related events.
+ * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt
+ * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read
+ * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n
+ * Interrupt register. The application must clear the appropriate bit in this register to clear the
+ * corresponding bits in the HAINT and GINTSTS registers.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hcintx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_11_31          : 21;
+        uint32_t datatglerr              : 1;       /**< Data Toggle Error (DataTglErr) */
+        uint32_t frmovrun                : 1;       /**< Frame Overrun (FrmOvrun) */
+        uint32_t bblerr                  : 1;       /**< Babble Error (BblErr) */
+        uint32_t xacterr                 : 1;       /**< Transaction Error (XactErr) */
+        uint32_t nyet                    : 1;       /**< NYET Response Received Interrupt (NYET) */
+        uint32_t ack                     : 1;       /**< ACK Response Received Interrupt (ACK) */
+        uint32_t nak                     : 1;       /**< NAK Response Received Interrupt (NAK) */
+        uint32_t stall                   : 1;       /**< STALL Response Received Interrupt (STALL) */
+        uint32_t ahberr                  : 1;       /**< This bit is always 0x0. */
+        uint32_t chhltd                  : 1;       /**< Channel Halted (ChHltd)
+                                                         Indicates the transfer completed abnormally either because of
+                                                         any USB transaction error or in response to disable request by
+                                                         the application. */
+        uint32_t xfercompl               : 1;       /**< Transfer Completed (XferCompl)
+                                                         Transfer completed normally without any errors. */
+#else
+        uint32_t xfercompl               : 1;
+        uint32_t chhltd                  : 1;
+        uint32_t ahberr                  : 1;
+        uint32_t stall                   : 1;
+        uint32_t nak                     : 1;
+        uint32_t ack                     : 1;
+        uint32_t nyet                    : 1;
+        uint32_t xacterr                 : 1;
+        uint32_t bblerr                  : 1;
+        uint32_t frmovrun                : 1;
+        uint32_t datatglerr              : 1;
+        uint32_t reserved_11_31          : 21;
+#endif
+    } s;
+    struct cvmx_usbcx_hcintx_s           cn30xx;
+    struct cvmx_usbcx_hcintx_s           cn31xx;
+    struct cvmx_usbcx_hcintx_s           cn50xx;
+    struct cvmx_usbcx_hcintx_s           cn52xx;
+    struct cvmx_usbcx_hcintx_s           cn52xxp1;
+    struct cvmx_usbcx_hcintx_s           cn56xx;
+    struct cvmx_usbcx_hcintx_s           cn56xxp1;
+} cvmx_usbcx_hcintx_t;
+
+
+/**
+ * cvmx_usbc#_hcintmsk#
+ *
+ * Host Channel-n Interrupt Mask Register (HCINTMSKn)
+ * 
+ * This register reflects the mask for each channel status described in the previous section.
+ * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hcintmskx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_11_31          : 21;
+        uint32_t datatglerrmsk           : 1;       /**< Data Toggle Error Mask (DataTglErrMsk) */
+        uint32_t frmovrunmsk             : 1;       /**< Frame Overrun Mask (FrmOvrunMsk) */
+        uint32_t bblerrmsk               : 1;       /**< Babble Error Mask (BblErrMsk) */
+        uint32_t xacterrmsk              : 1;       /**< Transaction Error Mask (XactErrMsk) */
+        uint32_t nyetmsk                 : 1;       /**< NYET Response Received Interrupt Mask (NyetMsk) */
+        uint32_t ackmsk                  : 1;       /**< ACK Response Received Interrupt Mask (AckMsk) */
+        uint32_t nakmsk                  : 1;       /**< NAK Response Received Interrupt Mask (NakMsk) */
+        uint32_t stallmsk                : 1;       /**< STALL Response Received Interrupt Mask (StallMsk) */
+        uint32_t ahberrmsk               : 1;       /**< AHB Error Mask (AHBErrMsk) */
+        uint32_t chhltdmsk               : 1;       /**< Channel Halted Mask (ChHltdMsk) */
+        uint32_t xfercomplmsk            : 1;       /**< Transfer Completed Mask (XferComplMsk) */
+#else
+        uint32_t xfercomplmsk            : 1;
+        uint32_t chhltdmsk               : 1;
+        uint32_t ahberrmsk               : 1;
+        uint32_t stallmsk                : 1;
+        uint32_t nakmsk                  : 1;
+        uint32_t ackmsk                  : 1;
+        uint32_t nyetmsk                 : 1;
+        uint32_t xacterrmsk              : 1;
+        uint32_t bblerrmsk               : 1;
+        uint32_t frmovrunmsk             : 1;
+        uint32_t datatglerrmsk           : 1;
+        uint32_t reserved_11_31          : 21;
+#endif
+    } s;
+    struct cvmx_usbcx_hcintmskx_s        cn30xx;
+    struct cvmx_usbcx_hcintmskx_s        cn31xx;
+    struct cvmx_usbcx_hcintmskx_s        cn50xx;
+    struct cvmx_usbcx_hcintmskx_s        cn52xx;
+    struct cvmx_usbcx_hcintmskx_s        cn52xxp1;
+    struct cvmx_usbcx_hcintmskx_s        cn56xx;
+    struct cvmx_usbcx_hcintmskx_s        cn56xxp1;
+} cvmx_usbcx_hcintmskx_t;
+
+
+/**
+ * cvmx_usbc#_hcsplt#
+ *
+ * Host Channel-n Split Control Register (HCSPLT)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hcspltx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t spltena                 : 1;       /**< Split Enable (SpltEna)
+                                                         The application sets this field to indicate that this channel is
+                                                         enabled to perform split transactions. */
+        uint32_t reserved_17_30          : 14;
+        uint32_t compsplt                : 1;       /**< Do Complete Split (CompSplt)
+                                                         The application sets this field to request the OTG host to
+                                                         perform a complete split transaction. */
+        uint32_t xactpos                 : 2;       /**< Transaction Position (XactPos)
+                                                         This field is used to determine whether to send all, first, middle,
+                                                         or last payloads with each OUT transaction.
+                                                         * 2'b11: All. This is the entire data payload is of this transaction
+                                                                  (which is less than or equal to 188 bytes).
+                                                         * 2'b10: Begin. This is the first data payload of this transaction
+                                                                  (which is larger than 188 bytes).
+                                                         * 2'b00: Mid. This is the middle payload of this transaction
+                                                                  (which is larger than 188 bytes).
+                                                         * 2'b01: End. This is the last payload of this transaction (which
+                                                                  is larger than 188 bytes). */
+        uint32_t hubaddr                 : 7;       /**< Hub Address (HubAddr)
+                                                         This field holds the device address of the transaction
+                                                         translator's hub. */
+        uint32_t prtaddr                 : 7;       /**< Port Address (PrtAddr)
+                                                         This field is the port number of the recipient transaction
+                                                         translator. */
+#else
+        uint32_t prtaddr                 : 7;
+        uint32_t hubaddr                 : 7;
+        uint32_t xactpos                 : 2;
+        uint32_t compsplt                : 1;
+        uint32_t reserved_17_30          : 14;
+        uint32_t spltena                 : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_hcspltx_s          cn30xx;
+    struct cvmx_usbcx_hcspltx_s          cn31xx;
+    struct cvmx_usbcx_hcspltx_s          cn50xx;
+    struct cvmx_usbcx_hcspltx_s          cn52xx;
+    struct cvmx_usbcx_hcspltx_s          cn52xxp1;
+    struct cvmx_usbcx_hcspltx_s          cn56xx;
+    struct cvmx_usbcx_hcspltx_s          cn56xxp1;
+} cvmx_usbcx_hcspltx_t;
+
+
+/**
+ * cvmx_usbc#_hctsiz#
+ *
+ * Host Channel-n Transfer Size Register (HCTSIZ)
+ *
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hctsizx_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t dopng                   : 1;       /**< Do Ping (DoPng)
+                                                         Setting this field to 1 directs the host to do PING protocol. */
+        uint32_t pid                     : 2;       /**< PID (Pid)
+                                                         The application programs this field with the type of PID to use
+                                                         for the initial transaction. The host will maintain this field for the
+                                                         rest of the transfer.
+                                                         * 2'b00: DATA0
+                                                         * 2'b01: DATA2
+                                                         * 2'b10: DATA1
+                                                         * 2'b11: MDATA (non-control)/SETUP (control) */
+        uint32_t pktcnt                  : 10;      /**< Packet Count (PktCnt)
+                                                         This field is programmed by the application with the expected
+                                                         number of packets to be transmitted (OUT) or received (IN).
+                                                         The host decrements this count on every successful
+                                                         transmission or reception of an OUT/IN packet. Once this count
+                                                         reaches zero, the application is interrupted to indicate normal
+                                                         completion. */
+        uint32_t xfersize                : 19;      /**< Transfer Size (XferSize)
+                                                         For an OUT, this field is the number of data bytes the host will
+                                                         send during the transfer.
+                                                         For an IN, this field is the buffer size that the application has
+                                                         reserved for the transfer. The application is expected to
+                                                         program this field as an integer multiple of the maximum packet
+                                                         size for IN transactions (periodic and non-periodic). */
+#else
+        uint32_t xfersize                : 19;
+        uint32_t pktcnt                  : 10;
+        uint32_t pid                     : 2;
+        uint32_t dopng                   : 1;
+#endif
+    } s;
+    struct cvmx_usbcx_hctsizx_s          cn30xx;
+    struct cvmx_usbcx_hctsizx_s          cn31xx;
+    struct cvmx_usbcx_hctsizx_s          cn50xx;
+    struct cvmx_usbcx_hctsizx_s          cn52xx;
+    struct cvmx_usbcx_hctsizx_s          cn52xxp1;
+    struct cvmx_usbcx_hctsizx_s          cn56xx;
+    struct cvmx_usbcx_hctsizx_s          cn56xxp1;
+} cvmx_usbcx_hctsizx_t;
+
+
+/**
+ * cvmx_usbc#_hfir
+ *
+ * Host Frame Interval Register (HFIR)
+ * 
+ * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hfir_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_16_31          : 16;
+        uint32_t frint                   : 16;      /**< Frame Interval (FrInt)
+                                                         The value that the application programs to this field specifies
+                                                         the interval between two consecutive SOFs (FS) or micro-
+                                                         SOFs (HS) or Keep-Alive tokens (HS). This field contains the
+                                                         number of PHY clocks that constitute the required frame
+                                                         interval. The default value set in this field for a FS operation
+                                                         when the PHY clock frequency is 60 MHz. The application can
+                                                         write a value to this register only after the Port Enable bit of
+                                                         the Host Port Control and Status register (HPRT.PrtEnaPort)
+                                                         has been set. If no value is programmed, the core calculates
+                                                         the value based on the PHY clock specified in the FS/LS PHY
+                                                         Clock Select field of the Host Configuration register
+                                                         (HCFG.FSLSPclkSel). Do not change the value of this field
+                                                         after the initial configuration.
+                                                         * 125 us (PHY clock frequency for HS)
+                                                         * 1 ms (PHY clock frequency for FS/LS) */
+#else
+        uint32_t frint                   : 16;
+        uint32_t reserved_16_31          : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_hfir_s             cn30xx;
+    struct cvmx_usbcx_hfir_s             cn31xx;
+    struct cvmx_usbcx_hfir_s             cn50xx;
+    struct cvmx_usbcx_hfir_s             cn52xx;
+    struct cvmx_usbcx_hfir_s             cn52xxp1;
+    struct cvmx_usbcx_hfir_s             cn56xx;
+    struct cvmx_usbcx_hfir_s             cn56xxp1;
+} cvmx_usbcx_hfir_t;
+
+
+/**
+ * cvmx_usbc#_hfnum
+ *
+ * Host Frame Number/Frame Time Remaining Register (HFNUM)
+ * 
+ * This register indicates the current frame number.
+ * It also indicates the time remaining (in terms of the number of PHY clocks)
+ * in the current (micro)frame.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hfnum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t frrem                   : 16;      /**< Frame Time Remaining (FrRem)
+                                                         Indicates the amount of time remaining in the current
+                                                         microframe (HS) or frame (FS/LS), in terms of PHY clocks.
+                                                         This field decrements on each PHY clock. When it reaches
+                                                         zero, this field is reloaded with the value in the Frame Interval
+                                                         register and a new SOF is transmitted on the USB. */
+        uint32_t frnum                   : 16;      /**< Frame Number (FrNum)
+                                                         This field increments when a new SOF is transmitted on the
+                                                         USB, and is reset to 0 when it reaches 16'h3FFF. */
+#else
+        uint32_t frnum                   : 16;
+        uint32_t frrem                   : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_hfnum_s            cn30xx;
+    struct cvmx_usbcx_hfnum_s            cn31xx;
+    struct cvmx_usbcx_hfnum_s            cn50xx;
+    struct cvmx_usbcx_hfnum_s            cn52xx;
+    struct cvmx_usbcx_hfnum_s            cn52xxp1;
+    struct cvmx_usbcx_hfnum_s            cn56xx;
+    struct cvmx_usbcx_hfnum_s            cn56xxp1;
+} cvmx_usbcx_hfnum_t;
+
+
+/**
+ * cvmx_usbc#_hprt
+ *
+ * Host Port Control and Status Register (HPRT)
+ * 
+ * This register is available in both Host and Device modes.
+ * Currently, the OTG Host supports only one port.
+ * A single register holds USB port-related information such as USB reset, enable, suspend, resume,
+ * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an
+ * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt
+ * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear
+ * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
+ * to clear the interrupt.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hprt_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_19_31          : 13;
+        uint32_t prtspd                  : 2;       /**< Port Speed (PrtSpd)
+                                                         Indicates the speed of the device attached to this port.
+                                                         * 2'b00: High speed
+                                                         * 2'b01: Full speed
+                                                         * 2'b10: Low speed
+                                                         * 2'b11: Reserved */
+        uint32_t prttstctl               : 4;       /**< Port Test Control (PrtTstCtl)
+                                                         The application writes a nonzero value to this field to put
+                                                         the port into a Test mode, and the corresponding pattern is
+                                                         signaled on the port.
+                                                         * 4'b0000: Test mode disabled
+                                                         * 4'b0001: Test_J mode
+                                                         * 4'b0010: Test_K mode
+                                                         * 4'b0011: Test_SE0_NAK mode
+                                                         * 4'b0100: Test_Packet mode
+                                                         * 4'b0101: Test_Force_Enable
+                                                         * Others: Reserved
+                                                         PrtSpd must be zero (i.e. the interface must be in high-speed
+                                                         mode) to use the PrtTstCtl test modes. */
+        uint32_t prtpwr                  : 1;       /**< Port Power (PrtPwr)
+                                                         The application uses this field to control power to this port,
+                                                         and the core clears this bit on an overcurrent condition.
+                                                         * 1'b0: Power off
+                                                         * 1'b1: Power on */
+        uint32_t prtlnsts                : 2;       /**< Port Line Status (PrtLnSts)
+                                                         Indicates the current logic level USB data lines
+                                                         * Bit [10]: Logic level of D-
+                                                         * Bit [11]: Logic level of D+ */
+        uint32_t reserved_9_9            : 1;
+        uint32_t prtrst                  : 1;       /**< Port Reset (PrtRst)
+                                                         When the application sets this bit, a reset sequence is
+                                                         started on this port. The application must time the reset
+                                                         period and clear this bit after the reset sequence is
+                                                         complete.
+                                                         * 1'b0: Port not in reset
+                                                         * 1'b1: Port in reset
+                                                         The application must leave this bit set for at least a
+                                                         minimum duration mentioned below to start a reset on the
+                                                         port. The application can leave it set for another 10 ms in
+                                                         addition to the required minimum duration, before clearing
+                                                         the bit, even though there is no maximum limit set by the
+                                                         USB standard.
+                                                         * High speed: 50 ms
+                                                         * Full speed/Low speed: 10 ms */
+        uint32_t prtsusp                 : 1;       /**< Port Suspend (PrtSusp)
+                                                         The application sets this bit to put this port in Suspend
+                                                         mode. The core only stops sending SOFs when this is set.
+                                                         To stop the PHY clock, the application must set the Port
+                                                         Clock Stop bit, which will assert the suspend input pin of
+                                                         the PHY.
+                                                         The read value of this bit reflects the current suspend
+                                                         status of the port. This bit is cleared by the core after a
+                                                         remote wakeup signal is detected or the application sets
+                                                         the Port Reset bit or Port Resume bit in this register or the
+                                                         Resume/Remote Wakeup Detected Interrupt bit or
+                                                         Disconnect Detected Interrupt bit in the Core Interrupt
+                                                         register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
+                                                         respectively).
+                                                         * 1'b0: Port not in Suspend mode
+                                                         * 1'b1: Port in Suspend mode */
+        uint32_t prtres                  : 1;       /**< Port Resume (PrtRes)
+                                                         The application sets this bit to drive resume signaling on
+                                                         the port. The core continues to drive the resume signal
+                                                         until the application clears this bit.
+                                                         If the core detects a USB remote wakeup sequence, as
+                                                         indicated by the Port Resume/Remote Wakeup Detected
+                                                         Interrupt bit of the Core Interrupt register
+                                                         (GINTSTS.WkUpInt), the core starts driving resume
+                                                         signaling without application intervention and clears this bit
+                                                         when it detects a disconnect condition. The read value of
+                                                         this bit indicates whether the core is currently driving
+                                                         resume signaling.
+                                                         * 1'b0: No resume driven
+                                                         * 1'b1: Resume driven */
+        uint32_t prtovrcurrchng          : 1;       /**< Port Overcurrent Change (PrtOvrCurrChng)
+                                                         The core sets this bit when the status of the Port
+                                                         Overcurrent Active bit (bit 4) in this register changes. */
+        uint32_t prtovrcurract           : 1;       /**< Port Overcurrent Active (PrtOvrCurrAct)
+                                                         Indicates the overcurrent condition of the port.
+                                                         * 1'b0: No overcurrent condition
+                                                         * 1'b1: Overcurrent condition */
+        uint32_t prtenchng               : 1;       /**< Port Enable/Disable Change (PrtEnChng)
+                                                         The core sets this bit when the status of the Port Enable bit
+                                                         [2] of this register changes. */
+        uint32_t prtena                  : 1;       /**< Port Enable (PrtEna)
+                                                         A port is enabled only by the core after a reset sequence,
+                                                         and is disabled by an overcurrent condition, a disconnect
+                                                         condition, or by the application clearing this bit. The
+                                                         application cannot set this bit by a register write. It can only
+                                                         clear it to disable the port. This bit does not trigger any
+                                                         interrupt to the application.
+                                                         * 1'b0: Port disabled
+                                                         * 1'b1: Port enabled */
+        uint32_t prtconndet              : 1;       /**< Port Connect Detected (PrtConnDet)
+                                                         The core sets this bit when a device connection is detected
+                                                         to trigger an interrupt to the application using the Host Port
+                                                         Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
+                                                         The application must write a 1 to this bit to clear the
+                                                         interrupt. */
+        uint32_t prtconnsts              : 1;       /**< Port Connect Status (PrtConnSts)
+                                                         * 0: No device is attached to the port.
+                                                         * 1: A device is attached to the port. */
+#else
+        uint32_t prtconnsts              : 1;
+        uint32_t prtconndet              : 1;
+        uint32_t prtena                  : 1;
+        uint32_t prtenchng               : 1;
+        uint32_t prtovrcurract           : 1;
+        uint32_t prtovrcurrchng          : 1;
+        uint32_t prtres                  : 1;
+        uint32_t prtsusp                 : 1;
+        uint32_t prtrst                  : 1;
+        uint32_t reserved_9_9            : 1;
+        uint32_t prtlnsts                : 2;
+        uint32_t prtpwr                  : 1;
+        uint32_t prttstctl               : 4;
+        uint32_t prtspd                  : 2;
+        uint32_t reserved_19_31          : 13;
+#endif
+    } s;
+    struct cvmx_usbcx_hprt_s             cn30xx;
+    struct cvmx_usbcx_hprt_s             cn31xx;
+    struct cvmx_usbcx_hprt_s             cn50xx;
+    struct cvmx_usbcx_hprt_s             cn52xx;
+    struct cvmx_usbcx_hprt_s             cn52xxp1;
+    struct cvmx_usbcx_hprt_s             cn56xx;
+    struct cvmx_usbcx_hprt_s             cn56xxp1;
+} cvmx_usbcx_hprt_t;
+
+
+/**
+ * cvmx_usbc#_hptxfsiz
+ *
+ * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
+ * 
+ * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hptxfsiz_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ptxfsize                : 16;      /**< Host Periodic TxFIFO Depth (PTxFSize)
+                                                         This value is in terms of 32-bit words.
+                                                         * Minimum value is 16
+                                                         * Maximum value is 32768 */
+        uint32_t ptxfstaddr              : 16;      /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */
+#else
+        uint32_t ptxfstaddr              : 16;
+        uint32_t ptxfsize                : 16;
+#endif
+    } s;
+    struct cvmx_usbcx_hptxfsiz_s         cn30xx;
+    struct cvmx_usbcx_hptxfsiz_s         cn31xx;
+    struct cvmx_usbcx_hptxfsiz_s         cn50xx;
+    struct cvmx_usbcx_hptxfsiz_s         cn52xx;
+    struct cvmx_usbcx_hptxfsiz_s         cn52xxp1;
+    struct cvmx_usbcx_hptxfsiz_s         cn56xx;
+    struct cvmx_usbcx_hptxfsiz_s         cn56xxp1;
+} cvmx_usbcx_hptxfsiz_t;
+
+
+/**
+ * cvmx_usbc#_hptxsts
+ *
+ * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
+ * 
+ * This read-only register contains the free space information for the Periodic TxFIFO and
+ * the Periodic Transmit Request Queue
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_hptxsts_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t ptxqtop                 : 8;       /**< Top of the Periodic Transmit Request Queue (PTxQTop)
+                                                         This indicates the entry in the Periodic Tx Request Queue that
+                                                         is currently being processes by the MAC.
+                                                         This register is used for debugging.
+                                                         * Bit [31]: Odd/Even (micro)frame
+                                                           - 1'b0: send in even (micro)frame
+                                                           - 1'b1: send in odd (micro)frame
+                                                         * Bits [30:27]: Channel/endpoint number
+                                                         * Bits [26:25]: Type
+                                                           - 2'b00: IN/OUT
+                                                           - 2'b01: Zero-length packet
+                                                           - 2'b10: CSPLIT
+                                                           - 2'b11: Disable channel command
+                                                         * Bit [24]: Terminate (last entry for the selected
+                                                           channel/endpoint) */
+        uint32_t ptxqspcavail            : 8;       /**< Periodic Transmit Request Queue Space Available
+                                                         (PTxQSpcAvail)
+                                                         Indicates the number of free locations available to be written in
+                                                         the Periodic Transmit Request Queue. This queue holds both
+                                                         IN and OUT requests.
+                                                         * 8'h0: Periodic Transmit Request Queue is full
+                                                         * 8'h1: 1 location available
+                                                         * 8'h2: 2 locations available
+                                                         * n: n locations available (0..8)
+                                                         * Others: Reserved */
+        uint32_t ptxfspcavail            : 16;      /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
+                                                         Indicates the number of free locations available to be written to
+                                                         in the Periodic TxFIFO.
+                                                         Values are in terms of 32-bit words
+                                                         * 16'h0: Periodic TxFIFO is full
+                                                         * 16'h1: 1 word available
+                                                         * 16'h2: 2 words available
+                                                         * 16'hn: n words available (where 0..32768)
+                                                         * 16'h8000: 32768 words available
+                                                         * Others: Reserved */
+#else
+        uint32_t ptxfspcavail            : 16;
+        uint32_t ptxqspcavail            : 8;
+        uint32_t ptxqtop                 : 8;
+#endif
+    } s;
+    struct cvmx_usbcx_hptxsts_s          cn30xx;
+    struct cvmx_usbcx_hptxsts_s          cn31xx;
+    struct cvmx_usbcx_hptxsts_s          cn50xx;
+    struct cvmx_usbcx_hptxsts_s          cn52xx;
+    struct cvmx_usbcx_hptxsts_s          cn52xxp1;
+    struct cvmx_usbcx_hptxsts_s          cn56xx;
+    struct cvmx_usbcx_hptxsts_s          cn56xxp1;
+} cvmx_usbcx_hptxsts_t;
+
+
+/**
+ * cvmx_usbc#_nptxdfifo#
+ *
+ * NPTX Data Fifo (NPTXDFIFO)
+ * 
+ * A slave mode application uses this register to access the Tx FIFO for channel n.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_nptxdfifox_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t data                    : 32;      /**< Reserved */
+#else
+        uint32_t data                    : 32;
+#endif
+    } s;
+    struct cvmx_usbcx_nptxdfifox_s       cn30xx;
+    struct cvmx_usbcx_nptxdfifox_s       cn31xx;
+    struct cvmx_usbcx_nptxdfifox_s       cn50xx;
+    struct cvmx_usbcx_nptxdfifox_s       cn52xx;
+    struct cvmx_usbcx_nptxdfifox_s       cn52xxp1;
+    struct cvmx_usbcx_nptxdfifox_s       cn56xx;
+    struct cvmx_usbcx_nptxdfifox_s       cn56xxp1;
+} cvmx_usbcx_nptxdfifox_t;
+
+
+/**
+ * cvmx_usbc#_pcgcctl
+ *
+ * Power and Clock Gating Control Register (PCGCCTL)
+ * 
+ * The application can use this register to control the core's power-down and clock gating features.
+ */
+typedef union
+{
+    uint32_t u32;
+    struct cvmx_usbcx_pcgcctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint32_t reserved_5_31           : 27;
+        uint32_t physuspended            : 1;       /**< PHY Suspended. (PhySuspended)
+                                                         Indicates that the PHY has been suspended. After the
+                                                         application sets the Stop Pclk bit (bit 0), this bit is updated once
+                                                         the PHY is suspended.
+                                                         Since the UTMI+ PHY suspend is controlled through a port, the
+                                                         UTMI+ PHY is suspended immediately after Stop Pclk is set.
+                                                         However, the ULPI PHY takes a few clocks to suspend,
+                                                         because the suspend information is conveyed through the ULPI
+                                                         protocol to the ULPI PHY. */
+        uint32_t rstpdwnmodule           : 1;       /**< Reset Power-Down Modules (RstPdwnModule)
+                                                         This bit is valid only in Partial Power-Down mode. The
+                                                         application sets this bit when the power is turned off. The
+                                                         application clears this bit after the power is turned on and the
+                                                         PHY clock is up. */
+        uint32_t pwrclmp                 : 1;       /**< Power Clamp (PwrClmp)
+                                                         This bit is only valid in Partial Power-Down mode. The
+                                                         application sets this bit before the power is turned off to clamp
+                                                         the signals between the power-on modules and the power-off
+                                                         modules. The application clears the bit to disable the clamping
+                                                         before the power is turned on. */
+        uint32_t gatehclk                : 1;       /**< Gate Hclk (GateHclk)
+                                                         The application sets this bit to gate hclk to modules other than
+                                                         the AHB Slave and Master and wakeup logic when the USB is
+                                                         suspended or the session is not valid. The application clears
+                                                         this bit when the USB is resumed or a new session starts. */
+        uint32_t stoppclk                : 1;       /**< Stop Pclk (StopPclk)
+                                                         The application sets this bit to stop the PHY clock (phy_clk)
+                                                         when the USB is suspended, the session is not valid, or the
+                                                         device is disconnected. The application clears this bit when the
+                                                         USB is resumed or a new session starts. */
+#else
+        uint32_t stoppclk                : 1;
+        uint32_t gatehclk                : 1;
+        uint32_t pwrclmp                 : 1;
+        uint32_t rstpdwnmodule           : 1;
+        uint32_t physuspended            : 1;
+        uint32_t reserved_5_31           : 27;
+#endif
+    } s;
+    struct cvmx_usbcx_pcgcctl_s          cn30xx;
+    struct cvmx_usbcx_pcgcctl_s          cn31xx;
+    struct cvmx_usbcx_pcgcctl_s          cn50xx;
+    struct cvmx_usbcx_pcgcctl_s          cn52xx;
+    struct cvmx_usbcx_pcgcctl_s          cn52xxp1;
+    struct cvmx_usbcx_pcgcctl_s          cn56xx;
+    struct cvmx_usbcx_pcgcctl_s          cn56xxp1;
+} cvmx_usbcx_pcgcctl_t;
+
+
+/**
+ * cvmx_usbn#_bist_status
+ *
+ * USBN_BIST_STATUS = USBN's Control and Status
+ * 
+ * Contain general control bits and status information for the USBN.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_bist_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_7_63           : 57;
+        uint64_t u2nc_bis                : 1;       /**< Bist status U2N CTL FIFO Memory. */
+        uint64_t u2nf_bis                : 1;       /**< Bist status U2N FIFO Memory. */
+        uint64_t e2hc_bis                : 1;       /**< Bist status E2H CTL FIFO Memory. */
+        uint64_t n2uf_bis                : 1;       /**< Bist status N2U  FIFO Memory. */
+        uint64_t usbc_bis                : 1;       /**< Bist status USBC FIFO Memory. */
+        uint64_t nif_bis                 : 1;       /**< Bist status for Inbound Memory. */
+        uint64_t nof_bis                 : 1;       /**< Bist status for Outbound Memory. */
+#else
+        uint64_t nof_bis                 : 1;
+        uint64_t nif_bis                 : 1;
+        uint64_t usbc_bis                : 1;
+        uint64_t n2uf_bis                : 1;
+        uint64_t e2hc_bis                : 1;
+        uint64_t u2nf_bis                : 1;
+        uint64_t u2nc_bis                : 1;
+        uint64_t reserved_7_63           : 57;
+#endif
+    } s;
+    struct cvmx_usbnx_bist_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_3_63           : 61;
+        uint64_t usbc_bis                : 1;       /**< Bist status USBC FIFO Memory. */
+        uint64_t nif_bis                 : 1;       /**< Bist status for Inbound Memory. */
+        uint64_t nof_bis                 : 1;       /**< Bist status for Outbound Memory. */
+#else
+        uint64_t nof_bis                 : 1;
+        uint64_t nif_bis                 : 1;
+        uint64_t usbc_bis                : 1;
+        uint64_t reserved_3_63           : 61;
+#endif
+    } cn30xx;
+    struct cvmx_usbnx_bist_status_cn30xx cn31xx;
+    struct cvmx_usbnx_bist_status_s      cn50xx;
+    struct cvmx_usbnx_bist_status_s      cn52xx;
+    struct cvmx_usbnx_bist_status_s      cn52xxp1;
+    struct cvmx_usbnx_bist_status_s      cn56xx;
+    struct cvmx_usbnx_bist_status_s      cn56xxp1;
+} cvmx_usbnx_bist_status_t;
+
+
+/**
+ * cvmx_usbn#_clk_ctl
+ *
+ * USBN_CLK_CTL = USBN's Clock Control
+ * 
+ * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_clk_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t divide2                 : 2;       /**< The 'hclk' used by the USB subsystem is derived
+                                                         from the eclk.
+                                                         Also see the field DIVIDE. DIVIDE2<1> must currently
+                                                         be zero because it is not implemented, so the maximum
+                                                         ratio of eclk/hclk is currently 16.
+                                                         The actual divide number for hclk is:
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1) */
+        uint64_t hclk_rst                : 1;       /**< When this field is '0' the HCLK-DIVIDER used to
+                                                         generate the hclk in the USB Subsystem is held
+                                                         in reset. This bit must be set to '0' before
+                                                         changing the value os DIVIDE in this register.
+                                                         The reset to the HCLK_DIVIDERis also asserted
+                                                         when core reset is asserted. */
+        uint64_t p_x_on                  : 1;       /**< Force USB-PHY on during suspend.
+                                                         '1' USB-PHY XO block is powered-down during
+                                                             suspend.
+                                                         '0' USB-PHY XO block is powered-up during
+                                                             suspend.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+        uint64_t reserved_14_15          : 2;
+        uint64_t p_com_on                : 1;       /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
+                                                             remain powered in Suspend Mode.
+                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
+                                                             powered down in suspend mode.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+        uint64_t p_c_sel                 : 2;       /**< Phy clock speed select.
+                                                         Selects the reference clock / crystal frequency.
+                                                         '11': Reserved
+                                                         '10': 48 MHz (reserved when a crystal is used)
+                                                         '01': 24 MHz (reserved when a crystal is used)
+                                                         '00': 12 MHz
+                                                         The value of this field must be set while POR is
+                                                         active.
+                                                         NOTE: if a crystal is used as a reference clock,
+                                                         this field must be set to 12 MHz. */
+        uint64_t cdiv_byp                : 1;       /**< Used to enable the bypass input to the USB_CLK_DIV. */
+        uint64_t sd_mode                 : 2;       /**< Scaledown mode for the USBC. Control timing events
+                                                         in the USBC, for normal operation this must be '0'. */
+        uint64_t s_bist                  : 1;       /**< Starts bist on the hclk memories, during the '0'
+                                                         to '1' transition. */
+        uint64_t por                     : 1;       /**< Power On Reset for the PHY.
+                                                         Resets all the PHYS registers and state machines. */
+        uint64_t enable                  : 1;       /**< When '1' allows the generation of the hclk. When
+                                                         '0' the hclk will not be generated. SEE DIVIDE
+                                                         field of this register. */
+        uint64_t prst                    : 1;       /**< When this field is '0' the reset associated with
+                                                         the phy_clk functionality in the USB Subsystem is
+                                                         help in reset. This bit should not be set to '1'
+                                                         until the time it takes 6 clocks (hclk or phy_clk,
+                                                         whichever is slower) has passed. Under normal
+                                                         operation once this bit is set to '1' it should not
+                                                         be set to '0'. */
+        uint64_t hrst                    : 1;       /**< When this field is '0' the reset associated with
+                                                         the hclk functioanlity in the USB Subsystem is
+                                                         held in reset.This bit should not be set to '1'
+                                                         until 12ms after phy_clk is stable. Under normal
+                                                         operation, once this bit is set to '1' it should
+                                                         not be set to '0'. */
+        uint64_t divide                  : 3;       /**< The frequency of 'hclk' used by the USB subsystem
+                                                         is the eclk frequency divided by the value of
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
+                                                         DIVIDE2 of this register.
+                                                         The hclk frequency should be less than 125Mhz.
+                                                         After writing a value to this field the SW should
+                                                         read the field for the value written.
+                                                         The ENABLE field of this register should not be set
+                                                         until AFTER this field is set and then read. */
+#else
+        uint64_t divide                  : 3;
+        uint64_t hrst                    : 1;
+        uint64_t prst                    : 1;
+        uint64_t enable                  : 1;
+        uint64_t por                     : 1;
+        uint64_t s_bist                  : 1;
+        uint64_t sd_mode                 : 2;
+        uint64_t cdiv_byp                : 1;
+        uint64_t p_c_sel                 : 2;
+        uint64_t p_com_on                : 1;
+        uint64_t reserved_14_15          : 2;
+        uint64_t p_x_on                  : 1;
+        uint64_t hclk_rst                : 1;
+        uint64_t divide2                 : 2;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } s;
+    struct cvmx_usbnx_clk_ctl_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_18_63          : 46;
+        uint64_t hclk_rst                : 1;       /**< When this field is '0' the HCLK-DIVIDER used to
+                                                         generate the hclk in the USB Subsystem is held
+                                                         in reset. This bit must be set to '0' before
+                                                         changing the value os DIVIDE in this register.
+                                                         The reset to the HCLK_DIVIDERis also asserted
+                                                         when core reset is asserted. */
+        uint64_t p_x_on                  : 1;       /**< Force USB-PHY on during suspend.
+                                                         '1' USB-PHY XO block is powered-down during
+                                                             suspend.
+                                                         '0' USB-PHY XO block is powered-up during
+                                                             suspend.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+        uint64_t p_rclk                  : 1;       /**< Phy refrence clock enable.
+                                                         '1' The PHY PLL uses the XO block output as a
+                                                         reference.
+                                                         '0' Reserved. */
+        uint64_t p_xenbn                 : 1;       /**< Phy external clock enable.
+                                                         '1' The XO block uses the clock from a crystal.
+                                                         '0' The XO block uses an external clock supplied
+                                                             on the XO pin. USB_XI should be tied to
+                                                             ground for this usage. */
+        uint64_t p_com_on                : 1;       /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
+                                                             remain powered in Suspend Mode.
+                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
+                                                             powered down in suspend mode.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+        uint64_t p_c_sel                 : 2;       /**< Phy clock speed select.
+                                                         Selects the reference clock / crystal frequency.
+                                                         '11': Reserved
+                                                         '10': 48 MHz
+                                                         '01': 24 MHz
+                                                         '00': 12 MHz
+                                                         The value of this field must be set while POR is
+                                                         active. */
+        uint64_t cdiv_byp                : 1;       /**< Used to enable the bypass input to the USB_CLK_DIV. */
+        uint64_t sd_mode                 : 2;       /**< Scaledown mode for the USBC. Control timing events
+                                                         in the USBC, for normal operation this must be '0'. */
+        uint64_t s_bist                  : 1;       /**< Starts bist on the hclk memories, during the '0'
+                                                         to '1' transition. */
+        uint64_t por                     : 1;       /**< Power On Reset for the PHY.
+                                                         Resets all the PHYS registers and state machines. */
+        uint64_t enable                  : 1;       /**< When '1' allows the generation of the hclk. When
+                                                         '0' the hclk will not be generated. */
+        uint64_t prst                    : 1;       /**< When this field is '0' the reset associated with
+                                                         the phy_clk functionality in the USB Subsystem is
+                                                         help in reset. This bit should not be set to '1'
+                                                         until the time it takes 6 clocks (hclk or phy_clk,
+                                                         whichever is slower) has passed. Under normal
+                                                         operation once this bit is set to '1' it should not
+                                                         be set to '0'. */
+        uint64_t hrst                    : 1;       /**< When this field is '0' the reset associated with
+                                                         the hclk functioanlity in the USB Subsystem is
+                                                         held in reset.This bit should not be set to '1'
+                                                         until 12ms after phy_clk is stable. Under normal
+                                                         operation, once this bit is set to '1' it should
+                                                         not be set to '0'. */
+        uint64_t divide                  : 3;       /**< The 'hclk' used by the USB subsystem is derived
+                                                         from the eclk. The eclk will be divided by the
+                                                         value of this field +1 to determine the hclk
+                                                         frequency. (Also see HRST of this register).
+                                                         The hclk frequency must be less than 125 MHz. */
+#else
+        uint64_t divide                  : 3;
+        uint64_t hrst                    : 1;
+        uint64_t prst                    : 1;
+        uint64_t enable                  : 1;
+        uint64_t por                     : 1;
+        uint64_t s_bist                  : 1;
+        uint64_t sd_mode                 : 2;
+        uint64_t cdiv_byp                : 1;
+        uint64_t p_c_sel                 : 2;
+        uint64_t p_com_on                : 1;
+        uint64_t p_xenbn                 : 1;
+        uint64_t p_rclk                  : 1;
+        uint64_t p_x_on                  : 1;
+        uint64_t hclk_rst                : 1;
+        uint64_t reserved_18_63          : 46;
+#endif
+    } cn30xx;
+    struct cvmx_usbnx_clk_ctl_cn30xx     cn31xx;
+    struct cvmx_usbnx_clk_ctl_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_20_63          : 44;
+        uint64_t divide2                 : 2;       /**< The 'hclk' used by the USB subsystem is derived
+                                                         from the eclk.
+                                                         Also see the field DIVIDE. DIVIDE2<1> must currently
+                                                         be zero because it is not implemented, so the maximum
+                                                         ratio of eclk/hclk is currently 16.
+                                                         The actual divide number for hclk is:
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1) */
+        uint64_t hclk_rst                : 1;       /**< When this field is '0' the HCLK-DIVIDER used to
+                                                         generate the hclk in the USB Subsystem is held
+                                                         in reset. This bit must be set to '0' before
+                                                         changing the value os DIVIDE in this register.
+                                                         The reset to the HCLK_DIVIDERis also asserted
+                                                         when core reset is asserted. */
+        uint64_t reserved_16_16          : 1;
+        uint64_t p_rtype                 : 2;       /**< PHY reference clock type
+                                                         '0' The USB-PHY uses a 12MHz crystal as a clock
+                                                             source at the USB_XO and USB_XI pins
+                                                         '1' Reserved
+                                                         '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
+                                                             at the USB_XO pin. USB_XI should be tied to
+                                                             ground in this case.
+                                                         '3' Reserved
+                                                         (bit 14 was P_XENBN on 3xxx)
+                                                         (bit 15 was P_RCLK on 3xxx) */
+        uint64_t p_com_on                : 1;       /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
+                                                             remain powered in Suspend Mode.
+                                                         '1' The USB-PHY XO Bias, Bandgap and PLL are
+                                                             powered down in suspend mode.
+                                                         The value of this field must be set while POR is
+                                                         active. */
+        uint64_t p_c_sel                 : 2;       /**< Phy clock speed select.
+                                                         Selects the reference clock / crystal frequency.
+                                                         '11': Reserved
+                                                         '10': 48 MHz (reserved when a crystal is used)
+                                                         '01': 24 MHz (reserved when a crystal is used)
+                                                         '00': 12 MHz
+                                                         The value of this field must be set while POR is
+                                                         active.
+                                                         NOTE: if a crystal is used as a reference clock,
+                                                         this field must be set to 12 MHz. */
+        uint64_t cdiv_byp                : 1;       /**< Used to enable the bypass input to the USB_CLK_DIV. */
+        uint64_t sd_mode                 : 2;       /**< Scaledown mode for the USBC. Control timing events
+                                                         in the USBC, for normal operation this must be '0'. */
+        uint64_t s_bist                  : 1;       /**< Starts bist on the hclk memories, during the '0'
+                                                         to '1' transition. */
+        uint64_t por                     : 1;       /**< Power On Reset for the PHY.
+                                                         Resets all the PHYS registers and state machines. */
+        uint64_t enable                  : 1;       /**< When '1' allows the generation of the hclk. When
+                                                         '0' the hclk will not be generated. SEE DIVIDE
+                                                         field of this register. */
+        uint64_t prst                    : 1;       /**< When this field is '0' the reset associated with
+                                                         the phy_clk functionality in the USB Subsystem is
+                                                         help in reset. This bit should not be set to '1'
+                                                         until the time it takes 6 clocks (hclk or phy_clk,
+                                                         whichever is slower) has passed. Under normal
+                                                         operation once this bit is set to '1' it should not
+                                                         be set to '0'. */
+        uint64_t hrst                    : 1;       /**< When this field is '0' the reset associated with
+                                                         the hclk functioanlity in the USB Subsystem is
+                                                         held in reset.This bit should not be set to '1'
+                                                         until 12ms after phy_clk is stable. Under normal
+                                                         operation, once this bit is set to '1' it should
+                                                         not be set to '0'. */
+        uint64_t divide                  : 3;       /**< The frequency of 'hclk' used by the USB subsystem
+                                                         is the eclk frequency divided by the value of
+                                                         (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
+                                                         DIVIDE2 of this register.
+                                                         The hclk frequency should be less than 125Mhz.
+                                                         After writing a value to this field the SW should
+                                                         read the field for the value written.
+                                                         The ENABLE field of this register should not be set
+                                                         until AFTER this field is set and then read. */
+#else
+        uint64_t divide                  : 3;
+        uint64_t hrst                    : 1;
+        uint64_t prst                    : 1;
+        uint64_t enable                  : 1;
+        uint64_t por                     : 1;
+        uint64_t s_bist                  : 1;
+        uint64_t sd_mode                 : 2;
+        uint64_t cdiv_byp                : 1;
+        uint64_t p_c_sel                 : 2;
+        uint64_t p_com_on                : 1;
+        uint64_t p_rtype                 : 2;
+        uint64_t reserved_16_16          : 1;
+        uint64_t hclk_rst                : 1;
+        uint64_t divide2                 : 2;
+        uint64_t reserved_20_63          : 44;
+#endif
+    } cn50xx;
+    struct cvmx_usbnx_clk_ctl_cn50xx     cn52xx;
+    struct cvmx_usbnx_clk_ctl_cn50xx     cn52xxp1;
+    struct cvmx_usbnx_clk_ctl_cn50xx     cn56xx;
+    struct cvmx_usbnx_clk_ctl_cn50xx     cn56xxp1;
+} cvmx_usbnx_clk_ctl_t;
+
+
+/**
+ * cvmx_usbn#_ctl_status
+ *
+ * USBN_CTL_STATUS = USBN's Control And Status Register
+ * 
+ * Contains general control and status information for the USBN block.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_6_63           : 58;
+        uint64_t dma_0pag                : 1;       /**< When '1' sets the DMA engine will set the zero-Page
+                                                         bit in the L2C store operation to the IOB. */
+        uint64_t dma_stt                 : 1;       /**< When '1' sets the DMA engine to use STT operations. */
+        uint64_t dma_test                : 1;       /**< When '1' sets the DMA engine into Test-Mode.
+                                                         For normal operation this bit should be '0'. */
+        uint64_t inv_a2                  : 1;       /**< When '1' causes the address[2] driven on the AHB
+                                                         for USB-CORE FIFO access to be inverted. Also data
+                                                         writen to and read from the AHB will have it byte
+                                                         order swapped. If the orginal order was A-B-C-D the
+                                                         new byte order will be D-C-B-A. */
+        uint64_t l2c_emod                : 2;       /**< Endian format for data from/to the L2C.
+                                                         IN:   A-B-C-D-E-F-G-H
+                                                         OUT0: A-B-C-D-E-F-G-H
+                                                         OUT1: H-G-F-E-D-C-B-A
+                                                         OUT2: D-C-B-A-H-G-F-E
+                                                         OUT3: E-F-G-H-A-B-C-D */
+#else
+        uint64_t l2c_emod                : 2;
+        uint64_t inv_a2                  : 1;
+        uint64_t dma_test                : 1;
+        uint64_t dma_stt                 : 1;
+        uint64_t dma_0pag                : 1;
+        uint64_t reserved_6_63           : 58;
+#endif
+    } s;
+    struct cvmx_usbnx_ctl_status_s       cn30xx;
+    struct cvmx_usbnx_ctl_status_s       cn31xx;
+    struct cvmx_usbnx_ctl_status_s       cn50xx;
+    struct cvmx_usbnx_ctl_status_s       cn52xx;
+    struct cvmx_usbnx_ctl_status_s       cn52xxp1;
+    struct cvmx_usbnx_ctl_status_s       cn56xx;
+    struct cvmx_usbnx_ctl_status_s       cn56xxp1;
+} cvmx_usbnx_ctl_status_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn0
+ *
+ * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel0.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn0_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn0_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn1
+ *
+ * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel1.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn1_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn1_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn2
+ *
+ * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel2.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn2_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn2_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn3
+ *
+ * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel3.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn3_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn3_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn4
+ *
+ * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel4.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn4_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn4_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn5
+ *
+ * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel5.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn5_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn5_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn6
+ *
+ * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel6.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn6_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn6_t;
+
+
+/**
+ * cvmx_usbn#_dma0_inb_chn7
+ *
+ * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7
+ * 
+ * Contains the starting address for use when USB0 writes to L2C via Channel7.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_inb_chn7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Write to L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn30xx;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn31xx;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn50xx;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn52xx;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn52xxp1;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn56xx;
+    struct cvmx_usbnx_dma0_inb_chn7_s    cn56xxp1;
+} cvmx_usbnx_dma0_inb_chn7_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn0
+ *
+ * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel0.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn0_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn0_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn1
+ *
+ * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel1.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn1_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn1_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn1_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn2
+ *
+ * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel2.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn2_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn2_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn2_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn3
+ *
+ * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel3.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn3_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn3_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn3_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn4
+ *
+ * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel4.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn4_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn4_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn4_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn5
+ *
+ * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel5.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn5_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn5_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn5_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn6
+ *
+ * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel6.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn6_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn6_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn6_t;
+
+
+/**
+ * cvmx_usbn#_dma0_outb_chn7
+ *
+ * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7
+ * 
+ * Contains the starting address for use when USB0 reads from L2C via Channel7.
+ * Writing of this register sets the base address.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma0_outb_chn7_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_36_63          : 28;
+        uint64_t addr                    : 36;      /**< Base address for DMA Read from L2C. */
+#else
+        uint64_t addr                    : 36;
+        uint64_t reserved_36_63          : 28;
+#endif
+    } s;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn30xx;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn31xx;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn50xx;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn52xx;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn52xxp1;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn56xx;
+    struct cvmx_usbnx_dma0_outb_chn7_s   cn56xxp1;
+} cvmx_usbnx_dma0_outb_chn7_t;
+
+
+/**
+ * cvmx_usbn#_dma_test
+ *
+ * USBN_DMA_TEST = USBN's DMA TestRegister
+ * 
+ * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_dma_test_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_40_63          : 24;
+        uint64_t done                    : 1;       /**< This field is set when a DMA completes. Writing a
+                                                         '1' to this field clears this bit. */
+        uint64_t req                     : 1;       /**< DMA Request. Writing a 1 to this register
+                                                         will cause a DMA request as specified in the other
+                                                         fields of this register to take place. This field
+                                                         will always read as '0'. */
+        uint64_t f_addr                  : 18;      /**< The address to read from in the Data-Fifo. */
+        uint64_t count                   : 11;      /**< DMA Request Count. */
+        uint64_t channel                 : 5;       /**< DMA Channel/Enpoint. */
+        uint64_t burst                   : 4;       /**< DMA Burst Size. */
+#else
+        uint64_t burst                   : 4;
+        uint64_t channel                 : 5;
+        uint64_t count                   : 11;
+        uint64_t f_addr                  : 18;
+        uint64_t req                     : 1;
+        uint64_t done                    : 1;
+        uint64_t reserved_40_63          : 24;
+#endif
+    } s;
+    struct cvmx_usbnx_dma_test_s         cn30xx;
+    struct cvmx_usbnx_dma_test_s         cn31xx;
+    struct cvmx_usbnx_dma_test_s         cn50xx;
+    struct cvmx_usbnx_dma_test_s         cn52xx;
+    struct cvmx_usbnx_dma_test_s         cn52xxp1;
+    struct cvmx_usbnx_dma_test_s         cn56xx;
+    struct cvmx_usbnx_dma_test_s         cn56xxp1;
+} cvmx_usbnx_dma_test_t;
+
+
+/**
+ * cvmx_usbn#_int_enb
+ *
+ * USBN_INT_ENB = USBN's Interrupt Enable
+ * 
+ * The USBN's interrupt enable register.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_int_enb_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t nd4o_dpf                : 1;       /**< When set (1) and bit 37 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nd4o_dpe                : 1;       /**< When set (1) and bit 36 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nd4o_rpf                : 1;       /**< When set (1) and bit 35 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nd4o_rpe                : 1;       /**< When set (1) and bit 34 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t ltl_f_pf                : 1;       /**< When set (1) and bit 33 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t ltl_f_pe                : 1;       /**< When set (1) and bit 32 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t u2n_c_pe                : 1;       /**< When set (1) and bit 31 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t u2n_c_pf                : 1;       /**< When set (1) and bit 30 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t u2n_d_pf                : 1;       /**< When set (1) and bit 29 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t u2n_d_pe                : 1;       /**< When set (1) and bit 28 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t n2u_pe                  : 1;       /**< When set (1) and bit 27 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t n2u_pf                  : 1;       /**< When set (1) and bit 26 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t uod_pf                  : 1;       /**< When set (1) and bit 25 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t uod_pe                  : 1;       /**< When set (1) and bit 24 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q3_e                 : 1;       /**< When set (1) and bit 23 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q3_f                 : 1;       /**< When set (1) and bit 22 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q2_e                 : 1;       /**< When set (1) and bit 21 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q2_f                 : 1;       /**< When set (1) and bit 20 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rg_fi_f                 : 1;       /**< When set (1) and bit 19 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rg_fi_e                 : 1;       /**< When set (1) and bit 18 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2_fi_f                 : 1;       /**< When set (1) and bit 17 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2_fi_e                 : 1;       /**< When set (1) and bit 16 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2c_a_f                 : 1;       /**< When set (1) and bit 15 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2c_s_e                 : 1;       /**< When set (1) and bit 14 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t dcred_f                 : 1;       /**< When set (1) and bit 13 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t dcred_e                 : 1;       /**< When set (1) and bit 12 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lt_pu_f                 : 1;       /**< When set (1) and bit 11 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lt_po_e                 : 1;       /**< When set (1) and bit 10 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nt_pu_f                 : 1;       /**< When set (1) and bit 9 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nt_po_e                 : 1;       /**< When set (1) and bit 8 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pt_pu_f                 : 1;       /**< When set (1) and bit 7 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pt_po_e                 : 1;       /**< When set (1) and bit 6 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lr_pu_f                 : 1;       /**< When set (1) and bit 5 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lr_po_e                 : 1;       /**< When set (1) and bit 4 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nr_pu_f                 : 1;       /**< When set (1) and bit 3 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nr_po_e                 : 1;       /**< When set (1) and bit 2 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pr_pu_f                 : 1;       /**< When set (1) and bit 1 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pr_po_e                 : 1;       /**< When set (1) and bit 0 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+#else
+        uint64_t pr_po_e                 : 1;
+        uint64_t pr_pu_f                 : 1;
+        uint64_t nr_po_e                 : 1;
+        uint64_t nr_pu_f                 : 1;
+        uint64_t lr_po_e                 : 1;
+        uint64_t lr_pu_f                 : 1;
+        uint64_t pt_po_e                 : 1;
+        uint64_t pt_pu_f                 : 1;
+        uint64_t nt_po_e                 : 1;
+        uint64_t nt_pu_f                 : 1;
+        uint64_t lt_po_e                 : 1;
+        uint64_t lt_pu_f                 : 1;
+        uint64_t dcred_e                 : 1;
+        uint64_t dcred_f                 : 1;
+        uint64_t l2c_s_e                 : 1;
+        uint64_t l2c_a_f                 : 1;
+        uint64_t l2_fi_e                 : 1;
+        uint64_t l2_fi_f                 : 1;
+        uint64_t rg_fi_e                 : 1;
+        uint64_t rg_fi_f                 : 1;
+        uint64_t rq_q2_f                 : 1;
+        uint64_t rq_q2_e                 : 1;
+        uint64_t rq_q3_f                 : 1;
+        uint64_t rq_q3_e                 : 1;
+        uint64_t uod_pe                  : 1;
+        uint64_t uod_pf                  : 1;
+        uint64_t n2u_pf                  : 1;
+        uint64_t n2u_pe                  : 1;
+        uint64_t u2n_d_pe                : 1;
+        uint64_t u2n_d_pf                : 1;
+        uint64_t u2n_c_pf                : 1;
+        uint64_t u2n_c_pe                : 1;
+        uint64_t ltl_f_pe                : 1;
+        uint64_t ltl_f_pf                : 1;
+        uint64_t nd4o_rpe                : 1;
+        uint64_t nd4o_rpf                : 1;
+        uint64_t nd4o_dpe                : 1;
+        uint64_t nd4o_dpf                : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_usbnx_int_enb_s          cn30xx;
+    struct cvmx_usbnx_int_enb_s          cn31xx;
+    struct cvmx_usbnx_int_enb_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t nd4o_dpf                : 1;       /**< When set (1) and bit 37 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nd4o_dpe                : 1;       /**< When set (1) and bit 36 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nd4o_rpf                : 1;       /**< When set (1) and bit 35 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nd4o_rpe                : 1;       /**< When set (1) and bit 34 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t ltl_f_pf                : 1;       /**< When set (1) and bit 33 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t ltl_f_pe                : 1;       /**< When set (1) and bit 32 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t reserved_26_31          : 6;
+        uint64_t uod_pf                  : 1;       /**< When set (1) and bit 25 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t uod_pe                  : 1;       /**< When set (1) and bit 24 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q3_e                 : 1;       /**< When set (1) and bit 23 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q3_f                 : 1;       /**< When set (1) and bit 22 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q2_e                 : 1;       /**< When set (1) and bit 21 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rq_q2_f                 : 1;       /**< When set (1) and bit 20 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rg_fi_f                 : 1;       /**< When set (1) and bit 19 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t rg_fi_e                 : 1;       /**< When set (1) and bit 18 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2_fi_f                 : 1;       /**< When set (1) and bit 17 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2_fi_e                 : 1;       /**< When set (1) and bit 16 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2c_a_f                 : 1;       /**< When set (1) and bit 15 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t l2c_s_e                 : 1;       /**< When set (1) and bit 14 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t dcred_f                 : 1;       /**< When set (1) and bit 13 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t dcred_e                 : 1;       /**< When set (1) and bit 12 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lt_pu_f                 : 1;       /**< When set (1) and bit 11 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lt_po_e                 : 1;       /**< When set (1) and bit 10 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nt_pu_f                 : 1;       /**< When set (1) and bit 9 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nt_po_e                 : 1;       /**< When set (1) and bit 8 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pt_pu_f                 : 1;       /**< When set (1) and bit 7 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pt_po_e                 : 1;       /**< When set (1) and bit 6 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lr_pu_f                 : 1;       /**< When set (1) and bit 5 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t lr_po_e                 : 1;       /**< When set (1) and bit 4 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nr_pu_f                 : 1;       /**< When set (1) and bit 3 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t nr_po_e                 : 1;       /**< When set (1) and bit 2 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pr_pu_f                 : 1;       /**< When set (1) and bit 1 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+        uint64_t pr_po_e                 : 1;       /**< When set (1) and bit 0 of the USBN_INT_SUM
+                                                         register is asserted the USBN will assert an
+                                                         interrupt. */
+#else
+        uint64_t pr_po_e                 : 1;
+        uint64_t pr_pu_f                 : 1;
+        uint64_t nr_po_e                 : 1;
+        uint64_t nr_pu_f                 : 1;
+        uint64_t lr_po_e                 : 1;
+        uint64_t lr_pu_f                 : 1;
+        uint64_t pt_po_e                 : 1;
+        uint64_t pt_pu_f                 : 1;
+        uint64_t nt_po_e                 : 1;
+        uint64_t nt_pu_f                 : 1;
+        uint64_t lt_po_e                 : 1;
+        uint64_t lt_pu_f                 : 1;
+        uint64_t dcred_e                 : 1;
+        uint64_t dcred_f                 : 1;
+        uint64_t l2c_s_e                 : 1;
+        uint64_t l2c_a_f                 : 1;
+        uint64_t l2_fi_e                 : 1;
+        uint64_t l2_fi_f                 : 1;
+        uint64_t rg_fi_e                 : 1;
+        uint64_t rg_fi_f                 : 1;
+        uint64_t rq_q2_f                 : 1;
+        uint64_t rq_q2_e                 : 1;
+        uint64_t rq_q3_f                 : 1;
+        uint64_t rq_q3_e                 : 1;
+        uint64_t uod_pe                  : 1;
+        uint64_t uod_pf                  : 1;
+        uint64_t reserved_26_31          : 6;
+        uint64_t ltl_f_pe                : 1;
+        uint64_t ltl_f_pf                : 1;
+        uint64_t nd4o_rpe                : 1;
+        uint64_t nd4o_rpf                : 1;
+        uint64_t nd4o_dpe                : 1;
+        uint64_t nd4o_dpf                : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } cn50xx;
+    struct cvmx_usbnx_int_enb_cn50xx     cn52xx;
+    struct cvmx_usbnx_int_enb_cn50xx     cn52xxp1;
+    struct cvmx_usbnx_int_enb_cn50xx     cn56xx;
+    struct cvmx_usbnx_int_enb_cn50xx     cn56xxp1;
+} cvmx_usbnx_int_enb_t;
+
+
+/**
+ * cvmx_usbn#_int_sum
+ *
+ * USBN_INT_SUM = USBN's Interrupt Summary Register
+ * 
+ * Contains the diffrent interrupt summary bits of the USBN.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_int_sum_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t nd4o_dpf                : 1;       /**< NCB DMA Out Data Fifo Push Full. */
+        uint64_t nd4o_dpe                : 1;       /**< NCB DMA Out Data Fifo Pop Empty. */
+        uint64_t nd4o_rpf                : 1;       /**< NCB DMA Out Request Fifo Push Full. */
+        uint64_t nd4o_rpe                : 1;       /**< NCB DMA Out Request Fifo Pop Empty. */
+        uint64_t ltl_f_pf                : 1;       /**< L2C Transfer Length Fifo Push Full. */
+        uint64_t ltl_f_pe                : 1;       /**< L2C Transfer Length Fifo Pop Empty. */
+        uint64_t u2n_c_pe                : 1;       /**< U2N Control Fifo Pop Empty. */
+        uint64_t u2n_c_pf                : 1;       /**< U2N Control Fifo Push Full. */
+        uint64_t u2n_d_pf                : 1;       /**< U2N Data Fifo Push Full. */
+        uint64_t u2n_d_pe                : 1;       /**< U2N Data Fifo Pop Empty. */
+        uint64_t n2u_pe                  : 1;       /**< N2U Fifo Pop Empty. */
+        uint64_t n2u_pf                  : 1;       /**< N2U Fifo Push Full. */
+        uint64_t uod_pf                  : 1;       /**< UOD Fifo Push Full. */
+        uint64_t uod_pe                  : 1;       /**< UOD Fifo Pop Empty. */
+        uint64_t rq_q3_e                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
+        uint64_t rq_q3_f                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
+        uint64_t rq_q2_e                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
+        uint64_t rq_q2_f                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
+        uint64_t rg_fi_f                 : 1;       /**< Register Request Fifo Pushed When Full. */
+        uint64_t rg_fi_e                 : 1;       /**< Register Request Fifo Pushed When Full. */
+        uint64_t lt_fi_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
+        uint64_t lt_fi_e                 : 1;       /**< L2C Request Fifo Pushed When Full. */
+        uint64_t l2c_a_f                 : 1;       /**< L2C Credit Count Added When Full. */
+        uint64_t l2c_s_e                 : 1;       /**< L2C Credit Count Subtracted When Empty. */
+        uint64_t dcred_f                 : 1;       /**< Data CreditFifo Pushed When Full. */
+        uint64_t dcred_e                 : 1;       /**< Data Credit Fifo Pushed When Full. */
+        uint64_t lt_pu_f                 : 1;       /**< L2C Trasaction Fifo Pushed When Full. */
+        uint64_t lt_po_e                 : 1;       /**< L2C Trasaction Fifo Popped When Full. */
+        uint64_t nt_pu_f                 : 1;       /**< NPI Trasaction Fifo Pushed When Full. */
+        uint64_t nt_po_e                 : 1;       /**< NPI Trasaction Fifo Popped When Full. */
+        uint64_t pt_pu_f                 : 1;       /**< PP  Trasaction Fifo Pushed When Full. */
+        uint64_t pt_po_e                 : 1;       /**< PP  Trasaction Fifo Popped When Full. */
+        uint64_t lr_pu_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
+        uint64_t lr_po_e                 : 1;       /**< L2C Request Fifo Popped When Empty. */
+        uint64_t nr_pu_f                 : 1;       /**< NPI Request Fifo Pushed When Full. */
+        uint64_t nr_po_e                 : 1;       /**< NPI Request Fifo Popped When Empty. */
+        uint64_t pr_pu_f                 : 1;       /**< PP  Request Fifo Pushed When Full. */
+        uint64_t pr_po_e                 : 1;       /**< PP  Request Fifo Popped When Empty. */
+#else
+        uint64_t pr_po_e                 : 1;
+        uint64_t pr_pu_f                 : 1;
+        uint64_t nr_po_e                 : 1;
+        uint64_t nr_pu_f                 : 1;
+        uint64_t lr_po_e                 : 1;
+        uint64_t lr_pu_f                 : 1;
+        uint64_t pt_po_e                 : 1;
+        uint64_t pt_pu_f                 : 1;
+        uint64_t nt_po_e                 : 1;
+        uint64_t nt_pu_f                 : 1;
+        uint64_t lt_po_e                 : 1;
+        uint64_t lt_pu_f                 : 1;
+        uint64_t dcred_e                 : 1;
+        uint64_t dcred_f                 : 1;
+        uint64_t l2c_s_e                 : 1;
+        uint64_t l2c_a_f                 : 1;
+        uint64_t lt_fi_e                 : 1;
+        uint64_t lt_fi_f                 : 1;
+        uint64_t rg_fi_e                 : 1;
+        uint64_t rg_fi_f                 : 1;
+        uint64_t rq_q2_f                 : 1;
+        uint64_t rq_q2_e                 : 1;
+        uint64_t rq_q3_f                 : 1;
+        uint64_t rq_q3_e                 : 1;
+        uint64_t uod_pe                  : 1;
+        uint64_t uod_pf                  : 1;
+        uint64_t n2u_pf                  : 1;
+        uint64_t n2u_pe                  : 1;
+        uint64_t u2n_d_pe                : 1;
+        uint64_t u2n_d_pf                : 1;
+        uint64_t u2n_c_pf                : 1;
+        uint64_t u2n_c_pe                : 1;
+        uint64_t ltl_f_pe                : 1;
+        uint64_t ltl_f_pf                : 1;
+        uint64_t nd4o_rpe                : 1;
+        uint64_t nd4o_rpf                : 1;
+        uint64_t nd4o_dpe                : 1;
+        uint64_t nd4o_dpf                : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } s;
+    struct cvmx_usbnx_int_sum_s          cn30xx;
+    struct cvmx_usbnx_int_sum_s          cn31xx;
+    struct cvmx_usbnx_int_sum_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t nd4o_dpf                : 1;       /**< NCB DMA Out Data Fifo Push Full. */
+        uint64_t nd4o_dpe                : 1;       /**< NCB DMA Out Data Fifo Pop Empty. */
+        uint64_t nd4o_rpf                : 1;       /**< NCB DMA Out Request Fifo Push Full. */
+        uint64_t nd4o_rpe                : 1;       /**< NCB DMA Out Request Fifo Pop Empty. */
+        uint64_t ltl_f_pf                : 1;       /**< L2C Transfer Length Fifo Push Full. */
+        uint64_t ltl_f_pe                : 1;       /**< L2C Transfer Length Fifo Pop Empty. */
+        uint64_t reserved_26_31          : 6;
+        uint64_t uod_pf                  : 1;       /**< UOD Fifo Push Full. */
+        uint64_t uod_pe                  : 1;       /**< UOD Fifo Pop Empty. */
+        uint64_t rq_q3_e                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
+        uint64_t rq_q3_f                 : 1;       /**< Request Queue-3 Fifo Pushed When Full. */
+        uint64_t rq_q2_e                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
+        uint64_t rq_q2_f                 : 1;       /**< Request Queue-2 Fifo Pushed When Full. */
+        uint64_t rg_fi_f                 : 1;       /**< Register Request Fifo Pushed When Full. */
+        uint64_t rg_fi_e                 : 1;       /**< Register Request Fifo Pushed When Full. */
+        uint64_t lt_fi_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
+        uint64_t lt_fi_e                 : 1;       /**< L2C Request Fifo Pushed When Full. */
+        uint64_t l2c_a_f                 : 1;       /**< L2C Credit Count Added When Full. */
+        uint64_t l2c_s_e                 : 1;       /**< L2C Credit Count Subtracted When Empty. */
+        uint64_t dcred_f                 : 1;       /**< Data CreditFifo Pushed When Full. */
+        uint64_t dcred_e                 : 1;       /**< Data Credit Fifo Pushed When Full. */
+        uint64_t lt_pu_f                 : 1;       /**< L2C Trasaction Fifo Pushed When Full. */
+        uint64_t lt_po_e                 : 1;       /**< L2C Trasaction Fifo Popped When Full. */
+        uint64_t nt_pu_f                 : 1;       /**< NPI Trasaction Fifo Pushed When Full. */
+        uint64_t nt_po_e                 : 1;       /**< NPI Trasaction Fifo Popped When Full. */
+        uint64_t pt_pu_f                 : 1;       /**< PP  Trasaction Fifo Pushed When Full. */
+        uint64_t pt_po_e                 : 1;       /**< PP  Trasaction Fifo Popped When Full. */
+        uint64_t lr_pu_f                 : 1;       /**< L2C Request Fifo Pushed When Full. */
+        uint64_t lr_po_e                 : 1;       /**< L2C Request Fifo Popped When Empty. */
+        uint64_t nr_pu_f                 : 1;       /**< NPI Request Fifo Pushed When Full. */
+        uint64_t nr_po_e                 : 1;       /**< NPI Request Fifo Popped When Empty. */
+        uint64_t pr_pu_f                 : 1;       /**< PP  Request Fifo Pushed When Full. */
+        uint64_t pr_po_e                 : 1;       /**< PP  Request Fifo Popped When Empty. */
+#else
+        uint64_t pr_po_e                 : 1;
+        uint64_t pr_pu_f                 : 1;
+        uint64_t nr_po_e                 : 1;
+        uint64_t nr_pu_f                 : 1;
+        uint64_t lr_po_e                 : 1;
+        uint64_t lr_pu_f                 : 1;
+        uint64_t pt_po_e                 : 1;
+        uint64_t pt_pu_f                 : 1;
+        uint64_t nt_po_e                 : 1;
+        uint64_t nt_pu_f                 : 1;
+        uint64_t lt_po_e                 : 1;
+        uint64_t lt_pu_f                 : 1;
+        uint64_t dcred_e                 : 1;
+        uint64_t dcred_f                 : 1;
+        uint64_t l2c_s_e                 : 1;
+        uint64_t l2c_a_f                 : 1;
+        uint64_t lt_fi_e                 : 1;
+        uint64_t lt_fi_f                 : 1;
+        uint64_t rg_fi_e                 : 1;
+        uint64_t rg_fi_f                 : 1;
+        uint64_t rq_q2_f                 : 1;
+        uint64_t rq_q2_e                 : 1;
+        uint64_t rq_q3_f                 : 1;
+        uint64_t rq_q3_e                 : 1;
+        uint64_t uod_pe                  : 1;
+        uint64_t uod_pf                  : 1;
+        uint64_t reserved_26_31          : 6;
+        uint64_t ltl_f_pe                : 1;
+        uint64_t ltl_f_pf                : 1;
+        uint64_t nd4o_rpe                : 1;
+        uint64_t nd4o_rpf                : 1;
+        uint64_t nd4o_dpe                : 1;
+        uint64_t nd4o_dpf                : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } cn50xx;
+    struct cvmx_usbnx_int_sum_cn50xx     cn52xx;
+    struct cvmx_usbnx_int_sum_cn50xx     cn52xxp1;
+    struct cvmx_usbnx_int_sum_cn50xx     cn56xx;
+    struct cvmx_usbnx_int_sum_cn50xx     cn56xxp1;
+} cvmx_usbnx_int_sum_t;
+
+
+/**
+ * cvmx_usbn#_usbp_ctl_status
+ *
+ * USBN_USBP_CTL_STATUS = USBP Control And Status Register
+ * 
+ * Contains general control and status information for the USBN block.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_usbnx_usbp_ctl_status_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t txrisetune              : 1;       /**< HS Transmitter Rise/Fall Time Adjustment */
+        uint64_t txvreftune              : 4;       /**< HS DC Voltage Level Adjustment */
+        uint64_t txfslstune              : 4;       /**< FS/LS Source Impedence Adjustment */
+        uint64_t txhsxvtune              : 2;       /**< Transmitter High-Speed Crossover Adjustment */
+        uint64_t sqrxtune                : 3;       /**< Squelch Threshold Adjustment */
+        uint64_t compdistune             : 3;       /**< Disconnect Threshold Adjustment */
+        uint64_t otgtune                 : 3;       /**< VBUS Valid Threshold Adjustment */
+        uint64_t otgdisable              : 1;       /**< OTG Block Disable */
+        uint64_t portreset               : 1;       /**< Per_Port Reset */
+        uint64_t drvvbus                 : 1;       /**< Drive VBUS */
+        uint64_t lsbist                  : 1;       /**< Low-Speed BIST Enable. */
+        uint64_t fsbist                  : 1;       /**< Full-Speed BIST Enable. */
+        uint64_t hsbist                  : 1;       /**< High-Speed BIST Enable. */
+        uint64_t bist_done               : 1;       /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+        uint64_t bist_err                : 1;       /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+        uint64_t siddq                   : 1;       /**< Drives the USBP (USB-PHY) SIDDQ input.
+                                                         Normally should be set to zero.
+                                                         When customers have no intent to use USB PHY
+                                                         interface, they should:
+                                                           - still provide 3.3V to USB_VDD33, and
+                                                           - tie USB_REXT to 3.3V supply, and
+                                                           - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
+        uint64_t txpreemphasistune       : 1;       /**< HS Transmitter Pre-Emphasis Enable */
+        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
+        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+        uint64_t tuning                  : 4;       /**< Transmitter Tuning for High-Speed Operation.
+                                                         Tunes the current supply and rise/fall output
+                                                         times for high-speed operation.
+                                                         [20:19] == 11: Current supply increased
+                                                         approximately 9%
+                                                         [20:19] == 10: Current supply increased
+                                                         approximately 4.5%
+                                                         [20:19] == 01: Design default.
+                                                         [20:19] == 00: Current supply decreased
+                                                         approximately 4.5%
+                                                         [22:21] == 11: Rise and fall times are increased.
+                                                         [22:21] == 10: Design default.
+                                                         [22:21] == 01: Rise and fall times are decreased.
+                                                         [22:21] == 00: Rise and fall times are decreased
+                                                         further as compared to the 01 setting. */
+        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+        uint64_t ate_reset               : 1;
+        uint64_t tdata_in                : 8;
+        uint64_t taddr_in                : 4;
+        uint64_t tdata_sel               : 1;
+        uint64_t bist_enb                : 1;
+        uint64_t vtest_enb               : 1;
+        uint64_t loop_enb                : 1;
+        uint64_t tx_bs_en                : 1;
+        uint64_t tx_bs_enh               : 1;
+        uint64_t tuning                  : 4;
+        uint64_t hst_mode                : 1;
+        uint64_t dm_pulld                : 1;
+        uint64_t dp_pulld                : 1;
+        uint64_t tclk                    : 1;
+        uint64_t usbp_bist               : 1;
+        uint64_t usbc_end                : 1;
+        uint64_t dma_bmode               : 1;
+        uint64_t txpreemphasistune       : 1;
+        uint64_t siddq                   : 1;
+        uint64_t tdata_out               : 4;
+        uint64_t bist_err                : 1;
+        uint64_t bist_done               : 1;
+        uint64_t hsbist                  : 1;
+        uint64_t fsbist                  : 1;
+        uint64_t lsbist                  : 1;
+        uint64_t drvvbus                 : 1;
+        uint64_t portreset               : 1;
+        uint64_t otgdisable              : 1;
+        uint64_t otgtune                 : 3;
+        uint64_t compdistune             : 3;
+        uint64_t sqrxtune                : 3;
+        uint64_t txhsxvtune              : 2;
+        uint64_t txfslstune              : 4;
+        uint64_t txvreftune              : 4;
+        uint64_t txrisetune              : 1;
+#endif
+    } s;
+    struct cvmx_usbnx_usbp_ctl_status_cn30xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_38_63          : 26;
+        uint64_t bist_done               : 1;       /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+        uint64_t bist_err                : 1;       /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+        uint64_t reserved_30_31          : 2;
+        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
+        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+        uint64_t tuning                  : 4;       /**< Transmitter Tuning for High-Speed Operation.
+                                                         Tunes the current supply and rise/fall output
+                                                         times for high-speed operation.
+                                                         [20:19] == 11: Current supply increased
+                                                         approximately 9%
+                                                         [20:19] == 10: Current supply increased
+                                                         approximately 4.5%
+                                                         [20:19] == 01: Design default.
+                                                         [20:19] == 00: Current supply decreased
+                                                         approximately 4.5%
+                                                         [22:21] == 11: Rise and fall times are increased.
+                                                         [22:21] == 10: Design default.
+                                                         [22:21] == 01: Rise and fall times are decreased.
+                                                         [22:21] == 00: Rise and fall times are decreased
+                                                         further as compared to the 01 setting. */
+        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+        uint64_t ate_reset               : 1;
+        uint64_t tdata_in                : 8;
+        uint64_t taddr_in                : 4;
+        uint64_t tdata_sel               : 1;
+        uint64_t bist_enb                : 1;
+        uint64_t vtest_enb               : 1;
+        uint64_t loop_enb                : 1;
+        uint64_t tx_bs_en                : 1;
+        uint64_t tx_bs_enh               : 1;
+        uint64_t tuning                  : 4;
+        uint64_t hst_mode                : 1;
+        uint64_t dm_pulld                : 1;
+        uint64_t dp_pulld                : 1;
+        uint64_t tclk                    : 1;
+        uint64_t usbp_bist               : 1;
+        uint64_t usbc_end                : 1;
+        uint64_t dma_bmode               : 1;
+        uint64_t reserved_30_31          : 2;
+        uint64_t tdata_out               : 4;
+        uint64_t bist_err                : 1;
+        uint64_t bist_done               : 1;
+        uint64_t reserved_38_63          : 26;
+#endif
+    } cn30xx;
+    struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
+    struct cvmx_usbnx_usbp_ctl_status_cn50xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t txrisetune              : 1;       /**< HS Transmitter Rise/Fall Time Adjustment */
+        uint64_t txvreftune              : 4;       /**< HS DC Voltage Level Adjustment */
+        uint64_t txfslstune              : 4;       /**< FS/LS Source Impedence Adjustment */
+        uint64_t txhsxvtune              : 2;       /**< Transmitter High-Speed Crossover Adjustment */
+        uint64_t sqrxtune                : 3;       /**< Squelch Threshold Adjustment */
+        uint64_t compdistune             : 3;       /**< Disconnect Threshold Adjustment */
+        uint64_t otgtune                 : 3;       /**< VBUS Valid Threshold Adjustment */
+        uint64_t otgdisable              : 1;       /**< OTG Block Disable */
+        uint64_t portreset               : 1;       /**< Per_Port Reset */
+        uint64_t drvvbus                 : 1;       /**< Drive VBUS */
+        uint64_t lsbist                  : 1;       /**< Low-Speed BIST Enable. */
+        uint64_t fsbist                  : 1;       /**< Full-Speed BIST Enable. */
+        uint64_t hsbist                  : 1;       /**< High-Speed BIST Enable. */
+        uint64_t bist_done               : 1;       /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+        uint64_t bist_err                : 1;       /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+        uint64_t reserved_31_31          : 1;
+        uint64_t txpreemphasistune       : 1;       /**< HS Transmitter Pre-Emphasis Enable */
+        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
+        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+        uint64_t reserved_19_22          : 4;
+        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+        uint64_t ate_reset               : 1;
+        uint64_t tdata_in                : 8;
+        uint64_t taddr_in                : 4;
+        uint64_t tdata_sel               : 1;
+        uint64_t bist_enb                : 1;
+        uint64_t vtest_enb               : 1;
+        uint64_t loop_enb                : 1;
+        uint64_t tx_bs_en                : 1;
+        uint64_t tx_bs_enh               : 1;
+        uint64_t reserved_19_22          : 4;
+        uint64_t hst_mode                : 1;
+        uint64_t dm_pulld                : 1;
+        uint64_t dp_pulld                : 1;
+        uint64_t tclk                    : 1;
+        uint64_t usbp_bist               : 1;
+        uint64_t usbc_end                : 1;
+        uint64_t dma_bmode               : 1;
+        uint64_t txpreemphasistune       : 1;
+        uint64_t reserved_31_31          : 1;
+        uint64_t tdata_out               : 4;
+        uint64_t bist_err                : 1;
+        uint64_t bist_done               : 1;
+        uint64_t hsbist                  : 1;
+        uint64_t fsbist                  : 1;
+        uint64_t lsbist                  : 1;
+        uint64_t drvvbus                 : 1;
+        uint64_t portreset               : 1;
+        uint64_t otgdisable              : 1;
+        uint64_t otgtune                 : 3;
+        uint64_t compdistune             : 3;
+        uint64_t sqrxtune                : 3;
+        uint64_t txhsxvtune              : 2;
+        uint64_t txfslstune              : 4;
+        uint64_t txvreftune              : 4;
+        uint64_t txrisetune              : 1;
+#endif
+    } cn50xx;
+    struct cvmx_usbnx_usbp_ctl_status_cn52xx
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t txrisetune              : 1;       /**< HS Transmitter Rise/Fall Time Adjustment */
+        uint64_t txvreftune              : 4;       /**< HS DC Voltage Level Adjustment */
+        uint64_t txfslstune              : 4;       /**< FS/LS Source Impedence Adjustment */
+        uint64_t txhsxvtune              : 2;       /**< Transmitter High-Speed Crossover Adjustment */
+        uint64_t sqrxtune                : 3;       /**< Squelch Threshold Adjustment */
+        uint64_t compdistune             : 3;       /**< Disconnect Threshold Adjustment */
+        uint64_t otgtune                 : 3;       /**< VBUS Valid Threshold Adjustment */
+        uint64_t otgdisable              : 1;       /**< OTG Block Disable */
+        uint64_t portreset               : 1;       /**< Per_Port Reset */
+        uint64_t drvvbus                 : 1;       /**< Drive VBUS */
+        uint64_t lsbist                  : 1;       /**< Low-Speed BIST Enable. */
+        uint64_t fsbist                  : 1;       /**< Full-Speed BIST Enable. */
+        uint64_t hsbist                  : 1;       /**< High-Speed BIST Enable. */
+        uint64_t bist_done               : 1;       /**< PHY Bist Done.
+                                                         Asserted at the end of the PHY BIST sequence. */
+        uint64_t bist_err                : 1;       /**< PHY Bist Error.
+                                                         Indicates an internal error was detected during
+                                                         the BIST sequence. */
+        uint64_t tdata_out               : 4;       /**< PHY Test Data Out.
+                                                         Presents either internaly generated signals or
+                                                         test register contents, based upon the value of
+                                                         test_data_out_sel. */
+        uint64_t siddq                   : 1;       /**< Drives the USBP (USB-PHY) SIDDQ input.
+                                                         Normally should be set to zero.
+                                                         When customers have no intent to use USB PHY
+                                                         interface, they should:
+                                                           - still provide 3.3V to USB_VDD33, and
+                                                           - tie USB_REXT to 3.3V supply, and
+                                                           - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
+        uint64_t txpreemphasistune       : 1;       /**< HS Transmitter Pre-Emphasis Enable */
+        uint64_t dma_bmode               : 1;       /**< When set to 1 the L2C DMA address will be updated
+                                                         with byte-counts between packets. When set to 0
+                                                         the L2C DMA address is incremented to the next
+                                                         4-byte aligned address after adding byte-count. */
+        uint64_t usbc_end                : 1;       /**< Bigendian input to the USB Core. This should be
+                                                         set to '0' for operation. */
+        uint64_t usbp_bist               : 1;       /**< PHY, This is cleared '0' to run BIST on the USBP. */
+        uint64_t tclk                    : 1;       /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
+        uint64_t dp_pulld                : 1;       /**< PHY DP_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D+ line. '1' pull down-resistance is connected
+                                                         to D+/ '0' pull down resistance is not connected
+                                                         to D+. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t dm_pulld                : 1;       /**< PHY DM_PULLDOWN input to the USB-PHY.
+                                                         This signal enables the pull-down resistance on
+                                                         the D- line. '1' pull down-resistance is connected
+                                                         to D-. '0' pull down resistance is not connected
+                                                         to D-. When an A/B device is acting as a host
+                                                         (downstream-facing port), dp_pulldown and
+                                                         dm_pulldown are enabled. This must not toggle
+                                                         during normal opeartion. */
+        uint64_t hst_mode                : 1;       /**< When '0' the USB is acting as HOST, when '1'
+                                                         USB is acting as device. This field needs to be
+                                                         set while the USB is in reset. */
+        uint64_t reserved_19_22          : 4;
+        uint64_t tx_bs_enh               : 1;       /**< Transmit Bit Stuffing on [15:8].
+                                                         Enables or disables bit stuffing on data[15:8]
+                                                         when bit-stuffing is enabled. */
+        uint64_t tx_bs_en                : 1;       /**< Transmit Bit Stuffing on [7:0].
+                                                         Enables or disables bit stuffing on data[7:0]
+                                                         when bit-stuffing is enabled. */
+        uint64_t loop_enb                : 1;       /**< PHY Loopback Test Enable.
+                                                         '1': During data transmission the receive is
+                                                         enabled.
+                                                         '0': During data transmission the receive is
+                                                         disabled.
+                                                         Must be '0' for normal operation. */
+        uint64_t vtest_enb               : 1;       /**< Analog Test Pin Enable.
+                                                         '1' The PHY's analog_test pin is enabled for the
+                                                         input and output of applicable analog test signals.
+                                                         '0' THe analog_test pin is disabled. */
+        uint64_t bist_enb                : 1;       /**< Built-In Self Test Enable.
+                                                         Used to activate BIST in the PHY. */
+        uint64_t tdata_sel               : 1;       /**< Test Data Out Select.
+                                                         '1' test_data_out[3:0] (PHY) register contents
+                                                         are output. '0' internaly generated signals are
+                                                         output. */
+        uint64_t taddr_in                : 4;       /**< Mode Address for Test Interface.
+                                                         Specifies the register address for writing to or
+                                                         reading from the PHY test interface register. */
+        uint64_t tdata_in                : 8;       /**< Internal Testing Register Input Data and Select
+                                                         This is a test bus. Data is present on [3:0],
+                                                         and its corresponding select (enable) is present
+                                                         on bits [7:4]. */
+        uint64_t ate_reset               : 1;       /**< Reset input from automatic test equipment.
+                                                         This is a test signal. When the USB Core is
+                                                         powered up (not in Susned Mode), an automatic
+                                                         tester can use this to disable phy_clock and
+                                                         free_clk, then re-eanable them with an aligned
+                                                         phase.
+                                                         '1': The phy_clk and free_clk outputs are
+                                                         disabled. "0": The phy_clock and free_clk outputs
+                                                         are available within a specific period after the
+                                                         de-assertion. */
+#else
+        uint64_t ate_reset               : 1;
+        uint64_t tdata_in                : 8;
+        uint64_t taddr_in                : 4;
+        uint64_t tdata_sel               : 1;
+        uint64_t bist_enb                : 1;
+        uint64_t vtest_enb               : 1;
+        uint64_t loop_enb                : 1;
+        uint64_t tx_bs_en                : 1;
+        uint64_t tx_bs_enh               : 1;
+        uint64_t reserved_19_22          : 4;
+        uint64_t hst_mode                : 1;
+        uint64_t dm_pulld                : 1;
+        uint64_t dp_pulld                : 1;
+        uint64_t tclk                    : 1;
+        uint64_t usbp_bist               : 1;
+        uint64_t usbc_end                : 1;
+        uint64_t dma_bmode               : 1;
+        uint64_t txpreemphasistune       : 1;
+        uint64_t siddq                   : 1;
+        uint64_t tdata_out               : 4;
+        uint64_t bist_err                : 1;
+        uint64_t bist_done               : 1;
+        uint64_t hsbist                  : 1;
+        uint64_t fsbist                  : 1;
+        uint64_t lsbist                  : 1;
+        uint64_t drvvbus                 : 1;
+        uint64_t portreset               : 1;
+        uint64_t otgdisable              : 1;
+        uint64_t otgtune                 : 3;
+        uint64_t compdistune             : 3;
+        uint64_t sqrxtune                : 3;
+        uint64_t txhsxvtune              : 2;
+        uint64_t txfslstune              : 4;
+        uint64_t txvreftune              : 4;
+        uint64_t txrisetune              : 1;
+#endif
+    } cn52xx;
+    struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1;
+    struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx;
+    struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1;
+} cvmx_usbnx_usbp_ctl_status_t;
+
+
+/**
+ * cvmx_zip_cmd_bist_result
+ *
+ * Notes:
+ * Access to the internal BiST results
+ * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail).
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_cmd_bist_result_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_31_63          : 33;
+        uint64_t zip_core                : 27;      /**< BiST result of the ZIP_CORE memories */
+        uint64_t zip_ctl                 : 4;       /**< BiST result of the ZIP_CTL  memories */
+#else
+        uint64_t zip_ctl                 : 4;
+        uint64_t zip_core                : 27;
+        uint64_t reserved_31_63          : 33;
+#endif
+    } s;
+    struct cvmx_zip_cmd_bist_result_s    cn31xx;
+    struct cvmx_zip_cmd_bist_result_s    cn38xx;
+    struct cvmx_zip_cmd_bist_result_s    cn38xxp2;
+    struct cvmx_zip_cmd_bist_result_s    cn56xx;
+    struct cvmx_zip_cmd_bist_result_s    cn56xxp1;
+    struct cvmx_zip_cmd_bist_result_s    cn58xx;
+    struct cvmx_zip_cmd_bist_result_s    cn58xxp1;
+} cvmx_zip_cmd_bist_result_t;
+
+
+/**
+ * cvmx_zip_cmd_buf
+ *
+ * Notes:
+ * Sets the command buffer parameters
+ * The size of the command buffer segments is measured in uint64s.  The pool specifies (1 of 8 free
+ * lists to be used when freeing command buffer segments.  The PTR field is overwritten with the next
+ * pointer each time that the command buffer segment is exhausted.
+ * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
+ * this register to effectively reset the command buffer state machine.  New commands will then be
+ * read from the newly specified command buffer pointer.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_cmd_buf_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_58_63          : 6;
+        uint64_t dwb                     : 9;       /**< Number of DontWriteBacks */
+        uint64_t pool                    : 3;       /**< Free list used to free command buffer segments */
+        uint64_t size                    : 13;      /**< Number of uint64s per command buffer segment */
+        uint64_t ptr                     : 33;      /**< Initial command buffer pointer[39:7] (128B-aligned) */
+#else
+        uint64_t ptr                     : 33;
+        uint64_t size                    : 13;
+        uint64_t pool                    : 3;
+        uint64_t dwb                     : 9;
+        uint64_t reserved_58_63          : 6;
+#endif
+    } s;
+    struct cvmx_zip_cmd_buf_s            cn31xx;
+    struct cvmx_zip_cmd_buf_s            cn38xx;
+    struct cvmx_zip_cmd_buf_s            cn38xxp2;
+    struct cvmx_zip_cmd_buf_s            cn56xx;
+    struct cvmx_zip_cmd_buf_s            cn56xxp1;
+    struct cvmx_zip_cmd_buf_s            cn58xx;
+    struct cvmx_zip_cmd_buf_s            cn58xxp1;
+} cvmx_zip_cmd_buf_t;
+
+
+/**
+ * cvmx_zip_cmd_ctl
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_cmd_ctl_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_2_63           : 62;
+        uint64_t forceclk                : 1;       /**< Force zip_ctl__clock_on_b == 1 when set */
+        uint64_t reset                   : 1;       /**< Reset oneshot pulse for zip core */
+#else
+        uint64_t reset                   : 1;
+        uint64_t forceclk                : 1;
+        uint64_t reserved_2_63           : 62;
+#endif
+    } s;
+    struct cvmx_zip_cmd_ctl_s            cn31xx;
+    struct cvmx_zip_cmd_ctl_s            cn38xx;
+    struct cvmx_zip_cmd_ctl_s            cn38xxp2;
+    struct cvmx_zip_cmd_ctl_s            cn56xx;
+    struct cvmx_zip_cmd_ctl_s            cn56xxp1;
+    struct cvmx_zip_cmd_ctl_s            cn58xx;
+    struct cvmx_zip_cmd_ctl_s            cn58xxp1;
+} cvmx_zip_cmd_ctl_t;
+
+
+/**
+ * cvmx_zip_constants
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_constants_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_48_63          : 16;
+        uint64_t depth                   : 16;      /**< Maximum search depth for compression */
+        uint64_t onfsize                 : 12;      /**< Output near full threshhold in bytes */
+        uint64_t ctxsize                 : 12;      /**< Context size in bytes */
+        uint64_t reserved_1_7            : 7;
+        uint64_t disabled                : 1;       /**< 1=zip unit isdisabled, 0=zip unit not disabled */
+#else
+        uint64_t disabled                : 1;
+        uint64_t reserved_1_7            : 7;
+        uint64_t ctxsize                 : 12;
+        uint64_t onfsize                 : 12;
+        uint64_t depth                   : 16;
+        uint64_t reserved_48_63          : 16;
+#endif
+    } s;
+    struct cvmx_zip_constants_s          cn31xx;
+    struct cvmx_zip_constants_s          cn38xx;
+    struct cvmx_zip_constants_s          cn38xxp2;
+    struct cvmx_zip_constants_s          cn56xx;
+    struct cvmx_zip_constants_s          cn56xxp1;
+    struct cvmx_zip_constants_s          cn58xx;
+    struct cvmx_zip_constants_s          cn58xxp1;
+} cvmx_zip_constants_t;
+
+
+/**
+ * cvmx_zip_debug0
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_debug0_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_14_63          : 50;
+        uint64_t asserts                 : 14;      /**< FIFO assertion checks */
+#else
+        uint64_t asserts                 : 14;
+        uint64_t reserved_14_63          : 50;
+#endif
+    } s;
+    struct cvmx_zip_debug0_s             cn31xx;
+    struct cvmx_zip_debug0_s             cn38xx;
+    struct cvmx_zip_debug0_s             cn38xxp2;
+    struct cvmx_zip_debug0_s             cn56xx;
+    struct cvmx_zip_debug0_s             cn56xxp1;
+    struct cvmx_zip_debug0_s             cn58xx;
+    struct cvmx_zip_debug0_s             cn58xxp1;
+} cvmx_zip_debug0_t;
+
+
+/**
+ * cvmx_zip_error
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ *
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_error_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t doorbell                : 1;       /**< A doorbell count has overflowed */
+#else
+        uint64_t doorbell                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_zip_error_s              cn31xx;
+    struct cvmx_zip_error_s              cn38xx;
+    struct cvmx_zip_error_s              cn38xxp2;
+    struct cvmx_zip_error_s              cn56xx;
+    struct cvmx_zip_error_s              cn56xxp1;
+    struct cvmx_zip_error_s              cn58xx;
+    struct cvmx_zip_error_s              cn58xxp1;
+} cvmx_zip_error_t;
+
+
+/**
+ * cvmx_zip_int_mask
+ *
+ * Notes:
+ * Note that this CSR is present only in chip revisions beginning with pass2.
+ * When a mask bit is set, the corresponding interrupt is enabled.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct cvmx_zip_int_mask_s
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t reserved_1_63           : 63;
+        uint64_t doorbell                : 1;       /**< Bit mask corresponding to PKO_REG_ERROR[1] above */
+#else
+        uint64_t doorbell                : 1;
+        uint64_t reserved_1_63           : 63;
+#endif
+    } s;
+    struct cvmx_zip_int_mask_s           cn31xx;
+    struct cvmx_zip_int_mask_s           cn38xx;
+    struct cvmx_zip_int_mask_s           cn38xxp2;
+    struct cvmx_zip_int_mask_s           cn56xx;
+    struct cvmx_zip_int_mask_s           cn56xxp1;
+    struct cvmx_zip_int_mask_s           cn58xx;
+    struct cvmx_zip_int_mask_s           cn58xxp1;
+} cvmx_zip_int_mask_t;
+#endif /* __CVMX_CSR_TYPEDEFS_H__ */
diff --git a/cvmx-csr.h b/cvmx-csr.h
new file mode 100644
index 0000000000000..80a8939fb627a
--- /dev/null
+++ b/cvmx-csr.h
@@ -0,0 +1,222 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Configuration and status register (CSR) address and type definitions for
+ * Octoen.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#ifndef __CVMX_CSR_H__
+#define __CVMX_CSR_H__
+
+#ifndef CVMX_ENABLE_CSR_ADDRESS_CHECKING
+#define CVMX_ENABLE_CSR_ADDRESS_CHECKING 0
+#endif
+
+#include "cvmx-platform.h"
+#include "cvmx-csr-enums.h"
+#include "cvmx-csr-addresses.h"
+#include "cvmx-csr-typedefs.h"
+
+/* Map the HW names to the SDK historical names */
+typedef cvmx_ciu_intx_en1_t             cvmx_ciu_int1_t;
+typedef cvmx_ciu_intx_sum0_t            cvmx_ciu_intx0_t;
+typedef cvmx_ciu_mbox_setx_t            cvmx_ciu_mbox_t;
+typedef cvmx_fpa_fpfx_marks_t           cvmx_fpa_fpf_marks_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que0_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que1_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que2_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que3_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que4_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que5_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que6_page_index_t;
+typedef cvmx_fpa_quex_page_index_t      cvmx_fpa_que7_page_index_t;
+typedef cvmx_ipd_1st_mbuff_skip_t       cvmx_ipd_mbuff_first_skip_t;
+typedef cvmx_ipd_1st_next_ptr_back_t    cvmx_ipd_first_next_ptr_back_t;
+typedef cvmx_ipd_packet_mbuff_size_t    cvmx_ipd_mbuff_size_t;
+typedef cvmx_ipd_qosx_red_marks_t       cvmx_ipd_qos_red_marks_t;
+typedef cvmx_ipd_wqe_fpa_queue_t        cvmx_ipd_wqe_fpa_pool_t;
+typedef cvmx_l2c_pfcx_t                 cvmx_l2c_pfc0_t;
+typedef cvmx_l2c_pfcx_t                 cvmx_l2c_pfc1_t;
+typedef cvmx_l2c_pfcx_t                 cvmx_l2c_pfc2_t;
+typedef cvmx_l2c_pfcx_t                 cvmx_l2c_pfc3_t;
+typedef cvmx_lmcx_bist_ctl_t            cvmx_lmc_bist_ctl_t;
+typedef cvmx_lmcx_bist_result_t         cvmx_lmc_bist_result_t;
+typedef cvmx_lmcx_comp_ctl_t            cvmx_lmc_comp_ctl_t;
+typedef cvmx_lmcx_ctl_t                 cvmx_lmc_ctl_t;
+typedef cvmx_lmcx_ctl1_t                cvmx_lmc_ctl1_t;
+typedef cvmx_lmcx_dclk_cnt_hi_t         cvmx_lmc_dclk_cnt_hi_t;
+typedef cvmx_lmcx_dclk_cnt_lo_t         cvmx_lmc_dclk_cnt_lo_t;
+typedef cvmx_lmcx_dclk_ctl_t            cvmx_lmc_dclk_ctl_t;
+typedef cvmx_lmcx_ddr2_ctl_t            cvmx_lmc_ddr2_ctl_t;
+typedef cvmx_lmcx_delay_cfg_t           cvmx_lmc_delay_cfg_t;
+typedef cvmx_lmcx_dll_ctl_t             cvmx_lmc_dll_ctl_t;
+typedef cvmx_lmcx_dual_memcfg_t         cvmx_lmc_dual_memcfg_t;
+typedef cvmx_lmcx_ecc_synd_t            cvmx_lmc_ecc_synd_t;
+typedef cvmx_lmcx_fadr_t                cvmx_lmc_fadr_t;
+typedef cvmx_lmcx_ifb_cnt_hi_t          cvmx_lmc_ifb_cnt_hi_t;
+typedef cvmx_lmcx_ifb_cnt_lo_t          cvmx_lmc_ifb_cnt_lo_t;
+typedef cvmx_lmcx_mem_cfg0_t            cvmx_lmc_mem_cfg0_t;
+typedef cvmx_lmcx_mem_cfg1_t            cvmx_lmc_mem_cfg1_t;
+typedef cvmx_lmcx_wodt_ctl0_t           cvmx_lmc_odt_ctl_t;
+typedef cvmx_lmcx_ops_cnt_hi_t          cvmx_lmc_ops_cnt_hi_t;
+typedef cvmx_lmcx_ops_cnt_lo_t          cvmx_lmc_ops_cnt_lo_t;
+typedef cvmx_lmcx_pll_bwctl_t           cvmx_lmc_pll_bwctl_t;
+typedef cvmx_lmcx_pll_ctl_t             cvmx_lmc_pll_ctl_t;
+typedef cvmx_lmcx_pll_status_t          cvmx_lmc_pll_status_t;
+typedef cvmx_lmcx_read_level_ctl_t      cvmx_lmc_read_level_ctl_t;
+typedef cvmx_lmcx_read_level_dbg_t      cvmx_lmc_read_level_dbg_t;
+typedef cvmx_lmcx_read_level_rankx_t    cvmx_lmc_read_level_rankx_t;
+typedef cvmx_lmcx_rodt_comp_ctl_t       cvmx_lmc_rodt_comp_ctl_t;
+typedef cvmx_lmcx_rodt_ctl_t            cvmx_lmc_rodt_ctl_t;
+typedef cvmx_lmcx_wodt_ctl0_t           cvmx_lmc_wodt_ctl_t;
+typedef cvmx_lmcx_wodt_ctl0_t           cvmx_lmc_wodt_ctl0_t;
+typedef cvmx_lmcx_wodt_ctl1_t           cvmx_lmc_wodt_ctl1_t;
+typedef cvmx_mio_boot_reg_cfgx_t	cvmx_mio_boot_reg_cfg0_t;
+typedef cvmx_mio_boot_reg_timx_t	cvmx_mio_boot_reg_tim0_t;
+typedef cvmx_mio_twsx_int_t             cvmx_mio_tws_int_t;
+typedef cvmx_mio_twsx_sw_twsi_t         cvmx_mio_tws_sw_twsi_t;
+typedef cvmx_mio_twsx_sw_twsi_ext_t     cvmx_mio_tws_sw_twsi_ext_t;
+typedef cvmx_mio_twsx_twsi_sw_t         cvmx_mio_tws_twsi_sw_t;
+typedef cvmx_npi_base_addr_inputx_t     cvmx_npi_base_addr_input_t;
+typedef cvmx_npi_base_addr_outputx_t    cvmx_npi_base_addr_output_t;
+typedef cvmx_npi_buff_size_outputx_t    cvmx_npi_buff_size_output_t;
+typedef cvmx_npi_dma_highp_counts_t     cvmx_npi_dma_counts_t;
+typedef cvmx_npi_dma_highp_naddr_t      cvmx_npi_dma_naddr_t;
+typedef cvmx_npi_highp_dbell_t          cvmx_npi_dbell_t;
+typedef cvmx_npi_highp_ibuff_saddr_t    cvmx_npi_dma_ibuff_saddr_t;
+typedef cvmx_npi_mem_access_subidx_t    cvmx_npi_mem_access_subid_t;
+typedef cvmx_npi_num_desc_outputx_t     cvmx_npi_num_desc_output_t;
+typedef cvmx_npi_px_dbpair_addr_t       cvmx_npi_dbpair_addr_t;
+typedef cvmx_npi_px_instr_addr_t        cvmx_npi_instr_addr_t;
+typedef cvmx_npi_px_instr_cnts_t        cvmx_npi_instr_cnts_t;
+typedef cvmx_npi_px_pair_cnts_t         cvmx_npi_pair_cnts_t;
+typedef cvmx_npi_size_inputx_t          cvmx_npi_size_input_t;
+typedef cvmx_pci_dbellx_t               cvmx_pci_dbell_t;
+typedef cvmx_pci_dma_cntx_t             cvmx_pci_dma_cnt_t;
+typedef cvmx_pci_dma_int_levx_t         cvmx_pci_dma_int_lev_t;
+typedef cvmx_pci_dma_timex_t            cvmx_pci_dma_time_t;
+typedef cvmx_pci_instr_countx_t         cvmx_pci_instr_count_t;
+typedef cvmx_pci_pkt_creditsx_t         cvmx_pci_pkt_credits_t;
+typedef cvmx_pci_pkts_sent_int_levx_t   cvmx_pci_pkts_sent_int_lev_t;
+typedef cvmx_pci_pkts_sent_timex_t      cvmx_pci_pkts_sent_time_t;
+typedef cvmx_pci_pkts_sentx_t           cvmx_pci_pkts_sent_t;
+typedef cvmx_pip_prt_cfgx_t             cvmx_pip_port_cfg_t;
+typedef cvmx_pip_prt_tagx_t             cvmx_pip_port_tag_cfg_t;
+typedef cvmx_pip_qos_watchx_t           cvmx_pip_port_watcher_cfg_t;
+typedef cvmx_pko_mem_queue_ptrs_t       cvmx_pko_queue_cfg_t;
+typedef cvmx_pko_reg_cmd_buf_t          cvmx_pko_pool_cfg_t;
+typedef cvmx_smix_clk_t                 cvmx_smi_clk_t;
+typedef cvmx_smix_cmd_t                 cvmx_smi_cmd_t;
+typedef cvmx_smix_en_t                  cvmx_smi_en_t;
+typedef cvmx_smix_rd_dat_t              cvmx_smi_rd_dat_t;
+typedef cvmx_smix_wr_dat_t              cvmx_smi_wr_dat_t;
+typedef cvmx_tim_reg_flags_t            cvmx_tim_control_t;
+
+/* The CSRs for bootbus region zero used to be independent of the
+    other 1-7. As of SDK 1.7.0 these were combined. These macros
+    are for backwards compactability */
+#define CVMX_MIO_BOOT_REG_CFG0		CVMX_MIO_BOOT_REG_CFGX(0)
+#define CVMX_MIO_BOOT_REG_TIM0		CVMX_MIO_BOOT_REG_TIMX(0)
+
+/* The CN3XXX and CN58XX chips use to not have a LMC number
+    passed to the address macros. These are here to supply backwards
+    compatability with old code. Code should really use the new addresses
+    with bus arguments for support on other chips */
+#define CVMX_LMC_BIST_CTL               CVMX_LMCX_BIST_CTL(0)
+#define CVMX_LMC_BIST_RESULT            CVMX_LMCX_BIST_RESULT(0)
+#define CVMX_LMC_COMP_CTL               CVMX_LMCX_COMP_CTL(0)
+#define CVMX_LMC_CTL                    CVMX_LMCX_CTL(0)
+#define CVMX_LMC_CTL1                   CVMX_LMCX_CTL1(0)
+#define CVMX_LMC_DCLK_CNT_HI            CVMX_LMCX_DCLK_CNT_HI(0)
+#define CVMX_LMC_DCLK_CNT_LO            CVMX_LMCX_DCLK_CNT_LO(0)
+#define CVMX_LMC_DCLK_CTL               CVMX_LMCX_DCLK_CTL(0)
+#define CVMX_LMC_DDR2_CTL               CVMX_LMCX_DDR2_CTL(0)
+#define CVMX_LMC_DELAY_CFG              CVMX_LMCX_DELAY_CFG(0)
+#define CVMX_LMC_DLL_CTL                CVMX_LMCX_DLL_CTL(0)
+#define CVMX_LMC_DUAL_MEMCFG            CVMX_LMCX_DUAL_MEMCFG(0)
+#define CVMX_LMC_ECC_SYND               CVMX_LMCX_ECC_SYND(0)
+#define CVMX_LMC_FADR                   CVMX_LMCX_FADR(0)
+#define CVMX_LMC_IFB_CNT_HI             CVMX_LMCX_IFB_CNT_HI(0)
+#define CVMX_LMC_IFB_CNT_LO             CVMX_LMCX_IFB_CNT_LO(0)
+#define CVMX_LMC_MEM_CFG0               CVMX_LMCX_MEM_CFG0(0)
+#define CVMX_LMC_MEM_CFG1               CVMX_LMCX_MEM_CFG1(0)
+#define CVMX_LMC_OPS_CNT_HI             CVMX_LMCX_OPS_CNT_HI(0)
+#define CVMX_LMC_OPS_CNT_LO             CVMX_LMCX_OPS_CNT_LO(0)
+#define CVMX_LMC_PLL_BWCTL              CVMX_LMCX_PLL_BWCTL(0)
+#define CVMX_LMC_PLL_CTL                CVMX_LMCX_PLL_CTL(0)
+#define CVMX_LMC_PLL_STATUS             CVMX_LMCX_PLL_STATUS(0)
+#define CVMX_LMC_READ_LEVEL_CTL         CVMX_LMCX_READ_LEVEL_CTL(0)
+#define CVMX_LMC_READ_LEVEL_DBG         CVMX_LMCX_READ_LEVEL_DBG(0)
+#define CVMX_LMC_READ_LEVEL_RANKX       CVMX_LMCX_READ_LEVEL_RANKX(0)
+#define CVMX_LMC_RODT_COMP_CTL          CVMX_LMCX_RODT_COMP_CTL(0)
+#define CVMX_LMC_RODT_CTL               CVMX_LMCX_RODT_CTL(0)
+#define CVMX_LMC_WODT_CTL               CVMX_LMCX_WODT_CTL0(0)
+#define CVMX_LMC_WODT_CTL0              CVMX_LMCX_WODT_CTL0(0)
+#define CVMX_LMC_WODT_CTL1              CVMX_LMCX_WODT_CTL1(0)
+
+/* The CN3XXX and CN58XX chips use to not have a TWSI bus number
+    passed to the address macros. These are here to supply backwards
+    compatability with old code. Code should really use the new addresses
+    with bus arguments for support on other chips */
+#define CVMX_MIO_TWS_INT            CVMX_MIO_TWSX_INT(0)
+#define CVMX_MIO_TWS_SW_TWSI        CVMX_MIO_TWSX_SW_TWSI(0)
+#define CVMX_MIO_TWS_SW_TWSI_EXT    CVMX_MIO_TWSX_SW_TWSI_EXT(0)
+#define CVMX_MIO_TWS_TWSI_SW        CVMX_MIO_TWSX_TWSI_SW(0)
+
+/* The CN3XXX and CN58XX chips use to not have a SMI/MDIO bus number
+    passed to the address macros. These are here to supply backwards
+    compatability with old code. Code should really use the new addresses
+    with bus arguments for support on other chips */
+#define CVMX_SMI_CLK    CVMX_SMIX_CLK(0)
+#define CVMX_SMI_CMD    CVMX_SMIX_CMD(0)
+#define CVMX_SMI_EN     CVMX_SMIX_EN(0)
+#define CVMX_SMI_RD_DAT CVMX_SMIX_RD_DAT(0)
+#define CVMX_SMI_WR_DAT CVMX_SMIX_WR_DAT(0)
+
+#endif /* __CVMX_CSR_H__ */
+
diff --git a/cvmx-cvmmem.h b/cvmx-cvmmem.h
new file mode 100644
index 0000000000000..7d79ee9ea8a84
--- /dev/null
+++ b/cvmx-cvmmem.h
@@ -0,0 +1,73 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interfaces and definitions for processor local memory
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_CVMMEM_H__
+#define __CVMX_CVMMEM_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+
+
+
+
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif // __CVMX_CVMMEM_H__
diff --git a/cvmx-dfa.c b/cvmx-dfa.c
new file mode 100644
index 0000000000000..9658c9eabf99d
--- /dev/null
+++ b/cvmx-dfa.c
@@ -0,0 +1,120 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the hardware DFA engine.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-fau.h"
+#include "cvmx-dfa.h"
+
+
+
+/**
+ * Initialize the DFA hardware before use
+ */
+int cvmx_dfa_initialize(void)
+{
+    cvmx_dfa_difctl_t control;
+    void *initial_base_address;
+    cvmx_dfa_state_t initial_state;
+    if (!octeon_has_feature(OCTEON_FEATURE_DFA))
+    {
+        cvmx_dprintf("ERROR: attempting to initialize DFA when no DFA hardware present\n.");
+        return -1;
+    }
+
+    control.u64 = 0;
+    control.s.dwbcnt = CVMX_FPA_DFA_POOL_SIZE / 128;
+    control.s.pool = CVMX_FPA_DFA_POOL;
+    control.s.size = (CVMX_FPA_DFA_POOL_SIZE - 8) / sizeof(cvmx_dfa_command_t);
+    CVMX_SYNCWS;
+    cvmx_write_csr(CVMX_DFA_DIFCTL, control.u64);
+
+    initial_base_address = cvmx_fpa_alloc(CVMX_FPA_DFA_POOL);
+
+    initial_state.u64 = 0;
+    initial_state.s.base_address_div16 = (CAST64(initial_base_address))/16;
+    cvmx_fau_atomic_write64(CVMX_FAU_DFA_STATE, initial_state.u64);
+
+    CVMX_SYNCWS;
+    cvmx_write_csr(CVMX_DFA_DIFRDPTR, cvmx_ptr_to_phys(initial_base_address));
+
+    return 0;
+}
+
+
+/**
+ * Shutdown and cleanup resources used by the DFA
+ */
+void cvmx_dfa_shutdown(void)
+{
+    void *final_base_address;
+    cvmx_dfa_state_t final_state;
+
+    CVMX_SYNCWS;
+
+    final_state.u64 = cvmx_fau_fetch_and_add64(CVMX_FAU_DFA_STATE, 0);
+
+    // make sure the carry is clear
+    final_base_address = CASTPTR(void, (final_state.s2.base_address_div32 * 32ull));
+
+    if (final_base_address)
+    {
+        cvmx_fpa_free(final_base_address, CVMX_FPA_DFA_POOL, 0);
+    }
+
+    CVMX_SYNCWS;
+    final_state.u64 = 0;
+    cvmx_fau_atomic_write64(CVMX_FAU_DFA_STATE, final_state.u64);
+}
+
+#endif
diff --git a/cvmx-dfa.h b/cvmx-dfa.h
new file mode 100644
index 0000000000000..2b943c37563f5
--- /dev/null
+++ b/cvmx-dfa.h
@@ -0,0 +1,800 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware DFA engine.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_DFA_H__
+#define __CVMX_DFA_H__
+#include "cvmx-llm.h"
+#include "cvmx-wqe.h"
+#include "cvmx-fpa.h"
+
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+#include "cvmx-config.h"
+#endif
+
+#define ENABLE_DEPRECATED   /* Set to enable the old 18/36 bit names */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/* Maximum nodes available in a small encoding */
+#define CVMX_DFA_NODESM_MAX_NODES       ((OCTEON_IS_MODEL(OCTEON_CN31XX)) ? 0x8000 : 0x20000)
+#define CVMX_DFA_NODESM_SIZE            512     /* Size of each node for small encoding */
+#define CVMX_DFA_NODELG_SIZE            1024    /* Size of each node for large encoding */
+#define CVMX_DFA_NODESM_LAST_TERMINAL  (CVMX_DFA_NODESM_MAX_NODES-1)
+
+#ifdef ENABLE_DEPRECATED
+/* These defines are for compatability with old code. They are deprecated */
+#define CVMX_DFA_NODE18_SIZE            CVMX_DFA_NODESM_SIZE
+#define CVMX_DFA_NODE36_SIZE            CVMX_DFA_NODELG_SIZE
+#define CVMX_DFA_NODE18_MAX_NODES       CVMX_DFA_NODESM_MAX_NODES
+#define CVMX_DFA_NODE18_LAST_TERMINAL   CVMX_DFA_NODESM_LAST_TERMINAL
+#endif
+
+/**
+ * Which type of memory encoding is this graph using. Make sure you setup
+ * the LLM to match.
+ */
+typedef enum
+{
+    CVMX_DFA_GRAPH_TYPE_SM              = 0,
+    CVMX_DFA_GRAPH_TYPE_LG              = 1,
+#ifdef ENABLE_DEPRECATED
+    CVMX_DFA_GRAPH_TYPE_18b             = 0,    /* Deprecated */
+    CVMX_DFA_GRAPH_TYPE_36b             = 1     /* Deprecated */
+#endif
+} cvmx_dfa_graph_type_t;
+
+/**
+ * The possible node types.
+ */
+typedef enum
+{
+    CVMX_DFA_NODE_TYPE_NORMAL           = 0,    /**< Node is a branch */
+    CVMX_DFA_NODE_TYPE_MARKED           = 1,    /**< Node is marked special */
+    CVMX_DFA_NODE_TYPE_TERMINAL         = 2     /**< Node is a terminal leaf */
+} cvmx_dfa_node_type_t;
+
+/**
+ * The possible reasons the DFA stopped processing.
+ */
+typedef enum
+{
+    CVMX_DFA_STOP_REASON_DATA_GONE      = 0,    /**< DFA ran out of data */
+    CVMX_DFA_STOP_REASON_PARITY_ERROR   = 1,    /**< DFA encountered a memory error */
+    CVMX_DFA_STOP_REASON_FULL           = 2,    /**< DFA is full */
+    CVMX_DFA_STOP_REASON_TERMINAL       = 3     /**< DFA hit a terminal */
+} cvmx_dfa_stop_reason_t;
+
+/**
+ * This format describes the DFA pointers in small mode
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t                mbz         :32;/**< Must be zero */
+        uint64_t                p1          : 1;/**< Set if next_node1 is odd parity */
+        uint64_t                next_node1  :15;/**< Next node if an odd character match */
+        uint64_t                p0          : 1;/**< Set if next_node0 is odd parity */
+        uint64_t                next_node0  :15;/**< Next node if an even character match */
+    } w32;
+    struct
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                p1          : 1;/**< Set if next_node1 is odd parity */
+        uint64_t                next_node1  :17;/**< Next node if an odd character match */
+        uint64_t                p0          : 1;/**< Set if next_node0 is odd parity */
+        uint64_t                next_node0  :17;/**< Next node if an even character match */
+    } w36;
+    struct /**< @ this structure only applies starting in CN58XX and if DFA_CFG[NRPL_ENA] == 1 and IWORD0[NREPLEN] == 1.  */
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                p1          : 1;/**< Set if next_node1 is odd parity */
+        uint64_t                per_node_repl1  : 1;/**< enable for extra replicaiton for next node (CN58XX) */
+        uint64_t                next_node_repl1 : 2;/**< extra replicaiton for next node (CN58XX) (if per_node_repl1 is set) */
+        uint64_t                next_node1  :14;/**< Next node if an odd character match - IWORD3[Msize], if per_node_repl1==1. */
+        uint64_t                p0          : 1;/**< Set if next_node0 is odd parity */
+        uint64_t                per_node_repl0  : 1;/**< enable for extra replicaiton for next node (CN58XX) */
+        uint64_t                next_node_repl0 : 2;/**< extra replicaiton for next node (CN58XX) (if per_node_repl0 is set) */
+        uint64_t                next_node0  :14;/**< Next node if an odd character match - IWORD3[Msize], if per_node_repl0==1. */
+    } w36nrepl_en; /**< use when next_node_repl[01] is 1. */
+    struct /**< this structure only applies starting in CN58XX and if DFA_CFG[NRPL_ENA] == 1 and IWORD0[NREPLEN] == 1.  */
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                p1          : 1;/**< Set if next_node1 is odd parity */
+        uint64_t                per_node_repl1  : 1;/**< enable for extra replicaiton for next node (CN58XX) */
+        uint64_t                next_node1  :16;/**< Next node if an odd character match, if per_node_repl1==0. */
+        uint64_t                p0          : 1;/**< Set if next_node0 is odd parity */
+        uint64_t                per_node_repl0  : 1;/**< enable for extra replicaiton for next node (CN58XX) */
+        uint64_t                next_node0  :16;/**< Next node if an odd character match, if per_node_repl0==0. */
+    } w36nrepl_dis; /**< use when next_node_repl[01] is 0. */
+#if defined(ENABLE_DEPRECATED) && !OCTEON_IS_COMMON_BINARY()
+#if CVMX_COMPILED_FOR(OCTEON_CN31XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :32;/**< Must be zero */
+        uint64_t                p1          : 1;/**< Set if next_node1 is odd parity */
+        uint64_t                next_node1  :15;/**< Next node if an odd character match */
+        uint64_t                p0          : 1;/**< Set if next_node0 is odd parity */
+        uint64_t                next_node0  :15;/**< Next node if an even character match */
+    };
+#elif CVMX_COMPILED_FOR(OCTEON_CN38XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                p1          : 1;/**< Set if next_node1 is odd parity */
+        uint64_t                next_node1  :17;/**< Next node if an odd character match */
+        uint64_t                p0          : 1;/**< Set if next_node0 is odd parity */
+        uint64_t                next_node0  :17;/**< Next node if an even character match */
+    };
+#else
+    /* Other chips don't support the deprecated unnamed unions */
+#endif
+#endif
+} cvmx_dfa_node_next_sm_t;
+
+/**
+ * This format describes the DFA pointers in large mode
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t                mbz         :32;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        cvmx_dfa_node_type_t    type        : 2;/**< Node type */
+        uint64_t                mbz2        : 3;/**< Must be zero */
+        uint64_t                next_node   :20;/**< Next node */
+    } w32;
+    struct
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        cvmx_dfa_node_type_t    type        : 2;/**< Node type */
+        uint64_t                extra_bits     : 5;/**< bits copied to report (PASS3/CN58XX), Must be zero previously */
+        uint64_t                next_node_repl : 2;/**< extra replicaiton for next node (PASS3/CN58XX), Must be zero previously */
+        uint64_t                next_node   :20;/**< Next node ID,  Note, combine with next_node_repl to use as start_node
+                                                     for continuation, as in cvmx_dfa_node_next_lgb_t. */
+    } w36;
+#if defined(ENABLE_DEPRECATED) && !OCTEON_IS_COMMON_BINARY()
+#if CVMX_COMPILED_FOR(OCTEON_CN31XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :32;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        cvmx_dfa_node_type_t    type        : 2;/**< Node type */
+        uint64_t                mbz2        : 3;/**< Must be zero */
+        uint64_t                next_node   :20;/**< Next node */
+    };
+#elif CVMX_COMPILED_FOR(OCTEON_CN38XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        cvmx_dfa_node_type_t    type        : 2;/**< Node type */
+        uint64_t                extra_bits     : 5;/**< bits copied to report (PASS3/CN58XX), Must be zero previously */
+        uint64_t                next_node_repl : 2;/**< extra replicaiton for next node (PASS3/CN58XX), Must be zero previously */
+        uint64_t                next_node   :20;/**< Next node ID,  Note, combine with next_node_repl to use as start_node
+                                                     for continuation, as in cvmx_dfa_node_next_lgb_t. */
+    };
+#else
+    /* Other chips don't support the deprecated unnamed unions */
+#endif
+#endif
+} cvmx_dfa_node_next_lg_t;
+
+/**
+ * This format describes the DFA pointers in large mode, another way
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t                mbz         :32;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        uint64_t  		type_terminal : 1;/**< Node type */
+        uint64_t	        type_marked   : 1;/**< Node type */
+        uint64_t                mbz2        : 3;/**< Must be zero */
+        uint64_t                next_node   :20;/**< Next node */
+    } w32;
+    struct
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        uint64_t                type_terminal : 1;/**< Node type */
+        uint64_t                type_marked   : 1;/**< Node type */
+        uint64_t                extra_bits     : 5;/**< bits copied to report (PASS3/CN58XX), Must be zero previously */
+        uint64_t                next_node_id_and_repl   :22;/**< Next node ID (and repl for PASS3/CN58XX or repl=0 if not),
+                                                                 use this as start node for continuation. */
+    } w36;
+#if defined(ENABLE_DEPRECATED) && !OCTEON_IS_COMMON_BINARY()
+#if CVMX_COMPILED_FOR(OCTEON_CN31XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :32;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        uint64_t  		type_terminal : 1;/**< Node type */
+        uint64_t	        type_marked   : 1;/**< Node type */
+        uint64_t                mbz2        : 3;/**< Must be zero */
+        uint64_t                next_node   :20;/**< Next node */
+    };
+#elif CVMX_COMPILED_FOR(OCTEON_CN38XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :28;/**< Must be zero */
+        uint64_t                ecc         : 7;/**< ECC checksum on the rest of the bits */
+        uint64_t                type_terminal : 1;/**< Node type */
+        uint64_t                type_marked   : 1;/**< Node type */
+        uint64_t                extra_bits     : 5;/**< bits copied to report (PASS3/CN58XX), Must be zero previously */
+        uint64_t                next_node_id_and_repl   :22;/**< Next node ID (and repl for PASS3/CN58XX or repl=0 if not),
+                                                                 use this as start node for continuation. */
+    };
+#else
+    /* Other chips don't support the deprecated unnamed unions */
+#endif
+#endif
+} cvmx_dfa_node_next_lgb_t;
+
+/**
+ * This format describes the DFA pointers in large mode
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t                mbz         :27;/**< Must be zero */
+        uint64_t                x0          : 1;/**< XOR of the rest of the bits */
+        uint64_t                reserved    : 4;/**< Must be zero */
+        uint64_t                data        :32;/**< LLM Data */
+    } w32;
+    struct
+    {
+        uint64_t                mbz         :27;/**< Must be zero */
+        uint64_t                x0          : 1;/**< XOR of the rest of the bits */
+        uint64_t                data        :36;/**< LLM Data */
+    } w36;
+#if defined(ENABLE_DEPRECATED) && !OCTEON_IS_COMMON_BINARY()
+#if CVMX_COMPILED_FOR(OCTEON_CN31XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :27;/**< Must be zero */
+        uint64_t                x0          : 1;/**< XOR of the rest of the bits */
+        uint64_t                reserved    : 4;/**< Must be zero */
+        uint64_t                data        :32;/**< LLM Data */
+    };
+#elif CVMX_COMPILED_FOR(OCTEON_CN38XX)
+    struct /**< @deprecated unnamed reference to members */
+    {
+        uint64_t                mbz         :27;/**< Must be zero */
+        uint64_t                x0          : 1;/**< XOR of the rest of the bits */
+        uint64_t                data        :36;/**< LLM Data */
+    };
+#else
+    /* Other chips don't support the deprecated unnamed unions */
+#endif
+#endif
+} cvmx_dfa_node_next_read_t;
+
+/**
+ * This structure defines the data format in the low-latency memory
+ */
+typedef union
+{
+    uint64_t u64;
+    cvmx_dfa_node_next_sm_t     sm;     /**< This format describes the DFA pointers in small mode */
+    cvmx_dfa_node_next_lg_t     lg;     /**< This format describes the DFA pointers in large mode */
+    cvmx_dfa_node_next_lgb_t    lgb;    /**< This format describes the DFA pointers in large mode, another way */
+    cvmx_dfa_node_next_read_t   read;   /**< This format describes the DFA pointers in large mode */
+#ifdef ENABLE_DEPRECATED
+    cvmx_dfa_node_next_sm_t     s18;    /**< Deprecated */
+    cvmx_dfa_node_next_lg_t     s36;    /**< Deprecated */
+    cvmx_dfa_node_next_lgb_t    s36b;   /**< Deprecated */
+#endif
+} cvmx_dfa_node_next_t;
+
+/**
+ * These structures define a DFA instruction
+ */
+typedef union
+{
+    uint64_t u64[4];
+    uint32_t u32;
+    struct
+    {
+        // WORD 0
+        uint64_t gxor                   : 8;   /**< Graph XOR value (PASS3/CN58XX), Must be zero for other chips
+                                                     or if DFA_CFG[GXOR_ENA] == 0.  */
+        uint64_t nxoren                 : 1;   /**< Node XOR enable (PASS3/CN58XX), Must be zero for other chips
+                                                     or if DFA_CFG[NXOR_ENA] == 0.  */
+        uint64_t nreplen                : 1;   /**< Node Replication mode enable (PASS3/CN58XX), Must be zero for other chips
+                                                     or if DFA_CFG[NRPL_ENA] == 0 or IWORD0[Ty] == 0.  */
+#if 0
+        uint64_t snrepl                 : 2;   /**< Start_Node Replication (PASS3/CN58XX), Must be zero for other chips
+                                                     or if DFA_CFG[NRPL_ENA] == 0 or IWORD0[Ty] == 0 or IWORD0[NREPLEN] == 0.  */
+        uint64_t start_node_id          : 20;   /**< Node to start the walk from */
+#else
+        uint64_t start_node             : 22;   /**< Node to start the walk from, includes ID and snrepl, see notes above. */
+#endif
+
+        uint64_t unused02               :  2;   /**< Must be zero */
+        cvmx_llm_replication_t replication : 2; /**< Type of memory replication to use */
+        uint64_t unused03               :  3;   /**< Must be zero */
+        cvmx_dfa_graph_type_t type      :  1;   /**< Type of graph */
+        uint64_t unused04               :  4;   /**< Must be zero */
+        uint64_t base                   : 20;   /**< All tables start on 1KB boundary */
+
+        // WORD 1
+        uint64_t input_length           : 16;   /**< In bytes, # pointers in gather case */
+        uint64_t use_gather             :  1;   /**< Set to use gather */
+        uint64_t no_L2_alloc            :  1;   /**< Set to disable loading of the L2 cache by the DFA */
+        uint64_t full_block_write       :  1;   /**< If set, HW can write entire cache blocks @ result_ptr */
+        uint64_t little_endian          :  1;   /**< Affects only packet data, not instruction, gather list, or result */
+        uint64_t unused1                :  8;   /**< Must be zero */
+        uint64_t data_ptr               : 36;   /**< Either directly points to data or the gather list. If gather list,
+                                                    data_ptr<2:0> must be zero (i.e. 8B aligned) */
+        // WORD 2
+        uint64_t max_results            : 16;   /**< in 64-bit quantities, mbz for store */
+        uint64_t unused2                : 12;   /**< Must be zero */
+        uint64_t result_ptr             : 36;   /**< must be 128 byte aligned */
+
+        // WORD 3
+        uint64_t tsize                  :  8;   /**< tsize*256 is the number of terminal nodes for GRAPH_TYPE_SM */
+        uint64_t msize                  : 16;   /**< msize is the number of marked nodes for GRAPH_TYPE_SM */
+        uint64_t unused3                :  4;   /**< Must be zero */
+        uint64_t wq_ptr                 : 36;   /**< 0 for no work queue entry creation */
+    } s;
+} cvmx_dfa_command_t;
+
+/**
+ * Format of the first result word written by the hardware.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        cvmx_dfa_stop_reason_t  reas        : 2;/**< Reason the DFA stopped */
+        uint64_t                mbz         :44;/**< Zero */
+        uint64_t                last_marked : 1;/**< Set if the last entry written is marked */
+        uint64_t                done        : 1;/**< Set to 1 when the DFA completes */
+        uint64_t                num_entries :16;/**< Number of result words written */
+    } s;
+} cvmx_dfa_result0_t;
+
+/**
+ * Format of the second result word and subsequent result words written by the hardware.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t byte_offset    : 16;   /**< Number of bytes consumed */
+        uint64_t extra_bits_high:  4;   /**< If PASS3 or CN58XX and DFA_CFG[NRPL_ENA] == 1 and IWORD0[Ty] == 1,
+                                             then set to <27:24> of the last next-node pointer. Else set to 0x0.  */
+        uint64_t prev_node      : 20;   /**< Index of the previous node */
+        uint64_t extra_bits_low :  2;   /**< If PASS3 or CN58XX and DFA_CFG[NRPL_ENA] == 1 and IWORD0[Ty] == 1,
+                                             then set to <23:22> of the last next-node pointer. Else set to 0x0.  */
+        uint64_t next_node_repl :  2;   /**< If PASS3 or CN58XX and DFA_CFG[NRPL_ENA] == 1 and IWORD0[Ty] == 1, then set
+                                             to next_node_repl (<21:20>) of the last next-node pointer. Else set to 0x0.  */
+        uint64_t current_node   : 20;   /**< Index of the current node */
+    } s;
+    struct
+    {
+        uint64_t byte_offset    : 16;   /**< Number of bytes consumed */
+        uint64_t extra_bits_high:  4;   /**< If PASS3 or CN58XX and DFA_CFG[NRPL_ENA] == 1 and IWORD0[Ty] == 1,
+                                             then set to <27:24> of the last next-node pointer. Else set to 0x0.  */
+        uint64_t prev_node      : 20;   /**< Index of the previous node */
+        uint64_t extra_bits_low :  2;   /**< If PASS3 or CN58XX and DFA_CFG[NRPL_ENA] == 1 and IWORD0[Ty] == 1,
+                                             then set to <23:22> of the last next-node pointer. Else set to 0x0.  */
+        uint64_t curr_id_and_repl:22;   /**< Use ths as start_node for continuation. */
+    } s2;
+} cvmx_dfa_result1_t;
+
+/**
+ * Abstract DFA graph
+ */
+typedef struct
+{
+    cvmx_llm_replication_t      replication;        /**< Level of memory replication to use. Must match the LLM setup */
+    cvmx_dfa_graph_type_t       type;               /**< Type of graph */
+    uint64_t                    base_address;       /**< LLM start address of the graph */
+    union {
+        struct {
+            uint64_t            gxor         : 8;   /**< Graph XOR value (PASS3/CN58XX), Must be zero for other chips
+                                                          or if DFA_CFG[GXOR_ENA] == 0.  */
+            uint64_t            nxoren       : 1;   /**< Node XOR enable (PASS3/CN58XX), Must be zero for other chips
+                                                          or if DFA_CFG[NXOR_ENA] == 0.  */
+            uint64_t            nreplen      : 1;   /**< Node Replication mode enable (PASS3/CN58XX), Must be zero for other chips
+                                                          or if DFA_CFG[NRPL_ENA] == 0 or IWORD0[Ty] == 0.  */
+            uint64_t            snrepl       : 2;   /**< Start_Node Replication (PASS3/CN58XX), Must be zero for other chips
+                                                          or if DFA_CFG[NRPL_ENA] == 0 or IWORD0[Ty] == 0 or IWORD0[NREPLEN] == 0.*/
+            uint64_t            start_node_id : 20; /**< Start node index for the root of the graph */
+        };
+        uint32_t                start_node;         /**< Start node index for the root of the graph, incl. snrepl (PASS3/CN58XX)
+                                                           NOTE: for backwards compatibility this name includes the the
+                                                                 gxor, nxoren, nreplen, and snrepl fields which will all be
+                                                                 zero in applicaitons existing before the introduction of these
+                                                                 fields, so that existing applicaiton do not need to change. */
+    };
+    int                         num_terminal_nodes; /**< Number of terminal nodes in the graph. Only needed for small graphs. */
+    int                         num_marked_nodes;   /**< Number of marked nodes in the graph. Only needed for small graphs. */
+} cvmx_dfa_graph_t;
+
+/**
+ * DFA internal global state -- stored in 8 bytes of FAU
+ */
+typedef union
+{
+    uint64_t u64;
+    struct {
+#define CVMX_DFA_STATE_TICKET_BIT_POS 16
+#if __BYTE_ORDER == __BIG_ENDIAN
+	// NOTE:  must clear LSB of base_address_div16 due to ticket overflow
+	uint32_t		base_address_div16;  /**< Current DFA instruction queue chunck base address/16 (clear LSB). */
+	uint8_t			ticket_loops;	     /**< bits [15:8] of total number of tickets requested. */
+	uint8_t			ticket;		     /**< bits [7:0] of total number of tickets requested (current ticket held). */
+	// NOTE: index and now_serving are written together
+	uint8_t			now_serving;	     /**< current ticket being served (or ready to be served). */
+	uint8_t			index;		     /**< index into current chunk: (base_address_div16*16)[index] = next entry. */
+#else	// NOTE: little endian mode probably won't work
+	uint8_t			index;
+	uint8_t			now_serving;
+	uint8_t			ticket;
+	uint8_t			ticket_loops;
+	uint32_t		base_address_div16;
+#endif
+    } s;
+    struct {	// a bitfield version of the same thing to extract base address while clearing carry.
+#if __BYTE_ORDER == __BIG_ENDIAN
+	uint64_t		base_address_div32	: 31;	/**< Current DFA instruction queue chunck base address/32. */
+	uint64_t		carry			: 1;	/**< Carry out from total_tickets. */
+	uint64_t		total_tickets		: 16;	/**< Total tickets. */
+	uint64_t		now_serving		: 8 ;	/**< current ticket being served (or ready to be served). */
+	uint64_t		index			: 8 ;   /**< index into current chunk. */
+#else	// NOTE: little endian mode probably won't work
+	uint64_t		index			: 8 ;
+	uint64_t		now_serving		: 8 ;
+	uint64_t		total_tickets		: 16;
+	uint64_t		carry			: 1;
+	uint64_t		base_address_div32	: 31;
+#endif
+    } s2;
+} cvmx_dfa_state_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Write a small node edge to LLM.
+ *
+ * @param graph  Graph to modify
+ * @param source_node
+ *               Source node for this edge
+ * @param match_index
+ *               Index into the node edge table. This is the match character/2.
+ * @param destination_node0
+ *               Destination if the character matches (match_index*2).
+ * @param destination_node1
+ *               Destination if the character matches (match_index*2+1).
+ */
+static inline void cvmx_dfa_write_edge_sm(const cvmx_dfa_graph_t *graph,
+                                         uint64_t source_node, uint64_t match_index,
+                                         uint64_t destination_node0, uint64_t destination_node1)
+{
+    cvmx_llm_address_t address;
+    cvmx_dfa_node_next_t    next_ptr;
+
+    address.u64 = graph->base_address + source_node * CVMX_DFA_NODESM_SIZE + match_index * 4;
+
+    next_ptr.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        next_ptr.sm.w32.next_node0 = destination_node0;
+        next_ptr.sm.w32.p0 = cvmx_llm_parity(destination_node0);
+
+        next_ptr.sm.w32.next_node1 = destination_node1;
+        next_ptr.sm.w32.p1 = cvmx_llm_parity(destination_node1);
+    }
+    else
+    {
+        next_ptr.sm.w36.next_node0 = destination_node0;
+        next_ptr.sm.w36.p0 = cvmx_llm_parity(destination_node0);
+
+        next_ptr.sm.w36.next_node1 = destination_node1;
+        next_ptr.sm.w36.p1 = cvmx_llm_parity(destination_node1);
+    }
+
+    cvmx_llm_write36(address, next_ptr.u64, 0);
+}
+#ifdef ENABLE_DEPRECATED
+#define cvmx_dfa_write_edge18 cvmx_dfa_write_edge_sm
+#endif
+
+
+/**
+ * Write a large node edge to LLM.
+ *
+ * @param graph  Graph to modify
+ * @param source_node
+ *               Source node for this edge
+ * @param match  Character to match before taking this edge.
+ * @param destination_node
+ *               Destination node of the edge.
+ * @param destination_type
+ *               Node type at the end of this edge.
+ */
+static inline void cvmx_dfa_write_node_lg(const cvmx_dfa_graph_t *graph,
+                                         uint64_t source_node, unsigned char match,
+                                         uint64_t destination_node, cvmx_dfa_node_type_t destination_type)
+{
+    cvmx_llm_address_t      address;
+    cvmx_dfa_node_next_t    next_ptr;
+
+    address.u64 = graph->base_address + source_node * CVMX_DFA_NODELG_SIZE + (uint64_t)match * 4;
+
+    next_ptr.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        next_ptr.lg.w32.type = destination_type;
+        next_ptr.lg.w32.next_node = destination_node;
+        next_ptr.lg.w32.ecc = cvmx_llm_ecc(next_ptr.u64);
+    }
+    else
+    {
+        next_ptr.lg.w36.type = destination_type;
+        next_ptr.lg.w36.next_node = destination_node;
+        next_ptr.lg.w36.ecc = cvmx_llm_ecc(next_ptr.u64);
+    }
+
+    cvmx_llm_write36(address, next_ptr.u64, 0);
+}
+#ifdef ENABLE_DEPRECATED
+#define cvmx_dfa_write_node36 cvmx_dfa_write_node_lg
+#endif
+
+/**
+ * Ring the DFA doorbell telling it that new commands are
+ * available.
+ *
+ * @param num_commands
+ *               Number of new commands
+ */
+static inline void cvmx_dfa_write_doorbell(uint64_t num_commands)
+{
+    CVMX_SYNCWS;
+    cvmx_write_csr(CVMX_DFA_DBELL, num_commands);
+}
+
+/**
+ * @INTERNAL
+ * Write a new command to the DFA. Calls to this function
+ * are internally synchronized across all processors, and
+ * the doorbell is rung during this function.
+ *
+ * @param command Command to write
+ */
+
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+static inline void __cvmx_dfa_write_command(cvmx_dfa_command_t *command)
+{
+    cvmx_dfa_state_t cvmx_dfa_state;
+    uint64_t my_ticket;	// needs to wrap to 8 bits
+    uint64_t index;
+    cvmx_dfa_command_t *head;
+
+    CVMX_PREFETCH0(command);
+    // take a ticket.
+    cvmx_dfa_state.u64 = cvmx_fau_fetch_and_add64(CVMX_FAU_DFA_STATE, 1ull<<CVMX_DFA_STATE_TICKET_BIT_POS);
+    my_ticket = cvmx_dfa_state.s.ticket;
+
+    // see if it is our turn
+    while (my_ticket != cvmx_dfa_state.s.now_serving) {
+	int delta = my_ticket - cvmx_dfa_state.s.now_serving;
+	if (delta < 0) delta += 256;
+	cvmx_wait(10*delta);	// reduce polling load on system
+	cvmx_dfa_state.u64 = cvmx_fau_fetch_and_add64(CVMX_FAU_DFA_STATE, 0);		// poll for my_ticket==now_serving
+    }
+
+    // compute index and instruction queue head pointer
+    index = cvmx_dfa_state.s.index;
+
+    // NOTE: the DFA only supports 36-bit addressing
+    head = &((CASTPTR(cvmx_dfa_command_t, (cvmx_dfa_state.s2.base_address_div32 * 32ull))[index]));
+    head = (cvmx_dfa_command_t*)cvmx_phys_to_ptr(CAST64(head));	// NOTE: since we are not storing bit 63 of address, we must set it now
+
+    // copy the command to the instruction queue
+    *head++ = *command;
+
+    // check if a new chunk is needed
+    if (cvmx_unlikely((++index >= ((CVMX_FPA_DFA_POOL_SIZE-8)/sizeof(cvmx_dfa_command_t))))) {
+        uint64_t *new_base = (uint64_t*)cvmx_fpa_alloc(CVMX_FPA_DFA_POOL);	// could make this async
+        if (new_base) {
+	    // put the link into the instruction queue's "Next Chunk Buffer Ptr"
+            *(uint64_t *)head = cvmx_ptr_to_phys(new_base);
+	    // update our state (note 32-bit write to not disturb other fields)
+            cvmx_fau_atomic_write32((cvmx_fau_reg_32_t)(CVMX_FAU_DFA_STATE + (CAST64(&cvmx_dfa_state.s.base_address_div16)-CAST64(&cvmx_dfa_state))),
+		    (CAST64(new_base))/16);
+        }
+        else {
+            cvmx_dprintf("__cvmx_dfa_write_command: Out of memory. Expect crashes.\n");
+        }
+	index=0;
+    }
+
+    cvmx_dfa_write_doorbell(1);
+
+    // update index and now_serving in the DFA state FAU location (NOTE: this write16 updates to 8-bit values.)
+    // NOTE: my_ticket+1 carry out is lost due to write16 and index has already been wrapped to fit in uint8.
+    cvmx_fau_atomic_write16((cvmx_fau_reg_16_t)(CVMX_FAU_DFA_STATE+(CAST64(&cvmx_dfa_state.s.now_serving) - CAST64(&cvmx_dfa_state))),
+	    ((my_ticket+1)<<8) | index);
+}
+
+
+/**
+ * Submit work to the DFA units for processing
+ *
+ * @param graph   Graph to process
+ * @param start_node
+ *                The node to start (or continue) walking from
+ *                includes. start_node_id and snrepl (PASS3/CN58XX), but gxor,
+ *                nxoren, and nreplen are taken from the graph structure
+ * @param input   The input to match against
+ * @param input_length
+ *                The length of the input in bytes
+ * @param use_gather
+ *		  The input and input_length are of a gather list
+ * @param is_little_endian
+ *                Set to 1 if the input is in little endian format and must
+ *                be swapped before compare.
+ * @param result  Location the DFA should put the results in. This must be
+ *                an area sized in multiples of a cache line.
+ * @param max_results
+ *                The maximum number of 64-bit result1 words after result0.
+ *                That is, "size of the result area in 64-bit words" - 1.
+ *                max_results must be at least 1.
+ * @param work    Work queue entry to submit when DFA completes. Can be NULL.
+ */
+static inline void cvmx_dfa_submit(const cvmx_dfa_graph_t *graph, int start_node,
+                                  void *input, int input_length, int use_gather, int is_little_endian,
+                                  cvmx_dfa_result0_t *result, int max_results, cvmx_wqe_t *work)
+{
+    cvmx_dfa_command_t command;
+
+    /* Make sure the result's first 64bit word is zero so we can tell when the
+        DFA is done. */
+    result->u64 = 0;
+
+    // WORD 0
+    command.u64[0] = 0;
+    command.s.gxor          = graph->gxor;      // (PASS3/CN58XX)
+    command.s.nxoren        = graph->nxoren;    // (PASS3/CN58XX)
+    command.s.nreplen       = graph->nreplen;   // (PASS3/CN58XX)
+    command.s.start_node    = start_node;       // includes snrepl (PASS3/CN58XX)
+    command.s.replication   = graph->replication;
+    command.s.type          = graph->type;
+    command.s.base          = graph->base_address>>10;
+
+    // WORD 1
+    command.u64[1] = 0;
+    command.s.input_length  = input_length;
+    command.s.use_gather   = use_gather;
+    command.s.no_L2_alloc   = 0;
+    command.s.full_block_write = 1;
+    command.s.little_endian = is_little_endian;
+    command.s.data_ptr      = cvmx_ptr_to_phys(input);
+
+    // WORD 2
+    command.u64[2] = 0;
+    command.s.max_results   = max_results;
+    command.s.result_ptr    = cvmx_ptr_to_phys(result);
+
+    // WORD 3
+    command.u64[3] = 0;
+    if (graph->type == CVMX_DFA_GRAPH_TYPE_SM)
+    {
+        command.s.tsize     = (graph->num_terminal_nodes + 255) / 256;
+        command.s.msize     = graph->num_marked_nodes;
+    }
+    command.s.wq_ptr        = cvmx_ptr_to_phys(work);
+
+    __cvmx_dfa_write_command(&command);	// NOTE: this does synchronization and rings doorbell
+}
+#endif
+
+/**
+ * DFA gather list element
+ */
+typedef struct {
+    uint64_t length         : 16;   /**< length of piece of data at addr */
+    uint64_t reserved       : 12;   /**< reserved, set to 0 */
+    uint64_t addr           : 36;   /**< pointer to piece of data */
+} cvmx_dfa_gather_entry_t;
+
+
+/**
+ * Check if a DFA has completed processing
+ *
+ * @param result_ptr Result area the DFA is using
+ * @return Non zero if the DFA is done
+ */
+static inline uint64_t cvmx_dfa_is_done(cvmx_dfa_result0_t *result_ptr)
+{
+    /* DFA sets the first result 64bit word to non zero when it's done */
+    return ((volatile cvmx_dfa_result0_t *)result_ptr)->s.done;
+}
+
+
+#ifdef CVMX_ENABLE_DFA_FUNCTIONS
+/**
+ * Initialize the DFA hardware before use
+ * Returns 0 on success, -1 on failure
+ */
+int cvmx_dfa_initialize(void);
+
+
+/**
+ * Shutdown and cleanup resources used by the DFA
+ */
+void cvmx_dfa_shutdown(void);
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_DFA_H__ */
diff --git a/cvmx-dma-engine.c b/cvmx-dma-engine.c
new file mode 100644
index 0000000000000..ad793ea9209a9
--- /dev/null
+++ b/cvmx-dma-engine.c
@@ -0,0 +1,464 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the PCI / PCIe DMA engines. These are only avialable
+ * on chips with PCI / PCIe.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-cmd-queue.h"
+#include "cvmx-dma-engine.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+/**
+ * Return the number of DMA engimes supported by this chip
+ *
+ * @return Number of DMA engines
+ */
+int cvmx_dma_engine_get_num(void)
+{
+    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+            return 4;
+        else
+            return 5;
+    }
+    else
+        return 2;
+}
+
+/**
+ * Initialize the DMA engines for use
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_initialize(void)
+{
+    cvmx_npei_dmax_ibuff_saddr_t dmax_ibuff_saddr;
+    int engine;
+
+    for (engine=0; engine < cvmx_dma_engine_get_num(); engine++)
+    {
+        cvmx_cmd_queue_result_t result;
+        result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_DMA(engine),
+                                           0, CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                           CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
+        if (result != CVMX_CMD_QUEUE_SUCCESS)
+            return -1;
+        dmax_ibuff_saddr.u64 = 0;
+        dmax_ibuff_saddr.s.saddr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_DMA(engine))) >> 7;
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+            cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), dmax_ibuff_saddr.u64);
+        else
+        {
+            if (engine)
+                cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, dmax_ibuff_saddr.u64);
+            else
+                cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, dmax_ibuff_saddr.u64);
+        }
+    }
+
+    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        cvmx_npei_dma_control_t dma_control;
+        dma_control.u64 = 0;
+        if (cvmx_dma_engine_get_num() >= 5)
+            dma_control.s.dma4_enb = 1;
+        dma_control.s.dma3_enb = 1;
+        dma_control.s.dma2_enb = 1;
+        dma_control.s.dma1_enb = 1;
+        dma_control.s.dma0_enb = 1;
+        dma_control.s.o_mode = 1; /* Pull NS and RO from this register, not the pointers */
+        //dma_control.s.dwb_denb = 1;
+        //dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
+        dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
+        dma_control.s.csize = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
+        cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64);
+        /* As a workaround for errata PCIE-811 we only allow a single
+            outstanding DMA read over PCIe at a time. This limits performance,
+            but works in all cases. If you need higher performance, remove
+            this code and implement the more complicated workaround documented
+            in the errata. This only affects CN56XX pass 2.0 chips */
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_0))
+        {
+            cvmx_npei_dma_pcie_req_num_t pcie_req_num;
+            pcie_req_num.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM);
+            pcie_req_num.s.dma_cnt = 1;
+            cvmx_write_csr(CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM, pcie_req_num.u64);
+        }
+    }
+    else
+    {
+        cvmx_npi_dma_control_t dma_control;
+        dma_control.u64 = 0;
+        //dma_control.s.dwb_denb = 1;
+        //dma_control.s.dwb_ichk = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
+        dma_control.s.o_add1 = 1;
+        dma_control.s.fpa_que = CVMX_FPA_OUTPUT_BUFFER_POOL;
+        dma_control.s.hp_enb = 1;
+        dma_control.s.lp_enb = 1;
+        dma_control.s.csize = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
+        cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64);
+    }
+
+    return 0;
+}
+
+
+/**
+ * Shutdown all DMA engines. The engeines must be idle when this
+ * function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_shutdown(void)
+{
+    int engine;
+
+    for (engine=0; engine < cvmx_dma_engine_get_num(); engine++)
+    {
+        if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_DMA(engine)))
+        {
+            cvmx_dprintf("ERROR: cvmx_dma_engine_shutdown: Engine not idle.\n");
+            return -1;
+        }
+    }
+
+    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        cvmx_npei_dma_control_t dma_control;
+        dma_control.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DMA_CONTROL);
+        if (cvmx_dma_engine_get_num() >= 5)
+            dma_control.s.dma4_enb = 0;
+        dma_control.s.dma3_enb = 0;
+        dma_control.s.dma2_enb = 0;
+        dma_control.s.dma1_enb = 0;
+        dma_control.s.dma0_enb = 0;
+        cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64);
+        /* Make sure the disable completes */
+        cvmx_read_csr(CVMX_PEXP_NPEI_DMA_CONTROL);
+    }
+    else
+    {
+        cvmx_npi_dma_control_t dma_control;
+        dma_control.u64 = cvmx_read_csr(CVMX_NPI_DMA_CONTROL);
+        dma_control.s.hp_enb = 0;
+        dma_control.s.lp_enb = 0;
+        cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64);
+        /* Make sure the disable completes */
+        cvmx_read_csr(CVMX_NPI_DMA_CONTROL);
+    }
+
+    for (engine=0; engine < cvmx_dma_engine_get_num(); engine++)
+    {
+        cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_DMA(engine));
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+            cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), 0);
+        else
+        {
+            if (engine)
+                cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, 0);
+            else
+                cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, 0);
+        }
+    }
+
+    return 0;
+}
+
+
+/**
+ * Submit a series of DMA comamnd to the DMA engines.
+ *
+ * @param engine  Engine to submit to (0-4)
+ * @param header  Command header
+ * @param num_buffers
+ *                The number of data pointers
+ * @param buffers Comamnd data pointers
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_buffers, cvmx_dma_engine_buffer_t buffers[])
+{
+    cvmx_cmd_queue_result_t result;
+    int cmd_count = 1;
+    uint64_t cmds[num_buffers + 1];
+
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+    {
+        /* Check for Errata PCIe-604 */
+        if ((header.s.nfst > 11) || (header.s.nlst > 11) || (header.s.nfst + header.s.nlst > 15))
+        {
+            cvmx_dprintf("DMA engine submit too large\n");
+            return -1;
+        }
+    }
+
+    cmds[0] = header.u64;
+    while (num_buffers--)
+    {
+        cmds[cmd_count++] = buffers->u64;
+        buffers++;
+    }
+
+    /* Due to errata PCIE-13315, it is necessary to have the queue lock while we
+        ring the doorbell for the DMA engines. This prevents doorbells from
+        possibly arriving out of order with respect to the command queue
+        entries */
+    __cvmx_cmd_queue_lock(CVMX_CMD_QUEUE_DMA(engine), __cvmx_cmd_queue_get_state(CVMX_CMD_QUEUE_DMA(engine)));
+    result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_DMA(engine), 0, cmd_count, cmds);
+    /* This SYNCWS is needed since the command queue didn't do locking, which
+        normally implies the SYNCWS. This one makes sure the command queue
+        updates make it to L2 before we ring the doorbell */
+    CVMX_SYNCWS;
+    /* A syncw isn't needed here since the command queue did one as part of the queue unlock */
+    if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
+    {
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        {
+            /* DMA doorbells are 32bit writes in little endian space. This means we need to xor the address with 4 */
+            cvmx_write64_uint32(CVMX_PEXP_NPEI_DMAX_DBELL(engine)^4, cmd_count);
+        }
+        else
+        {
+            if (engine)
+                cvmx_write_csr(CVMX_NPI_HIGHP_DBELL, cmd_count);
+            else
+                cvmx_write_csr(CVMX_NPI_LOWP_DBELL, cmd_count);
+        }
+    }
+    /* Here is the unlock for the above errata workaround */
+    __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_get_state(CVMX_CMD_QUEUE_DMA(engine)));
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Function used by cvmx_dma_engine_transfer() to build the
+ * internal address list.
+ *
+ * @param buffers Location to store the list
+ * @param address Address to build list for
+ * @param size    Length of the memory pointed to by address
+ *
+ * @return Number of internal pointer chunks created
+ */
+static inline int __cvmx_dma_engine_build_internal_pointers(cvmx_dma_engine_buffer_t *buffers, uint64_t address, int size)
+{
+    int segments = 0;
+    while (size)
+    {
+        /* Each internal chunk can contain a maximum of 8191 bytes */
+        int chunk = size;
+        if (chunk > 8191)
+            chunk = 8191;
+        buffers[segments].u64 = 0;
+        buffers[segments].internal.size = chunk;
+        buffers[segments].internal.addr = address;
+        address += chunk;
+        size -= chunk;
+        segments++;
+    }
+    return segments;
+}
+
+
+/**
+ * @INTERNAL
+ * Function used by cvmx_dma_engine_transfer() to build the PCI / PCIe address
+ * list.
+ * @param buffers Location to store the list
+ * @param address Address to build list for
+ * @param size    Length of the memory pointed to by address
+ *
+ * @return Number of PCI / PCIe address chunks created. The number of words used
+ *         will be segments + (segments-1)/4 + 1.
+ */
+static inline int __cvmx_dma_engine_build_external_pointers(cvmx_dma_engine_buffer_t *buffers, uint64_t address, int size)
+{
+    const int MAX_SIZE = 65535;
+    int segments = 0;
+    while (size)
+    {
+        /* Each block of 4 PCI / PCIe pointers uses one dword for lengths followed by
+            up to 4 addresses. This then repeats if more data is needed */
+        buffers[0].u64 = 0;
+        if (size <= MAX_SIZE)
+        {
+            /* Only one more segment needed */
+            buffers[0].pcie_length.len0 = size;
+            buffers[1].u64 = address;
+            segments++;
+            break;
+        }
+        else if (size <= MAX_SIZE * 2)
+        {
+            /* Two more segments needed */
+            buffers[0].pcie_length.len0 = MAX_SIZE;
+            buffers[0].pcie_length.len1 = size - MAX_SIZE;
+            buffers[1].u64 = address;
+            address += MAX_SIZE;
+            buffers[2].u64 = address;
+            segments+=2;
+            break;
+        }
+        else if (size <= MAX_SIZE * 3)
+        {
+            /* Three more segments needed */
+            buffers[0].pcie_length.len0 = MAX_SIZE;
+            buffers[0].pcie_length.len1 = MAX_SIZE;
+            buffers[0].pcie_length.len2 = size - MAX_SIZE * 2;
+            buffers[1].u64 = address;
+            address += MAX_SIZE;
+            buffers[2].u64 = address;
+            address += MAX_SIZE;
+            buffers[3].u64 = address;
+            segments+=3;
+            break;
+        }
+        else if (size <= MAX_SIZE * 4)
+        {
+            /* Four more segments needed */
+            buffers[0].pcie_length.len0 = MAX_SIZE;
+            buffers[0].pcie_length.len1 = MAX_SIZE;
+            buffers[0].pcie_length.len2 = MAX_SIZE;
+            buffers[0].pcie_length.len3 = size - MAX_SIZE * 3;
+            buffers[1].u64 = address;
+            address += MAX_SIZE;
+            buffers[2].u64 = address;
+            address += MAX_SIZE;
+            buffers[3].u64 = address;
+            address += MAX_SIZE;
+            buffers[4].u64 = address;
+            segments+=4;
+            break;
+        }
+        else
+        {
+            /* Five or more segments are needed */
+            buffers[0].pcie_length.len0 = MAX_SIZE;
+            buffers[0].pcie_length.len1 = MAX_SIZE;
+            buffers[0].pcie_length.len2 = MAX_SIZE;
+            buffers[0].pcie_length.len3 = MAX_SIZE;
+            buffers[1].u64 = address;
+            address += MAX_SIZE;
+            buffers[2].u64 = address;
+            address += MAX_SIZE;
+            buffers[3].u64 = address;
+            address += MAX_SIZE;
+            buffers[4].u64 = address;
+            address += MAX_SIZE;
+            size -= MAX_SIZE*4;
+            buffers += 5;
+            segments+=4;
+        }
+    }
+    return segments;
+}
+
+
+/**
+ * Build the first and last pointers based on a DMA engine header
+ * and submit them to the engine. The purpose of this function is
+ * to simplify the building of DMA engine commands by automatically
+ * converting a simple address and size into the apropriate internal
+ * or PCI / PCIe address list. This function does not support gather lists,
+ * so you will need to build your own lists in that case.
+ *
+ * @param engine Engine to submit to (0-4)
+ * @param header DMA Command header. Note that the nfst and nlst fields do not
+ *               need to be filled in. All other fields must be set properly.
+ * @param first_address
+ *               Address to use for the first pointers. In the case of INTERNAL,
+ *               INBOUND, and OUTBOUND this is an Octeon memory address. In the
+ *               case of EXTERNAL, this is the source PCI / PCIe address.
+ * @param last_address
+ *               Address to use for the last pointers. In the case of EXTERNAL,
+ *               INBOUND, and OUTBOUND this is a PCI / PCIe address. In the
+ *               case of INTERNAL, this is the Octeon memory destination address.
+ * @param size   Size of the transfer to perform.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header,
+                             uint64_t first_address, uint64_t last_address,
+                             int size)
+{
+    cvmx_dma_engine_buffer_t buffers[32];
+    int words = 0;
+
+    switch (header.s.type)
+    {
+        case CVMX_DMA_ENGINE_TRANSFER_INTERNAL:
+            header.s.nfst = __cvmx_dma_engine_build_internal_pointers(buffers, first_address, size);
+            words += header.s.nfst;
+            header.s.nlst = __cvmx_dma_engine_build_internal_pointers(buffers + words, last_address, size);
+            words += header.s.nlst;
+            break;
+        case CVMX_DMA_ENGINE_TRANSFER_INBOUND:
+        case CVMX_DMA_ENGINE_TRANSFER_OUTBOUND:
+            header.s.nfst = __cvmx_dma_engine_build_internal_pointers(buffers, first_address, size);
+            words += header.s.nfst;
+            header.s.nlst = __cvmx_dma_engine_build_external_pointers(buffers + words, last_address, size);
+            words +=  header.s.nlst + ((header.s.nlst-1) >> 2) + 1;
+            break;
+        case CVMX_DMA_ENGINE_TRANSFER_EXTERNAL:
+            header.s.nfst = __cvmx_dma_engine_build_external_pointers(buffers, first_address, size);
+            words +=  header.s.nfst + ((header.s.nfst-1) >> 2) + 1;
+            header.s.nlst = __cvmx_dma_engine_build_external_pointers(buffers + words, last_address, size);
+            words +=  header.s.nlst + ((header.s.nlst-1) >> 2) + 1;
+            break;
+    }
+    return cvmx_dma_engine_submit(engine, header, words, buffers);
+}
+
+#endif
diff --git a/cvmx-dma-engine.h b/cvmx-dma-engine.h
new file mode 100644
index 0000000000000..d17c7909e7921
--- /dev/null
+++ b/cvmx-dma-engine.h
@@ -0,0 +1,332 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the PCI / PCIe DMA engines. These are only avialable
+ * on chips with PCI / PCIe.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_DMA_ENGINES_H__
+#define __CVMX_DMA_ENGINES_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    CVMX_DMA_ENGINE_TRANSFER_OUTBOUND = 0,  /**< OUTBOUND (read from L2/DRAM, write into PCI / PCIe memory space) */
+    CVMX_DMA_ENGINE_TRANSFER_INBOUND = 1,   /**< INBOUND (read from PCI / PCIe memory space, write into L2/DRAM) */
+    CVMX_DMA_ENGINE_TRANSFER_INTERNAL = 2,  /**< INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM). Only available on chips with PCIe */
+    CVMX_DMA_ENGINE_TRANSFER_EXTERNAL = 3,  /**< EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). Only available on chips with PCIe */
+} cvmx_dma_engine_transfer_t;
+
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t    reserved_60_63 :   4;   /**< Must be zero */
+        uint64_t    fport           :  2;   /**< First port. FPort indicates the physical PCIe port used for the
+                                                PCIe memory space pointers in the FIRST POINTERS block in the
+                                                EXTERNAL-ONLY case. Must be zero in the OUTBOUND, INBOUND and
+                                                INTERNAL-ONLY cases. Must be zero on chips with PCI */
+        uint64_t    lport           :  2;   /**< Last port. LPort indicates the physical PCIe port used for the
+                                                PCIe memory space pointers in the LAST POINTERS block in the
+                                                OUTBOUND, INBOUND, and EXTERNAL-ONLY cases. Must be zero in the
+                                                INTERNAL-ONLY case. Must be zero on chips with PCI */
+        cvmx_dma_engine_transfer_t type :  2; /**< Type ­ A given PCI DMA transfer is either OUTBOUND (read from L2/DRAM,
+                                                write into PCI / PCIe memory space), INBOUND (read from PCI / PCIe memory space, write
+                                                into L2/DRAM), INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM), or
+                                                EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). */
+        uint64_t    wqp             :  1;   /**< Work-queue pointer. When WQP = 1, PTR (if non-zero) is a pointer to a
+                                                work-queue entry that is submitted by the hardware after completing the DMA;
+                                                when WQP = 0, PTR (if non-zero) is a pointer to a byte in local memory that
+                                                is written to 0 by the hardware after completing the DMA. */
+        uint64_t    c               :  1;   /**< C ­ Counter. 1 = use counter 1, 0 = use counter 0.
+                                                The C bit selects between the two counters (NPEI_DMA_CNTS[DMA0,DMA1])
+                                                that can optionally be updated after an OUTBOUND or EXTERNAL-ONLY
+                                                transfer, and also selects between the two forced-interrupt bits
+                                                (NPEI_INT_SUMn[DMA0_FI, DMA1_FI]) that can optionally be set after an
+                                                OUTBOUND or EXTERNAL-ONLY transfer. C must be zero for INBOUND or
+                                                INTERNAL-ONLY transfers. */
+        uint64_t    ca              :  1;   /**< CA ­ Counter add.
+                                                When CA = 1, the hardware updates the selected counter after it completes the
+                                                PCI DMA OUTBOUND or EXTERNAL-ONLY Instruction.
+                                                    - If C = 0, PCIE_DMA_CNT0 is updated
+                                                    - If C = 1, PCIE_DMA_CNT1 is updated.
+                                                Note that this update may indirectly cause
+                                                NPEI_INT_SUM[DCNT0,DCNT1,DTIME0,DTIME1] to become set (depending
+                                                on the NPEI_DMA*_INT_LEVEL settings), so may cause interrupts to occur on a
+                                                remote PCI host.
+                                                    - If NPEI_DMA_CONTROL[O_ADD1] = 1, the counter is updated by 1.
+                                                    - If NPEI_DMA_CONTROL[O_ADD1] = 0, the counter is updated by the total
+                                                    bytes in the transfer.
+                                                When CA = 0, the hardware does not update any counters.
+                                                For an INBOUND or INTERNAL-ONLY PCI DMA transfer, CA must never be
+                                                set, and the hardware never adds to the counters. */
+        uint64_t    fi              :  1;   /**< FI ­ Force interrupt.
+                                                When FI is set for an OUTBOUND or EXTERNAL-ONLY transfer, the hardware
+                                                sets a forced interrupt bit after it completes the PCI DMA Instruction. If C = 0,
+                                                NPEI_INT_SUMn[DMA0_FI] is set, else NPEI_INT_SUMn[DMA1_FI] is set. For
+                                                an INBOUND or INTERNAL-ONLY PCI DMA operation, FI must never be set,
+                                                and the hardware never generates interrupts. */
+        uint64_t    ii              :  1;   /**< II­ Ignore the I bit (i.e. the I bit of the PCI DMA instruction local pointer).
+                                                For OUTBOUND transfers when II = 1, ignore the I bit and the FL bit in the
+                                                DMA HDR alone determines whether the hardware frees any/all of the local
+                                                buffers in the FIRST POINTERS area:
+                                                    - when FL = 1, the hardware frees the local buffer when II=1.
+                                                    - when FL = 0, the hardware does not free the local buffer when II=1.
+                                                For OUTBOUND transfers when II = 0, the I bit in the local pointer selects
+                                                whether local buffers are freed on a pointer-by-pointer basis:
+                                                    - when (FL  I) is true, the hardware frees the local buffer when II=0.
+                                                For INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY PCI DMA transfers,
+                                                II must never be set, and local buffers are never freed. */
+        uint64_t    fl              :  1;   /**< FL ­ Free local buffer.
+                                                When FL = 1, for an OUTBOUND operation, it indicates that the local buffers in
+                                                the FIRST BUFFERS area should be freed.
+                                                If II = 1, the FL bit alone indicates whether the local buffer should be freed:
+                                                    - when FL = 1, the hardware frees the local buffer when II=1.
+                                                    - when FL = 0, the hardware does not free the local buffer when II=1.
+                                                If II = 0, the I bit in the local pointer (refer to Section 9.5.2) determines whether
+                                                the local buffer is freed:
+                                                    - when (FL  I) is true, the hardware frees the local buffer when II=0.
+                                                For an INBOUND, INTERNAL-ONLY, or EXTERNAL-ONLY PCI DMA transfer,
+                                                FL must never be set, and local buffers are never freed. */
+        uint64_t    nlst            :  4;   /**< NLST ­ Number Last pointers.
+                                                The number of pointers in the LAST POINTERS area.
+                                                In the INBOUND, OUTBOUND, and EXTERNAL-ONLY cases, the LAST
+                                                POINTERS area contains PCI components, and the number of 64-bit words
+                                                required in the LAST POINTERS area is:
+                                                    - HDR.NLST + ((HDR.NLST + 3)/4) where the division removes the fraction.
+                                                In the INTERNAL-ONLY case, the LAST POINTERS area contains local
+                                                pointers, and the number of 64-bit words required in the LAST POINTERS area is:
+                                                    - HDR.NLST
+                                                Note that the sum of the number of 64-bit words in the LAST POINTERS and
+                                                FIRST POINTERS area must never exceed 31. */
+        uint64_t    nfst            :  4;   /**< NFST ­ Number First pointers.
+                                                The number of pointers in the FIRST POINTERS area.
+                                                In the INBOUND, OUTBOUND, and INTERNAL-ONLY cases, the FIRST
+                                                POINTERS area contains local pointers, and the number of 64-bit words required
+                                                in the FIRST POINTERS area is:
+                                                    - HDR.NFST
+                                                In the EXTERNAL-ONLY case, the FIRST POINTERS area contains PCI
+                                                components, and the number of 64-bit words required in the FIRST POINTERS
+                                                area is:
+                                                    - HDR.NFST + ((HDR.NFST + 3)/4) where the division removes the fraction. */
+        uint64_t    addr            : 40;   /**< PTR ­ Pointer, either a work-queue-entry pointer (when WQP = 1) or a local
+                                                memory pointer (WQP = 0).
+                                                When WQP = 1 and PTR  0x0, the hardware inserts the work-queue entry
+                                                indicated by PTR into a POW input queue after the PCI DMA operation is
+                                                complete. (Section 5.4 describes the work queue entry requirements in this
+                                                case.) When WQP = 1, PTR<2:0> must be 0x0.
+                                                When WQP = 0 and PTR  0x0, the hardware writes the single byte in local
+                                                memory indicated by PTR to 0x0 after the PCI DMA operation is complete.
+                                                NPEI_DMA_CONTROL[B0_LEND] selects the endian-ness of PTR in this
+                                                case.
+                                                When PTR = 0x0, the hardware performs no operation after the PCI DMA
+                                                operation is complete. */
+    } s;
+} cvmx_dma_engine_header_t;
+
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t    i               :  1;   /**< I ­ Invert free.
+                                                This bit gives the software the ability to free buffers independently for an
+                                                OUTBOUND PCI DMA transfer. I is not used by the hardware when II is set. I
+                                                must not be set, and buffers are never freed, for INBOUND, INTERNAL-ONLY,
+                                                and EXTERNAL-ONLY PCI DMA transfers. */
+        uint64_t    back            :  4;   /**< Back ­ Backup amount.
+                                                Allows the start of a buffer that is to be freed during an OUTBOUND transfer to
+                                                be different from the ptr value. Back specifies the amount to subtract from the
+                                                pointer to reach the start when freeing a buffer.
+                                                The address that is the start of the buffer being freed is:
+                                                    - Buffer start address = ((ptr >> 7) - Back) << 7.
+                                                Back is only used by the hardware when the buffer corresponding to ptr is freed.
+                                                Back must be 0x0, and buffers are never freed, for INBOUND, INTERNAL-ONLY,
+                                                and EXTERNAL-ONLY PCI DMA transfers. */
+        uint64_t    pool            :  3;   /**< Pool ­ Free pool.
+                                                Specifies which pool (of the eight hardware-managed FPA free pools) receives the
+                                                buffer associated with ptr when freed during an OUTBOUND transfer.
+                                                Pool is only used when the buffer corresponding to ptr is freed. Pool must be 0x0,
+                                                and buffers are never freed, for INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY
+                                                PCI DMA transfers. */
+        uint64_t    f               :  1;   /**< F ­ Full-block writes are allowed.
+                                                When set, the hardware is permitted to write all the bytes in the cache blocks
+                                                covered by ptr, ptr + Size - 1. This can improve memory system performance
+                                                when the write misses in the L2 cache.
+                                                F can only be set for local pointers that can be written to:
+                                                    - The local pointers in the FIRST POINTERS area that are write pointers for
+                                                    INBOUND transfers.
+                                                    - The local pointers in the LAST POINTERS area that are always write
+                                                    pointers (when present for INTERNAL-ONLY transfers).
+                                                F must not be set for local pointers that are not written to:
+                                                    - The local pointers in the FIRST POINTERS area for OUTBOUND and
+                                                    INTERNAL-ONLY transfers. */
+        uint64_t    a               :  1;   /**< A ­ Allocate L2.
+                                                This is a hint to the hardware that the cache blocks should be allocated in the L2
+                                                cache (if they were not already). */
+        uint64_t    l               :  1;   /**< L ­ Little-endian.
+                                                When L is set, the data at ptr is in little-endian format rather than big-endian. */
+        uint64_t    size            : 13;   /**< Size ­ Size in bytes of the contiguous space specified by ptr. A Size value of 0 is
+                                                illegal. Note that the sum of the sizes in the FIRST POINTERS area must always
+                                                exactly equal the sum of the sizes/lengths in the LAST POINTERS area:
+                                                    - In the OUTBOUND and INBOUND cases, the HDR.NFST size fields in the
+                                                    local pointers in the FIRST POINTERS area must exactly equal the lengths
+                                                    of the HDR.NLST fragments in the PCI components in the LAST POINTERS
+                                                    area.
+                                                    - In the INTERNAL-ONLY case, the HDR.NFST size fields in the local
+                                                    pointers in the FIRST POINTERS area must equal the HDR.NLST size
+                                                    fields in the local pointers in the LAST POINTERS area. */
+        uint64_t    reserved_36_39  :  4;   /**< Must be zero */
+        uint64_t    addr            : 36;   /**< L2/DRAM byte pointer. Points to where the packet data starts.
+                                                Ptr can be any byte alignment. Note that ptr is interpreted as a big-endian byte
+                                                pointer when L is clear, a little-endian byte pointer when L is set. */
+    } internal;
+    struct
+    {
+        uint64_t    len0            : 16;   /**< Length of PCI / PCIe memory for address 0 */
+        uint64_t    len1            : 16;   /**< Length of PCI / PCIe memory for address 1 */
+        uint64_t    len2            : 16;   /**< Length of PCI / PCIe memory for address 2 */
+        uint64_t    len3            : 16;   /**< Length of PCI / PCIe memory for address 3 */
+    } pcie_length;
+} cvmx_dma_engine_buffer_t;
+
+/**
+ * Initialize the DMA engines for use
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_initialize(void);
+
+/**
+ * Shutdown all DMA engines. The engeines must be idle when this
+ * function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_shutdown(void);
+
+/**
+ * Return the number of DMA engimes supported by this chip
+ *
+ * @return Number of DMA engines
+ */
+int cvmx_dma_engine_get_num(void);
+
+/**
+ * Submit a series of DMA comamnd to the DMA engines.
+ *
+ * @param engine  Engine to submit to (0-4)
+ * @param header  Command header
+ * @param num_buffers
+ *                The number of data pointers
+ * @param buffers Comamnd data pointers
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_buffers, cvmx_dma_engine_buffer_t buffers[]);
+
+/**
+ * Build the first and last pointers based on a DMA engine header
+ * and submit them to the engine. The purpose of this function is
+ * to simplify the building of DMA engine commands by automatically
+ * converting a simple address and size into the apropriate internal
+ * or PCI / PCIe address list. This function does not support gather lists,
+ * so you will need to build your own lists in that case.
+ *
+ * @param engine Engine to submit to (0-4)
+ * @param header DMA Command header. Note that the nfst and nlst fields do not
+ *               need to be filled in. All other fields must be set properly.
+ * @param first_address
+ *               Address to use for the first pointers. In the case of INTERNAL,
+ *               INBOUND, and OUTBOUND this is an Octeon memory address. In the
+ *               case of EXTERNAL, this is the source PCI / PCIe address.
+ * @param last_address
+ *               Address to use for the last pointers. In the case of EXTERNAL,
+ *               INBOUND, and OUTBOUND this is a PCI / PCIe address. In the
+ *               case of INTERNAL, this is the Octeon memory destination address.
+ * @param size   Size of the transfer to perform.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header,
+                             uint64_t first_address, uint64_t last_address,
+                             int size);
+
+/**
+ * Simplified interface to the DMA engines to emulate memcpy()
+ *
+ * @param engine Engine to submit to (0-4)
+ * @param dest   Pointer to the destination memory. cvmx_ptr_to_phys() will be
+ *               used to turn this into a physical address. It cannot be a local
+ *               or CVMX_SHARED block.
+ * @param source Pointer to the source memory.
+ *               cvmx_ptr_to_phys() will be used to turn this
+ *               into a physical address. It cannot be a local
+ *               or CVMX_SHARED block.
+ * @param length Number of bytes to copy
+ *
+ * @return Zero on success, negative on failure
+ */
+static inline int cvmx_dma_engine_memcpy(int engine, void *dest, void *source, int length)
+{
+    cvmx_dma_engine_header_t header;
+    header.u64 = 0;
+    header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL;
+    return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source),
+                                    cvmx_ptr_to_phys(dest), length);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif // __CVMX_CMD_QUEUE_H__
diff --git a/cvmx-ebt3000.c b/cvmx-ebt3000.c
new file mode 100644
index 0000000000000..c3f2e9736889f
--- /dev/null
+++ b/cvmx-ebt3000.c
@@ -0,0 +1,112 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the EBT3000 specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+
+
+void ebt3000_char_write(int char_position, char val)
+{
+    /* Note: phys_to_ptr won't work here, as we are most likely going to access the boot bus. */
+    void *led_base = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, cvmx_sysinfo_get()->led_display_base_addr));
+    if (!led_base)
+        return;
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && cvmx_sysinfo_get()->board_rev_major == 1)
+    {
+        /* Rev 1 board */
+        char *ptr = (char *)(led_base + 4);
+        char_position &= 0x3;  /* only 4 chars */
+        ptr[3 - char_position] = val;
+    }
+    else
+    {
+        /* rev 2 or later board */
+        char *ptr = (char *)(led_base);
+        char_position &= 0x7;  /* only 8 chars */
+        ptr[char_position] = val;
+    }
+}
+
+void ebt3000_str_write(const char *str)
+{
+    /* Note: phys_to_ptr won't work here, as we are most likely going to access the boot bus. */
+    void *led_base;
+    if (!cvmx_sysinfo_get()->led_display_base_addr)
+        return;
+    led_base = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, cvmx_sysinfo_get()->led_display_base_addr));
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && cvmx_sysinfo_get()->board_rev_major == 1)
+    {
+        char *ptr = (char *)(led_base + 4);
+        int i;
+        for (i=0; i<4; i++)
+        {
+            if (*str)
+                ptr[3 - i] = *str++;
+            else
+                ptr[3 - i] = ' ';
+        }
+    }
+    else
+    {
+        /* rev 2 board */
+        char *ptr = (char *)(led_base);
+        int i;
+        for (i=0; i<8; i++)
+        {
+            if (*str)
+                ptr[i] = *str++;
+            else
+                ptr[i] = ' ';
+        }
+    }
+}
diff --git a/cvmx-ebt3000.h b/cvmx-ebt3000.h
new file mode 100644
index 0000000000000..7e519595d77f6
--- /dev/null
+++ b/cvmx-ebt3000.h
@@ -0,0 +1,67 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+#ifndef __CVMX_EBT3000_H__
+#define __CVMX_EBT3000_H__
+
+/**
+ * @file
+ *
+ * Interface to the EBT3000 specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+void ebt3000_str_write(const char *str);
+void ebt3000_char_write(int char_position, char val);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_EBT3000_H__ */
diff --git a/cvmx-fau.h b/cvmx-fau.h
new file mode 100644
index 0000000000000..4e3e4208306bd
--- /dev/null
+++ b/cvmx-fau.h
@@ -0,0 +1,636 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Fetch and Add Unit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_FAU_H__
+#define __CVMX_FAU_H__
+
+#ifndef CVMX_DONT_INCLUDE_CONFIG
+#include "cvmx-config.h"
+#else
+typedef int cvmx_fau_reg_64_t;
+typedef int cvmx_fau_reg_32_t;
+typedef int cvmx_fau_reg_16_t;
+typedef int cvmx_fau_reg_8_t;
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/*
+ * Octeon Fetch and Add Unit (FAU)
+ */
+
+#define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)
+#define CVMX_FAU_BITS_SCRADDR       63,56
+#define CVMX_FAU_BITS_LEN           55,48
+#define CVMX_FAU_BITS_INEVAL        35,14
+#define CVMX_FAU_BITS_TAGWAIT       13,13
+#define CVMX_FAU_BITS_NOADD         13,13
+#define CVMX_FAU_BITS_SIZE          12,11
+#define CVMX_FAU_BITS_REGISTER      10,0
+
+
+typedef enum {
+   CVMX_FAU_OP_SIZE_8  = 0,
+   CVMX_FAU_OP_SIZE_16 = 1,
+   CVMX_FAU_OP_SIZE_32 = 2,
+   CVMX_FAU_OP_SIZE_64 = 3
+} cvmx_fau_op_size_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct
+{
+    uint64_t    error   : 1;
+    int64_t     value   : 63;
+} cvmx_fau_tagwait64_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct
+{
+    uint64_t    error   : 1;
+    int32_t     value   : 31;
+} cvmx_fau_tagwait32_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct
+{
+    uint64_t    error   : 1;
+    int16_t     value   : 15;
+} cvmx_fau_tagwait16_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct
+{
+    uint64_t    error   : 1;
+    int8_t     value    : 7;
+} cvmx_fau_tagwait8_t;
+
+/**
+ * Asynchronous tagwait return definition. If a timeout occurs,
+ * the error bit will be set. Otherwise the value of the
+ * register before the update will be returned.
+ */
+typedef union {
+   uint64_t        u64;
+   struct {
+      uint64_t     invalid: 1;
+      uint64_t     data   :63; // unpredictable if invalid is set
+   } s;
+} cvmx_fau_async_tagwait_result_t;
+
+
+/**
+ * @INTERNAL
+ * Builds a store I/O address for writing to the FAU
+ *
+ * @param noadd  0 = Store value is atomically added to the current value
+ *               1 = Store value is atomically written over the current value
+ * @param reg    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 2 for 16 bit access.
+ *               - Step by 4 for 32 bit access.
+ *               - Step by 8 for 64 bit access.
+ * @return Address to store for atomic update
+ */
+static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
+{
+    return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
+            cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
+            cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
+}
+
+
+/**
+ * @INTERNAL
+ * Builds a I/O address for accessing the FAU
+ *
+ * @param tagwait Should the atomic add wait for the current tag switch
+ *                operation to complete.
+ *                - 0 = Don't wait
+ *                - 1 = Wait for tag switch to complete
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ *                - Step by 4 for 32 bit access.
+ *                - Step by 8 for 64 bit access.
+ * @param value   Signed value to add.
+ *                Note: When performing 32 and 64 bit access, only the low
+ *                22 bits are available.
+ * @return Address to read from for atomic update
+ */
+static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, int64_t value)
+{
+    return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
+            cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
+            cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
+            cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
+}
+
+
+/**
+ * Perform an atomic 64 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @param value   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * @return Value of the register before the update
+ */
+static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+    return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+
+/**
+ * Perform an atomic 32 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @param value   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * @return Value of the register before the update
+ */
+static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+    return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+
+/**
+ * Perform an atomic 16 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @param value   Signed value to add.
+ * @return Value of the register before the update
+ */
+static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+    return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+
+/**
+ * Perform an atomic 8 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ * @param value   Signed value to add.
+ * @return Value of the register before the update
+ */
+static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+    return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+
+/**
+ * Perform an atomic 64 bit add after the current tag switch
+ * completes
+ *
+ * @param reg    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 8 for 64 bit access.
+ * @param value  Signed value to add.
+ *               Note: Only the low 22 bits are available.
+ * @return If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait64_t cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+    union
+    {
+        uint64_t i64;
+        cvmx_fau_tagwait64_t t;
+    } result;
+    result.i64 = cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
+    return result.t;
+}
+
+
+/**
+ * Perform an atomic 32 bit add after the current tag switch
+ * completes
+ *
+ * @param reg    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 4 for 32 bit access.
+ * @param value  Signed value to add.
+ *               Note: Only the low 22 bits are available.
+ * @return If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait32_t cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+    union
+    {
+        uint64_t i32;
+        cvmx_fau_tagwait32_t t;
+    } result;
+    result.i32 = cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
+    return result.t;
+}
+
+
+/**
+ * Perform an atomic 16 bit add after the current tag switch
+ * completes
+ *
+ * @param reg    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 2 for 16 bit access.
+ * @param value  Signed value to add.
+ * @return If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait16_t cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+    union
+    {
+        uint64_t i16;
+        cvmx_fau_tagwait16_t t;
+    } result;
+    result.i16 = cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
+    return result.t;
+}
+
+
+/**
+ * Perform an atomic 8 bit add after the current tag switch
+ * completes
+ *
+ * @param reg    FAU atomic register to access. 0 <= reg < 2048.
+ * @param value  Signed value to add.
+ * @return If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait8_t cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+    union
+    {
+        uint64_t i8;
+        cvmx_fau_tagwait8_t t;
+    } result;
+    result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
+    return result.t;
+}
+
+
+/**
+ * @INTERNAL
+ * Builds I/O data for async operations
+ *
+ * @param scraddr Scratch pad byte addres to write to.  Must be 8 byte aligned
+ * @param value   Signed value to add.
+ *                Note: When performing 32 and 64 bit access, only the low
+ *                22 bits are available.
+ * @param tagwait Should the atomic add wait for the current tag switch
+ *                operation to complete.
+ *                - 0 = Don't wait
+ *                - 1 = Wait for tag switch to complete
+ * @param size    The size of the operation:
+ *                - CVMX_FAU_OP_SIZE_8  (0) = 8 bits
+ *                - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
+ *                - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
+ *                - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ *                - Step by 4 for 32 bit access.
+ *                - Step by 8 for 64 bit access.
+ * @return Data to write using cvmx_send_single
+ */
+static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, uint64_t tagwait,
+                                          cvmx_fau_op_size_t size, uint64_t reg)
+{
+    return (CVMX_FAU_LOAD_IO_ADDRESS |
+                      cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr>>3) |
+                      cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
+                      cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
+                      cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
+                      cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
+                      cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
+}
+
+
+/**
+ * Perform an async atomic 64 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @param value   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
+}
+
+
+/**
+ * Perform an async atomic 32 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @param value   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
+}
+
+
+/**
+ * Perform an async atomic 16 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @param value   Signed value to add.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
+}
+
+
+/**
+ * Perform an async atomic 8 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ * @param value   Signed value to add.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
+}
+
+
+/**
+ * Perform an async atomic 64 bit add after the current tag
+ * switch completes.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ *                If a timeout occurs, the error bit (63) will be set. Otherwise
+ *                the value of the register before the update will be
+ *                returned
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @param value   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
+}
+
+
+/**
+ * Perform an async atomic 32 bit add after the current tag
+ * switch completes.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ *                If a timeout occurs, the error bit (63) will be set. Otherwise
+ *                the value of the register before the update will be
+ *                returned
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @param value   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
+}
+
+
+/**
+ * Perform an async atomic 16 bit add after the current tag
+ * switch completes.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ *                If a timeout occurs, the error bit (63) will be set. Otherwise
+ *                the value of the register before the update will be
+ *                returned
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @param value   Signed value to add.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
+}
+
+
+/**
+ * Perform an async atomic 8 bit add after the current tag
+ * switch completes.
+ *
+ * @param scraddr Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ *                If a timeout occurs, the error bit (63) will be set. Otherwise
+ *                the value of the register before the update will be
+ *                returned
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ * @param value   Signed value to add.
+ * @return Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value)
+{
+    cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
+}
+
+
+
+
+/**
+ * Perform an atomic 64 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @param value   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+    cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
+}
+
+
+/**
+ * Perform an atomic 32 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @param value   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+    cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
+}
+
+
+/**
+ * Perform an atomic 16 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @param value   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+    cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
+}
+
+
+/**
+ * Perform an atomic 8 bit add
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ * @param value   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+    cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
+}
+
+
+/**
+ * Perform an atomic 64 bit write
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @param value   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+    cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
+}
+
+
+/**
+ * Perform an atomic 32 bit write
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @param value   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+    cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
+}
+
+
+/**
+ * Perform an atomic 16 bit write
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @param value   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+    cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
+}
+
+
+/**
+ * Perform an atomic 8 bit write
+ *
+ * @param reg     FAU atomic register to access. 0 <= reg < 2048.
+ * @param value   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+    cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_FAU_H__ */
diff --git a/cvmx-flash.c b/cvmx-flash.c
new file mode 100644
index 0000000000000..2c4ea042bb13b
--- /dev/null
+++ b/cvmx-flash.c
@@ -0,0 +1,672 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides bootbus flash operations
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-flash.h"
+
+#define MAX_NUM_FLASH_CHIPS 8   /* Maximum number of flash chips */
+#define MAX_NUM_REGIONS     8   /* Maximum number of block regions per chip */
+#define DEBUG 1
+
+#define CFI_CMDSET_NONE             0
+#define CFI_CMDSET_INTEL_EXTENDED   1
+#define CFI_CMDSET_AMD_STANDARD     2
+#define CFI_CMDSET_INTEL_STANDARD   3
+#define CFI_CMDSET_AMD_EXTENDED     4
+#define CFI_CMDSET_MITSU_STANDARD   256
+#define CFI_CMDSET_MITSU_EXTENDED   257
+#define CFI_CMDSET_SST              258
+
+typedef struct
+{
+    void *              base_ptr;       /**< Memory pointer to start of flash */
+    int                 is_16bit;       /**< Chip is 16bits wide in 8bit mode */
+    uint16_t            vendor;         /**< Vendor ID of Chip */
+    int                 size;           /**< Size of the chip in bytes */
+    uint64_t            erase_timeout;  /**< Erase timeout in cycles */
+    uint64_t            write_timeout;  /**< Write timeout in cycles */
+    int                 num_regions;    /**< Number of block regions */
+    cvmx_flash_region_t region[MAX_NUM_REGIONS];
+} cvmx_flash_t;
+
+static CVMX_SHARED cvmx_flash_t flash_info[MAX_NUM_FLASH_CHIPS];
+static CVMX_SHARED cvmx_spinlock_t flash_lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER;
+
+
+/**
+ * @INTERNAL
+ * Read a byte from flash
+ *
+ * @param chip_id Chip to read from
+ * @param offset  Offset into the chip
+ * @return Value read
+ */
+static uint8_t __cvmx_flash_read8(int chip_id, int offset)
+{
+    return *(volatile uint8_t *)(flash_info[chip_id].base_ptr + offset);
+}
+
+
+/**
+ * @INTERNAL
+ * Read a byte from flash (for commands)
+ *
+ * @param chip_id Chip to read from
+ * @param offset  Offset into the chip
+ * @return Value read
+ */
+static uint8_t __cvmx_flash_read_cmd(int chip_id, int offset)
+{
+    if (flash_info[chip_id].is_16bit)
+        offset<<=1;
+    return __cvmx_flash_read8(chip_id, offset);
+}
+
+
+/**
+ * @INTERNAL
+ * Read 16bits from flash (for commands)
+ *
+ * @param chip_id Chip to read from
+ * @param offset  Offset into the chip
+ * @return Value read
+ */
+static uint16_t __cvmx_flash_read_cmd16(int chip_id, int offset)
+{
+    uint16_t v = __cvmx_flash_read_cmd(chip_id, offset);
+    v |= __cvmx_flash_read_cmd(chip_id, offset + 1)<<8;
+    return v;
+}
+
+
+/**
+ * @INTERNAL
+ * Write a byte to flash
+ *
+ * @param chip_id Chip to write to
+ * @param offset  Offset into the chip
+ * @param data    Value to write
+ */
+static void __cvmx_flash_write8(int chip_id, int offset, uint8_t data)
+{
+    volatile uint8_t *flash_ptr = (volatile uint8_t *)flash_info[chip_id].base_ptr;
+    flash_ptr[offset] = data;
+}
+
+
+/**
+ * @INTERNAL
+ * Write a byte to flash (for commands)
+ *
+ * @param chip_id Chip to write to
+ * @param offset  Offset into the chip
+ * @param data    Value to write
+ */
+static void __cvmx_flash_write_cmd(int chip_id, int offset, uint8_t data)
+{
+    volatile uint8_t *flash_ptr = (volatile uint8_t *)flash_info[chip_id].base_ptr;
+    flash_ptr[offset<<flash_info[chip_id].is_16bit] = data;
+}
+
+
+/**
+ * @INTERNAL
+ * Query a address and see if a CFI flash chip is there.
+ *
+ * @param chip_id  Chip ID data to fill in if the chip is there
+ * @param base_ptr Memory pointer to the start address to query
+ * @return Zero on success, Negative on failure
+ */
+static int __cvmx_flash_queury_cfi(int chip_id, void *base_ptr)
+{
+    int region;
+    cvmx_flash_t *flash = flash_info + chip_id;
+
+    /* Set the minimum needed for the read and write primitives to work */
+    flash->base_ptr = base_ptr;
+    flash->is_16bit = 1;   /* FIXME: Currently assumes the chip is 16bits */
+
+    /* Put flash in CFI query mode */
+    __cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
+    __cvmx_flash_write_cmd(chip_id, 0x55, 0x98);
+
+    /* Make sure we get the QRY response we should */
+    if ((__cvmx_flash_read_cmd(chip_id, 0x10) != 'Q') ||
+        (__cvmx_flash_read_cmd(chip_id, 0x11) != 'R') ||
+        (__cvmx_flash_read_cmd(chip_id, 0x12) != 'Y'))
+    {
+        flash->base_ptr = NULL;
+        return -1;
+    }
+
+    /* Read the 16bit vendor ID */
+    flash->vendor = __cvmx_flash_read_cmd16(chip_id, 0x13);
+
+    /* Read the write timeout. The timeout is microseconds(us) is 2^0x1f
+        typically. The worst case is this value time 2^0x23 */
+    flash->write_timeout = 1ull << (__cvmx_flash_read_cmd(chip_id, 0x1f) +
+                                    __cvmx_flash_read_cmd(chip_id, 0x23));
+
+    /* Read the erase timeout. The timeout is milliseconds(ms) is 2^0x21
+        typically. The worst case is this value time 2^0x25 */
+    flash->erase_timeout = 1ull << (__cvmx_flash_read_cmd(chip_id, 0x21) +
+                                    __cvmx_flash_read_cmd(chip_id, 0x25));
+
+    /* Get the flash size. This is 2^0x27 */
+    flash->size = 1<<__cvmx_flash_read_cmd(chip_id, 0x27);
+
+    /* Get the number of different sized block regions from 0x2c */
+    flash->num_regions = __cvmx_flash_read_cmd(chip_id, 0x2c);
+
+    int start_offset = 0;
+    /* Loop through all regions get information about each */
+    for (region=0; region<flash->num_regions; region++)
+    {
+        cvmx_flash_region_t *rgn_ptr = flash->region + region;
+        rgn_ptr->start_offset = start_offset;
+
+        /* The number of blocks in each region is a 16 bit little endian
+            endian field. It is encoded at 0x2d + region*4 as (blocks-1) */
+        uint16_t blocks = __cvmx_flash_read_cmd16(chip_id, 0x2d + region*4);
+        rgn_ptr->num_blocks =  1u + blocks;
+
+        /* The size of each block is a 16 bit little endian endian field. It
+            is encoded at 0x2d + region*4 + 2 as (size/256). Zero is a special
+            case representing 128 */
+        uint16_t size = __cvmx_flash_read_cmd16(chip_id, 0x2d + region*4 + 2);
+        if (size == 0)
+            rgn_ptr->block_size = 128;
+        else
+            rgn_ptr->block_size = 256u * size;
+
+        start_offset += rgn_ptr->block_size * rgn_ptr->num_blocks;
+    }
+
+    /* Take the chip out of CFI query mode */
+    switch (flash_info[chip_id].vendor)
+    {
+        case CFI_CMDSET_AMD_STANDARD:
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xf0);
+        case CFI_CMDSET_INTEL_STANDARD:
+        case CFI_CMDSET_INTEL_EXTENDED:
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xff);
+            break;
+    }
+
+    /* Convert the timeouts to cycles */
+    flash->write_timeout *= cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+    flash->erase_timeout *= cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+
+#if DEBUG
+    /* Print the information about the chip */
+    cvmx_dprintf("cvmx-flash: Base pointer:  %p\n"
+           "            Vendor:        0x%04x\n"
+           "            Size:          %d bytes\n"
+           "            Num regions:   %d\n"
+           "            Erase timeout: %llu cycles\n"
+           "            Write timeout: %llu cycles\n",
+           flash->base_ptr,
+           (unsigned int)flash->vendor,
+           flash->size,
+           flash->num_regions,
+           (unsigned long long)flash->erase_timeout,
+           (unsigned long long)flash->write_timeout);
+
+    for (region=0; region<flash->num_regions; region++)
+    {
+        cvmx_dprintf("            Region %d: offset 0x%x, %d blocks, %d bytes/block\n",
+               region,
+               flash->region[region].start_offset,
+               flash->region[region].num_blocks,
+               flash->region[region].block_size);
+    }
+#endif
+
+    return 0;
+}
+
+
+/**
+ * Initialize the flash access library
+ */
+void cvmx_flash_initialize(void)
+{
+    int boot_region;
+    int chip_id = 0;
+
+    memset(flash_info, 0, sizeof(flash_info));
+
+    /* Loop through each boot bus chip select region */
+    for (boot_region=0; boot_region<MAX_NUM_FLASH_CHIPS; boot_region++)
+    {
+        cvmx_mio_boot_reg_cfgx_t region_cfg;
+        region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFG0 + boot_region*8);
+        /* Only try chip select regions that are enabled. This assumes the
+            bootloader already setup the flash */
+        if (region_cfg.s.en)
+        {
+            /* Convert the hardware address to a pointer. Note that the bootbus,
+                unlike memory, isn't 1:1 mapped in the simple exec */
+            void *base_ptr = cvmx_phys_to_ptr((region_cfg.s.base<<16) | 0xffffffff80000000ull);
+            if (__cvmx_flash_queury_cfi(chip_id, base_ptr) == 0)
+            {
+                /* Valid CFI flash chip found */
+                chip_id++;
+            }
+        }
+    }
+
+    if (chip_id == 0)
+        cvmx_dprintf("cvmx-flash: No CFI chips found\n");
+}
+
+
+/**
+ * Return a pointer to the flash chip
+ *
+ * @param chip_id Chip ID to return
+ * @return NULL if the chip doesn't exist
+ */
+void *cvmx_flash_get_base(int chip_id)
+{
+    return flash_info[chip_id].base_ptr;
+}
+
+
+/**
+ * Return the number of erasable regions on the chip
+ *
+ * @param chip_id Chip to return info for
+ * @return Number of regions
+ */
+int cvmx_flash_get_num_regions(int chip_id)
+{
+    return flash_info[chip_id].num_regions;
+}
+
+
+/**
+ * Return information about a flash chips region
+ *
+ * @param chip_id Chip to get info for
+ * @param region  Region to get info for
+ * @return Region information
+ */
+const cvmx_flash_region_t *cvmx_flash_get_region_info(int chip_id, int region)
+{
+    return flash_info[chip_id].region + region;
+}
+
+
+/**
+ * Erase a block on the flash chip
+ *
+ * @param chip_id Chip to erase a block on
+ * @param region  Region to erase a block in
+ * @param block   Block number to erase
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_flash_erase_block(int chip_id, int region, int block)
+{
+    cvmx_spinlock_lock(&flash_lock);
+#if DEBUG
+    cvmx_dprintf("cvmx-flash: Erasing chip %d, region %d, block %d\n",
+           chip_id, region, block);
+#endif
+
+    int offset = flash_info[chip_id].region[region].start_offset +
+                block * flash_info[chip_id].region[region].block_size;
+
+    switch (flash_info[chip_id].vendor)
+    {
+        case CFI_CMDSET_AMD_STANDARD:
+        {
+            /* Send the erase sector command sequence */
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
+            __cvmx_flash_write_cmd(chip_id, 0x555, 0xaa);
+            __cvmx_flash_write_cmd(chip_id, 0x2aa, 0x55);
+            __cvmx_flash_write_cmd(chip_id, 0x555, 0x80);
+            __cvmx_flash_write_cmd(chip_id, 0x555, 0xaa);
+            __cvmx_flash_write_cmd(chip_id, 0x2aa, 0x55);
+            __cvmx_flash_write8(chip_id, offset, 0x30);
+
+            /* Loop checking status */
+            uint8_t status = __cvmx_flash_read8(chip_id, offset);
+            uint64_t start_cycle = cvmx_get_cycle();
+            while (1)
+            {
+                /* Read the status and xor it with the old status so we can
+                    find toggling bits */
+                uint8_t old_status = status;
+                status = __cvmx_flash_read8(chip_id, offset);
+                uint8_t toggle = status ^ old_status;
+
+                /* Check if the erase in progress bit is toggling */
+                if (toggle & (1<<6))
+                {
+                    /* Check hardware timeout */
+                    if (status & (1<<5))
+                    {
+                        /* Chip has signalled a timeout. Reread the status */
+                        old_status = __cvmx_flash_read8(chip_id, offset);
+                        status = __cvmx_flash_read8(chip_id, offset);
+                        toggle = status ^ old_status;
+
+                        /* Check if the erase in progress bit is toggling */
+                        if (toggle & (1<<6))
+                        {
+                            cvmx_dprintf("cvmx-flash: Hardware timeout erasing block\n");
+                            cvmx_spinlock_unlock(&flash_lock);
+                            return -1;
+                        }
+                        else
+                            break;  /* Not toggling, erase complete */
+                    }
+                }
+                else
+                    break;  /* Not toggling, erase complete */
+
+                if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].erase_timeout)
+                {
+                    cvmx_dprintf("cvmx-flash: Timeout erasing block\n");
+                    cvmx_spinlock_unlock(&flash_lock);
+                    return -1;
+                }
+            }
+
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
+            cvmx_spinlock_unlock(&flash_lock);
+            return 0;
+        }
+        case CFI_CMDSET_INTEL_STANDARD:
+        case CFI_CMDSET_INTEL_EXTENDED:
+        {
+            /* Send the erase sector command sequence */
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
+            __cvmx_flash_write8(chip_id, offset, 0x20);
+            __cvmx_flash_write8(chip_id, offset, 0xd0);
+
+            /* Loop checking status */
+            uint8_t status = __cvmx_flash_read8(chip_id, offset);
+            uint64_t start_cycle = cvmx_get_cycle();
+            while ((status & 0x80) == 0)
+            {
+                if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].erase_timeout)
+                {
+                    cvmx_dprintf("cvmx-flash: Timeout erasing block\n");
+                    cvmx_spinlock_unlock(&flash_lock);
+                    return -1;
+                }
+                status = __cvmx_flash_read8(chip_id, offset);
+            }
+
+            /* Check the final status */
+            if (status & 0x7f)
+            {
+                cvmx_dprintf("cvmx-flash: Hardware failure erasing block\n");
+                cvmx_spinlock_unlock(&flash_lock);
+                return -1;
+            }
+
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
+            cvmx_spinlock_unlock(&flash_lock);
+            return 0;
+        }
+    }
+
+    cvmx_dprintf("cvmx-flash: Unsupported flash vendor\n");
+    cvmx_spinlock_unlock(&flash_lock);
+    return -1;
+}
+
+
+/**
+ * Write a block on the flash chip
+ *
+ * @param chip_id Chip to write a block on
+ * @param region  Region to write a block in
+ * @param block   Block number to write
+ * @param data    Data to write
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_flash_write_block(int chip_id, int region, int block, const void *data)
+{
+    cvmx_spinlock_lock(&flash_lock);
+#if DEBUG
+    cvmx_dprintf("cvmx-flash: Writing chip %d, region %d, block %d\n",
+           chip_id, region, block);
+#endif
+    int offset = flash_info[chip_id].region[region].start_offset +
+                block * flash_info[chip_id].region[region].block_size;
+    int len = flash_info[chip_id].region[region].block_size;
+    const uint8_t *ptr = (const uint8_t *)data;
+
+    switch (flash_info[chip_id].vendor)
+    {
+        case CFI_CMDSET_AMD_STANDARD:
+        {
+            /* Loop through one byte at a time */
+            while (len--)
+            {
+                /* Send the program sequence */
+                __cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
+                __cvmx_flash_write_cmd(chip_id, 0x555, 0xaa);
+                __cvmx_flash_write_cmd(chip_id, 0x2aa, 0x55);
+                __cvmx_flash_write_cmd(chip_id, 0x555, 0xa0);
+                __cvmx_flash_write8(chip_id, offset, *ptr);
+
+                /* Loop polling for status */
+                uint64_t start_cycle = cvmx_get_cycle();
+                while (1)
+                {
+                    uint8_t status = __cvmx_flash_read8(chip_id, offset);
+                    if (((status ^ *ptr) & (1<<7)) == 0)
+                        break;  /* Data matches, this byte is done */
+                    else if (status & (1<<5))
+                    {
+                        /* Hardware timeout, recheck status */
+                        status = __cvmx_flash_read8(chip_id, offset);
+                        if (((status ^ *ptr) & (1<<7)) == 0)
+                            break;  /* Data matches, this byte is done */
+                        else
+                        {
+                            cvmx_dprintf("cvmx-flash: Hardware write timeout\n");
+                            cvmx_spinlock_unlock(&flash_lock);
+                            return -1;
+                        }
+                    }
+
+                    if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].write_timeout)
+                    {
+                        cvmx_dprintf("cvmx-flash: Timeout writing block\n");
+                        cvmx_spinlock_unlock(&flash_lock);
+                        return -1;
+                    }
+                }
+
+                /* Increment to the next byte */
+                ptr++;
+                offset++;
+            }
+
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xf0); /* Reset the flash chip */
+            cvmx_spinlock_unlock(&flash_lock);
+            return 0;
+        }
+        case CFI_CMDSET_INTEL_STANDARD:
+        case CFI_CMDSET_INTEL_EXTENDED:
+        {
+cvmx_dprintf("%s:%d len=%d\n", __FUNCTION__, __LINE__, len);
+            /* Loop through one byte at a time */
+            while (len--)
+            {
+                /* Send the program sequence */
+                __cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
+                __cvmx_flash_write8(chip_id, offset, 0x40);
+                __cvmx_flash_write8(chip_id, offset, *ptr);
+
+                /* Loop polling for status */
+                uint8_t status = __cvmx_flash_read8(chip_id, offset);
+                uint64_t start_cycle = cvmx_get_cycle();
+                while ((status & 0x80) == 0)
+                {
+                    if (cvmx_get_cycle() > start_cycle + flash_info[chip_id].write_timeout)
+                    {
+                        cvmx_dprintf("cvmx-flash: Timeout writing block\n");
+                        cvmx_spinlock_unlock(&flash_lock);
+                        return -1;
+                    }
+                    status = __cvmx_flash_read8(chip_id, offset);
+                }
+
+                /* Check the final status */
+                if (status & 0x7f)
+                {
+                    cvmx_dprintf("cvmx-flash: Hardware failure erasing block\n");
+                    cvmx_spinlock_unlock(&flash_lock);
+                    return -1;
+                }
+
+                /* Increment to the next byte */
+                ptr++;
+                offset++;
+            }
+cvmx_dprintf("%s:%d\n", __FUNCTION__, __LINE__);
+
+            __cvmx_flash_write_cmd(chip_id, 0x00, 0xff); /* Reset the flash chip */
+            cvmx_spinlock_unlock(&flash_lock);
+            return 0;
+        }
+    }
+
+    cvmx_dprintf("cvmx-flash: Unsupported flash vendor\n");
+    cvmx_spinlock_unlock(&flash_lock);
+    return -1;
+}
+
+
+/**
+ * Erase and write data to a flash
+ *
+ * @param address Memory address to write to
+ * @param data    Data to write
+ * @param len     Length of the data
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_flash_write(void *address, const void *data, int len)
+{
+    int chip_id;
+
+    /* Find which chip controls this address. Don't allow the write to span
+        multiple chips */
+    for (chip_id=0; chip_id<MAX_NUM_FLASH_CHIPS; chip_id++)
+    {
+        if ((flash_info[chip_id].base_ptr <= address) &&
+            (flash_info[chip_id].base_ptr + flash_info[chip_id].size >= address + len))
+            break;
+    }
+
+    if (chip_id == MAX_NUM_FLASH_CHIPS)
+    {
+        cvmx_dprintf("cvmx-flash: Unable to find chip that contains address %p\n", address);
+        return -1;
+    }
+
+    cvmx_flash_t *flash = flash_info + chip_id;
+
+    /* Determine which block region we need to start writing to */
+    void *region_base = flash->base_ptr;
+    int region = 0;
+    while (region_base + flash->region[region].num_blocks * flash->region[region].block_size <= address)
+    {
+        region++;
+        region_base = flash->base_ptr + flash->region[region].start_offset;
+    }
+
+    /* Determine which block in the region to start at */
+    int block = (address - region_base) / flash->region[region].block_size;
+
+    /* Require all writes to start on block boundries */
+    if (address != region_base + block*flash->region[region].block_size)
+    {
+        cvmx_dprintf("cvmx-flash: Write address not aligned on a block boundry\n");
+        return -1;
+    }
+
+    /* Loop until we're out of data */
+    while (len > 0)
+    {
+        /* Erase the current block */
+        if (cvmx_flash_erase_block(chip_id, region, block))
+            return -1;
+        /* Write the new data */
+        if (cvmx_flash_write_block(chip_id, region, block, data))
+            return -1;
+
+        /* Increment to the next block */
+        data += flash->region[region].block_size;
+        len -= flash->region[region].block_size;
+        block++;
+        if (block >= flash->region[region].num_blocks)
+        {
+            block = 0;
+            region++;
+        }
+    }
+
+    return 0;
+}
+
diff --git a/cvmx-flash.h b/cvmx-flash.h
new file mode 100644
index 0000000000000..6bac1160c4018
--- /dev/null
+++ b/cvmx-flash.h
@@ -0,0 +1,134 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides bootbus flash operations
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+
+#ifndef __CVMX_FLASH_H__
+#define __CVMX_FLASH_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+    int start_offset;
+    int block_size;
+    int num_blocks;
+} cvmx_flash_region_t;
+
+/**
+ * Initialize the flash access library
+ */
+void cvmx_flash_initialize(void);
+
+/**
+ * Return a pointer to the flash chip
+ *
+ * @param chip_id Chip ID to return
+ * @return NULL if the chip doesn't exist
+ */
+void *cvmx_flash_get_base(int chip_id);
+
+/**
+ * Return the number of erasable regions on the chip
+ *
+ * @param chip_id Chip to return info for
+ * @return Number of regions
+ */
+int cvmx_flash_get_num_regions(int chip_id);
+
+/**
+ * Return information about a flash chips region
+ *
+ * @param chip_id Chip to get info for
+ * @param region  Region to get info for
+ * @return Region information
+ */
+const cvmx_flash_region_t *cvmx_flash_get_region_info(int chip_id, int region);
+
+/**
+ * Erase a block on the flash chip
+ *
+ * @param chip_id Chip to erase a block on
+ * @param region  Region to erase a block in
+ * @param block   Block number to erase
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_flash_erase_block(int chip_id, int region, int block);
+
+/**
+ * Write a block on the flash chip
+ *
+ * @param chip_id Chip to write a block on
+ * @param region  Region to write a block in
+ * @param block   Block number to write
+ * @param data    Data to write
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_flash_write_block(int chip_id, int region, int block, const void *data);
+
+/**
+ * Erase and write data to a flash
+ *
+ * @param address Memory address to write to
+ * @param data    Data to write
+ * @param len     Length of the data
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_flash_write(void *address, const void *data, int len);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_FLASH_H__ */
diff --git a/cvmx-fpa.c b/cvmx-fpa.c
new file mode 100644
index 0000000000000..6e719b507cf03
--- /dev/null
+++ b/cvmx-fpa.c
@@ -0,0 +1,193 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the hardware Free Pool Allocator.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-fpa.h"
+#include "cvmx-ipd.h"
+
+/**
+ * Current state of all the pools. Use access functions
+ * instead of using it directly.
+ */
+CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
+
+
+/**
+ * Setup a FPA pool to control a new block of memory. The
+ * buffer pointer must be a physical address.
+ *
+ * @param pool       Pool to initialize
+ *                   0 <= pool < 8
+ * @param name       Constant character string to name this pool.
+ *                   String is not copied.
+ * @param buffer     Pointer to the block of memory to use. This must be
+ *                   accessable by all processors and external hardware.
+ * @param block_size Size for each block controlled by the FPA
+ * @param num_blocks Number of blocks
+ *
+ * @return 0 on Success,
+ *         -1 on failure
+ */
+int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
+                         uint64_t block_size, uint64_t num_blocks)
+{
+    char *ptr;
+    if (!buffer)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
+        return(-1);
+    }
+    if (pool >= CVMX_FPA_NUM_POOLS)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
+        return(-1);
+    }
+
+    if (block_size < CVMX_FPA_MIN_BLOCK_SIZE)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
+        return(-1);
+    }
+
+    if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT-1)) != 0)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
+        return(-1);
+    }
+
+    cvmx_fpa_pool_info[pool].name = name;
+    cvmx_fpa_pool_info[pool].size = block_size;
+    cvmx_fpa_pool_info[pool].starting_element_count = num_blocks;
+    cvmx_fpa_pool_info[pool].base = buffer;
+
+    ptr = (char*)buffer;
+    while (num_blocks--)
+    {
+        cvmx_fpa_free(ptr, pool, 0);
+        ptr += block_size;
+    }
+    return(0);
+}
+
+/**
+ * Shutdown a Memory pool and validate that it had all of
+ * the buffers originally placed in it.
+ *
+ * @param pool   Pool to shutdown
+ * @return Zero on success
+ *         - Positive is count of missing buffers
+ *         - Negative is too many buffers or corrupted pointers
+ */
+uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
+{
+    uint64_t errors = 0;
+    uint64_t count  = 0;
+    uint64_t base   = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
+    uint64_t finish = base + cvmx_fpa_pool_info[pool].size * cvmx_fpa_pool_info[pool].starting_element_count;
+    void *ptr;
+    uint64_t address;
+
+    count = 0;
+    do
+    {
+        ptr = cvmx_fpa_alloc(pool);
+        if (ptr)
+            address = cvmx_ptr_to_phys(ptr);
+        else
+            address = 0;
+        if (address)
+        {
+            if ((address >= base) && (address < finish) &&
+                (((address - base) % cvmx_fpa_pool_info[pool].size) == 0))
+            {
+                count++;
+            }
+            else
+            {
+                cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
+                       (unsigned long long)address, cvmx_fpa_pool_info[pool].name, (int)pool);
+                errors++;
+            }
+        }
+    } while (address);
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+    if (pool == 0)
+	cvmx_ipd_free_ptr();
+#endif
+
+    if (errors)
+    {
+        cvmx_dprintf("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
+               cvmx_fpa_pool_info[pool].name, (int)pool, (unsigned long long)base, (unsigned long long)finish, (unsigned long long)cvmx_fpa_pool_info[pool].size);
+        return -errors;
+    }
+    else
+        return 0;
+}
+
+uint64_t cvmx_fpa_get_block_size(uint64_t pool)
+{
+    switch (pool)
+    {
+        case 0: return(CVMX_FPA_POOL_0_SIZE);
+        case 1: return(CVMX_FPA_POOL_1_SIZE);
+        case 2: return(CVMX_FPA_POOL_2_SIZE);
+        case 3: return(CVMX_FPA_POOL_3_SIZE);
+        case 4: return(CVMX_FPA_POOL_4_SIZE);
+        case 5: return(CVMX_FPA_POOL_5_SIZE);
+        case 6: return(CVMX_FPA_POOL_6_SIZE);
+        case 7: return(CVMX_FPA_POOL_7_SIZE);
+        default: return(0);
+    }
+}
diff --git a/cvmx-fpa.h b/cvmx-fpa.h
new file mode 100644
index 0000000000000..b1721164b9661
--- /dev/null
+++ b/cvmx-fpa.h
@@ -0,0 +1,300 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Free Pool Allocator.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_FPA_H__
+#define __CVMX_FPA_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_FPA_NUM_POOLS      8
+#define CVMX_FPA_MIN_BLOCK_SIZE 128
+#define CVMX_FPA_ALIGNMENT      128
+
+/**
+ * Structure describing the data format used for stores to the FPA.
+ */
+typedef union
+{
+    uint64_t        u64;
+    struct {
+        uint64_t    scraddr : 8;    /**< the (64-bit word) location in scratchpad to write to (if len != 0) */
+        uint64_t    len     : 8;    /**< the number of words in the response (0 => no response) */
+        uint64_t    did     : 8;    /**< the ID of the device on the non-coherent bus */
+        uint64_t    addr    :40;    /**< the address that will appear in the first tick on the NCB bus */
+    } s;
+} cvmx_fpa_iobdma_data_t;
+
+/**
+ * Structure describing the current state of a FPA pool.
+ */
+typedef struct
+{
+    const char *name;                   /**< Name it was created under */
+    uint64_t    size;                   /**< Size of each block */
+    void *      base;                   /**< The base memory address of whole block */
+    uint64_t    starting_element_count; /**< The number of elements in the pool at creation */
+} cvmx_fpa_pool_info_t;
+
+/**
+ * Current state of all the pools. Use access functions
+ * instead of using it directly.
+ */
+extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Return the name of the pool
+ *
+ * @param pool   Pool to get the name of
+ * @return The name
+ */
+static inline const char *cvmx_fpa_get_name(uint64_t pool)
+{
+    return cvmx_fpa_pool_info[pool].name;
+}
+
+/**
+ * Return the base of the pool
+ *
+ * @param pool   Pool to get the base of
+ * @return The base
+ */
+static inline void *cvmx_fpa_get_base(uint64_t pool)
+{
+    return cvmx_fpa_pool_info[pool].base;
+}
+
+/**
+ * Check if a pointer belongs to an FPA pool. Return non-zero
+ * if the supplied pointer is inside the memory controlled by
+ * an FPA pool.
+ *
+ * @param pool   Pool to check
+ * @param ptr    Pointer to check
+ * @return Non-zero if pointer is in the pool. Zero if not
+ */
+static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
+{
+    return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
+            ((char*)ptr < ((char*)(cvmx_fpa_pool_info[pool].base)) + cvmx_fpa_pool_info[pool].size * cvmx_fpa_pool_info[pool].starting_element_count));
+}
+
+
+
+/**
+ * Enable the FPA for use. Must be performed after any CSR
+ * configuration but before any other FPA functions.
+ */
+static inline void cvmx_fpa_enable(void)
+{
+    cvmx_fpa_ctl_status_t status;
+
+    status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
+    if (status.s.enb)
+    {
+        cvmx_dprintf("Warning: Enabling FPA when FPA already enabled.\n");
+    }
+
+    /* Do runtime check as we allow pass1 compiled code to run on pass2 chips */
+    if (cvmx_octeon_is_pass1())
+    {
+        cvmx_fpa_fpf_marks_t marks;
+        int i;
+        for (i=1; i<8; i++)
+        {
+            marks.u64 = cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i-1)*8ull);
+            marks.s.fpf_wr = 0xe0;
+            cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i-1)*8ull, marks.u64);
+        }
+
+        /* Enforce a 10 cycle delay between config and enable */
+        cvmx_wait(10);
+    }
+
+    status.u64 = 0; /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
+    status.s.enb = 1;
+    cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
+}
+
+
+/**
+ * Get a new block from the FPA
+ *
+ * @param pool   Pool to get the block from
+ * @return Pointer to the block or NULL on failure
+ */
+static inline void *cvmx_fpa_alloc(uint64_t pool)
+{
+    uint64_t address = cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA,pool)));
+    if (address)
+        return cvmx_phys_to_ptr(address);
+    else
+        return NULL;
+}
+
+
+/**
+ * Asynchronously get a new block from the FPA
+ *
+ * @param scr_addr Local scratch address to put response in.  This is a byte address,
+ *                  but must be 8 byte aligned.
+ * @param pool      Pool to get the block from
+ */
+static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
+{
+   cvmx_fpa_iobdma_data_t data;
+
+   /* Hardware only uses 64 bit alligned locations, so convert from byte address
+   ** to 64-bit index
+   */
+   data.s.scraddr = scr_addr >> 3;
+   data.s.len = 1;
+   data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA,pool);
+   data.s.addr = 0;
+   cvmx_send_single(data.u64);
+}
+
+
+/**
+ * Free a block allocated with a FPA pool.
+ * Does NOT provide memory ordering in cases where the memory block was modified by the core.
+ *
+ * @param ptr    Block to free
+ * @param pool   Pool to put it in
+ * @param num_cache_lines
+ *               Cache lines to invalidate
+ */
+static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, uint64_t num_cache_lines)
+{
+    cvmx_addr_t newptr;
+    newptr.u64 = cvmx_ptr_to_phys(ptr);
+    newptr.sfilldidspace.didspace = CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA,pool));
+    asm volatile ("" : : : "memory");  /* Prevent GCC from reordering around free */
+    /* value written is number of cache lines not written back */
+    cvmx_write_io(newptr.u64, num_cache_lines);
+}
+
+/**
+ * Free a block allocated with a FPA pool.  Provides required memory
+ * ordering in cases where memory block was modified by core.
+ *
+ * @param ptr    Block to free
+ * @param pool   Pool to put it in
+ * @param num_cache_lines
+ *               Cache lines to invalidate
+ */
+static inline void cvmx_fpa_free(void *ptr, uint64_t pool, uint64_t num_cache_lines)
+{
+    cvmx_addr_t newptr;
+    newptr.u64 = cvmx_ptr_to_phys(ptr);
+    newptr.sfilldidspace.didspace = CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA,pool));
+    /* Make sure that any previous writes to memory go out before we free this buffer.
+    ** This also serves as a barrier to prevent GCC from reordering operations to after
+    ** the free. */
+    CVMX_SYNCWS;
+    /* value written is number of cache lines not written back */
+    cvmx_write_io(newptr.u64, num_cache_lines);
+}
+
+
+/**
+ * Setup a FPA pool to control a new block of memory.
+ * This can only be called once per pool. Make sure proper
+ * locking enforces this.
+ *
+ * @param pool       Pool to initialize
+ *                   0 <= pool < 8
+ * @param name       Constant character string to name this pool.
+ *                   String is not copied.
+ * @param buffer     Pointer to the block of memory to use. This must be
+ *                   accessable by all processors and external hardware.
+ * @param block_size Size for each block controlled by the FPA
+ * @param num_blocks Number of blocks
+ *
+ * @return 0 on Success,
+ *         -1 on failure
+ */
+extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
+                                uint64_t block_size, uint64_t num_blocks);
+
+
+/**
+ * Shutdown a Memory pool and validate that it had all of
+ * the buffers originally placed in it. This should only be
+ * called by one processor after all hardware has finished
+ * using the pool.
+ *
+ * @param pool   Pool to shutdown
+ * @return Zero on success
+ *         - Positive is count of missing buffers
+ *         - Negative is too many buffers or corrupted pointers
+ */
+extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
+
+
+/**
+ * Get the size of blocks controlled by the pool
+ * This is resolved to a constant at compile time.
+ *
+ * @param pool   Pool to access
+ * @return Size of the block in bytes
+ */
+uint64_t cvmx_fpa_get_block_size(uint64_t pool);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif //  __CVM_FPA_H__
diff --git a/cvmx-gmx.h b/cvmx-gmx.h
new file mode 100644
index 0000000000000..e2e4d1ca857cb
--- /dev/null
+++ b/cvmx-gmx.h
@@ -0,0 +1,94 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the GMX hardware.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_GMX_H__
+#define __CVMX_GMX_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Disables the sending of flow control (pause) frames on the specified
+ * RGMII port(s).
+ *
+ * @param interface Which interface (0 or 1)
+ * @param port_mask Mask (4bits) of which ports on the interface to disable
+ *                  backpressure on.
+ *                  1 => disable backpressure
+ *                  0 => enable backpressure
+ *
+ * @return 0 on success
+ *         -1 on error
+ */
+
+static inline int cvmx_gmx_set_backpressure_override(uint32_t interface, uint32_t port_mask)
+{
+    cvmx_gmxx_tx_ovr_bp_t gmxx_tx_ovr_bp;
+    /* Check for valid arguments */
+    if (port_mask & ~0xf || interface & ~0x1)
+        return(-1);
+    gmxx_tx_ovr_bp.u64 = 0;
+    gmxx_tx_ovr_bp.s.en = port_mask; /* Per port Enable back pressure override */
+    gmxx_tx_ovr_bp.s.ign_full = port_mask; /* Ignore the RX FIFO full when computing BP */
+    cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmxx_tx_ovr_bp.u64);
+    return(0);
+
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-gpio.h b/cvmx-gpio.h
new file mode 100644
index 0000000000000..ffbd815326359
--- /dev/null
+++ b/cvmx-gpio.h
@@ -0,0 +1,122 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * General Purpose IO interface.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_GPIO_H__
+#define __CVMX_GPIO_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Clear the interrupt rising edge detector for the supplied
+ * pins in the mask. Chips which have more than 16 GPIO pins
+ * can't use them for interrupts.
+ *
+ * @param clear_mask Mask of pins to clear
+ */
+static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
+{
+    cvmx_gpio_int_clr_t gpio_int_clr;
+    gpio_int_clr.u64 = 0;
+    gpio_int_clr.s.type = clear_mask;
+    cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
+}
+
+
+/**
+ * GPIO Read Data
+ *
+ * @return Status of the GPIO pins
+ */
+static inline uint32_t cvmx_gpio_read(void)
+{
+    cvmx_gpio_rx_dat_t gpio_rx_dat;
+    gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT);
+    return gpio_rx_dat.s.dat;
+}
+
+
+/**
+ * GPIO Clear pin
+ *
+ * @param clear_mask Bit mask to indicate which bits to drive to '0'.
+ */
+static inline void cvmx_gpio_clear(uint32_t clear_mask)
+{
+    cvmx_gpio_tx_clr_t gpio_tx_clr;
+    gpio_tx_clr.u64 = 0;
+    gpio_tx_clr.s.clr = clear_mask;
+    cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64);
+}
+
+
+/**
+ * GPIO Set pin
+ *
+ * @param set_mask Bit mask to indicate which bits to drive to '1'.
+ */
+static inline void cvmx_gpio_set(uint32_t set_mask)
+{
+    cvmx_gpio_tx_set_t gpio_tx_set;
+    gpio_tx_set.u64 = 0;
+    gpio_tx_set.s.set = set_mask;
+    cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-helper-board.c b/cvmx-helper-board.c
new file mode 100644
index 0000000000000..503e3b6b018b8
--- /dev/null
+++ b/cvmx-helper-board.c
@@ -0,0 +1,653 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper functions to abstract board specific data about
+ * network ports from the rest of the cvmx-helper files.
+ *
+ * <hr>$Revision: 41946 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-app-init.h"
+#include "cvmx-mdio.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-board.h"
+
+/**
+ * cvmx_override_board_link_get(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the process of
+ * talking to a PHY to determine link speed. It is called every
+ * time a PHY must be polled for link status. Users should set
+ * this pointer to a function before calling any cvmx-helper
+ * operations.
+ */
+CVMX_SHARED cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port) = NULL;
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. A result of -1 means there isn't a MII capable PHY
+ * connected to this port. On chips supporting multiple MII
+ * busses the bus number is encoded in bits <15:8>.
+ *
+ * This function must be modified for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It replies on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @param ipd_port Octeon IPD port to get the MII address for.
+ *
+ * @return MII PHY address and bus number or -1.
+ */
+int cvmx_helper_board_get_mii_address(int ipd_port)
+{
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+        case CVMX_BOARD_TYPE_SIM:
+            /* Simulator doesn't have MII */
+            return -1;
+        case CVMX_BOARD_TYPE_EBT3000:
+        case CVMX_BOARD_TYPE_EBT5800:
+        case CVMX_BOARD_TYPE_THUNDER:
+        case CVMX_BOARD_TYPE_NICPRO2:
+            /* Interface 0 is SPI4, interface 1 is RGMII */
+            if ((ipd_port >= 16) && (ipd_port < 20))
+                return ipd_port - 16;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_KODAMA:
+        case CVMX_BOARD_TYPE_EBH3100:
+        case CVMX_BOARD_TYPE_HIKARI:
+        case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+            /* Port 0 is WAN connected to a PHY, Port 1 is GMII connected to a
+                switch */
+            if (ipd_port == 0)
+                return 4;
+            else if (ipd_port == 1)
+                return 9;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_NAC38:
+            /* Board has 8 RGMII ports PHYs are 0-7 */
+            if ((ipd_port >= 0) && (ipd_port < 4))
+                return ipd_port;
+            else if ((ipd_port >= 16) && (ipd_port < 20))
+                return ipd_port - 16 + 4;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_EBH3000:
+            /* Board has dual SPI4 and no PHYs */
+            return -1;
+        case CVMX_BOARD_TYPE_EBH5200:
+        case CVMX_BOARD_TYPE_EBH5201:
+        case CVMX_BOARD_TYPE_EBT5200:
+            /* Board has 4 SGMII ports. The PHYs start right after the MII
+                ports MII0 = 0, MII1 = 1, SGMII = 2-5 */
+            if ((ipd_port >= 0) && (ipd_port < 4))
+                return ipd_port+2;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_EBH5600:
+        case CVMX_BOARD_TYPE_EBH5601:
+            /* Board has 8 SGMII ports. 4 connect out, two connect to a switch,
+                and 2 loop to each other */
+            if ((ipd_port >= 0) && (ipd_port < 4))
+                return ipd_port+1;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_CUST_NB5:
+            if (ipd_port == 2)
+                return 4;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_NIC_XLE_4G:
+            /* Board has 4 SGMII ports. connected QLM3(interface 1) */
+            if ((ipd_port >= 16) && (ipd_port < 20))
+                return ipd_port - 16 + 1;
+            else
+                return -1;
+        case CVMX_BOARD_TYPE_BBGW_REF:
+            return -1;  /* No PHYs are connected to Octeon, everything is through switch */
+    }
+
+    /* Some unknown board. Somebody forgot to update this function... */
+    cvmx_dprintf("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
+                 cvmx_sysinfo_get()->board_type);
+    return -1;
+}
+
+
+/**
+ * @INTERNAL
+ * This function is the board specific method of determining an
+ * ethernet ports link speed. Most Octeon boards have Marvell PHYs
+ * and are handled by the fall through case. This function must be
+ * updated for boards that don't have the normal Marvell PHYs.
+ *
+ * This function must be modified for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relies on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @param ipd_port IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * @return The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
+{
+    cvmx_helper_link_info_t result;
+    int phy_addr;
+    int is_broadcom_phy = 0;
+
+    /* Give the user a chance to override the processing of this function */
+    if (cvmx_override_board_link_get)
+        return cvmx_override_board_link_get(ipd_port);
+
+    /* Unless we fix it later, all links are defaulted to down */
+    result.u64 = 0;
+
+    /* This switch statement should handle all ports that either don't use
+        Marvell PHYS, or don't support in-band status */
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+        case CVMX_BOARD_TYPE_SIM:
+            /* The simulator gives you a simulated 1Gbps full duplex link */
+            result.s.link_up = 1;
+            result.s.full_duplex = 1;
+            result.s.speed = 1000;
+            return result;
+        case CVMX_BOARD_TYPE_EBH3100:
+        case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+            /* Port 1 on these boards is always Gigabit */
+            if (ipd_port == 1)
+            {
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 1000;
+                return result;
+            }
+            /* Fall through to the generic code below */
+            break;
+        case CVMX_BOARD_TYPE_CUST_NB5:
+            /* Port 1 on these boards is always Gigabit */
+            if (ipd_port == 1)
+            {
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 1000;
+                return result;
+            }
+            else /* The other port uses a broadcom PHY */
+                is_broadcom_phy = 1;
+            break;
+        case CVMX_BOARD_TYPE_BBGW_REF:
+            /* Port 1 on these boards is always Gigabit */
+            if (ipd_port == 2)
+            {   
+                /* Port 2 is not hooked up */
+                result.u64 = 0;
+                return result;
+            }
+            else
+            {
+                /* Ports 0 and 1 connect to the switch */
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 1000;
+                return result;
+            }
+            break;
+    }
+
+    phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
+    if (phy_addr != -1)
+    {
+        if (is_broadcom_phy)
+        {
+            /* Below we are going to read SMI/MDIO register 0x19 which works
+                on Broadcom parts */
+            int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19);
+            switch ((phy_status>>8) & 0x7)
+            {
+                case 0:
+                    result.u64 = 0;
+                    break;
+                case 1:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 0;
+                    result.s.speed = 10;
+                    break;
+                case 2:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 1;
+                    result.s.speed = 10;
+                    break;
+                case 3:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 0;
+                    result.s.speed = 100;
+                    break;
+                case 4:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 1;
+                    result.s.speed = 100;
+                    break;
+                case 5:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 1;
+                    result.s.speed = 100;
+                    break;
+                case 6:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 0;
+                    result.s.speed = 1000;
+                    break;
+                case 7:
+                    result.s.link_up = 1;
+                    result.s.full_duplex = 1;
+                    result.s.speed = 1000;
+                    break;
+            }
+        }
+        else
+        {
+            /* This code assumes we are using a Marvell Gigabit PHY. All the
+                speed information can be read from register 17 in one go. Somebody
+                using a different PHY will need to handle it above in the board
+                specific area */
+            int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
+
+            /* If the resolve bit 11 isn't set, see if autoneg is turned off
+                (bit 12, reg 0). The resolve bit doesn't get set properly when
+                autoneg is off, so force it */
+            if ((phy_status & (1<<11)) == 0)
+            {
+                int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0);
+                if ((auto_status & (1<<12)) == 0)
+                    phy_status |= 1<<11;
+            }
+
+            /* Only return a link if the PHY has finished auto negotiation
+                and set the resolved bit (bit 11) */
+            if (phy_status & (1<<11))
+            {
+                result.s.link_up = 1;
+                result.s.full_duplex = ((phy_status>>13)&1);
+                switch ((phy_status>>14)&3)
+                {
+                    case 0: /* 10 Mbps */
+                        result.s.speed = 10;
+                        break;
+                    case 1: /* 100 Mbps */
+                        result.s.speed = 100;
+                        break;
+                    case 2: /* 1 Gbps */
+                        result.s.speed = 1000;
+                        break;
+                    case 3: /* Illegal */
+                        result.u64 = 0;
+                        break;
+                }
+            }
+        }
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        /* We don't have a PHY address, so attempt to use in-band status. It is
+            really important that boards not supporting in-band status never get
+            here. Reading broken in-band status tends to do bad things */
+        cvmx_gmxx_rxx_rx_inbnd_t inband_status;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
+
+        result.s.link_up = inband_status.s.status;
+        result.s.full_duplex = inband_status.s.duplex;
+        switch (inband_status.s.speed)
+        {
+            case 0: /* 10 Mbps */
+                result.s.speed = 10;
+                break;
+            case 1: /* 100 Mbps */
+                result.s.speed = 100;
+                break;
+            case 2: /* 1 Gbps */
+                result.s.speed = 1000;
+                break;
+            case 3: /* Illegal */
+                result.u64 = 0;
+                break;
+        }
+    }
+    else
+    {
+        /* We don't have a PHY address and we don't have in-band status. There
+            is no way to determine the link speed. Return down assuming this
+            port isn't wired */
+        result.u64 = 0;
+    }
+
+    /* If link is down, return all fields as zero. */
+    if (!result.s.link_up)
+        result.u64 = 0;
+
+    return result;
+}
+
+
+/**
+ * This function as a board specific method of changing the PHY
+ * speed, duplex, and auto-negotiation. This programs the PHY and
+ * not Octeon. This can be used to force Octeon's links to
+ * specific settings.
+ *
+ * @param phy_addr  The address of the PHY to program
+ * @param enable_autoneg
+ *                  Non zero if you want to enable auto-negotiation.
+ * @param link_info Link speed to program. If the speed is zero and auto-negotiation
+ *                  is enabled, all possible negotiation speeds are advertised.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_flags_types_t link_flags,
+                                   cvmx_helper_link_info_t link_info)
+{
+
+    /* Set the flow control settings based on link_flags */
+    if ((link_flags & set_phy_link_flags_flow_control_mask) != set_phy_link_flags_flow_control_dont_touch)
+    {
+        cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
+        reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
+        reg_autoneg_adver.s.asymmetric_pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable;
+        reg_autoneg_adver.s.pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable;
+        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16);
+    }
+
+    /* If speed isn't set and autoneg is on advertise all supported modes */
+    if ((link_flags & set_phy_link_flags_autoneg) && (link_info.s.speed == 0))
+    {
+        cvmx_mdio_phy_reg_control_t reg_control;
+        cvmx_mdio_phy_reg_status_t reg_status;
+        cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
+        cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
+        cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
+
+        reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
+        reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
+        reg_autoneg_adver.s.advert_100base_t4 = reg_status.s.capable_100base_t4;
+        reg_autoneg_adver.s.advert_10base_tx_full = reg_status.s.capable_10_full;
+        reg_autoneg_adver.s.advert_10base_tx_half = reg_status.s.capable_10_half;
+        reg_autoneg_adver.s.advert_100base_tx_full = reg_status.s.capable_100base_x_full;
+        reg_autoneg_adver.s.advert_100base_tx_half = reg_status.s.capable_100base_x_half;
+        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16);
+        if (reg_status.s.capable_extended_status)
+        {
+            reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
+            reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000);
+            reg_control_1000.s.advert_1000base_t_full = reg_extended_status.s.capable_1000base_t_full;
+            reg_control_1000.s.advert_1000base_t_half = reg_extended_status.s.capable_1000base_t_half;
+            cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16);
+        }
+        reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL);
+        reg_control.s.autoneg_enable = 1;
+        reg_control.s.restart_autoneg = 1;
+        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
+    }
+    else if ((link_flags & set_phy_link_flags_autoneg))
+    {
+        cvmx_mdio_phy_reg_control_t reg_control;
+        cvmx_mdio_phy_reg_status_t reg_status;
+        cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
+        cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
+        cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
+
+        reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
+        reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
+        reg_autoneg_adver.s.advert_100base_t4 = 0;
+        reg_autoneg_adver.s.advert_10base_tx_full = 0;
+        reg_autoneg_adver.s.advert_10base_tx_half = 0;
+        reg_autoneg_adver.s.advert_100base_tx_full = 0;
+        reg_autoneg_adver.s.advert_100base_tx_half = 0;
+        if (reg_status.s.capable_extended_status)
+        {
+            reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
+            reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000);
+            reg_control_1000.s.advert_1000base_t_full = 0;
+            reg_control_1000.s.advert_1000base_t_half = 0;
+        }
+        switch (link_info.s.speed)
+        {
+            case 10:
+                reg_autoneg_adver.s.advert_10base_tx_full = link_info.s.full_duplex;
+                reg_autoneg_adver.s.advert_10base_tx_half = !link_info.s.full_duplex;
+                break;
+            case 100:
+                reg_autoneg_adver.s.advert_100base_tx_full = link_info.s.full_duplex;
+                reg_autoneg_adver.s.advert_100base_tx_half = !link_info.s.full_duplex;
+                break;
+            case 1000:
+                reg_control_1000.s.advert_1000base_t_full = link_info.s.full_duplex;
+                reg_control_1000.s.advert_1000base_t_half = !link_info.s.full_duplex;
+                break;
+        }
+        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16);
+        if (reg_status.s.capable_extended_status)
+            cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16);
+        reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL);
+        reg_control.s.autoneg_enable = 1;
+        reg_control.s.restart_autoneg = 1;
+        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
+    }
+    else
+    {
+        cvmx_mdio_phy_reg_control_t reg_control;
+        reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL);
+        reg_control.s.autoneg_enable = 0;
+        reg_control.s.restart_autoneg = 1;
+        reg_control.s.duplex = link_info.s.full_duplex;
+        if (link_info.s.speed == 1000)
+        {
+            reg_control.s.speed_msb = 1;
+            reg_control.s.speed_lsb = 0;
+        }
+        else if (link_info.s.speed == 100)
+        {
+            reg_control.s.speed_msb = 0;
+            reg_control.s.speed_lsb = 1;
+        }
+        else if (link_info.s.speed == 10)
+        {
+            reg_control.s.speed_msb = 0;
+            reg_control.s.speed_lsb = 0;
+        }
+        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * This function is called by cvmx_helper_interface_probe() after it
+ * determines the number of ports Octeon can support on a specific
+ * interface. This function is the per board location to override
+ * this value. It is called with the number of ports Octeon might
+ * support and should return the number of actual ports on the
+ * board.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @param interface Interface to probe
+ * @param supported_ports
+ *                  Number of ports Octeon supports.
+ *
+ * @return Number of ports the actual board supports. Many times this will
+ *         simple be "support_ports".
+ */
+int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
+{
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+            if (interface == 0)
+                return 2;
+	    break;
+        case CVMX_BOARD_TYPE_BBGW_REF:
+            if (interface == 0)
+                return 2;
+	    break;
+        case CVMX_BOARD_TYPE_NIC_XLE_4G:
+            if (interface == 0)
+                return 0;
+	    break;
+        /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
+            which we don't support. Disable ports connected to it */
+        case CVMX_BOARD_TYPE_EBH5600:
+            if (interface == 1)
+                return 0;
+	    break;
+    }
+#ifdef CVMX_BUILD_FOR_UBOOT
+    if (CVMX_HELPER_INTERFACE_MODE_SPI == cvmx_helper_interface_get_mode(interface) && getenv("disable_spi"))
+        return 0;
+#endif
+    return supported_ports;
+}
+
+
+/**
+ * @INTERNAL
+ * Enable packet input/output from the hardware. This function is
+ * called after by cvmx_helper_packet_hardware_enable() to
+ * perform board specific initialization. For most boards
+ * nothing is needed.
+ *
+ * @param interface Interface to enable
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_board_hardware_enable(int interface)
+{
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5)
+    {
+        if (interface == 0)
+        {
+            /* Different config for switch port */
+            cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
+            cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
+            /* Boards with gigabit WAN ports need a different setting that is
+                compatible with 100 Mbit settings */
+            cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0xc);
+            cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0xc);
+        }
+    }
+    else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3010_EVB_HS5)
+    {
+        /* Broadcom PHYs require differnet ASX clocks. Unfortunately
+            many customer don't define a new board Id and simply
+            mangle the CN3010_EVB_HS5 */
+        if (interface == 0)
+        {
+            /* Some customers boards use a hacked up bootloader that identifies them as
+            ** CN3010_EVB_HS5 evaluation boards.  This leads to all kinds of configuration
+            ** problems.  Detect one case, and print warning, while trying to do the right thing.
+            */
+            int phy_addr = cvmx_helper_board_get_mii_address(0);
+            if (phy_addr != -1)
+            {
+                int phy_identifier = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x2);
+                /* Is it a Broadcom PHY? */
+                if (phy_identifier == 0x0143)
+                {
+                    cvmx_dprintf("\n");
+                    cvmx_dprintf("ERROR:\n");
+                    cvmx_dprintf("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
+                    cvmx_dprintf("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
+                    cvmx_dprintf("ERROR: All boards require a unique board type to identify them.\n");
+                    cvmx_dprintf("ERROR:\n");
+                    cvmx_dprintf("\n");
+                    cvmx_wait(1000000000);
+                    cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 5);
+                    cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 5);
+                }
+            }
+        }
+    }
+    return 0;
+}
+
+cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
+{
+    switch (cvmx_sysinfo_get()->board_type) {
+    case CVMX_BOARD_TYPE_BBGW_REF:
+            return USB_CLOCK_TYPE_CRYSTAL_12;
+    }
+    return USB_CLOCK_TYPE_REF_48;
+}
+
+int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
+{
+    switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_NIC_XLE_4G:
+            return 0;
+    }
+
+    return supported_ports;
+}
+
+
diff --git a/cvmx-helper-board.h b/cvmx-helper-board.h
new file mode 100644
index 0000000000000..fd07fc795fa6e
--- /dev/null
+++ b/cvmx-helper-board.h
@@ -0,0 +1,211 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper functions to abstract board specific data about
+ * network ports from the rest of the cvmx-helper files.
+ *
+ * <hr>$Revision: 41946 $<hr>
+ */
+#ifndef __CVMX_HELPER_BOARD_H__
+#define __CVMX_HELPER_BOARD_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+typedef enum {
+    USB_CLOCK_TYPE_REF_12,
+    USB_CLOCK_TYPE_REF_24,
+    USB_CLOCK_TYPE_REF_48,
+    USB_CLOCK_TYPE_CRYSTAL_12,
+} cvmx_helper_board_usb_clock_types_t;
+
+typedef enum {
+    set_phy_link_flags_autoneg                  = 0x1,
+    set_phy_link_flags_flow_control_dont_touch  = 0x0 << 1,
+    set_phy_link_flags_flow_control_enable      = 0x1 << 1,
+    set_phy_link_flags_flow_control_disable     = 0x2 << 1,
+    set_phy_link_flags_flow_control_mask        = 0x3 << 1,  /* Mask for 2 bit wide flow control field */
+} cvmx_helper_board_set_phy_link_flags_types_t;
+
+
+/**
+ * cvmx_override_board_link_get(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the process of
+ * talking to a PHY to determine link speed. It is called every
+ * time a PHY must be polled for link status. Users should set
+ * this pointer to a function before calling any cvmx-helper
+ * operations.
+ */
+extern cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port);
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. A result of -1 means there isn't a MII capable PHY
+ * connected to this port. On chips supporting multiple MII
+ * busses the bus number is encoded in bits <15:8>.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @param ipd_port Octeon IPD port to get the MII address for.
+ *
+ * @return MII PHY address and bus number or -1.
+ */
+extern int cvmx_helper_board_get_mii_address(int ipd_port);
+
+/**
+ * This function as a board specific method of changing the PHY
+ * speed, duplex, and autonegotiation. This programs the PHY and
+ * not Octeon. This can be used to force Octeon's links to
+ * specific settings.
+ *
+ * @param phy_addr  The address of the PHY to program
+ * @param link_flags
+ *                  Flags to control autonegotiation.  Bit 0 is autonegotiation
+ *                  enable/disable to maintain backware compatability.
+ * @param link_info Link speed to program. If the speed is zero and autonegotiation
+ *                  is enabled, all possible negotiation speeds are advertised.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_flags_types_t link_flags,
+                                   cvmx_helper_link_info_t link_info);
+
+/**
+ * @INTERNAL
+ * This function is the board specific method of determining an
+ * ethernet ports link speed. Most Octeon boards have Marvell PHYs
+ * and are handled by the fall through case. This function must be
+ * updated for boards that don't have the normal Marvell PHYs.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @param ipd_port IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * @return The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * This function is called by cvmx_helper_interface_probe() after it
+ * determines the number of ports Octeon can support on a specific
+ * interface. This function is the per board location to override
+ * this value. It is called with the number of ports Octeon might
+ * support and should return the number of actual ports on the
+ * board.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @param interface Interface to probe
+ * @param supported_ports
+ *                  Number of ports Octeon supports.
+ *
+ * @return Number of ports the actual board supports. Many times this will
+ *         simple be "support_ports".
+ */
+extern int __cvmx_helper_board_interface_probe(int interface, int supported_ports);
+
+/**
+ * @INTERNAL
+ * Enable packet input/output from the hardware. This function is
+ * called after by cvmx_helper_packet_hardware_enable() to
+ * perform board specific initialization. For most boards
+ * nothing is needed.
+ *
+ * @param interface Interface to enable
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_board_hardware_enable(int interface);
+
+
+
+
+/**
+ * @INTERNAL
+ * Gets the clock type used for the USB block based on board type.
+ * Used by the USB code for auto configuration of clock type.
+ *
+ * @return USB clock type enumeration
+ */
+cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void);
+
+
+/**
+ * @INTERNAL
+ * Adjusts the number of available USB ports on Octeon based on board
+ * specifics.
+ * 
+ * @param supported_ports expected number of ports based on chip type;
+ * 
+ *
+ * @return number of available usb ports, based on board specifics.
+ *         Return value is supported_ports if function does not
+ *         override.
+ */
+int __cvmx_helper_board_usb_get_num_ports(int supported_ports);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_HELPER_BOARD_H__ */
diff --git a/cvmx-helper-check-defines.h b/cvmx-helper-check-defines.h
new file mode 100644
index 0000000000000..7fd976bc25881
--- /dev/null
+++ b/cvmx-helper-check-defines.h
@@ -0,0 +1,102 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Validate defines required by cvmx-helper. This header file
+ * validates a number of defines required for cvmx-helper to
+ * function properly. It either supplies a default or fails
+ * compile if a define is incorrect.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_CHECK_DEFINES_H__
+#define __CVMX_HELPER_CHECK_DEFINES_H__
+
+/* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve before
+    the beginning of the packet. Override in executive-config.h */
+#ifndef CVMX_HELPER_FIRST_MBUFF_SKIP
+#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
+#warning WARNING: default CVMX_HELPER_FIRST_MBUFF_SKIP used.  Defaults deprecated, please set in executive-config.h
+#endif
+
+/* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve in each
+    chained packet element. Override in executive-config.h */
+#ifndef CVMX_HELPER_NOT_FIRST_MBUFF_SKIP
+#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
+#warning WARNING: default CVMX_HELPER_NOT_FIRST_MBUFF_SKIP used.  Defaults deprecated, please set in executive-config.h
+#endif
+
+/* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is enabled
+    for all input ports. Override in executive-config.h */
+#ifndef CVMX_HELPER_ENABLE_BACK_PRESSURE
+#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
+#warning WARNING: default CVMX_HELPER_ENABLE_BACK_PRESSURE used.  Defaults deprecated, please set in executive-config.h
+#endif
+
+/* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
+    function. Once it is enabled the hardware starts accepting packets. You
+    might want to skip the IPD enable if configuration changes are need
+    from the default helper setup. Override in executive-config.h */
+#ifndef CVMX_HELPER_ENABLE_IPD
+#define CVMX_HELPER_ENABLE_IPD 1
+#warning WARNING: default CVMX_HELPER_ENABLE_IPD used.  Defaults deprecated, please set in executive-config.h
+#endif
+
+/* Set default (defaults are deprecated) input tag type */
+#ifndef  CVMX_HELPER_INPUT_TAG_TYPE
+#define  CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
+#warning WARNING: default CVMX_HELPER_INPUT_TAG_TYPE used.  Defaults deprecated, please set in executive-config.h
+#endif
+
+#ifndef CVMX_HELPER_INPUT_PORT_SKIP_MODE
+#define CVMX_HELPER_INPUT_PORT_SKIP_MODE	CVMX_PIP_PORT_CFG_MODE_SKIPL2
+#warning WARNING: default CVMX_HELPER_INPUT_PORT_SKIP_MODE used.  Defaults deprecated, please set in executive-config.h
+#endif
+
+#if defined(CVMX_ENABLE_HELPER_FUNCTIONS) && !defined(CVMX_HELPER_INPUT_TAG_INPUT_PORT)
+#error CVMX_HELPER_INPUT_TAG_* values for determining tag hash inputs must be defined in executive-config.h
+#endif
+
+#endif
diff --git a/cvmx-helper-errata.c b/cvmx-helper-errata.c
new file mode 100644
index 0000000000000..16ecfb88fbb5c
--- /dev/null
+++ b/cvmx-helper-errata.c
@@ -0,0 +1,340 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Fixes and workaround for Octeon chip errata. This file
+ * contains functions called by cvmx-helper to workaround known
+ * chip errata. For the most part, code doesn't need to call
+ * these functions directly.
+ *
+ * <hr>$Revision: 42150 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+
+#include "cvmx.h"
+#include "cvmx-fpa.h"
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-ipd.h"
+#include "cvmx-asx.h"
+#include "cvmx-gmx.h"
+#include "cvmx-spi.h"
+#include "cvmx-pow.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+
+/**
+ * @INTERNAL
+ * Function to adjust internal IPD pointer alignments
+ *
+ * @return 0 on success
+ *         !0 on failure
+ */
+int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
+{
+#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES     (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP)
+#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
+#define FIX_IPD_OUTPORT 0
+#define INTERFACE(port) (port >> 4) /* Ports 0-15 are interface 0, 16-31 are interface 1 */
+#define INDEX(port) (port & 0xf)
+    uint64_t *p64;
+    cvmx_pko_command_word0_t    pko_command;
+    cvmx_buf_ptr_t              g_buffer, pkt_buffer;
+    cvmx_wqe_t *work;
+    int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
+    cvmx_gmxx_prtx_cfg_t gmx_cfg;
+    int retry_cnt;
+    int retry_loop_cnt;
+    int mtu;
+    int i;
+    cvmx_helper_link_info_t link_info;
+
+    /* Save values for restore at end */
+    uint64_t prtx_cfg = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+    uint64_t tx_ptr_en = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
+    uint64_t rx_ptr_en = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
+    uint64_t rxx_jabber = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+    uint64_t frame_max = cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+
+    /* Configure port to gig FDX as required for loopback mode */
+    cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
+
+    /* Disable reception on all ports so if traffic is present it will not interfere. */
+    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
+
+    cvmx_wait(100000000ull);
+
+    for (retry_loop_cnt = 0;retry_loop_cnt < 10;retry_loop_cnt++)
+    {
+        retry_cnt = 100000;
+        wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+        pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
+        wqe_pcnt &= 0x7f;
+
+        num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
+
+        if (num_segs == 0)
+            goto fix_ipd_exit;
+
+        num_segs += 1;
+
+        size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + ((num_segs-1)*FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
+            (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
+
+        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
+        CVMX_SYNC;
+
+        g_buffer.u64 = 0;
+        g_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
+        if (g_buffer.s.addr == 0) {
+            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
+            goto fix_ipd_exit;
+        }
+
+        g_buffer.s.pool = CVMX_FPA_WQE_POOL;
+        g_buffer.s.size = num_segs;
+
+        pkt_buffer.u64 = 0;
+        pkt_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
+        if (pkt_buffer.s.addr == 0) {
+            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
+            goto fix_ipd_exit;
+        }
+        pkt_buffer.s.i = 1;
+        pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
+        pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
+
+        p64 = (uint64_t*) cvmx_phys_to_ptr(pkt_buffer.s.addr);
+        p64[0] = 0xffffffffffff0000ull;
+        p64[1] = 0x08004510ull;
+        p64[2] = ((uint64_t)(size-14) << 48) | 0x5ae740004000ull;
+        p64[3] = 0x3a5fc0a81073c0a8ull;
+
+        for (i=0;i<num_segs;i++)
+        {
+            if (i>0)
+                pkt_buffer.s.size = FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
+
+            if (i==(num_segs-1))
+                pkt_buffer.s.i = 0;
+
+            *(uint64_t*)cvmx_phys_to_ptr(g_buffer.s.addr + 8*i) = pkt_buffer.u64;
+        }
+
+        /* Build the PKO command */
+        pko_command.u64 = 0;
+        pko_command.s.segs = num_segs;
+        pko_command.s.total_bytes = size;
+        pko_command.s.dontfree = 0;
+        pko_command.s.gather = 1;
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
+        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
+
+        mtu = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+        cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
+        cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
+
+        cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), CVMX_PKO_LOCK_CMD_QUEUE);
+        cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), pko_command, g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
+
+        CVMX_SYNC;
+
+        do {
+            work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
+            retry_cnt--;
+        } while ((work == NULL) && (retry_cnt > 0));
+
+        if (!retry_cnt)
+            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occured.\n");
+
+
+        /* Free packet */
+        if (work)
+            cvmx_helper_free_packet_data(work);
+    }
+
+fix_ipd_exit:
+
+    /* Return CSR configs to saved values */
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), prtx_cfg);
+    cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), tx_ptr_en);
+    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), rx_ptr_en);
+    cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), rxx_jabber);
+    cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), frame_max);
+    cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
+    link_info.u64 = 0;  /* Set link to down so autonegotiation will set it up again */
+    cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
+
+    /* Bring the link back up as autonegotiation is not done in user applications. */
+    cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
+
+    CVMX_SYNC;
+    if (num_segs)
+        cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
+
+    return(!!num_segs);
+
+}
+
+
+/**
+ * @INTERNAL
+ * Workaround ASX setup errata with CN38XX pass1
+ *
+ * @param interface Interface to setup
+ * @param port      Port to setup (0..3)
+ * @param cpu_clock_hz
+ *                  Chip frequency in Hertz
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
+{
+    /* Set hi water mark as per errata GMX-4 */
+    if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
+        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
+    else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
+        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
+    else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
+        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
+    else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
+        cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
+    else
+        cvmx_dprintf("Illegal clock frequency (%d). CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
+    return 0;
+}
+
+
+/**
+ * This function needs to be called on all Octeon chips with
+ * errata PKI-100.
+ *
+ * The Size field is 8 too large in WQE and next pointers
+ *
+ *  The Size field generated by IPD is 8 larger than it should
+ *  be. The Size field is <55:40> of both:
+ *      - WORD3 in the work queue entry, and
+ *      - the next buffer pointer (which precedes the packet data
+ *        in each buffer).
+ *
+ * @param work   Work queue entry to fix
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
+{
+    uint64_t number_buffers = work->word2.s.bufs;
+
+    /* We only need to do this if the work has buffers */
+    if (number_buffers)
+    {
+        cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
+        /* Check for errata PKI-100 */
+        if ( (buffer_ptr.s.pool == 0) && (((uint64_t)buffer_ptr.s.size +
+                 ((uint64_t)buffer_ptr.s.back << 7) + ((uint64_t)buffer_ptr.s.addr & 0x7F))
+                 != (CVMX_FPA_PACKET_POOL_SIZE+8))) {
+            /* fix is not needed */
+            return 0;
+        }
+        /* Decrement the work packet pointer */
+        buffer_ptr.s.size -= 8;
+        work->packet_ptr = buffer_ptr;
+
+        /* Now loop through decrementing the size for each additional buffer */
+        while (--number_buffers)
+        {
+            /* Chain pointers are 8 bytes before the data */
+            cvmx_buf_ptr_t *ptr = (cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+            buffer_ptr = *ptr;
+            buffer_ptr.s.size -= 8;
+            *ptr = buffer_ptr;
+        }
+    }
+    /* Make sure that these write go out before other operations such as FPA frees */
+    CVMX_SYNCWS;
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
+
+/**
+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
+ * 1 doesn't work properly. The following code disables 2nd order
+ * CDR for the specified QLM.
+ *
+ * @param qlm    QLM to disable 2nd order CDR for.
+ */
+void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
+{
+    int lane;
+    cvmx_helper_qlm_jtag_init();
+    /* We need to load all four lanes of the QLM, a total of 1072 bits */
+    for (lane=0; lane<4; lane++)
+    {
+        /* Each lane has 268 bits. We need to set cfg_cdr_incx<67:64>=3 and
+            cfg_cdr_secord<77>=1. All other bits are zero. Bits go in LSB
+            first, so start off with the zeros for bits <63:0> */
+        cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
+        /* cfg_cdr_incx<67:64>=3 */
+        cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
+        /* Zeros for bits <76:68> */
+        cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
+        /* cfg_cdr_secord<77>=1 */
+        cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
+        /* Zeros for bits <267:78> */
+        cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
+    }
+    cvmx_helper_qlm_jtag_update(qlm);
+}
+
diff --git a/cvmx-helper-errata.h b/cvmx-helper-errata.h
new file mode 100644
index 0000000000000..9982dd84792ee
--- /dev/null
+++ b/cvmx-helper-errata.h
@@ -0,0 +1,105 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Fixes and workaround for Octeon chip errata. This file
+ * contains functions called by cvmx-helper to workaround known
+ * chip errata. For the most part, code doesn't need to call
+ * these functions directly.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_ERRATA_H__
+#define __CVMX_HELPER_ERRATA_H__
+
+/**
+ * @INTERNAL
+ * Function to adjust internal IPD pointer alignments
+ *
+ * @return 0 on success
+ *         !0 on failure
+ */
+extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
+
+/**
+ * @INTERNAL
+ * Workaround ASX setup errata with CN38XX pass1
+ *
+ * @param interface Interface to setup
+ * @param port      Port to setup (0..3)
+ * @param cpu_clock_hz
+ *                  Chip frequency in Hertz
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz);
+
+/**
+ * This function needs to be called on all Octeon chips with
+ * errata PKI-100.
+ *
+ * The Size field is 8 too large in WQE and next pointers
+ *
+ *  The Size field generated by IPD is 8 larger than it should
+ *  be. The Size field is <55:40> of both:
+ *      - WORD3 in the work queue entry, and
+ *      - the next buffer pointer (which precedes the packet data
+ *        in each buffer).
+ *
+ * @param work   Work queue entry to fix
+ * @return Zero on success. Negative on failure
+ */
+extern int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work);
+
+/**
+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
+ * 1 doesn't work properly. The following code disables 2nd order
+ * CDR for the specified QLM.
+ *
+ * @param qlm    QLM to disable 2nd order CDR for.
+ */
+extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
+
+#endif
diff --git a/cvmx-helper-fpa.c b/cvmx-helper-fpa.c
new file mode 100644
index 0000000000000..0b91467c207c1
--- /dev/null
+++ b/cvmx-helper-fpa.c
@@ -0,0 +1,246 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper functions for FPA setup.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-fpa.h"
+#include "cvmx-helper-fpa.h"
+
+/**
+ * @INTERNAL
+ * Allocate memory for and initialize a single FPA pool.
+ *
+ * @param pool    Pool to initialize
+ * @param buffer_size  Size of buffers to allocate in bytes
+ * @param buffers Number of buffers to put in the pool. Zero is allowed
+ * @param name    String name of the pool for debugging purposes
+ * @return Zero on success, non-zero on failure
+ */
+static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
+                                           uint64_t buffers, const char *name)
+{
+    uint64_t current_num;
+    void *memory;
+    uint64_t align = CVMX_CACHE_LINE_SIZE;
+
+    /* Align the allocation so that power of 2 size buffers are naturally aligned */
+    while (align < buffer_size)
+        align = align << 1;
+
+    if (buffers == 0)
+        return 0;
+
+    current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool));
+    if (current_num)
+    {
+        cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. Skipping setup.\n",
+                     pool, name, (unsigned long long)current_num);
+        return 0;
+    }
+
+    memory = cvmx_bootmem_alloc(buffer_size * buffers, align);
+    if (memory == NULL)
+    {
+        cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", pool, name);
+        return -1;
+    }
+    cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers);
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Allocate memory and initialize the FPA pools using memory
+ * from cvmx-bootmem. Specifying zero for the number of
+ * buffers will cause that FPA pool to not be setup. This is
+ * useful if you aren't using some of the hardware and want
+ * to save memory. Use cvmx_helper_initialize_fpa instead of
+ * this function directly.
+ *
+ * @param pip_pool Should always be CVMX_FPA_PACKET_POOL
+ * @param pip_size Should always be CVMX_FPA_PACKET_POOL_SIZE
+ * @param pip_buffers
+ *                 Number of packet buffers.
+ * @param wqe_pool Should always be CVMX_FPA_WQE_POOL
+ * @param wqe_size Should always be CVMX_FPA_WQE_POOL_SIZE
+ * @param wqe_entries
+ *                 Number of work queue entries
+ * @param pko_pool Should always be CVMX_FPA_OUTPUT_BUFFER_POOL
+ * @param pko_size Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
+ * @param pko_buffers
+ *                 PKO Command buffers. You should at minimum have two per
+ *                 each PKO queue.
+ * @param tim_pool Should always be CVMX_FPA_TIMER_POOL
+ * @param tim_size Should always be CVMX_FPA_TIMER_POOL_SIZE
+ * @param tim_buffers
+ *                 TIM ring buffer command queues. At least two per timer bucket
+ *                 is recommened.
+ * @param dfa_pool Should always be CVMX_FPA_DFA_POOL
+ * @param dfa_size Should always be CVMX_FPA_DFA_POOL_SIZE
+ * @param dfa_buffers
+ *                 DFA command buffer. A relatively small (32 for example)
+ *                 number should work.
+ * @return Zero on success, non-zero if out of memory
+ */
+static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, int pip_buffers,
+                                        int wqe_pool, int wqe_size, int wqe_entries,
+                                        int pko_pool, int pko_size, int pko_buffers,
+                                        int tim_pool, int tim_size, int tim_buffers,
+                                        int dfa_pool, int dfa_size, int dfa_buffers)
+{
+    int status;
+
+    cvmx_fpa_enable();
+
+    if ((pip_buffers > 0) && (pip_buffers <= 64))
+        cvmx_dprintf("Warning: %d packet buffers may not be enough for hardware"
+                     " prefetch. 65 or more is recommended.\n", pip_buffers);
+
+    if (pip_pool >= 0)
+    {
+        status = __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, pip_buffers,
+                                                 "Packet Buffers");
+        if (status)
+            return status;
+    }
+
+    if (wqe_pool >= 0)
+    {
+        status = __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, wqe_entries,
+                                                 "Work Queue Entries");
+        if (status)
+            return status;
+    }
+
+    if (pko_pool >= 0)
+    {
+        status = __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, pko_buffers,
+                                                 "PKO Command Buffers");
+        if (status)
+            return status;
+    }
+
+    if (tim_pool >= 0)
+    {
+        status = __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, tim_buffers,
+                                                 "TIM Command Buffers");
+        if (status)
+            return status;
+    }
+
+    if (dfa_pool >= 0)
+    {
+        status = __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, dfa_buffers,
+                                                 "DFA Command Buffers");
+        if (status)
+            return status;
+    }
+
+    return 0;
+}
+
+
+/**
+ * Allocate memory and initialize the FPA pools using memory
+ * from cvmx-bootmem. Sizes of each element in the pools is
+ * controlled by the cvmx-config.h header file. Specifying
+ * zero for any parameter will cause that FPA pool to not be
+ * setup. This is useful if you aren't using some of the
+ * hardware and want to save memory.
+ *
+ * @param packet_buffers
+ *               Number of packet buffers to allocate
+ * @param work_queue_entries
+ *               Number of work queue entries
+ * @param pko_buffers
+ *               PKO Command buffers. You should at minimum have two per
+ *               each PKO queue.
+ * @param tim_buffers
+ *               TIM ring buffer command queues. At least two per timer bucket
+ *               is recommened.
+ * @param dfa_buffers
+ *               DFA command buffer. A relatively small (32 for example)
+ *               number should work.
+ * @return Zero on success, non-zero if out of memory
+ */
+int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
+                               int pko_buffers, int tim_buffers, int dfa_buffers)
+{
+#ifndef CVMX_FPA_PACKET_POOL
+#define CVMX_FPA_PACKET_POOL -1
+#define CVMX_FPA_PACKET_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_WQE_POOL
+#define CVMX_FPA_WQE_POOL -1
+#define CVMX_FPA_WQE_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL
+#define CVMX_FPA_OUTPUT_BUFFER_POOL -1
+#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_TIMER_POOL
+#define CVMX_FPA_TIMER_POOL -1
+#define CVMX_FPA_TIMER_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_DFA_POOL
+#define CVMX_FPA_DFA_POOL -1
+#define CVMX_FPA_DFA_POOL_SIZE 0
+#endif
+    return __cvmx_helper_initialize_fpa(
+        CVMX_FPA_PACKET_POOL,        CVMX_FPA_PACKET_POOL_SIZE,          packet_buffers,
+        CVMX_FPA_WQE_POOL,           CVMX_FPA_WQE_POOL_SIZE,             work_queue_entries,
+        CVMX_FPA_OUTPUT_BUFFER_POOL, CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,   pko_buffers,
+        CVMX_FPA_TIMER_POOL,         CVMX_FPA_TIMER_POOL_SIZE,           tim_buffers,
+        CVMX_FPA_DFA_POOL,           CVMX_FPA_DFA_POOL_SIZE,             dfa_buffers);
+}
+
diff --git a/cvmx-helper-fpa.h b/cvmx-helper-fpa.h
new file mode 100644
index 0000000000000..24f622afcd161
--- /dev/null
+++ b/cvmx-helper-fpa.h
@@ -0,0 +1,81 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper functions for FPA setup.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_H_FPA__
+#define __CVMX_HELPER_H_FPA__
+
+/**
+ * Allocate memory and initialize the FPA pools using memory
+ * from cvmx-bootmem. Sizes of each element in the pools is
+ * controlled by the cvmx-config.h header file. Specifying
+ * zero for any parameter will cause that FPA pool to not be
+ * setup. This is useful if you aren't using some of the
+ * hardware and want to save memory.
+ *
+ * @param packet_buffers
+ *               Number of packet buffers to allocate
+ * @param work_queue_entries
+ *               Number of work queue entries
+ * @param pko_buffers
+ *               PKO Command buffers. You should at minimum have two per
+ *               each PKO queue.
+ * @param tim_buffers
+ *               TIM ring buffer command queues. At least two per timer bucket
+ *               is recommened.
+ * @param dfa_buffers
+ *               DFA command buffer. A relatively small (32 for example)
+ *               number should work.
+ * @return Zero on success, non-zero if out of memory
+ */
+extern int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
+                                      int pko_buffers, int tim_buffers,
+                                      int dfa_buffers);
+
+#endif  /* __CVMX_HELPER_H__ */
diff --git a/cvmx-helper-loop.c b/cvmx-helper-loop.c
new file mode 100644
index 0000000000000..768d85508c752
--- /dev/null
+++ b/cvmx-helper-loop.c
@@ -0,0 +1,113 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for LOOP initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-helper.h"
+
+
+/**
+ * @INTERNAL
+ * Probe a LOOP interface and determine the number of ports
+ * connected to it. The LOOP interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_loop_probe(int interface)
+{
+    cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
+    int num_ports = 4;
+    int port;
+
+    /* We need to disable length checking so packet < 64 bytes and jumbo
+        frames don't get errors */
+    for (port=0; port<num_ports; port++)
+    {
+        cvmx_pip_port_cfg_t port_cfg;
+        int ipd_port = cvmx_helper_get_ipd_port(interface, port);
+        port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+        port_cfg.s.maxerr_en = 0;
+        port_cfg.s.minerr_en = 0;
+        cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
+    }
+
+    /* Disable FCS stripping for loopback ports */
+    ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+    ipd_sub_port_fcs.s.port_bit2 = 0;
+    cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+    return num_ports;
+}
+
+
+/**
+ * @INTERNAL
+ * Bringup and enable a LOOP interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_loop_enable(int interface)
+{
+    /* Do nothing. */
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/cvmx-helper-loop.h b/cvmx-helper-loop.h
new file mode 100644
index 0000000000000..42b2e15bc938b
--- /dev/null
+++ b/cvmx-helper-loop.h
@@ -0,0 +1,80 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for LOOP initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_LOOP_H__
+#define __CVMX_HELPER_LOOP_H__
+
+/**
+ * @INTERNAL
+ * Probe a LOOP interface and determine the number of ports
+ * connected to it. The LOOP interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_loop_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a LOOP interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_loop_enable(int interface);
+
+#endif
+
diff --git a/cvmx-helper-npi.c b/cvmx-helper-npi.c
new file mode 100644
index 0000000000000..f2a4f50bbba6f
--- /dev/null
+++ b/cvmx-helper-npi.c
@@ -0,0 +1,126 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for NPI initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-helper.h"
+
+
+/**
+ * @INTERNAL
+ * Probe a NPI interface and determine the number of ports
+ * connected to it. The NPI interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_npi_probe(int interface)
+{
+#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        return 4;
+    else if (OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+        return 4; /* The packet engines didn't exist before pass 2 */
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+        return 4; /* The packet engines didn't exist before pass 2 */
+#if 0
+    /* Technically CN30XX, CN31XX, and CN50XX contain packet engines, but
+        nobody ever uses them. Since this is the case, we disable them here */
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+        return 2;
+    else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+        return 1;
+#endif
+#endif
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Bringup and enable a NPI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_npi_enable(int interface)
+{
+    /* On CN50XX, CN52XX, and CN56XX we need to disable length checking
+        so packet < 64 bytes and jumbo frames don't get errors */
+    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && !OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        int num_ports = cvmx_helper_ports_on_interface(interface);
+        int port;
+        for (port=0; port<num_ports; port++)
+        {
+            cvmx_pip_port_cfg_t port_cfg;
+            int ipd_port = cvmx_helper_get_ipd_port(interface, port);
+            port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+            port_cfg.s.maxerr_en = 0;
+            port_cfg.s.minerr_en = 0;
+            cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
+        }
+    }
+
+    /* Enables are controlled by the remote host, so nothing to do here */
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/cvmx-helper-npi.h b/cvmx-helper-npi.h
new file mode 100644
index 0000000000000..c249e07c2b475
--- /dev/null
+++ b/cvmx-helper-npi.h
@@ -0,0 +1,80 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for NPI initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_NPI_H__
+#define __CVMX_HELPER_NPI_H__
+
+/**
+ * @INTERNAL
+ * Probe a NPI interface and determine the number of ports
+ * connected to it. The NPI interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_npi_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a NPI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_npi_enable(int interface);
+
+#endif
+
diff --git a/cvmx-helper-rgmii.c b/cvmx-helper-rgmii.c
new file mode 100644
index 0000000000000..95bf58968f27f
--- /dev/null
+++ b/cvmx-helper-rgmii.c
@@ -0,0 +1,507 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for RGMII/GMII/MII initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 42417 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-mdio.h"
+#include "cvmx-pko.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+
+/**
+ * @INTERNAL
+ * Probe RGMII ports and determine the number present
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of RGMII/GMII/MII ports (0-4).
+ */
+int __cvmx_helper_rgmii_probe(int interface)
+{
+    int num_ports = 0;
+    cvmx_gmxx_inf_mode_t mode;
+    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+    if (mode.s.type)
+    {
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        {
+            cvmx_dprintf("ERROR: RGMII initialize called in SPI interface\n");
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+        {
+            /* On these chips "type" says we're in GMII/MII mode. This
+                limits us to 2 ports */
+            num_ports = 2;
+        }
+        else
+        {
+            cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", __FUNCTION__);
+        }
+    }
+    else
+    {
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        {
+            num_ports = 4;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+        {
+            num_ports = 3;
+        }
+        else
+        {
+            cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", __FUNCTION__);
+        }
+    }
+    return num_ports;
+}
+
+
+/**
+ * Put an RGMII interface in loopback mode. Internal packets sent
+ * out will be received back again on the same port. Externally
+ * received packets will echo back out.
+ *
+ * @param port   IPD port number to loop.
+ */
+void cvmx_helper_rgmii_internal_loopback(int port)
+{
+    int interface = (port >> 4) & 1;
+    int index = port & 0xf;
+    uint64_t tmp;
+
+    cvmx_gmxx_prtx_cfg_t gmx_cfg;
+    gmx_cfg.u64 = 0;
+    gmx_cfg.s.duplex = 1;
+    gmx_cfg.s.slottime = 1;
+    gmx_cfg.s.speed = 1;
+    cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+    cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
+    cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+    tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
+    cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
+    tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
+    cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
+    tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
+    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
+    gmx_cfg.s.en = 1;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+}
+
+
+/**
+ * @INTERNAL
+ * Configure all of the ASX, GMX, and PKO regsiters required
+ * to get RGMII to function on the supplied interface.
+ *
+ * @param interface PKO Interface to configure (0 or 1)
+ *
+ * @return Zero on success
+ */
+int __cvmx_helper_rgmii_enable(int interface)
+{
+    int num_ports = cvmx_helper_ports_on_interface(interface);
+    int port;
+    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+    cvmx_gmxx_inf_mode_t mode;
+    cvmx_asxx_tx_prt_en_t asx_tx;
+    cvmx_asxx_rx_prt_en_t asx_rx;
+
+    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+    if (mode.s.en == 0)
+        return -1;
+    if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)   /* Ignore SPI interfaces */
+        return -1;
+
+    /* Configure the ASX registers needed to use the RGMII ports */
+    asx_tx.u64 = 0;
+    asx_tx.s.prt_en = cvmx_build_mask(num_ports);
+    cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
+
+    asx_rx.u64 = 0;
+    asx_rx.s.prt_en = cvmx_build_mask(num_ports);
+    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
+
+    /* Configure the GMX registers needed to use the RGMII ports */
+    for (port=0; port<num_ports; port++)
+    {
+        /* Setting of CVMX_GMXX_TXX_THRESH has been moved to
+            __cvmx_helper_setup_gmx() */
+
+        if (cvmx_octeon_is_pass1())
+            __cvmx_helper_errata_asx_pass1(interface, port, sys_info_ptr->cpu_clock_hz);
+        else
+        {
+            /* Configure more flexible RGMII preamble checking. Pass 1 doesn't
+                support this feature. */
+            cvmx_gmxx_rxx_frm_ctl_t frm_ctl;
+            frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface));
+            frm_ctl.s.pre_free = 1;  /* New field, so must be compile time */
+            cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64);
+        }
+
+        /* Each pause frame transmitted will ask for about 10M bit times
+            before resume.  If buffer space comes available before that time
+            has expired, an XON pause frame (0 time) will be transmitted to
+            restart the flow. */
+        cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), 20000);
+        cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(port, interface), 19000);
+
+        if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+        {
+            cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 16);
+            cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 16);
+        }
+        else
+        {
+            cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 24);
+            cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 24);
+        }
+    }
+
+    __cvmx_helper_setup_gmx(interface, num_ports);
+
+    /* enable the ports now */
+    for (port=0; port<num_ports; port++)
+    {
+        cvmx_gmxx_prtx_cfg_t gmx_cfg;
+        cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, port));
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), gmx_cfg.u64);
+    }
+
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    cvmx_asxx_prt_loop_t asxx_prt_loop;
+
+    asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
+    if (asxx_prt_loop.s.int_loop & (1<<index))
+    {
+        /* Force 1Gbps full duplex on internal loopback */
+        cvmx_helper_link_info_t result;
+        result.u64 = 0;
+        result.s.full_duplex = 1;
+        result.s.link_up = 1;
+        result.s.speed = 1000;
+        return result;
+    }
+    else
+        return __cvmx_helper_board_link_get(ipd_port);
+}
+
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    int result = 0;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    cvmx_gmxx_prtx_cfg_t original_gmx_cfg;
+    cvmx_gmxx_prtx_cfg_t new_gmx_cfg;
+    cvmx_pko_mem_queue_qos_t pko_mem_queue_qos;
+    cvmx_pko_mem_queue_qos_t pko_mem_queue_qos_save[16];
+    cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp;
+    cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp_save;
+    int i;
+
+    /* Ignore speed sets in the simulator */
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+        return 0;
+
+    /* Read the current settings so we know the current enable state */
+    original_gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+    new_gmx_cfg = original_gmx_cfg;
+
+    /* Disable the lowest level RX */
+    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
+                   cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & ~(1<<index));
+
+    /* Disable all queues so that TX should become idle */
+    for (i=0; i<cvmx_pko_get_num_queues(ipd_port); i++)
+    {
+        int queue = cvmx_pko_get_base_queue(ipd_port) + i;
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
+        pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);
+        pko_mem_queue_qos.s.pid = ipd_port;
+        pko_mem_queue_qos.s.qid = queue;
+        pko_mem_queue_qos_save[i] = pko_mem_queue_qos;
+        pko_mem_queue_qos.s.qos_mask = 0;
+        cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
+    }
+
+    /* Disable backpressure */
+    gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
+    gmx_tx_ovr_bp_save = gmx_tx_ovr_bp;
+    gmx_tx_ovr_bp.s.bp &= ~(1<<index);
+    gmx_tx_ovr_bp.s.en |= 1<<index;
+    cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
+    cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
+
+    /* Poll the GMX state machine waiting for it to become idle. Preferably we
+        should only change speed when it is idle. If it doesn't become idle we
+        will still do the speed change, but there is a slight chance that GMX
+        will lockup */
+    cvmx_write_csr(CVMX_NPI_DBG_SELECT, interface*0x800 + index*0x100 + 0x880);
+    CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, cvmx_dbg_data_t, data&7, ==, 0, 10000);
+    CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, cvmx_dbg_data_t, data&0xf, ==, 0, 10000);
+
+    /* Disable the port before we make any changes */
+    new_gmx_cfg.s.en = 0;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
+    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+    /* Set full/half duplex */
+    if (cvmx_octeon_is_pass1())
+        new_gmx_cfg.s.duplex = 1;   /* Half duplex is broken for 38XX Pass 1 */
+    else if (!link_info.s.link_up)
+        new_gmx_cfg.s.duplex = 1;   /* Force full duplex on down links */
+    else
+        new_gmx_cfg.s.duplex = link_info.s.full_duplex;
+
+    /* Set the link speed. Anything unknown is set to 1Gbps */
+    if (link_info.s.speed == 10)
+    {
+        new_gmx_cfg.s.slottime = 0;
+        new_gmx_cfg.s.speed = 0;
+    }
+    else if (link_info.s.speed == 100)
+    {
+        new_gmx_cfg.s.slottime = 0;
+        new_gmx_cfg.s.speed = 0;
+    }
+    else
+    {
+        new_gmx_cfg.s.slottime = 1;
+        new_gmx_cfg.s.speed = 1;
+    }
+
+    /* Adjust the clocks */
+    if (link_info.s.speed == 10)
+    {
+        cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
+        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
+        cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+    }
+    else if (link_info.s.speed == 100)
+    {
+        cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
+        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
+        cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+    }
+    else
+    {
+        cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
+        cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
+    }
+
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        if ((link_info.s.speed == 10) || (link_info.s.speed == 100))
+        {
+            cvmx_gmxx_inf_mode_t mode;
+            mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+            /*
+            ** Port  .en  .type  .p0mii  Configuration
+            ** ----  ---  -----  ------  -----------------------------------------
+            **  X      0     X      X    All links are disabled.
+            **  0      1     X      0    Port 0 is RGMII
+            **  0      1     X      1    Port 0 is MII
+            **  1      1     0      X    Ports 1 and 2 are configured as RGMII ports.
+            **  1      1     1      X    Port 1: GMII/MII; Port 2: disabled. GMII or
+            **                           MII port is selected by GMX_PRT1_CFG[SPEED].
+            */
+
+            /* In MII mode, CLK_CNT = 1. */
+            if (((index == 0) && (mode.s.p0mii == 1)) || ((index != 0) && (mode.s.type == 1)))
+            {
+                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+            }
+        }
+    }
+
+    /* Do a read to make sure all setup stuff is complete */
+    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+    /* Save the new GMX setting without enabling the port */
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
+
+    /* Enable the lowest level RX */
+    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
+                   cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1<<index));
+
+    /* Re-enable the TX path */
+    for (i=0; i<cvmx_pko_get_num_queues(ipd_port); i++)
+    {
+        int queue = cvmx_pko_get_base_queue(ipd_port) + i;
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
+        cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos_save[i].u64);
+    }
+
+    /* Restore backpressure */
+    cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
+
+    /* Restore the GMX enable state. Port config is complete */
+    new_gmx_cfg.s.en = original_gmx_cfg.s.en;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
+
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    int original_enable;
+    cvmx_gmxx_prtx_cfg_t gmx_cfg;
+    cvmx_asxx_prt_loop_t asxx_prt_loop;
+
+    /* Read the current enable state and save it */
+    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+    original_enable = gmx_cfg.s.en;
+    /* Force port to be disabled */
+    gmx_cfg.s.en = 0;
+    if (enable_internal)
+    {
+        /* Force speed if we're doing internal loopback */
+        gmx_cfg.s.duplex = 1;
+        gmx_cfg.s.slottime = 1;
+        gmx_cfg.s.speed = 1;
+        cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
+        cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
+    }
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+
+    /* Set the loopback bits */
+    asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
+    if (enable_internal)
+        asxx_prt_loop.s.int_loop |= 1<<index;
+    else
+        asxx_prt_loop.s.int_loop &= ~(1<<index);
+    if (enable_external)
+        asxx_prt_loop.s.ext_loop |= 1<<index;
+    else
+        asxx_prt_loop.s.ext_loop &= ~(1<<index);
+    cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
+
+    /* Force enables in internal loopback */
+    if (enable_internal)
+    {
+        uint64_t tmp;
+        tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
+        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
+        tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
+        original_enable = 1;
+    }
+
+    /* Restore the enable state */
+    gmx_cfg.s.en = original_enable;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/cvmx-helper-rgmii.h b/cvmx-helper-rgmii.h
new file mode 100644
index 0000000000000..2560adc7b64c4
--- /dev/null
+++ b/cvmx-helper-rgmii.h
@@ -0,0 +1,129 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for RGMII/GMII/MII initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_RGMII_H__
+#define __CVMX_HELPER_RGMII_H__
+
+/**
+ * @INTERNAL
+ * Probe RGMII ports and determine the number present
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of RGMII/GMII/MII ports (0-4).
+ */
+extern int __cvmx_helper_rgmii_probe(int interface);
+
+/**
+ * Put an RGMII interface in loopback mode. Internal packets sent
+ * out will be received back again on the same port. Externally
+ * received packets will echo back out.
+ *
+ * @param port   IPD port number to loop.
+ */
+extern void cvmx_helper_rgmii_internal_loopback(int port);
+
+/**
+ * @INTERNAL
+ * Configure all of the ASX, GMX, and PKO regsiters required
+ * to get RGMII to function on the supplied interface.
+ *
+ * @param interface PKO Interface to configure (0 or 1)
+ *
+ * @return Zero on success
+ */
+extern int __cvmx_helper_rgmii_enable(int interface);
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_rgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+/**
+ * @INTERNAL
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external);
+
+#endif
diff --git a/cvmx-helper-sgmii.c b/cvmx-helper-sgmii.c
new file mode 100644
index 0000000000000..4465ecc34d423
--- /dev/null
+++ b/cvmx-helper-sgmii.c
@@ -0,0 +1,523 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for SGMII initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 42417 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-mdio.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+
+
+/**
+ * @INTERNAL
+ * Perform initialization required only once for an SGMII port.
+ *
+ * @param interface Interface to init
+ * @param index     Index of prot on the interface
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
+{
+    const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+    cvmx_pcsx_miscx_ctl_reg_t pcs_misc_ctl_reg;
+    cvmx_pcsx_linkx_timer_count_reg_t pcsx_linkx_timer_count_reg;
+    cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
+
+    /* Disable GMX */
+    gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+    gmxx_prtx_cfg.s.en = 0;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+    /* Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the appropriate
+        value. 1000BASE-X specifies a 10ms interval. SGMII specifies a 1.6ms
+        interval. */
+    pcs_misc_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+    pcsx_linkx_timer_count_reg.u64 = cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
+    if (pcs_misc_ctl_reg.s.mode)
+    {
+        /* 1000BASE-X */
+        pcsx_linkx_timer_count_reg.s.count = (10000ull * clock_mhz) >> 10;
+    }
+    else
+    {
+        /* SGMII */
+        pcsx_linkx_timer_count_reg.s.count = (1600ull * clock_mhz) >> 10;
+    }
+    cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), pcsx_linkx_timer_count_reg.u64);
+
+    /* Write the advertisement register to be used as the
+        tx_Config_Reg<D15:D0> of the autonegotiation.
+        In 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG.
+        In SGMII PHY mode, tx_Config_Reg<D15:D0> is PCS*_SGM*_AN_ADV_REG.
+        In SGMII MAC mode, tx_Config_Reg<D15:D0> is the fixed value 0x4001, so
+        this step can be skipped. */
+    if (pcs_misc_ctl_reg.s.mode)
+    {
+        /* 1000BASE-X */
+        cvmx_pcsx_anx_adv_reg_t pcsx_anx_adv_reg;
+        pcsx_anx_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
+        pcsx_anx_adv_reg.s.rem_flt = 0;
+        pcsx_anx_adv_reg.s.pause = 3;
+        pcsx_anx_adv_reg.s.hfd = 1;
+        pcsx_anx_adv_reg.s.fd = 1;
+        cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), pcsx_anx_adv_reg.u64);
+    }
+    else
+    {
+        cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
+        pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+        if (pcsx_miscx_ctl_reg.s.mac_phy)
+        {
+            /* PHY Mode */
+            cvmx_pcsx_sgmx_an_adv_reg_t pcsx_sgmx_an_adv_reg;
+            pcsx_sgmx_an_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface));
+            pcsx_sgmx_an_adv_reg.s.link = 1;
+            pcsx_sgmx_an_adv_reg.s.dup = 1;
+            pcsx_sgmx_an_adv_reg.s.speed= 2;
+            cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface), pcsx_sgmx_an_adv_reg.u64);
+        }
+        else
+        {
+            /* MAC Mode - Nothing to do */
+        }
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Initialize the SERTES link for the first time or after a loss
+ * of link.
+ *
+ * @param interface Interface to init
+ * @param index     Index of prot on the interface
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
+{
+    cvmx_pcsx_mrx_control_reg_t control_reg;
+
+    /* Take PCS through a reset sequence.
+        PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero.
+        Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the value of
+            the other PCS*_MR*_CONTROL_REG bits).
+        Read PCS*_MR*_CONTROL_REG[RESET] until it changes value to zero. */
+    control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+    {
+        control_reg.s.reset = 1;
+        cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_CONTROL_REG(index, interface), cvmx_pcsx_mrx_control_reg_t, reset, ==, 0, 10000))
+        {
+            cvmx_dprintf("SGMII%d: Timeout waiting for port %d to finish reset\n", interface, index);
+            return -1;
+        }
+    }
+
+    /* Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh sgmii negotiation starts. */
+    control_reg.s.rst_an = 1;
+    control_reg.s.an_en = 1;
+    control_reg.s.pwr_dn = 0;
+    cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64);
+
+    /* Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating that
+        sgmii autonegotiation is complete. In MAC mode this isn't an ethernet
+        link, but a link between Octeon and the PHY */
+    if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+        CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), cvmx_pcsx_mrx_status_reg_t, an_cpt, ==, 1, 10000))
+    {
+        //cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index);
+        return -1;
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Configure an SGMII link to the specified speed after the SERTES
+ * link is up.
+ *
+ * @param interface Interface to init
+ * @param index     Index of prot on the interface
+ * @param link_info Link state to configure
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index, cvmx_helper_link_info_t link_info)
+{
+    int is_enabled;
+    cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
+    cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
+
+    /* Disable GMX before we make any changes. Remember the enable state */
+    gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+    is_enabled = gmxx_prtx_cfg.s.en;
+    gmxx_prtx_cfg.s.en = 0;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+    /* Wait for GMX to be idle */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000) ||
+        CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
+    {
+        cvmx_dprintf("SGMII%d: Timeout waiting for port %d to be idle\n", interface, index);
+        return -1;
+    }
+
+    /* Read GMX CFG again to make sure the disable completed */
+    gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+    /* Get the misc control for PCS. We will need to set the duplication amount */
+    pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+
+    /* Use GMXENO to force the link down if the status we get says it should be down */
+    pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up;
+
+    /* Only change the duplex setting if the link is up */
+    if (link_info.s.link_up)
+        gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex;
+
+    /* Do speed based setting for GMX */
+    switch (link_info.s.speed)
+    {
+        case 10:
+            gmxx_prtx_cfg.s.speed = 0;
+            gmxx_prtx_cfg.s.speed_msb = 1;
+            gmxx_prtx_cfg.s.slottime = 0;
+            pcsx_miscx_ctl_reg.s.samp_pt = 25; /* Setting from GMX-603 */
+            cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
+            cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+            break;
+        case 100:
+            gmxx_prtx_cfg.s.speed = 0;
+            gmxx_prtx_cfg.s.speed_msb = 0;
+            gmxx_prtx_cfg.s.slottime = 0;
+            pcsx_miscx_ctl_reg.s.samp_pt = 0x5;
+            cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
+            cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+            break;
+        case 1000:
+            gmxx_prtx_cfg.s.speed = 1;
+            gmxx_prtx_cfg.s.speed_msb = 0;
+            gmxx_prtx_cfg.s.slottime = 1;
+            pcsx_miscx_ctl_reg.s.samp_pt = 1;
+            cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
+            cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
+            break;
+        default:
+            break;
+    }
+
+    /* Write the new misc control for PCS */
+    cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
+
+    /* Write the new GMX settings with the port still disabled */
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+    /* Read GMX CFG again to make sure the config completed */
+    gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+    /* Restore the enabled / disabled state */
+    gmxx_prtx_cfg.s.en = is_enabled;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Bring up the SGMII interface to be ready for packet I/O but
+ * leave I/O disabled using the GMX override. This function
+ * follows the bringup documented in 10.6.3 of the manual.
+ *
+ * @param interface Interface to bringup
+ * @param num_ports Number of ports on the interface
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
+{
+    int index;
+
+    __cvmx_helper_setup_gmx(interface, num_ports);
+
+    for (index=0; index<num_ports; index++)
+    {
+        int ipd_port = cvmx_helper_get_ipd_port(interface, index);
+        __cvmx_helper_sgmii_hardware_init_one_time(interface, index);
+        __cvmx_helper_sgmii_link_set(ipd_port, __cvmx_helper_sgmii_link_get(ipd_port));
+
+    }
+
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Probe a SGMII interface and determine the number of ports
+ * connected to it. The SGMII interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_sgmii_probe(int interface)
+{
+    cvmx_gmxx_inf_mode_t mode;
+
+    /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
+        needs to be enabled before IPD otherwise per port backpressure
+        may not work properly */
+    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+    mode.s.en = 1;
+    cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
+    return 4;
+}
+
+
+/**
+ * @INTERNAL
+ * Bringup and enable a SGMII interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_sgmii_enable(int interface)
+{
+    int num_ports = cvmx_helper_ports_on_interface(interface);
+    int index;
+
+    __cvmx_helper_sgmii_hardware_init(interface, num_ports);
+
+    for (index=0; index<num_ports; index++)
+    {
+        cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
+        gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmxx_prtx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
+{
+    cvmx_helper_link_info_t result;
+    cvmx_pcsx_miscx_ctl_reg_t pcs_misc_ctl_reg;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    cvmx_pcsx_mrx_control_reg_t pcsx_mrx_control_reg;
+
+    result.u64 = 0;
+
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+        /* The simulator gives you a simulated 1Gbps full duplex link */
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 1000;
+        return result;
+    }
+
+    pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+    if (pcsx_mrx_control_reg.s.loopbck1)
+    {
+        /* Force 1Gbps full duplex link for internal loopback */
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 1000;
+        return result;
+    }
+
+
+    pcs_misc_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+    if (pcs_misc_ctl_reg.s.mode)
+    {
+        /* 1000BASE-X */
+        // FIXME
+    }
+    else
+    {
+        cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
+        pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+        if (pcsx_miscx_ctl_reg.s.mac_phy)
+        {
+            /* PHY Mode */
+            cvmx_pcsx_mrx_status_reg_t pcsx_mrx_status_reg;
+            cvmx_pcsx_anx_results_reg_t pcsx_anx_results_reg;
+
+            /* Don't bother continuing if the SERTES low level link is down */
+            pcsx_mrx_status_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface));
+            if (pcsx_mrx_status_reg.s.lnk_st == 0)
+            {
+                if (__cvmx_helper_sgmii_hardware_init_link(interface, index) != 0)
+                    return result;
+            }
+
+            /* Read the autoneg results */
+            pcsx_anx_results_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface));
+            if (pcsx_anx_results_reg.s.an_cpt)
+            {
+                /* Auto negotiation is complete. Set status accordingly */
+                result.s.full_duplex = pcsx_anx_results_reg.s.dup;
+                result.s.link_up = pcsx_anx_results_reg.s.link_ok;
+                switch (pcsx_anx_results_reg.s.spd)
+                {
+                    case 0:
+                        result.s.speed = 10;
+                        break;
+                    case 1:
+                        result.s.speed = 100;
+                        break;
+                    case 2:
+                        result.s.speed = 1000;
+                        break;
+                    default:
+                        result.s.speed = 0;
+                        result.s.link_up = 0;
+                        break;
+                }
+            }
+            else
+            {
+                /* Auto negotiation isn't complete. Return link down */
+                result.s.speed = 0;
+                result.s.link_up = 0;
+            }
+        }
+        else /* MAC Mode */
+        {
+            result = __cvmx_helper_board_link_get(ipd_port);
+        }
+    }
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_sgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    __cvmx_helper_sgmii_hardware_init_link(interface, index);
+    return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, link_info);
+}
+
+/**
+ * @INTERNAL
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    cvmx_pcsx_mrx_control_reg_t pcsx_mrx_control_reg;
+    cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
+
+    pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+    pcsx_mrx_control_reg.s.loopbck1 = enable_internal;
+    cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), pcsx_mrx_control_reg.u64);
+
+    pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+    pcsx_miscx_ctl_reg.s.loopbck2 = enable_external;
+    cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64);
+
+    __cvmx_helper_sgmii_hardware_init_link(interface, index);
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
diff --git a/cvmx-helper-sgmii.h b/cvmx-helper-sgmii.h
new file mode 100644
index 0000000000000..3ff1672477f4d
--- /dev/null
+++ b/cvmx-helper-sgmii.h
@@ -0,0 +1,123 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for SGMII initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_SGMII_H__
+#define __CVMX_HELPER_SGMII_H__
+
+/**
+ * @INTERNAL
+ * Probe a SGMII interface and determine the number of ports
+ * connected to it. The SGMII interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_sgmii_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a SGMII interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_sgmii_enable(int interface);
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_sgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+/**
+ * @INTERNAL
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external);
+
+#endif
diff --git a/cvmx-helper-spi.c b/cvmx-helper-spi.c
new file mode 100644
index 0000000000000..d2138af678599
--- /dev/null
+++ b/cvmx-helper-spi.c
@@ -0,0 +1,219 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for SPI initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 42417 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-spi.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+
+/* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
+    routines wait for SPI training. You can override the value using
+    executive-config.h if necessary */
+#ifndef CVMX_HELPER_SPI_TIMEOUT
+#define CVMX_HELPER_SPI_TIMEOUT 10
+#endif
+
+
+/**
+ * @INTERNAL
+ * Probe a SPI interface and determine the number of ports
+ * connected to it. The SPI interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_spi_probe(int interface)
+{
+    int num_ports = 0;
+
+    if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+        cvmx_spi4000_is_present(interface))
+    {
+        num_ports = 10;
+    }
+    else
+    {
+        cvmx_pko_reg_crc_enable_t enable;
+        num_ports = 16;
+        /* Unlike the SPI4000, most SPI devices don't automatically
+            put on the L2 CRC. For everything except for the SPI4000
+            have PKO append the L2 CRC to the packet */
+        enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
+        enable.s.enable |= 0xffff << (interface*16);
+        cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
+    }
+    __cvmx_helper_setup_gmx(interface, num_ports);
+    return num_ports;
+}
+
+
+/**
+ * @INTERNAL
+ * Bringup and enable a SPI interface. After this call packet I/O
+ * should be fully functional. This is called with IPD enabled but
+ * PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_spi_enable(int interface)
+{
+    /* Normally the ethernet L2 CRC is checked and stripped in the GMX block.
+        When you are using SPI, this isn' the case and IPD needs to check
+        the L2 CRC */
+    int num_ports = cvmx_helper_ports_on_interface(interface);
+    int ipd_port;
+    for (ipd_port=interface*16; ipd_port<interface*16+num_ports; ipd_port++)
+    {
+        cvmx_pip_port_cfg_t port_config;
+        port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+        port_config.s.crc_en = 1;
+        cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
+    }
+
+    if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
+    {
+        cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, CVMX_HELPER_SPI_TIMEOUT, num_ports);
+        if (cvmx_spi4000_is_present(interface))
+            cvmx_spi4000_initialize(interface);
+    }
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port)
+{
+    cvmx_helper_link_info_t result;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+    result.u64 = 0;
+
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+        /* The simulator gives you a simulated full duplex link */
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 10000;
+    }
+    else if (cvmx_spi4000_is_present(interface))
+    {
+        cvmx_gmxx_rxx_rx_inbnd_t inband = cvmx_spi4000_check_speed(interface, index);
+        result.s.link_up = inband.s.status;
+        result.s.full_duplex = inband.s.duplex;
+        switch (inband.s.speed)
+        {
+            case 0: /* 10 Mbps */
+                result.s.speed = 10;
+                break;
+            case 1: /* 100 Mbps */
+                result.s.speed = 100;
+                break;
+            case 2: /* 1 Gbps */
+                result.s.speed = 1000;
+                break;
+            case 3: /* Illegal */
+                result.s.speed = 0;
+                result.s.link_up = 0;
+                break;
+        }
+    }
+    else
+    {
+        /* For generic SPI we can't determine the link, just return some
+            sane results */
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 10000;
+    }
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    /* Nothing to do. If we have a SPI4000 then the setup was already performed
+        by cvmx_spi4000_check_speed(). If not then there isn't any link
+        info */
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/cvmx-helper-spi.h b/cvmx-helper-spi.h
new file mode 100644
index 0000000000000..7f2f82f1fc88d
--- /dev/null
+++ b/cvmx-helper-spi.h
@@ -0,0 +1,107 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for SPI initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_SPI_H__
+#define __CVMX_HELPER_SPI_H__
+
+/**
+ * @INTERNAL
+ * Probe a SPI interface and determine the number of ports
+ * connected to it. The SPI interface should still be down after
+ * this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_spi_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a SPI interface. After this call packet I/O
+ * should be fully functional. This is called with IPD enabled but
+ * PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_spi_enable(int interface);
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+#endif
diff --git a/cvmx-helper-util.c b/cvmx-helper-util.c
new file mode 100644
index 0000000000000..52f648ba5b5d6
--- /dev/null
+++ b/cvmx-helper-util.c
@@ -0,0 +1,564 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Small helper utilities.
+ *
+ * <hr>$Revision: 42493 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-fpa.h"
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-ipd.h"
+#include "cvmx-asx.h"
+#include "cvmx-gmx.h"
+#include "cvmx-spi.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-version.h"
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+/**
+ * Get the version of the CVMX libraries.
+ *
+ * @return Version string. Note this buffer is allocated statically
+ *         and will be shared by all callers.
+ */
+const char *cvmx_helper_get_version(void)
+{
+    return OCTEON_SDK_VERSION_STRING;
+}
+
+
+/**
+ * Convert a interface mode into a human readable string
+ *
+ * @param mode   Mode to convert
+ *
+ * @return String
+ */
+const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode)
+{
+    switch (mode)
+    {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:   return "DISABLED";
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:      return "RGMII";
+        case CVMX_HELPER_INTERFACE_MODE_GMII:       return "GMII";
+        case CVMX_HELPER_INTERFACE_MODE_SPI:        return "SPI";
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:       return "PCIE";
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:       return "XAUI";
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:      return "SGMII";
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:      return "PICMG";
+        case CVMX_HELPER_INTERFACE_MODE_NPI:        return "NPI";
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:       return "LOOP";
+    }
+    return "UNKNOWN";
+}
+
+
+/**
+ * Debug routine to dump the packet structure to the console
+ *
+ * @param work   Work queue entry containing the packet to dump
+ * @return
+ */
+int cvmx_helper_dump_packet(cvmx_wqe_t *work)
+{
+    uint64_t        count;
+    uint64_t        remaining_bytes;
+    cvmx_buf_ptr_t  buffer_ptr;
+    uint64_t        start_of_buffer;
+    uint8_t *       data_address;
+    uint8_t *       end_of_data;
+
+    cvmx_dprintf("Packet Length:   %u\n", work->len);
+    cvmx_dprintf("    Input Port:  %u\n", work->ipprt);
+    cvmx_dprintf("    QoS:         %u\n", work->qos);
+    cvmx_dprintf("    Buffers:     %u\n", work->word2.s.bufs);
+
+    if (work->word2.s.bufs == 0)
+    {
+        cvmx_ipd_wqe_fpa_queue_t wqe_pool;
+        wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
+        buffer_ptr.u64 = 0;
+        buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
+        buffer_ptr.s.size = 128;
+        buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
+        if (cvmx_likely(!work->word2.s.not_IP))
+        {
+            cvmx_pip_ip_offset_t pip_ip_offset;
+            pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET);
+            buffer_ptr.s.addr += (pip_ip_offset.s.offset<<3) - work->word2.s.ip_offset;
+            buffer_ptr.s.addr += (work->word2.s.is_v6^1)<<2;
+        }
+        else
+        {
+            /* WARNING: This code assume that the packet is not RAW. If it was,
+                we would use PIP_GBL_CFG[RAW_SHF] instead of
+                PIP_GBL_CFG[NIP_SHF] */
+            cvmx_pip_gbl_cfg_t pip_gbl_cfg;
+            pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG);
+            buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf;
+        }
+    }
+    else
+        buffer_ptr = work->packet_ptr;
+    remaining_bytes = work->len;
+
+    while (remaining_bytes)
+    {
+        start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+        cvmx_dprintf("    Buffer Start:%llx\n", (unsigned long long)start_of_buffer);
+        cvmx_dprintf("    Buffer I   : %u\n", buffer_ptr.s.i);
+        cvmx_dprintf("    Buffer Back: %u\n", buffer_ptr.s.back);
+        cvmx_dprintf("    Buffer Pool: %u\n", buffer_ptr.s.pool);
+        cvmx_dprintf("    Buffer Data: %llx\n", (unsigned long long)buffer_ptr.s.addr);
+        cvmx_dprintf("    Buffer Size: %u\n", buffer_ptr.s.size);
+
+        cvmx_dprintf("\t\t");
+        data_address = (uint8_t *)cvmx_phys_to_ptr(buffer_ptr.s.addr);
+        end_of_data = data_address + buffer_ptr.s.size;
+        count = 0;
+        while (data_address < end_of_data)
+        {
+            if (remaining_bytes == 0)
+                break;
+            else
+                remaining_bytes--;
+            cvmx_dprintf("%02x", (unsigned int)*data_address);
+            data_address++;
+            if (remaining_bytes && (count == 7))
+            {
+                cvmx_dprintf("\n\t\t");
+                count = 0;
+            }
+            else
+                count++;
+        }
+        cvmx_dprintf("\n");
+
+        if (remaining_bytes)
+            buffer_ptr = *(cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+    }
+    return 0;
+}
+
+
+/**
+ * Setup Random Early Drop on a specific input queue
+ *
+ * @param queue  Input queue to setup RED on (0-7)
+ * @param pass_thresh
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @param drop_thresh
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
+{
+    cvmx_ipd_qos_red_marks_t red_marks;
+    cvmx_ipd_red_quex_param_t red_param;
+
+    /* Set RED to begin dropping packets when there are pass_thresh buffers
+        left. It will linearly drop more packets until reaching drop_thresh
+        buffers */
+    red_marks.u64 = 0;
+    red_marks.s.drop = drop_thresh;
+    red_marks.s.pass = pass_thresh;
+    cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
+
+    /* Use the actual queue 0 counter, not the average */
+    red_param.u64 = 0;
+    red_param.s.prb_con = (255ul<<24) / (red_marks.s.pass - red_marks.s.drop);
+    red_param.s.avg_con = 1;
+    red_param.s.new_con = 255;
+    red_param.s.use_pcnt = 1;
+    cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
+    return 0;
+}
+
+
+/**
+ * Setup Random Early Drop to automatically begin dropping packets.
+ *
+ * @param pass_thresh
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @param drop_thresh
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * @return Zero on success. Negative on failure
+ */
+int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
+{
+    cvmx_ipd_portx_bp_page_cnt_t page_cnt;
+    cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end;
+    cvmx_ipd_red_port_enable_t red_port_enable;
+    int queue;
+    int interface;
+    int port;
+
+    /* Disable backpressure based on queued buffers. It needs SW support */
+    page_cnt.u64 = 0;
+    page_cnt.s.bp_enb = 0;
+    page_cnt.s.page_cnt = 100;
+    for (interface=0; interface<2; interface++)
+    {
+        for (port=cvmx_helper_get_first_ipd_port(interface); port<cvmx_helper_get_last_ipd_port(interface); port++)
+            cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), page_cnt.u64);
+    }
+
+    for (queue=0; queue<8; queue++)
+        cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
+
+    /* Shutoff the dropping based on the per port page count. SW isn't
+        decrementing it right now */
+    ipd_bp_prt_red_end.u64 = 0;
+    ipd_bp_prt_red_end.s.prt_enb = 0;
+    cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
+
+    red_port_enable.u64 = 0;
+    red_port_enable.s.prt_enb = 0xfffffffffull;
+    red_port_enable.s.avg_dly = 10000;
+    red_port_enable.s.prb_dly = 10000;
+    cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
+
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Setup the common GMX settings that determine the number of
+ * ports. These setting apply to almost all configurations of all
+ * chips.
+ *
+ * @param interface Interface to configure
+ * @param num_ports Number of ports on the interface
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_setup_gmx(int interface, int num_ports)
+{
+    cvmx_gmxx_tx_prts_t gmx_tx_prts;
+    cvmx_gmxx_rx_prts_t gmx_rx_prts;
+    cvmx_pko_reg_gmx_port_mode_t pko_mode;
+    cvmx_gmxx_txx_thresh_t gmx_tx_thresh;
+    int index;
+
+    /* Tell GMX the number of TX ports on this interface */
+    gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
+    gmx_tx_prts.s.prts = num_ports;
+    cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
+
+    /* Tell GMX the number of RX ports on this interface.  This only
+    ** applies to *GMII and XAUI ports */
+    if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_RGMII
+        || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_SGMII
+        || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_GMII
+        || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_XAUI)
+    {
+        if (num_ports > 4)
+        {
+            cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal num_ports\n");
+            return(-1);
+        }
+
+        gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
+        gmx_rx_prts.s.prts = num_ports;
+        cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
+    }
+
+    /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */
+    if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        /* Tell PKO the number of ports on this interface */
+        pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
+        if (interface == 0)
+        {
+            if (num_ports == 1)
+                pko_mode.s.mode0 = 4;
+            else if (num_ports == 2)
+                pko_mode.s.mode0 = 3;
+            else if (num_ports <= 4)
+                pko_mode.s.mode0 = 2;
+            else if (num_ports <= 8)
+                pko_mode.s.mode0 = 1;
+            else
+                pko_mode.s.mode0 = 0;
+        }
+        else
+        {
+            if (num_ports == 1)
+                pko_mode.s.mode1 = 4;
+            else if (num_ports == 2)
+                pko_mode.s.mode1 = 3;
+            else if (num_ports <= 4)
+                pko_mode.s.mode1 = 2;
+            else if (num_ports <= 8)
+                pko_mode.s.mode1 = 1;
+            else
+                pko_mode.s.mode1 = 0;
+        }
+        cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
+    }
+
+    /* Set GMX to buffer as much data as possible before starting transmit.
+        This reduces the chances that we have a TX under run due to memory
+        contention. Any packet that fits entirely in the GMX FIFO can never
+        have an under run regardless of memory load */
+    gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        /* These chips have a fixed max threshold of 0x40 */
+        gmx_tx_thresh.s.cnt = 0x40;
+    }
+    else
+    {
+        /* Choose the max value for the number of ports */
+        if (num_ports <= 1)
+            gmx_tx_thresh.s.cnt = 0x100 / 1;
+        else if (num_ports == 2)
+            gmx_tx_thresh.s.cnt = 0x100 / 2;
+        else
+            gmx_tx_thresh.s.cnt = 0x100 / 4;
+    }
+    /* SPI and XAUI can have lots of ports but the GMX hardware only ever has
+        a max of 4 */
+    if (num_ports > 4)
+        num_ports = 4;
+    for (index=0; index<num_ports; index++)
+        cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), gmx_tx_thresh.u64);
+
+    return 0;
+}
+
+
+/**
+ * Returns the IPD/PKO port number for a port on teh given
+ * interface.
+ *
+ * @param interface Interface to use
+ * @param port      Port on the interface
+ *
+ * @return IPD/PKO port number
+ */
+int cvmx_helper_get_ipd_port(int interface, int port)
+{
+    switch (interface)
+    {
+        case 0: return port;
+        case 1: return port + 16;
+        case 2: return port + 32;
+        case 3: return port + 36;
+    }
+    return -1;
+}
+
+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
+
+
+/**
+ * Returns the interface number for an IPD/PKO port number.
+ *
+ * @param ipd_port IPD/PKO port number
+ *
+ * @return Interface number
+ */
+int cvmx_helper_get_interface_num(int ipd_port)
+{
+    if (ipd_port < 16)
+        return 0;
+    else if (ipd_port < 32)
+        return 1;
+    else if (ipd_port < 36)
+        return 2;
+    else if (ipd_port < 40)
+        return 3;
+    else
+        cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n");
+
+    return -1;
+}
+
+
+/**
+ * Returns the interface index number for an IPD/PKO port
+ * number.
+ *
+ * @param ipd_port IPD/PKO port number
+ *
+ * @return Interface index number
+ */
+int cvmx_helper_get_interface_index_num(int ipd_port)
+{
+    if (ipd_port < 32)
+        return ipd_port & 15;
+    else if (ipd_port < 36)
+        return ipd_port & 3;
+    else if (ipd_port < 40)
+        return ipd_port & 3;
+    else
+        cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n");
+
+    return -1;
+}
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+void cvmx_helper_qlm_jtag_init(void)
+{
+    cvmx_ciu_qlm_jtgc_t jtgc;
+    int clock_div = 0;
+    int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
+    divisor = (divisor-1)>>2;
+    /* Convert the divisor into a power of 2 shift */
+    CVMX_CLZ(clock_div, divisor);
+    clock_div = 32 - clock_div;
+
+    /* Clock divider for QLM JTAG operations.  eclk is divided by 2^(CLK_DIV + 2) */
+    jtgc.u64 = 0;
+    jtgc.s.clk_div = clock_div;
+    jtgc.s.mux_sel = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        jtgc.s.bypass = 0x3;
+    else
+        jtgc.s.bypass = 0xf;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+    cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+}
+
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain is
+ * 4 * 268 bits long, or 1072.
+ *
+ * @param qlm    QLM to shift value into
+ * @param bits   Number of bits to shift in (1-32).
+ * @param data   Data to shift in. Bit 0 enters the chain first, followed by
+ *               bit 1, etc.
+ *
+ * @return The low order bits of the JTAG chain that shifted out of the
+ *         circle.
+ */
+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
+{
+    cvmx_ciu_qlm_jtgd_t jtgd;
+    jtgd.u64 = 0;
+    jtgd.s.shift = 1;
+    jtgd.s.shft_cnt = bits-1;
+    jtgd.s.shft_reg = data;
+    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+        jtgd.s.select = 1 << qlm;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+    do
+    {
+        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    } while (jtgd.s.shift);
+    return jtgd.s.shft_reg >> (32-bits);
+}
+
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @param qlm    QLM to shift zeros into
+ * @param bits
+ */
+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
+{
+    while (bits > 0)
+    {
+        int n = bits;
+        if (n > 32)
+            n = 32;
+        cvmx_helper_qlm_jtag_shift(qlm, n, 0);
+        bits -= n;
+    }
+}
+
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in 268*4, or 1072 bits into the JTAG
+ * chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @param qlm    QLM to program
+ */
+void cvmx_helper_qlm_jtag_update(int qlm)
+{
+    cvmx_ciu_qlm_jtgd_t jtgd;
+
+    /* Update the new data */
+    jtgd.u64 = 0;
+    jtgd.s.update = 1;
+    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+        jtgd.s.select = 1 << qlm;
+    cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+    do
+    {
+        jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+    } while (jtgd.s.update);
+}
+
diff --git a/cvmx-helper-util.h b/cvmx-helper-util.h
new file mode 100644
index 0000000000000..553e9e0971fae
--- /dev/null
+++ b/cvmx-helper-util.h
@@ -0,0 +1,277 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Small helper utilities.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_HELPER_UTIL_H__
+#define __CVMX_HELPER_UTIL_H__
+
+
+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+
+/**
+ * Convert a interface mode into a human readable string
+ *
+ * @param mode   Mode to convert
+ *
+ * @return String
+ */
+extern const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
+
+/**
+ * Debug routine to dump the packet structure to the console
+ *
+ * @param work   Work queue entry containing the packet to dump
+ * @return
+ */
+extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
+
+/**
+ * Setup Random Early Drop on a specific input queue
+ *
+ * @param queue  Input queue to setup RED on (0-7)
+ * @param pass_thresh
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @param drop_thresh
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * @return Zero on success. Negative on failure
+ */
+extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh);
+
+/**
+ * Setup Random Early Drop to automatically begin dropping packets.
+ *
+ * @param pass_thresh
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @param drop_thresh
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * @return Zero on success. Negative on failure
+ */
+extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
+
+
+/**
+ * Get the version of the CVMX libraries.
+ *
+ * @return Version string. Note this buffer is allocated statically
+ *         and will be shared by all callers.
+ */
+extern const char *cvmx_helper_get_version(void);
+
+
+/**
+ * @INTERNAL
+ * Setup the common GMX settings that determine the number of
+ * ports. These setting apply to almost all configurations of all
+ * chips.
+ *
+ * @param interface Interface to configure
+ * @param num_ports Number of ports on the interface
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
+
+/**
+ * Returns the IPD/PKO port number for a port on the given
+ * interface.
+ *
+ * @param interface Interface to use
+ * @param port      Port on the interface
+ *
+ * @return IPD/PKO port number
+ */
+extern int cvmx_helper_get_ipd_port(int interface, int port);
+
+
+/**
+ * Returns the IPD/PKO port number for the first port on the given
+ * interface.
+ *
+ * @param interface Interface to use
+ *
+ * @return IPD/PKO port number
+ */
+static inline int cvmx_helper_get_first_ipd_port(int interface)
+{
+    return (cvmx_helper_get_ipd_port (interface, 0));
+}
+
+/**
+ * Returns the IPD/PKO port number for the last port on the given
+ * interface.
+ *
+ * @param interface Interface to use
+ *
+ * @return IPD/PKO port number
+ */
+static inline int cvmx_helper_get_last_ipd_port (int interface)
+{
+    extern int cvmx_helper_ports_on_interface (int interface);
+
+    return (cvmx_helper_get_first_ipd_port (interface) +
+  	    cvmx_helper_ports_on_interface (interface) - 1);
+}
+
+
+/**
+ * Free the packet buffers contained in a work queue entry.
+ * The work queue entry is not freed.
+ *
+ * @param work   Work queue entry with packet to free
+ */
+static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
+{
+    uint64_t        number_buffers;
+    cvmx_buf_ptr_t  buffer_ptr;
+    cvmx_buf_ptr_t  next_buffer_ptr;
+    uint64_t        start_of_buffer;
+
+    number_buffers = work->word2.s.bufs;
+    if (number_buffers == 0)
+        return;
+    buffer_ptr = work->packet_ptr;
+
+    /* Since the number of buffers is not zero, we know this is not a dynamic
+        short packet. We need to check if it is a packet received with
+        IPD_CTL_STATUS[NO_WPTR]. If this is true, we need to free all buffers
+        except for the first one. The caller doesn't expect their WQE pointer
+        to be freed */
+    start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+    if (cvmx_ptr_to_phys(work) == start_of_buffer)
+    {
+        next_buffer_ptr = *(cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+        buffer_ptr = next_buffer_ptr;
+        number_buffers--;
+    }
+
+    while (number_buffers--)
+    {
+        /* Remember the back pointer is in cache lines, not 64bit words */
+        start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+        /* Read pointer to next buffer before we free the current buffer. */
+        next_buffer_ptr = *(cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+        cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), buffer_ptr.s.pool, 0);
+        buffer_ptr = next_buffer_ptr;
+    }
+}
+
+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
+
+/**
+ * Returns the interface number for an IPD/PKO port number.
+ *
+ * @param ipd_port IPD/PKO port number
+ *
+ * @return Interface number
+ */
+extern int cvmx_helper_get_interface_num(int ipd_port);
+
+
+/**
+ * Returns the interface index number for an IPD/PKO port
+ * number.
+ *
+ * @param ipd_port IPD/PKO port number
+ *
+ * @return Interface index number
+ */
+extern int cvmx_helper_get_interface_index_num(int ipd_port);
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+extern void cvmx_helper_qlm_jtag_init(void);
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain is
+ * 4 * 268 bits long, or 1072.
+ *
+ * @param qlm    QLM to shift value into
+ * @param bits   Number of bits to shift in (1-32).
+ * @param data   Data to shift in. Bit 0 enters the chain first, followed by
+ *               bit 1, etc.
+ *
+ * @return The low order bits of the JTAG chain that shifted out of the
+ *         circle.
+ */
+extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @param qlm    QLM to shift zeros into
+ * @param bits
+ */
+extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in 268*4, or 1072 bits into the JTAG
+ * chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @param qlm    QLM to program
+ */
+extern void cvmx_helper_qlm_jtag_update(int qlm);
+
+#endif  /* __CVMX_HELPER_H__ */
diff --git a/cvmx-helper-xaui.c b/cvmx-helper-xaui.c
new file mode 100644
index 0000000000000..3027cdefb5537
--- /dev/null
+++ b/cvmx-helper-xaui.c
@@ -0,0 +1,334 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for XAUI initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 42417 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx.h"
+#include "cvmx-helper.h"
+
+
+/**
+ * @INTERNAL
+ * Probe a XAUI interface and determine the number of ports
+ * connected to it. The XAUI interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_xaui_probe(int interface)
+{
+    int i;
+    cvmx_gmxx_hg2_control_t gmx_hg2_control;
+    cvmx_gmxx_inf_mode_t mode;
+
+    /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
+        needs to be enabled before IPD otherwise per port backpressure
+        may not work properly */
+    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+    mode.s.en = 1;
+    cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
+
+    __cvmx_helper_setup_gmx(interface, 1);
+
+    /* Setup PKO to support 16 ports for HiGig2 virtual ports. We're pointing
+        all of the PKO packet ports for this interface to the XAUI. This allows
+        us to use HiGig2 backpressure per port */
+    for (i=0; i<16; i++)
+    {
+        cvmx_pko_mem_port_ptrs_t pko_mem_port_ptrs;
+        pko_mem_port_ptrs.u64 = 0;
+        /* We set each PKO port to have equal priority in a round robin
+            fashion */
+        pko_mem_port_ptrs.s.static_p = 0;
+        pko_mem_port_ptrs.s.qos_mask = 0xff;
+        /* All PKO ports map to the same XAUI hardware port */
+        pko_mem_port_ptrs.s.eid = interface*4;
+        pko_mem_port_ptrs.s.pid = interface*16 + i;
+        cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
+    }
+
+    /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
+    gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
+    if (gmx_hg2_control.s.hg2tx_en)
+        return 16;
+    else
+        return 1;
+}
+
+
+/**
+ * @INTERNAL
+ * Bringup and enable a XAUI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_xaui_enable(int interface)
+{
+    cvmx_gmxx_prtx_cfg_t          gmx_cfg;
+    cvmx_pcsxx_control1_reg_t     xauiCtl;
+    cvmx_pcsxx_misc_ctl_reg_t     xauiMiscCtl;
+    cvmx_gmxx_tx_xaui_ctl_t       gmxXauiTxCtl;
+    cvmx_gmxx_rxx_int_en_t        gmx_rx_int_en;
+    cvmx_gmxx_tx_int_en_t         gmx_tx_int_en;
+    cvmx_pcsxx_int_en_reg_t       pcsx_int_en_reg;
+
+    /* (1) Interface has already been enabled. */
+
+    /* (2) Disable GMX. */
+    xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
+    xauiMiscCtl.s.gmxeno = 1;
+    cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+
+    /* (3) Disable GMX and PCSX interrupts. */
+    gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0,interface));
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
+    gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
+    cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
+    pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
+    cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
+
+    /* (4) Bring up the PCSX and GMX reconciliation layer. */
+    /* (4)a Set polarity and lane swapping. */
+    /* (4)b */
+    gmxXauiTxCtl.u64 = cvmx_read_csr (CVMX_GMXX_TX_XAUI_CTL(interface));
+    gmxXauiTxCtl.s.dic_en = 1; /* Enable better IFG packing and improves performance */
+    gmxXauiTxCtl.s.uni_en = 0;
+    cvmx_write_csr (CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
+
+    /* (4)c Aply reset sequence */
+    xauiCtl.u64 = cvmx_read_csr (CVMX_PCSXX_CONTROL1_REG(interface));
+    xauiCtl.s.lo_pwr = 0;
+    xauiCtl.s.reset  = 1;
+    cvmx_write_csr (CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
+
+    /* Wait for PCS to come out of reset */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_CONTROL1_REG(interface), cvmx_pcsxx_control1_reg_t, reset, ==, 0, 10000))
+        return -1;
+    /* Wait for PCS to be aligned */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_10GBX_STATUS_REG(interface), cvmx_pcsxx_10gbx_status_reg_t, alignd, ==, 1, 10000))
+        return -1;
+    /* Wait for RX to be ready */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_RX_XAUI_CTL(interface), cvmx_gmxx_rx_xaui_ctl_t, status, ==, 0, 10000))
+        return -1;
+
+    /* (6) Configure GMX */
+    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+    gmx_cfg.s.en = 0;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+
+    /* Wait for GMX RX to be idle */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000))
+        return -1;
+    /* Wait for GMX TX to be idle */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
+        return -1;
+
+    /* GMX configure */
+    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+    gmx_cfg.s.speed = 1;
+    gmx_cfg.s.speed_msb = 0;
+    gmx_cfg.s.slottime = 1;
+    cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
+    cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
+    cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+
+    /* (7) Clear out any error state */
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0,interface), cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0,interface)));
+    cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
+    cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
+
+    /* Wait for receive link */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS1_REG(interface), cvmx_pcsxx_status1_reg_t, rcv_lnk, ==, 1, 10000))
+        return -1;
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, xmtflt, ==, 0, 10000))
+        return -1;
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, rcvflt, ==, 0, 10000))
+        return -1;
+
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), gmx_rx_int_en.u64);
+    cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
+    cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
+
+    cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
+
+    /* (8) Enable packet reception */
+    xauiMiscCtl.s.gmxeno = 0;
+    cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+
+    gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+    gmx_cfg.s.en = 1;
+    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+    return 0;
+}
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    cvmx_gmxx_tx_xaui_ctl_t gmxx_tx_xaui_ctl;
+    cvmx_gmxx_rx_xaui_ctl_t gmxx_rx_xaui_ctl;
+    cvmx_pcsxx_status1_reg_t pcsxx_status1_reg;
+    cvmx_helper_link_info_t result;
+
+    gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+    gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
+    pcsxx_status1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
+    result.u64 = 0;
+
+    /* Only return a link if both RX and TX are happy */
+    if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
+        (pcsxx_status1_reg.s.rcv_lnk == 1))
+    {
+        result.s.link_up = 1;
+        result.s.full_duplex = 1;
+        result.s.speed = 10000;
+    }
+    else
+    {
+        /* Disable GMX and PCSX interrupts. */
+        cvmx_write_csr (CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
+        cvmx_write_csr (CVMX_GMXX_TX_INT_EN(interface), 0x0);
+        cvmx_write_csr (CVMX_PCSXX_INT_EN_REG(interface), 0x0);
+    }
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    cvmx_gmxx_tx_xaui_ctl_t gmxx_tx_xaui_ctl;
+    cvmx_gmxx_rx_xaui_ctl_t gmxx_rx_xaui_ctl;
+
+    gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+    gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
+
+    /* If the link shouldn't be up, then just return */
+    if (!link_info.s.link_up)
+        return 0;
+
+    /* Do nothing if both RX and TX are happy */
+    if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
+        return 0;
+
+    /* Bring the link up */
+    return __cvmx_helper_xaui_enable(interface);
+}
+
+
+/**
+ * @INTERNAL
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, int enable_internal, int enable_external)
+{
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    cvmx_pcsxx_control1_reg_t pcsxx_control1_reg;
+    cvmx_gmxx_xaui_ext_loopback_t gmxx_xaui_ext_loopback;
+
+    /* Set the internal loop */
+    pcsxx_control1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
+    pcsxx_control1_reg.s.loopbck1 = enable_internal;
+    cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), pcsxx_control1_reg.u64);
+
+    /* Set the external loop */
+    gmxx_xaui_ext_loopback.u64 = cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
+    gmxx_xaui_ext_loopback.s.en = enable_external;
+    cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), gmxx_xaui_ext_loopback.u64);
+
+    /* Take the link through a reset */
+    return __cvmx_helper_xaui_enable(interface);
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/cvmx-helper-xaui.h b/cvmx-helper-xaui.h
new file mode 100644
index 0000000000000..4bea0c2ebc012
--- /dev/null
+++ b/cvmx-helper-xaui.h
@@ -0,0 +1,124 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for XAUI initialization, configuration,
+ * and monitoring.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#ifndef __CVMX_HELPER_XAUI_H__
+#define __CVMX_HELPER_XAUI_H__
+
+/**
+ * @INTERNAL
+ * Probe a XAUI interface and determine the number of ports
+ * connected to it. The XAUI interface should still be down
+ * after this call.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_xaui_probe(int interface);
+
+/**
+ * @INTERNAL
+ * Bringup and enable a XAUI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_xaui_enable(int interface);
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port);
+
+/**
+ * @INTERNAL
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+/**
+ * @INTERNAL
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, int enable_internal, int enable_external);
+
+#endif
+
diff --git a/cvmx-helper.c b/cvmx-helper.c
new file mode 100644
index 0000000000000..50cbdb915607e
--- /dev/null
+++ b/cvmx-helper.c
@@ -0,0 +1,835 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper functions for common, but complicated tasks.
+ *
+ * <hr>$Revision: 42150 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-fpa.h"
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-ipd.h"
+#include "cvmx-asx.h"
+#include "cvmx-gmx.h"
+#include "cvmx-spi.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+#include "cvmx-version.h"
+#include "cvmx-helper-check-defines.h"
+#include "cvmx-helper-board.h"
+#include "cvmx-helper-errata.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+/**
+ * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * priorities[16]) is a function pointer. It is meant to allow
+ * customization of the PKO queue priorities based on the port
+ * number. Users should set this pointer to a function before
+ * calling any cvmx-helper operations.
+ */
+CVMX_SHARED void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t priorities[16]) = NULL;
+
+/**
+ * cvmx_override_ipd_port_setup(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the IPD port
+ * setup before packet input/output comes online. It is called
+ * after cvmx-helper does the default IPD configuration, but
+ * before IPD is enabled. Users should set this pointer to a
+ * function before calling any cvmx-helper operations.
+ */
+CVMX_SHARED void (*cvmx_override_ipd_port_setup)(int ipd_port) = NULL;
+
+/* Port count per interface */
+static CVMX_SHARED int interface_port_count[4] = {0,0,0,0};
+/* Port last configured link info index by IPD/PKO port */
+static CVMX_SHARED cvmx_helper_link_info_t port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
+
+
+/**
+ * Return the number of interfaces the chip has. Each interface
+ * may have multiple ports. Most chips support two interfaces,
+ * but the CNX0XX and CNX1XX are exceptions. These only support
+ * one interface.
+ *
+ * @return Number of interfaces on chip
+ */
+int cvmx_helper_get_number_of_interfaces(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+        return 4;
+    else
+        return 3;
+}
+
+
+/**
+ * Return the number of ports on an interface. Depending on the
+ * chip and configuration, this can be 1-16. A value of 0
+ * specifies that the interface doesn't exist or isn't usable.
+ *
+ * @param interface Interface to get the port count for
+ *
+ * @return Number of ports on interface. Can be Zero.
+ */
+int cvmx_helper_ports_on_interface(int interface)
+{
+    return interface_port_count[interface];
+}
+
+
+/**
+ * Get the operating mode of an interface. Depending on the Octeon
+ * chip and configuration, this function returns an enumeration
+ * of the type of packet I/O supported by an interface.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Mode of the interface. Unknown or unsupported interfaces return
+ *         DISABLED.
+ */
+cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
+{
+    cvmx_gmxx_inf_mode_t mode;
+    if (interface == 2)
+        return CVMX_HELPER_INTERFACE_MODE_NPI;
+
+    if (interface == 3)
+    {
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+            return CVMX_HELPER_INTERFACE_MODE_LOOP;
+        else
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+    }
+
+    if (interface == 0 && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 && cvmx_sysinfo_get()->board_rev_major == 1)
+    {
+        /* Lie about interface type of CN3005 board.  This board has a switch on port 1 like
+        ** the other evaluation boards, but it is connected over RGMII instead of GMII.  Report
+        ** GMII mode so that the speed is forced to 1 Gbit full duplex.  Other than some initial configuration
+        ** (which does not use the output of this function) there is no difference in setup between GMII and RGMII modes.
+        */
+        return CVMX_HELPER_INTERFACE_MODE_GMII;
+    }
+
+    /* Interface 1 is always disabled on CN31XX and CN30XX */
+    if ((interface == 1) && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)))
+        return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        switch(mode.cn56xx.mode)
+        {
+            case 0: return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+            case 1: return CVMX_HELPER_INTERFACE_MODE_XAUI;
+            case 2: return CVMX_HELPER_INTERFACE_MODE_SGMII;
+            case 3: return CVMX_HELPER_INTERFACE_MODE_PICMG;
+            default:return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+        }
+    }
+    else
+    {
+        if (!mode.s.en)
+            return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+        if (mode.s.type)
+        {
+            if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+                return CVMX_HELPER_INTERFACE_MODE_SPI;
+            else
+                return CVMX_HELPER_INTERFACE_MODE_GMII;
+        }
+        else
+            return CVMX_HELPER_INTERFACE_MODE_RGMII;
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Configure the IPD/PIP tagging and QoS options for a specific
+ * port. This function determines the POW work queue entry
+ * contents for a port. The setup performed here is controlled by
+ * the defines in executive-config.h.
+ *
+ * @param ipd_port Port to configure. This follows the IPD numbering, not the
+ *                 per interface numbering
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_port_setup_ipd(int ipd_port)
+{
+    cvmx_pip_port_cfg_t port_config;
+    cvmx_pip_port_tag_cfg_t tag_config;
+
+    port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+    tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
+
+    /* Have each port go to a different POW queue */
+    port_config.s.qos = ipd_port & 0x7;
+
+    /* Process the headers and place the IP header in the work queue */
+    port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE;
+
+    tag_config.s.ip6_src_flag  = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP;
+    tag_config.s.ip6_dst_flag  = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP;
+    tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT;
+    tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT;
+    tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER;
+    tag_config.s.ip4_src_flag  = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP;
+    tag_config.s.ip4_dst_flag  = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP;
+    tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT;
+    tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT;
+    tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL;
+    tag_config.s.inc_prt_flag  = CVMX_HELPER_INPUT_TAG_INPUT_PORT;
+    tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+    tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+    tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+    tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+    tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+    /* Put all packets in group 0. Other groups can be used by the app */
+    tag_config.s.grp = 0;
+
+    cvmx_pip_config_port(ipd_port, port_config, tag_config);
+
+    /* Give the user a chance to override our setting for each port */
+    if (cvmx_override_ipd_port_setup)
+        cvmx_override_ipd_port_setup(ipd_port);
+
+    return 0;
+}
+
+
+/**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_helper_interface_probe(int interface)
+{
+    /* At this stage in the game we don't want packets to be moving yet.
+        The following probe calls should perform hardware setup
+        needed to determine port counts. Receive must still be disabled */
+    switch (cvmx_helper_interface_get_mode(interface))
+    {
+        /* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            interface_port_count[interface] = 0;
+            break;
+        /* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            interface_port_count[interface] = __cvmx_helper_xaui_probe(interface);
+            break;
+        /* RGMII/GMII/MII are all treated about the same. Most functions
+            refer to these ports as RGMII */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            interface_port_count[interface] = __cvmx_helper_rgmii_probe(interface);
+            break;
+        /* SPI4 can have 1-16 ports depending on the device at the other end */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+            interface_port_count[interface] = __cvmx_helper_spi_probe(interface);
+            break;
+        /* SGMII can have 1-4 ports depending on how many are hooked up */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            interface_port_count[interface] = __cvmx_helper_sgmii_probe(interface);
+            break;
+        /* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+            interface_port_count[interface] = __cvmx_helper_npi_probe(interface);
+            break;
+        /* Special loopback only ports. These are not the same as other ports
+            in loopback mode */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+            interface_port_count[interface] = __cvmx_helper_loop_probe(interface);
+            break;
+    }
+
+    interface_port_count[interface] = __cvmx_helper_board_interface_probe(interface, interface_port_count[interface]);
+
+    /* Make sure all global variables propagate to other cores */
+    CVMX_SYNCWS;
+
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Setup the IPD/PIP for the ports on an interface. Packet
+ * classification and tagging are set for every port on the
+ * interface. The number of ports on the interface must already
+ * have been probed.
+ *
+ * @param interface Interface to setup IPD/PIP for
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_interface_setup_ipd(int interface)
+{
+    int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
+    int num_ports = interface_port_count[interface];
+
+    while (num_ports--)
+    {
+        __cvmx_helper_port_setup_ipd(ipd_port);
+        ipd_port++;
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Setup global setting for IPD/PIP not related to a specific
+ * interface or port. This must be called before IPD is enabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+static int __cvmx_helper_global_setup_ipd(void)
+{
+    /* Setup the global packet input options */
+    cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE/8,
+                    CVMX_HELPER_FIRST_MBUFF_SKIP/8,
+                    CVMX_HELPER_NOT_FIRST_MBUFF_SKIP/8,
+                    (CVMX_HELPER_FIRST_MBUFF_SKIP+8) / 128, /* The +8 is to account for the next ptr */
+                    (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP+8) / 128, /* The +8 is to account for the next ptr */
+                    CVMX_FPA_WQE_POOL,
+                    CVMX_IPD_OPC_MODE_STT,
+                    CVMX_HELPER_ENABLE_BACK_PRESSURE);
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Setup the PKO for the ports on an interface. The number of
+ * queues per port and the priority of each PKO output queue
+ * is set here. PKO must be disabled when this function is called.
+ *
+ * @param interface Interface to setup PKO for
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_interface_setup_pko(int interface)
+{
+    /* Each packet output queue has an associated priority. The higher the
+        priority, the more often it can send a packet. A priority of 8 means
+        it can send in all 8 rounds of contention. We're going to make each
+        queue one less than the last.
+        The vector of priorities has been extended to support CN5xxx CPUs,
+        where up to 16 queues can be associated to a port.
+        To keep backward compatibility we don't change the initial 8
+        priorities and replicate them in the second half.
+        With per-core PKO queues (PKO lockless operation) all queues have
+        the same priority. */
+    uint64_t priorities[16] = {8,7,6,5,4,3,2,1,8,7,6,5,4,3,2,1};
+
+    /* Setup the IPD/PIP and PKO for the ports discovered above. Here packet
+        classification, tagging and output priorities are set */
+    int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
+    int num_ports = interface_port_count[interface];
+    while (num_ports--)
+    {
+        /* Give the user a chance to override the per queue priorities */
+        if (cvmx_override_pko_queue_priority)
+            cvmx_override_pko_queue_priority(ipd_port, priorities);
+
+        cvmx_pko_config_port(ipd_port, cvmx_pko_get_base_queue_per_core(ipd_port, 0),
+                             cvmx_pko_get_num_queues(ipd_port), priorities);
+        ipd_port++;
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Setup global setting for PKO not related to a specific
+ * interface or port. This must be called before PKO is enabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+static int __cvmx_helper_global_setup_pko(void)
+{
+    /* Disable tagwait FAU timeout. This needs to be done before anyone might
+        start packet output using tags */
+    cvmx_iob_fau_timeout_t fau_to;
+    fau_to.u64 = 0;
+    fau_to.s.tout_val = 0xfff;
+    fau_to.s.tout_enb = 0;
+    cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Setup global backpressure setting.
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_global_setup_backpressure(void)
+{
+#if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
+    /* Disable backpressure if configured to do so */
+    /* Disable backpressure (pause frame) generation */
+    int num_interfaces = cvmx_helper_get_number_of_interfaces();
+    int interface;
+    for (interface=0; interface<num_interfaces; interface++)
+    {
+        switch (cvmx_helper_interface_get_mode(interface))
+        {
+            case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+            case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            case CVMX_HELPER_INTERFACE_MODE_NPI:
+            case CVMX_HELPER_INTERFACE_MODE_LOOP:
+            case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                break;
+            case CVMX_HELPER_INTERFACE_MODE_RGMII:
+            case CVMX_HELPER_INTERFACE_MODE_GMII:
+            case CVMX_HELPER_INTERFACE_MODE_SPI:
+            case CVMX_HELPER_INTERFACE_MODE_SGMII:
+            case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                cvmx_gmx_set_backpressure_override(interface, 0xf);
+                break;
+        }
+    }
+    //cvmx_dprintf("Disabling backpressure\n");
+#endif
+
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Enable packet input/output from the hardware. This function is
+ * called after all internal setup is complete and IPD is enabled.
+ * After this function completes, packets will be accepted from the
+ * hardware ports. PKO should still be disabled to make sure packets
+ * aren't sent out partially setup hardware.
+ *
+ * @param interface Interface to enable
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_packet_hardware_enable(int interface)
+{
+    int result = 0;
+    switch (cvmx_helper_interface_get_mode(interface))
+    {
+        /* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            /* Nothing to do */
+            break;
+        /* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            result = __cvmx_helper_xaui_enable(interface);
+            break;
+        /* RGMII/GMII/MII are all treated about the same. Most functions
+            refer to these ports as RGMII */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            result = __cvmx_helper_rgmii_enable(interface);
+            break;
+        /* SPI4 can have 1-16 ports depending on the device at the other end */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+            result = __cvmx_helper_spi_enable(interface);
+            break;
+        /* SGMII can have 1-4 ports depending on how many are hooked up */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            result = __cvmx_helper_sgmii_enable(interface);
+            break;
+        /* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+            result = __cvmx_helper_npi_enable(interface);
+            break;
+        /* Special loopback only ports. These are not the same as other ports
+            in loopback mode */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+            result = __cvmx_helper_loop_enable(interface);
+            break;
+    }
+    result |= __cvmx_helper_board_hardware_enable(interface);
+    return result;
+}
+
+
+/**
+ * Called after all internal packet IO paths are setup. This
+ * function enables IPD/PIP and begins packet input and output.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_helper_ipd_and_packet_input_enable(void)
+{
+    int num_interfaces;
+    int interface;
+
+    /* Enable IPD */
+    cvmx_ipd_enable();
+
+    /* Time to enable hardware ports packet input and output. Note that at this
+        point IPD/PIP must be fully functional and PKO must be disabled */
+    num_interfaces = cvmx_helper_get_number_of_interfaces();
+    for (interface=0; interface<num_interfaces; interface++)
+    {
+        if (cvmx_helper_ports_on_interface(interface) > 0)
+        {
+            //cvmx_dprintf("Enabling packet I/O on interface %d\n", interface);
+            __cvmx_helper_packet_hardware_enable(interface);
+        }
+    }
+
+    /* Finally enable PKO now that the entire path is up and running */
+    cvmx_pko_enable();
+
+    if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) &&
+        (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM))
+        __cvmx_helper_errata_fix_ipd_ptr_alignment();
+    return 0;
+}
+
+
+/**
+ * Initialize the PIP, IPD, and PKO hardware to support
+ * simple priority based queues for the ethernet ports. Each
+ * port is configured with a number of priority queues based
+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
+ * priority than the previous.
+ *
+ * @return Zero on success, non-zero on failure
+ */
+int cvmx_helper_initialize_packet_io_global(void)
+{
+    int result = 0;
+    int interface;
+    cvmx_l2c_cfg_t l2c_cfg;
+    cvmx_smix_en_t smix_en;
+    const int num_interfaces = cvmx_helper_get_number_of_interfaces();
+
+    /* CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to be disabled */
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
+        __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1);
+
+    /* Tell L2 to give the IOB statically higher priority compared to the
+        cores. This avoids conditions where IO blocks might be starved under
+        very high L2 loads */
+    l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+    l2c_cfg.s.lrf_arb_mode = 0;
+    l2c_cfg.s.rfb_arb_mode = 0;
+    cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
+
+    /* Make sure SMI/MDIO is enabled so we can query PHYs */
+    smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
+    if (!smix_en.s.en)
+    {
+        smix_en.s.en = 1;
+        cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
+    }
+
+    /* Newer chips actually have two SMI/MDIO interfaces */
+    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
+        !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
+        !OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
+        if (!smix_en.s.en)
+        {
+            smix_en.s.en = 1;
+            cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
+        }
+    }
+
+    cvmx_pko_initialize_global();
+    for (interface=0; interface<num_interfaces; interface++)
+    {
+        result |= cvmx_helper_interface_probe(interface);
+        if (cvmx_helper_ports_on_interface(interface) > 0)
+            cvmx_dprintf("Interface %d has %d ports (%s)\n",
+                     interface, cvmx_helper_ports_on_interface(interface),
+                     cvmx_helper_interface_mode_to_string(cvmx_helper_interface_get_mode(interface)));
+        result |= __cvmx_helper_interface_setup_ipd(interface);
+        result |= __cvmx_helper_interface_setup_pko(interface);
+    }
+
+    result |= __cvmx_helper_global_setup_ipd();
+    result |= __cvmx_helper_global_setup_pko();
+
+    /* Enable any flow control and backpressure */
+    result |= __cvmx_helper_global_setup_backpressure();
+
+#if CVMX_HELPER_ENABLE_IPD
+    result |= cvmx_helper_ipd_and_packet_input_enable();
+#endif
+    return result;
+}
+
+
+/**
+ * Does core local initialization for packet io
+ *
+ * @return Zero on success, non-zero on failure
+ */
+int cvmx_helper_initialize_packet_io_local(void)
+{
+    return cvmx_pko_initialize_local();
+}
+
+
+/**
+ * Auto configure an IPD/PKO port link state and speed. This
+ * function basically does the equivalent of:
+ * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
+ *
+ * @param ipd_port IPD/PKO port to auto configure
+ *
+ * @return Link state after configure
+ */
+cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
+{
+    cvmx_helper_link_info_t link_info;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+    if (index >= cvmx_helper_ports_on_interface(interface))
+    {
+        link_info.u64 = 0;
+        return link_info;
+    }
+
+    link_info = cvmx_helper_link_get(ipd_port);
+    if (link_info.u64 ==  port_link_info[ipd_port].u64)
+        return link_info;
+
+    /* If we fail to set the link speed, port_link_info will not change */
+    cvmx_helper_link_set(ipd_port, link_info);
+
+    /* port_link_info should be the current value, which will be different
+        than expect if cvmx_helper_link_set() failed */
+    return port_link_info[ipd_port];
+}
+
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
+{
+    cvmx_helper_link_info_t result;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+    /* The default result will be a down link unless the code below
+        changes it */
+    result.u64 = 0;
+
+    if (index >= cvmx_helper_ports_on_interface(interface))
+        return result;
+
+    switch (cvmx_helper_interface_get_mode(interface))
+    {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            /* Network links are not supported */
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            result = __cvmx_helper_xaui_link_get(ipd_port);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            if (index == 0)
+                result = __cvmx_helper_rgmii_link_get(ipd_port);
+            else
+            {
+                result.s.full_duplex = 1;
+                result.s.link_up = 1;
+                result.s.speed = 1000;
+            }
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+            result = __cvmx_helper_rgmii_link_get(ipd_port);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+            result = __cvmx_helper_spi_link_get(ipd_port);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            result = __cvmx_helper_sgmii_link_get(ipd_port);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+            /* Network links are not supported */
+            break;
+    }
+    return result;
+}
+
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+    int result = -1;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+    if (index >= cvmx_helper_ports_on_interface(interface))
+        return -1;
+
+    switch (cvmx_helper_interface_get_mode(interface))
+    {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            result = __cvmx_helper_xaui_link_set(ipd_port, link_info);
+            break;
+        /* RGMII/GMII/MII are all treated about the same. Most functions
+            refer to these ports as RGMII */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            result = __cvmx_helper_rgmii_link_set(ipd_port, link_info);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+            result = __cvmx_helper_spi_link_set(ipd_port, link_info);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            result = __cvmx_helper_sgmii_link_set(ipd_port, link_info);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+            break;
+    }
+    /* Set the port_link_info here so that the link status is updated
+       no matter how cvmx_helper_link_set is called. We don't change
+       the value if link_set failed */
+    if (result == 0)
+        port_link_info[ipd_port].u64 = link_info.u64;
+    return result;
+}
+
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int enable_external)
+{
+    int result = -1;
+    int interface = cvmx_helper_get_interface_num(ipd_port);
+    int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+    if (index >= cvmx_helper_ports_on_interface(interface))
+        return -1;
+
+    switch (cvmx_helper_interface_get_mode(interface))
+    {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+            result = __cvmx_helper_xaui_configure_loopback(ipd_port, enable_internal, enable_external);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+            result = __cvmx_helper_rgmii_configure_loopback(ipd_port, enable_internal, enable_external);
+            break;
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+            result = __cvmx_helper_sgmii_configure_loopback(ipd_port, enable_internal, enable_external);
+            break;
+    }
+    return result;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
diff --git a/cvmx-helper.h b/cvmx-helper.h
new file mode 100644
index 0000000000000..1c0226afc0373
--- /dev/null
+++ b/cvmx-helper.h
@@ -0,0 +1,259 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Helper functions for common, but complicated tasks.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_HELPER_H__
+#define __CVMX_HELPER_H__
+
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx-fpa.h"
+#include "cvmx-wqe.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    CVMX_HELPER_INTERFACE_MODE_DISABLED,
+    CVMX_HELPER_INTERFACE_MODE_RGMII,
+    CVMX_HELPER_INTERFACE_MODE_GMII,
+    CVMX_HELPER_INTERFACE_MODE_SPI,
+    CVMX_HELPER_INTERFACE_MODE_PCIE,
+    CVMX_HELPER_INTERFACE_MODE_XAUI,
+    CVMX_HELPER_INTERFACE_MODE_SGMII,
+    CVMX_HELPER_INTERFACE_MODE_PICMG,
+    CVMX_HELPER_INTERFACE_MODE_NPI,
+    CVMX_HELPER_INTERFACE_MODE_LOOP,
+} cvmx_helper_interface_mode_t;
+
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t    reserved_20_63  : 44;
+        uint64_t    link_up         : 1;    /**< Is the physical link up? */
+        uint64_t    full_duplex     : 1;    /**< 1 if the link is full duplex */
+        uint64_t    speed           : 18;   /**< Speed of the link in Mbps */
+    } s;
+} cvmx_helper_link_info_t;
+
+#include "cvmx-helper-fpa.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+#include "cvmx-helper-errata.h"
+#include "cvmx-helper-loop.h"
+#include "cvmx-helper-npi.h"
+#include "cvmx-helper-rgmii.h"
+#include "cvmx-helper-sgmii.h"
+#include "cvmx-helper-spi.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-xaui.h"
+
+/**
+ * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * priorities[16]) is a function pointer. It is meant to allow
+ * customization of the PKO queue priorities based on the port
+ * number. Users should set this pointer to a function before
+ * calling any cvmx-helper operations.
+ */
+extern void (*cvmx_override_pko_queue_priority)(int pko_port, uint64_t priorities[16]);
+
+/**
+ * cvmx_override_ipd_port_setup(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the IPD port
+ * setup before packet input/output comes online. It is called
+ * after cvmx-helper does the default IPD configuration, but
+ * before IPD is enabled. Users should set this pointer to a
+ * function before calling any cvmx-helper operations.
+ */
+extern void (*cvmx_override_ipd_port_setup)(int ipd_port);
+
+/**
+ * This function enables the IPD and also enables the packet interfaces.
+ * The packet interfaces (RGMII and SPI) must be enabled after the
+ * IPD.  This should be called by the user program after any additional
+ * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
+ * is not set in the executive-config.h file.
+ *
+ * @return 0 on success
+ *         -1 on failure
+ */
+extern int cvmx_helper_ipd_and_packet_input_enable(void);
+
+/**
+ * Initialize the PIP, IPD, and PKO hardware to support
+ * simple priority based queues for the ethernet ports. Each
+ * port is configured with a number of priority queues based
+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
+ * priority than the previous.
+ *
+ * @return Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_initialize_packet_io_global(void);
+
+/**
+ * Does core local initialization for packet io
+ *
+ * @return Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_initialize_packet_io_local(void);
+
+/**
+ * Returns the number of ports on the given interface.
+ * The interface must be initialized before the port count
+ * can be returned.
+ *
+ * @param interface Which interface to return port count for.
+ *
+ * @return Port count for interface
+ *         -1 for uninitialized interface
+ */
+extern int cvmx_helper_ports_on_interface(int interface);
+
+/**
+ * Return the number of interfaces the chip has. Each interface
+ * may have multiple ports. Most chips support two interfaces,
+ * but the CNX0XX and CNX1XX are exceptions. These only support
+ * one interface.
+ *
+ * @return Number of interfaces on chip
+ */
+extern int cvmx_helper_get_number_of_interfaces(void);
+
+/**
+ * Get the operating mode of an interface. Depending on the Octeon
+ * chip and configuration, this function returns an enumeration
+ * of the type of packet I/O supported by an interface.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Mode of the interface. Unknown or unsupported interfaces return
+ *         DISABLED.
+ */
+extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface);
+
+/**
+ * Auto configure an IPD/PKO port link state and speed. This
+ * function basically does the equivalent of:
+ * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
+ *
+ * @param ipd_port IPD/PKO port to auto configure
+ *
+ * @return Link state after configure
+ */
+extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @param ipd_port  IPD/PKO port to configure
+ * @param link_info The new link state
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info);
+
+
+
+/**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @param interface Interface to probe
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int cvmx_helper_interface_probe(int interface);
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @param ipd_port IPD/PKO port to loopback.
+ * @param enable_internal
+ *                 Non zero if you want internal loopback
+ * @param enable_external
+ *                 Non zero if you want external loopback
+ *
+ * @return Zero on success, negative on failure.
+ */
+extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, int enable_external);
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_HELPER_H__ */
diff --git a/cvmx-higig.h b/cvmx-higig.h
new file mode 100644
index 0000000000000..02eeda204706b
--- /dev/null
+++ b/cvmx-higig.h
@@ -0,0 +1,283 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over
+ * XAUI.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_HIGIG_H__
+#define __CVMX_HIGIG_H__
+#include "cvmx-wqe.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t start          : 8; /**< 8-bits of Preamble indicating start of frame */
+            uint32_t dst_modid_6    : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
+                                            DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field
+                                            value of b'01' this field should be b'1'. For all other values of HGI it is don't
+                                            care. */
+            uint32_t src_modid_6    : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
+                                            SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field
+                                            value of b'01' this field should be b'0'. For all other values of HGI it is don't
+                                            care. */
+            uint32_t hdr_ext_len    : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
+                                            to the standard 12-bytes of XGS HiGig header. Each unit represents 4
+                                            bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
+                                            and b'111' are reserved. For HGI field value of b'01' this field should be
+                                            b'01'. For all other values of HGI it is don't care. */
+            uint32_t cng_high       : 1; /**< Congestion Bit High flag */
+            uint32_t hgi            : 2; /**< HiGig interface format indicator
+                                            00 = Reserved
+                                            01 = Pure preamble - IEEE standard framing of 10GE
+                                            10 = XGS header - framing based on XGS family definition In this
+                                                format, the default length of the header is 12 bytes and additional
+                                                bytes are indicated by the HDR_EXT_LEN field
+                                            11 = Reserved */
+            uint32_t vid_high       : 8; /**< 8-bits of the VLAN tag information */
+            uint32_t vid_low        : 8; /**< 8 bits LSB of the VLAN tag information */
+        } s;
+    } dw0;
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t opcode         : 3; /**< XGS HiGig op-code, indicating the type of packet
+                                            000 =     Control frames used for CPU to CPU communications
+                                            001 =     Unicast packet with destination resolved; The packet can be
+                                                      either Layer 2 unicast packet or L3 unicast packet that was
+                                                      routed in the ingress chip.
+                                            010 =     Broadcast or unknown Unicast packet or unknown multicast,
+                                                      destined to all members of the VLAN
+                                            011 =     L2 Multicast packet, destined to all ports of the group indicated
+                                                      in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields
+                                            100 =     IP Multicast packet, destined to all ports of the group indicated
+                                                      in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields
+                                            101 =     Reserved
+                                            110 =     Reserved
+                                            111 =     Reserved */
+            uint32_t src_modid_low  : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit
+                                            5 is in Byte 9 and bit 6 Is in Byte 1) */
+            uint32_t src_port_tgid  : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
+                                            on, else it represents the physical port the packet ingressed on. */
+            uint32_t pfm            : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
+                                            multicast (unknown L2 multicast and IPMC) packets. This field is used
+                                            when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
+                                            For registered L2 multicast packets:
+                                                PFM= 0 ­ Flood to VLAN
+                                                PFM= 1 or 2 ­ Send to group members in the L2MC table
+                                            For unregistered L2 multicast packets:
+                                                PFM= 0 or 1 ­ Flood to VLAN
+                                                PFM= 2 ­ Drop the packet */
+            uint32_t priority       : 3; /**< This is the internal priority of the packet. This internal priority will go through
+                                            COS_SEL mapping registers to map to the actual MMU queues. */
+            uint32_t dst_port       : 5; /**< Port number of destination port on which the packet needs to egress. */
+            uint32_t dst_modid_low  : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
+            uint32_t cng_low        : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following
+                                            encodings are to make it backward compatible:
+                                            {CNG_HIGH, CNG_LOW] - COLOR
+                                            [0, 0] ­ Packet is green
+                                            [0, 1] ­ Packet is red
+                                            [1, 1] ­ Packet is yellow
+                                            [1, 0] ­ Undefined */
+            uint32_t header_type    : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header
+                                            00 = Overlay 1 (default)
+                                            01 = Overlay 2 (Classification Tag)
+                                            10 = Reserved
+                                            11 = Reserved */
+        } s;
+    } dw1;
+    union
+    {
+        uint32_t u32;
+        struct
+        {
+            uint32_t mirror         : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
+                                            packet was switched and only needs to be mirrored. */
+            uint32_t mirror_done    : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
+                                            may still need to be switched. */
+            uint32_t mirror_only    : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
+                                            needs to be mirrored. */
+            uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
+                                            ingressed the system. */
+            uint32_t dst_tgid       : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
+                                            DO_NOT_LEARN bit is overlaid on the second bit of this field. */
+            uint32_t dst_t          : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk
+                                            group. */
+            uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */
+            uint32_t label_present  : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
+                                            added field. */
+            uint32_t l3             : 1; /**< L3: Indicates that the packet is L3 switched */
+            uint32_t dst_modid_5    : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6
+                                            is in byte 1) */
+            uint32_t src_modid_5    : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in
+                                            byte 1) */
+            uint32_t vc_label_0_15  : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */
+        } o1;
+        struct
+        {
+            uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */
+            uint32_t reserved_0_15  : 16;
+
+        } o2;
+    } dw2;
+} cvmx_higig_header_t;
+
+
+/**
+ * Initialize the HiGig aspects of a XAUI interface. This function
+ * should be called before the cvmx-helper generic init.
+ *
+ * @param interface Interface to initialize HiGig on (0-1)
+ * @param enable_higig2
+ *                  Non zero to enable HiGig2 support. Zero to support HiGig
+ *                  and HiGig+.
+ *
+ * @return Zero on success, negative on failure
+ */
+static inline int cvmx_higig_initialize(int interface, int enable_higig2)
+{
+    cvmx_pip_prt_cfgx_t pip_prt_cfg;
+    cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp;
+    cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt;
+    cvmx_gmxx_txx_append_t gmx_tx_append;
+    cvmx_gmxx_tx_ifg_t gmx_tx_ifg;
+    cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp;
+    cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl;
+    cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl;
+    int i;
+    int header_size = (enable_higig2) ? 16 : 12;
+
+    /* Setup PIP to handle HiGig */
+    pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16));
+    pip_prt_cfg.s.dsa_en = 0;
+    pip_prt_cfg.s.higig_en = 1;
+    pip_prt_cfg.s.hg_qos = 1;
+    pip_prt_cfg.s.skip = header_size;
+    cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64);
+
+    /* Setup some sample QoS defaults. These can be changed later */
+    for (i=0; i<64; i++)
+    {
+        cvmx_pip_hg_pri_qos_t pip_hg_pri_qos;
+        pip_hg_pri_qos.u64 = 0;
+        pip_hg_pri_qos.s.up_qos = 1;
+        pip_hg_pri_qos.s.pri = i;
+        pip_hg_pri_qos.s.qos = i&7;
+        cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64);
+    }
+
+    /* Setup GMX RX to treat the HiGig header as user data to ignore */
+    gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface));
+    gmx_rx_udd_skp.s.len = header_size;
+    gmx_rx_udd_skp.s.fcssel = 0;
+    cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64);
+
+    /* Disable GMX preamble checking */
+    gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface));
+    gmx_rx_frm_ctl.s.pre_chk = 0;
+    cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64);
+
+    /* Setup GMX TX to pad properly min sized packets */
+    gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface));
+    gmx_tx_min_pkt.s.min_size = 59 + header_size;
+    cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64);
+
+    /* Setup GMX TX to not add a preamble */
+    gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
+    gmx_tx_append.s.preamble = 0;
+    cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64);
+
+    /* Reduce the inter frame gap to 8 bytes */
+    gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface));
+    gmx_tx_ifg.s.ifg1 = 4;
+    gmx_tx_ifg.s.ifg2 = 4;
+    cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64);
+
+    /* Disable GMX backpressure */
+    gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
+    gmx_tx_ovr_bp.s.bp = 0;
+    gmx_tx_ovr_bp.s.en = 0xf;
+    gmx_tx_ovr_bp.s.ign_full = 0xf;
+    cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
+
+    if (enable_higig2)
+    {
+        /* Enable HiGig2 support and forwarding of virtual port backpressure
+            to PKO */
+        cvmx_gmxx_hg2_control_t gmx_hg2_control;
+        gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
+        gmx_hg2_control.s.hg2rx_en = 1;
+        gmx_hg2_control.s.hg2tx_en = 1;
+        gmx_hg2_control.s.logl_en = 0xffff;
+        gmx_hg2_control.s.phys_en = 1;
+        cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64);
+    }
+
+    /* Enable HiGig */
+    gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+    gmx_tx_xaui_ctl.s.hg_en = 1;
+    cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64);
+
+    return 0;
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif //  __CVMX_HIGIG_H__
diff --git a/cvmx-interrupt-decodes.c b/cvmx-interrupt-decodes.c
new file mode 100644
index 0000000000000..0902492bd75c9
--- /dev/null
+++ b/cvmx-interrupt-decodes.c
@@ -0,0 +1,3584 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Automatically generated functions useful for enabling
+ * and decoding RSL_INT_BLOCKS interrupts.
+ *
+ * This file is auto generated. Do not edit.
+ *
+ * <hr>$Revision$<hr>
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-interrupt.h"
+#include "cvmx-pcie.h"
+
+#ifndef PRINT_ERROR
+#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
+#endif
+
+void __cvmx_interrupt_pci_int_enb2_enable(void);
+void __cvmx_interrupt_pci_int_sum2_decode(void);
+void __cvmx_interrupt_pescx_dbg_info_en_enable(int index);
+void __cvmx_interrupt_pescx_dbg_info_decode(int index);
+
+/**
+ * __cvmx_interrupt_agl_gmx_rxx_int_en_enable enables all interrupt bits in cvmx_agl_gmx_rxx_int_en_t
+ */
+void __cvmx_interrupt_agl_gmx_rxx_int_en_enable(int index)
+{
+    cvmx_agl_gmx_rxx_int_en_t agl_gmx_rx_int_en;
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_REG(index), cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_REG(index)));
+    agl_gmx_rx_int_en.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping agl_gmx_rx_int_en.s.reserved_20_63
+        agl_gmx_rx_int_en.s.pause_drp = 1;
+        // Skipping agl_gmx_rx_int_en.s.reserved_16_18
+        agl_gmx_rx_int_en.s.ifgerr = 1;
+        //agl_gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //agl_gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //agl_gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //agl_gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        agl_gmx_rx_int_en.s.ovrerr = 1;
+        // Skipping agl_gmx_rx_int_en.s.reserved_9_9
+        agl_gmx_rx_int_en.s.skperr = 1;
+        agl_gmx_rx_int_en.s.rcverr = 1;
+        agl_gmx_rx_int_en.s.lenerr = 1;
+        agl_gmx_rx_int_en.s.alnerr = 1;
+        agl_gmx_rx_int_en.s.fcserr = 1;
+        agl_gmx_rx_int_en.s.jabber = 1;
+        agl_gmx_rx_int_en.s.maxerr = 1;
+        // Skipping agl_gmx_rx_int_en.s.reserved_1_1
+        agl_gmx_rx_int_en.s.minerr = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping agl_gmx_rx_int_en.s.reserved_20_63
+        agl_gmx_rx_int_en.s.pause_drp = 1;
+        // Skipping agl_gmx_rx_int_en.s.reserved_16_18
+        agl_gmx_rx_int_en.s.ifgerr = 1;
+        //agl_gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //agl_gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //agl_gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //agl_gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        agl_gmx_rx_int_en.s.ovrerr = 1;
+        // Skipping agl_gmx_rx_int_en.s.reserved_9_9
+        agl_gmx_rx_int_en.s.skperr = 1;
+        agl_gmx_rx_int_en.s.rcverr = 1;
+        agl_gmx_rx_int_en.s.lenerr = 1;
+        agl_gmx_rx_int_en.s.alnerr = 1;
+        agl_gmx_rx_int_en.s.fcserr = 1;
+        agl_gmx_rx_int_en.s.jabber = 1;
+        agl_gmx_rx_int_en.s.maxerr = 1;
+        // Skipping agl_gmx_rx_int_en.s.reserved_1_1
+        agl_gmx_rx_int_en.s.minerr = 1;
+    }
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_EN(index), agl_gmx_rx_int_en.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_agl_gmx_rxx_int_reg_decode decodes all interrupt bits in cvmx_agl_gmx_rxx_int_reg_t
+ */
+void __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(int index)
+{
+    cvmx_agl_gmx_rxx_int_reg_t agl_gmx_rx_int_reg;
+    agl_gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_REG(index));
+    agl_gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_AGL_GMX_RXX_INT_EN(index));
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_INT_REG(index), agl_gmx_rx_int_reg.u64);
+    // Skipping agl_gmx_rx_int_reg.s.reserved_20_63
+    if (agl_gmx_rx_int_reg.s.pause_drp)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[PAUSE_DRP]: Pause packet was dropped due to full GMX RX FIFO\n", index);
+    // Skipping agl_gmx_rx_int_reg.s.reserved_16_18
+    if (agl_gmx_rx_int_reg.s.ifgerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[IFGERR]: Interframe Gap Violation\n"
+                    "    Does not necessarily indicate a failure\n", index);
+    if (agl_gmx_rx_int_reg.s.coldet)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[COLDET]: Collision Detection\n", index);
+    if (agl_gmx_rx_int_reg.s.falerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[FALERR]: False carrier error or extend error after slottime\n", index);
+    if (agl_gmx_rx_int_reg.s.rsverr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[RSVERR]: MII reserved opcodes\n", index);
+    if (agl_gmx_rx_int_reg.s.pcterr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[PCTERR]: Bad Preamble / Protocol\n", index);
+    if (agl_gmx_rx_int_reg.s.ovrerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[OVRERR]: Internal Data Aggregation Overflow\n"
+                    "    This interrupt should never assert\n", index);
+    // Skipping agl_gmx_rx_int_reg.s.reserved_9_9
+    if (agl_gmx_rx_int_reg.s.skperr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[SKPERR]: Skipper error\n", index);
+    if (agl_gmx_rx_int_reg.s.rcverr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[RCVERR]: Frame was received with MII Data reception error\n", index);
+    if (agl_gmx_rx_int_reg.s.lenerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[LENERR]: Frame was received with length error\n", index);
+    if (agl_gmx_rx_int_reg.s.alnerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[ALNERR]: Frame was received with an alignment error\n", index);
+    if (agl_gmx_rx_int_reg.s.fcserr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[FCSERR]: Frame was received with FCS/CRC error\n", index);
+    if (agl_gmx_rx_int_reg.s.jabber)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[JABBER]: Frame was received with length > sys_length\n", index);
+    if (agl_gmx_rx_int_reg.s.maxerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[MAXERR]: Frame was received with length > max_length\n", index);
+    // Skipping agl_gmx_rx_int_reg.s.reserved_1_1
+    if (agl_gmx_rx_int_reg.s.minerr)
+        PRINT_ERROR("AGL_GMX_RX%d_INT_REG[MINERR]: Frame was received with length < min_length\n", index);
+}
+
+
+/**
+ * __cvmx_interrupt_fpa_int_enb_enable enables all interrupt bits in cvmx_fpa_int_enb_t
+ */
+void __cvmx_interrupt_fpa_int_enb_enable(void)
+{
+    cvmx_fpa_int_enb_t fpa_int_enb;
+    cvmx_write_csr(CVMX_FPA_INT_SUM, cvmx_read_csr(CVMX_FPA_INT_SUM));
+    fpa_int_enb.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping fpa_int_enb.s.reserved_28_63
+        fpa_int_enb.s.q7_perr = 1;
+        fpa_int_enb.s.q7_coff = 1;
+        fpa_int_enb.s.q7_und = 1;
+        fpa_int_enb.s.q6_perr = 1;
+        fpa_int_enb.s.q6_coff = 1;
+        fpa_int_enb.s.q6_und = 1;
+        fpa_int_enb.s.q5_perr = 1;
+        fpa_int_enb.s.q5_coff = 1;
+        fpa_int_enb.s.q5_und = 1;
+        fpa_int_enb.s.q4_perr = 1;
+        fpa_int_enb.s.q4_coff = 1;
+        fpa_int_enb.s.q4_und = 1;
+        fpa_int_enb.s.q3_perr = 1;
+        fpa_int_enb.s.q3_coff = 1;
+        fpa_int_enb.s.q3_und = 1;
+        fpa_int_enb.s.q2_perr = 1;
+        fpa_int_enb.s.q2_coff = 1;
+        fpa_int_enb.s.q2_und = 1;
+        fpa_int_enb.s.q1_perr = 1;
+        fpa_int_enb.s.q1_coff = 1;
+        fpa_int_enb.s.q1_und = 1;
+        fpa_int_enb.s.q0_perr = 1;
+        fpa_int_enb.s.q0_coff = 1;
+        fpa_int_enb.s.q0_und = 1;
+        fpa_int_enb.s.fed1_dbe = 1;
+        fpa_int_enb.s.fed1_sbe = 1;
+        fpa_int_enb.s.fed0_dbe = 1;
+        fpa_int_enb.s.fed0_sbe = 1;
+    }
+    cvmx_write_csr(CVMX_FPA_INT_ENB, fpa_int_enb.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_fpa_int_sum_decode decodes all interrupt bits in cvmx_fpa_int_sum_t
+ */
+void __cvmx_interrupt_fpa_int_sum_decode(void)
+{
+    cvmx_fpa_int_sum_t fpa_int_sum;
+    fpa_int_sum.u64 = cvmx_read_csr(CVMX_FPA_INT_SUM);
+    fpa_int_sum.u64 &= cvmx_read_csr(CVMX_FPA_INT_ENB);
+    cvmx_write_csr(CVMX_FPA_INT_SUM, fpa_int_sum.u64);
+    // Skipping fpa_int_sum.s.reserved_28_63
+    if (fpa_int_sum.s.q7_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q7_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q7_und)
+        PRINT_ERROR("FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q6_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q6_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q6_und)
+        PRINT_ERROR("FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q5_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q5_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q5_und)
+        PRINT_ERROR("FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q4_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q4_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q4_und)
+        PRINT_ERROR("FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q3_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q3_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q3_und)
+        PRINT_ERROR("FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q2_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q2_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q2_und)
+        PRINT_ERROR("FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q1_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q1_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q1_und)
+        PRINT_ERROR("FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.q0_perr)
+        PRINT_ERROR("FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
+                    "    the L2C does not have the FPA owner ship bit set.\n");
+    if (fpa_int_sum.s.q0_coff)
+        PRINT_ERROR("FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
+                    "    the count available is greater than pointers\n"
+                    "    present in the FPA.\n");
+    if (fpa_int_sum.s.q0_und)
+        PRINT_ERROR("FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
+                    "    negative.\n");
+    if (fpa_int_sum.s.fed1_dbe)
+        PRINT_ERROR("FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n");
+    if (fpa_int_sum.s.fed1_sbe)
+        PRINT_ERROR("FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n");
+    if (fpa_int_sum.s.fed0_dbe)
+        PRINT_ERROR("FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n");
+    if (fpa_int_sum.s.fed0_sbe)
+        PRINT_ERROR("FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n");
+}
+
+
+/**
+ * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t
+ */
+void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
+{
+    cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
+    gmx_rx_int_en.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_29_63
+        gmx_rx_int_en.s.hg2cc = 1;
+        gmx_rx_int_en.s.hg2fld = 1;
+        gmx_rx_int_en.s.undat = 1;
+        gmx_rx_int_en.s.uneop = 1;
+        gmx_rx_int_en.s.unsop = 1;
+        gmx_rx_int_en.s.bad_term = 1;
+        gmx_rx_int_en.s.bad_seq = 1;
+        gmx_rx_int_en.s.rem_fault = 1;
+        gmx_rx_int_en.s.loc_fault = 1;
+        gmx_rx_int_en.s.pause_drp = 1;
+        // Skipping gmx_rx_int_en.s.reserved_16_18
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        // Skipping gmx_rx_int_en.s.reserved_9_9
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        // Skipping gmx_rx_int_en.s.reserved_5_6
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        // Skipping gmx_rx_int_en.s.reserved_2_2
+        gmx_rx_int_en.s.carext = 1;
+        // Skipping gmx_rx_int_en.s.reserved_0_0
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_19_63
+        //gmx_rx_int_en.s.phy_dupx = 1;
+        //gmx_rx_int_en.s.phy_spd = 1;
+        //gmx_rx_int_en.s.phy_link = 1;
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        gmx_rx_int_en.s.niberr = 1;
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
+        gmx_rx_int_en.s.alnerr = 1;
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        gmx_rx_int_en.s.maxerr = 1;
+        gmx_rx_int_en.s.carext = 1;
+        gmx_rx_int_en.s.minerr = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_20_63
+        gmx_rx_int_en.s.pause_drp = 1;
+        //gmx_rx_int_en.s.phy_dupx = 1;
+        //gmx_rx_int_en.s.phy_spd = 1;
+        //gmx_rx_int_en.s.phy_link = 1;
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        gmx_rx_int_en.s.niberr = 1;
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        // Skipping gmx_rx_int_en.s.reserved_6_6
+        gmx_rx_int_en.s.alnerr = 1;
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        // Skipping gmx_rx_int_en.s.reserved_2_2
+        gmx_rx_int_en.s.carext = 1;
+        // Skipping gmx_rx_int_en.s.reserved_0_0
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_19_63
+        //gmx_rx_int_en.s.phy_dupx = 1;
+        //gmx_rx_int_en.s.phy_spd = 1;
+        //gmx_rx_int_en.s.phy_link = 1;
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        gmx_rx_int_en.s.niberr = 1;
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
+        gmx_rx_int_en.s.alnerr = 1;
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        gmx_rx_int_en.s.maxerr = 1;
+        gmx_rx_int_en.s.carext = 1;
+        gmx_rx_int_en.s.minerr = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_19_63
+        //gmx_rx_int_en.s.phy_dupx = 1;
+        //gmx_rx_int_en.s.phy_spd = 1;
+        //gmx_rx_int_en.s.phy_link = 1;
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        gmx_rx_int_en.s.niberr = 1;
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
+        gmx_rx_int_en.s.alnerr = 1;
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        gmx_rx_int_en.s.maxerr = 1;
+        gmx_rx_int_en.s.carext = 1;
+        gmx_rx_int_en.s.minerr = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_20_63
+        gmx_rx_int_en.s.pause_drp = 1;
+        //gmx_rx_int_en.s.phy_dupx = 1;
+        //gmx_rx_int_en.s.phy_spd = 1;
+        //gmx_rx_int_en.s.phy_link = 1;
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        gmx_rx_int_en.s.niberr = 1;
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        //gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work
+        gmx_rx_int_en.s.alnerr = 1;
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        gmx_rx_int_en.s.maxerr = 1;
+        gmx_rx_int_en.s.carext = 1;
+        gmx_rx_int_en.s.minerr = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping gmx_rx_int_en.s.reserved_29_63
+        gmx_rx_int_en.s.hg2cc = 1;
+        gmx_rx_int_en.s.hg2fld = 1;
+        gmx_rx_int_en.s.undat = 1;
+        gmx_rx_int_en.s.uneop = 1;
+        gmx_rx_int_en.s.unsop = 1;
+        gmx_rx_int_en.s.bad_term = 1;
+        gmx_rx_int_en.s.bad_seq = 0;
+        gmx_rx_int_en.s.rem_fault = 1;
+        gmx_rx_int_en.s.loc_fault = 0;
+        gmx_rx_int_en.s.pause_drp = 1;
+        // Skipping gmx_rx_int_en.s.reserved_16_18
+        //gmx_rx_int_en.s.ifgerr = 1;
+        //gmx_rx_int_en.s.coldet = 1; // Collsion detect
+        //gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime
+        //gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes
+        //gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol
+        gmx_rx_int_en.s.ovrerr = 1;
+        // Skipping gmx_rx_int_en.s.reserved_9_9
+        gmx_rx_int_en.s.skperr = 1;
+        gmx_rx_int_en.s.rcverr = 1;
+        // Skipping gmx_rx_int_en.s.reserved_5_6
+        //gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work
+        gmx_rx_int_en.s.jabber = 1;
+        // Skipping gmx_rx_int_en.s.reserved_2_2
+        gmx_rx_int_en.s.carext = 1;
+        // Skipping gmx_rx_int_en.s.reserved_0_0
+    }
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_gmxx_rxx_int_reg_decode decodes all interrupt bits in cvmx_gmxx_rxx_int_reg_t
+ */
+void __cvmx_interrupt_gmxx_rxx_int_reg_decode(int index, int block)
+{
+    cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
+    gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block));
+    /* Don't clear inband status bits so someone else can use them */
+    gmx_rx_int_reg.s.phy_dupx = 0;
+    gmx_rx_int_reg.s.phy_spd = 0;
+    gmx_rx_int_reg.s.phy_link = 0;
+    gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, block));
+    cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), gmx_rx_int_reg.u64);
+    // Skipping gmx_rx_int_reg.s.reserved_29_63
+    if (gmx_rx_int_reg.s.hg2cc)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[HG2CC]: HiGig2 received message CRC or Control char  error\n"
+                    "    Set when either CRC8 error detected or when\n"
+                    "    a Control Character is found in the message\n"
+                    "    bytes after the K.SOM\n"
+                    "    NOTE: HG2CC has higher priority than HG2FLD\n"
+                    "          i.e. a HiGig2 message that results in HG2CC\n"
+                    "          getting set, will never set HG2FLD.\n", block, index);
+    if (gmx_rx_int_reg.s.hg2fld)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[HG2FLD]: HiGig2 received message field error, as below\n"
+                    "    1) MSG_TYPE field not 6'b00_0000\n"
+                    "       i.e. it is not a FLOW CONTROL message, which\n"
+                    "       is the only defined type for HiGig2\n"
+                    "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
+                    "       which is the only defined type for HiGig2\n"
+                    "    3) FC_OBJECT field is neither 4'b0000 for\n"
+                    "       Physical Link nor 4'b0010 for Logical Link.\n"
+                    "       Those are the only two defined types in HiGig2\n", block, index);
+    if (gmx_rx_int_reg.s.undat)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[UNDAT]: Unexpected Data\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.uneop)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[UNEOP]: Unexpected EOP\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.unsop)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[UNSOP]: Unexpected SOP\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.bad_term)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[BAD_TERM]: Frame is terminated by control character other\n"
+                    "    than /T/.  The error propagation control\n"
+                    "    character /E/ will be included as part of the\n"
+                    "    frame and does not cause a frame termination.\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.bad_seq)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[BAD_SEQ]: Reserved Sequence Deteted\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.rem_fault)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[REM_FAULT]: Remote Fault Sequence Deteted\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.loc_fault)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[LOC_FAULT]: Local Fault Sequence Deteted\n"
+                    "    (XAUI Mode only)\n", block, index);
+    if (gmx_rx_int_reg.s.pause_drp)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[PAUSE_DRP]: Pause packet was dropped due to full GMX RX FIFO\n", block, index);
+#if 0
+    if (gmx_rx_int_reg.s.phy_dupx)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_DUPX]: Change in the RMGII inbound LinkDuplex\n", block, index);
+    if (gmx_rx_int_reg.s.phy_spd)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_SPD]: Change in the RMGII inbound LinkSpeed\n", block, index);
+    if (gmx_rx_int_reg.s.phy_link)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[PHY_LINK]: Change in the RMGII inbound LinkStatus\n", block, index);
+#endif
+    if (gmx_rx_int_reg.s.ifgerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[IFGERR]: Interframe Gap Violation\n"
+                    "    Does not necessarily indicate a failure\n", block, index);
+    if (gmx_rx_int_reg.s.coldet)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[COLDET]: Collision Detection\n", block, index);
+    if (gmx_rx_int_reg.s.falerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[FALERR]: False carrier error or extend error after slottime\n", block, index);
+    if (gmx_rx_int_reg.s.rsverr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[RSVERR]: RGMII reserved opcodes\n", block, index);
+    if (gmx_rx_int_reg.s.pcterr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[PCTERR]: Bad Preamble / Protocol\n", block, index);
+    if (gmx_rx_int_reg.s.ovrerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[OVRERR]: Internal Data Aggregation Overflow\n"
+                    "    This interrupt should never assert\n", block, index);
+    if (gmx_rx_int_reg.s.niberr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n", block, index);
+    if (gmx_rx_int_reg.s.skperr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[SKPERR]: Skipper error\n", block, index);
+    if (gmx_rx_int_reg.s.rcverr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[RCVERR]: Frame was received with RMGII Data reception error\n", block, index);
+    if (gmx_rx_int_reg.s.lenerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[LENERR]: Frame was received with length error\n", block, index);
+    if (gmx_rx_int_reg.s.alnerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[ALNERR]: Frame was received with an alignment error\n", block, index);
+    if (gmx_rx_int_reg.s.fcserr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[FCSERR]: Frame was received with FCS/CRC error\n", block, index);
+    if (gmx_rx_int_reg.s.jabber)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[JABBER]: Frame was received with length > sys_length\n", block, index);
+    if (gmx_rx_int_reg.s.maxerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[MAXERR]: Frame was received with length > max_length\n", block, index);
+    if (gmx_rx_int_reg.s.carext)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[CAREXT]: RGMII carrier extend error\n", block, index);
+    if (gmx_rx_int_reg.s.minerr)
+        PRINT_ERROR("GMX%d_RX%d_INT_REG[MINERR]: Frame was received with length < min_length\n", block, index);
+}
+
+
+/**
+ * __cvmx_interrupt_iob_int_enb_enable enables all interrupt bits in cvmx_iob_int_enb_t
+ */
+void __cvmx_interrupt_iob_int_enb_enable(void)
+{
+    cvmx_iob_int_enb_t iob_int_enb;
+    cvmx_write_csr(CVMX_IOB_INT_SUM, cvmx_read_csr(CVMX_IOB_INT_SUM));
+    iob_int_enb.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping iob_int_enb.s.reserved_6_63
+        iob_int_enb.s.p_dat = 1;
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        /* These interrupts are disabled on CN56XXp2.X due to errata IOB-800 */
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X))
+        {
+            iob_int_enb.s.np_dat = 1;
+            iob_int_enb.s.np_eop = 1;
+            iob_int_enb.s.np_sop = 1;
+        }
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping iob_int_enb.s.reserved_4_63
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        iob_int_enb.s.np_eop = 1;
+        iob_int_enb.s.np_sop = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping iob_int_enb.s.reserved_6_63
+        iob_int_enb.s.p_dat = 1;
+        iob_int_enb.s.np_dat = 1;
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        iob_int_enb.s.np_eop = 1;
+        iob_int_enb.s.np_sop = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping iob_int_enb.s.reserved_4_63
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        iob_int_enb.s.np_eop = 1;
+        iob_int_enb.s.np_sop = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping iob_int_enb.s.reserved_4_63
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        iob_int_enb.s.np_eop = 1;
+        iob_int_enb.s.np_sop = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping iob_int_enb.s.reserved_6_63
+        iob_int_enb.s.p_dat = 1;
+        iob_int_enb.s.np_dat = 1;
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        iob_int_enb.s.np_eop = 1;
+        iob_int_enb.s.np_sop = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping iob_int_enb.s.reserved_6_63
+        iob_int_enb.s.p_dat = 1;
+        iob_int_enb.s.p_eop = 1;
+        iob_int_enb.s.p_sop = 1;
+        /* These interrupts are disabled on CN52XXp2.X due to errata IOB-800 */
+        if (!OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X))
+        {
+            iob_int_enb.s.np_dat = 1;
+            iob_int_enb.s.np_eop = 1;
+            iob_int_enb.s.np_sop = 1;
+        }
+    }
+    cvmx_write_csr(CVMX_IOB_INT_ENB, iob_int_enb.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_iob_int_sum_decode decodes all interrupt bits in cvmx_iob_int_sum_t
+ */
+void __cvmx_interrupt_iob_int_sum_decode(void)
+{
+    cvmx_iob_int_sum_t iob_int_sum;
+    iob_int_sum.u64 = cvmx_read_csr(CVMX_IOB_INT_SUM);
+    iob_int_sum.u64 &= cvmx_read_csr(CVMX_IOB_INT_ENB);
+    cvmx_write_csr(CVMX_IOB_INT_SUM, iob_int_sum.u64);
+    // Skipping iob_int_sum.s.reserved_6_63
+    if (iob_int_sum.s.p_dat)
+        PRINT_ERROR("IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
+                    "    port for a passthrough packet.\n"
+                    "    The first detected error associated with bits [5:0]\n"
+                    "    of this register will only be set here. A new bit\n"
+                    "    can be set when the previous reported bit is cleared.\n");
+    if (iob_int_sum.s.np_dat)
+        PRINT_ERROR("IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
+                    "    port for a non-passthrough packet.\n"
+                    "    The first detected error associated with bits [5:0]\n"
+                    "    of this register will only be set here. A new bit\n"
+                    "    can be set when the previous reported bit is cleared.\n");
+    if (iob_int_sum.s.p_eop)
+        PRINT_ERROR("IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
+                    "    port for a passthrough packet.\n"
+                    "    The first detected error associated with bits [5:0]\n"
+                    "    of this register will only be set here. A new bit\n"
+                    "    can be set when the previous reported bit is cleared.\n");
+    if (iob_int_sum.s.p_sop)
+        PRINT_ERROR("IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
+                    "    port for a passthrough packet.\n"
+                    "    The first detected error associated with bits [5:0]\n"
+                    "    of this register will only be set here. A new bit\n"
+                    "    can be set when the previous reported bit is cleared.\n");
+    if (iob_int_sum.s.np_eop)
+        PRINT_ERROR("IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
+                    "    port for a non-passthrough packet.\n"
+                    "    The first detected error associated with bits [5:0]\n"
+                    "    of this register will only be set here. A new bit\n"
+                    "    can be set when the previous reported bit is cleared.\n");
+    if (iob_int_sum.s.np_sop)
+        PRINT_ERROR("IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
+                    "    port for a non-passthrough packet.\n"
+                    "    The first detected error associated with bits [5:0]\n"
+                    "    of this register will only be set here. A new bit\n"
+                    "    can be set when the previous reported bit is cleared.\n");
+}
+
+
+/**
+ * __cvmx_interrupt_ipd_int_enb_enable enables all interrupt bits in cvmx_ipd_int_enb_t
+ */
+void __cvmx_interrupt_ipd_int_enb_enable(void)
+{
+    cvmx_ipd_int_enb_t ipd_int_enb;
+    cvmx_write_csr(CVMX_IPD_INT_SUM, cvmx_read_csr(CVMX_IPD_INT_SUM));
+    ipd_int_enb.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_12_63
+        //ipd_int_enb.s.pq_sub = 1; // Disable per port backpressure overflow checking since it happens when not in use
+        //ipd_int_enb.s.pq_add = 1; // Disable per port backpressure overflow checking since it happens when not in use
+        ipd_int_enb.s.bc_ovr = 1;
+        ipd_int_enb.s.d_coll = 1;
+        ipd_int_enb.s.c_coll = 1;
+        ipd_int_enb.s.cc_ovr = 1;
+        ipd_int_enb.s.dc_ovr = 1;
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_5_63
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_10_63
+        ipd_int_enb.s.bc_ovr = 1;
+        ipd_int_enb.s.d_coll = 1;
+        ipd_int_enb.s.c_coll = 1;
+        ipd_int_enb.s.cc_ovr = 1;
+        ipd_int_enb.s.dc_ovr = 1;
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_10_63
+        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+        {
+            ipd_int_enb.s.bc_ovr = 1;
+            ipd_int_enb.s.d_coll = 1;
+            ipd_int_enb.s.c_coll = 1;
+            ipd_int_enb.s.cc_ovr = 1;
+            ipd_int_enb.s.dc_ovr = 1;
+        }
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_5_63
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_10_63
+        ipd_int_enb.s.bc_ovr = 1;
+        ipd_int_enb.s.d_coll = 1;
+        ipd_int_enb.s.c_coll = 1;
+        ipd_int_enb.s.cc_ovr = 1;
+        ipd_int_enb.s.dc_ovr = 1;
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping ipd_int_enb.s.reserved_12_63
+        //ipd_int_enb.s.pq_sub = 1; // Disable per port backpressure overflow checking since it happens when not in use
+        //ipd_int_enb.s.pq_add = 1; // Disable per port backpressure overflow checking since it happens when not in use
+        ipd_int_enb.s.bc_ovr = 1;
+        ipd_int_enb.s.d_coll = 1;
+        ipd_int_enb.s.c_coll = 1;
+        ipd_int_enb.s.cc_ovr = 1;
+        ipd_int_enb.s.dc_ovr = 1;
+        ipd_int_enb.s.bp_sub = 1;
+        ipd_int_enb.s.prc_par3 = 1;
+        ipd_int_enb.s.prc_par2 = 1;
+        ipd_int_enb.s.prc_par1 = 1;
+        ipd_int_enb.s.prc_par0 = 1;
+    }
+    cvmx_write_csr(CVMX_IPD_INT_ENB, ipd_int_enb.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_ipd_int_sum_decode decodes all interrupt bits in cvmx_ipd_int_sum_t
+ */
+void __cvmx_interrupt_ipd_int_sum_decode(void)
+{
+    cvmx_ipd_int_sum_t ipd_int_sum;
+    ipd_int_sum.u64 = cvmx_read_csr(CVMX_IPD_INT_SUM);
+    ipd_int_sum.u64 &= cvmx_read_csr(CVMX_IPD_INT_ENB);
+    cvmx_write_csr(CVMX_IPD_INT_SUM, ipd_int_sum.u64);
+    // Skipping ipd_int_sum.s.reserved_12_63
+    if (ipd_int_sum.s.pq_sub)
+        PRINT_ERROR("IPD_INT_SUM[PQ_SUB]: Set when a port-qos does an sub to the count\n"
+                    "    that causes the counter to wrap.\n");
+    if (ipd_int_sum.s.pq_add)
+        PRINT_ERROR("IPD_INT_SUM[PQ_ADD]: Set when a port-qos does an add to the count\n"
+                    "    that causes the counter to wrap.\n");
+    if (ipd_int_sum.s.bc_ovr)
+        PRINT_ERROR("IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
+                    "    This is a PASS-3 Field.\n");
+    if (ipd_int_sum.s.d_coll)
+        PRINT_ERROR("IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
+                    "    collides.\n"
+                    "    This is a PASS-3 Field.\n");
+    if (ipd_int_sum.s.c_coll)
+        PRINT_ERROR("IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
+                    "    collides.\n"
+                    "    This is a PASS-3 Field.\n");
+    if (ipd_int_sum.s.cc_ovr)
+        PRINT_ERROR("IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
+                    "    This is a PASS-3 Field.\n");
+    if (ipd_int_sum.s.dc_ovr)
+        PRINT_ERROR("IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
+                    "    This is a PASS-3 Field.\n");
+    if (ipd_int_sum.s.bp_sub)
+        PRINT_ERROR("IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
+                    "    supplied illegal value.\n");
+    if (ipd_int_sum.s.prc_par3)
+        PRINT_ERROR("IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
+                    "    [127:96] of the PBM memory.\n");
+    if (ipd_int_sum.s.prc_par2)
+        PRINT_ERROR("IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
+                    "    [95:64] of the PBM memory.\n");
+    if (ipd_int_sum.s.prc_par1)
+        PRINT_ERROR("IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
+                    "    [63:32] of the PBM memory.\n");
+    if (ipd_int_sum.s.prc_par0)
+        PRINT_ERROR("IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
+                    "    [31:0] of the PBM memory.\n");
+}
+
+
+/**
+ * __cvmx_interrupt_key_int_enb_enable enables all interrupt bits in cvmx_key_int_enb_t
+ */
+void __cvmx_interrupt_key_int_enb_enable(void)
+{
+    cvmx_key_int_enb_t key_int_enb;
+    cvmx_write_csr(CVMX_KEY_INT_SUM, cvmx_read_csr(CVMX_KEY_INT_SUM));
+    key_int_enb.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping key_int_enb.s.reserved_4_63
+        key_int_enb.s.ked1_dbe = 1;
+        key_int_enb.s.ked1_sbe = 1;
+        key_int_enb.s.ked0_dbe = 1;
+        key_int_enb.s.ked0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping key_int_enb.s.reserved_4_63
+        key_int_enb.s.ked1_dbe = 1;
+        key_int_enb.s.ked1_sbe = 1;
+        key_int_enb.s.ked0_dbe = 1;
+        key_int_enb.s.ked0_sbe = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping key_int_enb.s.reserved_4_63
+        key_int_enb.s.ked1_dbe = 1;
+        key_int_enb.s.ked1_sbe = 1;
+        key_int_enb.s.ked0_dbe = 1;
+        key_int_enb.s.ked0_sbe = 1;
+    }
+    cvmx_write_csr(CVMX_KEY_INT_ENB, key_int_enb.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_key_int_sum_decode decodes all interrupt bits in cvmx_key_int_sum_t
+ */
+void __cvmx_interrupt_key_int_sum_decode(void)
+{
+    cvmx_key_int_sum_t key_int_sum;
+    key_int_sum.u64 = cvmx_read_csr(CVMX_KEY_INT_SUM);
+    key_int_sum.u64 &= cvmx_read_csr(CVMX_KEY_INT_ENB);
+    cvmx_write_csr(CVMX_KEY_INT_SUM, key_int_sum.u64);
+    // Skipping key_int_sum.s.reserved_4_63
+    if (key_int_sum.s.ked1_dbe)
+        PRINT_ERROR("KEY_INT_SUM[KED1_DBE]: Error bit\n");
+    if (key_int_sum.s.ked1_sbe)
+        PRINT_ERROR("KEY_INT_SUM[KED1_SBE]: Error bit\n");
+    if (key_int_sum.s.ked0_dbe)
+        PRINT_ERROR("KEY_INT_SUM[KED0_DBE]: Error bit\n");
+    if (key_int_sum.s.ked0_sbe)
+        PRINT_ERROR("KEY_INT_SUM[KED0_SBE]: Error bit\n");
+}
+
+
+/**
+ * __cvmx_interrupt_mio_boot_int_enable enables all interrupt bits in cvmx_mio_boot_int_t
+ */
+void __cvmx_interrupt_mio_boot_int_enable(void)
+{
+    cvmx_mio_boot_int_t mio_boot_int;
+    cvmx_write_csr(CVMX_MIO_BOOT_ERR, cvmx_read_csr(CVMX_MIO_BOOT_ERR));
+    mio_boot_int.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping mio_boot_int.s.reserved_2_63
+        mio_boot_int.s.wait_int = 1;
+        mio_boot_int.s.adr_int = 1;
+    }
+    cvmx_write_csr(CVMX_MIO_BOOT_INT, mio_boot_int.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_mio_boot_err_decode decodes all interrupt bits in cvmx_mio_boot_err_t
+ */
+void __cvmx_interrupt_mio_boot_err_decode(void)
+{
+    cvmx_mio_boot_err_t mio_boot_err;
+    mio_boot_err.u64 = cvmx_read_csr(CVMX_MIO_BOOT_ERR);
+    mio_boot_err.u64 &= cvmx_read_csr(CVMX_MIO_BOOT_INT);
+    cvmx_write_csr(CVMX_MIO_BOOT_ERR, mio_boot_err.u64);
+    // Skipping mio_boot_err.s.reserved_2_63
+    if (mio_boot_err.s.wait_err)
+        PRINT_ERROR("MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n");
+    if (mio_boot_err.s.adr_err)
+        PRINT_ERROR("MIO_BOOT_ERR[ADR_ERR]: Address decode error\n");
+}
+
+
+/**
+ * __cvmx_interrupt_npei_int_sum_decode decodes all interrupt bits in cvmx_npei_int_sum_t
+ */
+void __cvmx_interrupt_npei_int_sum_decode(void)
+{
+    cvmx_npei_int_sum_t npei_int_sum;
+    npei_int_sum.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM);
+    /* Note that NPEI_INT_ENB2 controls the internal RSL interrupts.
+        NPEI_INT_ENB controls external forwarding which is not what we
+        want. It is a little strange that we are using NPEI_INT_SUM with
+        NPEI_INT_ENB2, but we need the R/W version of NPEI_INT_SUM2 and
+        internal RSL interrupts */
+    npei_int_sum.u64 &= cvmx_read_csr(CVMX_PEXP_NPEI_INT_ENB2);
+    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, npei_int_sum.u64);
+    if (npei_int_sum.s.mio_inta)
+        PRINT_ERROR("NPEI_INT_SUM[MIO_INTA]: Interrupt from MIO.\n");
+    // Skipping npei_int_sum.s.reserved_62_62
+    if (npei_int_sum.s.int_a)
+        PRINT_ERROR("NPEI_INT_SUM[INT_A]: Set when a bit in the NPEI_INT_A_SUM register and\n"
+                    "    the cooresponding bit in the NPEI_INT_A_ENB\n"
+                    "    register is set.\n");
+    if (npei_int_sum.s.c1_ldwn)
+    {
+        cvmx_ciu_soft_prst_t ciu_soft_prst;
+        PRINT_ERROR("NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n");
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        if (!ciu_soft_prst.s.soft_prst)
+        {
+            /* Attempt to automatically bring the link back up */
+            cvmx_pcie_rc_shutdown(1);
+            cvmx_pcie_rc_initialize(1);
+        }
+        cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
+    }
+    if (npei_int_sum.s.c0_ldwn)
+    {
+        cvmx_ciu_soft_prst_t ciu_soft_prst;
+        PRINT_ERROR("NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n");
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        if (!ciu_soft_prst.s.soft_prst)
+        {
+            /* Attempt to automatically bring the link back up */
+            cvmx_pcie_rc_shutdown(0);
+            cvmx_pcie_rc_initialize(0);
+        }
+        cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
+    }
+    if (npei_int_sum.s.c1_exc)
+    {
+#if 0
+        PRINT_ERROR("NPEI_INT_SUM[C1_EXC]: Set when the PESC1_DBG_INFO register has a bit\n"
+                    "    set and its cooresponding PESC1_DBG_INFO_EN bit\n"
+                    "    is set.\n");
+#endif
+        __cvmx_interrupt_pescx_dbg_info_decode(1);
+    }
+    if (npei_int_sum.s.c0_exc)
+    {
+#if 0
+        PRINT_ERROR("NPEI_INT_SUM[C0_EXC]: Set when the PESC0_DBG_INFO register has a bit\n"
+                    "    set and its cooresponding PESC0_DBG_INFO_EN bit\n"
+                    "    is set.\n");
+#endif
+        __cvmx_interrupt_pescx_dbg_info_decode(0);
+    }
+    if (npei_int_sum.s.c1_up_wf)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+                    "    register. Core1.\n");
+    if (npei_int_sum.s.c0_up_wf)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
+                    "    register. Core0.\n");
+    if (npei_int_sum.s.c1_un_wf)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+                    "    register. Core1.\n");
+    if (npei_int_sum.s.c0_un_wf)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
+                    "    register. Core0.\n");
+    if (npei_int_sum.s.c1_un_bx)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_un_wi)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_un_b2)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_un_b1)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_un_b0)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_up_bx)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_up_wi)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_up_b2)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_up_b1)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c1_up_b0)
+        PRINT_ERROR("NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+                    "    Core 1.\n");
+    if (npei_int_sum.s.c0_un_bx)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_un_wi)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_un_b2)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_un_b1)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_un_b0)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_up_bx)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_up_wi)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_up_b2)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_up_b1)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c0_up_b0)
+        PRINT_ERROR("NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
+                    "    Core 0.\n");
+    if (npei_int_sum.s.c1_hpint)
+        PRINT_ERROR("NPEI_INT_SUM[C1_HPINT]: Hot-Plug Interrupt.\n"
+                    "    Pcie Core 1 (hp_int).\n"
+                    "    This interrupt will only be generated when\n"
+                    "    PCIERC1_CFG034[DLLS_C] is generated. Hot plug is\n"
+                    "    not supported.\n");
+    if (npei_int_sum.s.c1_pmei)
+        PRINT_ERROR("NPEI_INT_SUM[C1_PMEI]: PME Interrupt.\n"
+                    "    Pcie Core 1. (cfg_pme_int)\n");
+    if (npei_int_sum.s.c1_wake)
+        PRINT_ERROR("NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
+                    "    Pcie Core 1. (wake_n)\n"
+                    "    Octeon will never generate this interrupt.\n");
+    if (npei_int_sum.s.crs1_dr)
+        PRINT_ERROR("NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n");
+    if (npei_int_sum.s.c1_se)
+        PRINT_ERROR("NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
+                    "    Pcie Core 1. (cfg_sys_err_rc)\n");
+    if (npei_int_sum.s.crs1_er)
+        PRINT_ERROR("NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n");
+    if (npei_int_sum.s.c1_aeri)
+        PRINT_ERROR("NPEI_INT_SUM[C1_AERI]: Advanced Error Reporting Interrupt, RC Mode Only.\n"
+                    "    Pcie Core 1.\n");
+    if (npei_int_sum.s.c0_hpint)
+        PRINT_ERROR("NPEI_INT_SUM[C0_HPINT]: Hot-Plug Interrupt.\n"
+                    "    Pcie Core 0 (hp_int).\n"
+                    "    This interrupt will only be generated when\n"
+                    "    PCIERC0_CFG034[DLLS_C] is generated. Hot plug is\n"
+                    "    not supported.\n");
+    if (npei_int_sum.s.c0_pmei)
+        PRINT_ERROR("NPEI_INT_SUM[C0_PMEI]: PME Interrupt.\n"
+                    "    Pcie Core 0. (cfg_pme_int)\n");
+    if (npei_int_sum.s.c0_wake)
+        PRINT_ERROR("NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
+                    "    Pcie Core 0. (wake_n)\n"
+                    "    Octeon will never generate this interrupt.\n");
+    if (npei_int_sum.s.crs0_dr)
+        PRINT_ERROR("NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n");
+    if (npei_int_sum.s.c0_se)
+        PRINT_ERROR("NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
+                    "    Pcie Core 0. (cfg_sys_err_rc)\n");
+    if (npei_int_sum.s.crs0_er)
+        PRINT_ERROR("NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n");
+    if (npei_int_sum.s.c0_aeri)
+        PRINT_ERROR("NPEI_INT_SUM[C0_AERI]: Advanced Error Reporting Interrupt, RC Mode Only.\n"
+                    "    Pcie Core 0 (cfg_aer_rc_err_int).\n");
+    if (npei_int_sum.s.ptime)
+        PRINT_ERROR("NPEI_INT_SUM[PTIME]: Packet Timer has an interrupt. Which rings can\n"
+                    "    be found in NPEI_PKT_TIME_INT.\n");
+    if (npei_int_sum.s.pcnt)
+        PRINT_ERROR("NPEI_INT_SUM[PCNT]: Packet Counter has an interrupt. Which rings can\n"
+                    "    be found in NPEI_PKT_CNT_INT.\n");
+    if (npei_int_sum.s.pidbof)
+        PRINT_ERROR("NPEI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
+                    "    doorbell can be found in NPEI_INT_INFO[PIDBOF]\n");
+    if (npei_int_sum.s.psldbof)
+        PRINT_ERROR("NPEI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
+                    "    doorbell can be found in NPEI_INT_INFO[PSLDBOF]\n");
+    if (npei_int_sum.s.dtime1)
+        PRINT_ERROR("NPEI_INT_SUM[DTIME1]: Whenever NPEI_DMA_CNTS[DMA1] is not 0, the\n"
+                    "    DMA_CNT1 timer increments every core clock. When\n"
+                    "    DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME],\n"
+                    "    this bit is set. Writing a '1' to this bit also\n"
+                    "    clears the DMA_CNT1 timer.\n");
+    if (npei_int_sum.s.dtime0)
+        PRINT_ERROR("NPEI_INT_SUM[DTIME0]: Whenever NPEI_DMA_CNTS[DMA0] is not 0, the\n"
+                    "    DMA_CNT0 timer increments every core clock. When\n"
+                    "    DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME],\n"
+                    "    this bit is set. Writing a '1' to this bit also\n"
+                    "    clears the DMA_CNT0 timer.\n");
+    if (npei_int_sum.s.dcnt1)
+        PRINT_ERROR("NPEI_INT_SUM[DCNT1]: This bit indicates that NPEI_DMA_CNTS[DMA1] was/is\n"
+                    "    greater than NPEI_DMA1_INT_LEVEL[CNT].\n");
+    if (npei_int_sum.s.dcnt0)
+        PRINT_ERROR("NPEI_INT_SUM[DCNT0]: This bit indicates that NPEI_DMA_CNTS[DMA0] was/is\n"
+                    "    greater than NPEI_DMA0_INT_LEVEL[CNT].\n");
+    if (npei_int_sum.s.dma1fi)
+        PRINT_ERROR("NPEI_INT_SUM[DMA1FI]: DMA0 set Forced Interrupt.\n");
+    if (npei_int_sum.s.dma0fi)
+        PRINT_ERROR("NPEI_INT_SUM[DMA0FI]: DMA0 set Forced Interrupt.\n");
+    if (npei_int_sum.s.dma4dbo)
+        PRINT_ERROR("NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
+                    "    Bit[32] of the doorbell count was set.\n");
+    if (npei_int_sum.s.dma3dbo)
+        PRINT_ERROR("NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
+                    "    Bit[32] of the doorbell count was set.\n");
+    if (npei_int_sum.s.dma2dbo)
+        PRINT_ERROR("NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
+                    "    Bit[32] of the doorbell count was set.\n");
+    if (npei_int_sum.s.dma1dbo)
+        PRINT_ERROR("NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
+                    "    Bit[32] of the doorbell count was set.\n");
+    if (npei_int_sum.s.dma0dbo)
+        PRINT_ERROR("NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
+                    "    Bit[32] of the doorbell count was set.\n");
+    if (npei_int_sum.s.iob2big)
+        PRINT_ERROR("NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n");
+    if (npei_int_sum.s.bar0_to)
+        PRINT_ERROR("NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
+                    "    read-data/commit in 0xffff core clocks.\n");
+    if (npei_int_sum.s.rml_wto)
+        PRINT_ERROR("NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n");
+    if (npei_int_sum.s.rml_rto)
+        PRINT_ERROR("NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n");
+}
+
+
+/**
+ * __cvmx_interrupt_npei_int_enb2_enable enables all interrupt bits in cvmx_npei_int_enb2_t
+ */
+void __cvmx_interrupt_npei_int_enb2_enable(void)
+{
+    int enable_pcie0 = 0;
+    int enable_pcie1 = 0;
+    cvmx_npei_int_enb2_t npei_int_enb2;
+    /* Reset NPEI_INT_SUM, as NPEI_INT_SUM2 is a read-only copy of NPEI_INT_SUM. */
+    cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
+    npei_int_enb2.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        cvmx_pescx_ctl_status2_t pescx_ctl_status2;
+        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(0));
+        enable_pcie0 = !pescx_ctl_status2.s.pcierst;
+        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(1));
+        enable_pcie1 = !pescx_ctl_status2.s.pcierst;
+
+        // Skipping npei_int_enb2.s.reserved_62_63
+        npei_int_enb2.s.int_a = 1;
+        npei_int_enb2.s.c1_ldwn = enable_pcie1;
+        npei_int_enb2.s.c0_ldwn = enable_pcie0;
+        npei_int_enb2.s.c1_exc = enable_pcie1;
+        npei_int_enb2.s.c0_exc = enable_pcie0;
+        npei_int_enb2.s.c1_up_wf = enable_pcie1;
+        npei_int_enb2.s.c0_up_wf = enable_pcie0;
+        npei_int_enb2.s.c1_un_wf = enable_pcie1;
+        npei_int_enb2.s.c0_un_wf = enable_pcie0;
+        npei_int_enb2.s.c1_un_bx = enable_pcie1;
+        npei_int_enb2.s.c1_un_wi = enable_pcie1;
+        npei_int_enb2.s.c1_un_b2 = enable_pcie1;
+        npei_int_enb2.s.c1_un_b1 = enable_pcie1;
+        npei_int_enb2.s.c1_un_b0 = enable_pcie1;
+        npei_int_enb2.s.c1_up_bx = enable_pcie1;
+        npei_int_enb2.s.c1_up_wi = enable_pcie1;
+        npei_int_enb2.s.c1_up_b2 = enable_pcie1;
+        npei_int_enb2.s.c1_up_b1 = enable_pcie1;
+        npei_int_enb2.s.c1_up_b0 = enable_pcie1;
+        npei_int_enb2.s.c0_un_bx = enable_pcie0;
+        npei_int_enb2.s.c0_un_wi = enable_pcie0;
+        npei_int_enb2.s.c0_un_b2 = enable_pcie0;
+        npei_int_enb2.s.c0_un_b1 = enable_pcie0;
+        npei_int_enb2.s.c0_un_b0 = enable_pcie0;
+        npei_int_enb2.s.c0_up_bx = enable_pcie0;
+        npei_int_enb2.s.c0_up_wi = enable_pcie0;
+        npei_int_enb2.s.c0_up_b2 = enable_pcie0;
+        npei_int_enb2.s.c0_up_b1 = enable_pcie0;
+        npei_int_enb2.s.c0_up_b0 = enable_pcie0;
+        npei_int_enb2.s.c1_hpint = enable_pcie1;
+        npei_int_enb2.s.c1_pmei = enable_pcie1;
+        npei_int_enb2.s.c1_wake = enable_pcie1;
+        npei_int_enb2.s.crs1_dr = enable_pcie1;
+        npei_int_enb2.s.c1_se = enable_pcie1;
+        npei_int_enb2.s.crs1_er = enable_pcie1;
+        npei_int_enb2.s.c1_aeri = enable_pcie1;
+        npei_int_enb2.s.c0_hpint = enable_pcie0;
+        npei_int_enb2.s.c0_pmei = enable_pcie0;
+        npei_int_enb2.s.c0_wake = enable_pcie0;
+        npei_int_enb2.s.crs0_dr = enable_pcie0;
+        npei_int_enb2.s.c0_se = enable_pcie0;
+        npei_int_enb2.s.crs0_er = enable_pcie0;
+        npei_int_enb2.s.c0_aeri = enable_pcie0;
+        npei_int_enb2.s.ptime = 1;
+        npei_int_enb2.s.pcnt = 1;
+        npei_int_enb2.s.pidbof = 1;
+        npei_int_enb2.s.psldbof = 1;
+        npei_int_enb2.s.dtime1 = 1;
+        npei_int_enb2.s.dtime0 = 1;
+        npei_int_enb2.s.dcnt1 = 1;
+        npei_int_enb2.s.dcnt0 = 1;
+        npei_int_enb2.s.dma1fi = 1;
+        npei_int_enb2.s.dma0fi = 1;
+        npei_int_enb2.s.dma4dbo = 1;
+        npei_int_enb2.s.dma3dbo = 1;
+        npei_int_enb2.s.dma2dbo = 1;
+        npei_int_enb2.s.dma1dbo = 1;
+        npei_int_enb2.s.dma0dbo = 1;
+        npei_int_enb2.s.iob2big = 1;
+        npei_int_enb2.s.bar0_to = 1;
+        npei_int_enb2.s.rml_wto = 1;
+        npei_int_enb2.s.rml_rto = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        cvmx_pescx_ctl_status2_t pescx_ctl_status2;
+        cvmx_npei_dbg_data_t npei_dbg_data;
+        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(0));
+        enable_pcie0 = !pescx_ctl_status2.s.pcierst;
+        npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+        if (!npei_dbg_data.cn52xx.qlm0_link_width)
+        {
+            pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(1));
+            enable_pcie1 = !pescx_ctl_status2.s.pcierst;
+        }
+
+        // Skipping npei_int_enb2.s.reserved_62_63
+        npei_int_enb2.s.int_a = 1;
+        npei_int_enb2.s.c1_ldwn = enable_pcie1;
+        npei_int_enb2.s.c0_ldwn = enable_pcie0;
+        npei_int_enb2.s.c1_exc = enable_pcie1;
+        npei_int_enb2.s.c0_exc = enable_pcie0;
+        npei_int_enb2.s.c1_up_wf = enable_pcie1;
+        npei_int_enb2.s.c0_up_wf = enable_pcie0;
+        npei_int_enb2.s.c1_un_wf = enable_pcie1;
+        npei_int_enb2.s.c0_un_wf = enable_pcie0;
+        npei_int_enb2.s.c1_un_bx = enable_pcie1;
+        npei_int_enb2.s.c1_un_wi = enable_pcie1;
+        npei_int_enb2.s.c1_un_b2 = enable_pcie1;
+        npei_int_enb2.s.c1_un_b1 = enable_pcie1;
+        npei_int_enb2.s.c1_un_b0 = enable_pcie1;
+        npei_int_enb2.s.c1_up_bx = enable_pcie1;
+        npei_int_enb2.s.c1_up_wi = enable_pcie1;
+        npei_int_enb2.s.c1_up_b2 = enable_pcie1;
+        npei_int_enb2.s.c1_up_b1 = enable_pcie1;
+        npei_int_enb2.s.c1_up_b0 = enable_pcie1;
+        npei_int_enb2.s.c0_un_bx = enable_pcie0;
+        npei_int_enb2.s.c0_un_wi = enable_pcie0;
+        npei_int_enb2.s.c0_un_b2 = enable_pcie0;
+        npei_int_enb2.s.c0_un_b1 = enable_pcie0;
+        npei_int_enb2.s.c0_un_b0 = enable_pcie0;
+        npei_int_enb2.s.c0_up_bx = enable_pcie0;
+        npei_int_enb2.s.c0_up_wi = enable_pcie0;
+        npei_int_enb2.s.c0_up_b2 = enable_pcie0;
+        npei_int_enb2.s.c0_up_b1 = enable_pcie0;
+        npei_int_enb2.s.c0_up_b0 = enable_pcie0;
+        npei_int_enb2.s.c1_hpint = enable_pcie1;
+        npei_int_enb2.s.c1_pmei = enable_pcie1;
+        npei_int_enb2.s.c1_wake = enable_pcie1;
+        npei_int_enb2.s.crs1_dr = enable_pcie1;
+        npei_int_enb2.s.c1_se = enable_pcie1;
+        npei_int_enb2.s.crs1_er = enable_pcie1;
+        npei_int_enb2.s.c1_aeri = enable_pcie1;
+        npei_int_enb2.s.c0_hpint = enable_pcie0;
+        npei_int_enb2.s.c0_pmei = enable_pcie0;
+        npei_int_enb2.s.c0_wake = enable_pcie0;
+        npei_int_enb2.s.crs0_dr = enable_pcie0;
+        npei_int_enb2.s.c0_se = enable_pcie0;
+        npei_int_enb2.s.crs0_er = enable_pcie0;
+        npei_int_enb2.s.c0_aeri = enable_pcie0;
+        npei_int_enb2.s.ptime = 1;
+        npei_int_enb2.s.pcnt = 1;
+        npei_int_enb2.s.pidbof = 1;
+        npei_int_enb2.s.psldbof = 1;
+        npei_int_enb2.s.dtime1 = 1;
+        npei_int_enb2.s.dtime0 = 1;
+        npei_int_enb2.s.dcnt1 = 1;
+        npei_int_enb2.s.dcnt0 = 1;
+        npei_int_enb2.s.dma1fi = 1;
+        npei_int_enb2.s.dma0fi = 1;
+        if (!OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+            npei_int_enb2.s.dma4dbo = 1;
+        npei_int_enb2.s.dma3dbo = 1;
+        npei_int_enb2.s.dma2dbo = 1;
+        npei_int_enb2.s.dma1dbo = 1;
+        npei_int_enb2.s.dma0dbo = 1;
+        npei_int_enb2.s.iob2big = 1;
+        npei_int_enb2.s.bar0_to = 1;
+        npei_int_enb2.s.rml_wto = 1;
+        npei_int_enb2.s.rml_rto = 1;
+    }
+    cvmx_write_csr(CVMX_PEXP_NPEI_INT_ENB2, npei_int_enb2.u64);
+    if (enable_pcie0)
+        __cvmx_interrupt_pescx_dbg_info_en_enable(0);
+    if (enable_pcie1)
+        __cvmx_interrupt_pescx_dbg_info_en_enable(1);
+}
+
+
+/**
+ * __cvmx_interrupt_npi_int_enb_enable enables all interrupt bits in cvmx_npi_int_enb_t
+ */
+void __cvmx_interrupt_npi_int_enb_enable(void)
+{
+    cvmx_npi_int_enb_t npi_int_enb;
+    cvmx_write_csr(CVMX_NPI_INT_SUM, cvmx_read_csr(CVMX_NPI_INT_SUM));
+    npi_int_enb.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping npi_int_enb.s.reserved_62_63
+        npi_int_enb.s.q1_a_f = 1;
+        npi_int_enb.s.q1_s_e = 1;
+        npi_int_enb.s.pdf_p_f = 1;
+        npi_int_enb.s.pdf_p_e = 1;
+        npi_int_enb.s.pcf_p_f = 1;
+        npi_int_enb.s.pcf_p_e = 1;
+        npi_int_enb.s.rdx_s_e = 1;
+        npi_int_enb.s.rwx_s_e = 1;
+        npi_int_enb.s.pnc_a_f = 1;
+        npi_int_enb.s.pnc_s_e = 1;
+        npi_int_enb.s.com_a_f = 1;
+        npi_int_enb.s.com_s_e = 1;
+        npi_int_enb.s.q3_a_f = 1;
+        npi_int_enb.s.q3_s_e = 1;
+        npi_int_enb.s.q2_a_f = 1;
+        npi_int_enb.s.q2_s_e = 1;
+        npi_int_enb.s.pcr_a_f = 1;
+        npi_int_enb.s.pcr_s_e = 1;
+        npi_int_enb.s.fcr_a_f = 1;
+        npi_int_enb.s.fcr_s_e = 1;
+        npi_int_enb.s.iobdma = 1;
+        npi_int_enb.s.p_dperr = 1;
+        npi_int_enb.s.win_rto = 1;
+        // Skipping npi_int_enb.s.reserved_36_38
+        npi_int_enb.s.i0_pperr = 1;
+        // Skipping npi_int_enb.s.reserved_32_34
+        npi_int_enb.s.p0_ptout = 1;
+        // Skipping npi_int_enb.s.reserved_28_30
+        npi_int_enb.s.p0_pperr = 1;
+        // Skipping npi_int_enb.s.reserved_24_26
+        npi_int_enb.s.g0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_20_22
+        npi_int_enb.s.p0_perr = 1;
+        // Skipping npi_int_enb.s.reserved_16_18
+        npi_int_enb.s.p0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_12_14
+        npi_int_enb.s.i0_overf = 1;
+        // Skipping npi_int_enb.s.reserved_8_10
+        npi_int_enb.s.i0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_4_6
+        npi_int_enb.s.po0_2sml = 1;
+        npi_int_enb.s.pci_rsl = 1;
+        npi_int_enb.s.rml_wto = 1;
+        npi_int_enb.s.rml_rto = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping npi_int_enb.s.reserved_62_63
+        npi_int_enb.s.q1_a_f = 1;
+        npi_int_enb.s.q1_s_e = 1;
+        npi_int_enb.s.pdf_p_f = 1;
+        npi_int_enb.s.pdf_p_e = 1;
+        npi_int_enb.s.pcf_p_f = 1;
+        npi_int_enb.s.pcf_p_e = 1;
+        npi_int_enb.s.rdx_s_e = 1;
+        npi_int_enb.s.rwx_s_e = 1;
+        npi_int_enb.s.pnc_a_f = 1;
+        npi_int_enb.s.pnc_s_e = 1;
+        npi_int_enb.s.com_a_f = 1;
+        npi_int_enb.s.com_s_e = 1;
+        npi_int_enb.s.q3_a_f = 1;
+        npi_int_enb.s.q3_s_e = 1;
+        npi_int_enb.s.q2_a_f = 1;
+        npi_int_enb.s.q2_s_e = 1;
+        npi_int_enb.s.pcr_a_f = 1;
+        npi_int_enb.s.pcr_s_e = 1;
+        npi_int_enb.s.fcr_a_f = 1;
+        npi_int_enb.s.fcr_s_e = 1;
+        npi_int_enb.s.iobdma = 1;
+        npi_int_enb.s.p_dperr = 1;
+        npi_int_enb.s.win_rto = 1;
+        // Skipping npi_int_enb.s.reserved_37_38
+        npi_int_enb.s.i1_pperr = 1;
+        npi_int_enb.s.i0_pperr = 1;
+        // Skipping npi_int_enb.s.reserved_33_34
+        npi_int_enb.s.p1_ptout = 1;
+        npi_int_enb.s.p0_ptout = 1;
+        // Skipping npi_int_enb.s.reserved_29_30
+        npi_int_enb.s.p1_pperr = 1;
+        npi_int_enb.s.p0_pperr = 1;
+        // Skipping npi_int_enb.s.reserved_25_26
+        npi_int_enb.s.g1_rtout = 1;
+        npi_int_enb.s.g0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_21_22
+        npi_int_enb.s.p1_perr = 1;
+        npi_int_enb.s.p0_perr = 1;
+        // Skipping npi_int_enb.s.reserved_17_18
+        npi_int_enb.s.p1_rtout = 1;
+        npi_int_enb.s.p0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_13_14
+        npi_int_enb.s.i1_overf = 1;
+        npi_int_enb.s.i0_overf = 1;
+        // Skipping npi_int_enb.s.reserved_9_10
+        npi_int_enb.s.i1_rtout = 1;
+        npi_int_enb.s.i0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_5_6
+        npi_int_enb.s.po1_2sml = 1;
+        npi_int_enb.s.po0_2sml = 1;
+        npi_int_enb.s.pci_rsl = 1;
+        npi_int_enb.s.rml_wto = 1;
+        npi_int_enb.s.rml_rto = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping npi_int_enb.s.reserved_62_63
+        npi_int_enb.s.q1_a_f = 1;
+        npi_int_enb.s.q1_s_e = 1;
+        npi_int_enb.s.pdf_p_f = 1;
+        npi_int_enb.s.pdf_p_e = 1;
+        npi_int_enb.s.pcf_p_f = 1;
+        npi_int_enb.s.pcf_p_e = 1;
+        npi_int_enb.s.rdx_s_e = 1;
+        npi_int_enb.s.rwx_s_e = 1;
+        npi_int_enb.s.pnc_a_f = 1;
+        npi_int_enb.s.pnc_s_e = 1;
+        npi_int_enb.s.com_a_f = 1;
+        npi_int_enb.s.com_s_e = 1;
+        npi_int_enb.s.q3_a_f = 1;
+        npi_int_enb.s.q3_s_e = 1;
+        npi_int_enb.s.q2_a_f = 1;
+        npi_int_enb.s.q2_s_e = 1;
+        npi_int_enb.s.pcr_a_f = 1;
+        npi_int_enb.s.pcr_s_e = 1;
+        npi_int_enb.s.fcr_a_f = 1;
+        npi_int_enb.s.fcr_s_e = 1;
+        npi_int_enb.s.iobdma = 1;
+        npi_int_enb.s.p_dperr = 1;
+        npi_int_enb.s.win_rto = 1;
+        npi_int_enb.s.i3_pperr = 1;
+        npi_int_enb.s.i2_pperr = 1;
+        npi_int_enb.s.i1_pperr = 1;
+        npi_int_enb.s.i0_pperr = 1;
+        npi_int_enb.s.p3_ptout = 1;
+        npi_int_enb.s.p2_ptout = 1;
+        npi_int_enb.s.p1_ptout = 1;
+        npi_int_enb.s.p0_ptout = 1;
+        npi_int_enb.s.p3_pperr = 1;
+        npi_int_enb.s.p2_pperr = 1;
+        npi_int_enb.s.p1_pperr = 1;
+        npi_int_enb.s.p0_pperr = 1;
+        npi_int_enb.s.g3_rtout = 1;
+        npi_int_enb.s.g2_rtout = 1;
+        npi_int_enb.s.g1_rtout = 1;
+        npi_int_enb.s.g0_rtout = 1;
+        npi_int_enb.s.p3_perr = 1;
+        npi_int_enb.s.p2_perr = 1;
+        npi_int_enb.s.p1_perr = 1;
+        npi_int_enb.s.p0_perr = 1;
+        npi_int_enb.s.p3_rtout = 1;
+        npi_int_enb.s.p2_rtout = 1;
+        npi_int_enb.s.p1_rtout = 1;
+        npi_int_enb.s.p0_rtout = 1;
+        npi_int_enb.s.i3_overf = 1;
+        npi_int_enb.s.i2_overf = 1;
+        npi_int_enb.s.i1_overf = 1;
+        npi_int_enb.s.i0_overf = 1;
+        npi_int_enb.s.i3_rtout = 1;
+        npi_int_enb.s.i2_rtout = 1;
+        npi_int_enb.s.i1_rtout = 1;
+        npi_int_enb.s.i0_rtout = 1;
+        npi_int_enb.s.po3_2sml = 1;
+        npi_int_enb.s.po2_2sml = 1;
+        npi_int_enb.s.po1_2sml = 1;
+        npi_int_enb.s.po0_2sml = 1;
+        npi_int_enb.s.pci_rsl = 1;
+        npi_int_enb.s.rml_wto = 1;
+        npi_int_enb.s.rml_rto = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping npi_int_enb.s.reserved_62_63
+        npi_int_enb.s.q1_a_f = 1;
+        npi_int_enb.s.q1_s_e = 1;
+        npi_int_enb.s.pdf_p_f = 1;
+        npi_int_enb.s.pdf_p_e = 1;
+        npi_int_enb.s.pcf_p_f = 1;
+        npi_int_enb.s.pcf_p_e = 1;
+        npi_int_enb.s.rdx_s_e = 1;
+        npi_int_enb.s.rwx_s_e = 1;
+        npi_int_enb.s.pnc_a_f = 1;
+        npi_int_enb.s.pnc_s_e = 1;
+        npi_int_enb.s.com_a_f = 1;
+        npi_int_enb.s.com_s_e = 1;
+        npi_int_enb.s.q3_a_f = 1;
+        npi_int_enb.s.q3_s_e = 1;
+        npi_int_enb.s.q2_a_f = 1;
+        npi_int_enb.s.q2_s_e = 1;
+        npi_int_enb.s.pcr_a_f = 1;
+        npi_int_enb.s.pcr_s_e = 1;
+        npi_int_enb.s.fcr_a_f = 1;
+        npi_int_enb.s.fcr_s_e = 1;
+        npi_int_enb.s.iobdma = 1;
+        npi_int_enb.s.p_dperr = 1;
+        npi_int_enb.s.win_rto = 1;
+        // Skipping npi_int_enb.s.reserved_37_38
+        npi_int_enb.s.i1_pperr = 1;
+        npi_int_enb.s.i0_pperr = 1;
+        // Skipping npi_int_enb.s.reserved_33_34
+        npi_int_enb.s.p1_ptout = 1;
+        npi_int_enb.s.p0_ptout = 1;
+        // Skipping npi_int_enb.s.reserved_29_30
+        npi_int_enb.s.p1_pperr = 1;
+        npi_int_enb.s.p0_pperr = 1;
+        // Skipping npi_int_enb.s.reserved_25_26
+        npi_int_enb.s.g1_rtout = 1;
+        npi_int_enb.s.g0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_21_22
+        npi_int_enb.s.p1_perr = 1;
+        npi_int_enb.s.p0_perr = 1;
+        // Skipping npi_int_enb.s.reserved_17_18
+        npi_int_enb.s.p1_rtout = 1;
+        npi_int_enb.s.p0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_13_14
+        npi_int_enb.s.i1_overf = 1;
+        npi_int_enb.s.i0_overf = 1;
+        // Skipping npi_int_enb.s.reserved_9_10
+        npi_int_enb.s.i1_rtout = 1;
+        npi_int_enb.s.i0_rtout = 1;
+        // Skipping npi_int_enb.s.reserved_5_6
+        npi_int_enb.s.po1_2sml = 1;
+        npi_int_enb.s.po0_2sml = 1;
+        npi_int_enb.s.pci_rsl = 1;
+        npi_int_enb.s.rml_wto = 1;
+        npi_int_enb.s.rml_rto = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping npi_int_enb.s.reserved_62_63
+        npi_int_enb.s.q1_a_f = 1;
+        npi_int_enb.s.q1_s_e = 1;
+        npi_int_enb.s.pdf_p_f = 1;
+        npi_int_enb.s.pdf_p_e = 1;
+        npi_int_enb.s.pcf_p_f = 1;
+        npi_int_enb.s.pcf_p_e = 1;
+        npi_int_enb.s.rdx_s_e = 1;
+        npi_int_enb.s.rwx_s_e = 1;
+        npi_int_enb.s.pnc_a_f = 1;
+        npi_int_enb.s.pnc_s_e = 1;
+        npi_int_enb.s.com_a_f = 1;
+        npi_int_enb.s.com_s_e = 1;
+        npi_int_enb.s.q3_a_f = 1;
+        npi_int_enb.s.q3_s_e = 1;
+        npi_int_enb.s.q2_a_f = 1;
+        npi_int_enb.s.q2_s_e = 1;
+        npi_int_enb.s.pcr_a_f = 1;
+        npi_int_enb.s.pcr_s_e = 1;
+        npi_int_enb.s.fcr_a_f = 1;
+        npi_int_enb.s.fcr_s_e = 1;
+        npi_int_enb.s.iobdma = 1;
+        npi_int_enb.s.p_dperr = 1;
+        npi_int_enb.s.win_rto = 1;
+        npi_int_enb.s.i3_pperr = 1;
+        npi_int_enb.s.i2_pperr = 1;
+        npi_int_enb.s.i1_pperr = 1;
+        npi_int_enb.s.i0_pperr = 1;
+        npi_int_enb.s.p3_ptout = 1;
+        npi_int_enb.s.p2_ptout = 1;
+        npi_int_enb.s.p1_ptout = 1;
+        npi_int_enb.s.p0_ptout = 1;
+        npi_int_enb.s.p3_pperr = 1;
+        npi_int_enb.s.p2_pperr = 1;
+        npi_int_enb.s.p1_pperr = 1;
+        npi_int_enb.s.p0_pperr = 1;
+        npi_int_enb.s.g3_rtout = 1;
+        npi_int_enb.s.g2_rtout = 1;
+        npi_int_enb.s.g1_rtout = 1;
+        npi_int_enb.s.g0_rtout = 1;
+        npi_int_enb.s.p3_perr = 1;
+        npi_int_enb.s.p2_perr = 1;
+        npi_int_enb.s.p1_perr = 1;
+        npi_int_enb.s.p0_perr = 1;
+        npi_int_enb.s.p3_rtout = 1;
+        npi_int_enb.s.p2_rtout = 1;
+        npi_int_enb.s.p1_rtout = 1;
+        npi_int_enb.s.p0_rtout = 1;
+        npi_int_enb.s.i3_overf = 1;
+        npi_int_enb.s.i2_overf = 1;
+        npi_int_enb.s.i1_overf = 1;
+        npi_int_enb.s.i0_overf = 1;
+        npi_int_enb.s.i3_rtout = 1;
+        npi_int_enb.s.i2_rtout = 1;
+        npi_int_enb.s.i1_rtout = 1;
+        npi_int_enb.s.i0_rtout = 1;
+        npi_int_enb.s.po3_2sml = 1;
+        npi_int_enb.s.po2_2sml = 1;
+        npi_int_enb.s.po1_2sml = 1;
+        npi_int_enb.s.po0_2sml = 1;
+        npi_int_enb.s.pci_rsl = 1;
+        npi_int_enb.s.rml_wto = 1;
+        npi_int_enb.s.rml_rto = 1;
+    }
+    cvmx_write_csr(CVMX_NPI_INT_ENB, npi_int_enb.u64);
+    __cvmx_interrupt_pci_int_enb2_enable();
+}
+
+
+/**
+ * __cvmx_interrupt_npi_int_sum_decode decodes all interrupt bits in cvmx_npi_int_sum_t
+ */
+void __cvmx_interrupt_npi_int_sum_decode(void)
+{
+    cvmx_npi_int_sum_t npi_int_sum;
+    npi_int_sum.u64 = cvmx_read_csr(CVMX_NPI_INT_SUM);
+    npi_int_sum.u64 &= cvmx_read_csr(CVMX_NPI_INT_ENB);
+    cvmx_write_csr(CVMX_NPI_INT_SUM, npi_int_sum.u64);
+    // Skipping npi_int_sum.s.reserved_62_63
+    if (npi_int_sum.s.q1_a_f)
+        PRINT_ERROR("NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.q1_s_e)
+        PRINT_ERROR("NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pdf_p_f)
+        PRINT_ERROR("NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pdf_p_e)
+        PRINT_ERROR("NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pcf_p_f)
+        PRINT_ERROR("NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pcf_p_e)
+        PRINT_ERROR("NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.rdx_s_e)
+        PRINT_ERROR("NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.rwx_s_e)
+        PRINT_ERROR("NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pnc_a_f)
+        PRINT_ERROR("NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pnc_s_e)
+        PRINT_ERROR("NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.com_a_f)
+        PRINT_ERROR("NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.com_s_e)
+        PRINT_ERROR("NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.q3_a_f)
+        PRINT_ERROR("NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.q3_s_e)
+        PRINT_ERROR("NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.q2_a_f)
+        PRINT_ERROR("NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.q2_s_e)
+        PRINT_ERROR("NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pcr_a_f)
+        PRINT_ERROR("NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.pcr_s_e)
+        PRINT_ERROR("NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.fcr_a_f)
+        PRINT_ERROR("NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.fcr_s_e)
+        PRINT_ERROR("NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
+                    "    PASS3 Field.\n");
+    if (npi_int_sum.s.iobdma)
+        PRINT_ERROR("NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n");
+    if (npi_int_sum.s.p_dperr)
+        PRINT_ERROR("NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
+                    "    from the PCI this bit may be set.\n");
+    if (npi_int_sum.s.win_rto)
+        PRINT_ERROR("NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n");
+    if (npi_int_sum.s.i3_pperr)
+        PRINT_ERROR("NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
+                    "    this bit may be set.\n");
+    if (npi_int_sum.s.i2_pperr)
+        PRINT_ERROR("NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
+                    "    this bit may be set.\n");
+    if (npi_int_sum.s.i1_pperr)
+        PRINT_ERROR("NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
+                    "    this bit may be set.\n");
+    if (npi_int_sum.s.i0_pperr)
+        PRINT_ERROR("NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
+                    "    this bit may be set.\n");
+    if (npi_int_sum.s.p3_ptout)
+        PRINT_ERROR("NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
+                    "    pair.\n");
+    if (npi_int_sum.s.p2_ptout)
+        PRINT_ERROR("NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
+                    "    pair.\n");
+    if (npi_int_sum.s.p1_ptout)
+        PRINT_ERROR("NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
+                    "    pair.\n");
+    if (npi_int_sum.s.p0_ptout)
+        PRINT_ERROR("NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
+                    "    pair.\n");
+    if (npi_int_sum.s.p3_pperr)
+        PRINT_ERROR("NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
+                    "    pointer-pair, this bit may be set.\n");
+    if (npi_int_sum.s.p2_pperr)
+        PRINT_ERROR("NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
+                    "    pointer-pair, this bit may be set.\n");
+    if (npi_int_sum.s.p1_pperr)
+        PRINT_ERROR("NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
+                    "    pointer-pair, this bit may be set.\n");
+    if (npi_int_sum.s.p0_pperr)
+        PRINT_ERROR("NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
+                    "    pointer-pair, this bit may be set.\n");
+    if (npi_int_sum.s.g3_rtout)
+        PRINT_ERROR("NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+                    "    read a gather list.\n");
+    if (npi_int_sum.s.g2_rtout)
+        PRINT_ERROR("NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+                    "    read a gather list.\n");
+    if (npi_int_sum.s.g1_rtout)
+        PRINT_ERROR("NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+                    "    read a gather list.\n");
+    if (npi_int_sum.s.g0_rtout)
+        PRINT_ERROR("NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+                    "    read a gather list.\n");
+    if (npi_int_sum.s.p3_perr)
+        PRINT_ERROR("NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
+                    "    data this bit may be set.\n");
+    if (npi_int_sum.s.p2_perr)
+        PRINT_ERROR("NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
+                    "    data this bit may be set.\n");
+    if (npi_int_sum.s.p1_perr)
+        PRINT_ERROR("NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
+                    "    data this bit may be set.\n");
+    if (npi_int_sum.s.p0_perr)
+        PRINT_ERROR("NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
+                    "    data this bit may be set.\n");
+    if (npi_int_sum.s.p3_rtout)
+        PRINT_ERROR("NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+                    "    read packet data.\n");
+    if (npi_int_sum.s.p2_rtout)
+        PRINT_ERROR("NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+                    "    read packet data.\n");
+    if (npi_int_sum.s.p1_rtout)
+        PRINT_ERROR("NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+                    "    read packet data.\n");
+    if (npi_int_sum.s.p0_rtout)
+        PRINT_ERROR("NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+                    "    read packet data.\n");
+    if (npi_int_sum.s.i3_overf)
+        PRINT_ERROR("NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
+                    "    doorbell count was set.\n");
+    if (npi_int_sum.s.i2_overf)
+        PRINT_ERROR("NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
+                    "    doorbell count was set.\n");
+    if (npi_int_sum.s.i1_overf)
+        PRINT_ERROR("NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
+                    "    doorbell count was set.\n");
+    if (npi_int_sum.s.i0_overf)
+        PRINT_ERROR("NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
+                    "    doorbell count was set.\n");
+    if (npi_int_sum.s.i3_rtout)
+        PRINT_ERROR("NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
+                    "    read instructions.\n");
+    if (npi_int_sum.s.i2_rtout)
+        PRINT_ERROR("NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
+                    "    read instructions.\n");
+    if (npi_int_sum.s.i1_rtout)
+        PRINT_ERROR("NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
+                    "    read instructions.\n");
+    if (npi_int_sum.s.i0_rtout)
+        PRINT_ERROR("NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
+                    "    read instructions.\n");
+    if (npi_int_sum.s.po3_2sml)
+        PRINT_ERROR("NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
+                    "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n");
+    if (npi_int_sum.s.po2_2sml)
+        PRINT_ERROR("NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
+                    "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n");
+    if (npi_int_sum.s.po1_2sml)
+        PRINT_ERROR("NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
+                    "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n");
+    if (npi_int_sum.s.po0_2sml)
+        PRINT_ERROR("NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
+                    "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n");
+    if (npi_int_sum.s.pci_rsl)
+    {
+#if 0
+        PRINT_ERROR("NPI_INT_SUM[PCI_RSL]: This '1' when a bit in PCI_INT_SUM2 is SET and the\n"
+                    "    corresponding bit in the PCI_INT_ENB2 is SET.\n");
+#endif
+        __cvmx_interrupt_pci_int_sum2_decode();
+    }
+    if (npi_int_sum.s.rml_wto)
+        PRINT_ERROR("NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
+                    "    back from a RSL after sending a write command to\n"
+                    "    a RSL.\n");
+    if (npi_int_sum.s.rml_rto)
+        PRINT_ERROR("NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
+                    "    back from a RSL after sending a read command to\n"
+                    "    a RSL.\n");
+}
+
+
+/**
+ * __cvmx_interrupt_pci_int_enb2_enable enables all interrupt bits in cvmx_pci_int_enb2_t
+ */
+void __cvmx_interrupt_pci_int_enb2_enable(void)
+{
+    cvmx_pci_int_enb2_t pci_int_enb2;
+    cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, cvmx_read_csr(CVMX_NPI_PCI_INT_SUM2));
+    pci_int_enb2.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping pci_int_enb2.s.reserved_34_63
+        pci_int_enb2.s.ill_rd = 1;
+        pci_int_enb2.s.ill_wr = 1;
+        pci_int_enb2.s.win_wr = 1;
+        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
+        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
+        // Skipping pci_int_enb2.s.reserved_22_24
+        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
+        // Skipping pci_int_enb2.s.reserved_18_20
+        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
+        pci_int_enb2.s.ill_rrd = 1;
+        pci_int_enb2.s.ill_rwr = 1;
+        pci_int_enb2.s.rdperr = 1;
+        pci_int_enb2.s.raperr = 1;
+        pci_int_enb2.s.rserr = 1;
+        pci_int_enb2.s.rtsr_abt = 1;
+        pci_int_enb2.s.rmsc_msg = 1;
+        pci_int_enb2.s.rmsi_mabt = 1;
+        pci_int_enb2.s.rmsi_tabt = 1;
+        pci_int_enb2.s.rmsi_per = 1;
+        pci_int_enb2.s.rmr_tto = 1;
+        pci_int_enb2.s.rmr_abt = 1;
+        pci_int_enb2.s.rtr_abt = 1;
+        pci_int_enb2.s.rmr_wtto = 1;
+        pci_int_enb2.s.rmr_wabt = 1;
+        pci_int_enb2.s.rtr_wabt = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping pci_int_enb2.s.reserved_34_63
+        pci_int_enb2.s.ill_rd = 1;
+        pci_int_enb2.s.ill_wr = 1;
+        pci_int_enb2.s.win_wr = 1;
+        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
+        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
+        // Skipping pci_int_enb2.s.reserved_23_24
+        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
+        // Skipping pci_int_enb2.s.reserved_19_20
+        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
+        pci_int_enb2.s.ill_rrd = 1;
+        pci_int_enb2.s.ill_rwr = 1;
+        pci_int_enb2.s.rdperr = 1;
+        pci_int_enb2.s.raperr = 1;
+        pci_int_enb2.s.rserr = 1;
+        pci_int_enb2.s.rtsr_abt = 1;
+        pci_int_enb2.s.rmsc_msg = 1;
+        pci_int_enb2.s.rmsi_mabt = 1;
+        pci_int_enb2.s.rmsi_tabt = 1;
+        pci_int_enb2.s.rmsi_per = 1;
+        pci_int_enb2.s.rmr_tto = 1;
+        pci_int_enb2.s.rmr_abt = 1;
+        pci_int_enb2.s.rtr_abt = 1;
+        pci_int_enb2.s.rmr_wtto = 1;
+        pci_int_enb2.s.rmr_wabt = 1;
+        pci_int_enb2.s.rtr_wabt = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping pci_int_enb2.s.reserved_34_63
+        pci_int_enb2.s.ill_rd = 1;
+        pci_int_enb2.s.ill_wr = 1;
+        pci_int_enb2.s.win_wr = 1;
+        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
+        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime3 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime2 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt3 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt2 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
+        pci_int_enb2.s.ill_rrd = 1;
+        pci_int_enb2.s.ill_rwr = 1;
+        pci_int_enb2.s.rdperr = 1;
+        pci_int_enb2.s.raperr = 1;
+        pci_int_enb2.s.rserr = 1;
+        pci_int_enb2.s.rtsr_abt = 1;
+        pci_int_enb2.s.rmsc_msg = 1;
+        pci_int_enb2.s.rmsi_mabt = 1;
+        pci_int_enb2.s.rmsi_tabt = 1;
+        pci_int_enb2.s.rmsi_per = 1;
+        pci_int_enb2.s.rmr_tto = 1;
+        pci_int_enb2.s.rmr_abt = 1;
+        pci_int_enb2.s.rtr_abt = 1;
+        pci_int_enb2.s.rmr_wtto = 1;
+        pci_int_enb2.s.rmr_wabt = 1;
+        pci_int_enb2.s.rtr_wabt = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping pci_int_enb2.s.reserved_34_63
+        pci_int_enb2.s.ill_rd = 1;
+        pci_int_enb2.s.ill_wr = 1;
+        pci_int_enb2.s.win_wr = 1;
+        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
+        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
+        // Skipping pci_int_enb2.s.reserved_23_24
+        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
+        // Skipping pci_int_enb2.s.reserved_19_20
+        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
+        pci_int_enb2.s.ill_rrd = 1;
+        pci_int_enb2.s.ill_rwr = 1;
+        pci_int_enb2.s.rdperr = 1;
+        pci_int_enb2.s.raperr = 1;
+        pci_int_enb2.s.rserr = 1;
+        pci_int_enb2.s.rtsr_abt = 1;
+        pci_int_enb2.s.rmsc_msg = 1;
+        pci_int_enb2.s.rmsi_mabt = 1;
+        pci_int_enb2.s.rmsi_tabt = 1;
+        pci_int_enb2.s.rmsi_per = 1;
+        pci_int_enb2.s.rmr_tto = 1;
+        pci_int_enb2.s.rmr_abt = 1;
+        pci_int_enb2.s.rtr_abt = 1;
+        pci_int_enb2.s.rmr_wtto = 1;
+        pci_int_enb2.s.rmr_wabt = 1;
+        pci_int_enb2.s.rtr_wabt = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping pci_int_enb2.s.reserved_34_63
+        pci_int_enb2.s.ill_rd = 1;
+        pci_int_enb2.s.ill_wr = 1;
+        pci_int_enb2.s.win_wr = 1;
+        // pci_int_enb2.s.dma1_fi = 1; // Not an error condition
+        // pci_int_enb2.s.dma0_fi = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdtime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rdcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime3 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime2 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime1 = 1; // Not an error condition
+        // pci_int_enb2.s.rptime0 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt3 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt2 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt1 = 1; // Not an error condition
+        // pci_int_enb2.s.rpcnt0 = 1; // Not an error condition
+        // pci_int_enb2.s.rrsl_int = 1; // Not an error condition
+        pci_int_enb2.s.ill_rrd = 1;
+        pci_int_enb2.s.ill_rwr = 1;
+        pci_int_enb2.s.rdperr = 1;
+        pci_int_enb2.s.raperr = 1;
+        pci_int_enb2.s.rserr = 1;
+        pci_int_enb2.s.rtsr_abt = 1;
+        pci_int_enb2.s.rmsc_msg = 1;
+        pci_int_enb2.s.rmsi_mabt = 1;
+        pci_int_enb2.s.rmsi_tabt = 1;
+        pci_int_enb2.s.rmsi_per = 1;
+        pci_int_enb2.s.rmr_tto = 1;
+        pci_int_enb2.s.rmr_abt = 1;
+        pci_int_enb2.s.rtr_abt = 1;
+        pci_int_enb2.s.rmr_wtto = 1;
+        pci_int_enb2.s.rmr_wabt = 1;
+        pci_int_enb2.s.rtr_wabt = 1;
+    }
+    cvmx_write_csr(CVMX_NPI_PCI_INT_ENB2, pci_int_enb2.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_pci_int_sum2_decode decodes all interrupt bits in cvmx_pci_int_sum2_t
+ */
+void __cvmx_interrupt_pci_int_sum2_decode(void)
+{
+    cvmx_pci_int_sum2_t pci_int_sum2;
+    pci_int_sum2.u64 = cvmx_read_csr(CVMX_NPI_PCI_INT_SUM2);
+    pci_int_sum2.u64 &= cvmx_read_csr(CVMX_NPI_PCI_INT_ENB2);
+    cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, pci_int_sum2.u64);
+    // Skipping pci_int_sum2.s.reserved_34_63
+    if (pci_int_sum2.s.ill_rd)
+        PRINT_ERROR("PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
+                    "    when the mem area is disabled.\n");
+    if (pci_int_sum2.s.ill_wr)
+        PRINT_ERROR("PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
+                    "    when the mem area is disabled.\n");
+    if (pci_int_sum2.s.win_wr)
+        PRINT_ERROR("PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
+                    "    Read-Address Register took place.\n");
+    if (pci_int_sum2.s.dma1_fi)
+        PRINT_ERROR("PCI_INT_SUM2[DMA1_FI]: A DMA operation operation finished that was\n"
+                    "    required to set the FORCE-INT bit for counter 1.\n");
+    if (pci_int_sum2.s.dma0_fi)
+        PRINT_ERROR("PCI_INT_SUM2[DMA0_FI]: A DMA operation operation finished that was\n"
+                    "    required to set the FORCE-INT bit for counter 0.\n");
+    if (pci_int_sum2.s.dtime1)
+        PRINT_ERROR("PCI_INT_SUM2[DTIME1]: When the value in the PCI_DMA_CNT1\n"
+                    "    register is not 0 the DMA_CNT1 timer counts.\n"
+                    "    When the DMA1_CNT timer has a value greater\n"
+                    "    than the PCI_DMA_TIME1 register this\n"
+                    "    bit is set. The timer is reset when bit is\n"
+                    "    written with a one.\n");
+    if (pci_int_sum2.s.dtime0)
+        PRINT_ERROR("PCI_INT_SUM2[DTIME0]: When the value in the PCI_DMA_CNT0\n"
+                    "    register is not 0 the DMA_CNT0 timer counts.\n"
+                    "    When the DMA0_CNT timer has a value greater\n"
+                    "    than the PCI_DMA_TIME0 register this\n"
+                    "    bit is set. The timer is reset when bit is\n"
+                    "    written with a one.\n");
+    if (pci_int_sum2.s.dcnt1)
+        PRINT_ERROR("PCI_INT_SUM2[DCNT1]: This bit indicates that PCI_DMA_CNT1\n"
+                    "    value is greater than the value\n"
+                    "    in the PCI_DMA_INT_LEV1 register.\n");
+    if (pci_int_sum2.s.dcnt0)
+        PRINT_ERROR("PCI_INT_SUM2[DCNT0]: This bit indicates that PCI_DMA_CNT0\n"
+                    "    value is greater than the value\n"
+                    "    in the PCI_DMA_INT_LEV0 register.\n");
+    if (pci_int_sum2.s.ptime3)
+        PRINT_ERROR("PCI_INT_SUM2[PTIME3]: When the value in the PCI_PKTS_SENT3\n"
+                    "    register is not 0 the Sent-3 timer counts.\n"
+                    "    When the Sent-3 timer has a value greater\n"
+                    "    than the PCI_PKTS_SENT_TIME3 register this\n"
+                    "    bit is set. The timer is reset when bit is\n"
+                    "    written with a one.\n");
+    if (pci_int_sum2.s.ptime2)
+        PRINT_ERROR("PCI_INT_SUM2[PTIME2]: When the value in the PCI_PKTS_SENT2\n"
+                    "    register is not 0 the Sent-2 timer counts.\n"
+                    "    When the Sent-2 timer has a value greater\n"
+                    "    than the PCI_PKTS_SENT_TIME2 register this\n"
+                    "    bit is set. The timer is reset when bit is\n"
+                    "    written with a one.\n");
+    if (pci_int_sum2.s.ptime1)
+        PRINT_ERROR("PCI_INT_SUM2[PTIME1]: When the value in the PCI_PKTS_SENT1\n"
+                    "    register is not 0 the Sent-1 timer counts.\n"
+                    "    When the Sent-1 timer has a value greater\n"
+                    "    than the PCI_PKTS_SENT_TIME1 register this\n"
+                    "    bit is set. The timer is reset when bit is\n"
+                    "    written with a one.\n");
+    if (pci_int_sum2.s.ptime0)
+        PRINT_ERROR("PCI_INT_SUM2[PTIME0]: When the value in the PCI_PKTS_SENT0\n"
+                    "    register is not 0 the Sent-0 timer counts.\n"
+                    "    When the Sent-0 timer has a value greater\n"
+                    "    than the PCI_PKTS_SENT_TIME0 register this\n"
+                    "    bit is set. The timer is reset when bit is\n"
+                    "    written with a one.\n");
+    if (pci_int_sum2.s.pcnt3)
+        PRINT_ERROR("PCI_INT_SUM2[PCNT3]: This bit indicates that PCI_PKTS_SENT3\n"
+                    "    value is greater than the value\n"
+                    "    in the PCI_PKTS_SENT_INT_LEV3 register.\n");
+    if (pci_int_sum2.s.pcnt2)
+        PRINT_ERROR("PCI_INT_SUM2[PCNT2]: This bit indicates that PCI_PKTS_SENT2\n"
+                    "    value is greater than the value\n"
+                    "    in the PCI_PKTS_SENT_INT_LEV2 register.\n");
+    if (pci_int_sum2.s.pcnt1)
+        PRINT_ERROR("PCI_INT_SUM2[PCNT1]: This bit indicates that PCI_PKTS_SENT1\n"
+                    "    value is greater than the value\n"
+                    "    in the PCI_PKTS_SENT_INT_LEV1 register.\n");
+    if (pci_int_sum2.s.pcnt0)
+        PRINT_ERROR("PCI_INT_SUM2[PCNT0]: This bit indicates that PCI_PKTS_SENT0\n"
+                    "    value is greater than the value\n"
+                    "    in the PCI_PKTS_SENT_INT_LEV0 register.\n");
+    if (pci_int_sum2.s.rsl_int)
+        PRINT_ERROR("PCI_INT_SUM2[RSL_INT]: This bit is set when the RSL Chain has\n"
+                    "    generated an interrupt.\n");
+    if (pci_int_sum2.s.ill_rrd)
+        PRINT_ERROR("PCI_INT_SUM2[ILL_RRD]: A read  to the disabled PCI registers took place.\n");
+    if (pci_int_sum2.s.ill_rwr)
+        PRINT_ERROR("PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n");
+    if (pci_int_sum2.s.dperr)
+        PRINT_ERROR("PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n");
+    if (pci_int_sum2.s.aperr)
+        PRINT_ERROR("PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n");
+    if (pci_int_sum2.s.serr)
+        PRINT_ERROR("PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n");
+    if (pci_int_sum2.s.tsr_abt)
+        PRINT_ERROR("PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n");
+    if (pci_int_sum2.s.msc_msg)
+        PRINT_ERROR("PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n");
+    if (pci_int_sum2.s.msi_mabt)
+        PRINT_ERROR("PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n");
+    if (pci_int_sum2.s.msi_tabt)
+        PRINT_ERROR("PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n");
+    if (pci_int_sum2.s.msi_per)
+        PRINT_ERROR("PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n");
+    if (pci_int_sum2.s.mr_tto)
+        PRINT_ERROR("PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n");
+    if (pci_int_sum2.s.mr_abt)
+        PRINT_ERROR("PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n");
+    if (pci_int_sum2.s.tr_abt)
+        PRINT_ERROR("PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n");
+    if (pci_int_sum2.s.mr_wtto)
+        PRINT_ERROR("PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n");
+    if (pci_int_sum2.s.mr_wabt)
+        PRINT_ERROR("PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n");
+    if (pci_int_sum2.s.tr_wabt)
+        PRINT_ERROR("PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n");
+}
+
+
+/**
+ * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t
+ */
+void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
+{
+    cvmx_pcsx_intx_en_reg_t pcs_int_en_reg;
+    cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
+    pcs_int_en_reg.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping pcs_int_en_reg.s.reserved_12_63
+        //pcs_int_en_reg.s.dup = 1; // This happens during normal operation
+        pcs_int_en_reg.s.sync_bad_en = 1;
+        pcs_int_en_reg.s.an_bad_en = 1;
+        pcs_int_en_reg.s.rxlock_en = 1;
+        pcs_int_en_reg.s.rxbad_en = 1;
+        //pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation
+        pcs_int_en_reg.s.txbad_en = 1;
+        pcs_int_en_reg.s.txfifo_en = 1;
+        pcs_int_en_reg.s.txfifu_en = 1;
+        pcs_int_en_reg.s.an_err_en = 1;
+        //pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation
+        //pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping pcs_int_en_reg.s.reserved_12_63
+        //pcs_int_en_reg.s.dup = 1; // This happens during normal operation
+        pcs_int_en_reg.s.sync_bad_en = 1;
+        pcs_int_en_reg.s.an_bad_en = 1;
+        pcs_int_en_reg.s.rxlock_en = 1;
+        pcs_int_en_reg.s.rxbad_en = 1;
+        //pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation
+        pcs_int_en_reg.s.txbad_en = 1;
+        pcs_int_en_reg.s.txfifo_en = 1;
+        pcs_int_en_reg.s.txfifu_en = 1;
+        pcs_int_en_reg.s.an_err_en = 1;
+        //pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation
+        //pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation
+    }
+    cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_pcsx_intx_reg_decode decodes all interrupt bits in cvmx_pcsx_intx_reg_t
+ */
+void __cvmx_interrupt_pcsx_intx_reg_decode(int index, int block)
+{
+    cvmx_pcsx_intx_reg_t pcs_int_reg;
+    pcs_int_reg.u64 = cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block));
+    pcs_int_reg.u64 &= cvmx_read_csr(CVMX_PCSX_INTX_EN_REG(index, block));
+    cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), pcs_int_reg.u64);
+    // Skipping pcs_int_reg.s.reserved_12_63
+    if (pcs_int_reg.s.dup)
+        PRINT_ERROR("PCS%d_INT%d_REG[DUP]: Set whenever Duplex mode changes on the link\n", block, index);
+    if (pcs_int_reg.s.sync_bad)
+        PRINT_ERROR("PCS%d_INT%d_REG[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
+                    "    state. Should never be set during normal operation\n", block, index);
+    if (pcs_int_reg.s.an_bad)
+        PRINT_ERROR("PCS%d_INT%d_REG[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
+                    "    state. Should never be set during normal operation\n", block, index);
+    if (pcs_int_reg.s.rxlock)
+        PRINT_ERROR("PCS%d_INT%d_REG[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
+                    "    failure occurs\n"
+                    "    Cannot fire in loopback1 mode\n", block, index);
+    if (pcs_int_reg.s.rxbad)
+        PRINT_ERROR("PCS%d_INT%d_REG[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
+                    "    state. Should never be set during normal operation\n", block, index);
+    if (pcs_int_reg.s.rxerr)
+        PRINT_ERROR("PCS%d_INT%d_REG[RXERR]: Set whenever RX receives a code group error in\n"
+                    "    10 bit to 8 bit decode logic\n"
+                    "    Cannot fire in loopback1 mode\n", block, index);
+    if (pcs_int_reg.s.txbad)
+        PRINT_ERROR("PCS%d_INT%d_REG[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
+                    "    state. Should never be set during normal operation\n", block, index);
+    if (pcs_int_reg.s.txfifo)
+        PRINT_ERROR("PCS%d_INT%d_REG[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
+                    "    condition\n", block, index);
+    if (pcs_int_reg.s.txfifu)
+        PRINT_ERROR("PCS%d_INT%d_REG[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
+                    "    condition\n", block, index);
+    if (pcs_int_reg.s.an_err)
+        PRINT_ERROR("PCS%d_INT%d_REG[AN_ERR]: AN Error, AN resolution function failed\n", block, index);
+    if (pcs_int_reg.s.xmit)
+        PRINT_ERROR("PCS%d_INT%d_REG[XMIT]: Set whenever HW detects a change in the XMIT\n"
+                    "    variable. XMIT variable states are IDLE, CONFIG and\n"
+                    "    DATA\n", block, index);
+    if (pcs_int_reg.s.lnkspd)
+        PRINT_ERROR("PCS%d_INT%d_REG[LNKSPD]: Set by HW whenever Link Speed has changed\n", block, index);
+}
+
+
+/**
+ * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t
+ */
+void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
+{
+    cvmx_pcsxx_int_en_reg_t pcsx_int_en_reg;
+    cvmx_write_csr(CVMX_PCSXX_INT_REG(index), cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
+    pcsx_int_en_reg.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping pcsx_int_en_reg.s.reserved_6_63
+        pcsx_int_en_reg.s.algnlos_en = 1;
+        pcsx_int_en_reg.s.synlos_en = 1;
+        pcsx_int_en_reg.s.bitlckls_en = 1;
+        pcsx_int_en_reg.s.rxsynbad_en = 1;
+        pcsx_int_en_reg.s.rxbad_en = 1;
+        pcsx_int_en_reg.s.txflt_en = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping pcsx_int_en_reg.s.reserved_6_63
+        pcsx_int_en_reg.s.algnlos_en = 1;
+        pcsx_int_en_reg.s.synlos_en = 1;
+        pcsx_int_en_reg.s.bitlckls_en = 0;  // Happens if XAUI module is not installed
+        pcsx_int_en_reg.s.rxsynbad_en = 1;
+        pcsx_int_en_reg.s.rxbad_en = 1;
+        pcsx_int_en_reg.s.txflt_en = 1;
+    }
+    cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_pcsxx_int_reg_decode decodes all interrupt bits in cvmx_pcsxx_int_reg_t
+ */
+void __cvmx_interrupt_pcsxx_int_reg_decode(int index)
+{
+    cvmx_pcsxx_int_reg_t pcsx_int_reg;
+    pcsx_int_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_REG(index));
+    pcsx_int_reg.u64 &= cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(index));
+    cvmx_write_csr(CVMX_PCSXX_INT_REG(index), pcsx_int_reg.u64);
+    // Skipping pcsx_int_reg.s.reserved_6_63
+    if (pcsx_int_reg.s.algnlos)
+        PRINT_ERROR("PCSX%d_INT_REG[ALGNLOS]: Set when XAUI lanes lose alignment\n", index);
+    if (pcsx_int_reg.s.synlos)
+        PRINT_ERROR("PCSX%d_INT_REG[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n", index);
+    if (pcsx_int_reg.s.bitlckls)
+        PRINT_ERROR("PCSX%d_INT_REG[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n", index);
+    if (pcsx_int_reg.s.rxsynbad)
+        PRINT_ERROR("PCSX%d_INT_REG[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
+                    "    in one of the 4 xaui lanes\n", index);
+    if (pcsx_int_reg.s.rxbad)
+        PRINT_ERROR("PCSX%d_INT_REG[RXBAD]: Set when RX state machine in bad state\n", index);
+    if (pcsx_int_reg.s.txflt)
+        PRINT_ERROR("PCSX%d_INT_REG[TXFLT]: None defined at this time, always 0x0\n", index);
+}
+
+
+/**
+ * __cvmx_interrupt_pescx_dbg_info_en_enable enables all interrupt bits in cvmx_pescx_dbg_info_en_t
+ */
+void __cvmx_interrupt_pescx_dbg_info_en_enable(int index)
+{
+    cvmx_pescx_dbg_info_en_t pesc_dbg_info_en;
+    cvmx_write_csr(CVMX_PESCX_DBG_INFO(index), cvmx_read_csr(CVMX_PESCX_DBG_INFO(index)));
+    pesc_dbg_info_en.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping pesc_dbg_info_en.s.reserved_31_63
+        pesc_dbg_info_en.s.ecrc_e = 1;
+        pesc_dbg_info_en.s.rawwpp = 1;
+        pesc_dbg_info_en.s.racpp = 1;
+        pesc_dbg_info_en.s.ramtlp = 1;
+        pesc_dbg_info_en.s.rarwdns = 1;
+        pesc_dbg_info_en.s.caar = 1;
+        pesc_dbg_info_en.s.racca = 1;
+        pesc_dbg_info_en.s.racur = 1;
+        pesc_dbg_info_en.s.rauc = 1;
+        pesc_dbg_info_en.s.rqo = 1;
+        pesc_dbg_info_en.s.fcuv = 1;
+        pesc_dbg_info_en.s.rpe = 1;
+        pesc_dbg_info_en.s.fcpvwt = 1;
+        pesc_dbg_info_en.s.dpeoosd = 1;
+        pesc_dbg_info_en.s.rtwdle = 1;
+        pesc_dbg_info_en.s.rdwdle = 1;
+        pesc_dbg_info_en.s.mre = 1;
+        pesc_dbg_info_en.s.rte = 1;
+        pesc_dbg_info_en.s.acto = 1;
+        pesc_dbg_info_en.s.rvdm = 1;
+        pesc_dbg_info_en.s.rumep = 1;
+        pesc_dbg_info_en.s.rptamrc = 1;
+        pesc_dbg_info_en.s.rpmerc = 1;
+        pesc_dbg_info_en.s.rfemrc = 1;
+        pesc_dbg_info_en.s.rnfemrc = 1;
+        pesc_dbg_info_en.s.rcemrc = 1;
+        pesc_dbg_info_en.s.rpoison = 1;
+        pesc_dbg_info_en.s.recrce = 1;
+        pesc_dbg_info_en.s.rtlplle = 1;
+#if 0
+    /* RTLPMAL is disabled since it will be generated under normal conditions,
+        like devices causing legacy PCI interrupts */
+        pesc_dbg_info_en.s.rtlpmal = 1;
+#endif
+        pesc_dbg_info_en.s.spoison = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping pesc_dbg_info_en.s.reserved_31_63
+        pesc_dbg_info_en.s.ecrc_e = 1;
+        pesc_dbg_info_en.s.rawwpp = 1;
+        pesc_dbg_info_en.s.racpp = 1;
+        pesc_dbg_info_en.s.ramtlp = 1;
+        pesc_dbg_info_en.s.rarwdns = 1;
+        pesc_dbg_info_en.s.caar = 1;
+        pesc_dbg_info_en.s.racca = 1;
+        pesc_dbg_info_en.s.racur = 1;
+        pesc_dbg_info_en.s.rauc = 1;
+        pesc_dbg_info_en.s.rqo = 1;
+        pesc_dbg_info_en.s.fcuv = 1;
+        pesc_dbg_info_en.s.rpe = 1;
+        pesc_dbg_info_en.s.fcpvwt = 1;
+        pesc_dbg_info_en.s.dpeoosd = 1;
+        pesc_dbg_info_en.s.rtwdle = 1;
+        pesc_dbg_info_en.s.rdwdle = 1;
+        pesc_dbg_info_en.s.mre = 1;
+        pesc_dbg_info_en.s.rte = 1;
+        pesc_dbg_info_en.s.acto = 1;
+        pesc_dbg_info_en.s.rvdm = 1;
+        pesc_dbg_info_en.s.rumep = 1;
+        pesc_dbg_info_en.s.rptamrc = 1;
+        pesc_dbg_info_en.s.rpmerc = 1;
+        pesc_dbg_info_en.s.rfemrc = 1;
+        pesc_dbg_info_en.s.rnfemrc = 1;
+        pesc_dbg_info_en.s.rcemrc = 1;
+        pesc_dbg_info_en.s.rpoison = 1;
+        pesc_dbg_info_en.s.recrce = 1;
+        pesc_dbg_info_en.s.rtlplle = 1;
+#if 0
+    /* RTLPMAL is disabled since it will be generated under normal conditions,
+        like devices causing legacy PCI interrupts */
+        pesc_dbg_info_en.s.rtlpmal = 1;
+#endif
+        pesc_dbg_info_en.s.spoison = 1;
+    }
+    cvmx_write_csr(CVMX_PESCX_DBG_INFO_EN(index), pesc_dbg_info_en.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_pescx_dbg_info_decode decodes all interrupt bits in cvmx_pescx_dbg_info_t
+ */
+void __cvmx_interrupt_pescx_dbg_info_decode(int index)
+{
+    cvmx_pescx_dbg_info_t pesc_dbg_info;
+    pesc_dbg_info.u64 = cvmx_read_csr(CVMX_PESCX_DBG_INFO(index));
+    pesc_dbg_info.u64 &= cvmx_read_csr(CVMX_PESCX_DBG_INFO_EN(index));
+    cvmx_write_csr(CVMX_PESCX_DBG_INFO(index), pesc_dbg_info.u64);
+    // Skipping pesc_dbg_info.s.reserved_31_63
+    if (pesc_dbg_info.s.ecrc_e)
+        PRINT_ERROR("PESC%d_DBG_INFO[ECRC_E]: Received a ECRC error.\n"
+                    "    radm_ecrc_err\n", index);
+    if (pesc_dbg_info.s.rawwpp)
+        PRINT_ERROR("PESC%d_DBG_INFO[RAWWPP]: Received a write with poisoned payload\n"
+                    "    radm_rcvd_wreq_poisoned\n", index);
+    if (pesc_dbg_info.s.racpp)
+        PRINT_ERROR("PESC%d_DBG_INFO[RACPP]: Received a completion with poisoned payload\n"
+                    "    radm_rcvd_cpl_poisoned\n", index);
+    if (pesc_dbg_info.s.ramtlp)
+        PRINT_ERROR("PESC%d_DBG_INFO[RAMTLP]: Received a malformed TLP\n"
+                    "    radm_mlf_tlp_err\n", index);
+    if (pesc_dbg_info.s.rarwdns)
+        PRINT_ERROR("PESC%d_DBG_INFO[RARWDNS]: Recieved a request which device does not support\n"
+                    "    radm_rcvd_ur_req\n", index);
+    if (pesc_dbg_info.s.caar)
+        PRINT_ERROR("PESC%d_DBG_INFO[CAAR]: Completer aborted a request\n"
+                    "    radm_rcvd_ca_req\n"
+                    "    This bit will never be set because Octeon does\n"
+                    "    not generate Completer Aborts.\n", index);
+    if (pesc_dbg_info.s.racca)
+        PRINT_ERROR("PESC%d_DBG_INFO[RACCA]: Received a completion with CA status\n"
+                    "    radm_rcvd_cpl_ca\n", index);
+    if (pesc_dbg_info.s.racur)
+        PRINT_ERROR("PESC%d_DBG_INFO[RACUR]: Received a completion with UR status\n"
+                    "    radm_rcvd_cpl_ur\n", index);
+    if (pesc_dbg_info.s.rauc)
+        PRINT_ERROR("PESC%d_DBG_INFO[RAUC]: Received an unexpected completion\n"
+                    "    radm_unexp_cpl_err\n", index);
+    if (pesc_dbg_info.s.rqo)
+        PRINT_ERROR("PESC%d_DBG_INFO[RQO]: Receive queue overflow. Normally happens only when\n"
+                    "    flow control advertisements are ignored\n"
+                    "    radm_qoverflow\n", index);
+    if (pesc_dbg_info.s.fcuv)
+        PRINT_ERROR("PESC%d_DBG_INFO[FCUV]: Flow Control Update Violation (opt. checks)\n"
+                    "    int_xadm_fc_prot_err\n", index);
+    if (pesc_dbg_info.s.rpe)
+        PRINT_ERROR("PESC%d_DBG_INFO[RPE]: When the PHY reports 8B/10B decode error\n"
+                    "    (RxStatus = 3b100) or disparity error\n"
+                    "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
+                    "    be asserted.\n"
+                    "    rmlh_rcvd_err\n", index);
+    if (pesc_dbg_info.s.fcpvwt)
+        PRINT_ERROR("PESC%d_DBG_INFO[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
+                    "    rtlh_fc_prot_err\n", index);
+    if (pesc_dbg_info.s.dpeoosd)
+        PRINT_ERROR("PESC%d_DBG_INFO[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
+                    "    rdlh_prot_err\n", index);
+    if (pesc_dbg_info.s.rtwdle)
+        PRINT_ERROR("PESC%d_DBG_INFO[RTWDLE]: Received TLP with DataLink Layer Error\n"
+                    "    rdlh_bad_tlp_err\n", index);
+    if (pesc_dbg_info.s.rdwdle)
+        PRINT_ERROR("PESC%d_DBG_INFO[RDWDLE]: Received DLLP with DataLink Layer Error\n"
+                    "    rdlh_bad_dllp_err\n", index);
+    if (pesc_dbg_info.s.mre)
+        PRINT_ERROR("PESC%d_DBG_INFO[MRE]: Max Retries Exceeded\n"
+                    "    xdlh_replay_num_rlover_err\n", index);
+    if (pesc_dbg_info.s.rte)
+        PRINT_ERROR("PESC%d_DBG_INFO[RTE]: Replay Timer Expired\n"
+                    "    xdlh_replay_timeout_err\n"
+                    "    This bit is set when the REPLAY_TIMER expires in\n"
+                    "    the PCIE core. The probability of this bit being\n"
+                    "    set will increase with the traffic load.\n", index);
+    if (pesc_dbg_info.s.acto)
+        PRINT_ERROR("PESC%d_DBG_INFO[ACTO]: A Completion Timeout Occured\n"
+                    "    pedc_radm_cpl_timeout\n", index);
+    if (pesc_dbg_info.s.rvdm)
+        PRINT_ERROR("PESC%d_DBG_INFO[RVDM]: Received Vendor-Defined Message\n"
+                    "    pedc_radm_vendor_msg\n", index);
+    if (pesc_dbg_info.s.rumep)
+        PRINT_ERROR("PESC%d_DBG_INFO[RUMEP]: Received Unlock Message (EP Mode Only)\n"
+                    "    pedc_radm_msg_unlock\n", index);
+    if (pesc_dbg_info.s.rptamrc)
+        PRINT_ERROR("PESC%d_DBG_INFO[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
+                    "    (RC Mode only)\n"
+                    "    pedc_radm_pm_to_ack\n", index);
+    if (pesc_dbg_info.s.rpmerc)
+        PRINT_ERROR("PESC%d_DBG_INFO[RPMERC]: Received PME Message (RC Mode only)\n"
+                    "    pedc_radm_pm_pme\n", index);
+    if (pesc_dbg_info.s.rfemrc)
+        PRINT_ERROR("PESC%d_DBG_INFO[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
+                    "    pedc_radm_fatal_err\n"
+                    "    Bit set when a message with ERR_FATAL is set.\n", index);
+    if (pesc_dbg_info.s.rnfemrc)
+        PRINT_ERROR("PESC%d_DBG_INFO[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
+                    "    pedc_radm_nonfatal_err\n", index);
+    if (pesc_dbg_info.s.rcemrc)
+        PRINT_ERROR("PESC%d_DBG_INFO[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
+                    "    pedc_radm_correctable_err\n", index);
+    if (pesc_dbg_info.s.rpoison)
+        PRINT_ERROR("PESC%d_DBG_INFO[RPOISON]: Received Poisoned TLP\n"
+                    "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n", index);
+    if (pesc_dbg_info.s.recrce)
+        PRINT_ERROR("PESC%d_DBG_INFO[RECRCE]: Received ECRC Error\n"
+                    "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n", index);
+    if (pesc_dbg_info.s.rtlplle)
+        PRINT_ERROR("PESC%d_DBG_INFO[RTLPLLE]: Received TLP has link layer error\n"
+                    "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n", index);
+    if (pesc_dbg_info.s.rtlpmal)
+        PRINT_ERROR("PESC%d_DBG_INFO[RTLPMAL]: Received TLP is malformed or a message.\n"
+                    "    pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot\n"
+                    "    If the core receives a MSG (or Vendor Message)\n"
+                    "    this bit will be set.\n", index);
+    if (pesc_dbg_info.s.spoison)
+        PRINT_ERROR("PESC%d_DBG_INFO[SPOISON]: Poisoned TLP sent\n"
+                    "    peai__client0_tlp_ep & peai__client0_tlp_hv\n", index);
+}
+
+
+/**
+ * __cvmx_interrupt_pip_int_en_enable enables all interrupt bits in cvmx_pip_int_en_t
+ */
+void __cvmx_interrupt_pip_int_en_enable(void)
+{
+    cvmx_pip_int_en_t pip_int_en;
+    cvmx_write_csr(CVMX_PIP_INT_REG, cvmx_read_csr(CVMX_PIP_INT_REG));
+    pip_int_en.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping pip_int_en.s.reserved_13_63
+        pip_int_en.s.punyerr = 1;
+        //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.minerr = 1; // Signalled in packet WQE
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping pip_int_en.s.reserved_9_63
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping pip_int_en.s.reserved_12_63
+        //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.minerr = 1; // Signalled in packet WQE
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        // Skipping pip_int_en.s.reserved_1_1
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping pip_int_en.s.reserved_9_63
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping pip_int_en.s.reserved_9_63
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping pip_int_en.s.reserved_13_63
+        pip_int_en.s.punyerr = 1;
+        // Skipping pip_int_en.s.reserved_9_11
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        //pip_int_en.s.crcerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping pip_int_en.s.reserved_13_63
+        pip_int_en.s.punyerr = 1;
+        //pip_int_en.s.lenerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.maxerr = 1; // Signalled in packet WQE
+        //pip_int_en.s.minerr = 1; // Signalled in packet WQE
+        pip_int_en.s.beperr = 1;
+        pip_int_en.s.feperr = 1;
+        pip_int_en.s.todoovr = 1;
+        pip_int_en.s.skprunt = 1;
+        pip_int_en.s.badtag = 1;
+        pip_int_en.s.prtnxa = 1;
+        //pip_int_en.s.bckprs = 1; // Don't care
+        // Skipping pip_int_en.s.reserved_1_1
+        //pip_int_en.s.pktdrp = 1; // Don't care
+    }
+    cvmx_write_csr(CVMX_PIP_INT_EN, pip_int_en.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_pip_int_reg_decode decodes all interrupt bits in cvmx_pip_int_reg_t
+ */
+void __cvmx_interrupt_pip_int_reg_decode(void)
+{
+    cvmx_pip_int_reg_t pip_int_reg;
+    pip_int_reg.u64 = cvmx_read_csr(CVMX_PIP_INT_REG);
+    pip_int_reg.u64 &= cvmx_read_csr(CVMX_PIP_INT_EN);
+    cvmx_write_csr(CVMX_PIP_INT_REG, pip_int_reg.u64);
+    // Skipping pip_int_reg.s.reserved_13_63
+    if (pip_int_reg.s.punyerr)
+        PRINT_ERROR("PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
+                    "    stripping in IPD is enable\n");
+    if (pip_int_reg.s.lenerr)
+        PRINT_ERROR("PIP_INT_REG[LENERR]: Frame was received with length error\n");
+    if (pip_int_reg.s.maxerr)
+        PRINT_ERROR("PIP_INT_REG[MAXERR]: Frame was received with length > max_length\n");
+    if (pip_int_reg.s.minerr)
+        PRINT_ERROR("PIP_INT_REG[MINERR]: Frame was received with length < min_length\n");
+    if (pip_int_reg.s.beperr)
+        PRINT_ERROR("PIP_INT_REG[BEPERR]: Parity Error in back end memory\n");
+    if (pip_int_reg.s.feperr)
+        PRINT_ERROR("PIP_INT_REG[FEPERR]: Parity Error in front end memory\n");
+    if (pip_int_reg.s.todoovr)
+        PRINT_ERROR("PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n");
+    if (pip_int_reg.s.skprunt)
+        PRINT_ERROR("PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
+                    "    This interrupt can occur with received PARTIAL\n"
+                    "    packets that are truncated to SKIP bytes or\n"
+                    "    smaller.\n");
+    if (pip_int_reg.s.badtag)
+        PRINT_ERROR("PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n");
+    if (pip_int_reg.s.prtnxa)
+        PRINT_ERROR("PIP_INT_REG[PRTNXA]: Non-existent port\n");
+    if (pip_int_reg.s.bckprs)
+        PRINT_ERROR("PIP_INT_REG[BCKPRS]: PIP asserted backpressure\n");
+    if (pip_int_reg.s.crcerr)
+        PRINT_ERROR("PIP_INT_REG[CRCERR]: PIP calculated bad CRC\n");
+    if (pip_int_reg.s.pktdrp)
+        PRINT_ERROR("PIP_INT_REG[PKTDRP]: Packet Dropped due to QOS\n");
+}
+
+
+/**
+ * __cvmx_interrupt_pko_reg_int_mask_enable enables all interrupt bits in cvmx_pko_reg_int_mask_t
+ */
+void __cvmx_interrupt_pko_reg_int_mask_enable(void)
+{
+    cvmx_pko_reg_int_mask_t pko_reg_int_mask;
+    cvmx_write_csr(CVMX_PKO_REG_ERROR, cvmx_read_csr(CVMX_PKO_REG_ERROR));
+    pko_reg_int_mask.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_3_63
+        pko_reg_int_mask.s.currzero = 1;
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_2_63
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_3_63
+        pko_reg_int_mask.s.currzero = 1;
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_2_63
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_2_63
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_3_63
+        pko_reg_int_mask.s.currzero = 1;
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping pko_reg_int_mask.s.reserved_3_63
+        pko_reg_int_mask.s.currzero = 1;
+        pko_reg_int_mask.s.doorbell = 1;
+        pko_reg_int_mask.s.parity = 1;
+    }
+    cvmx_write_csr(CVMX_PKO_REG_INT_MASK, pko_reg_int_mask.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_pko_reg_error_decode decodes all interrupt bits in cvmx_pko_reg_error_t
+ */
+void __cvmx_interrupt_pko_reg_error_decode(void)
+{
+    cvmx_pko_reg_error_t pko_reg_error;
+    pko_reg_error.u64 = cvmx_read_csr(CVMX_PKO_REG_ERROR);
+    pko_reg_error.u64 &= cvmx_read_csr(CVMX_PKO_REG_INT_MASK);
+    cvmx_write_csr(CVMX_PKO_REG_ERROR, pko_reg_error.u64);
+    // Skipping pko_reg_error.s.reserved_3_63
+    if (pko_reg_error.s.currzero)
+        PRINT_ERROR("PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n");
+    if (pko_reg_error.s.doorbell)
+        PRINT_ERROR("PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n");
+    if (pko_reg_error.s.parity)
+        PRINT_ERROR("PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n");
+}
+
+
+/**
+ * __cvmx_interrupt_rad_reg_int_mask_enable enables all interrupt bits in cvmx_rad_reg_int_mask_t
+ */
+void __cvmx_interrupt_rad_reg_int_mask_enable(void)
+{
+    cvmx_rad_reg_int_mask_t rad_reg_int_mask;
+    cvmx_write_csr(CVMX_RAD_REG_ERROR, cvmx_read_csr(CVMX_RAD_REG_ERROR));
+    rad_reg_int_mask.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping rad_reg_int_mask.s.reserved_1_63
+        rad_reg_int_mask.s.doorbell = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping rad_reg_int_mask.s.reserved_1_63
+        rad_reg_int_mask.s.doorbell = 1;
+    }
+    cvmx_write_csr(CVMX_RAD_REG_INT_MASK, rad_reg_int_mask.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_rad_reg_error_decode decodes all interrupt bits in cvmx_rad_reg_error_t
+ */
+void __cvmx_interrupt_rad_reg_error_decode(void)
+{
+    cvmx_rad_reg_error_t rad_reg_error;
+    rad_reg_error.u64 = cvmx_read_csr(CVMX_RAD_REG_ERROR);
+    rad_reg_error.u64 &= cvmx_read_csr(CVMX_RAD_REG_INT_MASK);
+    cvmx_write_csr(CVMX_RAD_REG_ERROR, rad_reg_error.u64);
+    // Skipping rad_reg_error.s.reserved_1_63
+    if (rad_reg_error.s.doorbell)
+        PRINT_ERROR("RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n");
+}
+
+
+/**
+ * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t
+ */
+void __cvmx_interrupt_spxx_int_msk_enable(int index)
+{
+    cvmx_spxx_int_msk_t spx_int_msk;
+    cvmx_write_csr(CVMX_SPXX_INT_REG(index), cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
+    spx_int_msk.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping spx_int_msk.s.reserved_12_63
+        spx_int_msk.s.calerr = 1;
+        spx_int_msk.s.syncerr = 1;
+        spx_int_msk.s.diperr = 1;
+        spx_int_msk.s.tpaovr = 1;
+        spx_int_msk.s.rsverr = 1;
+        spx_int_msk.s.drwnng = 1;
+        spx_int_msk.s.clserr = 1;
+        spx_int_msk.s.spiovr = 1;
+        // Skipping spx_int_msk.s.reserved_2_3
+        spx_int_msk.s.abnorm = 1;
+        spx_int_msk.s.prtnxa = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping spx_int_msk.s.reserved_12_63
+        spx_int_msk.s.calerr = 1;
+        spx_int_msk.s.syncerr = 1;
+        spx_int_msk.s.diperr = 1;
+        spx_int_msk.s.tpaovr = 1;
+        spx_int_msk.s.rsverr = 1;
+        spx_int_msk.s.drwnng = 1;
+        spx_int_msk.s.clserr = 1;
+        spx_int_msk.s.spiovr = 1;
+        // Skipping spx_int_msk.s.reserved_2_3
+        spx_int_msk.s.abnorm = 1;
+        spx_int_msk.s.prtnxa = 1;
+    }
+    cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_spxx_int_reg_decode decodes all interrupt bits in cvmx_spxx_int_reg_t
+ */
+void __cvmx_interrupt_spxx_int_reg_decode(int index)
+{
+    cvmx_spxx_int_reg_t spx_int_reg;
+    spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));
+    spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));
+    cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);
+    // Skipping spx_int_reg.s.reserved_32_63
+    if (spx_int_reg.s.spf)
+        PRINT_ERROR("SPX%d_INT_REG[SPF]: Spi interface down\n", index);
+    // Skipping spx_int_reg.s.reserved_12_30
+    if (spx_int_reg.s.calerr)
+        PRINT_ERROR("SPX%d_INT_REG[CALERR]: Spi4 Calendar table parity error\n", index);
+    if (spx_int_reg.s.syncerr)
+        PRINT_ERROR("SPX%d_INT_REG[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
+                    "    SPX_ERR_CTL[ERRCNT]\n", index);
+    if (spx_int_reg.s.diperr)
+        PRINT_ERROR("SPX%d_INT_REG[DIPERR]: Spi4 DIP4 error\n", index);
+    if (spx_int_reg.s.tpaovr)
+        PRINT_ERROR("SPX%d_INT_REG[TPAOVR]: Selected port has hit TPA overflow\n", index);
+    if (spx_int_reg.s.rsverr)
+        PRINT_ERROR("SPX%d_INT_REG[RSVERR]: Spi4 reserved control word detected\n", index);
+    if (spx_int_reg.s.drwnng)
+        PRINT_ERROR("SPX%d_INT_REG[DRWNNG]: Spi4 receive FIFO drowning/overflow\n", index);
+    if (spx_int_reg.s.clserr)
+        PRINT_ERROR("SPX%d_INT_REG[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n", index);
+    if (spx_int_reg.s.spiovr)
+        PRINT_ERROR("SPX%d_INT_REG[SPIOVR]: Spi async FIFO overflow\n", index);
+    // Skipping spx_int_reg.s.reserved_2_3
+    if (spx_int_reg.s.abnorm)
+        PRINT_ERROR("SPX%d_INT_REG[ABNORM]: Abnormal packet termination (ERR bit)\n", index);
+    if (spx_int_reg.s.prtnxa)
+        PRINT_ERROR("SPX%d_INT_REG[PRTNXA]: Port out of range\n", index);
+}
+
+
+/**
+ * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t
+ */
+void __cvmx_interrupt_stxx_int_msk_enable(int index)
+{
+    cvmx_stxx_int_msk_t stx_int_msk;
+    cvmx_write_csr(CVMX_STXX_INT_REG(index), cvmx_read_csr(CVMX_STXX_INT_REG(index)));
+    stx_int_msk.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping stx_int_msk.s.reserved_8_63
+        stx_int_msk.s.frmerr = 1;
+        stx_int_msk.s.unxfrm = 1;
+        stx_int_msk.s.nosync = 1;
+        stx_int_msk.s.diperr = 1;
+        stx_int_msk.s.datovr = 1;
+        stx_int_msk.s.ovrbst = 1;
+        stx_int_msk.s.calpar1 = 1;
+        stx_int_msk.s.calpar0 = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping stx_int_msk.s.reserved_8_63
+        stx_int_msk.s.frmerr = 1;
+        stx_int_msk.s.unxfrm = 1;
+        stx_int_msk.s.nosync = 1;
+        stx_int_msk.s.diperr = 1;
+        stx_int_msk.s.datovr = 1;
+        stx_int_msk.s.ovrbst = 1;
+        stx_int_msk.s.calpar1 = 1;
+        stx_int_msk.s.calpar0 = 1;
+    }
+    cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_stxx_int_reg_decode decodes all interrupt bits in cvmx_stxx_int_reg_t
+ */
+void __cvmx_interrupt_stxx_int_reg_decode(int index)
+{
+    cvmx_stxx_int_reg_t stx_int_reg;
+    stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));
+    stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));
+    cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);
+    // Skipping stx_int_reg.s.reserved_9_63
+    if (stx_int_reg.s.syncerr)
+        PRINT_ERROR("STX%d_INT_REG[SYNCERR]: Interface encountered a fatal error\n", index);
+    if (stx_int_reg.s.frmerr)
+        PRINT_ERROR("STX%d_INT_REG[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n", index);
+    if (stx_int_reg.s.unxfrm)
+        PRINT_ERROR("STX%d_INT_REG[UNXFRM]: Unexpected framing sequence\n", index);
+    if (stx_int_reg.s.nosync)
+        PRINT_ERROR("STX%d_INT_REG[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n", index);
+    if (stx_int_reg.s.diperr)
+        PRINT_ERROR("STX%d_INT_REG[DIPERR]: DIP2 error on the Spi4 Status channel\n", index);
+    if (stx_int_reg.s.datovr)
+        PRINT_ERROR("STX%d_INT_REG[DATOVR]: Spi4 FIFO overflow error\n", index);
+    if (stx_int_reg.s.ovrbst)
+        PRINT_ERROR("STX%d_INT_REG[OVRBST]: Transmit packet burst too big\n", index);
+    if (stx_int_reg.s.calpar1)
+        PRINT_ERROR("STX%d_INT_REG[CALPAR1]: STX Calendar Table Parity Error Bank1\n", index);
+    if (stx_int_reg.s.calpar0)
+        PRINT_ERROR("STX%d_INT_REG[CALPAR0]: STX Calendar Table Parity Error Bank0\n", index);
+}
+
+
+/**
+ * __cvmx_interrupt_usbnx_int_enb_enable enables all interrupt bits in cvmx_usbnx_int_enb_t
+ */
+void __cvmx_interrupt_usbnx_int_enb_enable(int index)
+{
+    cvmx_usbnx_int_enb_t usbn_int_enb;
+    cvmx_write_csr(CVMX_USBNX_INT_SUM(index), cvmx_read_csr(CVMX_USBNX_INT_SUM(index)));
+    usbn_int_enb.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        // Skipping usbn_int_enb.s.reserved_38_63
+        usbn_int_enb.s.nd4o_dpf = 1;
+        usbn_int_enb.s.nd4o_dpe = 1;
+        usbn_int_enb.s.nd4o_rpf = 1;
+        usbn_int_enb.s.nd4o_rpe = 1;
+        usbn_int_enb.s.ltl_f_pf = 1;
+        usbn_int_enb.s.ltl_f_pe = 1;
+        usbn_int_enb.s.u2n_c_pe = 1;
+        usbn_int_enb.s.u2n_c_pf = 1;
+        usbn_int_enb.s.u2n_d_pf = 1;
+        usbn_int_enb.s.u2n_d_pe = 1;
+        usbn_int_enb.s.n2u_pe = 1;
+        usbn_int_enb.s.n2u_pf = 1;
+        usbn_int_enb.s.uod_pf = 1;
+        usbn_int_enb.s.uod_pe = 1;
+        usbn_int_enb.s.rq_q3_e = 1;
+        usbn_int_enb.s.rq_q3_f = 1;
+        usbn_int_enb.s.rq_q2_e = 1;
+        usbn_int_enb.s.rq_q2_f = 1;
+        usbn_int_enb.s.rg_fi_f = 1;
+        usbn_int_enb.s.rg_fi_e = 1;
+        usbn_int_enb.s.l2_fi_f = 1;
+        usbn_int_enb.s.l2_fi_e = 1;
+        usbn_int_enb.s.l2c_a_f = 1;
+        usbn_int_enb.s.l2c_s_e = 1;
+        usbn_int_enb.s.dcred_f = 1;
+        usbn_int_enb.s.dcred_e = 1;
+        usbn_int_enb.s.lt_pu_f = 1;
+        usbn_int_enb.s.lt_po_e = 1;
+        usbn_int_enb.s.nt_pu_f = 1;
+        usbn_int_enb.s.nt_po_e = 1;
+        usbn_int_enb.s.pt_pu_f = 1;
+        usbn_int_enb.s.pt_po_e = 1;
+        usbn_int_enb.s.lr_pu_f = 1;
+        usbn_int_enb.s.lr_po_e = 1;
+        usbn_int_enb.s.nr_pu_f = 1;
+        usbn_int_enb.s.nr_po_e = 1;
+        usbn_int_enb.s.pr_pu_f = 1;
+        usbn_int_enb.s.pr_po_e = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        // Skipping usbn_int_enb.s.reserved_38_63
+        usbn_int_enb.s.nd4o_dpf = 1;
+        usbn_int_enb.s.nd4o_dpe = 1;
+        usbn_int_enb.s.nd4o_rpf = 1;
+        usbn_int_enb.s.nd4o_rpe = 1;
+        usbn_int_enb.s.ltl_f_pf = 1;
+        usbn_int_enb.s.ltl_f_pe = 1;
+        // Skipping usbn_int_enb.s.reserved_26_31
+        usbn_int_enb.s.uod_pf = 1;
+        usbn_int_enb.s.uod_pe = 1;
+        usbn_int_enb.s.rq_q3_e = 1;
+        usbn_int_enb.s.rq_q3_f = 1;
+        usbn_int_enb.s.rq_q2_e = 1;
+        usbn_int_enb.s.rq_q2_f = 1;
+        usbn_int_enb.s.rg_fi_f = 1;
+        usbn_int_enb.s.rg_fi_e = 1;
+        usbn_int_enb.s.l2_fi_f = 1;
+        usbn_int_enb.s.l2_fi_e = 1;
+        usbn_int_enb.s.l2c_a_f = 1;
+        usbn_int_enb.s.l2c_s_e = 1;
+        usbn_int_enb.s.dcred_f = 1;
+        usbn_int_enb.s.dcred_e = 1;
+        usbn_int_enb.s.lt_pu_f = 1;
+        usbn_int_enb.s.lt_po_e = 1;
+        usbn_int_enb.s.nt_pu_f = 1;
+        usbn_int_enb.s.nt_po_e = 1;
+        usbn_int_enb.s.pt_pu_f = 1;
+        usbn_int_enb.s.pt_po_e = 1;
+        usbn_int_enb.s.lr_pu_f = 1;
+        usbn_int_enb.s.lr_po_e = 1;
+        usbn_int_enb.s.nr_pu_f = 1;
+        usbn_int_enb.s.nr_po_e = 1;
+        usbn_int_enb.s.pr_pu_f = 1;
+        usbn_int_enb.s.pr_po_e = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping usbn_int_enb.s.reserved_38_63
+        usbn_int_enb.s.nd4o_dpf = 1;
+        usbn_int_enb.s.nd4o_dpe = 1;
+        usbn_int_enb.s.nd4o_rpf = 1;
+        usbn_int_enb.s.nd4o_rpe = 1;
+        usbn_int_enb.s.ltl_f_pf = 1;
+        usbn_int_enb.s.ltl_f_pe = 1;
+        usbn_int_enb.s.u2n_c_pe = 1;
+        usbn_int_enb.s.u2n_c_pf = 1;
+        usbn_int_enb.s.u2n_d_pf = 1;
+        usbn_int_enb.s.u2n_d_pe = 1;
+        usbn_int_enb.s.n2u_pe = 1;
+        usbn_int_enb.s.n2u_pf = 1;
+        usbn_int_enb.s.uod_pf = 1;
+        usbn_int_enb.s.uod_pe = 1;
+        usbn_int_enb.s.rq_q3_e = 1;
+        usbn_int_enb.s.rq_q3_f = 1;
+        usbn_int_enb.s.rq_q2_e = 1;
+        usbn_int_enb.s.rq_q2_f = 1;
+        usbn_int_enb.s.rg_fi_f = 1;
+        usbn_int_enb.s.rg_fi_e = 1;
+        usbn_int_enb.s.l2_fi_f = 1;
+        usbn_int_enb.s.l2_fi_e = 1;
+        usbn_int_enb.s.l2c_a_f = 1;
+        usbn_int_enb.s.l2c_s_e = 1;
+        usbn_int_enb.s.dcred_f = 1;
+        usbn_int_enb.s.dcred_e = 1;
+        usbn_int_enb.s.lt_pu_f = 1;
+        usbn_int_enb.s.lt_po_e = 1;
+        usbn_int_enb.s.nt_pu_f = 1;
+        usbn_int_enb.s.nt_po_e = 1;
+        usbn_int_enb.s.pt_pu_f = 1;
+        usbn_int_enb.s.pt_po_e = 1;
+        usbn_int_enb.s.lr_pu_f = 1;
+        usbn_int_enb.s.lr_po_e = 1;
+        usbn_int_enb.s.nr_pu_f = 1;
+        usbn_int_enb.s.nr_po_e = 1;
+        usbn_int_enb.s.pr_pu_f = 1;
+        usbn_int_enb.s.pr_po_e = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping usbn_int_enb.s.reserved_38_63
+        usbn_int_enb.s.nd4o_dpf = 1;
+        usbn_int_enb.s.nd4o_dpe = 1;
+        usbn_int_enb.s.nd4o_rpf = 1;
+        usbn_int_enb.s.nd4o_rpe = 1;
+        usbn_int_enb.s.ltl_f_pf = 1;
+        usbn_int_enb.s.ltl_f_pe = 1;
+        // Skipping usbn_int_enb.s.reserved_26_31
+        usbn_int_enb.s.uod_pf = 1;
+        usbn_int_enb.s.uod_pe = 1;
+        usbn_int_enb.s.rq_q3_e = 1;
+        usbn_int_enb.s.rq_q3_f = 1;
+        usbn_int_enb.s.rq_q2_e = 1;
+        usbn_int_enb.s.rq_q2_f = 1;
+        usbn_int_enb.s.rg_fi_f = 1;
+        usbn_int_enb.s.rg_fi_e = 1;
+        usbn_int_enb.s.l2_fi_f = 1;
+        usbn_int_enb.s.l2_fi_e = 1;
+        usbn_int_enb.s.l2c_a_f = 1;
+        usbn_int_enb.s.l2c_s_e = 1;
+        usbn_int_enb.s.dcred_f = 1;
+        usbn_int_enb.s.dcred_e = 1;
+        usbn_int_enb.s.lt_pu_f = 1;
+        usbn_int_enb.s.lt_po_e = 1;
+        usbn_int_enb.s.nt_pu_f = 1;
+        usbn_int_enb.s.nt_po_e = 1;
+        usbn_int_enb.s.pt_pu_f = 1;
+        usbn_int_enb.s.pt_po_e = 1;
+        usbn_int_enb.s.lr_pu_f = 1;
+        usbn_int_enb.s.lr_po_e = 1;
+        usbn_int_enb.s.nr_pu_f = 1;
+        usbn_int_enb.s.nr_po_e = 1;
+        usbn_int_enb.s.pr_pu_f = 1;
+        usbn_int_enb.s.pr_po_e = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        // Skipping usbn_int_enb.s.reserved_38_63
+        usbn_int_enb.s.nd4o_dpf = 1;
+        usbn_int_enb.s.nd4o_dpe = 1;
+        usbn_int_enb.s.nd4o_rpf = 1;
+        usbn_int_enb.s.nd4o_rpe = 1;
+        usbn_int_enb.s.ltl_f_pf = 1;
+        usbn_int_enb.s.ltl_f_pe = 1;
+        // Skipping usbn_int_enb.s.reserved_26_31
+        usbn_int_enb.s.uod_pf = 1;
+        usbn_int_enb.s.uod_pe = 1;
+        usbn_int_enb.s.rq_q3_e = 1;
+        usbn_int_enb.s.rq_q3_f = 1;
+        usbn_int_enb.s.rq_q2_e = 1;
+        usbn_int_enb.s.rq_q2_f = 1;
+        usbn_int_enb.s.rg_fi_f = 1;
+        usbn_int_enb.s.rg_fi_e = 1;
+        usbn_int_enb.s.l2_fi_f = 1;
+        usbn_int_enb.s.l2_fi_e = 1;
+        usbn_int_enb.s.l2c_a_f = 1;
+        usbn_int_enb.s.l2c_s_e = 1;
+        usbn_int_enb.s.dcred_f = 1;
+        usbn_int_enb.s.dcred_e = 1;
+        usbn_int_enb.s.lt_pu_f = 1;
+        usbn_int_enb.s.lt_po_e = 1;
+        usbn_int_enb.s.nt_pu_f = 1;
+        usbn_int_enb.s.nt_po_e = 1;
+        usbn_int_enb.s.pt_pu_f = 1;
+        usbn_int_enb.s.pt_po_e = 1;
+        usbn_int_enb.s.lr_pu_f = 1;
+        usbn_int_enb.s.lr_po_e = 1;
+        usbn_int_enb.s.nr_pu_f = 1;
+        usbn_int_enb.s.nr_po_e = 1;
+        usbn_int_enb.s.pr_pu_f = 1;
+        usbn_int_enb.s.pr_po_e = 1;
+    }
+    cvmx_write_csr(CVMX_USBNX_INT_ENB(index), usbn_int_enb.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_usbnx_int_sum_decode decodes all interrupt bits in cvmx_usbnx_int_sum_t
+ */
+void __cvmx_interrupt_usbnx_int_sum_decode(int index)
+{
+    cvmx_usbnx_int_sum_t usbn_int_sum;
+    usbn_int_sum.u64 = cvmx_read_csr(CVMX_USBNX_INT_SUM(index));
+    usbn_int_sum.u64 &= cvmx_read_csr(CVMX_USBNX_INT_ENB(index));
+    cvmx_write_csr(CVMX_USBNX_INT_SUM(index), usbn_int_sum.u64);
+    // Skipping usbn_int_sum.s.reserved_38_63
+    if (usbn_int_sum.s.nd4o_dpf)
+        PRINT_ERROR("USBN%d_INT_SUM[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.nd4o_dpe)
+        PRINT_ERROR("USBN%d_INT_SUM[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.nd4o_rpf)
+        PRINT_ERROR("USBN%d_INT_SUM[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.nd4o_rpe)
+        PRINT_ERROR("USBN%d_INT_SUM[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.ltl_f_pf)
+        PRINT_ERROR("USBN%d_INT_SUM[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.ltl_f_pe)
+        PRINT_ERROR("USBN%d_INT_SUM[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.u2n_c_pe)
+        PRINT_ERROR("USBN%d_INT_SUM[U2N_C_PE]: U2N Control Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.u2n_c_pf)
+        PRINT_ERROR("USBN%d_INT_SUM[U2N_C_PF]: U2N Control Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.u2n_d_pf)
+        PRINT_ERROR("USBN%d_INT_SUM[U2N_D_PF]: U2N Data Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.u2n_d_pe)
+        PRINT_ERROR("USBN%d_INT_SUM[U2N_D_PE]: U2N Data Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.n2u_pe)
+        PRINT_ERROR("USBN%d_INT_SUM[N2U_PE]: N2U Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.n2u_pf)
+        PRINT_ERROR("USBN%d_INT_SUM[N2U_PF]: N2U Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.uod_pf)
+        PRINT_ERROR("USBN%d_INT_SUM[UOD_PF]: UOD Fifo Push Full.\n", index);
+    if (usbn_int_sum.s.uod_pe)
+        PRINT_ERROR("USBN%d_INT_SUM[UOD_PE]: UOD Fifo Pop Empty.\n", index);
+    if (usbn_int_sum.s.rq_q3_e)
+        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.rq_q3_f)
+        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.rq_q2_e)
+        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.rq_q2_f)
+        PRINT_ERROR("USBN%d_INT_SUM[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.rg_fi_f)
+        PRINT_ERROR("USBN%d_INT_SUM[RG_FI_F]: Register Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.rg_fi_e)
+        PRINT_ERROR("USBN%d_INT_SUM[RG_FI_E]: Register Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.lt_fi_f)
+        PRINT_ERROR("USBN%d_INT_SUM[LT_FI_F]: L2C Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.lt_fi_e)
+        PRINT_ERROR("USBN%d_INT_SUM[LT_FI_E]: L2C Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.l2c_a_f)
+        PRINT_ERROR("USBN%d_INT_SUM[L2C_A_F]: L2C Credit Count Added When Full.\n", index);
+    if (usbn_int_sum.s.l2c_s_e)
+        PRINT_ERROR("USBN%d_INT_SUM[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n", index);
+    if (usbn_int_sum.s.dcred_f)
+        PRINT_ERROR("USBN%d_INT_SUM[DCRED_F]: Data CreditFifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.dcred_e)
+        PRINT_ERROR("USBN%d_INT_SUM[DCRED_E]: Data Credit Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.lt_pu_f)
+        PRINT_ERROR("USBN%d_INT_SUM[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.lt_po_e)
+        PRINT_ERROR("USBN%d_INT_SUM[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n", index);
+    if (usbn_int_sum.s.nt_pu_f)
+        PRINT_ERROR("USBN%d_INT_SUM[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.nt_po_e)
+        PRINT_ERROR("USBN%d_INT_SUM[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n", index);
+    if (usbn_int_sum.s.pt_pu_f)
+        PRINT_ERROR("USBN%d_INT_SUM[PT_PU_F]: PP  Trasaction Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.pt_po_e)
+        PRINT_ERROR("USBN%d_INT_SUM[PT_PO_E]: PP  Trasaction Fifo Popped When Full.\n", index);
+    if (usbn_int_sum.s.lr_pu_f)
+        PRINT_ERROR("USBN%d_INT_SUM[LR_PU_F]: L2C Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.lr_po_e)
+        PRINT_ERROR("USBN%d_INT_SUM[LR_PO_E]: L2C Request Fifo Popped When Empty.\n", index);
+    if (usbn_int_sum.s.nr_pu_f)
+        PRINT_ERROR("USBN%d_INT_SUM[NR_PU_F]: NPI Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.nr_po_e)
+        PRINT_ERROR("USBN%d_INT_SUM[NR_PO_E]: NPI Request Fifo Popped When Empty.\n", index);
+    if (usbn_int_sum.s.pr_pu_f)
+        PRINT_ERROR("USBN%d_INT_SUM[PR_PU_F]: PP  Request Fifo Pushed When Full.\n", index);
+    if (usbn_int_sum.s.pr_po_e)
+        PRINT_ERROR("USBN%d_INT_SUM[PR_PO_E]: PP  Request Fifo Popped When Empty.\n", index);
+}
+
+
+/**
+ * __cvmx_interrupt_zip_int_mask_enable enables all interrupt bits in cvmx_zip_int_mask_t
+ */
+void __cvmx_interrupt_zip_int_mask_enable(void)
+{
+    cvmx_zip_int_mask_t zip_int_mask;
+    cvmx_write_csr(CVMX_ZIP_ERROR, cvmx_read_csr(CVMX_ZIP_ERROR));
+    zip_int_mask.u64 = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        // Skipping zip_int_mask.s.reserved_1_63
+        zip_int_mask.s.doorbell = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        // Skipping zip_int_mask.s.reserved_1_63
+        zip_int_mask.s.doorbell = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        // Skipping zip_int_mask.s.reserved_1_63
+        zip_int_mask.s.doorbell = 1;
+    }
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        // Skipping zip_int_mask.s.reserved_1_63
+        zip_int_mask.s.doorbell = 1;
+    }
+    cvmx_write_csr(CVMX_ZIP_INT_MASK, zip_int_mask.u64);
+}
+
+
+/**
+ * __cvmx_interrupt_zip_error_decode decodes all interrupt bits in cvmx_zip_error_t
+ */
+void __cvmx_interrupt_zip_error_decode(void)
+{
+    cvmx_zip_error_t zip_error;
+    zip_error.u64 = cvmx_read_csr(CVMX_ZIP_ERROR);
+    zip_error.u64 &= cvmx_read_csr(CVMX_ZIP_INT_MASK);
+    cvmx_write_csr(CVMX_ZIP_ERROR, zip_error.u64);
+    // Skipping zip_error.s.reserved_1_63
+    if (zip_error.s.doorbell)
+        PRINT_ERROR("ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n");
+}
+
diff --git a/cvmx-interrupt-handler.S b/cvmx-interrupt-handler.S
new file mode 100644
index 0000000000000..af47cbc321603
--- /dev/null
+++ b/cvmx-interrupt-handler.S
@@ -0,0 +1,181 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+
+
+#include <machine/asm.h>
+#include <machine/regdef.h>
+
+.set noreorder
+.set noat
+
+LEAF(cvmx_interrupt_stage1)
+	dla     k0, cvmx_interrupt_stage2
+	jalr 	k1, k0   // Save our address in k1, so we can tell which
+                         // vector we are coming from.
+	nop
+END(cvmx_interrupt_stage1)
+
+#define STACK_SIZE  (36*8)
+LEAF(cvmx_interrupt_stage2)
+	dsubu	sp, sp, STACK_SIZE
+	sd	zero, 0(sp)	// Just a place holder
+	sd	$1, 8(sp)	// start saving registers
+	sd	$2, 16(sp)
+	sd 	$3, 24(sp)
+	sd 	$4, 32(sp)
+	sd	$5, 40(sp)
+	sd	$6, 48(sp)
+	sd	$7, 56(sp)
+	sd	$8, 64(sp)
+	sd	$9, 72(sp)
+	sd	$10, 80(sp)
+	sd	$11, 88(sp)
+	sd	$12, 96(sp)
+	sd	$13, 104(sp)
+	sd	$14, 112(sp)
+	sd	$15, 120(sp)
+	sd	$16, 128(sp)
+	sd	$17, 136(sp)
+	sd	$18, 144(sp)
+	sd	$19, 152(sp)
+	sd	$20, 160(sp)
+	sd	$21, 168(sp)
+	sd	$22, 176(sp)
+	sd	$23, 184(sp)
+	sd	$24, 192(sp)
+	sd	$25, 200(sp)
+	sd	$26, 208(sp)
+	sd	$27, 216(sp)
+	mfhi	k0		// Reading lo and high takes multiple cycles
+	mflo	k1		// Do it here so it completes by the time we need it
+	sd	$28, 224(sp)
+	daddu	$1, sp, STACK_SIZE // Correct the SP for the space we used
+	sd	$1, 232(sp)
+	sd	$30, 240(sp)
+	sd	$31, 248(sp)	// saved all general purpose registers
+	sd	k0, 256(sp)	// save hi
+	sd	k1, 264(sp)	// save lo
+        /* Save DCACHE error register early, since any non-errored DCACHE accesses will clear
+        ** error bit */
+        dmfc0   k0, $27, 1
+        sd      k0, 272(sp)
+        /* Store DEPC for GCC's frame unwinder. */
+        dmfc0   k0, $14
+        sd      k0, 280(sp)
+
+	dla     k0, cvmx_interrupt_do_irq
+	jal 	k0
+	dadd	a0, sp, 0	// First argument is array of registers
+
+	ld	k0, 256(sp)	// read hi
+	ld	k1, 264(sp)	// read lo
+	mthi	k0		// restore hi
+	mtlo	k1		// restore lo
+
+	ld	$1, 8(sp)	// start restoring registers
+	ld	$2, 16(sp)
+	ld 	$3, 24(sp)
+	ld 	$4, 32(sp)
+	ld	$5, 40(sp)
+	ld	$6, 48(sp)
+	ld	$7, 56(sp)
+	ld	$8, 64(sp)
+	ld	$9, 72(sp)
+	ld	$10, 80(sp)
+	ld	$11, 88(sp)
+	ld	$12, 96(sp)
+	ld	$13, 104(sp)
+	ld	$14, 112(sp)
+	ld	$15, 120(sp)
+	ld	$16, 128(sp)
+	ld	$17, 136(sp)
+	ld	$18, 144(sp)
+	ld	$19, 152(sp)
+	ld	$20, 160(sp)
+	ld	$21, 168(sp)
+	ld	$22, 176(sp)
+	ld	$23, 184(sp)
+	ld	$24, 192(sp)
+	ld	$25, 200(sp)
+	ld	$26, 208(sp)
+	ld	$28, 224(sp)
+	ld	$30, 240(sp)
+	ld	$31, 248(sp)	// restored all general purpose registers
+	ld	$29, 232(sp)	// No need to correct for STACK_SIZE
+	eret
+	nop
+END(cvmx_interrupt_stage2)
+
+// Icache and Dcache exception handler. This code is executed
+// with ERL set so we can't us virtual addresses. We save and restore
+// K0 to a global memory location so we can handle cache errors from exception
+// context. This means that if two cores get a cache exception at the same time
+// the K0 might be corrupted. This entire handler MUST fit in 128 bytes.
+#define K0_STORE_LOCATION	8
+#define DCACHE_ERROR_COUNT	16
+#define ICACHE_ERROR_COUNT	24
+LEAF(cvmx_interrupt_cache_error)
+	.set push
+	.set noreorder
+	sd	k0, K0_STORE_LOCATION($0)	// Store K0 into global loc in case we're in an exception
+	dmfc0	k0, $27, 1			// Get Dcache error status before any loads
+	bbit0	k0, 0, not_dcache_error		// Skip dcache count if no error
+	 dmtc0	k0, $27, 1			// Clear any Dcache errors
+	ld	k0, DCACHE_ERROR_COUNT($0)	// Load the dcache error count
+	daddu	k0, 1				// Increment the dcache error count
+	sd	k0, DCACHE_ERROR_COUNT($0)	// Store the dcache error count
+not_dcache_error:
+	dmfc0	k0, $27, 0			// Get the Icache error status
+	bbit0	k0, 0, not_icache_error		// Skip Icache count if no error
+	 dmtc0	k0, $27, 0			// Clear any Icache errors
+	ld	k0, ICACHE_ERROR_COUNT($0)	// Load the icache error count
+	daddu	k0, 1				// Increment the icache error count
+	sd	k0, ICACHE_ERROR_COUNT($0)	// Store the icache error count
+not_icache_error:
+	ld	k0, K0_STORE_LOCATION($0)	// Restore K0 since we might have been in an exception
+	eret					// Return from the Icache exception
+	.set pop
+END(cvmx_interrupt_cache_error)
+
diff --git a/cvmx-interrupt-rsl.c b/cvmx-interrupt-rsl.c
new file mode 100644
index 0000000000000..aaafc304d0ef9
--- /dev/null
+++ b/cvmx-interrupt-rsl.c
@@ -0,0 +1,762 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Utility functions to decode Octeon's RSL_INT_BLOCKS
+ * interrupts into error messages.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-interrupt.h"
+#include "cvmx-l2c.h"
+
+#ifndef PRINT_ERROR
+#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
+#endif
+
+/* Change this to a 1 before calling cvmx_interrupt_rsl_enable() to report
+    single bit ecc errors and other correctable errors */
+CVMX_SHARED int __cvmx_interrupt_ecc_report_single_bit_errors = 0;
+
+void __cvmx_interrupt_agl_gmx_rxx_int_en_enable(int index);
+void __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(int index);
+void __cvmx_interrupt_fpa_int_enb_enable(void);
+void __cvmx_interrupt_fpa_int_sum_decode(void);
+void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
+void __cvmx_interrupt_gmxx_rxx_int_reg_decode(int index, int block);
+void __cvmx_interrupt_iob_int_enb_enable(void);
+void __cvmx_interrupt_iob_int_sum_decode(void);
+void __cvmx_interrupt_ipd_int_enb_enable(void);
+void __cvmx_interrupt_ipd_int_sum_decode(void);
+void __cvmx_interrupt_key_int_enb_enable(void);
+void __cvmx_interrupt_key_int_sum_decode(void);
+void __cvmx_interrupt_mio_boot_int_enable(void);
+void __cvmx_interrupt_mio_boot_err_decode(void);
+void __cvmx_interrupt_npei_int_sum_decode(void);
+void __cvmx_interrupt_npei_int_enb2_enable(void);
+void __cvmx_interrupt_npi_int_enb_enable(void);
+void __cvmx_interrupt_npi_int_sum_decode(void);
+void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
+void __cvmx_interrupt_pcsx_intx_reg_decode(int index, int block);
+void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
+void __cvmx_interrupt_pcsxx_int_reg_decode(int index);
+void __cvmx_interrupt_pescx_dbg_info_en_enable(int index);
+void __cvmx_interrupt_pescx_dbg_info_decode(int index);
+void __cvmx_interrupt_pip_int_en_enable(void);
+void __cvmx_interrupt_pip_int_reg_decode(void);
+void __cvmx_interrupt_pko_reg_int_mask_enable(void);
+void __cvmx_interrupt_pko_reg_error_decode(void);
+void __cvmx_interrupt_rad_reg_int_mask_enable(void);
+void __cvmx_interrupt_rad_reg_error_decode(void);
+void __cvmx_interrupt_spxx_int_msk_enable(int index);
+void __cvmx_interrupt_spxx_int_reg_decode(int index);
+void __cvmx_interrupt_stxx_int_msk_enable(int index);
+void __cvmx_interrupt_stxx_int_reg_decode(int index);
+void __cvmx_interrupt_usbnx_int_enb_enable(int index);
+void __cvmx_interrupt_usbnx_int_sum_decode(int index);
+void __cvmx_interrupt_zip_int_mask_enable(void);
+void __cvmx_interrupt_zip_error_decode(void);
+
+
+/**
+ * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
+ * CN58XX.
+ *
+ * @param block  Interface to enable 0-1
+ */
+static void __cvmx_interrupt_asxx_enable(int block)
+{
+    int mask;
+    cvmx_asxx_int_en_t csr;
+    /* CN38XX and CN58XX have two interfaces with 4 ports per interface. All
+        other chips have a max of 3 ports on interface 0 */
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        mask = 0xf; /* Set enables for 4 ports */
+    else
+        mask = 0x7; /* Set enables for 3 ports */
+
+    /* Enable interface interrupts */
+    csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
+    csr.s.txpsh = mask;
+    csr.s.txpop = mask;
+    csr.s.ovrflw = mask;
+    cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
+}
+
+
+/**
+ * Decode ASX error interrupts for CN3XXX, CN50XX, and CN58XX
+ *
+ * @param block  Interface to decode 0-1
+ */
+static void __cvmx_interrupt_asxx_decode(int block)
+{
+    cvmx_asxx_int_reg_t err;
+    err.u64 = cvmx_read_csr(CVMX_ASXX_INT_REG(block));
+    cvmx_write_csr(CVMX_ASXX_INT_REG(block), err.u64);
+    if (err.u64)
+    {
+        int port;
+        for (port = 0; port < 4; port++)
+        {
+            if (err.s.ovrflw & (1 << port))
+                PRINT_ERROR("ASX%d_INT_REG[OVRFLW]: RX FIFO overflow on RMGII port %d\n",
+                             block, port + block*16);
+            if (err.s.txpop & (1 << port))
+                PRINT_ERROR("ASX%d_INT_REG[TXPOP]: TX FIFO underflow on RMGII port %d\n",
+                             block, port + block*16);
+            if (err.s.txpsh & (1 << port))
+                PRINT_ERROR("ASX%d_INT_REG[TXPSH]: TX FIFO overflow on RMGII port %d\n",
+                             block, port + block*16);
+        }
+    }
+}
+
+
+/**
+ * Enable DFA errors for CN38XX, CN58XX, and CN31XX
+ */
+static void __cvmx_interrupt_dfa_enable(void)
+{
+    cvmx_dfa_err_t csr;
+    csr.u64 = cvmx_read_csr(CVMX_DFA_ERR);
+    csr.s.dblina = 1;
+    csr.s.cp2pina = 1;
+    csr.s.cp2parena = 0;
+    csr.s.dtepina = 1;
+    csr.s.dteparena = 1;
+    csr.s.dtedbina = 1;
+    csr.s.dtesbina = __cvmx_interrupt_ecc_report_single_bit_errors;
+    csr.s.dteeccena = 1;
+    csr.s.cp2dbina = 1;
+    csr.s.cp2sbina = __cvmx_interrupt_ecc_report_single_bit_errors;
+    csr.s.cp2eccena = 1;
+    cvmx_write_csr(CVMX_DFA_ERR, csr.u64);
+}
+
+
+/**
+ * Decode DFA errors for CN38XX, CN58XX, and CN31XX
+ */
+static void __cvmx_interrupt_dfa_decode(void)
+{
+    cvmx_dfa_err_t err;
+
+    err.u64 = cvmx_read_csr(CVMX_DFA_ERR);
+    cvmx_write_csr(CVMX_DFA_ERR, err.u64);
+    if (err.u64)
+    {
+        if (err.s.dblovf)
+            PRINT_ERROR("DFA_ERR[DBLOVF]: Doorbell Overflow detected\n");
+        if (err.s.cp2perr)
+            PRINT_ERROR("DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected\n");
+        if (err.s.dteperr)
+            PRINT_ERROR("DFA_ERR[DTEPERR]: DTE Parity Error Detected\n");
+
+        if (err.s.dtedbe)
+            PRINT_ERROR("DFA_ERR[DTEDBE]: DFA DTE 29b Double Bit Error Detected\n");
+        if (err.s.dtesbe && __cvmx_interrupt_ecc_report_single_bit_errors)
+            PRINT_ERROR("DFA_ERR[DTESBE]: DFA DTE 29b Single Bit Error Corrected\n");
+        if (err.s.dtedbe || (err.s.dtesbe && __cvmx_interrupt_ecc_report_single_bit_errors))
+            PRINT_ERROR("DFA_ERR[DTESYN]: Failing syndrome %u\n", err.s.dtesyn);
+
+        if (err.s.cp2dbe)
+            PRINT_ERROR("DFA_ERR[CP2DBE]: DFA PP-CP2 Double Bit Error Detected\n");
+        if (err.s.cp2sbe && __cvmx_interrupt_ecc_report_single_bit_errors)
+            PRINT_ERROR("DFA_ERR[CP2SBE]: DFA PP-CP2 Single Bit Error Corrected\n");
+        if (err.s.cp2dbe || (err.s.cp2sbe && __cvmx_interrupt_ecc_report_single_bit_errors))
+            PRINT_ERROR("DFA_ERR[CP2SYN]: Failing syndrome %u\n", err.s.cp2syn);
+    }
+}
+
+
+/**
+ * Enable L2 error interrupts for all chips
+ */
+static void __cvmx_interrupt_l2_enable(void)
+{
+    cvmx_l2t_err_t csr;
+    cvmx_l2d_err_t csr2;
+
+    /* Enable ECC Interrupts for double bit errors from L2C Tags */
+    csr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+    csr.s.lck_intena2 = 1;
+    csr.s.lck_intena = 1;
+    csr.s.ded_intena = 1;
+    csr.s.sec_intena = __cvmx_interrupt_ecc_report_single_bit_errors;
+    csr.s.ecc_ena = 1;
+    cvmx_write_csr(CVMX_L2T_ERR, csr.u64);
+
+    /* Enable ECC Interrupts for double bit errors from L2D Errors */
+    csr2.u64 = cvmx_read_csr(CVMX_L2D_ERR);
+    csr2.s.ded_intena = 1;
+    csr2.s.sec_intena = __cvmx_interrupt_ecc_report_single_bit_errors;
+    csr2.s.ecc_ena = 1;
+    cvmx_write_csr(CVMX_L2D_ERR, csr2.u64);
+}
+
+
+/**
+ * Decode L2 error interrupts for all chips
+ */
+static void __cvmx_interrupt_l2_decode(void)
+{
+    cvmx_l2t_err_t terr;
+    cvmx_l2d_err_t derr;
+    uint64_t clr_val;
+
+    terr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+    cvmx_write_csr(CVMX_L2T_ERR, terr.u64);
+    if (terr.u64)
+    {
+        if (terr.s.ded_err)
+            PRINT_ERROR("L2T_ERR[DED_ERR]: double bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
+                         terr.s.fadr, terr.s.fset, terr.s.fsyn);
+        if (terr.s.sec_err && __cvmx_interrupt_ecc_report_single_bit_errors)
+            PRINT_ERROR("L2T_ERR[SEC_ERR]: single bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
+                         terr.s.fadr, terr.s.fset, terr.s.fsyn);
+        if (terr.s.ded_err || terr.s.sec_err)
+        {
+            if (!terr.s.fsyn)
+            {
+                /* Syndrome is zero, which means error was in non-hit line,
+                    so flush all associations */
+                int i;
+                int l2_assoc = cvmx_l2c_get_num_assoc();
+
+                for (i = 0; i < l2_assoc; i++)
+                    cvmx_l2c_flush_line(i, terr.s.fadr);
+            }
+            else
+                cvmx_l2c_flush_line(terr.s.fset, terr.s.fadr);
+
+        }
+        if (terr.s.lckerr2)
+            PRINT_ERROR("L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n could not find an available/unlocked set (for replacement).\n");
+        if (terr.s.lckerr)
+            PRINT_ERROR("L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of the INDEX (which is ignored by HW - but reported to SW).\n");
+    }
+
+    clr_val = derr.u64 = cvmx_read_csr(CVMX_L2D_ERR);
+    if (derr.u64)
+    {
+        cvmx_l2d_fadr_t fadr;
+
+        if (derr.s.ded_err || (derr.s.sec_err && __cvmx_interrupt_ecc_report_single_bit_errors))
+        {
+            const int coreid = (int) cvmx_get_core_num();
+            uint64_t syn0 = cvmx_read_csr(CVMX_L2D_FSYN0);
+            uint64_t syn1 = cvmx_read_csr(CVMX_L2D_FSYN1);
+            fadr.u64 = cvmx_read_csr(CVMX_L2D_FADR);
+            if (derr.s.ded_err)
+                PRINT_ERROR("L2D_ERR[DED_ERR] ECC double (core %d): fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
+                             coreid, (unsigned long long) fadr.u64, (unsigned long long) syn0, (unsigned long long) syn1);
+            else
+                PRINT_ERROR("L2D_ERR[SEC_ERR] ECC single (core %d): fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
+                             coreid, (unsigned long long) fadr.u64, (unsigned long long) syn0, (unsigned long long) syn1);
+            /* Flush the line that had the error */
+            if (derr.s.ded_err || derr.s.sec_err)
+                cvmx_l2c_flush_line(fadr.s.fset, fadr.s.fadr >> 1);
+        }
+    }
+    cvmx_write_csr(CVMX_L2D_ERR, clr_val);
+}
+
+
+/**
+ * Enable LMC (DDR controller) interrupts for all chips
+ *
+ * @param ddr_controller
+ *               Which controller to enable for 0-1
+ */
+static void __cvmx_interrupt_lmcx_enable(int ddr_controller)
+{
+    cvmx_lmc_mem_cfg0_t csr;
+
+    /* The LMC controllers can be independently enabled/disabled on CN56XX.
+        If a controller is disabled it can't be accessed at all since it
+        isn't clocked */
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        cvmx_l2c_cfg_t l2c_cfg;
+        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        if (!l2c_cfg.s.dpres0 && (ddr_controller == 0))
+            return;
+        if (!l2c_cfg.s.dpres1 && (ddr_controller == 1))
+            return;
+    }
+
+    csr.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(ddr_controller));
+    csr.s.intr_ded_ena = 1;
+    csr.s.intr_sec_ena = __cvmx_interrupt_ecc_report_single_bit_errors;
+    cvmx_write_csr(CVMX_LMCX_MEM_CFG0(ddr_controller), csr.u64);
+}
+
+
+/**
+ * Decode LMC (DDR controller) interrupts for all chips
+ *
+ * @param ddr_controller
+ *               Which controller to decode 0-1
+ */
+static void __cvmx_interrupt_lmcx_decode(int ddr_controller)
+{
+    /* These static counters are used to track ECC error counts */
+    static CVMX_SHARED unsigned long single_bit_errors[2] = {0, 0};
+    static CVMX_SHARED unsigned long double_bit_errors[2] = {0, 0};
+    cvmx_lmcx_mem_cfg0_t mem_cfg0;
+    cvmx_lmc_fadr_t fadr;
+
+    mem_cfg0.u64 =cvmx_read_csr(CVMX_LMCX_MEM_CFG0(ddr_controller));
+    fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR (ddr_controller));
+    cvmx_write_csr(CVMX_LMCX_MEM_CFG0(ddr_controller),mem_cfg0.u64);
+    if (mem_cfg0.s.sec_err || mem_cfg0.s.ded_err)
+    {
+        int pop_count;
+        CVMX_DPOP(pop_count, mem_cfg0.s.sec_err);
+        single_bit_errors[ddr_controller] += pop_count;
+        CVMX_DPOP(pop_count, mem_cfg0.s.ded_err);
+        double_bit_errors[ddr_controller] += pop_count;
+        if (mem_cfg0.s.ded_err || (mem_cfg0.s.sec_err && __cvmx_interrupt_ecc_report_single_bit_errors))
+        {
+            PRINT_ERROR("DDR%d ECC: %lu Single bit corrections, %lu Double bit errors\n"
+                         "DDR%d ECC:\tFailing dimm:   %u\n"
+                         "DDR%d ECC:\tFailing rank:   %u\n"
+                         "DDR%d ECC:\tFailing bank:   %u\n"
+                         "DDR%d ECC:\tFailing row:    0x%x\n"
+                         "DDR%d ECC:\tFailing column: 0x%x\n",
+                         ddr_controller, single_bit_errors[ddr_controller], double_bit_errors[ddr_controller],
+                         ddr_controller, fadr.s.fdimm,
+                         ddr_controller, fadr.s.fbunk,
+                         ddr_controller, fadr.s.fbank,
+                         ddr_controller, fadr.s.frow,
+                         ddr_controller, fadr.s.fcol);
+        }
+    }
+}
+
+
+/**
+ * Decode GMX error interrupts
+ *
+ * @param block  GMX interface to decode
+ */
+static void __cvmx_interrupt_gmxx_decode(int block)
+{
+    int index;
+    cvmx_gmxx_tx_int_reg_t csr;
+
+    csr.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_REG(block)) & cvmx_read_csr(CVMX_GMXX_TX_INT_EN(block));
+    cvmx_write_csr(CVMX_GMXX_TX_INT_REG(block), csr.u64);
+
+    for (index=0; index<4; index++)
+    {
+        if (csr.s.late_col & (1<<index))
+            PRINT_ERROR("GMX%d_TX%d_INT_REG[LATE_COL]: TX Late Collision\n", block, index);
+        if (csr.s.xsdef & (1<<index))
+            PRINT_ERROR("GMX%d_TX%d_INT_REG[XSDEF]: TX Excessive deferral\n", block, index);
+        if (csr.s.xscol & (1<<index))
+            PRINT_ERROR("GMX%d_TX%d_INT_REG[XSCOL]: TX Excessive collisions\n", block, index);
+        if (csr.s.undflw & (1<<index))
+            PRINT_ERROR("GMX%d_TX%d_INT_REG[UNDFLW]: TX Underflow\n", block, index);
+    }
+    if (csr.s.ncb_nxa)
+        PRINT_ERROR("GMX%d_TX_INT_REG[NCB_NXA]: Port address out-of-range from NCB Interface\n", block);
+    if (csr.s.pko_nxa)
+        PRINT_ERROR("GMX%d_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n", block);
+
+    __cvmx_interrupt_gmxx_rxx_int_reg_decode(0, block);
+    __cvmx_interrupt_gmxx_rxx_int_reg_decode(1, block);
+    __cvmx_interrupt_gmxx_rxx_int_reg_decode(2, block);
+    if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
+        __cvmx_interrupt_gmxx_rxx_int_reg_decode(3, block);
+}
+
+
+/**
+ * Enable POW error interrupts for all chips
+ */
+static void __cvmx_interrupt_pow_enable(void)
+{
+    cvmx_pow_ecc_err_t csr;
+    csr.u64 = cvmx_read_csr(CVMX_POW_ECC_ERR);
+    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) && !OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+            /* These doesn't exist for chips CN31XX and CN38XXp2 */
+            csr.s.iop_ie = 0x1fff;
+    }
+    csr.s.rpe_ie = 1;
+    csr.s.dbe_ie = 1;
+    csr.s.sbe_ie = __cvmx_interrupt_ecc_report_single_bit_errors;
+    cvmx_write_csr(CVMX_POW_ECC_ERR, csr.u64);
+}
+
+
+/**
+ * Decode POW error interrupts for all chips
+ */
+static void __cvmx_interrupt_pow_decode(void)
+{
+    cvmx_pow_ecc_err_t err;
+
+    err.u64 = cvmx_read_csr(CVMX_POW_ECC_ERR);
+    cvmx_write_csr(CVMX_POW_ECC_ERR, err.u64);
+    if (err.u64)
+    {
+        if (err.s.sbe && __cvmx_interrupt_ecc_report_single_bit_errors)
+            PRINT_ERROR("POW_ECC_ERR[SBE]: POW single bit error\n");
+        if (err.s.dbe)
+            PRINT_ERROR("POW_ECC_ERR[DBE]: POW double bit error\n");
+        if (err.s.dbe || (err.s.sbe && __cvmx_interrupt_ecc_report_single_bit_errors))
+            PRINT_ERROR("POW_ECC_ERR[SYN]: Failing syndrome %u\n", err.s.syn);
+        if (err.s.rpe)
+            PRINT_ERROR("POW_ECC_ERR[RPE]: Remote pointer error\n");
+        if (err.s.iop & (1 << 0))
+            PRINT_ERROR("POW_ECC_ERR[IOP0]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state\n");
+        if (err.s.iop & (1 << 1))
+            PRINT_ERROR("POW_ECC_ERR[IOP1]: Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state\n");
+        if (err.s.iop & (1 << 2))
+            PRINT_ERROR("POW_ECC_ERR[IOP2]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC\n");
+        if (err.s.iop & (1 << 3))
+            PRINT_ERROR("POW_ECC_ERR[IOP3]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL\n");
+        if (err.s.iop & (1 << 4))
+            PRINT_ERROR("POW_ECC_ERR[IOP4]: Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL\n");
+        if (err.s.iop & (1 << 5))
+            PRINT_ERROR("POW_ECC_ERR[IOP5]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending\n");
+        if (err.s.iop & (1 << 6))
+            PRINT_ERROR("POW_ECC_ERR[IOP6]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending\n");
+        if (err.s.iop & (1 << 7))
+            PRINT_ERROR("POW_ECC_ERR[IOP7]: Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending\n");
+        if (err.s.iop & (1 << 8))
+            PRINT_ERROR("POW_ECC_ERR[IOP8]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending\n");
+        if (err.s.iop & (1 << 9))
+            PRINT_ERROR("POW_ECC_ERR[IOP9]: Received illegal opcode\n");
+        if (err.s.iop & (1 << 10))
+            PRINT_ERROR("POW_ECC_ERR[IOP10]: Received ADD_WORK with tag specified as NULL_NULL\n");
+        if (err.s.iop & (1 << 11))
+            PRINT_ERROR("POW_ECC_ERR[IOP11]: Received DBG load from PP with DBG load pending\n");
+        if (err.s.iop & (1 << 12))
+            PRINT_ERROR("POW_ECC_ERR[IOP12]: Received CSR load from PP with CSR load pending\n");
+    }
+}
+
+
+/**
+ * Enable TIM tiemr wheel interrupts for all chips
+ */
+static void __cvmx_interrupt_tim_enable(void)
+{
+    cvmx_tim_reg_int_mask_t csr;
+    csr.u64 = cvmx_read_csr(CVMX_TIM_REG_INT_MASK);
+    csr.s.mask = 0xffff;
+    cvmx_write_csr(CVMX_TIM_REG_INT_MASK, csr.u64);
+}
+
+
+/**
+ * Decode TIM timer wheel interrupts
+ */
+static void __cvmx_interrupt_tim_decode(void)
+{
+    cvmx_tim_reg_error_t err;
+
+    err.u64 = cvmx_read_csr(CVMX_TIM_REG_ERROR);
+    cvmx_write_csr(CVMX_TIM_REG_ERROR, err.u64);
+    if (err.u64)
+    {
+        int i;
+        for (i = 0; i < 16; i++)
+            if (err.s.mask & (1 << i))
+                PRINT_ERROR("TIM_REG_ERROR[MASK]: Timer wheel %d error\n", i);
+    }
+}
+
+
+/**
+ * Utility function to decode Octeon's RSL_INT_BLOCKS interrupts
+ * into error messages.
+ */
+void cvmx_interrupt_rsl_decode(void)
+{
+    uint64_t rsl_int_blocks;
+
+    /* Reading the RSL interrupts is different between PCI and PCIe chips */
+    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        rsl_int_blocks = cvmx_read_csr(CVMX_PEXP_NPEI_RSL_INT_BLOCKS);
+    else
+        rsl_int_blocks = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
+
+    /* Not all chips support all error interrupts. This code assumes
+        that unsupported interrupts always are zero */
+
+    /* Bits 63-31 are unused on all chips */
+    if (rsl_int_blocks & (1ull<<30)) __cvmx_interrupt_iob_int_sum_decode();
+    if (rsl_int_blocks & (1ull<<29)) __cvmx_interrupt_lmcx_decode(1);
+    if (rsl_int_blocks & (1ull<<28))
+    {
+        __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(0);
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+            __cvmx_interrupt_agl_gmx_rxx_int_reg_decode(1);
+    }
+    /* Bit 27-24 are unused on all chips */
+    if (rsl_int_blocks & (1ull<<23))
+    {
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        {
+            __cvmx_interrupt_pcsx_intx_reg_decode(0, 1);
+            __cvmx_interrupt_pcsx_intx_reg_decode(1, 1);
+            __cvmx_interrupt_pcsx_intx_reg_decode(2, 1);
+            __cvmx_interrupt_pcsx_intx_reg_decode(3, 1);
+            __cvmx_interrupt_pcsxx_int_reg_decode(1);
+        }
+        else
+            __cvmx_interrupt_asxx_decode(1);
+    }
+    if (rsl_int_blocks & (1ull<<22))
+    {
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+        {
+            __cvmx_interrupt_pcsx_intx_reg_decode(0, 0);
+            __cvmx_interrupt_pcsx_intx_reg_decode(1, 0);
+            __cvmx_interrupt_pcsx_intx_reg_decode(2, 0);
+            __cvmx_interrupt_pcsx_intx_reg_decode(3, 0);
+            __cvmx_interrupt_pcsxx_int_reg_decode(0);
+        }
+        else
+            __cvmx_interrupt_asxx_decode(0);
+    }
+    /* Bit 21 is unsed on all chips */
+    if (rsl_int_blocks & (1ull<<20)) __cvmx_interrupt_pip_int_reg_decode();
+    if (rsl_int_blocks & (1ull<<19))
+    {
+        __cvmx_interrupt_spxx_int_reg_decode(1);
+        __cvmx_interrupt_stxx_int_reg_decode(1);
+    }
+    if (rsl_int_blocks & (1ull<<18))
+    {
+        __cvmx_interrupt_spxx_int_reg_decode(0);
+        __cvmx_interrupt_stxx_int_reg_decode(0);
+    }
+    if (rsl_int_blocks & (1ull<<17)) __cvmx_interrupt_lmcx_decode(0);
+    if (rsl_int_blocks & (1ull<<16)) __cvmx_interrupt_l2_decode();
+    if (rsl_int_blocks & (1ull<<15)) __cvmx_interrupt_usbnx_int_sum_decode(1);
+    if (rsl_int_blocks & (1ull<<14)) __cvmx_interrupt_rad_reg_error_decode();
+    if (rsl_int_blocks & (1ull<<13)) __cvmx_interrupt_usbnx_int_sum_decode(0);
+    if (rsl_int_blocks & (1ull<<12)) __cvmx_interrupt_pow_decode();
+    if (rsl_int_blocks & (1ull<<11)) __cvmx_interrupt_tim_decode();
+    if (rsl_int_blocks & (1ull<<10)) __cvmx_interrupt_pko_reg_error_decode();
+    if (rsl_int_blocks & (1ull<< 9)) __cvmx_interrupt_ipd_int_sum_decode();
+    /* Bit 8 is unused on all chips */
+    if (rsl_int_blocks & (1ull<< 7)) __cvmx_interrupt_zip_error_decode();
+    if (rsl_int_blocks & (1ull<< 6)) __cvmx_interrupt_dfa_decode();
+    if (rsl_int_blocks & (1ull<< 5)) __cvmx_interrupt_fpa_int_sum_decode();
+    if (rsl_int_blocks & (1ull<< 4)) __cvmx_interrupt_key_int_sum_decode();
+    if (rsl_int_blocks & (1ull<< 3))
+    {
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+            __cvmx_interrupt_npei_int_sum_decode();
+        else
+            __cvmx_interrupt_npi_int_sum_decode();
+    }
+    if (rsl_int_blocks & (1ull<< 2)) __cvmx_interrupt_gmxx_decode(1);
+    if (rsl_int_blocks & (1ull<< 1)) __cvmx_interrupt_gmxx_decode(0);
+    if (rsl_int_blocks & (1ull<< 0)) __cvmx_interrupt_mio_boot_err_decode();
+}
+
+
+/**
+ * Enable GMX error reporting for the supplied interface
+ *
+ * @param interface Interface to enable
+ */
+static void __cvmx_interrupt_gmxx_enable(int interface)
+{
+    cvmx_gmxx_inf_mode_t mode;
+    cvmx_gmxx_tx_int_en_t gmx_tx_int_en;
+    int num_ports;
+    int index;
+
+    mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        if (mode.s.en)
+        {
+            switch(mode.cn56xx.mode)
+            {
+                case 1: /* XAUI */
+                    num_ports = 1;
+                    break;
+                case 2: /* SGMII */
+                case 3: /* PICMG */
+                    num_ports = 4;
+                    break;
+                default: /* Disabled */
+                    num_ports = 0;
+                    break;
+            }
+        }
+        else
+            num_ports = 0;
+    }
+    else
+    {
+        if (mode.s.en)
+        {
+            if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+            {
+                /* SPI on CN38XX and CN58XX report all errors through port 0.
+                    RGMII needs to check all 4 ports */
+                if (mode.s.type)
+                    num_ports = 1;
+                else
+                    num_ports = 4;
+            }
+            else
+            {
+                /* CN30XX, CN31XX, and CN50XX have two or three ports. GMII
+                    and MII has 2, RGMII has three */
+                if (mode.s.type)
+                    num_ports = 2;
+                else
+                    num_ports = 3;
+            }
+        }
+        else
+            num_ports = 0;
+    }
+
+    gmx_tx_int_en.u64 = 0;
+    if (num_ports)
+    {
+        gmx_tx_int_en.s.ncb_nxa = 1;
+        gmx_tx_int_en.s.pko_nxa = 1;
+    }
+    gmx_tx_int_en.s.undflw = (1<<num_ports)-1;
+    cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
+    for (index=0; index<num_ports;index++)
+        __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
+}
+
+
+/**
+ * Utility function to enable all RSL error interupts
+ */
+void cvmx_interrupt_rsl_enable(void)
+{
+    /* Bits 63-31 are unused on all chips */
+    __cvmx_interrupt_iob_int_enb_enable();
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+        __cvmx_interrupt_lmcx_enable(1);
+    if (octeon_has_feature(OCTEON_FEATURE_MGMT_PORT))
+    {
+        // FIXME __cvmx_interrupt_agl_gmx_rxx_int_en_enable(0);
+        //if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        //    __cvmx_interrupt_agl_gmx_rxx_int_en_enable(1);
+    }
+    /* Bit 27-24 are unused on all chips */
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        __cvmx_interrupt_asxx_enable(1);
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(0, 1);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(1, 1);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(2, 1);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(3, 1);
+        __cvmx_interrupt_pcsxx_int_en_reg_enable(1);
+    }
+    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(0, 0);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(1, 0);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(2, 0);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(3, 0);
+        __cvmx_interrupt_pcsxx_int_en_reg_enable(0);
+    }
+    else
+        __cvmx_interrupt_asxx_enable(0);
+    /* Bit 21 is unsed on all chips */
+    __cvmx_interrupt_pip_int_en_enable();
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        __cvmx_interrupt_spxx_int_msk_enable(1);
+        __cvmx_interrupt_stxx_int_msk_enable(1);
+        __cvmx_interrupt_spxx_int_msk_enable(0);
+        __cvmx_interrupt_stxx_int_msk_enable(0);
+    }
+    __cvmx_interrupt_lmcx_enable(0);
+    __cvmx_interrupt_l2_enable();
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        __cvmx_interrupt_usbnx_int_enb_enable(1);
+    if (octeon_has_feature(OCTEON_FEATURE_RAID))
+        __cvmx_interrupt_rad_reg_int_mask_enable();
+    if (octeon_has_feature(OCTEON_FEATURE_USB))
+        __cvmx_interrupt_usbnx_int_enb_enable(0);
+    __cvmx_interrupt_pow_enable();
+    __cvmx_interrupt_tim_enable();
+    __cvmx_interrupt_pko_reg_int_mask_enable();
+    __cvmx_interrupt_ipd_int_enb_enable();
+    /* Bit 8 is unused on all chips */
+    if (octeon_has_feature(OCTEON_FEATURE_ZIP))
+        __cvmx_interrupt_zip_int_mask_enable();
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        __cvmx_interrupt_dfa_enable();
+    __cvmx_interrupt_fpa_int_enb_enable();
+    if (octeon_has_feature(OCTEON_FEATURE_KEY_MEMORY))
+        __cvmx_interrupt_key_int_enb_enable();
+    if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+    {
+        cvmx_ciu_soft_prst_t ciu_soft_prst;
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        if (ciu_soft_prst.s.soft_prst == 0)
+            __cvmx_interrupt_npei_int_enb2_enable();
+    }
+    else if (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST)
+        __cvmx_interrupt_npi_int_enb_enable();
+
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN56XX))
+        __cvmx_interrupt_gmxx_enable(1);
+    __cvmx_interrupt_gmxx_enable(0);
+
+    __cvmx_interrupt_mio_boot_int_enable();
+}
+
diff --git a/cvmx-interrupt.c b/cvmx-interrupt.c
new file mode 100644
index 0000000000000..fdf3645c320d3
--- /dev/null
+++ b/cvmx-interrupt.c
@@ -0,0 +1,528 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the Mips interrupts.
+ *
+ * <hr>$Revision: 42264 $<hr>
+ */
+#if __GNUC__ >= 4
+/* Backtrace is only available with the new toolchain.  */
+#include <execinfo.h>
+#endif
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-interrupt.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-uart.h"
+#include "cvmx-pow.h"
+#include "cvmx-ebt3000.h"
+#include "cvmx-coremask.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-app-init.h"
+
+EXTERN_ASM void cvmx_interrupt_stage1(void);
+EXTERN_ASM void cvmx_interrupt_cache_error(void);
+
+/**
+ * Internal status the interrupt registration
+ */
+typedef struct
+{
+    cvmx_interrupt_func_t handlers[256];  /**< One function to call per interrupt */
+    void *                data[256];      /**< User data per interrupt */
+    cvmx_interrupt_exception_t exception_handler;
+} cvmx_interrupt_state_t;
+
+/**
+ * Internal state the interrupt registration
+ */
+static CVMX_SHARED cvmx_interrupt_state_t cvmx_interrupt_state;
+static CVMX_SHARED cvmx_spinlock_t cvmx_interrupt_default_lock;
+
+#define COP0_CAUSE      "$13,0"
+#define COP0_STATUS     "$12,0"
+#define COP0_BADVADDR   "$8,0"
+#define COP0_EPC        "$14,0"
+#define READ_COP0(dest, R) asm volatile ("dmfc0 %[rt]," R : [rt] "=r" (dest))
+#define ULL unsigned long long
+
+
+
+/**
+ * @INTERNAL
+ * Dump all useful registers to the console
+ *
+ * @param registers CPU register to dump
+ */
+static void __cvmx_interrupt_dump_registers(uint64_t registers[32])
+{
+    static const char *name[32] = {"r0","at","v0","v1","a0","a1","a2","a3",
+        "t0","t1","t2","t3","t4","t5","t6","t7","s0","s1","s2","s3","s4","s5",
+        "s6","s7", "t8","t9", "k0","k1","gp","sp","s8","ra"};
+    uint64_t reg;
+    for (reg=0; reg<16; reg++)
+    {
+        cvmx_safe_printf("%3s ($%02d): 0x%016llx \t %3s ($%02d): 0x%016llx\n",
+               name[reg], (int)reg, (ULL)registers[reg], name[reg+16], (int)reg+16, (ULL)registers[reg+16]);
+    }
+    READ_COP0(reg, COP0_CAUSE);
+    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_CAUSE", (ULL)reg);
+    READ_COP0(reg, COP0_STATUS);
+    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_STATUS", (ULL)reg);
+    READ_COP0(reg, COP0_BADVADDR);
+    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_BADVADDR", (ULL)reg);
+    READ_COP0(reg, COP0_EPC);
+    cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_EPC", (ULL)reg);
+}
+
+
+/**
+ * @INTERNAL
+ * Default exception handler. Prints out the exception
+ * cause decode and all relevant registers.
+ *
+ * @param registers Registers at time of the exception
+ */
+static void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
+{
+    uint64_t trap_print_cause;
+
+    ebt3000_str_write("Trap");
+    cvmx_spinlock_lock(&cvmx_interrupt_default_lock);
+    cvmx_safe_printf("******************************************************************\n");
+    cvmx_safe_printf("Core %d: Unhandled Exception. Cause register decodes to:\n", (int)cvmx_get_core_num());
+    READ_COP0(trap_print_cause, COP0_CAUSE);
+    switch ((trap_print_cause >> 2) & 0x1f)
+    {
+        case 0x0:
+            cvmx_safe_printf("Interrupt\n");
+            break;
+        case 0x1:
+            cvmx_safe_printf("TLB Mod\n");
+            break;
+        case 0x2:
+            cvmx_safe_printf("tlb load/fetch\n");
+            break;
+        case 0x3:
+            cvmx_safe_printf("tlb store\n");
+            break;
+        case 0x4:
+            cvmx_safe_printf("address exc, load/fetch\n");
+            break;
+        case 0x5:
+            cvmx_safe_printf("address exc, store\n");
+            break;
+        case 0x6:
+            cvmx_safe_printf("bus error, inst. fetch\n");
+            break;
+        case 0x7:
+            cvmx_safe_printf("bus error, load/store\n");
+            break;
+        case 0x8:
+            cvmx_safe_printf("syscall\n");
+            break;
+        case 0x9:
+            cvmx_safe_printf("breakpoint \n");
+            break;
+        case 0xa:
+            cvmx_safe_printf("reserved instruction\n");
+            break;
+        case 0xb:
+            cvmx_safe_printf("cop unusable\n");
+            break;
+        case 0xc:
+            cvmx_safe_printf("arithmetic overflow\n");
+            break;
+        case 0xd:
+            cvmx_safe_printf("trap\n");
+            break;
+        case 0xf:
+            cvmx_safe_printf("floating point exc\n");
+            break;
+        case 0x12:
+            cvmx_safe_printf("cop2 exception\n");
+            break;
+        case 0x16:
+            cvmx_safe_printf("mdmx unusable\n");
+            break;
+        case 0x17:
+            cvmx_safe_printf("watch\n");
+            break;
+        case 0x18:
+            cvmx_safe_printf("machine check\n");
+            break;
+        case 0x1e:
+            cvmx_safe_printf("cache error\n");
+            break;
+        default:
+            cvmx_safe_printf("Reserved exception cause.\n");
+            break;
+
+    }
+
+    cvmx_safe_printf("******************************************************************\n");
+    __cvmx_interrupt_dump_registers(registers);
+    cvmx_safe_printf("******************************************************************\n");
+
+#if __GNUC__ >= 4 && !defined(OCTEON_DISABLE_BACKTRACE)
+    cvmx_safe_printf("Backtrace:\n\n");
+    __octeon_print_backtrace_func ((__octeon_backtrace_printf_t)cvmx_safe_printf);
+    cvmx_safe_printf("******************************************************************\n");
+#endif
+
+    cvmx_spinlock_unlock(&cvmx_interrupt_default_lock);
+
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+      CVMX_BREAK;
+
+    while (1)
+    {
+	/* Interrupts are suppressed when we are in the exception
+	   handler (because of SR[EXL]).  Spin and poll the uart
+	   status and see if the debugger is trying to stop us. */
+	cvmx_uart_lsr_t lsrval;
+	lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
+	if (lsrval.s.dr)
+	{
+	    uint64_t tmp;
+	    /* Pulse the MCD0 signal. */
+	    asm volatile (
+		".set push\n"
+		".set noreorder\n"
+		".set mips64\n"
+		"dmfc0 %0, $22\n"
+		"ori   %0, %0, 0x10\n"
+		"dmtc0 %0, $22\n"
+		".set pop\n"
+		: "=r" (tmp));
+	}
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Default interrupt handler if the user doesn't register one.
+ *
+ * @param irq_number IRQ that caused this interrupt
+ * @param registers  Register at the time of the interrupt
+ * @param user_arg   Unused optional user data
+ */
+static void __cvmx_interrupt_default(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    cvmx_safe_printf("cvmx_interrupt_default: Received interrupt %d\n", irq_number);
+    __cvmx_interrupt_dump_registers(registers);
+}
+
+
+/**
+ * @INTERNAL
+ * Handler for interrupt lines 2 and 3. These are directly tied
+ * to the CIU. The handler queres the status of the CIU and
+ * calls the secondary handler for the CIU interrupt that
+ * occurred.
+ *
+ * @param irq_number Interrupt number that fired (2 or 3)
+ * @param registers  Registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+static void __cvmx_interrupt_ciu(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    int ciu_offset = cvmx_get_core_num() * 2 + irq_number - 2;
+    uint64_t irq_mask = cvmx_read_csr(CVMX_CIU_INTX_SUM0(ciu_offset)) & cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
+    int irq = 8;
+
+    /* Handle EN0 sources */
+    while (irq_mask)
+    {
+        if (irq_mask&1)
+        {
+            cvmx_interrupt_state.handlers[irq](irq, registers, cvmx_interrupt_state.data[irq]);
+            return;
+        }
+        irq_mask = irq_mask >> 1;
+        irq++;
+    }
+
+    /* Handle EN1 sources */
+    irq_mask = cvmx_read_csr(CVMX_CIU_INT_SUM1) & cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
+    irq = 8 + 64;
+    while (irq_mask)
+    {
+        if (irq_mask&1)
+        {
+            cvmx_interrupt_state.handlers[irq](irq, registers, cvmx_interrupt_state.data[irq]);
+            return;
+        }
+        irq_mask = irq_mask >> 1;
+        irq++;
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Called for all RML interrupts. This is usually an ECC error
+ *
+ * @param irq_number Interrupt number that we're being called for
+ * @param registers  Registers at the time of the interrupt
+ * @param user_arg   Unused user argument
+ */
+static void __cvmx_interrupt_ecc(int irq_number, uint64_t registers[32], void *user_arg)
+{
+    cvmx_interrupt_rsl_decode();
+}
+
+
+/**
+ * Process an interrupt request
+ *
+ * @param registers Registers at time of interrupt / exception
+ * Registers 0-31 are standard MIPS, others specific to this routine
+ * @return
+ */
+EXTERN_ASM void cvmx_interrupt_do_irq(uint64_t registers[35]);
+void cvmx_interrupt_do_irq(uint64_t registers[35])
+{
+    uint64_t        mask;
+    uint64_t        cause;
+    uint64_t        status;
+    uint64_t        cache_err;
+    int             i;
+    uint32_t exc_vec;
+
+    /* Determine the cause of the interrupt */
+    asm volatile ("dmfc0 %0,$13,0" : "=r" (cause));
+    asm volatile ("dmfc0 %0,$12,0" : "=r" (status));
+
+    /* The assembly stub at each exception vector saves its address in k1 when
+    ** it calls the stage 2 handler.  We use this to compute the exception vector
+    ** that brought us here */
+    exc_vec = (uint32_t)(registers[27] & 0x780);  /* Mask off bits we need to ignore */
+
+    /* Check for cache errors.  The cache errors go to a separate exception vector,
+    ** so we will only check these if we got here from a cache error exception, and
+    ** the ERL (error level) bit is set. */
+    if (exc_vec == 0x100 && (status & 0x4))
+    {
+        i = cvmx_get_core_num();
+        CVMX_MF_CACHE_ERR(cache_err);
+
+        /* Use copy of DCACHE_ERR register that early exception stub read */
+        if (registers[34] & 0x1)
+        {
+            cvmx_safe_printf("Dcache error detected: core: %d, set: %d, va 6:3: 0x%x\n", i, (int)(cache_err >> 3) & 0x3, (int)(cache_err >> 3) & 0xf);
+            uint64_t dcache_err = 0;
+            CVMX_MT_DCACHE_ERR(dcache_err);
+        }
+        else if (cache_err & 0x1)
+        {
+            cvmx_safe_printf("Icache error detected: core: %d, set: %d, way : %d\n", i, (int)(cache_err >> 5) & 0x3f, (int)(cache_err >> 7) & 0x3);
+            cache_err = 0;
+            CVMX_MT_CACHE_ERR(cache_err);
+        }
+        else
+            cvmx_safe_printf("Cache error exception: core %d\n", i);
+    }
+
+    if ((cause & 0x7c) != 0)
+    {
+        cvmx_interrupt_state.exception_handler(registers);
+        return;
+    }
+
+    /* Convert the cause into an active mask */
+    mask = ((cause & status) >> 8) & 0xff;
+    if (mask == 0)
+        return; /* Spurious interrupt */
+
+    for (i=0; i<8; i++)
+    {
+        if (mask & (1<<i))
+        {
+            cvmx_interrupt_state.handlers[i](i, registers, cvmx_interrupt_state.data[i]);
+            return;
+        }
+    }
+
+    /* We should never get here */
+    __cvmx_interrupt_default_exception_handler(registers);
+}
+
+
+/**
+ * Initialize the interrupt routine and copy the low level
+ * stub into the correct interrupt vector. This is called
+ * automatically during application startup.
+ */
+void cvmx_interrupt_initialize(void)
+{
+    void *low_level_loc;
+    cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
+    int i;
+
+    /* Disable all CIU interrupts by default */
+    cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
+    cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
+    cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
+    cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
+
+    if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
+    {
+        cvmx_interrupt_state.exception_handler = __cvmx_interrupt_default_exception_handler;
+
+        for (i=0; i<256; i++)
+        {
+            cvmx_interrupt_state.handlers[i] = __cvmx_interrupt_default;
+            cvmx_interrupt_state.data[i] = NULL;
+        }
+
+        low_level_loc = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,sys_info_ptr->exception_base_addr));
+        memcpy(low_level_loc + 0x80, (void*)cvmx_interrupt_stage1, 0x80);
+        memcpy(low_level_loc + 0x100, (void*)cvmx_interrupt_cache_error, 0x80);
+        memcpy(low_level_loc + 0x180, (void*)cvmx_interrupt_stage1, 0x80);
+        memcpy(low_level_loc + 0x200, (void*)cvmx_interrupt_stage1, 0x80);
+        /* Make sure the locations used to count Icache and Dcache exceptions
+            starts out as zero */
+        cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 8), 0);
+        cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 16), 0);
+        cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 24), 0);
+        CVMX_SYNC;
+
+        /* Add an interrupt handlers for chained CIU interrupts */
+        cvmx_interrupt_register(CVMX_IRQ_CIU0, __cvmx_interrupt_ciu, NULL);
+        cvmx_interrupt_register(CVMX_IRQ_CIU1, __cvmx_interrupt_ciu, NULL);
+
+        /* Add an interrupt handler for ECC failures */
+        cvmx_interrupt_register(CVMX_IRQ_RML, __cvmx_interrupt_ecc, NULL);
+
+        cvmx_interrupt_rsl_enable();
+        cvmx_interrupt_unmask_irq(CVMX_IRQ_RML);
+    }
+
+    cvmx_interrupt_unmask_irq(CVMX_IRQ_CIU0);
+    cvmx_interrupt_unmask_irq(CVMX_IRQ_CIU1);
+    CVMX_ICACHE_INVALIDATE;
+
+    /* Enable interrupts for each core (bit0 of COP0 Status) */
+    uint32_t mask;
+    asm volatile (
+        "mfc0   %0,$12,0\n"
+        "ori    %0, %0, 1\n"
+        "mtc0   %0,$12,0\n"
+        : "=r" (mask));
+}
+
+
+/**
+ * Register an interrupt handler for the specified interrupt number.
+ *
+ * @param irq_number Interrupt number to register for (0-135)  See
+ *                   cvmx-interrupt.h for enumeration and description of sources.
+ * @param func       Function to call on interrupt.
+ * @param user_arg   User data to pass to the interrupt handler
+ */
+void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg)
+{
+    cvmx_interrupt_state.handlers[irq_number] = func;
+    cvmx_interrupt_state.data[irq_number] = user_arg;
+    CVMX_SYNCWS;
+}
+
+
+/**
+ * Set the exception handler for all non interrupt sources.
+ *
+ * @param handler New exception handler
+ * @return Old exception handler
+ */
+cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler)
+{
+    cvmx_interrupt_exception_t result = cvmx_interrupt_state.exception_handler;
+    cvmx_interrupt_state.exception_handler = handler;
+    CVMX_SYNCWS;
+    return result;
+}
+
+
+/**
+ * version of printf that works better in exception context.
+ *
+ * @param format
+ */
+void cvmx_safe_printf(const char *format, ...)
+{
+    static char buffer[256];
+    va_list args;
+    va_start(args, format);
+    int count = vsnprintf(buffer, sizeof(buffer), format, args);
+    va_end(args);
+
+    char *ptr = buffer;
+    while (count-- > 0)
+    {
+        cvmx_uart_lsr_t lsrval;
+
+        /* Spin until there is room */
+        do
+        {
+            lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
+            if (lsrval.s.temt == 0)
+                cvmx_wait(10000);   /* Just to reduce the load on the system */
+        }
+        while (lsrval.s.temt == 0);
+
+        if (*ptr == '\n')
+            cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
+        cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
+    }
+}
+
+
+
+
+
+
diff --git a/cvmx-interrupt.h b/cvmx-interrupt.h
new file mode 100644
index 0000000000000..0683d6ebb2681
--- /dev/null
+++ b/cvmx-interrupt.h
@@ -0,0 +1,306 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the Mips interrupts.
+ *
+ * <hr>$Revision: 42203 $<hr>
+ */
+#ifndef __CVMX_INTERRUPT_H__
+#define __CVMX_INTERRUPT_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of Interrupt numbers
+ */
+typedef enum
+{
+    /* 0 - 7 represent the 8 MIPS standard interrupt sources */
+    CVMX_IRQ_SW0        = 0,
+    CVMX_IRQ_SW1        = 1,
+    CVMX_IRQ_CIU0       = 2,
+    CVMX_IRQ_CIU1       = 3,
+    CVMX_IRQ_4          = 4,
+    CVMX_IRQ_5          = 5,
+    CVMX_IRQ_6          = 6,
+    CVMX_IRQ_7          = 7,
+
+    /* 8 - 71 represent the sources in CIU_INTX_EN0 */
+    CVMX_IRQ_WORKQ0     = 8,
+    CVMX_IRQ_WORKQ1     = 9,
+    CVMX_IRQ_WORKQ2     = 10,
+    CVMX_IRQ_WORKQ3     = 11,
+    CVMX_IRQ_WORKQ4     = 12,
+    CVMX_IRQ_WORKQ5     = 13,
+    CVMX_IRQ_WORKQ6     = 14,
+    CVMX_IRQ_WORKQ7     = 15,
+    CVMX_IRQ_WORKQ8     = 16,
+    CVMX_IRQ_WORKQ9     = 17,
+    CVMX_IRQ_WORKQ10    = 18,
+    CVMX_IRQ_WORKQ11    = 19,
+    CVMX_IRQ_WORKQ12    = 20,
+    CVMX_IRQ_WORKQ13    = 21,
+    CVMX_IRQ_WORKQ14    = 22,
+    CVMX_IRQ_WORKQ15    = 23,
+    CVMX_IRQ_GPIO0      = 24,
+    CVMX_IRQ_GPIO1      = 25,
+    CVMX_IRQ_GPIO2      = 26,
+    CVMX_IRQ_GPIO3      = 27,
+    CVMX_IRQ_GPIO4      = 28,
+    CVMX_IRQ_GPIO5      = 29,
+    CVMX_IRQ_GPIO6      = 30,
+    CVMX_IRQ_GPIO7      = 31,
+    CVMX_IRQ_GPIO8      = 32,
+    CVMX_IRQ_GPIO9      = 33,
+    CVMX_IRQ_GPIO10     = 34,
+    CVMX_IRQ_GPIO11     = 35,
+    CVMX_IRQ_GPIO12     = 36,
+    CVMX_IRQ_GPIO13     = 37,
+    CVMX_IRQ_GPIO14     = 38,
+    CVMX_IRQ_GPIO15     = 39,
+    CVMX_IRQ_MBOX0      = 40,
+    CVMX_IRQ_MBOX1      = 41,
+    CVMX_IRQ_UART0      = 42,
+    CVMX_IRQ_UART1      = 43,
+    CVMX_IRQ_PCI_INT0   = 44,
+    CVMX_IRQ_PCI_INT1   = 45,
+    CVMX_IRQ_PCI_INT2   = 46,
+    CVMX_IRQ_PCI_INT3   = 47,
+    CVMX_IRQ_PCI_MSI0   = 48,
+    CVMX_IRQ_PCI_MSI1   = 49,
+    CVMX_IRQ_PCI_MSI2   = 50,
+    CVMX_IRQ_PCI_MSI3   = 51,
+    CVMX_IRQ_RESERVED44 = 52,
+    CVMX_IRQ_TWSI       = 53,
+    CVMX_IRQ_RML        = 54,
+    CVMX_IRQ_TRACE      = 55,
+    CVMX_IRQ_GMX_DRP0   = 56,
+    CVMX_IRQ_GMX_DRP1   = 57,
+    CVMX_IRQ_IPD_DRP    = 58,
+    CVMX_IRQ_KEY_ZERO   = 59,
+    CVMX_IRQ_TIMER0     = 60,
+    CVMX_IRQ_TIMER1     = 61,
+    CVMX_IRQ_TIMER2     = 62,
+    CVMX_IRQ_TIMER3     = 63,
+    CVMX_IRQ_USB        = 64,   /* Doesn't apply on CN38XX or CN58XX */
+    CVMX_IRQ_PCM        = 65,
+    CVMX_IRQ_MPI        = 66,
+    CVMX_IRQ_TWSI2      = 67,   /* Added in CN56XX */
+    CVMX_IRQ_POWIQ      = 68,   /* Added in CN56XX */
+    CVMX_IRQ_IPDPPTHR   = 69,   /* Added in CN56XX */
+    CVMX_IRQ_MII        = 70,   /* Added in CN56XX */
+    CVMX_IRQ_BOOTDMA    = 71,   /* Added in CN56XX */
+
+    /* 72 - 135 represent the sources in CIU_INTX_EN1 */
+    CVMX_IRQ_WDOG0 = 72,
+    CVMX_IRQ_WDOG1 = 73,
+    CVMX_IRQ_WDOG2 = 74,
+    CVMX_IRQ_WDOG3 = 75,
+    CVMX_IRQ_WDOG4 = 76,
+    CVMX_IRQ_WDOG5 = 77,
+    CVMX_IRQ_WDOG6 = 78,
+    CVMX_IRQ_WDOG7 = 79,
+    CVMX_IRQ_WDOG8 = 80,
+    CVMX_IRQ_WDOG9 = 81,
+    CVMX_IRQ_WDOG10= 82,
+    CVMX_IRQ_WDOG11= 83,
+    CVMX_IRQ_WDOG12= 84,
+    CVMX_IRQ_WDOG13= 85,
+    CVMX_IRQ_WDOG14= 86,
+    CVMX_IRQ_WDOG15= 87
+    /* numbers 88 - 135 are reserved */
+} cvmx_irq_t;
+
+/**
+ * Function prototype for the exception handler
+ */
+typedef void (*cvmx_interrupt_exception_t)(uint64_t registers[32]);
+
+/**
+ * Function prototype for interrupt handlers
+ */
+typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t registers[32], void *user_arg);
+
+/**
+ * Register an interrupt handler for the specified interrupt number.
+ *
+ * @param irq_number Interrupt number to register for (0-135)
+ * @param func       Function to call on interrupt.
+ * @param user_arg   User data to pass to the interrupt handler
+ */
+void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg);
+
+/**
+ * Set the exception handler for all non interrupt sources.
+ *
+ * @param handler New exception handler
+ * @return Old exception handler
+ */
+cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler);
+
+/**
+ * Masks a given interrupt number.
+ * EN0 sources are masked on IP2
+ * EN1 sources are masked on IP3
+ *
+ * @param irq_number interrupt number to mask (0-135)
+ */
+static inline void cvmx_interrupt_mask_irq(int irq_number)
+{
+    if (irq_number<8)
+    {
+        uint32_t mask;
+        asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
+        mask &= ~(1<< (8 + irq_number));
+        asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
+    }
+    else if (irq_number < 8 + 64)
+    {
+        int ciu_bit = (irq_number - 8) & 63;
+        int ciu_offset = cvmx_get_core_num() * 2;
+        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
+        mask &= ~(1ull << ciu_bit);
+        cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
+    }
+    else
+    {
+        int ciu_bit = (irq_number - 8) & 63;
+        int ciu_offset = cvmx_get_core_num() * 2 + 1;
+        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
+        mask &= ~(1ull << ciu_bit);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
+    }
+}
+
+
+/**
+ * Unmasks a given interrupt number
+ * EN0 sources are unmasked on IP2
+ * EN1 sources are unmasked on IP3
+ *
+ * @param irq_number interrupt number to unmask (0-135)
+ */
+static inline void cvmx_interrupt_unmask_irq(int irq_number)
+{
+    if (irq_number<8)
+    {
+        uint32_t mask;
+        asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
+        mask |= (1<< (8 + irq_number));
+        asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
+    }
+    else if (irq_number < 8 + 64)
+    {
+        int ciu_bit = (irq_number - 8) & 63;
+        int ciu_offset = cvmx_get_core_num() * 2;
+        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
+        mask |= (1ull << ciu_bit);
+        cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
+    }
+    else
+    {
+        int ciu_bit = (irq_number - 8) & 63;
+        int ciu_offset = cvmx_get_core_num() * 2 + 1;
+        uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
+        mask |= (1ull << ciu_bit);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
+    }
+}
+
+
+/* Disable interrupts by clearing bit 0 of the COP0 status register,
+** and return the previous contents of the status register.
+** Note: this is only used to track interrupt status. */
+static inline uint32_t cvmx_interrupt_disable_save(void)
+{
+    uint32_t flags;
+    asm volatile (
+        "DI   %[flags]\n"
+        : [flags]"=r" (flags));
+    return(flags);
+}
+
+/* Restore the contents of the cop0 status register.  Used with
+** cvmx_interrupt_disable_save to allow recursive interrupt disabling */
+static inline void cvmx_interrupt_restore(uint32_t flags)
+{
+    /* If flags value indicates interrupts should be enabled, then enable them */
+    if (flags & 1)
+    {
+        asm volatile (
+            "EI     \n"
+            ::);
+    }
+}
+
+/**
+ * Utility function to decode Octeon's RSL_INT_BLOCKS interrupts
+ * into error messages.
+ */
+extern void cvmx_interrupt_rsl_decode(void);
+
+/**
+ * Utility function to enable all RSL error interupts
+ */
+extern void cvmx_interrupt_rsl_enable(void);
+
+/**
+ * Utility function to do interrupt safe printf 
+ */
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+	#define cvmx_safe_printf printk
+#elif defined(CVMX_BUILD_FOR_LINUX_USER)
+	#define cvmx_safe_printf printf
+#else
+	extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));
+#endif 
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/cvmx-iob.h b/cvmx-iob.h
new file mode 100644
index 0000000000000..7f897117107fd
--- /dev/null
+++ b/cvmx-iob.h
@@ -0,0 +1,66 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file contains defines for the IO bridge
+
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+#ifndef __CVMX_IOB_H__
+#define __CVMX_IOB_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_IOB_H__ */
diff --git a/cvmx-ipd.h b/cvmx-ipd.h
new file mode 100644
index 0000000000000..2c3b177bbd183
--- /dev/null
+++ b/cvmx-ipd.h
@@ -0,0 +1,309 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Input Packet Data unit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+#ifndef __CVMX_IPD_H__
+#define __CVMX_IPD_H__
+
+#ifndef CVMX_DONT_INCLUDE_CONFIG
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include "cvmx-config.h"
+#endif
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef CVMX_ENABLE_LEN_M8_FIX
+#define CVMX_ENABLE_LEN_M8_FIX 0
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
+typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
+
+
+/**
+ * Configure IPD
+ *
+ * @param mbuff_size Packets buffer size in 8 byte words
+ * @param first_mbuff_skip
+ *                   Number of 8 byte words to skip in the first buffer
+ * @param not_first_mbuff_skip
+ *                   Number of 8 byte words to skip in each following buffer
+ * @param first_back Must be same as first_mbuff_skip / 128
+ * @param second_back
+ *                   Must be same as not_first_mbuff_skip / 128
+ * @param wqe_fpa_pool
+ *                   FPA pool to get work entries from
+ * @param cache_mode
+ * @param back_pres_enable_flag
+ *                   Enable or disable port back pressure
+ */
+static inline void cvmx_ipd_config(uint64_t mbuff_size,
+                                   uint64_t first_mbuff_skip,
+                                   uint64_t not_first_mbuff_skip,
+                                   uint64_t first_back,
+                                   uint64_t second_back,
+                                   uint64_t wqe_fpa_pool,
+                                   cvmx_ipd_mode_t cache_mode,
+                                   uint64_t back_pres_enable_flag
+                                  )
+{
+    cvmx_ipd_mbuff_first_skip_t first_skip;
+    cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
+    cvmx_ipd_mbuff_size_t size;
+    cvmx_ipd_first_next_ptr_back_t first_back_struct;
+    cvmx_ipd_second_next_ptr_back_t second_back_struct;
+    cvmx_ipd_wqe_fpa_pool_t wqe_pool;
+    cvmx_ipd_ctl_status_t ipd_ctl_reg;
+
+    first_skip.u64 = 0;
+    first_skip.s.skip_sz = first_mbuff_skip;
+    cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
+
+    not_first_skip.u64 = 0;
+    not_first_skip.s.skip_sz = not_first_mbuff_skip;
+    cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
+
+    size.u64 = 0;
+    size.s.mb_size = mbuff_size;
+    cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
+
+    first_back_struct.u64 = 0;
+    first_back_struct.s.back = first_back;
+    cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
+
+    second_back_struct.u64 = 0;
+    second_back_struct.s.back = second_back;
+    cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64);
+
+    wqe_pool.u64 = 0;
+    wqe_pool.s.wqe_pool = wqe_fpa_pool;
+    cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
+
+    ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+    ipd_ctl_reg.s.opc_mode = cache_mode;
+    ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
+    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
+
+    /* Note: the example RED code that used to be here has been moved to
+        cvmx_helper_setup_red */
+}
+
+
+/**
+ * Enable IPD
+ */
+static inline void cvmx_ipd_enable(void)
+{
+    cvmx_ipd_ctl_status_t ipd_reg;
+    ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+    if (ipd_reg.s.ipd_en)
+    {
+        cvmx_dprintf("Warning: Enabling IPD when IPD already enabled.\n");
+    }
+    ipd_reg.s.ipd_en = TRUE;
+    #if  CVMX_ENABLE_LEN_M8_FIX
+    if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+        ipd_reg.s.len_m8 = TRUE;
+    }
+    #endif
+    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+}
+
+
+/**
+ * Disable IPD
+ */
+static inline void cvmx_ipd_disable(void)
+{
+    cvmx_ipd_ctl_status_t ipd_reg;
+    ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+    ipd_reg.s.ipd_en = FALSE;
+    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+}
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/**
+ * Supportive function for cvmx_fpa_shutdown_pool.
+ */
+static inline void cvmx_ipd_free_ptr(void)
+{
+    /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
+    if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+	int no_wptr = 0;
+	cvmx_ipd_ptr_count_t ipd_ptr_count;
+	ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+
+	/* Handle Work Queue Entry in cn56xx and cn52xx */
+	if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
+	    cvmx_ipd_ctl_status_t ipd_ctl_status;
+	    ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+	    if (ipd_ctl_status.s.no_wptr) 
+		no_wptr = 1;
+	}
+
+	/* Free the prefetched WQE */
+	if (ipd_ptr_count.s.wqev_cnt) {
+	    cvmx_ipd_wqe_ptr_valid_t ipd_wqe_ptr_valid;
+	    ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
+	    if (no_wptr)
+	        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    else
+	        cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
+	}
+
+	/* Free all WQE in the fifo */
+	if (ipd_ptr_count.s.wqe_pcnt) {
+	    int i;
+	    cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
+	    ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+	    for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
+		ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+		ipd_pwp_ptr_fifo_ctl.s.raddr = ipd_pwp_ptr_fifo_ctl.s.max_cnts + (ipd_pwp_ptr_fifo_ctl.s.wraddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+		cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+		ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+		if (no_wptr)
+		    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+		else
+		    cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
+	    }
+	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+	}
+
+	/* Free the prefetched packet */
+	if (ipd_ptr_count.s.pktv_cnt) {
+	    cvmx_ipd_pkt_ptr_valid_t ipd_pkt_ptr_valid;
+	    ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
+	    cvmx_fpa_free(cvmx_phys_to_ptr(ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	}
+
+	/* Free the per port prefetched packets */
+	if (1) {
+	    int i;
+	    cvmx_ipd_prc_port_ptr_fifo_ctl_t ipd_prc_port_ptr_fifo_ctl;
+	    ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+
+	    for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; i++) {
+		ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
+		ipd_prc_port_ptr_fifo_ctl.s.raddr = i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
+		cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
+		ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_port_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    }
+	    ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
+	}
+
+	/* Free all packets in the holding fifo */
+	if (ipd_ptr_count.s.pfif_cnt) {
+	    int i;
+	    cvmx_ipd_prc_hold_ptr_fifo_ctl_t ipd_prc_hold_ptr_fifo_ctl;
+
+	    ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+
+	    for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
+		ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
+		ipd_prc_hold_ptr_fifo_ctl.s.raddr = (ipd_prc_hold_ptr_fifo_ctl.s.praddr + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
+		cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
+		ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_hold_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    }
+	    ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
+	}
+
+	/* Free all packets in the fifo */
+	if (ipd_ptr_count.s.pkt_pcnt) {
+	    int i;
+	    cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
+	    ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+
+	    for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
+		ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+		ipd_pwp_ptr_fifo_ctl.s.raddr = (ipd_pwp_ptr_fifo_ctl.s.praddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+		cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+		ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+		cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
+	    }
+	    ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+	    cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
+	}
+
+	/* Reset the IPD to get all buffers out of it */
+	{
+	    cvmx_ipd_ctl_status_t ipd_ctl_status;
+	    ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+	    ipd_ctl_status.s.reset = 1;
+	    cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
+	}
+
+	/* Reset the PIP */
+	{
+	    cvmx_pip_sft_rst_t pip_sft_rst;
+	    pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
+	    pip_sft_rst.s.rst = 1;
+	    cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
+	}
+    }
+}
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /*  __CVMX_IPD_H__ */
diff --git a/cvmx-key.h b/cvmx-key.h
new file mode 100644
index 0000000000000..791006e53d8e0
--- /dev/null
+++ b/cvmx-key.h
@@ -0,0 +1,113 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the on chip key memory. Key memory is
+ * 8k on chip that is inaccessible from off chip. It can
+ * also be cleared using an external hardware pin.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_KEY_H__
+#define __CVMX_KEY_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_KEY_MEM_SIZE 8192  /* Size in bytes */
+
+
+/**
+ * Read from KEY memory
+ *
+ * @param address Address (byte) in key memory to read
+ *                0 <= address < CVMX_KEY_MEM_SIZE
+ * @return Value from key memory
+ */
+static inline uint64_t cvmx_key_read(uint64_t address)
+{
+    cvmx_addr_t ptr;
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region  = CVMX_IO_SEG;
+    ptr.sio.is_io       = 1;
+    ptr.sio.did         = CVMX_OCT_DID_KEY_RW;
+    ptr.sio.offset      = address;
+
+    return cvmx_read_csr(ptr.u64);
+}
+
+
+/**
+ * Write to KEY memory
+ *
+ * @param address Address (byte) in key memory to write
+ *                0 <= address < CVMX_KEY_MEM_SIZE
+ * @param value   Value to write to key memory
+ */
+static inline void cvmx_key_write(uint64_t address, uint64_t value)
+{
+    cvmx_addr_t ptr;
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region  = CVMX_IO_SEG;
+    ptr.sio.is_io       = 1;
+    ptr.sio.did         = CVMX_OCT_DID_KEY_RW;
+    ptr.sio.offset      = address;
+
+    cvmx_write_io(ptr.u64, value);
+}
+
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /*  __CVMX_KEY_H__ */
diff --git a/cvmx-l2c.c b/cvmx-l2c.c
new file mode 100644
index 0000000000000..c1a3320487684
--- /dev/null
+++ b/cvmx-l2c.c
@@ -0,0 +1,747 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Implementation of the Level 2 Cache (L2C) control,
+ * measurement, and debugging facilities.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-l2c.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-interrupt.h"
+
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/* This spinlock is used internally to ensure that only one core is performing
+** certain L2 operations at a time.
+**
+** NOTE: This only protects calls from within a single application - if multiple applications
+** or operating systems are running, then it is up to the user program to coordinate between them.
+*/
+CVMX_SHARED cvmx_spinlock_t cvmx_l2c_spinlock;
+#endif
+
+static inline int l2_size_half(void)
+{
+    uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
+    return !!(val & (1ull << 34));
+}
+int cvmx_l2c_get_core_way_partition(uint32_t core)
+{
+    uint32_t    field;
+
+    /* Validate the core number */
+    if (core >= cvmx_octeon_num_cores())
+        return -1;
+
+    /* Use the lower two bits of the coreNumber to determine the bit offset
+     * of the UMSK[] field in the L2C_SPAR register.
+     */
+    field = (core & 0x3) * 8;
+
+    /* Return the UMSK[] field from the appropriate L2C_SPAR register based
+     * on the coreNumber.
+     */
+
+    switch (core & 0xC)
+    {
+        case 0x0:
+            return((cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field);
+        case 0x4:
+            return((cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field);
+        case 0x8:
+            return((cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field);
+        case 0xC:
+            return((cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field);
+    }
+    return(0);
+}
+
+int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
+{
+    uint32_t    field;
+    uint32_t    valid_mask;
+
+    valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
+
+    mask &= valid_mask;
+
+    /* A UMSK setting which blocks all L2C Ways is an error. */
+    if (mask == valid_mask)
+        return -1;
+
+    /* Validate the core number */
+    if (core >= cvmx_octeon_num_cores())
+        return -1;
+
+    /* Check to make sure current mask & new mask don't block all ways */
+    if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) == valid_mask)
+        return -1;
+
+
+    /* Use the lower two bits of core to determine the bit offset of the
+     * UMSK[] field in the L2C_SPAR register.
+     */
+    field = (core & 0x3) * 8;
+
+    /* Assign the new mask setting to the UMSK[] field in the appropriate
+     * L2C_SPAR register based on the core_num.
+     *
+     */
+    switch (core & 0xC)
+    {
+        case 0x0:
+            cvmx_write_csr(CVMX_L2C_SPAR0,
+                           (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
+                           mask << field);
+            break;
+        case 0x4:
+            cvmx_write_csr(CVMX_L2C_SPAR1,
+                           (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
+                           mask << field);
+            break;
+        case 0x8:
+            cvmx_write_csr(CVMX_L2C_SPAR2,
+                           (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
+                           mask << field);
+            break;
+        case 0xC:
+            cvmx_write_csr(CVMX_L2C_SPAR3,
+                           (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
+                           mask << field);
+            break;
+    }
+    return 0;
+}
+
+
+int cvmx_l2c_set_hw_way_partition(uint32_t mask)
+{
+    uint32_t valid_mask;
+
+    valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
+    mask &= valid_mask;
+
+    /* A UMSK setting which blocks all L2C Ways is an error. */
+    if (mask == valid_mask)
+        return -1;
+    /* Check to make sure current mask & new mask don't block all ways */
+    if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) == valid_mask)
+        return -1;
+
+    cvmx_write_csr(CVMX_L2C_SPAR4, (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+    return 0;
+}
+
+int cvmx_l2c_get_hw_way_partition(void)
+{
+    return(cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF));
+}
+
+
+void cvmx_l2c_config_perf(uint32_t counter, cvmx_l2c_event_t event,
+                          uint32_t clear_on_read)
+{   cvmx_l2c_pfctl_t pfctl;
+
+    pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+
+    switch (counter)
+    {
+        case 0:
+            pfctl.s.cnt0sel = event;
+            pfctl.s.cnt0ena = 1;
+            if (!cvmx_octeon_is_pass1())
+                pfctl.s.cnt0rdclr = clear_on_read;
+            break;
+        case 1:
+            pfctl.s.cnt1sel = event;
+            pfctl.s.cnt1ena = 1;
+            if (!cvmx_octeon_is_pass1())
+                pfctl.s.cnt1rdclr = clear_on_read;
+            break;
+        case 2:
+            pfctl.s.cnt2sel = event;
+            pfctl.s.cnt2ena = 1;
+            if (!cvmx_octeon_is_pass1())
+                pfctl.s.cnt2rdclr = clear_on_read;
+            break;
+        case 3:
+        default:
+            pfctl.s.cnt3sel = event;
+            pfctl.s.cnt3ena = 1;
+            if (!cvmx_octeon_is_pass1())
+                pfctl.s.cnt3rdclr = clear_on_read;
+            break;
+    }
+
+    cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+}
+
+uint64_t cvmx_l2c_read_perf(uint32_t counter)
+{
+    switch (counter)
+    {
+        case 0:
+            return(cvmx_read_csr(CVMX_L2C_PFC0));
+        case 1:
+            return(cvmx_read_csr(CVMX_L2C_PFC1));
+        case 2:
+            return(cvmx_read_csr(CVMX_L2C_PFC2));
+        case 3:
+        default:
+            return(cvmx_read_csr(CVMX_L2C_PFC3));
+    }
+}
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * @INTERNAL
+ * Helper function use to fault in cache lines for L2 cache locking
+ *
+ * @param addr   Address of base of memory region to read into L2 cache
+ * @param len    Length (in bytes) of region to fault in
+ */
+static void fault_in(uint64_t addr, int len)
+{
+    volatile char *ptr;
+    volatile char dummy;
+    /* Adjust addr and length so we get all cache lines even for
+    ** small ranges spanning two cache lines */
+    len += addr & CVMX_CACHE_LINE_MASK;
+    addr &= ~CVMX_CACHE_LINE_MASK;
+    ptr = (volatile char *)cvmx_phys_to_ptr(addr);
+    CVMX_DCACHE_INVALIDATE;  /* Invalidate L1 cache to make sure all loads result in data being in L2 */
+    while (len > 0)
+    {
+        dummy += *ptr;
+        len -= CVMX_CACHE_LINE_SIZE;
+        ptr += CVMX_CACHE_LINE_SIZE;
+    }
+}
+
+int cvmx_l2c_lock_line(uint64_t addr)
+{
+    int retval = 0;
+    cvmx_l2c_dbg_t l2cdbg;
+    cvmx_l2c_lckbase_t lckbase;
+    cvmx_l2c_lckoff_t lckoff;
+    cvmx_l2t_err_t l2t_err;
+    l2cdbg.u64 = 0;
+    lckbase.u64 = 0;
+    lckoff.u64 = 0;
+
+    cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+
+    /* Clear l2t error bits if set */
+    l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+    l2t_err.s.lckerr = 1;
+    l2t_err.s.lckerr2 = 1;
+    cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+
+    addr &= ~CVMX_CACHE_LINE_MASK;
+
+    /* Set this core as debug core */
+    l2cdbg.s.ppnum = cvmx_get_core_num();
+    CVMX_SYNC;
+    cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+    cvmx_read_csr(CVMX_L2C_DBG);
+
+    lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+    cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+    cvmx_read_csr(CVMX_L2C_LCKOFF);
+
+    if (((cvmx_l2c_cfg_t)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias)
+    {
+        int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+        uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+        lckbase.s.lck_base = addr_tmp >> 7;
+    }
+    else
+    {
+        lckbase.s.lck_base = addr >> 7;
+    }
+
+    lckbase.s.lck_ena = 1;
+    cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+    cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+
+    fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+    lckbase.s.lck_ena = 0;
+    cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+    cvmx_read_csr(CVMX_L2C_LCKBASE);    // Make sure it gets there
+
+    /* Stop being debug core */
+    cvmx_write_csr(CVMX_L2C_DBG, 0);
+    cvmx_read_csr(CVMX_L2C_DBG);
+
+    l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+    if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+        retval = 1;  /* We were unable to lock the line */
+
+    cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+
+    return(retval);
+}
+
+
+int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
+{
+    int retval = 0;
+
+    /* Round start/end to cache line boundaries */
+    len += start & CVMX_CACHE_LINE_MASK;
+    start &= ~CVMX_CACHE_LINE_MASK;
+    len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
+
+    while (len)
+    {
+        retval += cvmx_l2c_lock_line(start);
+        start += CVMX_CACHE_LINE_SIZE;
+        len -= CVMX_CACHE_LINE_SIZE;
+    }
+
+    return(retval);
+}
+
+
+void cvmx_l2c_flush(void)
+{
+    uint64_t assoc, set;
+    uint64_t n_assoc, n_set;
+    cvmx_l2c_dbg_t l2cdbg;
+
+    cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+
+    l2cdbg.u64 = 0;
+    if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+        l2cdbg.s.ppnum = cvmx_get_core_num();
+    l2cdbg.s.finv = 1;
+    n_set = CVMX_L2_SETS;
+    n_assoc = l2_size_half() ? (CVMX_L2_ASSOC/2) : CVMX_L2_ASSOC ;
+    for(set=0; set < n_set; set++)
+    {
+        for(assoc = 0; assoc < n_assoc; assoc++)
+        {
+            l2cdbg.s.set = assoc;
+            /* Enter debug mode, and make sure all other writes complete before we
+            ** enter debug mode */
+            CVMX_SYNCW;
+            cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+            cvmx_read_csr(CVMX_L2C_DBG);
+
+            CVMX_PREPARE_FOR_STORE (CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, set*CVMX_CACHE_LINE_SIZE), 0);
+            CVMX_SYNCW; /* Push STF out to L2 */
+            /* Exit debug mode */
+            CVMX_SYNC;
+            cvmx_write_csr(CVMX_L2C_DBG, 0);
+            cvmx_read_csr(CVMX_L2C_DBG);
+        }
+    }
+
+    cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+}
+
+
+int cvmx_l2c_unlock_line(uint64_t address)
+{
+    int assoc;
+    cvmx_l2c_tag_t tag;
+    cvmx_l2c_dbg_t l2cdbg;
+    uint32_t tag_addr;
+
+    uint32_t index = cvmx_l2c_address_to_index(address);
+
+    cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+    /* Compute portion of address that is stored in tag */
+    tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+    for(assoc = 0; assoc < CVMX_L2_ASSOC; assoc++)
+    {
+        tag = cvmx_get_l2c_tag(assoc, index);
+
+        if (tag.s.V && (tag.s.addr == tag_addr))
+        {
+            l2cdbg.u64 = 0;
+            l2cdbg.s.ppnum = cvmx_get_core_num();
+            l2cdbg.s.set = assoc;
+            l2cdbg.s.finv = 1;
+
+            CVMX_SYNC;
+            cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); /* Enter debug mode */
+            cvmx_read_csr(CVMX_L2C_DBG);
+
+            CVMX_PREPARE_FOR_STORE (CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
+            CVMX_SYNC;
+            /* Exit debug mode */
+            cvmx_write_csr(CVMX_L2C_DBG, 0);
+            cvmx_read_csr(CVMX_L2C_DBG);
+            cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+            return tag.s.L;
+        }
+    }
+    cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+    return 0;
+}
+
+int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
+{
+    int num_unlocked = 0;
+    /* Round start/end to cache line boundaries */
+    len += start & CVMX_CACHE_LINE_MASK;
+    start &= ~CVMX_CACHE_LINE_MASK;
+    len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
+    while (len > 0)
+    {
+        num_unlocked += cvmx_l2c_unlock_line(start);
+        start += CVMX_CACHE_LINE_SIZE;
+        len -= CVMX_CACHE_LINE_SIZE;
+    }
+
+    return num_unlocked;
+}
+
+
+/* Internal l2c tag types.  These are converted to a generic structure
+** that can be used on all chips */
+typedef union
+{
+    uint64_t u64;
+#if __BYTE_ORDER == __BIG_ENDIAN
+    struct cvmx_l2c_tag_cn50xx
+    {
+	uint64_t reserved		: 40;
+	uint64_t V			: 1;	// Line valid
+	uint64_t D			: 1;	// Line dirty
+	uint64_t L			: 1;	// Line locked
+	uint64_t U			: 1;	// Use, LRU eviction
+	uint64_t addr			: 20;	// Phys mem addr (33..14)
+    } cn50xx;
+    struct cvmx_l2c_tag_cn30xx
+    {
+	uint64_t reserved		: 41;
+	uint64_t V			: 1;	// Line valid
+	uint64_t D			: 1;	// Line dirty
+	uint64_t L			: 1;	// Line locked
+	uint64_t U			: 1;	// Use, LRU eviction
+	uint64_t addr			: 19;	// Phys mem addr (33..15)
+    } cn30xx;
+    struct cvmx_l2c_tag_cn31xx
+    {
+	uint64_t reserved		: 42;
+	uint64_t V			: 1;	// Line valid
+	uint64_t D			: 1;	// Line dirty
+	uint64_t L			: 1;	// Line locked
+	uint64_t U			: 1;	// Use, LRU eviction
+	uint64_t addr			: 18;	// Phys mem addr (33..16)
+    } cn31xx;
+    struct cvmx_l2c_tag_cn38xx
+    {
+	uint64_t reserved		: 43;
+	uint64_t V			: 1;	// Line valid
+	uint64_t D			: 1;	// Line dirty
+	uint64_t L			: 1;	// Line locked
+	uint64_t U			: 1;	// Use, LRU eviction
+	uint64_t addr			: 17;	// Phys mem addr (33..17)
+    } cn38xx;
+    struct cvmx_l2c_tag_cn58xx
+    {
+	uint64_t reserved		: 44;
+	uint64_t V			: 1;	// Line valid
+	uint64_t D			: 1;	// Line dirty
+	uint64_t L			: 1;	// Line locked
+	uint64_t U			: 1;	// Use, LRU eviction
+	uint64_t addr			: 16;	// Phys mem addr (33..18)
+    } cn58xx;
+    struct cvmx_l2c_tag_cn58xx   cn56xx; /* 2048 sets */
+    struct cvmx_l2c_tag_cn31xx   cn52xx; /* 512 sets */
+#endif
+} __cvmx_l2c_tag_t;
+
+
+/**
+ * @INTERNAL
+ * Function to read a L2C tag.  This code make the current core
+ * the 'debug core' for the L2.  This code must only be executed by
+ * 1 core at a time.
+ *
+ * @param assoc  Association (way) of the tag to dump
+ * @param index  Index of the cacheline
+ *
+ * @return The Octeon model specific tag structure.  This is translated by a wrapper
+ *         function to a generic form that is easier for applications to use.
+ */
+static __cvmx_l2c_tag_t __read_l2_tag(uint64_t assoc, uint64_t index)
+{
+
+    uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+    uint64_t core = cvmx_get_core_num();
+    __cvmx_l2c_tag_t tag_val;
+    uint64_t dbg_addr = CVMX_L2C_DBG;
+    uint32_t flags;
+
+    cvmx_l2c_dbg_t debug_val;
+    debug_val.u64 = 0;
+    /* For low core count parts, the core number is always small enough
+    ** to stay in the correct field and not set any reserved bits */
+    debug_val.s.ppnum = core;
+    debug_val.s.l2t = 1;
+    debug_val.s.set = assoc;
+
+    CVMX_SYNC;  /* Make sure core is quiet (no prefetches, etc.) before entering debug mode */
+    CVMX_DCACHE_INVALIDATE;  /* Flush L1 to make sure debug load misses L1 */
+
+    flags = cvmx_interrupt_disable_save();
+
+    /* The following must be done in assembly as when in debug mode all data loads from
+    ** L2 return special debug data, not normal memory contents.  Also, interrupts must be disabled,
+    ** since if an interrupt occurs while in debug mode the ISR will get debug data from all its memory
+    ** reads instead of the contents of memory */
+
+        asm volatile (
+    "        .set push              \n"
+    "        .set mips64              \n"
+    "        .set noreorder           \n"
+    "        sd    %[dbg_val], 0(%[dbg_addr])  \n"   /* Enter debug mode, wait for store */
+    "        ld    $0, 0(%[dbg_addr]) \n"
+    "        ld    %[tag_val], 0(%[tag_addr]) \n"   /* Read L2C tag data */
+    "        sd    $0, 0(%[dbg_addr])  \n"          /* Exit debug mode, wait for store */
+    "        ld    $0, 0(%[dbg_addr]) \n"
+    "        cache 9, 0($0) \n"             /* Invalidate dcache to discard debug data */
+    "        .set pop             \n"
+    :[tag_val] "=r" (tag_val):  [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr) : "memory");
+
+    cvmx_interrupt_restore(flags);
+
+    return(tag_val);
+
+}
+
+
+cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index)
+{
+    __cvmx_l2c_tag_t tmp_tag;
+    cvmx_l2c_tag_t tag;
+    tag.u64 = 0;
+
+    if ((int)association >= cvmx_l2c_get_num_assoc())
+    {
+        cvmx_dprintf("ERROR: cvmx_get_l2c_tag association out of range\n");
+        return(tag);
+    }
+    if ((int)index >= cvmx_l2c_get_num_sets())
+    {
+        cvmx_dprintf("ERROR: cvmx_get_l2c_tag index out of range (arg: %d, max: %d)\n", (int)index, cvmx_l2c_get_num_sets());
+        return(tag);
+    }
+    /* __read_l2_tag is intended for internal use only */
+    tmp_tag = __read_l2_tag(association, index);
+
+    /* Convert all tag structure types to generic version, as it can represent all models */
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))
+    {
+        tag.s.V    = tmp_tag.cn58xx.V;
+        tag.s.D    = tmp_tag.cn58xx.D;
+        tag.s.L    = tmp_tag.cn58xx.L;
+        tag.s.U    = tmp_tag.cn58xx.U;
+        tag.s.addr = tmp_tag.cn58xx.addr;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+    {
+        tag.s.V    = tmp_tag.cn38xx.V;
+        tag.s.D    = tmp_tag.cn38xx.D;
+        tag.s.L    = tmp_tag.cn38xx.L;
+        tag.s.U    = tmp_tag.cn38xx.U;
+        tag.s.addr = tmp_tag.cn38xx.addr;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        tag.s.V    = tmp_tag.cn31xx.V;
+        tag.s.D    = tmp_tag.cn31xx.D;
+        tag.s.L    = tmp_tag.cn31xx.L;
+        tag.s.U    = tmp_tag.cn31xx.U;
+        tag.s.addr = tmp_tag.cn31xx.addr;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+    {
+        tag.s.V    = tmp_tag.cn30xx.V;
+        tag.s.D    = tmp_tag.cn30xx.D;
+        tag.s.L    = tmp_tag.cn30xx.L;
+        tag.s.U    = tmp_tag.cn30xx.U;
+        tag.s.addr = tmp_tag.cn30xx.addr;
+    }
+    else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+    {
+        tag.s.V    = tmp_tag.cn50xx.V;
+        tag.s.D    = tmp_tag.cn50xx.D;
+        tag.s.L    = tmp_tag.cn50xx.L;
+        tag.s.U    = tmp_tag.cn50xx.U;
+        tag.s.addr = tmp_tag.cn50xx.addr;
+    }
+    else
+    {
+        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+    }
+
+    return tag;
+}
+
+#endif
+
+uint32_t cvmx_l2c_address_to_index (uint64_t addr)
+{
+    uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
+    cvmx_l2c_cfg_t l2c_cfg;
+    l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+
+    if (l2c_cfg.s.idxalias)
+    {
+        idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+    }
+    idx &= CVMX_L2C_IDX_MASK;
+    return(idx);
+}
+
+int cvmx_l2c_get_cache_size_bytes(void)
+{
+    return (cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() * CVMX_CACHE_LINE_SIZE);
+}
+
+/**
+ * Return log base 2 of the number of sets in the L2 cache
+ * @return
+ */
+int cvmx_l2c_get_set_bits(void)
+{
+    int l2_set_bits;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN58XX))
+        l2_set_bits =  11; /* 2048 sets */
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+        l2_set_bits =  10; /* 1024 sets */
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+        l2_set_bits =  9; /* 512 sets */
+    else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+        l2_set_bits =  8; /* 256 sets */
+    else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
+        l2_set_bits =  7; /* 128 sets */
+    else
+    {
+        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+        l2_set_bits =  11; /* 2048 sets */
+    }
+    return(l2_set_bits);
+
+}
+
+/* Return the number of sets in the L2 Cache */
+int cvmx_l2c_get_num_sets(void)
+{
+    return (1 << cvmx_l2c_get_set_bits());
+}
+
+/* Return the number of associations in the L2 Cache */
+int cvmx_l2c_get_num_assoc(void)
+{
+    int l2_assoc;
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN52XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN58XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN50XX) ||
+        OCTEON_IS_MODEL(OCTEON_CN38XX))
+        l2_assoc =  8;
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || 
+             OCTEON_IS_MODEL(OCTEON_CN30XX))
+        l2_assoc =  4;
+    else
+    {
+        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __FUNCTION__);
+        l2_assoc =  8;
+    }
+
+    /* Check to see if part of the cache is disabled */
+    if (cvmx_fuse_read(265))
+        l2_assoc = l2_assoc >> 2;
+    else if (cvmx_fuse_read(264))
+        l2_assoc = l2_assoc >> 1;
+
+    return(l2_assoc);
+}
+
+
+#ifndef CVMX_BUILD_FOR_LINUX_HOST
+/**
+ * Flush a line from the L2 cache
+ * This should only be called from one core at a time, as this routine
+ * sets the core to the 'debug' core in order to flush the line.
+ *
+ * @param assoc  Association (or way) to flush
+ * @param index  Index to flush
+ */
+void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
+{
+    cvmx_l2c_dbg_t l2cdbg;
+
+    l2cdbg.u64 = 0;
+    l2cdbg.s.ppnum = cvmx_get_core_num();
+    l2cdbg.s.finv = 1;
+
+    l2cdbg.s.set = assoc;
+    /* Enter debug mode, and make sure all other writes complete before we
+    ** enter debug mode */
+    asm volatile ("sync \n"::: "memory");
+    cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+    cvmx_read_csr(CVMX_L2C_DBG);
+
+    CVMX_PREPARE_FOR_STORE (((1ULL << 63) + (index)*128), 0);
+    /* Exit debug mode */
+    asm volatile ("sync \n"::: "memory");
+    cvmx_write_csr(CVMX_L2C_DBG, 0);
+    cvmx_read_csr(CVMX_L2C_DBG);
+}
+#endif
diff --git a/cvmx-l2c.h b/cvmx-l2c.h
new file mode 100644
index 0000000000000..bd049c0c9dc9c
--- /dev/null
+++ b/cvmx-l2c.h
@@ -0,0 +1,364 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
+ * facilities.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_L2C_H__
+#define __CVMX_L2C_H__
+
+#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()   /* Deprecated macro, use function */
+#define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()    /* Deprecated macro, use function */
+#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()    /* Deprecated macro, use function */
+
+
+#define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */
+#define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
+
+/* Defines for index aliasing computations */
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+
+
+  /*------------*/
+  /*  TYPEDEFS  */
+  /*------------*/
+typedef union {        // L2C Tag/Data Store Debug Register
+  uint64_t    u64;
+  struct {
+    uint64_t  reserved: 32,
+	      lfb_enum:  4,
+	      lfb_dmp:   1,
+	      ppnum:     4,
+	      set:       3,
+	      finv:      1,
+	      l2d:       1,
+	      l2t:       1;
+  };
+} cvmx_l2c_dbg;
+
+typedef union
+{
+    uint64_t u64;
+#if __BYTE_ORDER == __BIG_ENDIAN
+    struct
+    {
+	uint64_t reserved		: 28;
+	uint64_t V			: 1;	// Line valid
+	uint64_t D			: 1;	// Line dirty
+	uint64_t L			: 1;	// Line locked
+	uint64_t U			: 1;	// Use, LRU eviction
+	uint64_t addr			: 32;	// Phys mem (not all bits valid)
+    } s;
+#endif
+} cvmx_l2c_tag_t;
+
+
+  /* L2C Performance Counter events. */
+typedef enum
+{
+    CVMX_L2C_EVENT_CYCLES           =  0,
+    CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
+    CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
+    CVMX_L2C_EVENT_DATA_MISS        =  3,
+    CVMX_L2C_EVENT_DATA_HIT         =  4,
+    CVMX_L2C_EVENT_MISS             =  5,
+    CVMX_L2C_EVENT_HIT              =  6,
+    CVMX_L2C_EVENT_VICTIM_HIT       =  7,
+    CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
+    CVMX_L2C_EVENT_TAG_PROBE        =  9,
+    CVMX_L2C_EVENT_TAG_UPDATE       = 10,
+    CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
+    CVMX_L2C_EVENT_TAG_DIRTY        = 12,
+    CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
+    CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
+    CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
+    CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
+    CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
+    CVMX_L2C_EVENT_READ_REQUEST     = 18,
+    CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
+    CVMX_L2C_EVENT_XMC_NOP          = 20,
+    CVMX_L2C_EVENT_XMC_LDT          = 21,
+    CVMX_L2C_EVENT_XMC_LDI          = 22,
+    CVMX_L2C_EVENT_XMC_LDD          = 23,
+    CVMX_L2C_EVENT_XMC_STF          = 24,
+    CVMX_L2C_EVENT_XMC_STT          = 25,
+    CVMX_L2C_EVENT_XMC_STP          = 26,
+    CVMX_L2C_EVENT_XMC_STC          = 27,
+    CVMX_L2C_EVENT_XMC_DWB          = 28,
+    CVMX_L2C_EVENT_XMC_PL2          = 29,
+    CVMX_L2C_EVENT_XMC_PSL1         = 30,
+    CVMX_L2C_EVENT_XMC_IOBLD        = 31,
+    CVMX_L2C_EVENT_XMC_IOBST        = 32,
+    CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
+    CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
+    CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
+    CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
+    CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
+    CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
+    CVMX_L2C_EVENT_RSC_NOP          = 39,
+    CVMX_L2C_EVENT_RSC_STDN         = 40,
+    CVMX_L2C_EVENT_RSC_FILL         = 41,
+    CVMX_L2C_EVENT_RSC_REFL         = 42,
+    CVMX_L2C_EVENT_RSC_STIN         = 43,
+    CVMX_L2C_EVENT_RSC_SCIN         = 44,
+    CVMX_L2C_EVENT_RSC_SCFL         = 45,
+    CVMX_L2C_EVENT_RSC_SCDN         = 46,
+    CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
+    CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
+    CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
+    CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
+    CVMX_L2C_EVENT_LRF_REQ          = 51,
+    CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
+    CVMX_L2C_EVENT_DT_WR_INVAL      = 53
+} cvmx_l2c_event_t;
+
+/**
+ * Configure one of the four L2 Cache performance counters to capture event
+ * occurences.
+ *
+ * @param counter        The counter to configure. Range 0..3.
+ * @param event          The type of L2 Cache event occurrence to count.
+ * @param clear_on_read  When asserted, any read of the performance counter
+ *                       clears the counter.
+ *
+ * @note The routine does not clear the counter.
+ */
+void cvmx_l2c_config_perf(uint32_t         counter,
+                               cvmx_l2c_event_t event,
+                               uint32_t         clear_on_read);
+/**
+ * Read the given L2 Cache performance counter. The counter must be configured
+ * before reading, but this routine does not enforce this requirement.
+ *
+ * @param counter  The counter to configure. Range 0..3.
+ *
+ * @return The current counter value.
+ */
+uint64_t cvmx_l2c_read_perf(uint32_t counter);
+
+/**
+ * Return the L2 Cache way partitioning for a given core.
+ *
+ * @param core  The core processor of interest.
+ *
+ * @return    The mask specifying the partitioning. 0 bits in mask indicates
+ *              the cache 'ways' that a core can evict from.
+ *            -1 on error
+ */
+int cvmx_l2c_get_core_way_partition(uint32_t core);
+
+/**
+ * Partitions the L2 cache for a core
+ *
+ * @param core   The core that the partitioning applies to.
+ * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
+ *             to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
+ *             from that way. There must be at least one allowed way (0 bit) in the mask.
+ *
+ * @note  If any ways are blocked for all cores and the HW blocks, then those ways will never have
+ *        any cache lines evicted from them.  All cores and the hardware blocks are free to read from
+ *        all ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
+
+/**
+ * Return the L2 Cache way partitioning for the hw blocks.
+ *
+ * @return    The mask specifying the reserved way. 0 bits in mask indicates
+ *              the cache 'ways' that a core can evict from.
+ *            -1 on error
+ */
+int cvmx_l2c_get_hw_way_partition(void);
+
+/**
+ * Partitions the L2 cache for the hardware blocks.
+ *
+ * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
+ *             to evict cache lines from a way, while a 1 bit blocks the core from evicting any lines
+ *             from that way. There must be at least one allowed way (0 bit) in the mask.
+ *
+ * @note  If any ways are blocked for all cores and the HW blocks, then those ways will never have
+ *        any cache lines evicted from them.  All cores and the hardware blocks are free to read from
+ *        all ways regardless of the partitioning.
+ */
+int cvmx_l2c_set_hw_way_partition(uint32_t mask);
+
+
+/**
+ * Locks a line in the L2 cache at the specified physical address
+ *
+ * @param addr   physical address of line to lock
+ *
+ * @return 0 on success,
+ *         1 if line not locked.
+ */
+int cvmx_l2c_lock_line(uint64_t addr);
+
+/**
+ * Locks a specified memory region in the L2 cache.
+ *
+ * Note that if not all lines can be locked, that means that all
+ * but one of the ways (associations) available to the locking
+ * core are locked.  Having only 1 association available for
+ * normal caching may have a significant adverse affect on performance.
+ * Care should be taken to ensure that enough of the L2 cache is left
+ * unlocked to allow for normal caching of DRAM.
+ *
+ * @param start  Physical address of the start of the region to lock
+ * @param len    Length (in bytes) of region to lock
+ *
+ * @return Number of requested lines that where not locked.
+ *         0 on success (all locked)
+ */
+int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
+
+
+/**
+ * Unlock and flush a cache line from the L2 cache.
+ * IMPORTANT: Must only be run by one core at a time due to use
+ * of L2C debug features.
+ * Note that this function will flush a matching but unlocked cache line.
+ * (If address is not in L2, no lines are flushed.)
+ *
+ * @param address Physical address to unlock
+ *
+ * @return 0: line not unlocked
+ *         1: line unlocked
+ */
+int cvmx_l2c_unlock_line(uint64_t address);
+
+/**
+ * Unlocks a region of memory that is locked in the L2 cache
+ *
+ * @param start  start physical address
+ * @param len    length (in bytes) to unlock
+ *
+ * @return Number of locked lines that the call unlocked
+ */
+int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
+
+
+
+
+/**
+ * Read the L2 controller tag for a given location in L2
+ *
+ * @param association
+ *               Which association to read line from
+ * @param index  Which way to read from.
+ *
+ * @return l2c tag structure for line requested.
+ */
+cvmx_l2c_tag_t cvmx_l2c_get_tag(uint32_t association, uint32_t index);
+
+/* Wrapper around deprecated old function name */
+static inline cvmx_l2c_tag_t cvmx_get_l2c_tag(uint32_t association, uint32_t index)
+{
+    return cvmx_l2c_get_tag(association, index);
+}
+
+
+/**
+ * Returns the cache index for a given physical address
+ *
+ * @param addr   physical address
+ *
+ * @return L2 cache index
+ */
+uint32_t cvmx_l2c_address_to_index (uint64_t addr);
+
+
+/**
+ * Flushes (and unlocks) the entire L2 cache.
+ * IMPORTANT: Must only be run by one core at a time due to use
+ * of L2C debug features.
+ */
+void cvmx_l2c_flush(void);
+
+
+
+/**
+ *
+ * @return Returns the size of the L2 cache in bytes,
+ * -1 on error (unrecognized model)
+ */
+int cvmx_l2c_get_cache_size_bytes(void);
+
+/**
+ * Return the number of sets in the L2 Cache
+ *
+ * @return
+ */
+int cvmx_l2c_get_num_sets(void);
+
+/**
+ * Return log base 2 of the number of sets in the L2 cache
+ * @return
+ */
+int cvmx_l2c_get_set_bits(void);
+/**
+ * Return the number of associations in the L2 Cache
+ *
+ * @return
+ */
+int cvmx_l2c_get_num_assoc(void);
+
+/**
+ * Flush a line from the L2 cache
+ * This should only be called from one core at a time, as this routine
+ * sets the core to the 'debug' core in order to flush the line.
+ *
+ * @param assoc  Association (or way) to flush
+ * @param index  Index to flush
+ */
+void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
+
+#endif /* __CVMX_L2C_H__ */
diff --git a/cvmx-llm.c b/cvmx-llm.c
new file mode 100644
index 0000000000000..fb058c8083908
--- /dev/null
+++ b/cvmx-llm.c
@@ -0,0 +1,956 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Configuration functions for low latency memory.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-llm.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-csr-db.h"
+
+#define	MIN(a,b) (((a)<(b))?(a):(b))
+
+typedef struct
+{
+    uint32_t dfa_memcfg0_base;
+    uint32_t dfa_memcfg1_base;
+    uint32_t mrs_dat_p0bunk0;
+    uint32_t mrs_dat_p0bunk1;
+    uint32_t mrs_dat_p1bunk0;
+    uint32_t mrs_dat_p1bunk1;
+    uint8_t  p0_ena;
+    uint8_t  p1_ena;
+    uint8_t  bunkport;
+} rldram_csr_config_t;
+
+
+
+
+
+int rld_csr_config_generate(llm_descriptor_t *llm_desc_ptr, rldram_csr_config_t *cfg_ptr);
+
+
+void print_rld_cfg(rldram_csr_config_t *cfg_ptr);
+void write_rld_cfg(rldram_csr_config_t *cfg_ptr);
+static void cn31xx_dfa_memory_init(void);
+
+static uint32_t process_address_map_str(uint32_t mrs_dat, char *addr_str);
+
+
+
+#ifndef CVMX_LLM_NUM_PORTS
+#warning WARNING: default CVMX_LLM_NUM_PORTS used.  Defaults deprecated, please set in executive-config.h
+#define CVMX_LLM_NUM_PORTS 1
+#endif
+
+
+#if (CVMX_LLM_NUM_PORTS != 1) && (CVMX_LLM_NUM_PORTS != 2)
+#error "Invalid CVMX_LLM_NUM_PORTS value: must be 1 or 2\n"
+#endif
+
+int cvmx_llm_initialize()
+{
+    if (cvmx_llm_initialize_desc(NULL) < 0)
+        return -1;
+
+    return 0;
+}
+
+
+int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr)
+{
+    cvmx_sysinfo_t *sys_ptr;
+    sys_ptr = cvmx_sysinfo_get();
+
+    if (!llm_desc_ptr)
+        return -1;
+
+    memset(llm_desc_ptr, 0, sizeof(llm_descriptor_t));
+
+    llm_desc_ptr->cpu_hz = sys_ptr->cpu_clock_hz;
+
+    if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBT3000)
+    { // N3K->RLD0 Address Swizzle
+        strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10");
+        // N3K->RLD1 Address Swizzle
+        strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+        /* NOTE: The ebt3000 has a strange RLDRAM configuration for validation purposes.  It is not recommended to have
+        ** different amounts of memory on different ports as that renders some memory unusable */
+        llm_desc_ptr->rld0_bunks = 2;
+        llm_desc_ptr->rld1_bunks = 2;
+        llm_desc_ptr->rld0_mbytes = 128;          // RLD0: 4x 32Mx9
+        llm_desc_ptr->rld1_mbytes = 64;           // RLD1: 2x 16Mx18
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBT5800)
+    {
+        strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+        strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+        llm_desc_ptr->rld0_bunks = 2;
+        llm_desc_ptr->rld1_bunks = 2;
+        llm_desc_ptr->rld0_mbytes = 128;
+        llm_desc_ptr->rld1_mbytes = 128;
+        llm_desc_ptr->max_rld_clock_mhz = 400;  /* CN58XX needs a max clock speed for selecting optimal divisor */
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBH3000)
+    {
+        strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10");
+        strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10");
+        llm_desc_ptr->rld0_bunks = 2;
+        llm_desc_ptr->rld1_bunks = 2;
+        llm_desc_ptr->rld0_mbytes = 128;
+        llm_desc_ptr->rld1_mbytes = 128;
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_NAC38)
+    {
+        if (sys_ptr->board_rev_major == 1 && sys_ptr->board_rev_minor == 0)
+        {
+            strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+            strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+            strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+            strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 00 08 07 06 05 04 13 02 01 03 09 18 17 16 15 14 10 12 11 19");
+            llm_desc_ptr->rld0_bunks = 2;
+            llm_desc_ptr->rld1_bunks = 2;
+            llm_desc_ptr->rld0_mbytes = 128;
+            llm_desc_ptr->rld1_mbytes = 128;
+        }
+        else
+        {   /* Asus new recommendation  */
+            strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 09 11 04 06 05 08 15 20 16 18 12 13 00 01 07 02 19 17 10 14 03");
+            strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 11 09 00 01 07 02 19 17 10 14 03 13 04 06 05 08 15 20 16 18 12");
+            strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 08 13 14 00 04 12 16 11 19 10 07 02 01 05 03 06 17 18 20 09 15");
+            strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 13 08 01 05 03 06 17 18 20 09 15 02 14 00 04 12 16 11 19 10 07");
+            llm_desc_ptr->rld0_bunks = 2;
+            llm_desc_ptr->rld1_bunks = 2;
+            llm_desc_ptr->rld0_mbytes = 128;
+            llm_desc_ptr->rld1_mbytes = 128;
+        }
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_THUNDER)
+    {
+
+        if (sys_ptr->board_rev_major >= 4)
+        {
+            strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 13 11 01 02 07 19 03 18 10 12 20 06 04 08 17 05 14 16 00 09 15");
+            strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 11 13 04 08 17 05 14 16 00 09 15 06 01 02 07 19 03 18 10 12 20");
+            strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 02 19 18 17 16 09 14 13 20 11 10 01 08 03 06 15 04 07 05 12 00");
+            strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 19 02 08 03 06 15 04 07 05 12 00 01 18 17 16 09 14 13 20 11 10");
+        }
+        else
+        {
+            strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+            strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+            strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+            strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        }
+
+        llm_desc_ptr->rld0_bunks = 2;
+        llm_desc_ptr->rld1_bunks = 2;
+        llm_desc_ptr->rld0_mbytes = 128;
+        llm_desc_ptr->rld1_mbytes = 128;
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_NICPRO2)
+    {
+        strcpy(llm_desc_ptr->addr_rld0_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld0_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10");
+        strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 19 20 08 07 06 05 04 03 02 01 00 09 18 17 16 15 14 13 12 11 10");
+        llm_desc_ptr->rld0_bunks = 2;
+        llm_desc_ptr->rld1_bunks = 2;
+        llm_desc_ptr->rld0_mbytes = 256;
+        llm_desc_ptr->rld1_mbytes = 256;
+        llm_desc_ptr->max_rld_clock_mhz = 400;  /* CN58XX needs a max clock speed for selecting optimal divisor */
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBH3100)
+    {
+        /* CN31xx DFA memory is DDR based, so it is completely different from the CN38XX DFA memory */
+        llm_desc_ptr->rld0_bunks = 1;
+        llm_desc_ptr->rld0_mbytes = 256;
+    }
+    else if (sys_ptr->board_type == CVMX_BOARD_TYPE_KBP)
+    {
+        strcpy(llm_desc_ptr->addr_rld0_fb_str, "");
+        strcpy(llm_desc_ptr->addr_rld0_bb_str, "");
+        llm_desc_ptr->rld0_bunks = 0;
+        llm_desc_ptr->rld0_mbytes = 0;
+        strcpy(llm_desc_ptr->addr_rld1_fb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        strcpy(llm_desc_ptr->addr_rld1_bb_str, "22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00");
+        llm_desc_ptr->rld1_bunks = 2;
+        llm_desc_ptr->rld1_mbytes = 64;
+    }
+    else
+    {
+        cvmx_dprintf("No default LLM configuration available for board %s (%d)\n", cvmx_board_type_to_string(sys_ptr->board_type),  sys_ptr->board_type);
+        return -1;
+    }
+
+    return(0);
+}
+
+int cvmx_llm_initialize_desc(llm_descriptor_t *llm_desc_ptr)
+{
+    cvmx_sysinfo_t *sys_ptr;
+    sys_ptr = cvmx_sysinfo_get();
+    llm_descriptor_t default_llm_desc;
+
+    memset(&default_llm_desc, 0, sizeof(default_llm_desc));
+    if (sys_ptr->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+        cvmx_dprintf("Skipping llm configuration for simulator.\n");
+        return 0;
+    }
+
+    if (sys_ptr->board_type == CVMX_BOARD_TYPE_EBH3100)
+    {
+        /* CN31xx DFA memory is DDR based, so it is completely different from the CN38XX DFA memory
+        ** config descriptors are not supported yet.*/
+        cvmx_dprintf("Warning: preliminary DFA memory configuration\n");
+        cn31xx_dfa_memory_init();
+        return(256*1024*1024);
+    }
+
+    /* If no descriptor passed, generate default descriptor based on board type.
+    ** Fail if no default available for given board type
+    */
+    if (!llm_desc_ptr)
+    {
+        /* Get default descriptor */
+        if (0 > cvmx_llm_get_default_descriptor(&default_llm_desc))
+            return -1;
+
+        /* Disable second port depending on CVMX config */
+        if (CVMX_LLM_NUM_PORTS == 1)
+	  default_llm_desc.rld0_bunks = 0;        // For single port: Force RLD0(P1) to appear EMPTY
+
+        cvmx_dprintf("Using default LLM configuration for board %s (%d)\n", cvmx_board_type_to_string(sys_ptr->board_type),  sys_ptr->board_type);
+
+        llm_desc_ptr = &default_llm_desc;
+    }
+
+
+
+    rldram_csr_config_t ebt3000_rld_cfg;
+    if (!rld_csr_config_generate(llm_desc_ptr, &ebt3000_rld_cfg))
+    {
+        cvmx_dprintf("Configuring %d llm port(s).\n", !!llm_desc_ptr->rld0_bunks + !!llm_desc_ptr->rld1_bunks);
+        write_rld_cfg(&ebt3000_rld_cfg);
+    }
+    else
+    {
+        cvmx_dprintf("Error creating rldram configuration\n");
+        return(-1);
+    }
+
+    /* Compute how much memory is configured
+    ** Memory is interleaved, so if one port has more than the other some memory is not usable */
+
+    /* If both ports are enabled, handle the case where one port has more than the other.
+    ** This is an unusual and not recommended configuration that exists on the ebt3000 board */
+    if (!!llm_desc_ptr->rld0_bunks && !!llm_desc_ptr->rld1_bunks)
+        llm_desc_ptr->rld0_mbytes = llm_desc_ptr->rld1_mbytes = MIN(llm_desc_ptr->rld0_mbytes, llm_desc_ptr->rld1_mbytes);
+
+    return(((!!llm_desc_ptr->rld0_bunks) * llm_desc_ptr->rld0_mbytes
+          + (!!llm_desc_ptr->rld1_bunks) * llm_desc_ptr->rld1_mbytes) * 1024*1024);
+}
+
+//======================
+// SUPPORT FUNCTIONS:
+//======================
+//======================================================================
+// Extracts srcvec[srcbitpos] and places it in return int (bit[0])
+int bit_extract ( int srcvec,         // source word (to extract)
+                  int srcbitpos       // source bit position
+                )
+{
+    return(((1 << srcbitpos) & srcvec) >> srcbitpos);
+}
+//======================================================================
+// Inserts srcvec[0] into dstvec[dstbitpos] (without affecting other bits)
+int bit_insert ( int srcvec,           // srcvec[0] = bit to be inserted
+                 int dstbitpos,        // Bit position to insert into returned int
+                 int dstvec            // dstvec (destination vector)
+               )
+{
+    return((srcvec << dstbitpos) | dstvec);      // Shift bit to insert into bit position/OR with accumulated number
+}
+//======================================================================
+
+int rld_csr_config_generate(llm_descriptor_t *llm_desc_ptr, rldram_csr_config_t *cfg_ptr)
+{
+    char *addr_rld0_fb_str;
+    char *addr_rld0_bb_str;
+    char *addr_rld1_fb_str;
+    char *addr_rld1_bb_str;
+    int eclk_ps;
+    int mtype = 0;                           // MTYPE (0: RLDRAM/1: FCRAM
+    int trcmin = 20;                         // tRC(min) - from RLDRAM data sheet
+    int trc_cyc;                             // TRC(cyc)
+    int trc_mod;
+    int trl_cyc;                             // TRL(cyc)
+    int twl_cyc;                             // TWL(cyc)
+    int tmrsc_cyc = 6;                       // tMRSC(cyc)  [2-7]
+    int mclk_ps;                             // DFA Memory Clock(in ps) = 2x eclk
+    int rldcfg = 99;                         // RLDRAM-II CFG (1,2,3)
+    int mrs_odt = 0;                         // RLDRAM MRS A[9]=ODT (default)
+    int mrs_impmatch = 0;                    // RLDRAM MRS A[8]=Impedance Matching (default)
+    int mrs_dllrst = 1;                      // RLDRAM MRS A[7]=DLL Reset (default)
+    uint32_t mrs_dat;
+    int mrs_dat_p0bunk0 = 0;                 // MRS Register Data After Address Map (for Port0 Bunk0)
+    int mrs_dat_p0bunk1 = 0;                 // MRS Register Data After Address Map (for Port0 Bunk1)
+    int mrs_dat_p1bunk0 = 0;                 // MRS Register Data After Address Map (for Port1 Bunk0)
+    int mrs_dat_p1bunk1 = 0;                 // MRS Register Data After Address Map (for Port1 Bunk1)
+    int p0_ena = 0;                          // DFA Port#0 Enabled
+    int p1_ena = 0;                          // DFA Port#1 Enabled
+    int memport = 0;                       // Memory(MB) per Port [MAX=512]
+    int membunk;                             // Memory(MB) per Bunk
+    int bunkport = 0;                        // Bunks/Port [1/2]
+    int pbunk = 0;                               // Physical Bunk(or Rank) encoding for address bit
+    int tref_ms = 32;                        // tREF(ms) (RLDRAM-II overall device refresh interval
+    int trefi_ns;                            // tREFI(ns) = tREF(ns)/#rows/bank
+    int rows = 8;                            // #rows/bank (K) typically 8K
+    int ref512int;
+    int ref512mod;
+    int tskw_cyc = 0;
+    int fprch = 1;
+    int bprch = 0;
+    int dfa_memcfg0_base = 0;
+    int dfa_memcfg1_base = 0;
+    int tbl = 1;                             // tBL (1: 2-burst /2: 4-burst)
+    int rw_dly;
+    int wr_dly;
+    int r2r = 1;
+    int sil_lat = 1;
+    int clkdiv = 2;  /* CN38XX is fixed at 2, CN58XX supports 2,3,4 */
+    int clkdiv_enc = 0x0;  /* Encoded clock divisor, only used for CN58XX */
+
+    if (!llm_desc_ptr)
+        return -1;
+
+    /* Setup variables from descriptor */
+
+    addr_rld0_fb_str = llm_desc_ptr->addr_rld0_fb_str;
+    addr_rld0_bb_str = llm_desc_ptr->addr_rld0_bb_str;
+    addr_rld1_fb_str = llm_desc_ptr->addr_rld1_fb_str;
+    addr_rld1_bb_str = llm_desc_ptr->addr_rld1_bb_str;
+
+    p0_ena = !!llm_desc_ptr->rld1_bunks;        // NOTE: P0 == RLD1
+    p1_ena = !!llm_desc_ptr->rld0_bunks;        // NOTE: P1 == RLD0
+
+    // Massage the code, so that if the user had imbalanced memory per-port (or imbalanced bunks/port), we
+    // at least try to configure 'workable' memory.
+    if (p0_ena && p1_ena)  // IF BOTH PORTS Enabled (imbalanced memory), select smaller of BOTH
+    {
+        memport = MIN(llm_desc_ptr->rld0_mbytes, llm_desc_ptr->rld1_mbytes);
+        bunkport = MIN(llm_desc_ptr->rld0_bunks, llm_desc_ptr->rld1_bunks);
+    }
+    else if (p0_ena) // P0=RLD1 Enabled
+    {
+        memport = llm_desc_ptr->rld1_mbytes;
+        bunkport = llm_desc_ptr->rld1_bunks;
+    }
+    else if (p1_ena) // P1=RLD0 Enabled
+    {
+        memport = llm_desc_ptr->rld0_mbytes;
+        bunkport = llm_desc_ptr->rld0_bunks;
+    }
+    else
+        return -1;
+
+    uint32_t eclk_mhz = llm_desc_ptr->cpu_hz/1000000;
+
+
+
+    /* Tweak skew based on cpu clock */
+    if (eclk_mhz <= 367)
+    {
+        tskw_cyc = 0;
+    }
+    else
+    {
+        tskw_cyc = 1;
+    }
+
+    /* Determine clock divider ratio (only required for CN58XX) */
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+    {
+        uint32_t max_llm_clock_mhz = llm_desc_ptr->max_rld_clock_mhz;
+        if (!max_llm_clock_mhz)
+        {
+            max_llm_clock_mhz = 400;  /* Default to 400 MHz */
+            cvmx_dprintf("Warning, using default max_rld_clock_mhz of: %lu MHz\n", (unsigned long)max_llm_clock_mhz);
+        }
+
+        /* Compute the divisor, and round up */
+        clkdiv = eclk_mhz/max_llm_clock_mhz;
+        if (clkdiv * max_llm_clock_mhz < eclk_mhz)
+            clkdiv++;
+
+        if (clkdiv > 4)
+        {
+            cvmx_dprintf("ERROR: CN58XX LLM clock divisor out of range\n");
+            goto TERMINATE;
+        }
+        if (clkdiv < 2)
+            clkdiv = 2;
+
+        cvmx_dprintf("Using llm clock divisor: %d, llm clock is: %lu MHz\n", clkdiv, (unsigned long)eclk_mhz/clkdiv);
+        /* Translate divisor into bit encoding for register */
+        /* 0 -> div 2
+        ** 1 -> reserved
+        ** 2 -> div 3
+        ** 3 -> div 4
+        */
+        if (clkdiv == 2)
+            clkdiv_enc = 0;
+        else
+            clkdiv_enc = clkdiv - 1;
+
+    /* Odd divisor needs sil_lat to be 2 */
+        if (clkdiv == 0x3)
+            sil_lat = 2;
+
+        /* Increment tskw for high clock speeds */
+        if ((unsigned long)eclk_mhz/clkdiv > 375)
+            tskw_cyc += 1;
+    }
+
+    eclk_ps = (1000000+(eclk_mhz-1)) / eclk_mhz;  // round up if nonzero remainder
+    //=======================================================================
+
+    //=======================================================================
+    // Now, Query User for DFA Memory Type
+    if (mtype != 0)
+    {
+        goto TERMINATE;         // Complete this code for FCRAM usage on N3K-P2
+    }
+    //=======================================================================
+    // Query what the tRC(min) value is from the data sheets
+    //=======================================================================
+    // Now determine the Best CFG based on Memory clock(ps) and tRCmin(ns)
+    mclk_ps = eclk_ps * clkdiv;
+    trc_cyc = ((trcmin * 1000)/mclk_ps);
+    trc_mod = ((trcmin * 1000) % mclk_ps);
+    // If remainder exists, bump up to the next integer multiple
+    if (trc_mod != 0)
+    {
+        trc_cyc = trc_cyc + 1;
+    }
+    // If tRC is now ODD, then bump it to the next EVEN integer (RLDRAM-II does not support odd tRC values at this time).
+    if (trc_cyc & 1)
+    {
+        trc_cyc = trc_cyc + 1;           // Bump it to an even #
+    }
+    // RLDRAM CFG Range Check: If the computed trc_cyc is less than 4, then set it to min CFG1 [tRC=4]
+    if (trc_cyc < 4)
+    {
+        trc_cyc = 4;             // If computed trc_cyc < 4 then clamp to 4
+    }
+    else if (trc_cyc > 8)
+    {    // If the computed trc_cyc > 8, then report an error (because RLDRAM cannot support a tRC>8
+        goto TERMINATE;
+    }
+    // Assuming all is ok(up to here)
+    // At this point the tRC_cyc has been clamped  between 4 and 8 (and is even), So it can only be 4,6,8 which are
+    // the RLDRAM valid CFG range values.
+    trl_cyc = trc_cyc;                 // tRL = tRC (for RLDRAM=II)
+    twl_cyc = trl_cyc + 1;             // tWL = tRL + 1 (for RLDRAM-II)
+    // NOTE: RLDRAM-II (as of 4/25/05) only have 3 supported CFG encodings:
+    if (trc_cyc == 4)
+    {
+        rldcfg = 1;           // CFG #1 (tRL=4/tRC=4/tWL=5)
+    }
+    else if (trc_cyc == 6)
+    {
+        rldcfg = 2;           // CFG #2 (tRL=6/tRC=6/tWL=7)
+    }
+    else if (trc_cyc == 8)
+    {
+        rldcfg = 3;           // CFG #3 (tRL=8/tRC=8/tWL=9)
+    }
+    else
+    {
+        goto TERMINATE;
+    }
+    //=======================================================================
+    mrs_dat = ( (mrs_odt << 9) | (mrs_impmatch << 8) | (mrs_dllrst << 7) | rldcfg );
+    //=======================================================================
+    // If there is only a single bunk, then skip over address mapping queries (which are not required)
+    if (bunkport == 1)
+    {
+        goto CALC_PBUNK;
+    }
+
+    /* Process the address mappings */
+    /* Note that that RLD0 pins corresponds to Port#1, and
+    **                RLD1 pins corresponds to Port#0.
+    */
+    mrs_dat_p1bunk0 = process_address_map_str(mrs_dat, addr_rld0_fb_str);
+    mrs_dat_p1bunk1 = process_address_map_str(mrs_dat, addr_rld0_bb_str);
+    mrs_dat_p0bunk0 = process_address_map_str(mrs_dat, addr_rld1_fb_str);
+    mrs_dat_p0bunk1 = process_address_map_str(mrs_dat, addr_rld1_bb_str);
+
+
+    //=======================================================================
+    CALC_PBUNK:
+    // Determine the PBUNK field (based on Memory/Bunk)
+    // This determines the addr bit used to distinguish when crossing a bunk.
+    // NOTE: For RLDRAM, the bunk bit is extracted from 'a' programmably selected high
+    // order addr bit. [linear address per-bunk]
+    if (bunkport == 2)
+    {
+        membunk = (memport / 2);
+    }
+    else
+    {
+        membunk = memport;
+    }
+    if (membunk == 16)
+    {       // 16MB/bunk MA[19]
+        pbunk = 0;
+    }
+    else if (membunk == 32)
+    {  // 32MB/bunk MA[20]
+        pbunk = 1;
+    }
+    else if (membunk == 64)
+    {  // 64MB/bunk MA[21]
+        pbunk = 2;
+    }
+    else if (membunk == 128)
+    { // 128MB/bunk MA[22]
+        pbunk = 3;
+    }
+    else if (membunk == 256)
+    { // 256MB/bunk MA[23]
+        pbunk = 4;
+    }
+    else if (membunk == 512)
+    { // 512MB/bunk
+        if (cvmx_octeon_is_pass1() == 1)
+        {
+            goto TERMINATE;
+        }
+    }
+    //=======================================================================
+    //=======================================================================
+    //=======================================================================
+    // Now determine N3K REFINT
+    trefi_ns = (tref_ms * 1000 * 1000) / (rows * 1024);
+    ref512int = ((trefi_ns * 1000) / (eclk_ps * 512));
+    ref512mod = ((trefi_ns * 1000) % (eclk_ps * 512));
+    //=======================================================================
+    // Ask about tSKW
+#if 0
+    if (tskw_ps ==  0)
+    {
+        tskw_cyc = 0;
+    }
+    else
+    { // CEILING function
+        tskw_cyc = (tskw_ps / eclk_ps);
+        tskw_mod = (tskw_ps % eclk_ps);
+        if (tskw_mod != 0)
+        {  // If there's a remainder - then bump to next (+1)
+            tskw_cyc = tskw_cyc + 1;
+        }
+    }
+#endif
+    if (tskw_cyc > 3)
+    {
+        goto TERMINATE;
+    }
+
+    tbl = 1;        // BLEN=2 (ALWAYs for RLDRAM)
+    //=======================================================================
+    // RW_DLY = (ROUND_UP{[[(TRL+TBL)*2 + tSKW + BPRCH] + 1] / 2}) - tWL
+    rw_dly = ((((trl_cyc + tbl) * 2 + tskw_cyc + bprch) + 1) / 2);
+    if (rw_dly & 1)
+    { // If it's ODD then round up
+        rw_dly = rw_dly + 1;
+    }
+    rw_dly = rw_dly - twl_cyc +1 ;
+    if (rw_dly < 0)
+    { // range check - is it positive
+        goto TERMINATE;
+    }
+    //=======================================================================
+    // WR_DLY = (ROUND_UP[[(tWL + tBL)*2 - tSKW + FPRCH] / 2]) - tRL
+    wr_dly = (((twl_cyc + tbl) * 2 - tskw_cyc + fprch) / 2);
+    if (wr_dly & 1)
+    { // If it's ODD then round up
+        wr_dly = wr_dly + 1;
+    }
+    wr_dly = wr_dly - trl_cyc + 1;
+    if (wr_dly < 0)
+    { // range check - is it positive
+        goto TERMINATE;
+    }
+
+
+    dfa_memcfg0_base = 0;
+    dfa_memcfg0_base = ( p0_ena |
+                         (p1_ena << 1) |
+                         (mtype << 3) |
+                         (sil_lat << 4) |
+                         (rw_dly << 6) |
+                         (wr_dly << 10) |
+                         (fprch << 14) |
+                         (bprch << 16) |
+                         (0 << 18) |         // BLEN=0(2-burst for RLDRAM)
+                         (pbunk << 19) |
+                         (r2r << 22) |       // R2R=1
+    			 (clkdiv_enc << 28 )
+                       );
+
+
+    dfa_memcfg1_base = 0;
+    dfa_memcfg1_base = ( ref512int |
+                         (tskw_cyc << 4) |
+                         (trl_cyc << 8) |
+                         (twl_cyc << 12) |
+                         (trc_cyc << 16) |
+                         (tmrsc_cyc << 20)
+                       );
+
+
+
+
+    cfg_ptr->dfa_memcfg0_base = dfa_memcfg0_base;
+    cfg_ptr->dfa_memcfg1_base = dfa_memcfg1_base;
+    cfg_ptr->mrs_dat_p0bunk0 =  mrs_dat_p0bunk0;
+    cfg_ptr->mrs_dat_p1bunk0 =  mrs_dat_p1bunk0;
+    cfg_ptr->mrs_dat_p0bunk1 =  mrs_dat_p0bunk1;
+    cfg_ptr->mrs_dat_p1bunk1 =  mrs_dat_p1bunk1;
+    cfg_ptr->p0_ena =           p0_ena;
+    cfg_ptr->p1_ena =           p1_ena;
+    cfg_ptr->bunkport =         bunkport;
+    //=======================================================================
+
+    return(0);
+    TERMINATE:
+    return(-1);
+
+}
+
+
+
+static uint32_t process_address_map_str(uint32_t mrs_dat, char *addr_str)
+{
+    int count = 0;
+    int amap [23];
+    uint32_t new_mrs_dat = 0;
+
+//    cvmx_dprintf("mrs_dat: 0x%x, str: %x\n", mrs_dat, addr_str);
+    char *charptr = strtok(addr_str," ");
+    while ((charptr != NULL) & (count <= 22))
+    {
+        amap[22-count] = atoi(charptr);         // Assign the AMAP Array
+        charptr = strtok(NULL," ");             // Get Next char string (which represents next addr bit mapping)
+        count++;
+    }
+    // Now do the bit swap of MRSDAT (based on address mapping)
+    uint32_t mrsdat_bit;
+    for (count=0;count<=22;count++)
+    {
+        mrsdat_bit = bit_extract(mrs_dat, count);
+        new_mrs_dat = bit_insert(mrsdat_bit, amap[count], new_mrs_dat);
+    }
+
+    return new_mrs_dat;
+}
+
+
+//#define PRINT_LLM_CONFIG
+#ifdef PRINT_LLM_CONFIG
+#define ll_printf printf
+#else
+#define ll_printf(...)
+#define cvmx_csr_db_decode(...)
+#endif
+
+static void cn31xx_dfa_memory_init(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+    {
+        cvmx_dfa_ddr2_cfg_t  dfaCfg;
+        cvmx_dfa_eclkcfg_t   dfaEcklCfg;
+        cvmx_dfa_ddr2_addr_t dfaAddr;
+        cvmx_dfa_ddr2_tmg_t  dfaTmg;
+        cvmx_dfa_ddr2_pll_t  dfaPll;
+        int mem_freq_hz = 533*1000000;
+        int ref_freq_hz = cvmx_sysinfo_get()->dfa_ref_clock_hz;
+        if (!ref_freq_hz)
+            ref_freq_hz = 33*1000000;
+
+        cvmx_dprintf ("Configuring DFA memory for %d MHz operation.\n",mem_freq_hz/1000000);
+
+          /* Turn on the DFA memory port. */
+        dfaCfg.u64 = cvmx_read_csr (CVMX_DFA_DDR2_CFG);
+        dfaCfg.s.prtena = 1;
+        cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64);
+
+          /* Start the PLL alignment sequence */
+        dfaPll.u64 = 0;
+        dfaPll.s.pll_ratio  = mem_freq_hz/ref_freq_hz         /*400Mhz / 33MHz*/;
+        dfaPll.s.pll_div2   = 1              /*400 - 1 */;
+        dfaPll.s.pll_bypass = 0;
+        cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64);
+
+        dfaPll.s.pll_init = 1;
+        cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64);
+
+        cvmx_wait (RLD_INIT_DELAY); //want 150uS
+        dfaPll.s.qdll_ena = 1;
+        cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64);
+
+        cvmx_wait (RLD_INIT_DELAY); //want 10us
+        dfaEcklCfg.u64 = 0;
+        dfaEcklCfg.s.dfa_frstn = 1;
+        cvmx_write_csr (CVMX_DFA_ECLKCFG, dfaEcklCfg.u64);
+
+          /* Configure the DFA Memory */
+        dfaCfg.s.silo_hc = 1 /*400 - 1 */;
+        dfaCfg.s.silo_qc = 0 /*400 - 0 */;
+        dfaCfg.s.tskw    = 1 /*400 - 1 */;
+        dfaCfg.s.ref_int = 0x820 /*533 - 0x820  400 - 0x618*/;
+        dfaCfg.s.trfc    = 0x1A  /*533 - 0x23   400 - 0x1A*/;
+        dfaCfg.s.fprch   = 0; /* 1 more conservative*/
+        dfaCfg.s.bprch   = 0; /* 1 */
+        cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64);
+
+        dfaEcklCfg.u64 = cvmx_read_csr (CVMX_DFA_ECLKCFG);
+        dfaEcklCfg.s.maxbnk = 1;
+        cvmx_write_csr (CVMX_DFA_ECLKCFG, dfaEcklCfg.u64);
+
+        dfaAddr.u64 = cvmx_read_csr (CVMX_DFA_DDR2_ADDR);
+        dfaAddr.s.num_cols    = 0x1;
+        dfaAddr.s.num_colrows = 0x2;
+        dfaAddr.s.num_rnks    = 0x1;
+        cvmx_write_csr (CVMX_DFA_DDR2_ADDR, dfaAddr.u64);
+
+        dfaTmg.u64 =  cvmx_read_csr (CVMX_DFA_DDR2_TMG);
+        dfaTmg.s.ddr2t    = 0;
+        dfaTmg.s.tmrd     = 0x2;
+        dfaTmg.s.caslat   = 0x4 /*400 - 0x3, 500 - 0x4*/;
+        dfaTmg.s.pocas    = 0;
+        dfaTmg.s.addlat   = 0;
+        dfaTmg.s.trcd     = 4   /*400 - 3, 500 - 4*/;
+        dfaTmg.s.trrd     = 2;
+        dfaTmg.s.tras     = 0xB /*400 - 8, 500 - 0xB*/;
+        dfaTmg.s.trp      = 4   /*400 - 3, 500 - 4*/;
+        dfaTmg.s.twr      = 4   /*400 - 3, 500 - 4*/;
+        dfaTmg.s.twtr     = 2   /*400 - 2 */;
+        dfaTmg.s.tfaw     = 0xE /*400 - 0xA, 500 - 0xE*/;
+        dfaTmg.s.r2r_slot = 0;
+        dfaTmg.s.dic      = 0;  /*400 - 0 */
+        dfaTmg.s.dqsn_ena = 0;
+        dfaTmg.s.odt_rtt  = 0;
+        cvmx_write_csr (CVMX_DFA_DDR2_TMG, dfaTmg.u64);
+
+          /* Turn on the DDR2 interface and wait a bit for the hardware to setup. */
+        dfaCfg.s.init = 1;
+        cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64);
+        cvmx_wait(RLD_INIT_DELAY); // want at least 64K cycles
+    }
+}
+
+void write_rld_cfg(rldram_csr_config_t *cfg_ptr)
+{
+    cvmx_dfa_memcfg0_t    memcfg0;
+    cvmx_dfa_memcfg2_t    memcfg2;
+
+    memcfg0.u64 = cfg_ptr->dfa_memcfg0_base;
+
+    if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+    {
+        uint32_t dfa_memcfg0;
+
+        if (OCTEON_IS_MODEL (OCTEON_CN58XX)) {
+	      // Set RLDQK90_RST and RDLCK_RST to reset all three DLLs.
+	    memcfg0.s.rldck_rst    = 1;
+	    memcfg0.s.rldqck90_rst = 1;
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  clk/qk90 reset\n", (uint32_t) memcfg0.u64);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64);
+
+	      // Clear RDLCK_RST while asserting RLDQK90_RST to bring RLDCK DLL out of reset.
+	    memcfg0.s.rldck_rst    = 0;
+	    memcfg0.s.rldqck90_rst = 1;
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64);
+            cvmx_wait(4000000);  /* Wait  */
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  qk90 reset\n", (uint32_t) memcfg0.u64);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64);
+
+	      // Clear both RDLCK90_RST and RLDQK90_RST to bring the RLDQK90 DLL out of reset.
+	    memcfg0.s.rldck_rst    = 0;
+	    memcfg0.s.rldqck90_rst = 0;
+	    cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64);
+            cvmx_wait(4000000);  /* Wait  */
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  DLL out of reset\n", (uint32_t) memcfg0.u64);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64);
+	}
+
+        //=======================================================================
+        // Now print out the sequence of events:
+        cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
+        ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  port enables\n", cfg_ptr->dfa_memcfg0_base);
+        cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
+        cvmx_wait(4000000);  /* Wait  */
+
+        cvmx_write_csr(CVMX_DFA_MEMCFG1, cfg_ptr->dfa_memcfg1_base);
+        ll_printf("CVMX_DFA_MEMCFG1: 0x%08x\n", cfg_ptr->dfa_memcfg1_base);
+        cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG1 & ~(1ull<<63), cfg_ptr->dfa_memcfg1_base);
+
+        if (cfg_ptr->p0_ena ==1)
+        {
+            cvmx_write_csr(CVMX_DFA_MEMRLD,  cfg_ptr->mrs_dat_p0bunk0);
+            ll_printf("CVMX_DFA_MEMRLD : 0x%08x  p0_ena memrld\n", cfg_ptr->mrs_dat_p0bunk0);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p0bunk0);
+
+            dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
+                            (1 << 23) |   // P0_INIT
+                            (1 << 25)     // BUNK_INIT[1:0]=Bunk#0
+                          );
+
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  p0_init/bunk_init\n", dfa_memcfg0);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
+            cvmx_wait(RLD_INIT_DELAY);
+            ll_printf("Delay.....\n");
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  back to base\n", cfg_ptr->dfa_memcfg0_base);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
+        }
+
+        if (cfg_ptr->p1_ena ==1)
+        {
+            cvmx_write_csr(CVMX_DFA_MEMRLD,  cfg_ptr->mrs_dat_p1bunk0);
+            ll_printf("CVMX_DFA_MEMRLD : 0x%08x  p1_ena memrld\n", cfg_ptr->mrs_dat_p1bunk0);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p1bunk0);
+
+            dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
+                            (1 << 24) |   // P1_INIT
+                            (1 << 25)     // BUNK_INIT[1:0]=Bunk#0
+                          );
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  p1_init/bunk_init\n", dfa_memcfg0);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
+            cvmx_wait(RLD_INIT_DELAY);
+            ll_printf("Delay.....\n");
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  back to base\n", cfg_ptr->dfa_memcfg0_base);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
+	}
+
+        // P0 Bunk#1
+        if ((cfg_ptr->p0_ena ==1) && (cfg_ptr->bunkport == 2))
+        {
+            cvmx_write_csr(CVMX_DFA_MEMRLD,  cfg_ptr->mrs_dat_p0bunk1);
+            ll_printf("CVMX_DFA_MEMRLD : 0x%08x  p0_ena memrld\n", cfg_ptr->mrs_dat_p0bunk1);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p0bunk1);
+
+            dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
+                            (1 << 23) |   // P0_INIT
+                            (2 << 25)     // BUNK_INIT[1:0]=Bunk#1
+                          );
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  p0_init/bunk_init\n", dfa_memcfg0);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
+            cvmx_wait(RLD_INIT_DELAY);
+            ll_printf("Delay.....\n");
+
+            if (cfg_ptr->p1_ena == 1)
+            { // Re-arm Px_INIT if P1-B1 init is required
+                cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
+                ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  px_init rearm\n", cfg_ptr->dfa_memcfg0_base);
+                cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
+            }
+        }
+
+        if ((cfg_ptr->p1_ena == 1) && (cfg_ptr->bunkport == 2))
+        {
+            cvmx_write_csr(CVMX_DFA_MEMRLD,  cfg_ptr->mrs_dat_p1bunk1);
+            ll_printf("CVMX_DFA_MEMRLD : 0x%08x  p1_ena memrld\n", cfg_ptr->mrs_dat_p1bunk1);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p1bunk1);
+
+            dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
+                            (1 << 24) |   // P1_INIT
+                            (2 << 25)     // BUNK_INIT[1:0]=10
+                          );
+            cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
+            ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  p1_init/bunk_init\n", dfa_memcfg0);
+            cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
+        }
+        cvmx_wait(4000000);  // 1/100S, 0.01S, 10mS
+        ll_printf("Delay.....\n");
+
+          /* Enable bunks */
+        dfa_memcfg0 = cfg_ptr->dfa_memcfg0_base |((cfg_ptr->bunkport >= 1) << 25) | ((cfg_ptr->bunkport == 2) << 26);
+        cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
+        ll_printf("CVMX_DFA_MEMCFG0: 0x%08x  enable bunks\n", dfa_memcfg0);
+        cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
+        cvmx_wait(RLD_INIT_DELAY);
+        ll_printf("Delay.....\n");
+
+          /* Issue a Silo reset by toggling SILRST in memcfg2. */
+        memcfg2.u64 = cvmx_read_csr (CVMX_DFA_MEMCFG2);
+        memcfg2.s.silrst = 1;
+	cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64);
+        ll_printf("CVMX_DFA_MEMCFG2: 0x%08x  silo reset start\n", (uint32_t) memcfg2.u64);
+        memcfg2.s.silrst = 0;
+	cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64);
+        ll_printf("CVMX_DFA_MEMCFG2: 0x%08x  silo reset done\n", (uint32_t) memcfg2.u64);
+    }
+}
+
diff --git a/cvmx-llm.h b/cvmx-llm.h
new file mode 100644
index 0000000000000..b1d1e1f32dfbe
--- /dev/null
+++ b/cvmx-llm.h
@@ -0,0 +1,401 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * interface to the low latency DRAM
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_LLM_H__
+#define __CVMX_LLM_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define ENABLE_DEPRECATED   /* Set to enable the old 18/36 bit names */
+
+typedef enum
+{
+    CVMX_LLM_REPLICATION_NONE = 0,
+    CVMX_LLM_REPLICATION_2X = 1, // on both interfaces, or 2x if only one interface
+    CVMX_LLM_REPLICATION_4X = 2, // both interfaces, 2x, or 4x if only one interface
+    CVMX_LLM_REPLICATION_8X = 3, // both interfaces, 4x,  or 8x if only one interface
+} cvmx_llm_replication_t;
+
+/**
+ * This structure defines the address used to the low-latency memory.
+ * This address format is used for both loads and stores.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t                mbz     :30;
+        cvmx_llm_replication_t  repl    : 2;
+        uint64_t                address :32; // address<1:0> mbz, address<31:30> mbz
+    } s;
+} cvmx_llm_address_t;
+
+/**
+ * This structure defines the data format in the low-latency memory
+ */
+typedef union
+{
+    uint64_t u64;
+
+    /**
+     * this format defines the format returned on a load
+     *   a load returns the 32/36-bits in memory, plus xxor = even_parity(dat<35:0>)
+     *   typically, dat<35> = parity(dat<34:0>), so the xor bit directly indicates parity error
+     *   Note that the data field size is 36 bits on the 36XX/38XX, and 32 bits on the 31XX
+     */
+    struct
+    {
+        uint64_t                       mbz1  :27;
+        uint64_t                       xxor  : 1;
+        uint64_t                       mbz   : 4;
+        uint64_t                       dat   :32;
+    } cn31xx;
+
+    struct
+    {
+        uint64_t                       mbz   :27;
+        uint64_t                       xxor  : 1;
+        uint64_t                       dat   :36;
+    } s;
+
+    /**
+     *  This format defines what should be used if parity is desired.  Hardware returns
+     *  the XOR of all the bits in the 36/32 bit data word, so for parity software must use
+     * one of the data field bits as a parity bit.
+     */
+    struct cn31xx_par_struct
+    {
+        uint64_t                       mbz   :32;
+        uint64_t                       par   : 1;
+        uint64_t                       dat   :31;
+    } cn31xx_par;
+    struct cn38xx_par_struct
+    {
+        uint64_t                       mbz   :28;
+        uint64_t                       par   : 1;
+        uint64_t                       dat   :35;
+    } cn38xx_par;
+#if !OCTEON_IS_COMMON_BINARY()
+#if CVMX_COMPILED_FOR(OCTEON_CN31XX)
+    struct cn31xx_par_struct spar;
+#else
+    struct cn38xx_par_struct spar;
+#endif
+#endif
+} cvmx_llm_data_t;
+
+#define CVMX_LLM_NARROW_DATA_WIDTH  ((CVMX_COMPILED_FOR(OCTEON_CN31XX)) ? 32 : 36)
+
+/**
+ * Calculate the parity value of a number
+ *
+ * @param value
+ * @return parity value
+ */
+static inline uint64_t cvmx_llm_parity(uint64_t value)
+{
+    uint64_t result;
+    CVMX_DPOP(result, value);
+    return result;
+}
+
+
+/**
+ * Calculate the ECC needed for 36b LLM mode
+ *
+ * @param value
+ * @return  ECC value
+ */
+static inline int cvmx_llm_ecc(uint64_t value)
+{
+    /* FIXME: This needs a re-write */
+    static const uint32_t ecc_code_29[7] = {
+        0x08962595,
+        0x112a4aaa,
+        0x024c934f,
+        0x04711c73,
+        0x0781e07c,
+        0x1801ff80,
+        0x1ffe0000};
+    uint64_t pop0, pop1, pop2, pop3, pop4, pop5, pop6;
+
+    pop0 = ecc_code_29[0];
+    pop1 = ecc_code_29[1];
+    pop2 = ecc_code_29[2];
+    pop0 &= value;
+    pop3 = ecc_code_29[3];
+    CVMX_DPOP(pop0, pop0);
+    pop4 = ecc_code_29[4];
+    pop1 &= value;
+    CVMX_DPOP(pop1, pop1);
+    pop2 &= value;
+    pop5 = ecc_code_29[5];
+    CVMX_DPOP(pop2, pop2);
+    pop6 = ecc_code_29[6];
+    pop3 &= value;
+    CVMX_DPOP(pop3, pop3);
+    pop4 &= value;
+    CVMX_DPOP(pop4, pop4);
+    pop5 &= value;
+    CVMX_DPOP(pop5, pop5);
+    pop6 &= value;
+    CVMX_DPOP(pop6, pop6);
+
+    return((pop6&1)<<6) | ((pop5&1)<<5) | ((pop4&1)<<4) | ((pop3&1)<<3) | ((pop2&1)<<2) | ((pop1&1)<<1) | (pop0&1);
+}
+
+
+#ifdef ENABLE_DEPRECATED
+/* These macros are provided to provide compatibility with code that uses
+** the old names for the llm access functions.  The names were changed
+** when support for the 31XX llm was added, as the widths differ between Octeon Models.
+** The wide/narrow names are preferred, and should be used in all new code */
+#define cvmx_llm_write36 cvmx_llm_write_narrow
+#define cvmx_llm_read36  cvmx_llm_read_narrow
+#define cvmx_llm_write64 cvmx_llm_write_wide
+#define cvmx_llm_read64  cvmx_llm_read_wide
+#endif
+/**
+ * Write to LLM memory - 36 bit
+ *
+ * @param address Address in LLM to write. Consecutive writes increment the
+ *                address by 4. The replication mode is also encoded in this
+ *                address.
+ * @param value   Value to write to LLM. Only the low 36 bits will be used.
+ * @param set     Which of the two coprocessor 2 register sets to use for the
+ *                write. May be used to get two outstanding LLM access at once
+ *                per core. Range: 0-1
+ */
+static inline void cvmx_llm_write_narrow(cvmx_llm_address_t address, uint64_t value, int set)
+{
+    cvmx_llm_data_t data;
+    data.s.mbz = 0;
+
+    if (cvmx_octeon_is_pass1())
+        data.s.dat = ((value & 0x3ffff) << 18) | ((value >> 18) & 0x3ffff);
+    else
+        data.s.dat = value;
+
+    data.s.xxor = 0;
+
+    if (set)
+    {
+        CVMX_MT_LLM_DATA(1, data.u64);
+        CVMX_MT_LLM_WRITE_ADDR_INTERNAL(1, address.u64);
+    }
+    else
+    {
+        CVMX_MT_LLM_DATA(0, data.u64);
+        CVMX_MT_LLM_WRITE_ADDR_INTERNAL(0, address.u64);
+    }
+}
+
+
+/**
+ * Write to LLM memory - 64 bit
+ *
+ * @param address Address in LLM to write. Consecutive writes increment the
+ *                address by 8. The replication mode is also encoded in this
+ *                address.
+ * @param value   Value to write to LLM.
+ * @param set     Which of the two coprocessor 2 register sets to use for the
+ *                write. May be used to get two outstanding LLM access at once
+ *                per core. Range: 0-1
+ */
+static inline void cvmx_llm_write_wide(cvmx_llm_address_t address, uint64_t value, int set)
+{
+    if (cvmx_octeon_is_pass1())
+    {
+        cvmx_llm_write36(address, value & 0xfffffffffull, set);
+        address.s.address+=4;
+        cvmx_llm_write36(address, ((value>>36) & 0xfffffff) | (cvmx_llm_ecc(value) << 28), set);
+    }
+    else
+    {
+        if (set)
+        {
+            CVMX_MT_LLM_DATA(1, value);
+            CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(1, address.u64);
+        }
+        else
+        {
+            CVMX_MT_LLM_DATA(0, value);
+            CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(0, address.u64);
+        }
+    }
+}
+
+
+/**
+ * Read from LLM memory - 36 bit
+ *
+ * @param address Address in LLM to read. Consecutive reads increment the
+ *                address by 4. The replication mode is also encoded in this
+ *                address.
+ * @param set     Which of the two coprocessor 2 register sets to use for the
+ *                write. May be used to get two outstanding LLM access at once
+ *                per core. Range: 0-1
+ * @return The lower 36 bits contain the result of the read
+ */
+static inline cvmx_llm_data_t cvmx_llm_read_narrow(cvmx_llm_address_t address, int set)
+{
+    cvmx_llm_data_t value;
+    if (set)
+    {
+        CVMX_MT_LLM_READ_ADDR(1, address.u64);
+        CVMX_MF_LLM_DATA(1, value.u64);
+    }
+    else
+    {
+        CVMX_MT_LLM_READ_ADDR(0, address.u64);
+        CVMX_MF_LLM_DATA(0, value.u64);
+    }
+    return value;
+}
+
+
+/**
+ * Read from LLM memory - 64 bit
+ *
+ * @param address Address in LLM to read. Consecutive reads increment the
+ *                address by 8. The replication mode is also encoded in this
+ *                address.
+ * @param set     Which of the two coprocessor 2 register sets to use for the
+ *                write. May be used to get two outstanding LLM access at once
+ *                per core. Range: 0-1
+ * @return The result of the read
+ */
+static inline uint64_t cvmx_llm_read_wide(cvmx_llm_address_t address, int set)
+{
+    uint64_t value;
+    if (set)
+    {
+        CVMX_MT_LLM_READ64_ADDR(1, address);
+        CVMX_MF_LLM_DATA(1, value);
+    }
+    else
+    {
+        CVMX_MT_LLM_READ64_ADDR(0, address);
+        CVMX_MF_LLM_DATA(0, value);
+    }
+    return value;
+}
+
+
+#define RLD_INIT_DELAY  (1<<18)
+
+
+
+/* This structure describes the RLDRAM configuration for a board.  This structure
+** must be populated with the correct values and passed to the initialization function.
+*/
+typedef struct
+{
+    uint32_t cpu_hz;            /* CPU frequency in Hz */
+    char addr_rld0_fb_str [100];   /* String describing RLDRAM connections on rld 0 front (0) bunk*/
+    char addr_rld0_bb_str [100];   /* String describing RLDRAM connections on rld 0 back (1) bunk*/
+    char addr_rld1_fb_str [100];   /* String describing RLDRAM connections on rld 1 front (0) bunk*/
+    char addr_rld1_bb_str [100];   /* String describing RLDRAM connections on rld 1 back (1) bunk*/
+    uint8_t rld0_bunks;     /* Number of bunks on rld 0 (0 is disabled) */
+    uint8_t rld1_bunks;     /* Number of bunks on rld 1 (0 is disabled) */
+    uint16_t rld0_mbytes;   /* mbytes on rld 0 */
+    uint16_t rld1_mbytes;   /* mbytes on rld 1 */
+    uint16_t max_rld_clock_mhz;  /* Maximum RLD clock in MHz, only used for CN58XX */
+} llm_descriptor_t;
+
+/**
+ * Initialize LLM memory controller.  This must be done
+ * before the low latency memory can be used.
+ * This is simply a wrapper around cvmx_llm_initialize_desc(),
+ * and is deprecated.
+ *
+ * @return -1 on error
+ *         0 on success
+ */
+int cvmx_llm_initialize(void);
+
+
+/**
+ * Initialize LLM memory controller.  This must be done
+ * before the low latency memory can be used.
+ *
+ * @param llm_desc_ptr
+ *              Pointer to descriptor structure. If NULL
+ *              is passed, a default setting is used if available.
+ *
+ * @return -1 on error
+ *         Size of llm in bytes on success
+ */
+int cvmx_llm_initialize_desc(llm_descriptor_t *llm_desc_ptr);
+
+
+
+/**
+ * Gets the default llm descriptor for the board code is being run on.
+ *
+ * @param llm_desc_ptr
+ *               Pointer to descriptor structure to be filled in.  Contents are only
+ *               valid after successful completion.  Must not be NULL.
+ *
+ * @return -1 on error
+ *         0 on success
+ */
+int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /*  __CVM_LLM_H__ */
diff --git a/cvmx-lmc.h b/cvmx-lmc.h
new file mode 100644
index 0000000000000..54cda6a6efd27
--- /dev/null
+++ b/cvmx-lmc.h
@@ -0,0 +1,66 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Memory controller interface.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_ASX_H__
+#define __CVMX_ASX_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-log-arc.S b/cvmx-log-arc.S
new file mode 100644
index 0000000000000..c60462b7726bd
--- /dev/null
+++ b/cvmx-log-arc.S
@@ -0,0 +1,176 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+//
+// The function defined here is called for every function as it is executed.
+// These calls are automatically inserted by GCC when the switch "-pg" is
+// used. This allows cvmx-log to add a PC entry as each function is executed.
+// This information, along with the timestamps can give the user a good idea
+// of the performance characteristics of their program. This function normally
+// takes about 22 cycles to execute.
+//
+
+#ifdef __linux__
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#define LA dla
+#else
+#include <machine/asm.h>
+#include <machine/regdef.h>
+#define LA la
+#endif
+
+.set noreorder
+.set noat
+LEAF(_mcount)
+	//
+	// All registers we use must be saved since calls are added by gcc
+	// after register allocation. The at register ($3) will contain the
+	// original ra register before the _mcount call. Also the compiler
+	// automatically performs a "dsubu sp, sp, 16" before we're called.
+	// At the end of this function all registers must have their original
+	// values and the stack pointr must be adjusted by 16. This code is
+	// pretty unreadable since it has been arranged to promote dual issue.
+	//
+#ifdef __linux__
+	dsubu	sp, sp, 32
+#else
+	dsubu	sp, sp, 16
+#endif
+	sd	s3, 24(sp)				// Save register
+	rdhwr	s3, $31					// Read the cycle count
+	sd	s0, 0(sp)				// Save register
+	LA	s0, cvmx_log_buffer_end_ptr		// Load the address of the end of the log buffer
+	sd	s1, 8(sp)				// Save register
+	LA	s1, cvmx_log_buffer_write_ptr		// Load the address of the location in the log buffer
+	sd	s2, 16(sp)				// Save register
+	ld	s0, 0(s0)				// Get value of the current log buffer end location
+	ld	s2, 0(s1)				// Get value of the current log buffer location
+	dsubu	s0, s0, s2				// Subtract the end pointer and the write pointer
+	sltiu	s0, s0, 16				// Check if there are at least 16 bytes
+	bne	s0, $0, call_c_pc			// Call the slow C function if we don't have room in the log
+	li	s0, 0x001				// 11 bit constant that matches the first 11 bits of a CVMX_LOG_TYPE_PC header
+	sd	ra, 8(s2)				// Write the pc to the log
+	dins	s3, s0, 53, 11				// Overwrite the upper cycle count bits with the CVMX_LOG_TYPE_PC header
+	sd	s3, 0(s2)				// Write the log header
+	daddu	s2, s2, 16				// Increment the write location ptr
+	sd	s2, 0(s1)				// Store the write location ptr
+return_c_pc:
+	ld	s0, 0(sp)				// Restore register
+	ld	s1, 8(sp)				// Restore register
+	ld	s2, 16(sp)				// Restore register
+	ld	s3, 24(sp)				// Restore register
+	daddu	sp, sp, 32				// Pop everything off the stack, even the 16 bytes done by gcc
+	jr	ra					// Return to the caller and
+	or	ra, $1, $1				// make sure the ra is back to its original value
+
+call_c_pc:
+	// The registers used by the C code may change based on optimizations. To be
+	// safe, I'll save all registers. We're in the slow path case anyway.
+	dsubu	sp, sp, 216
+	sd	$1, 0(sp)
+	sd	$2, 8(sp)
+	sd	$3, 16(sp)
+	sd 	$4, 24(sp)
+	sd 	$5, 32(sp)
+	sd	$6, 40(sp)
+	sd	$7, 48(sp)
+	sd	$8, 56(sp)
+	sd	$9, 64(sp)
+	sd	$10, 72(sp)
+	sd	$11, 80(sp)
+	sd	$12, 88(sp)
+	sd	$13, 96(sp)
+	sd	$14, 104(sp)
+	sd	$15, 112(sp)
+	// s0, s1, s2, s3 are already saved
+	sd	$20, 120(sp)
+	sd	$21, 128(sp)
+	sd	$22, 136(sp)
+	sd	$23, 144(sp)
+	sd	$24, 152(sp)
+	sd	$25, 160(sp)
+	sd	$26, 168(sp)
+	sd	$27, 176(sp)
+	sd	$28, 184(sp)
+	sd	$29, 192(sp)
+	sd	$30, 200(sp)
+	sd	$31, 208(sp)
+
+	or	a0, ra, ra
+	jal	cvmx_log_pc
+	nop
+
+	ld	$1, 0(sp)
+	ld	$2, 8(sp)
+	ld	$3, 16(sp)
+	ld 	$4, 24(sp)
+	ld 	$5, 32(sp)
+	ld	$6, 40(sp)
+	ld	$7, 48(sp)
+	ld	$8, 56(sp)
+	ld	$9, 64(sp)
+	ld	$10, 72(sp)
+	ld	$11, 80(sp)
+	ld	$12, 88(sp)
+	ld	$13, 96(sp)
+	ld	$14, 104(sp)
+	ld	$15, 112(sp)
+	// s0, s1, s2, s3 will be restored later
+	ld	$20, 120(sp)
+	ld	$21, 128(sp)
+	ld	$22, 136(sp)
+	ld	$23, 144(sp)
+	ld	$24, 152(sp)
+	ld	$25, 160(sp)
+	ld	$26, 168(sp)
+	ld	$27, 176(sp)
+	ld	$28, 184(sp)
+	ld	$29, 192(sp)
+	ld	$30, 200(sp)
+	ld	$31, 208(sp)
+	b	return_c_pc
+	daddu	sp, sp, 216
+
+END(_mcount)
+
diff --git a/cvmx-log.c b/cvmx-log.c
new file mode 100644
index 0000000000000..b3aeb90b2619b
--- /dev/null
+++ b/cvmx-log.c
@@ -0,0 +1,536 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * cvmx-log supplies a fast log buffer implementation. Each core writes
+ * log data to a differnet buffer to avoid synchronization overhead. Function
+ * call logging can be turned on with the GCC option "-pg".
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-log.h"
+
+#define CVMX_LOG_BUFFER_SIZE (1<<15)
+#define CVMX_LOG_NUM_BUFFERS 4
+
+/**
+ * The possible types of log data that can be stored in the
+ * buffer.
+ */
+typedef enum
+{
+    CVMX_LOG_TYPE_PC = 0,   /**< Log of the program counter location. used for code profiling / tracing */
+    CVMX_LOG_TYPE_PRINTF,   /**< Constant printf format string with two 64bit arguments */
+    CVMX_LOG_TYPE_DATA,     /**< Arbitrary array of dwords. Max size is 31 dwords */
+    CVMX_LOG_TYPE_STRUCTURE,/**< Log a structured data element. Max size is 30 dwords */
+    CVMX_LOG_TYPE_PERF,     /**< Mips performance counters control registers followed by the data */
+} cvmx_log_type_t;
+
+/**
+ * Header definition for each log entry.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        cvmx_log_type_t     type    : 3; /* Data in the log entry */
+        uint64_t            size    : 8; /* Data size in 64bit words */
+        uint64_t            cycle   :53; /* Low bits of the cycle counter as a timestamp */
+    } s;
+} cvmx_log_header_t;
+
+/**
+ * Circular log buffer. Each processor gets a private one to
+ * write to. Log entries are added at the current write
+ * location, then the write location is incremented. The
+ * buffer may wrap in the middle of a log entry.
+ */
+static uint64_t cvmx_log_buffers[CVMX_LOG_NUM_BUFFERS][CVMX_LOG_BUFFER_SIZE];
+
+/**
+ * Current locations in the log.
+ */
+uint64_t *cvmx_log_buffer_write_ptr             = NULL; /* The next write will occur here */
+uint64_t *cvmx_log_buffer_end_ptr               = NULL; /* Write must move to the next buffer when it equals this */
+uint64_t *cvmx_log_buffer_head_ptr              = NULL; /* Pointer to begin extracting log data from */
+static uint64_t *cvmx_log_buffer_read_ptr       = NULL; /* Location cvmx_display is reading from */
+static uint64_t *cvmx_log_buffer_read_end_ptr   = NULL; /* Location where read will need the next buffer */
+uint64_t cvmx_log_mcd0_on_full                  = 0;    /* If this is set, cvm-log will assert MCD0 when the log
+                                                            is full. This is set by the remote logging utility through
+                                                            the debugger interface. */
+
+
+/**
+ * @INTERNAL
+ * Initialize the log for writing
+ */
+static void __cvmx_log_initialize(void) CVMX_LOG_DISABLE_PC_LOGGING;
+static void __cvmx_log_initialize(void)
+{
+    int buf_num;
+
+    /* Link the buffers together using the last element in each buffer */
+    for (buf_num=0; buf_num<CVMX_LOG_NUM_BUFFERS-1; buf_num++)
+        cvmx_log_buffers[buf_num][CVMX_LOG_BUFFER_SIZE-1] = CAST64(cvmx_log_buffers[buf_num+1]);
+    cvmx_log_buffers[CVMX_LOG_NUM_BUFFERS-1][CVMX_LOG_BUFFER_SIZE-1] = CAST64(NULL);
+
+    cvmx_log_buffer_head_ptr = &cvmx_log_buffers[0][0];
+    cvmx_log_buffer_write_ptr = &cvmx_log_buffers[0][0];
+    cvmx_log_buffer_end_ptr = cvmx_log_buffer_write_ptr + CVMX_LOG_BUFFER_SIZE-1;
+}
+
+
+/**
+ * @INTERNAL
+ * Called when the log is full of data. This function must
+ * make room for more log data before returning.
+ */
+static void __cvmx_log_full_process(void) CVMX_LOG_DISABLE_PC_LOGGING;
+static void __cvmx_log_full_process(void)
+{
+    if (cvmx_log_mcd0_on_full)
+    {
+        register uint64_t tmp;
+        /* Pulse MCD0 signal so a remote utility can extract the data */
+        asm volatile (
+            "dmfc0 %0, $22\n"
+	        "ori   %0, %0, 0x1110\n"
+            "dmtc0 %0, $22\n"
+            "nop\n"
+            "nop\n"
+            "nop\n"
+            "nop\n"
+            "nop\n"
+            "nop\n"
+            : "=r" (tmp));
+    }
+    /* The write ptr may have been modifed by the debugger, check it again */
+    if (!(volatile uint64_t)CAST64(cvmx_log_buffer_write_ptr))
+    {
+        #ifndef __KERNEL__
+            /* Disabled for the Linux kernel since printk is also profiled */
+            cvmx_dprintf("Log is full, reusing first buffer\n");
+        #endif
+        *cvmx_log_buffer_end_ptr = CAST64(cvmx_log_buffer_head_ptr);
+        cvmx_log_buffer_write_ptr = cvmx_log_buffer_head_ptr;
+        cvmx_log_buffer_end_ptr = cvmx_log_buffer_write_ptr + CVMX_LOG_BUFFER_SIZE-1;
+        cvmx_log_buffer_head_ptr = CASTPTR(uint64_t, *cvmx_log_buffer_end_ptr);
+        *cvmx_log_buffer_end_ptr = CAST64(NULL);
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Simple inline function to build a log header
+ *
+ * @param type   Type of header to build
+ * @param size   Amount of data that follows the header in dwords
+ * @return The header
+ */
+static inline uint64_t __cvmx_log_build_header(cvmx_log_type_t type, uint64_t size) CVMX_LOG_DISABLE_PC_LOGGING;
+static inline uint64_t __cvmx_log_build_header(cvmx_log_type_t type, uint64_t size)
+{
+    cvmx_log_header_t header;
+    header.u64 = 0;
+    header.s.type = type;
+    header.s.size = size;
+    header.s.cycle = cvmx_get_cycle();
+    return header.u64;
+}
+
+
+/**
+ * @INTERNAL
+ * Function to write and increment the position. It rotates
+ * to the next log buffer as necessary.
+ *
+ * @param data   Data to write to the log
+ */
+static inline void __cvmx_log_write(uint64_t data) CVMX_LOG_DISABLE_PC_LOGGING;
+static inline void __cvmx_log_write(uint64_t data)
+{
+    /* Check and see if we need to rotate the log */
+    if (cvmx_likely(cvmx_log_buffer_write_ptr != cvmx_log_buffer_end_ptr))
+    {
+        /* No rotate is necessary, just write the data */
+        *cvmx_log_buffer_write_ptr++ = data;
+    }
+    else
+    {
+        /* Initialize the log if necessary */
+        if (cvmx_unlikely(cvmx_log_buffer_head_ptr == NULL))
+            __cvmx_log_initialize();
+        else
+        {
+            cvmx_log_buffer_write_ptr = CASTPTR(uint64_t, *cvmx_log_buffer_end_ptr);
+            if (cvmx_likely(cvmx_log_buffer_write_ptr))
+            {
+                /* Rotate the log. Might be a good time to send the old buffer
+                    somewhere */
+                cvmx_log_buffer_end_ptr = cvmx_log_buffer_write_ptr + CVMX_LOG_BUFFER_SIZE-1;
+            }
+            else
+                __cvmx_log_full_process();    /* After this function returns, the log must be ready for updates */
+        }
+        *cvmx_log_buffer_write_ptr++ = data;
+    }
+}
+
+
+/**
+ * Log a program counter address to the log. This is caused by
+ * the assembly code function mcount when writing the PC value
+ * is more complicated that the simple case support by it.
+ *
+ * @param pc     Program counter address to log
+ */
+void cvmx_log_pc(uint64_t pc) CVMX_LOG_DISABLE_PC_LOGGING;
+void cvmx_log_pc(uint64_t pc)
+{
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PC, 1));
+    __cvmx_log_write(pc);
+}
+
+
+/**
+ * Log a constant printf style format string with 0 to 4
+ * arguments. The string must persist until the log is read,
+ * but the parameters are copied into the log.
+ *
+ * @param format  Constant printf style format string.
+ */
+void cvmx_log_printf0(const char *format)
+{
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PRINTF, 1));
+    __cvmx_log_write(CAST64(format));
+}
+
+
+/**
+ * Log a constant printf style format string with 0 to 4
+ * arguments. The string must persist until the log is read,
+ * but the parameters are copied into the log.
+ *
+ * @param format  Constant printf style format string.
+ * @param number1 64bit argument to the printf format string
+ */
+void cvmx_log_printf1(const char *format, uint64_t number1)
+{
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PRINTF, 2));
+    __cvmx_log_write(CAST64(format));
+    __cvmx_log_write(number1);
+}
+
+
+/**
+ * Log a constant printf style format string with 0 to 4
+ * arguments. The string must persist until the log is read,
+ * but the parameters are copied into the log.
+ *
+ * @param format  Constant printf style format string.
+ * @param number1 64bit argument to the printf format string
+ * @param number2 64bit argument to the printf format string
+ */
+void cvmx_log_printf2(const char *format, uint64_t number1, uint64_t number2)
+{
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PRINTF, 3));
+    __cvmx_log_write(CAST64(format));
+    __cvmx_log_write(number1);
+    __cvmx_log_write(number2);
+}
+
+
+/**
+ * Log a constant printf style format string with 0 to 4
+ * arguments. The string must persist until the log is read,
+ * but the parameters are copied into the log.
+ *
+ * @param format  Constant printf style format string.
+ * @param number1 64bit argument to the printf format string
+ * @param number2 64bit argument to the printf format string
+ * @param number3 64bit argument to the printf format string
+ */
+void cvmx_log_printf3(const char *format, uint64_t number1, uint64_t number2, uint64_t number3)
+{
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PRINTF, 4));
+    __cvmx_log_write(CAST64(format));
+    __cvmx_log_write(number1);
+    __cvmx_log_write(number2);
+    __cvmx_log_write(number3);
+}
+
+
+/**
+ * Log a constant printf style format string with 0 to 4
+ * arguments. The string must persist until the log is read,
+ * but the parameters are copied into the log.
+ *
+ * @param format  Constant printf style format string.
+ * @param number1 64bit argument to the printf format string
+ * @param number2 64bit argument to the printf format string
+ * @param number3 64bit argument to the printf format string
+ * @param number4 64bit argument to the printf format string
+ */
+void cvmx_log_printf4(const char *format, uint64_t number1, uint64_t number2, uint64_t number3, uint64_t number4)
+{
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PRINTF, 5));
+    __cvmx_log_write(CAST64(format));
+    __cvmx_log_write(number1);
+    __cvmx_log_write(number2);
+    __cvmx_log_write(number3);
+    __cvmx_log_write(number4);
+}
+
+
+/**
+ * Log an arbitrary block of 64bit words. At most 255 64bit
+ * words can be logged. The words are copied into the log.
+ *
+ * @param size_in_dwords
+ *               Number of 64bit dwords to copy into the log.
+ * @param data   Array of 64bit dwords to copy
+ */
+void cvmx_log_data(uint64_t size_in_dwords, const uint64_t *data)
+{
+    if (size_in_dwords > 255)
+        size_in_dwords = 255;
+
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_DATA, size_in_dwords));
+    while (size_in_dwords--)
+        __cvmx_log_write(*data++);
+}
+
+
+/**
+ * Log a structured data object. Post processing will use the
+ * debugging information in the ELF file to determine how to
+ * display the structure. Max of 2032 bytes.
+ *
+ * Example:
+ * cvmx_log_structure("cvmx_wqe_t", work, sizeof(*work));
+ *
+ * @param type   C typedef expressed as a string. This will be used to
+ *               lookup the structure in the debugging infirmation.
+ * @param data   Data to be written to the log.
+ * @param size_in_bytes
+ *               Size if the data in bytes. Normally you'll use the
+ *               sizeof() operator here.
+ */
+void cvmx_log_structure(const char *type, void *data, int size_in_bytes)
+{
+    uint64_t size_in_dwords = (size_in_bytes + 7) >> 3;
+    uint64_t *ptr = (uint64_t*)data;
+
+    if (size_in_dwords > 254)
+        size_in_dwords = 254;
+
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_STRUCTURE, size_in_dwords + 1));
+    __cvmx_log_write(CAST64(type));
+    while (size_in_dwords--)
+        __cvmx_log_write(*ptr++);
+}
+
+
+/**
+ * Setup the mips performance counters
+ *
+ * @param counter1 Event type for counter 1
+ * @param counter2 Event type for counter 2
+ */
+void cvmx_log_perf_setup(cvmx_log_perf_event_t counter1, cvmx_log_perf_event_t counter2)
+{
+    cvmx_log_perf_control_t control;
+
+    control.u32 = 0;
+    control.s.event = counter1;
+    control.s.U = 1;
+    control.s.S = 1;
+    control.s.K = 1;
+    control.s.EX = 1;
+    asm ("mtc0 %0, $25, 0\n" : : "r"(control.u32));
+    control.s.event = counter2;
+    asm ("mtc0 %0, $25, 2\n" : : "r"(control.u32));
+}
+
+
+/**
+ * Log the performance counters
+ */
+void cvmx_log_perf(void)
+{
+    uint64_t control1;
+    uint64_t control2;
+    uint64_t data1;
+    uint64_t data2;
+    asm ("dmfc0 %0, $25, 1\n" : "=r"(data1));
+    asm ("dmfc0 %0, $25, 3\n" : "=r"(data2));
+    asm ("mfc0 %0, $25, 0\n" : "=r"(control1));
+    asm ("mfc0 %0, $25, 2\n" : "=r"(control2));
+    __cvmx_log_write(__cvmx_log_build_header(CVMX_LOG_TYPE_PERF, 3));
+    __cvmx_log_write(((control1 & 0xffffffff) << 32) | (control2 & 0xffffffff));
+    __cvmx_log_write(data1);
+    __cvmx_log_write(data2);
+}
+
+
+/**
+ * @INTERNAL
+ * Read a dword from the log
+ *
+ * @return the dword
+ */
+static uint64_t __cvmx_log_read(void) CVMX_LOG_DISABLE_PC_LOGGING;
+static uint64_t __cvmx_log_read(void)
+{
+    uint64_t data;
+
+    /* Check and see if we need to rotate the log */
+    if (cvmx_likely(cvmx_log_buffer_read_ptr != cvmx_log_buffer_read_end_ptr))
+    {
+        /* No rotate is necessary, just read the data */
+        data = *cvmx_log_buffer_read_ptr++;
+    }
+    else
+    {
+        cvmx_log_buffer_read_ptr = CASTPTR(uint64_t, *cvmx_log_buffer_read_end_ptr);
+        if (cvmx_likely(cvmx_log_buffer_read_ptr))
+        {
+            /* Rotate to the next log buffer */
+            cvmx_log_buffer_read_end_ptr = cvmx_log_buffer_read_ptr + CVMX_LOG_BUFFER_SIZE-1;
+            data = *cvmx_log_buffer_read_ptr++;
+        }
+        else
+        {
+            /* No more log buffers, return 0 */
+            cvmx_log_buffer_read_end_ptr = NULL;
+            data = 0;
+        }
+    }
+
+    return data;
+}
+
+
+/**
+ * Display the current log in a human readable format.
+ */
+void cvmx_log_display(void)
+{
+    unsigned int i;
+    cvmx_log_header_t header;
+
+    cvmx_log_buffer_read_ptr = cvmx_log_buffer_head_ptr;
+    cvmx_log_buffer_read_end_ptr = cvmx_log_buffer_read_ptr + CVMX_LOG_BUFFER_SIZE-1;
+
+    while (cvmx_log_buffer_read_ptr && (cvmx_log_buffer_read_ptr != cvmx_log_buffer_write_ptr))
+    {
+        header.u64 = __cvmx_log_read();
+        if (header.s.cycle == 0)
+            continue;
+        printf("%llu: ", (unsigned long long)header.s.cycle);
+        switch (header.s.type)
+        {
+            case CVMX_LOG_TYPE_PC:
+                if (header.s.size == 1)
+                    printf("pc 0x%016llx\n", (unsigned long long)__cvmx_log_read());
+                else
+                    printf("Illegal size (%d) for log entry: pc\n", header.s.size);
+                break;
+            case CVMX_LOG_TYPE_PRINTF:
+                switch (header.s.size)
+                {
+                    case 1:
+                        printf(CASTPTR(const char, __cvmx_log_read()));
+                        break;
+                    case 2:
+                        printf(CASTPTR(const char, __cvmx_log_read()), __cvmx_log_read());
+                        break;
+                    case 3:
+                        printf(CASTPTR(const char, __cvmx_log_read()), __cvmx_log_read(), __cvmx_log_read());
+                        break;
+                    case 4:
+                        printf(CASTPTR(const char, __cvmx_log_read()), __cvmx_log_read(), __cvmx_log_read(), __cvmx_log_read());
+                        break;
+                    case 5:
+                        printf(CASTPTR(const char, __cvmx_log_read()), __cvmx_log_read(), __cvmx_log_read(), __cvmx_log_read(), __cvmx_log_read());
+                        break;
+                    default:
+                        printf("Illegal size (%d) for log entry: printf\n", header.s.size);
+                        break;
+                }
+                printf("\n");
+                break;
+            case CVMX_LOG_TYPE_DATA:
+                printf("data");
+                for (i=0; i<header.s.size; i++)
+                    printf(" 0x%016llx", (unsigned long long)__cvmx_log_read());
+                printf("\n");
+                break;
+            case CVMX_LOG_TYPE_STRUCTURE:
+                printf("struct %s", CASTPTR(const char, __cvmx_log_read()));
+                for (i=1; i<header.s.size; i++)
+                    printf(" 0x%016llx", (unsigned long long)__cvmx_log_read());
+                printf("\n");
+                break;
+            case CVMX_LOG_TYPE_PERF:
+                if (header.s.size == 3)
+                {
+                    unsigned long long control = __cvmx_log_read();
+                    unsigned long long data1 = __cvmx_log_read();
+                    unsigned long long data2 = __cvmx_log_read();
+                    printf("perf control=0x%016llx data1=0x%016llx data2=0x%016llx\n", control, data1, data2);
+                }
+                else
+                    printf("Illegal size (%d) for log entry: perf\n", header.s.size);
+                break;
+            default:
+                break;
+        }
+    }
+}
+
diff --git a/cvmx-log.h b/cvmx-log.h
new file mode 100644
index 0000000000000..8b6e4c5fd38e6
--- /dev/null
+++ b/cvmx-log.h
@@ -0,0 +1,212 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+#ifndef __CVMX_LOG_H__
+#define __CVMX_LOG_H__
+
+/**
+ * @file
+ *
+ * cvmx-log supplies a fast log buffer implementation. Each core writes
+ * log data to a differnet buffer to avoid synchronization overhead. Function
+ * call logging can be turned on with the GCC option "-pg".
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of all supported performance counter types
+ */
+typedef enum
+{
+    CVMX_LOG_PERF_CNT_NONE      = 0,    /**< Turn off the performance counter */
+    CVMX_LOG_PERF_CNT_CLK       = 1,    /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */
+    CVMX_LOG_PERF_CNT_ISSUE     = 2,    /**< Instructions issued but not retired */
+    CVMX_LOG_PERF_CNT_RET       = 3,    /**< Instructions retired */
+    CVMX_LOG_PERF_CNT_NISSUE    = 4,    /**< Cycles no issue */
+    CVMX_LOG_PERF_CNT_SISSUE    = 5,    /**< Cycles single issue */
+    CVMX_LOG_PERF_CNT_DISSUE    = 6,    /**< Cycles dual issue */
+    CVMX_LOG_PERF_CNT_IFI       = 7,    /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */
+    CVMX_LOG_PERF_CNT_BR        = 8,    /**< Branches retired */
+    CVMX_LOG_PERF_CNT_BRMIS     = 9,    /**< Branch mispredicts */
+    CVMX_LOG_PERF_CNT_J         = 10,   /**< Jumps retired */
+    CVMX_LOG_PERF_CNT_JMIS      = 11,   /**< Jumps mispredicted */
+    CVMX_LOG_PERF_CNT_REPLAY    = 12,   /**< Mem Replays */
+    CVMX_LOG_PERF_CNT_IUNA      = 13,   /**< Cycles idle due to unaligned_replays */
+    CVMX_LOG_PERF_CNT_TRAP      = 14,   /**< trap_6a signal */
+    CVMX_LOG_PERF_CNT_UULOAD    = 16,   /**< Unexpected unaligned loads (REPUN=1) */
+    CVMX_LOG_PERF_CNT_UUSTORE   = 17,   /**< Unexpected unaligned store (REPUN=1) */
+    CVMX_LOG_PERF_CNT_ULOAD     = 18,   /**< Unaligned loads (REPUN=1 or USEUN=1) */
+    CVMX_LOG_PERF_CNT_USTORE    = 19,   /**< Unaligned store (REPUN=1 or USEUN=1) */
+    CVMX_LOG_PERF_CNT_EC        = 20,   /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_LOG_PERF_CNT_MC        = 21,   /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_LOG_PERF_CNT_CC        = 22,   /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_LOG_PERF_CNT_CSRC      = 23,   /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_LOG_PERF_CNT_CFETCH    = 24,   /**< Icache committed fetches (demand+prefetch) */
+    CVMX_LOG_PERF_CNT_CPREF     = 25,   /**< Icache committed prefetches */
+    CVMX_LOG_PERF_CNT_ICA       = 26,   /**< Icache aliases */
+    CVMX_LOG_PERF_CNT_II        = 27,   /**< Icache invalidates */
+    CVMX_LOG_PERF_CNT_IP        = 28,   /**< Icache parity error */
+    CVMX_LOG_PERF_CNT_CIMISS    = 29,   /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */
+    CVMX_LOG_PERF_CNT_WBUF      = 32,   /**< Number of write buffer entries created */
+    CVMX_LOG_PERF_CNT_WDAT      = 33,   /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_LOG_PERF_CNT_WBUFLD    = 34,   /**< Number of write buffer entries forced out by loads */
+    CVMX_LOG_PERF_CNT_WBUFFL    = 35,   /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
+    CVMX_LOG_PERF_CNT_WBUFTR    = 36,   /**< Number of stores that found no available write buffer entries */
+    CVMX_LOG_PERF_CNT_BADD      = 37,   /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_LOG_PERF_CNT_BADDL2    = 38,   /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_LOG_PERF_CNT_BFILL     = 39,   /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_LOG_PERF_CNT_DDIDS     = 40,   /**< Number of Dstream DIDs created */
+    CVMX_LOG_PERF_CNT_IDIDS     = 41,   /**< Number of Istream DIDs created */
+    CVMX_LOG_PERF_CNT_DIDNA     = 42,   /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
+    CVMX_LOG_PERF_CNT_LDS       = 43,   /**< Number of load issues */
+    CVMX_LOG_PERF_CNT_LMLDS     = 44,   /**< Number of local memory load */
+    CVMX_LOG_PERF_CNT_IOLDS     = 45,   /**< Number of I/O load issues */
+    CVMX_LOG_PERF_CNT_DMLDS     = 46,   /**< Number of loads that were not prefetches and missed in the cache */
+    CVMX_LOG_PERF_CNT_STS       = 48,   /**< Number of store issues */
+    CVMX_LOG_PERF_CNT_LMSTS     = 49,   /**< Number of local memory store issues */
+    CVMX_LOG_PERF_CNT_IOSTS     = 50,   /**< Number of I/O store issues */
+    CVMX_LOG_PERF_CNT_IOBDMA    = 51,   /**< Number of IOBDMAs */
+    CVMX_LOG_PERF_CNT_DTLB      = 53,   /**< Number of dstream TLB refill, invalid, or modified exceptions */
+    CVMX_LOG_PERF_CNT_DTLBAD    = 54,   /**< Number of dstream TLB address errors */
+    CVMX_LOG_PERF_CNT_ITLB      = 55,   /**< Number of istream TLB refill, invalid, or address error exceptions */
+    CVMX_LOG_PERF_CNT_SYNC      = 56,   /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_LOG_PERF_CNT_SYNCIOB   = 57,   /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
+    CVMX_LOG_PERF_CNT_SYNCW     = 58,   /**< Number of SYNCWs */
+} cvmx_log_perf_event_t;
+
+/**
+ * Structure of the performance counter control register
+ */
+typedef union
+{
+    uint32_t u32;
+    struct
+    {
+        uint32_t                M       : 1;
+        uint32_t                W       : 1;
+        uint32_t                reserved: 19;
+        cvmx_log_perf_event_t   event   : 6;
+        uint32_t                IE      : 1;
+        uint32_t                U       : 1;
+        uint32_t                S       : 1;
+        uint32_t                K       : 1;
+        uint32_t                EX      : 1;
+    } s;
+} cvmx_log_perf_control_t;
+
+/*
+ * Add CVMX_LOG_DISABLE_PC_LOGGING as an attribute to and function prototype
+ * that you don't want logged when the gcc option "-pg" is supplied. We
+ * use it on the cvmx-log functions since it is pointless to log the
+ * calling of a function than in itself writes to the log.
+ */
+#define CVMX_LOG_DISABLE_PC_LOGGING __attribute__((no_instrument_function))
+
+/**
+ * Log a constant printf style format string with 0 to 4
+ * arguments. The string must persist until the log is read,
+ * but the parameters are copied into the log.
+ *
+ * @param format  Constant printf style format string.
+ * @param numberx 64bit argument to the printf format string
+ */
+void cvmx_log_printf0(const char *format) CVMX_LOG_DISABLE_PC_LOGGING;
+void cvmx_log_printf1(const char *format, uint64_t number1) CVMX_LOG_DISABLE_PC_LOGGING;
+void cvmx_log_printf2(const char *format, uint64_t number1, uint64_t number2) CVMX_LOG_DISABLE_PC_LOGGING;
+void cvmx_log_printf3(const char *format, uint64_t number1, uint64_t number2, uint64_t number3) CVMX_LOG_DISABLE_PC_LOGGING;
+void cvmx_log_printf4(const char *format, uint64_t number1, uint64_t number2, uint64_t number3, uint64_t number4) CVMX_LOG_DISABLE_PC_LOGGING;
+
+/**
+ * Log an arbitrary block of 64bit words. At most 255 64bit
+ * words can be logged. The words are copied into the log.
+ *
+ * @param size_in_dwords
+ *               Number of 64bit dwords to copy into the log.
+ * @param data   Array of 64bit dwords to copy
+ */
+void cvmx_log_data(uint64_t size_in_dwords, const uint64_t *data) CVMX_LOG_DISABLE_PC_LOGGING;
+
+/**
+ * Log a structured data object. Post processing will use the
+ * debugging information in the ELF file to determine how to
+ * display the structure. Max of 2032 bytes.
+ *
+ * Example:
+ * cvmx_log_structure("cvmx_wqe_t", work, sizeof(*work));
+ *
+ * @param type   C typedef expressed as a string. This will be used to
+ *               lookup the structure in the debugging infirmation.
+ * @param data   Data to be written to the log.
+ * @param size_in_bytes
+ *               Size if the data in bytes. Normally you'll use the
+ *               sizeof() operator here.
+ */
+void cvmx_log_structure(const char *type, void *data, int size_in_bytes) CVMX_LOG_DISABLE_PC_LOGGING;
+
+/**
+ * Setup the mips performance counters
+ *
+ * @param counter1 Event type for counter 1
+ * @param counter2 Event type for counter 2
+ */
+void cvmx_log_perf_setup(cvmx_log_perf_event_t counter1, cvmx_log_perf_event_t counter2);
+
+/**
+ * Log the performance counters
+ */
+void cvmx_log_perf(void) CVMX_LOG_DISABLE_PC_LOGGING;
+
+/**
+ * Display the current log in a human readable format.
+ */
+void cvmx_log_display(void);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/cvmx-malloc.h b/cvmx-malloc.h
new file mode 100644
index 0000000000000..bb21a285583a8
--- /dev/null
+++ b/cvmx-malloc.h
@@ -0,0 +1,219 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides prototypes for the memory management library functions.
+ * Two different allocators are provided: an arena based allocator that is derived from a
+ * modified version of ptmalloc2 (used in glibc), and a zone allocator for allocating fixed
+ * size memory blocks.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_MALLOC_H__
+#define __CVMX_MALLOC_H__
+
+#include "cvmx-spinlock.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+struct malloc_state; /* forward declaration */
+typedef struct malloc_state *cvmx_arena_list_t;
+
+
+/**
+ * Creates an arena from the memory region specified and adds it
+ * to the supplied arena list.
+ *
+ * @param arena_list Pointer to an arena list to add new arena to.
+ *                   If NULL, new list is created.
+ * @param ptr        pointer to memory region to create arena from
+ *
+ * @param size       Size of memory region available at ptr in bytes.
+ *
+ * @return -1 on Failure
+ *         0 on success
+ */
+int cvmx_add_arena(cvmx_arena_list_t *arena_list, void *ptr, size_t size);
+
+/**
+ * allocate buffer from an arena list
+ *
+ * @param arena_list arena list to allocate buffer from
+ * @param size       size of buffer to allocate (in bytes)
+ *
+ * @return pointer to buffer or NULL if allocation failed
+ */
+void *cvmx_malloc(cvmx_arena_list_t arena_list, size_t size);
+/**
+ * Allocate zero initialized buffer
+ *
+ * @param arena_list arena list to allocate from
+ * @param n          number of elements
+ * @param elem_size  size of elementes
+ *
+ * @return pointer to (n*elem_size) byte zero initialized buffer or NULL
+ *         on allocation failure
+ */
+void *cvmx_calloc(cvmx_arena_list_t arena_list, size_t n, size_t elem_size);
+/**
+ * attempt to increase the size of an already allocated buffer
+ * This function may allocate a new buffer and copy
+ * the data if current buffer can't be extended.
+ *
+ * @param arena_list arena list to allocate from
+ * @param ptr        pointer to buffer to extend
+ * @param size       new buffer size
+ *
+ * @return pointer to expanded buffer (may differ from ptr)
+ *         or NULL on failure
+ */
+void *cvmx_realloc(cvmx_arena_list_t arena_list, void *ptr, size_t size);
+/**
+ * allocate a buffer with a specified alignment
+ *
+ * @param arena_list arena list to allocate from
+ * @param alignment  alignment of buffer.  Must be a power of 2
+ * @param bytes      size of buffer in bytes
+ *
+ * @return pointer to buffer on success
+ *         NULL on failure
+ */
+void *cvmx_memalign(cvmx_arena_list_t arena_list, size_t alignment, size_t bytes);
+/**
+ * free a previously allocated buffer
+ *
+ * @param ptr    pointer of buffer to deallocate
+ */
+void cvmx_free(void *ptr);
+
+
+
+
+#define CVMX_ZONE_OVERHEAD  (64)
+/** Zone allocator definitions
+ *
+ */
+struct cvmx_zone
+{
+	cvmx_spinlock_t lock;
+	char *baseptr;
+	char *name;
+	void *freelist;
+	uint32_t num_elem;
+	uint32_t elem_size;
+	uint32_t align;
+};
+typedef struct cvmx_zone * cvmx_zone_t;
+
+static inline uint32_t cvmx_zone_size(cvmx_zone_t zone)
+{
+    return(zone->elem_size);
+}
+static inline char *cvmx_zone_name(cvmx_zone_t zone)
+{
+    return(zone->name);
+}
+
+
+/**
+ * Creates a memory zone for efficient allocation/deallocation of
+ * fixed size memory blocks from a specified memory region.
+ *
+ * @param name      name of zone.
+ * @param elem_size size of blocks that will be requested from zone
+ * @param num_elem  number of elements to allocate
+ * @param mem_ptr   pointer to memory to allocate zone from
+ * @param mem_size  size of memory region available
+ *                  (must be at least elem_size * num_elem + CVMX_ZONE_OVERHEAD bytes)
+ * @param flags     flags for zone.  Currently unused.
+ *
+ * @return pointer to zone on success or
+ *         NULL on failure
+ */
+cvmx_zone_t cvmx_zone_create_from_addr(char *name, uint32_t elem_size, uint32_t num_elem,
+                             void* mem_ptr, uint64_t mem_size, uint32_t flags);
+/**
+ * Creates a memory zone for efficient allocation/deallocation of
+ * fixed size memory blocks from a previously initialized arena list.
+ *
+ * @param name       name of zone.
+ * @param elem_size  size of blocks that will be requested from zone
+ * @param num_elem   number of elements to allocate
+ * @param align      alignment of buffers (must be power of 2)
+ *                   Elements are allocated contiguously, so the buffer size
+ *                   must be a multiple of the requested alignment for all
+ *                   buffers to have the requested alignment.
+ * @param arena_list arena list to allocate memory from
+ * @param flags      flags for zone.  Currently unused.
+ *
+ * @return pointer to zone on success or
+ *         NULL on failure
+ */
+cvmx_zone_t cvmx_zone_create_from_arena(char *name, uint32_t elem_size, uint32_t num_elem, uint32_t align,
+                             cvmx_arena_list_t arena_list, uint32_t flags);
+/**
+ * Allocate a buffer from a memory zone
+ *
+ * @param zone   zone to allocate buffer from
+ * @param flags  flags (currently unused)
+ *
+ * @return pointer to buffer or NULL on failure
+ */
+void * cvmx_zone_alloc(cvmx_zone_t zone, uint32_t flags);
+/**
+ * Free a previously allocated buffer
+ *
+ * @param zone   zone that buffer was allocated from
+ * @param ptr    pointer to buffer to be freed
+ */
+void cvmx_zone_free(cvmx_zone_t zone, void *ptr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CVMX_MALLOC_H__
diff --git a/cvmx-malloc/README-malloc b/cvmx-malloc/README-malloc
new file mode 100644
index 0000000000000..922a713410a9b
--- /dev/null
+++ b/cvmx-malloc/README-malloc
@@ -0,0 +1,12 @@
+Readme for Octeon shared memory malloc
+
+This malloc is based on ptmalloc2, which is the malloc
+implementation of glibc.  Source code and more information
+on this can be found at http://www.malloc.de/en/index.html.
+Please see the individual files for licensing terms.
+
+The main change to the code modifies the way the malloc
+gets memory from the system.  Under Linux/Unix, malloc
+uses the brk or memmap sytem calls to request more memory.
+In this implementation, memory regions must be explicitly
+given to malloc by the application.
diff --git a/cvmx-malloc/arena.c b/cvmx-malloc/arena.c
new file mode 100644
index 0000000000000..8e0ce1fe25fac
--- /dev/null
+++ b/cvmx-malloc/arena.c
@@ -0,0 +1,293 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+/* $Id: arena.c 30481 2007-12-05 21:46:59Z rfranz $ */
+
+/* Compile-time constants.  */
+
+#define HEAP_MIN_SIZE (4096)   /* Must leave room for struct malloc_state, arena ptrs, etc., totals about 2400 bytes */
+
+#ifndef THREAD_STATS
+#define THREAD_STATS 0
+#endif
+
+/* If THREAD_STATS is non-zero, some statistics on mutex locking are
+   computed.  */
+
+/***************************************************************************/
+
+// made static to avoid conflicts with newlib
+static mstate         _int_new_arena __MALLOC_P ((size_t __ini_size));
+
+/***************************************************************************/
+
+#define top(ar_ptr) ((ar_ptr)->top)
+
+/* A heap is a single contiguous memory region holding (coalesceable)
+   malloc_chunks.    Not used unless compiling with
+   USE_ARENAS. */
+
+typedef struct _heap_info {
+  mstate ar_ptr; /* Arena for this heap. */
+  struct _heap_info *prev; /* Previous heap. */
+  size_t size;   /* Current size in bytes. */
+  size_t pad;    /* Make sure the following data is properly aligned. */
+} heap_info;
+
+/* Thread specific data */
+
+static tsd_key_t arena_key;  // one per PP (thread)
+static CVMX_SHARED mutex_t list_lock;  // shared...
+
+#if THREAD_STATS
+static int stat_n_heaps;
+#define THREAD_STAT(x) x
+#else
+#define THREAD_STAT(x) do ; while(0)
+#endif
+
+/* Mapped memory in non-main arenas (reliable only for NO_THREADS). */
+static unsigned long arena_mem;
+
+/* Already initialized? */
+int CVMX_SHARED cvmx__malloc_initialized = -1;
+
+/**************************************************************************/
+
+#if USE_ARENAS
+
+/* find the heap and corresponding arena for a given ptr */
+
+#define arena_for_chunk(ptr) ((ptr)->arena_ptr)
+#define set_arena_for_chunk(ptr, arena) (ptr)->arena_ptr = (arena)
+
+
+#endif /* USE_ARENAS */
+
+/**************************************************************************/
+
+#ifndef NO_THREADS
+
+/* atfork support.  */
+
+static __malloc_ptr_t (*save_malloc_hook) __MALLOC_P ((size_t __size,
+						       __const __malloc_ptr_t));
+static void           (*save_free_hook) __MALLOC_P ((__malloc_ptr_t __ptr,
+						     __const __malloc_ptr_t));
+static Void_t*        save_arena;
+
+/* Magic value for the thread-specific arena pointer when
+   malloc_atfork() is in use.  */
+
+#define ATFORK_ARENA_PTR ((Void_t*)-1)
+
+/* The following hooks are used while the `atfork' handling mechanism
+   is active. */
+
+static Void_t*
+malloc_atfork(size_t sz, const Void_t *caller)
+{
+return(NULL);
+}
+
+static void
+free_atfork(Void_t* mem, const Void_t *caller)
+{
+  Void_t *vptr = NULL;
+  mstate ar_ptr;
+  mchunkptr p;                          /* chunk corresponding to mem */
+
+  if (mem == 0)                              /* free(0) has no effect */
+    return;
+
+  p = mem2chunk(mem);         /* do not bother to replicate free_check here */
+
+#if HAVE_MMAP
+  if (chunk_is_mmapped(p))                       /* release mmapped memory. */
+  {
+    munmap_chunk(p);
+    return;
+  }
+#endif
+
+  ar_ptr = arena_for_chunk(p);
+  tsd_getspecific(arena_key, vptr);
+  if(vptr != ATFORK_ARENA_PTR)
+    (void)mutex_lock(&ar_ptr->mutex);
+  _int_free(ar_ptr, mem);
+  if(vptr != ATFORK_ARENA_PTR)
+    (void)mutex_unlock(&ar_ptr->mutex);
+}
+
+
+
+#ifdef __linux__
+#error   __linux__defined!
+#endif
+
+#endif /* !defined NO_THREADS */
+
+
+
+/* Initialization routine. */
+#ifdef _LIBC
+#error  _LIBC is defined, and should not be
+#endif /* _LIBC */
+
+static CVMX_SHARED cvmx_spinlock_t malloc_init_spin_lock;
+
+
+
+
+/* Managing heaps and arenas (for concurrent threads) */
+
+#if USE_ARENAS
+
+#if MALLOC_DEBUG > 1
+
+/* Print the complete contents of a single heap to stderr. */
+
+static void
+#if __STD_C
+dump_heap(heap_info *heap)
+#else
+dump_heap(heap) heap_info *heap;
+#endif
+{
+  char *ptr;
+  mchunkptr p;
+
+  fprintf(stderr, "Heap %p, size %10lx:\n", heap, (long)heap->size);
+  ptr = (heap->ar_ptr != (mstate)(heap+1)) ?
+    (char*)(heap + 1) : (char*)(heap + 1) + sizeof(struct malloc_state);
+  p = (mchunkptr)(((unsigned long)ptr + MALLOC_ALIGN_MASK) &
+                  ~MALLOC_ALIGN_MASK);
+  for(;;) {
+    fprintf(stderr, "chunk %p size %10lx", p, (long)p->size);
+    if(p == top(heap->ar_ptr)) {
+      fprintf(stderr, " (top)\n");
+      break;
+    } else if(p->size == (0|PREV_INUSE)) {
+      fprintf(stderr, " (fence)\n");
+      break;
+    }
+    fprintf(stderr, "\n");
+    p = next_chunk(p);
+  }
+}
+
+#endif /* MALLOC_DEBUG > 1 */
+/* Delete a heap. */
+
+
+static mstate cvmx_new_arena(void *addr, size_t size)
+{
+  mstate a;
+  heap_info *h;
+  char *ptr;
+  unsigned long misalign;
+  int page_mask = malloc_getpagesize - 1;
+
+  debug_printf("cvmx_new_arena called, addr: %p, size %ld\n", addr, size);
+  debug_printf("heapinfo size: %ld, mstate size: %d\n", sizeof(heap_info), sizeof(struct malloc_state));
+
+  if (!addr || (size < HEAP_MIN_SIZE))
+  {
+      return(NULL);
+  }
+  /* We must zero out the arena as the malloc code assumes this. */
+  memset(addr, 0, size);
+
+  h = (heap_info *)addr;
+  h->size = size;
+
+  a = h->ar_ptr = (mstate)(h+1);
+  malloc_init_state(a);
+  /*a->next = NULL;*/
+  a->system_mem = a->max_system_mem = h->size;
+  arena_mem += h->size;
+  a->next = a;
+
+  /* Set up the top chunk, with proper alignment. */
+  ptr = (char *)(a + 1);
+  misalign = (unsigned long)chunk2mem(ptr) & MALLOC_ALIGN_MASK;
+  if (misalign > 0)
+    ptr += MALLOC_ALIGNMENT - misalign;
+  top(a) = (mchunkptr)ptr;
+  set_head(top(a), (((char*)h + h->size) - ptr) | PREV_INUSE);
+
+  return a;
+}
+
+
+int cvmx_add_arena(cvmx_arena_list_t *arena_list, void *ptr, size_t size)
+{
+  mstate a;
+
+  /* Enforce required alignement, and adjust size */
+  int misaligned = ((size_t)ptr) & (MALLOC_ALIGNMENT - 1);
+  if (misaligned)
+  {
+      ptr = (char*)ptr + MALLOC_ALIGNMENT - misaligned;
+      size -= MALLOC_ALIGNMENT - misaligned;
+  }
+
+  debug_printf("Adding arena at addr: %p, size %d\n", ptr, size);
+
+  a = cvmx_new_arena(ptr, size);  /* checks ptr and size */
+  if (!a)
+  {
+      return(-1);
+  }
+
+  debug_printf("cmvx_add_arena - arena_list: %p, *arena_list: %p\n", arena_list, *arena_list);
+  debug_printf("cmvx_add_arena - list: %p, new: %p\n", *arena_list, a);
+  mutex_init(&a->mutex);
+  mutex_lock(&a->mutex);
+
+
+  if (*arena_list)
+  {
+      mstate ar_ptr = *arena_list;
+      (void)mutex_lock(&ar_ptr->mutex);
+      a->next = ar_ptr->next;  // lock held on a and ar_ptr
+      ar_ptr->next = a;
+      (void)mutex_unlock(&ar_ptr->mutex);
+  }
+  else
+  {
+      *arena_list = a;
+//      a->next = a;
+  }
+
+  debug_printf("cvmx_add_arena - list: %p, list->next: %p\n", *arena_list, ((mstate)*arena_list)->next);
+
+  // unlock, since it is not going to be used immediately
+  (void)mutex_unlock(&a->mutex);
+
+  return(0);
+}
+
+
+
+#endif /* USE_ARENAS */
diff --git a/cvmx-malloc/malloc.c b/cvmx-malloc/malloc.c
new file mode 100644
index 0000000000000..222ad5def124c
--- /dev/null
+++ b/cvmx-malloc/malloc.c
@@ -0,0 +1,4106 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+/*
+  This is a version (aka ptmalloc2) of malloc/free/realloc written by
+  Doug Lea and adapted to multiple threads/arenas by Wolfram Gloger.
+
+* Version ptmalloc2-20011215
+  $Id: malloc.c 30481 2007-12-05 21:46:59Z rfranz $
+  based on:
+  VERSION 2.7.1pre1 Sat May 12 07:41:21 2001  Doug Lea  (dl at gee)
+
+   Note: There may be an updated version of this malloc obtainable at
+           http://www.malloc.de/malloc/ptmalloc2.tar.gz
+         Check before installing!
+
+* Quickstart
+
+  In order to compile this implementation, a Makefile is provided with
+  the ptmalloc2 distribution, which has pre-defined targets for some
+  popular systems (e.g. "make posix" for Posix threads).  All that is
+  typically required with regard to compiler flags is the selection of
+  the thread package via defining one out of USE_PTHREADS, USE_THR or
+  USE_SPROC.  Check the thread-m.h file for what effects this has.
+  Many/most systems will additionally require USE_TSD_DATA_HACK to be
+  defined, so this is the default for "make posix".
+
+* Why use this malloc?
+
+  This is not the fastest, most space-conserving, most portable, or
+  most tunable malloc ever written. However it is among the fastest
+  while also being among the most space-conserving, portable and tunable.
+  Consistent balance across these factors results in a good general-purpose
+  allocator for malloc-intensive programs.
+
+  The main properties of the algorithms are:
+  * For large (>= 512 bytes) requests, it is a pure best-fit allocator,
+    with ties normally decided via FIFO (i.e. least recently used).
+  * For small (<= 64 bytes by default) requests, it is a caching
+    allocator, that maintains pools of quickly recycled chunks.
+  * In between, and for combinations of large and small requests, it does
+    the best it can trying to meet both goals at once.
+  * For very large requests (>= 128KB by default), it relies on system
+    memory mapping facilities, if supported.
+
+  For a longer but slightly out of date high-level description, see
+     http://gee.cs.oswego.edu/dl/html/malloc.html
+
+  You may already by default be using a C library containing a malloc
+  that is  based on some version of this malloc (for example in
+  linux). You might still want to use the one in this file in order to
+  customize settings or to avoid overheads associated with library
+  versions.
+
+* Contents, described in more detail in "description of public routines" below.
+
+  Standard (ANSI/SVID/...)  functions:
+    malloc(size_t n);
+    calloc(size_t n_elements, size_t element_size);
+    free(Void_t* p);
+    realloc(Void_t* p, size_t n);
+    memalign(size_t alignment, size_t n);
+    valloc(size_t n);
+    mallinfo()
+    mallopt(int parameter_number, int parameter_value)
+
+  Additional functions:
+    independent_calloc(size_t n_elements, size_t size, Void_t* chunks[]);
+    independent_comalloc(size_t n_elements, size_t sizes[], Void_t* chunks[]);
+    pvalloc(size_t n);
+    cfree(Void_t* p);
+    malloc_trim(size_t pad);
+    malloc_usable_size(Void_t* p);
+    malloc_stats();
+
+* Vital statistics:
+
+  Supported pointer representation:       4 or 8 bytes
+  Supported size_t  representation:       4 or 8 bytes
+       Note that size_t is allowed to be 4 bytes even if pointers are 8.
+       You can adjust this by defining INTERNAL_SIZE_T
+
+  Alignment:                              2 * sizeof(size_t) (default)
+       (i.e., 8 byte alignment with 4byte size_t). This suffices for
+       nearly all current machines and C compilers. However, you can
+       define MALLOC_ALIGNMENT to be wider than this if necessary.
+
+  Minimum overhead per allocated chunk:   4 or 8 bytes
+       Each malloced chunk has a hidden word of overhead holding size
+       and status information.
+
+  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
+                          8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
+
+       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
+       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
+       needed; 4 (8) for a trailing size field and 8 (16) bytes for
+       free list pointers. Thus, the minimum allocatable size is
+       16/24/32 bytes.
+
+       Even a request for zero bytes (i.e., malloc(0)) returns a
+       pointer to something of the minimum allocatable size.
+
+       The maximum overhead wastage (i.e., number of extra bytes
+       allocated than were requested in malloc) is less than or equal
+       to the minimum size, except for requests >= mmap_threshold that
+       are serviced via mmap(), where the worst case wastage is 2 *
+       sizeof(size_t) bytes plus the remainder from a system page (the
+       minimal mmap unit); typically 4096 or 8192 bytes.
+
+  Maximum allocated size:  4-byte size_t: 2^32 minus about two pages
+                           8-byte size_t: 2^64 minus about two pages
+
+       It is assumed that (possibly signed) size_t values suffice to
+       represent chunk sizes. `Possibly signed' is due to the fact
+       that `size_t' may be defined on a system as either a signed or
+       an unsigned type. The ISO C standard says that it must be
+       unsigned, but a few systems are known not to adhere to this.
+       Additionally, even when size_t is unsigned, sbrk (which is by
+       default used to obtain memory from system) accepts signed
+       arguments, and may not be able to handle size_t-wide arguments
+       with negative sign bit.  Generally, values that would
+       appear as negative after accounting for overhead and alignment
+       are supported only via mmap(), which does not have this
+       limitation.
+
+       Requests for sizes outside the allowed range will perform an optional
+       failure action and then return null. (Requests may also
+       also fail because a system is out of memory.)
+
+  Thread-safety: thread-safe unless NO_THREADS is defined
+
+  Compliance: I believe it is compliant with the 1997 Single Unix Specification
+       (See http://www.opennc.org). Also SVID/XPG, ANSI C, and probably
+       others as well.
+
+* Synopsis of compile-time options:
+
+    People have reported using previous versions of this malloc on all
+    versions of Unix, sometimes by tweaking some of the defines
+    below. It has been tested most extensively on Solaris and
+    Linux. It is also reported to work on WIN32 platforms.
+    People also report using it in stand-alone embedded systems.
+
+    The implementation is in straight, hand-tuned ANSI C.  It is not
+    at all modular. (Sorry!)  It uses a lot of macros.  To be at all
+    usable, this code should be compiled using an optimizing compiler
+    (for example gcc -O3) that can simplify expressions and control
+    paths. (FAQ: some macros import variables as arguments rather than
+    declare locals because people reported that some debuggers
+    otherwise get confused.)
+
+    OPTION                     DEFAULT VALUE
+
+    Compilation Environment options:
+
+    __STD_C                    derived from C compiler defines
+    WIN32                      NOT defined
+    HAVE_MEMCPY                defined
+    USE_MEMCPY                 1 if HAVE_MEMCPY is defined
+    HAVE_MMAP                  defined as 1
+    MMAP_CLEARS                1
+    HAVE_MREMAP                0 unless linux defined
+    USE_ARENAS                 the same as HAVE_MMAP
+    malloc_getpagesize         derived from system #includes, or 4096 if not
+    HAVE_USR_INCLUDE_MALLOC_H  NOT defined
+    LACKS_UNISTD_H             NOT defined unless WIN32
+    LACKS_SYS_PARAM_H          NOT defined unless WIN32
+    LACKS_SYS_MMAN_H           NOT defined unless WIN32
+
+    Changing default word sizes:
+
+    INTERNAL_SIZE_T            size_t
+    MALLOC_ALIGNMENT           2 * sizeof(INTERNAL_SIZE_T)
+
+    Configuration and functionality options:
+
+    USE_DL_PREFIX              NOT defined
+    USE_PUBLIC_MALLOC_WRAPPERS NOT defined
+    USE_MALLOC_LOCK            NOT defined
+    MALLOC_DEBUG               NOT defined
+    REALLOC_ZERO_BYTES_FREES   1
+    MALLOC_FAILURE_ACTION      errno = ENOMEM, if __STD_C defined, else no-op
+    TRIM_FASTBINS              0
+    FIRST_SORTED_BIN_SIZE      512
+
+    Options for customizing MORECORE:
+
+    MORECORE                   sbrk
+    MORECORE_FAILURE           -1
+    MORECORE_CONTIGUOUS        1
+    MORECORE_CANNOT_TRIM       NOT defined
+    MORECORE_CLEARS            1
+    MMAP_AS_MORECORE_SIZE      (1024 * 1024)
+
+    Tuning options that are also dynamically changeable via mallopt:
+
+    DEFAULT_MXFAST             64
+    DEFAULT_TRIM_THRESHOLD     128 * 1024
+    DEFAULT_TOP_PAD            0
+    DEFAULT_MMAP_THRESHOLD     128 * 1024
+    DEFAULT_MMAP_MAX           65536
+
+    There are several other #defined constants and macros that you
+    probably don't want to touch unless you are extending or adapting malloc.  */
+
+/*
+  __STD_C should be nonzero if using ANSI-standard C compiler, a C++
+  compiler, or a C compiler sufficiently close to ANSI to get away
+  with it.
+*/
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-malloc.h"
+
+
+#ifndef __STD_C
+#if defined(__STDC__) || defined(__cplusplus)
+#define __STD_C     1
+#else
+#define __STD_C     0
+#endif
+#endif /*__STD_C*/
+
+
+/*
+  Void_t* is the pointer type that malloc should say it returns
+*/
+
+#ifndef Void_t
+#if 1
+#define Void_t      void
+#else
+#define Void_t      char
+#endif
+#endif /*Void_t*/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* define LACKS_UNISTD_H if your system does not have a <unistd.h>. */
+
+/* #define  LACKS_UNISTD_H */
+
+#ifndef LACKS_UNISTD_H
+#include <unistd.h>
+#endif
+
+/* define LACKS_SYS_PARAM_H if your system does not have a <sys/param.h>. */
+
+/* #define  LACKS_SYS_PARAM_H */
+
+
+#include <stdio.h>    /* needed for malloc_stats */
+#include <errno.h>    /* needed for optional MALLOC_FAILURE_ACTION */
+
+
+/*
+  Debugging:
+
+  Because freed chunks may be overwritten with bookkeeping fields, this
+  malloc will often die when freed memory is overwritten by user
+  programs.  This can be very effective (albeit in an annoying way)
+  in helping track down dangling pointers.
+
+  If you compile with -DMALLOC_DEBUG, a number of assertion checks are
+  enabled that will catch more memory errors. You probably won't be
+  able to make much sense of the actual assertion errors, but they
+  should help you locate incorrectly overwritten memory.  The checking
+  is fairly extensive, and will slow down execution
+  noticeably. Calling malloc_stats or mallinfo with MALLOC_DEBUG set
+  will attempt to check every non-mmapped allocated and free chunk in
+  the course of computing the summmaries. (By nature, mmapped regions
+  cannot be checked very much automatically.)
+
+  Setting MALLOC_DEBUG may also be helpful if you are trying to modify
+  this code. The assertions in the check routines spell out in more
+  detail the assumptions and invariants underlying the algorithms.
+
+  Setting MALLOC_DEBUG does NOT provide an automated mechanism for
+  checking that all accesses to malloced memory stay within their
+  bounds. However, there are several add-ons and adaptations of this
+  or other mallocs available that do this.
+*/
+
+#define MALLOC_DEBUG 1
+#if MALLOC_DEBUG
+#include <assert.h>
+#else
+#define assert(x) ((void)0)
+#endif
+
+
+/*
+  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
+  of chunk sizes.
+
+  The default version is the same as size_t.
+
+  While not strictly necessary, it is best to define this as an
+  unsigned type, even if size_t is a signed type. This may avoid some
+  artificial size limitations on some systems.
+
+  On a 64-bit machine, you may be able to reduce malloc overhead by
+  defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' at the
+  expense of not being able to handle more than 2^32 of malloced
+  space. If this limitation is acceptable, you are encouraged to set
+  this unless you are on a platform requiring 16byte alignments. In
+  this case the alignment requirements turn out to negate any
+  potential advantages of decreasing size_t word size.
+
+  Implementors: Beware of the possible combinations of:
+     - INTERNAL_SIZE_T might be signed or unsigned, might be 32 or 64 bits,
+       and might be the same width as int or as long
+     - size_t might have different width and signedness as INTERNAL_SIZE_T
+     - int and long might be 32 or 64 bits, and might be the same width
+  To deal with this, most comparisons and difference computations
+  among INTERNAL_SIZE_Ts should cast them to unsigned long, being
+  aware of the fact that casting an unsigned int to a wider long does
+  not sign-extend. (This also makes checking for negative numbers
+  awkward.) Some of these casts result in harmless compiler warnings
+  on some systems.
+*/
+
+#ifndef INTERNAL_SIZE_T
+#define INTERNAL_SIZE_T size_t
+#endif
+
+/* The corresponding word size */
+#define SIZE_SZ                (sizeof(INTERNAL_SIZE_T))
+
+
+/*
+  MALLOC_ALIGNMENT is the minimum alignment for malloc'ed chunks.
+  It must be a power of two at least 2 * SIZE_SZ, even on machines
+  for which smaller alignments would suffice. It may be defined as
+  larger than this though. Note however that code and data structures
+  are optimized for the case of 8-byte alignment.
+*/
+
+
+#ifndef MALLOC_ALIGNMENT
+#define MALLOC_ALIGNMENT       (2 * SIZE_SZ)
+#endif
+
+/* The corresponding bit mask value */
+#define MALLOC_ALIGN_MASK      (MALLOC_ALIGNMENT - 1)
+
+
+
+/*
+  REALLOC_ZERO_BYTES_FREES should be set if a call to
+  realloc with zero bytes should be the same as a call to free.
+  This is required by the C standard. Otherwise, since this malloc
+  returns a unique pointer for malloc(0), so does realloc(p, 0).
+*/
+
+#ifndef REALLOC_ZERO_BYTES_FREES
+#define REALLOC_ZERO_BYTES_FREES 1
+#endif
+
+/*
+  TRIM_FASTBINS controls whether free() of a very small chunk can
+  immediately lead to trimming. Setting to true (1) can reduce memory
+  footprint, but will almost always slow down programs that use a lot
+  of small chunks.
+
+  Define this only if you are willing to give up some speed to more
+  aggressively reduce system-level memory footprint when releasing
+  memory in programs that use many small chunks.  You can get
+  essentially the same effect by setting MXFAST to 0, but this can
+  lead to even greater slowdowns in programs using many small chunks.
+  TRIM_FASTBINS is an in-between compile-time option, that disables
+  only those chunks bordering topmost memory from being placed in
+  fastbins.
+*/
+
+#ifndef TRIM_FASTBINS
+#define TRIM_FASTBINS  0
+#endif
+
+
+/*
+  USE_DL_PREFIX will prefix all public routines with the string 'dl'.
+  This is necessary when you only want to use this malloc in one part
+  of a program, using your regular system malloc elsewhere.
+*/
+
+#define USE_DL_PREFIX
+
+
+/*
+   Two-phase name translation.
+   All of the actual routines are given mangled names.
+   When wrappers are used, they become the public callable versions.
+   When DL_PREFIX is used, the callable names are prefixed.
+*/
+
+#ifdef USE_DL_PREFIX
+#define public_cALLOc    cvmx_calloc
+#define public_fREe      cvmx_free
+#define public_cFREe     dlcfree
+#define public_mALLOc    cvmx_malloc
+#define public_mEMALIGn  cvmx_memalign
+#define public_rEALLOc   cvmx_realloc
+#define public_vALLOc    dlvalloc
+#define public_pVALLOc   dlpvalloc
+#define public_mALLINFo  dlmallinfo
+#define public_mALLOPt   dlmallopt
+#define public_mTRIm     dlmalloc_trim
+#define public_mSTATs    dlmalloc_stats
+#define public_mUSABLe   dlmalloc_usable_size
+#define public_iCALLOc   dlindependent_calloc
+#define public_iCOMALLOc dlindependent_comalloc
+#define public_gET_STATe dlget_state
+#define public_sET_STATe dlset_state
+#else /* USE_DL_PREFIX */
+#ifdef _LIBC
+#error _LIBC defined and should not be
+/* Special defines for the GNU C library.  */
+#define public_cALLOc    __libc_calloc
+#define public_fREe      __libc_free
+#define public_cFREe     __libc_cfree
+#define public_mALLOc    __libc_malloc
+#define public_mEMALIGn  __libc_memalign
+#define public_rEALLOc   __libc_realloc
+#define public_vALLOc    __libc_valloc
+#define public_pVALLOc   __libc_pvalloc
+#define public_mALLINFo  __libc_mallinfo
+#define public_mALLOPt   __libc_mallopt
+#define public_mTRIm     __malloc_trim
+#define public_mSTATs    __malloc_stats
+#define public_mUSABLe   __malloc_usable_size
+#define public_iCALLOc   __libc_independent_calloc
+#define public_iCOMALLOc __libc_independent_comalloc
+#define public_gET_STATe __malloc_get_state
+#define public_sET_STATe __malloc_set_state
+#define malloc_getpagesize __getpagesize()
+#define open             __open
+#define mmap             __mmap
+#define munmap           __munmap
+#define mremap           __mremap
+#define mprotect         __mprotect
+#define MORECORE         (*__morecore)
+#define MORECORE_FAILURE 0
+
+Void_t * __default_morecore (ptrdiff_t);
+Void_t *(*__morecore)(ptrdiff_t) = __default_morecore;
+
+#else /* !_LIBC */
+#define public_cALLOc    calloc
+#define public_fREe      free
+#define public_cFREe     cfree
+#define public_mALLOc    malloc
+#define public_mEMALIGn  memalign
+#define public_rEALLOc   realloc
+#define public_vALLOc    valloc
+#define public_pVALLOc   pvalloc
+#define public_mALLINFo  mallinfo
+#define public_mALLOPt   mallopt
+#define public_mTRIm     malloc_trim
+#define public_mSTATs    malloc_stats
+#define public_mUSABLe   malloc_usable_size
+#define public_iCALLOc   independent_calloc
+#define public_iCOMALLOc independent_comalloc
+#define public_gET_STATe malloc_get_state
+#define public_sET_STATe malloc_set_state
+#endif /* _LIBC */
+#endif /* USE_DL_PREFIX */
+
+
+/*
+  HAVE_MEMCPY should be defined if you are not otherwise using
+  ANSI STD C, but still have memcpy and memset in your C library
+  and want to use them in calloc and realloc. Otherwise simple
+  macro versions are defined below.
+
+  USE_MEMCPY should be defined as 1 if you actually want to
+  have memset and memcpy called. People report that the macro
+  versions are faster than libc versions on some systems.
+
+  Even if USE_MEMCPY is set to 1, loops to copy/clear small chunks
+  (of <= 36 bytes) are manually unrolled in realloc and calloc.
+*/
+
+#define HAVE_MEMCPY
+
+#ifndef USE_MEMCPY
+#ifdef HAVE_MEMCPY
+#define USE_MEMCPY 1
+#else
+#define USE_MEMCPY 0
+#endif
+#endif
+
+
+#if (__STD_C || defined(HAVE_MEMCPY))
+
+#ifdef WIN32
+/* On Win32 memset and memcpy are already declared in windows.h */
+#else
+#if __STD_C
+void* memset(void*, int, size_t);
+void* memcpy(void*, const void*, size_t);
+#else
+Void_t* memset();
+Void_t* memcpy();
+#endif
+#endif
+#endif
+
+/*
+  MALLOC_FAILURE_ACTION is the action to take before "return 0" when
+  malloc fails to be able to return memory, either because memory is
+  exhausted or because of illegal arguments.
+
+  By default, sets errno if running on STD_C platform, else does nothing.
+*/
+
+#ifndef MALLOC_FAILURE_ACTION
+#if __STD_C
+#define MALLOC_FAILURE_ACTION \
+   errno = ENOMEM;
+
+#else
+#define MALLOC_FAILURE_ACTION
+#endif
+#endif
+
+/*
+  MORECORE-related declarations. By default, rely on sbrk
+*/
+
+
+#ifdef LACKS_UNISTD_H
+#if !defined(__FreeBSD__) && !defined(__OpenBSD__) && !defined(__NetBSD__)
+#if __STD_C
+extern Void_t*     sbrk(ptrdiff_t);
+#else
+extern Void_t*     sbrk();
+#endif
+#endif
+#endif
+
+/*
+  MORECORE is the name of the routine to call to obtain more memory
+  from the system.  See below for general guidance on writing
+  alternative MORECORE functions, as well as a version for WIN32 and a
+  sample version for pre-OSX macos.
+*/
+#undef MORECORE  // not supported
+#ifndef MORECORE
+#define MORECORE notsupported
+#endif
+
+/*
+  MORECORE_FAILURE is the value returned upon failure of MORECORE
+  as well as mmap. Since it cannot be an otherwise valid memory address,
+  and must reflect values of standard sys calls, you probably ought not
+  try to redefine it.
+*/
+
+#ifndef MORECORE_FAILURE
+#define MORECORE_FAILURE (-1)
+#endif
+
+/*
+  If MORECORE_CONTIGUOUS is true, take advantage of fact that
+  consecutive calls to MORECORE with positive arguments always return
+  contiguous increasing addresses.  This is true of unix sbrk.  Even
+  if not defined, when regions happen to be contiguous, malloc will
+  permit allocations spanning regions obtained from different
+  calls. But defining this when applicable enables some stronger
+  consistency checks and space efficiencies.
+*/
+
+#ifndef MORECORE_CONTIGUOUS
+#define MORECORE_CONTIGUOUS 0
+#endif
+
+/*
+  Define MORECORE_CANNOT_TRIM if your version of MORECORE
+  cannot release space back to the system when given negative
+  arguments. This is generally necessary only if you are using
+  a hand-crafted MORECORE function that cannot handle negative arguments.
+*/
+
+#define MORECORE_CANNOT_TRIM 1
+
+/*  MORECORE_CLEARS           (default 1)
+     The degree to which the routine mapped to MORECORE zeroes out
+     memory: never (0), only for newly allocated space (1) or always
+     (2).  The distinction between (1) and (2) is necessary because on
+     some systems, if the application first decrements and then
+     increments the break value, the contents of the reallocated space
+     are unspecified.
+*/
+
+#ifndef MORECORE_CLEARS
+#define MORECORE_CLEARS 0
+#endif
+
+
+/*
+  Define HAVE_MMAP as true to optionally make malloc() use mmap() to
+  allocate very large blocks.  These will be returned to the
+  operating system immediately after a free(). Also, if mmap
+  is available, it is used as a backup strategy in cases where
+  MORECORE fails to provide space from system.
+
+  This malloc is best tuned to work with mmap for large requests.
+  If you do not have mmap, operations involving very large chunks (1MB
+  or so) may be slower than you'd like.
+*/
+
+#undef HAVE_MMAP
+#ifndef HAVE_MMAP
+#define HAVE_MMAP 0
+
+/*
+   Standard unix mmap using /dev/zero clears memory so calloc doesn't
+   need to.
+*/
+
+#ifndef MMAP_CLEARS
+#define MMAP_CLEARS 0
+#endif
+
+#else /* no mmap */
+#ifndef MMAP_CLEARS
+#define MMAP_CLEARS 0
+#endif
+#endif
+
+
+/*
+   MMAP_AS_MORECORE_SIZE is the minimum mmap size argument to use if
+   sbrk fails, and mmap is used as a backup (which is done only if
+   HAVE_MMAP).  The value must be a multiple of page size.  This
+   backup strategy generally applies only when systems have "holes" in
+   address space, so sbrk cannot perform contiguous expansion, but
+   there is still space available on system.  On systems for which
+   this is known to be useful (i.e. most linux kernels), this occurs
+   only when programs allocate huge amounts of memory.  Between this,
+   and the fact that mmap regions tend to be limited, the size should
+   be large, to avoid too many mmap calls and thus avoid running out
+   of kernel resources.
+*/
+
+#ifndef MMAP_AS_MORECORE_SIZE
+#define MMAP_AS_MORECORE_SIZE (1024 * 1024)
+#endif
+
+/*
+  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
+  large blocks.  This is currently only possible on Linux with
+  kernel versions newer than 1.3.77.
+*/
+#undef linux
+#ifndef HAVE_MREMAP
+#ifdef linux
+#define HAVE_MREMAP 1
+#else
+#define HAVE_MREMAP 0
+#endif
+
+#endif /* HAVE_MMAP */
+
+/* Define USE_ARENAS to enable support for multiple `arenas'.  These
+   are allocated using mmap(), are necessary for threads and
+   occasionally useful to overcome address space limitations affecting
+   sbrk(). */
+
+#ifndef USE_ARENAS
+#define USE_ARENAS 1  // we 'manually' mmap the arenas.....
+#endif
+
+
+/*
+  The system page size. To the extent possible, this malloc manages
+  memory from the system in page-size units.  Note that this value is
+  cached during initialization into a field of malloc_state. So even
+  if malloc_getpagesize is a function, it is only called once.
+
+  The following mechanics for getpagesize were adapted from bsd/gnu
+  getpagesize.h. If none of the system-probes here apply, a value of
+  4096 is used, which should be OK: If they don't apply, then using
+  the actual value probably doesn't impact performance.
+*/
+
+
+#define malloc_getpagesize (4096)
+#ifndef malloc_getpagesize
+
+#ifndef LACKS_UNISTD_H
+#  include <unistd.h>
+#endif
+
+#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
+#    ifndef _SC_PAGE_SIZE
+#      define _SC_PAGE_SIZE _SC_PAGESIZE
+#    endif
+#  endif
+
+#  ifdef _SC_PAGE_SIZE
+#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
+#  else
+#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
+       extern size_t getpagesize();
+#      define malloc_getpagesize getpagesize()
+#    else
+#      ifdef WIN32 /* use supplied emulation of getpagesize */
+#        define malloc_getpagesize getpagesize()
+#      else
+#        ifndef LACKS_SYS_PARAM_H
+#          include <sys/param.h>
+#        endif
+#        ifdef EXEC_PAGESIZE
+#          define malloc_getpagesize EXEC_PAGESIZE
+#        else
+#          ifdef NBPG
+#            ifndef CLSIZE
+#              define malloc_getpagesize NBPG
+#            else
+#              define malloc_getpagesize (NBPG * CLSIZE)
+#            endif
+#          else
+#            ifdef NBPC
+#              define malloc_getpagesize NBPC
+#            else
+#              ifdef PAGESIZE
+#                define malloc_getpagesize PAGESIZE
+#              else /* just guess */
+#                define malloc_getpagesize (4096)
+#              endif
+#            endif
+#          endif
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+/*
+  This version of malloc supports the standard SVID/XPG mallinfo
+  routine that returns a struct containing usage properties and
+  statistics. It should work on any SVID/XPG compliant system that has
+  a /usr/include/malloc.h defining struct mallinfo. (If you'd like to
+  install such a thing yourself, cut out the preliminary declarations
+  as described above and below and save them in a malloc.h file. But
+  there's no compelling reason to bother to do this.)
+
+  The main declaration needed is the mallinfo struct that is returned
+  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
+  bunch of fields that are not even meaningful in this version of
+  malloc.  These fields are are instead filled by mallinfo() with
+  other numbers that might be of interest.
+
+  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
+  /usr/include/malloc.h file that includes a declaration of struct
+  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
+  version is declared below.  These must be precisely the same for
+  mallinfo() to work.  The original SVID version of this struct,
+  defined on most systems with mallinfo, declares all fields as
+  ints. But some others define as unsigned long. If your system
+  defines the fields using a type of different width than listed here,
+  you must #include your system version and #define
+  HAVE_USR_INCLUDE_MALLOC_H.
+*/
+
+/* #define HAVE_USR_INCLUDE_MALLOC_H */
+
+#ifdef HAVE_USR_INCLUDE_MALLOC_H
+#include "/usr/include/malloc.h"
+#endif
+
+
+/* ---------- description of public routines ------------ */
+
+/*
+  malloc(size_t n)
+  Returns a pointer to a newly allocated chunk of at least n bytes, or null
+  if no space is available. Additionally, on failure, errno is
+  set to ENOMEM on ANSI C systems.
+
+  If n is zero, malloc returns a minumum-sized chunk. (The minimum
+  size is 16 bytes on most 32bit systems, and 24 or 32 bytes on 64bit
+  systems.)  On most systems, size_t is an unsigned type, so calls
+  with negative arguments are interpreted as requests for huge amounts
+  of space, which will often fail. The maximum supported value of n
+  differs across systems, but is in all cases less than the maximum
+  representable value of a size_t.
+*/
+#if __STD_C
+Void_t*  public_mALLOc(cvmx_arena_list_t arena_list, size_t);
+#else
+Void_t*  public_mALLOc();
+#endif
+
+/*
+  free(Void_t* p)
+  Releases the chunk of memory pointed to by p, that had been previously
+  allocated using malloc or a related routine such as realloc.
+  It has no effect if p is null. It can have arbitrary (i.e., bad!)
+  effects if p has already been freed.
+
+  Unless disabled (using mallopt), freeing very large spaces will
+  when possible, automatically trigger operations that give
+  back unused memory to the system, thus reducing program footprint.
+*/
+#if __STD_C
+void     public_fREe(Void_t*);
+#else
+void     public_fREe();
+#endif
+
+/*
+  calloc(size_t n_elements, size_t element_size);
+  Returns a pointer to n_elements * element_size bytes, with all locations
+  set to zero.
+*/
+#if __STD_C
+Void_t*  public_cALLOc(cvmx_arena_list_t arena_list, size_t, size_t);
+#else
+Void_t*  public_cALLOc();
+#endif
+
+/*
+  realloc(Void_t* p, size_t n)
+  Returns a pointer to a chunk of size n that contains the same data
+  as does chunk p up to the minimum of (n, p's size) bytes, or null
+  if no space is available.
+
+  The returned pointer may or may not be the same as p. The algorithm
+  prefers extending p when possible, otherwise it employs the
+  equivalent of a malloc-copy-free sequence.
+
+  If p is null, realloc is equivalent to malloc.
+
+  If space is not available, realloc returns null, errno is set (if on
+  ANSI) and p is NOT freed.
+
+  if n is for fewer bytes than already held by p, the newly unused
+  space is lopped off and freed if possible.  Unless the #define
+  REALLOC_ZERO_BYTES_FREES is set, realloc with a size argument of
+  zero (re)allocates a minimum-sized chunk.
+
+  Large chunks that were internally obtained via mmap will always
+  be reallocated using malloc-copy-free sequences unless
+  the system supports MREMAP (currently only linux).
+
+  The old unix realloc convention of allowing the last-free'd chunk
+  to be used as an argument to realloc is not supported.
+*/
+#if __STD_C
+Void_t*  public_rEALLOc(cvmx_arena_list_t arena_list, Void_t*, size_t);
+#else
+Void_t*  public_rEALLOc();
+#endif
+
+/*
+  memalign(size_t alignment, size_t n);
+  Returns a pointer to a newly allocated chunk of n bytes, aligned
+  in accord with the alignment argument.
+
+  The alignment argument should be a power of two. If the argument is
+  not a power of two, the nearest greater power is used.
+  8-byte alignment is guaranteed by normal malloc calls, so don't
+  bother calling memalign with an argument of 8 or less.
+
+  Overreliance on memalign is a sure way to fragment space.
+*/
+#if __STD_C
+Void_t*  public_mEMALIGn(cvmx_arena_list_t arena_list, size_t, size_t);
+#else
+Void_t*  public_mEMALIGn();
+#endif
+
+/*
+  valloc(size_t n);
+  Equivalent to memalign(pagesize, n), where pagesize is the page
+  size of the system. If the pagesize is unknown, 4096 is used.
+*/
+#if __STD_C
+Void_t*  public_vALLOc(size_t);
+#else
+Void_t*  public_vALLOc();
+#endif
+
+
+
+/*
+  mallopt(int parameter_number, int parameter_value)
+  Sets tunable parameters The format is to provide a
+  (parameter-number, parameter-value) pair.  mallopt then sets the
+  corresponding parameter to the argument value if it can (i.e., so
+  long as the value is meaningful), and returns 1 if successful else
+  0.  SVID/XPG/ANSI defines four standard param numbers for mallopt,
+  normally defined in malloc.h.  Only one of these (M_MXFAST) is used
+  in this malloc. The others (M_NLBLKS, M_GRAIN, M_KEEP) don't apply,
+  so setting them has no effect. But this malloc also supports four
+  other options in mallopt. See below for details.  Briefly, supported
+  parameters are as follows (listed defaults are for "typical"
+  configurations).
+
+  Symbol            param #   default    allowed param values
+  M_MXFAST          1         64         0-80  (0 disables fastbins)
+  M_TRIM_THRESHOLD -1         128*1024   any   (-1U disables trimming)
+  M_TOP_PAD        -2         0          any
+  M_MMAP_THRESHOLD -3         128*1024   any   (or 0 if no MMAP support)
+  M_MMAP_MAX       -4         65536      any   (0 disables use of mmap)
+*/
+#if __STD_C
+int      public_mALLOPt(int, int);
+#else
+int      public_mALLOPt();
+#endif
+
+
+/*
+  mallinfo()
+  Returns (by copy) a struct containing various summary statistics:
+
+  arena:     current total non-mmapped bytes allocated from system
+  ordblks:   the number of free chunks
+  smblks:    the number of fastbin blocks (i.e., small chunks that
+               have been freed but not use resused or consolidated)
+  hblks:     current number of mmapped regions
+  hblkhd:    total bytes held in mmapped regions
+  usmblks:   the maximum total allocated space. This will be greater
+                than current total if trimming has occurred.
+  fsmblks:   total bytes held in fastbin blocks
+  uordblks:  current total allocated space (normal or mmapped)
+  fordblks:  total free space
+  keepcost:  the maximum number of bytes that could ideally be released
+               back to system via malloc_trim. ("ideally" means that
+               it ignores page restrictions etc.)
+
+  Because these fields are ints, but internal bookkeeping may
+  be kept as longs, the reported values may wrap around zero and
+  thus be inaccurate.
+*/
+#if __STD_C
+struct mallinfo public_mALLINFo(void);
+#else
+struct mallinfo public_mALLINFo();
+#endif
+
+/*
+  independent_calloc(size_t n_elements, size_t element_size, Void_t* chunks[]);
+
+  independent_calloc is similar to calloc, but instead of returning a
+  single cleared space, it returns an array of pointers to n_elements
+  independent elements that can hold contents of size elem_size, each
+  of which starts out cleared, and can be independently freed,
+  realloc'ed etc. The elements are guaranteed to be adjacently
+  allocated (this is not guaranteed to occur with multiple callocs or
+  mallocs), which may also improve cache locality in some
+  applications.
+
+  The "chunks" argument is optional (i.e., may be null, which is
+  probably the most typical usage). If it is null, the returned array
+  is itself dynamically allocated and should also be freed when it is
+  no longer needed. Otherwise, the chunks array must be of at least
+  n_elements in length. It is filled in with the pointers to the
+  chunks.
+
+  In either case, independent_calloc returns this pointer array, or
+  null if the allocation failed.  If n_elements is zero and "chunks"
+  is null, it returns a chunk representing an array with zero elements
+  (which should be freed if not wanted).
+
+  Each element must be individually freed when it is no longer
+  needed. If you'd like to instead be able to free all at once, you
+  should instead use regular calloc and assign pointers into this
+  space to represent elements.  (In this case though, you cannot
+  independently free elements.)
+
+  independent_calloc simplifies and speeds up implementations of many
+  kinds of pools.  It may also be useful when constructing large data
+  structures that initially have a fixed number of fixed-sized nodes,
+  but the number is not known at compile time, and some of the nodes
+  may later need to be freed. For example:
+
+  struct Node { int item; struct Node* next; };
+
+  struct Node* build_list() {
+    struct Node** pool;
+    int n = read_number_of_nodes_needed();
+    if (n <= 0) return 0;
+    pool = (struct Node**)(independent_calloc(n, sizeof(struct Node), 0);
+    if (pool == 0) die();
+    // organize into a linked list...
+    struct Node* first = pool[0];
+    for (i = 0; i < n-1; ++i)
+      pool[i]->next = pool[i+1];
+    free(pool);     // Can now free the array (or not, if it is needed later)
+    return first;
+  }
+*/
+#if __STD_C
+Void_t** public_iCALLOc(size_t, size_t, Void_t**);
+#else
+Void_t** public_iCALLOc();
+#endif
+
+/*
+  independent_comalloc(size_t n_elements, size_t sizes[], Void_t* chunks[]);
+
+  independent_comalloc allocates, all at once, a set of n_elements
+  chunks with sizes indicated in the "sizes" array.    It returns
+  an array of pointers to these elements, each of which can be
+  independently freed, realloc'ed etc. The elements are guaranteed to
+  be adjacently allocated (this is not guaranteed to occur with
+  multiple callocs or mallocs), which may also improve cache locality
+  in some applications.
+
+  The "chunks" argument is optional (i.e., may be null). If it is null
+  the returned array is itself dynamically allocated and should also
+  be freed when it is no longer needed. Otherwise, the chunks array
+  must be of at least n_elements in length. It is filled in with the
+  pointers to the chunks.
+
+  In either case, independent_comalloc returns this pointer array, or
+  null if the allocation failed.  If n_elements is zero and chunks is
+  null, it returns a chunk representing an array with zero elements
+  (which should be freed if not wanted).
+
+  Each element must be individually freed when it is no longer
+  needed. If you'd like to instead be able to free all at once, you
+  should instead use a single regular malloc, and assign pointers at
+  particular offsets in the aggregate space. (In this case though, you
+  cannot independently free elements.)
+
+  independent_comallac differs from independent_calloc in that each
+  element may have a different size, and also that it does not
+  automatically clear elements.
+
+  independent_comalloc can be used to speed up allocation in cases
+  where several structs or objects must always be allocated at the
+  same time.  For example:
+
+  struct Head { ... }
+  struct Foot { ... }
+
+  void send_message(char* msg) {
+    int msglen = strlen(msg);
+    size_t sizes[3] = { sizeof(struct Head), msglen, sizeof(struct Foot) };
+    void* chunks[3];
+    if (independent_comalloc(3, sizes, chunks) == 0)
+      die();
+    struct Head* head = (struct Head*)(chunks[0]);
+    char*        body = (char*)(chunks[1]);
+    struct Foot* foot = (struct Foot*)(chunks[2]);
+    // ...
+  }
+
+  In general though, independent_comalloc is worth using only for
+  larger values of n_elements. For small values, you probably won't
+  detect enough difference from series of malloc calls to bother.
+
+  Overuse of independent_comalloc can increase overall memory usage,
+  since it cannot reuse existing noncontiguous small chunks that
+  might be available for some of the elements.
+*/
+#if __STD_C
+Void_t** public_iCOMALLOc(size_t, size_t*, Void_t**);
+#else
+Void_t** public_iCOMALLOc();
+#endif
+
+
+/*
+  pvalloc(size_t n);
+  Equivalent to valloc(minimum-page-that-holds(n)), that is,
+  round up n to nearest pagesize.
+ */
+#if __STD_C
+Void_t*  public_pVALLOc(size_t);
+#else
+Void_t*  public_pVALLOc();
+#endif
+
+/*
+  cfree(Void_t* p);
+  Equivalent to free(p).
+
+  cfree is needed/defined on some systems that pair it with calloc,
+  for odd historical reasons (such as: cfree is used in example
+  code in the first edition of K&R).
+*/
+#if __STD_C
+void     public_cFREe(Void_t*);
+#else
+void     public_cFREe();
+#endif
+
+/*
+  malloc_trim(size_t pad);
+
+  If possible, gives memory back to the system (via negative
+  arguments to sbrk) if there is unused memory at the `high' end of
+  the malloc pool. You can call this after freeing large blocks of
+  memory to potentially reduce the system-level memory requirements
+  of a program. However, it cannot guarantee to reduce memory. Under
+  some allocation patterns, some large free blocks of memory will be
+  locked between two used chunks, so they cannot be given back to
+  the system.
+
+  The `pad' argument to malloc_trim represents the amount of free
+  trailing space to leave untrimmed. If this argument is zero,
+  only the minimum amount of memory to maintain internal data
+  structures will be left (one page or less). Non-zero arguments
+  can be supplied to maintain enough trailing space to service
+  future expected allocations without having to re-obtain memory
+  from the system.
+
+  Malloc_trim returns 1 if it actually released any memory, else 0.
+  On systems that do not support "negative sbrks", it will always
+  rreturn 0.
+*/
+#if __STD_C
+int      public_mTRIm(size_t);
+#else
+int      public_mTRIm();
+#endif
+
+/*
+  malloc_usable_size(Void_t* p);
+
+  Returns the number of bytes you can actually use in
+  an allocated chunk, which may be more than you requested (although
+  often not) due to alignment and minimum size constraints.
+  You can use this many bytes without worrying about
+  overwriting other allocated objects. This is not a particularly great
+  programming practice. malloc_usable_size can be more useful in
+  debugging and assertions, for example:
+
+  p = malloc(n);
+  assert(malloc_usable_size(p) >= 256);
+
+*/
+#if __STD_C
+size_t   public_mUSABLe(Void_t*);
+#else
+size_t   public_mUSABLe();
+#endif
+
+/*
+  malloc_stats();
+  Prints on stderr the amount of space obtained from the system (both
+  via sbrk and mmap), the maximum amount (which may be more than
+  current if malloc_trim and/or munmap got called), and the current
+  number of bytes allocated via malloc (or realloc, etc) but not yet
+  freed. Note that this is the number of bytes allocated, not the
+  number requested. It will be larger than the number requested
+  because of alignment and bookkeeping overhead. Because it includes
+  alignment wastage as being in use, this figure may be greater than
+  zero even when no user-level chunks are allocated.
+
+  The reported current and maximum system memory can be inaccurate if
+  a program makes other calls to system memory allocation functions
+  (normally sbrk) outside of malloc.
+
+  malloc_stats prints only the most commonly interesting statistics.
+  More information can be obtained by calling mallinfo.
+
+*/
+#if __STD_C
+void     public_mSTATs(void);
+#else
+void     public_mSTATs();
+#endif
+
+/*
+  malloc_get_state(void);
+
+  Returns the state of all malloc variables in an opaque data
+  structure.
+*/
+#if __STD_C
+Void_t*  public_gET_STATe(void);
+#else
+Void_t*  public_gET_STATe();
+#endif
+
+/*
+  malloc_set_state(Void_t* state);
+
+  Restore the state of all malloc variables from data obtained with
+  malloc_get_state().
+*/
+#if __STD_C
+int      public_sET_STATe(Void_t*);
+#else
+int      public_sET_STATe();
+#endif
+
+#ifdef _LIBC
+/*
+  posix_memalign(void **memptr, size_t alignment, size_t size);
+
+  POSIX wrapper like memalign(), checking for validity of size.
+*/
+int      __posix_memalign(void **, size_t, size_t);
+#endif
+
+/* mallopt tuning options */
+
+/*
+  M_MXFAST is the maximum request size used for "fastbins", special bins
+  that hold returned chunks without consolidating their spaces. This
+  enables future requests for chunks of the same size to be handled
+  very quickly, but can increase fragmentation, and thus increase the
+  overall memory footprint of a program.
+
+  This malloc manages fastbins very conservatively yet still
+  efficiently, so fragmentation is rarely a problem for values less
+  than or equal to the default.  The maximum supported value of MXFAST
+  is 80. You wouldn't want it any higher than this anyway.  Fastbins
+  are designed especially for use with many small structs, objects or
+  strings -- the default handles structs/objects/arrays with sizes up
+  to 8 4byte fields, or small strings representing words, tokens,
+  etc. Using fastbins for larger objects normally worsens
+  fragmentation without improving speed.
+
+  M_MXFAST is set in REQUEST size units. It is internally used in
+  chunksize units, which adds padding and alignment.  You can reduce
+  M_MXFAST to 0 to disable all use of fastbins.  This causes the malloc
+  algorithm to be a closer approximation of fifo-best-fit in all cases,
+  not just for larger requests, but will generally cause it to be
+  slower.
+*/
+
+
+/* M_MXFAST is a standard SVID/XPG tuning option, usually listed in malloc.h */
+#ifndef M_MXFAST
+#define M_MXFAST            1
+#endif
+
+#ifndef DEFAULT_MXFAST
+#define DEFAULT_MXFAST     64
+#endif
+
+
+/*
+  M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
+  to keep before releasing via malloc_trim in free().
+
+  Automatic trimming is mainly useful in long-lived programs.
+  Because trimming via sbrk can be slow on some systems, and can
+  sometimes be wasteful (in cases where programs immediately
+  afterward allocate more large chunks) the value should be high
+  enough so that your overall system performance would improve by
+  releasing this much memory.
+
+  The trim threshold and the mmap control parameters (see below)
+  can be traded off with one another. Trimming and mmapping are
+  two different ways of releasing unused memory back to the
+  system. Between these two, it is often possible to keep
+  system-level demands of a long-lived program down to a bare
+  minimum. For example, in one test suite of sessions measuring
+  the XF86 X server on Linux, using a trim threshold of 128K and a
+  mmap threshold of 192K led to near-minimal long term resource
+  consumption.
+
+  If you are using this malloc in a long-lived program, it should
+  pay to experiment with these values.  As a rough guide, you
+  might set to a value close to the average size of a process
+  (program) running on your system.  Releasing this much memory
+  would allow such a process to run in memory.  Generally, it's
+  worth it to tune for trimming rather tham memory mapping when a
+  program undergoes phases where several large chunks are
+  allocated and released in ways that can reuse each other's
+  storage, perhaps mixed with phases where there are no such
+  chunks at all.  And in well-behaved long-lived programs,
+  controlling release of large blocks via trimming versus mapping
+  is usually faster.
+
+  However, in most programs, these parameters serve mainly as
+  protection against the system-level effects of carrying around
+  massive amounts of unneeded memory. Since frequent calls to
+  sbrk, mmap, and munmap otherwise degrade performance, the default
+  parameters are set to relatively high values that serve only as
+  safeguards.
+
+  The trim value It must be greater than page size to have any useful
+  effect.  To disable trimming completely, you can set to
+  (unsigned long)(-1)
+
+  Trim settings interact with fastbin (MXFAST) settings: Unless
+  TRIM_FASTBINS is defined, automatic trimming never takes place upon
+  freeing a chunk with size less than or equal to MXFAST. Trimming is
+  instead delayed until subsequent freeing of larger chunks. However,
+  you can still force an attempted trim by calling malloc_trim.
+
+  Also, trimming is not generally possible in cases where
+  the main arena is obtained via mmap.
+
+  Note that the trick some people use of mallocing a huge space and
+  then freeing it at program startup, in an attempt to reserve system
+  memory, doesn't have the intended effect under automatic trimming,
+  since that memory will immediately be returned to the system.
+*/
+
+#define M_TRIM_THRESHOLD       -1
+
+#ifndef DEFAULT_TRIM_THRESHOLD
+#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
+#endif
+
+/*
+  M_TOP_PAD is the amount of extra `padding' space to allocate or
+  retain whenever sbrk is called. It is used in two ways internally:
+
+  * When sbrk is called to extend the top of the arena to satisfy
+  a new malloc request, this much padding is added to the sbrk
+  request.
+
+  * When malloc_trim is called automatically from free(),
+  it is used as the `pad' argument.
+
+  In both cases, the actual amount of padding is rounded
+  so that the end of the arena is always a system page boundary.
+
+  The main reason for using padding is to avoid calling sbrk so
+  often. Having even a small pad greatly reduces the likelihood
+  that nearly every malloc request during program start-up (or
+  after trimming) will invoke sbrk, which needlessly wastes
+  time.
+
+  Automatic rounding-up to page-size units is normally sufficient
+  to avoid measurable overhead, so the default is 0.  However, in
+  systems where sbrk is relatively slow, it can pay to increase
+  this value, at the expense of carrying around more memory than
+  the program needs.
+*/
+
+#define M_TOP_PAD              -2
+
+#ifndef DEFAULT_TOP_PAD
+#define DEFAULT_TOP_PAD        (0)
+#endif
+
+/*
+  M_MMAP_THRESHOLD is the request size threshold for using mmap()
+  to service a request. Requests of at least this size that cannot
+  be allocated using already-existing space will be serviced via mmap.
+  (If enough normal freed space already exists it is used instead.)
+
+  Using mmap segregates relatively large chunks of memory so that
+  they can be individually obtained and released from the host
+  system. A request serviced through mmap is never reused by any
+  other request (at least not directly; the system may just so
+  happen to remap successive requests to the same locations).
+
+  Segregating space in this way has the benefits that:
+
+   1. Mmapped space can ALWAYS be individually released back
+      to the system, which helps keep the system level memory
+      demands of a long-lived program low.
+   2. Mapped memory can never become `locked' between
+      other chunks, as can happen with normally allocated chunks, which
+      means that even trimming via malloc_trim would not release them.
+   3. On some systems with "holes" in address spaces, mmap can obtain
+      memory that sbrk cannot.
+
+  However, it has the disadvantages that:
+
+   1. The space cannot be reclaimed, consolidated, and then
+      used to service later requests, as happens with normal chunks.
+   2. It can lead to more wastage because of mmap page alignment
+      requirements
+   3. It causes malloc performance to be more dependent on host
+      system memory management support routines which may vary in
+      implementation quality and may impose arbitrary
+      limitations. Generally, servicing a request via normal
+      malloc steps is faster than going through a system's mmap.
+
+  The advantages of mmap nearly always outweigh disadvantages for
+  "large" chunks, but the value of "large" varies across systems.  The
+  default is an empirically derived value that works well in most
+  systems.
+*/
+
+#define M_MMAP_THRESHOLD      -3
+
+#ifndef DEFAULT_MMAP_THRESHOLD
+#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
+#endif
+
+/*
+  M_MMAP_MAX is the maximum number of requests to simultaneously
+  service using mmap. This parameter exists because
+  some systems have a limited number of internal tables for
+  use by mmap, and using more than a few of them may degrade
+  performance.
+
+  The default is set to a value that serves only as a safeguard.
+  Setting to 0 disables use of mmap for servicing large requests.  If
+  HAVE_MMAP is not set, the default value is 0, and attempts to set it
+  to non-zero values in mallopt will fail.
+*/
+
+#define M_MMAP_MAX             -4
+
+#ifndef DEFAULT_MMAP_MAX
+#if HAVE_MMAP
+#define DEFAULT_MMAP_MAX       (65536)
+#else
+#define DEFAULT_MMAP_MAX       (0)
+#endif
+#endif
+
+#ifdef __cplusplus
+};  /* end of extern "C" */
+#endif
+
+#include <cvmx-spinlock.h>
+#include "malloc.h"
+#include "thread-m.h"
+
+#ifdef DEBUG_PRINTS
+#define debug_printf    printf
+#else
+#define debug_printf(format, args...)  
+#endif
+
+#ifndef BOUNDED_N
+#define BOUNDED_N(ptr, sz) (ptr)
+#endif
+#ifndef RETURN_ADDRESS
+#define RETURN_ADDRESS(X_) (NULL)
+#endif
+
+/* On some platforms we can compile internal, not exported functions better.
+   Let the environment provide a macro and define it to be empty if it
+   is not available.  */
+#ifndef internal_function
+# define internal_function
+#endif
+
+/* Forward declarations.  */
+struct malloc_chunk;
+typedef struct malloc_chunk* mchunkptr;
+
+/* Internal routines.  */
+
+#if __STD_C
+
+static Void_t*         _int_malloc(mstate, size_t);
+static void            _int_free(mstate, Void_t*);
+static Void_t*         _int_realloc(mstate, Void_t*, size_t);
+static Void_t*         _int_memalign(mstate, size_t, size_t);
+static Void_t*         _int_valloc(mstate, size_t);
+static Void_t*  _int_pvalloc(mstate, size_t);
+static Void_t*  cALLOc(cvmx_arena_list_t arena_list, size_t, size_t);
+static Void_t** _int_icalloc(mstate, size_t, size_t, Void_t**);
+static Void_t** _int_icomalloc(mstate, size_t, size_t*, Void_t**);
+static int      mTRIm(size_t);
+static size_t   mUSABLe(Void_t*);
+static void     mSTATs(void);
+static int      mALLOPt(int, int);
+static struct mallinfo mALLINFo(mstate);
+
+static Void_t* internal_function mem2mem_check(Void_t *p, size_t sz);
+static int internal_function top_check(void);
+static void internal_function munmap_chunk(mchunkptr p);
+#if HAVE_MREMAP
+static mchunkptr internal_function mremap_chunk(mchunkptr p, size_t new_size);
+#endif
+
+static Void_t*   malloc_check(size_t sz, const Void_t *caller);
+static void      free_check(Void_t* mem, const Void_t *caller);
+static Void_t*   realloc_check(Void_t* oldmem, size_t bytes,
+			       const Void_t *caller);
+static Void_t*   memalign_check(size_t alignment, size_t bytes,
+				const Void_t *caller);
+#ifndef NO_THREADS
+static Void_t*   malloc_starter(size_t sz, const Void_t *caller);
+static void      free_starter(Void_t* mem, const Void_t *caller);
+static Void_t*   malloc_atfork(size_t sz, const Void_t *caller);
+static void      free_atfork(Void_t* mem, const Void_t *caller);
+#endif
+
+#else
+
+Void_t*         _int_malloc();
+void            _int_free();
+Void_t*         _int_realloc();
+Void_t*         _int_memalign();
+Void_t*         _int_valloc();
+Void_t*         _int_pvalloc();
+/*static Void_t*  cALLOc();*/
+static Void_t** _int_icalloc();
+static Void_t** _int_icomalloc();
+static int      mTRIm();
+static size_t   mUSABLe();
+static void     mSTATs();
+static int      mALLOPt();
+static struct mallinfo mALLINFo();
+
+#endif
+
+
+
+
+/* ------------- Optional versions of memcopy ---------------- */
+
+
+#if USE_MEMCPY
+
+/*
+  Note: memcpy is ONLY invoked with non-overlapping regions,
+  so the (usually slower) memmove is not needed.
+*/
+
+#define MALLOC_COPY(dest, src, nbytes)  memcpy(dest, src, nbytes)
+#define MALLOC_ZERO(dest, nbytes)       memset(dest, 0,   nbytes)
+
+#else /* !USE_MEMCPY */
+
+/* Use Duff's device for good zeroing/copying performance. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
+  unsigned long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T);                     \
+  long mcn;                                                                   \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mzp++ = 0;                                             \
+    case 7:           *mzp++ = 0;                                             \
+    case 6:           *mzp++ = 0;                                             \
+    case 5:           *mzp++ = 0;                                             \
+    case 4:           *mzp++ = 0;                                             \
+    case 3:           *mzp++ = 0;                                             \
+    case 2:           *mzp++ = 0;                                             \
+    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
+  }                                                                           \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
+  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
+  unsigned long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T);                     \
+  long mcn;                                                                   \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
+    case 7:           *mcdst++ = *mcsrc++;                                    \
+    case 6:           *mcdst++ = *mcsrc++;                                    \
+    case 5:           *mcdst++ = *mcsrc++;                                    \
+    case 4:           *mcdst++ = *mcsrc++;                                    \
+    case 3:           *mcdst++ = *mcsrc++;                                    \
+    case 2:           *mcdst++ = *mcsrc++;                                    \
+    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
+  }                                                                           \
+} while(0)
+
+#endif
+
+/* ------------------ MMAP support ------------------  */
+
+
+#if HAVE_MMAP
+
+#include <fcntl.h>
+#ifndef LACKS_SYS_MMAN_H
+#include <sys/mman.h>
+#endif
+
+#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
+# define MAP_ANONYMOUS MAP_ANON
+#endif
+#if !defined(MAP_FAILED)
+# define MAP_FAILED ((char*)-1)
+#endif
+
+#ifndef MAP_NORESERVE
+# ifdef MAP_AUTORESRV
+#  define MAP_NORESERVE MAP_AUTORESRV
+# else
+#  define MAP_NORESERVE 0
+# endif
+#endif
+
+/*
+   Nearly all versions of mmap support MAP_ANONYMOUS,
+   so the following is unlikely to be needed, but is
+   supplied just in case.
+*/
+
+#ifndef MAP_ANONYMOUS
+
+static int dev_zero_fd = -1; /* Cached file descriptor for /dev/zero. */
+
+#define MMAP(addr, size, prot, flags) ((dev_zero_fd < 0) ? \
+ (dev_zero_fd = open("/dev/zero", O_RDWR), \
+  mmap((addr), (size), (prot), (flags), dev_zero_fd, 0)) : \
+   mmap((addr), (size), (prot), (flags), dev_zero_fd, 0))
+
+#else
+
+#define MMAP(addr, size, prot, flags) \
+ (mmap((addr), (size), (prot), (flags)|MAP_ANONYMOUS, -1, 0))
+
+#endif
+
+
+#endif /* HAVE_MMAP */
+
+
+/*
+  -----------------------  Chunk representations -----------------------
+*/
+
+
+/*
+  This struct declaration is misleading (but accurate and necessary).
+  It declares a "view" into memory allowing access to necessary
+  fields at known offsets from a given base. See explanation below.
+*/
+struct malloc_chunk {
+
+  INTERNAL_SIZE_T      prev_size;  /* Size of previous chunk (if free).  */
+  INTERNAL_SIZE_T      size;       /* Size in bytes, including overhead. */
+  mstate               arena_ptr;  /* ptr to arena chunk belongs to */
+
+  struct malloc_chunk* fd;         /* double links -- used only if free. */
+  struct malloc_chunk* bk;
+};
+
+
+/*
+   malloc_chunk details:
+
+    (The following includes lightly edited explanations by Colin Plumb.)
+
+    Chunks of memory are maintained using a `boundary tag' method as
+    described in e.g., Knuth or Standish.  (See the paper by Paul
+    Wilson ftp://ftp.cs.utexas.edu/pub/garbage/allocsrv.ps for a
+    survey of such techniques.)  Sizes of free chunks are stored both
+    in the front of each chunk and at the end.  This makes
+    consolidating fragmented chunks into bigger chunks very fast.  The
+    size fields also hold bits representing whether chunks are free or
+    in use.
+
+    An allocated chunk looks like this:
+
+
+    chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of previous chunk, if allocated            | |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of chunk, in bytes                         |P|
+      mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             User data starts here...                          .
+            .                                                               .
+            .             (malloc_usable_space() bytes)                     .
+            .                                                               |
+nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of chunk                                     |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+
+
+    Where "chunk" is the front of the chunk for the purpose of most of
+    the malloc code, but "mem" is the pointer that is returned to the
+    user.  "Nextchunk" is the beginning of the next contiguous chunk.
+
+    Chunks always begin on even word boundries, so the mem portion
+    (which is returned to the user) is also on an even word boundary, and
+    thus at least double-word aligned.
+
+    Free chunks are stored in circular doubly-linked lists, and look like this:
+
+    chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Size of previous chunk                            |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+    `head:' |             Size of chunk, in bytes                         |P|
+      mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Forward pointer to next chunk in list             |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Back pointer to previous chunk in list            |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+            |             Unused space (may be 0 bytes long)                .
+            .                                                               .
+            .                                                               |
+nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+    `foot:' |             Size of chunk, in bytes                           |
+            +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+
+    The P (PREV_INUSE) bit, stored in the unused low-order bit of the
+    chunk size (which is always a multiple of two words), is an in-use
+    bit for the *previous* chunk.  If that bit is *clear*, then the
+    word before the current chunk size contains the previous chunk
+    size, and can be used to find the front of the previous chunk.
+    The very first chunk allocated always has this bit set,
+    preventing access to non-existent (or non-owned) memory. If
+    prev_inuse is set for any given chunk, then you CANNOT determine
+    the size of the previous chunk, and might even get a memory
+    addressing fault when trying to do so.
+
+    Note that the `foot' of the current chunk is actually represented
+    as the prev_size of the NEXT chunk. This makes it easier to
+    deal with alignments etc but can be very confusing when trying
+    to extend or adapt this code.
+
+    The two exceptions to all this are
+
+     1. The special chunk `top' doesn't bother using the
+        trailing size field since there is no next contiguous chunk
+        that would have to index off it. After initialization, `top'
+        is forced to always exist.  If it would become less than
+        MINSIZE bytes long, it is replenished.
+
+     2. Chunks allocated via mmap, which have the second-lowest-order
+        bit (IS_MMAPPED) set in their size fields.  Because they are
+        allocated one-by-one, each must contain its own trailing size field.
+
+*/
+
+/*
+  ---------- Size and alignment checks and conversions ----------
+*/
+
+/* conversion from malloc headers to user pointers, and back */
+/* Added size for pointer to make room for arena_ptr */
+#define chunk2mem(p)   ((Void_t*)((char*)(p) + 2*SIZE_SZ + sizeof(void *)))
+#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - 2*SIZE_SZ - sizeof(void *)))
+
+/* The smallest possible chunk */
+#define MIN_CHUNK_SIZE        (sizeof(struct malloc_chunk))
+
+/* The smallest size we can malloc is an aligned minimal chunk */
+
+#define MINSIZE  \
+  (unsigned long)(((MIN_CHUNK_SIZE+MALLOC_ALIGN_MASK) & ~MALLOC_ALIGN_MASK))
+
+/* Check if m has acceptable alignment */
+
+#define aligned_OK(m)  (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0)
+
+
+/*
+   Check if a request is so large that it would wrap around zero when
+   padded and aligned. To simplify some other code, the bound is made
+   low enough so that adding MINSIZE will also not wrap around zero.
+*/
+
+#define REQUEST_OUT_OF_RANGE(req)                                 \
+  ((unsigned long)(req) >=                                        \
+   (unsigned long)(INTERNAL_SIZE_T)(-2 * MINSIZE))
+
+/* pad request bytes into a usable size -- internal version */
+
+
+/* prev_size field of next chunk is overwritten with data
+** when in use.  NOTE - last SIZE_SZ of arena must be left
+** unused for last chunk to use
+*/
+/* Added sizeof(void *) to make room for arena_ptr */
+#define request2size(req)                                         \
+  (((req) + sizeof(void *) + SIZE_SZ + MALLOC_ALIGN_MASK < MINSIZE)  ?             \
+   MINSIZE :                                                      \
+   ((req) + sizeof(void *) + SIZE_SZ + MALLOC_ALIGN_MASK) & ~MALLOC_ALIGN_MASK)
+
+/*  Same, except also perform argument check */
+
+#define checked_request2size(req, sz)                             \
+  if (REQUEST_OUT_OF_RANGE(req)) {                                \
+    MALLOC_FAILURE_ACTION;                                        \
+    return 0;                                                     \
+  }                                                               \
+  (sz) = request2size(req);
+
+/*
+  --------------- Physical chunk operations ---------------
+*/
+
+
+/* size field is or'ed with PREV_INUSE when previous adjacent chunk in use */
+#define PREV_INUSE 0x1
+
+/* extract inuse bit of previous chunk */
+#define prev_inuse(p)       ((p)->size & PREV_INUSE)
+
+
+/* size field is or'ed with IS_MMAPPED if the chunk was obtained with mmap() */
+#define IS_MMAPPED 0x2
+
+/* check for mmap()'ed chunk */
+#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
+
+
+
+/*
+  Bits to mask off when extracting size
+
+  Note: IS_MMAPPED is intentionally not masked off from size field in
+  macros for which mmapped chunks should never be seen. This should
+  cause helpful core dumps to occur if it is tried by accident by
+  people extending or adapting this malloc.
+*/
+#define SIZE_BITS (PREV_INUSE|IS_MMAPPED)
+
+/* Get size, ignoring use bits */
+#define chunksize(p)         ((p)->size & ~(SIZE_BITS))
+
+
+/* Ptr to next physical malloc_chunk. */
+#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~SIZE_BITS) ))
+
+/* Ptr to previous physical malloc_chunk */
+#define prev_chunk(p) ((mchunkptr)( ((char*)(p)) - ((p)->prev_size) ))
+
+/* Treat space at ptr + offset as a chunk */
+#define chunk_at_offset(p, s)  ((mchunkptr)(((char*)(p)) + (s)))
+
+/* extract p's inuse bit */
+#define inuse(p)\
+((((mchunkptr)(((char*)(p))+((p)->size & ~SIZE_BITS)))->size) & PREV_INUSE)
+
+/* set/clear chunk as being inuse without otherwise disturbing */
+#define set_inuse(p)\
+((mchunkptr)(((char*)(p)) + ((p)->size & ~SIZE_BITS)))->size |= PREV_INUSE
+
+#define clear_inuse(p)\
+((mchunkptr)(((char*)(p)) + ((p)->size & ~SIZE_BITS)))->size &= ~(PREV_INUSE)
+
+
+/* check/set/clear inuse bits in known places */
+#define inuse_bit_at_offset(p, s)\
+ (((mchunkptr)(((char*)(p)) + (s)))->size & PREV_INUSE)
+
+#define set_inuse_bit_at_offset(p, s)\
+ (((mchunkptr)(((char*)(p)) + (s)))->size |= PREV_INUSE)
+
+#define clear_inuse_bit_at_offset(p, s)\
+ (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE))
+
+
+/* Set size at head, without disturbing its use bit */
+#define set_head_size(p, s)  ((p)->size = (((p)->size & SIZE_BITS) | (s)))
+
+/* Set size/use field */
+#define set_head(p, s)       ((p)->size = (s))
+
+/* Set size at footer (only when chunk is not in use) */
+#define set_foot(p, s)       (((mchunkptr)((char*)(p) + (s)))->prev_size = (s))
+
+
+/*
+  -------------------- Internal data structures --------------------
+
+   All internal state is held in an instance of malloc_state defined
+   below. There are no other static variables, except in two optional
+   cases:
+   * If USE_MALLOC_LOCK is defined, the mALLOC_MUTEx declared above.
+   * If HAVE_MMAP is true, but mmap doesn't support
+     MAP_ANONYMOUS, a dummy file descriptor for mmap.
+
+   Beware of lots of tricks that minimize the total bookkeeping space
+   requirements. The result is a little over 1K bytes (for 4byte
+   pointers and size_t.)
+*/
+
+/*
+  Bins
+
+    An array of bin headers for free chunks. Each bin is doubly
+    linked.  The bins are approximately proportionally (log) spaced.
+    There are a lot of these bins (128). This may look excessive, but
+    works very well in practice.  Most bins hold sizes that are
+    unusual as malloc request sizes, but are more usual for fragments
+    and consolidated sets of chunks, which is what these bins hold, so
+    they can be found quickly.  All procedures maintain the invariant
+    that no consolidated chunk physically borders another one, so each
+    chunk in a list is known to be preceeded and followed by either
+    inuse chunks or the ends of memory.
+
+    Chunks in bins are kept in size order, with ties going to the
+    approximately least recently used chunk. Ordering isn't needed
+    for the small bins, which all contain the same-sized chunks, but
+    facilitates best-fit allocation for larger chunks. These lists
+    are just sequential. Keeping them in order almost never requires
+    enough traversal to warrant using fancier ordered data
+    structures.
+
+    Chunks of the same size are linked with the most
+    recently freed at the front, and allocations are taken from the
+    back.  This results in LRU (FIFO) allocation order, which tends
+    to give each chunk an equal opportunity to be consolidated with
+    adjacent freed chunks, resulting in larger free chunks and less
+    fragmentation.
+
+    To simplify use in double-linked lists, each bin header acts
+    as a malloc_chunk. This avoids special-casing for headers.
+    But to conserve space and improve locality, we allocate
+    only the fd/bk pointers of bins, and then use repositioning tricks
+    to treat these as the fields of a malloc_chunk*.
+*/
+
+typedef struct malloc_chunk* mbinptr;
+
+/* addressing -- note that bin_at(0) does not exist */
+#define bin_at(m, i) ((mbinptr)((char*)&((m)->bins[(i)<<1]) - (SIZE_SZ<<1)))
+
+/* analog of ++bin */
+#define next_bin(b)  ((mbinptr)((char*)(b) + (sizeof(mchunkptr)<<1)))
+
+/* Reminders about list directionality within bins */
+#define first(b)     ((b)->fd)
+#define last(b)      ((b)->bk)
+
+/* Take a chunk off a bin list */
+#define unlink(P, BK, FD) {                                            \
+  FD = P->fd;                                                          \
+  BK = P->bk;                                                          \
+  FD->bk = BK;                                                         \
+  BK->fd = FD;                                                         \
+}
+
+/*
+  Indexing
+
+    Bins for sizes < 512 bytes contain chunks of all the same size, spaced
+    8 bytes apart. Larger bins are approximately logarithmically spaced:
+
+    64 bins of size       8
+    32 bins of size      64
+    16 bins of size     512
+     8 bins of size    4096
+     4 bins of size   32768
+     2 bins of size  262144
+     1 bin  of size what's left
+
+    There is actually a little bit of slop in the numbers in bin_index
+    for the sake of speed. This makes no difference elsewhere.
+
+    The bins top out around 1MB because we expect to service large
+    requests via mmap.
+*/
+
+#define NBINS             128
+#define NSMALLBINS         64
+#define SMALLBIN_WIDTH      8
+#define MIN_LARGE_SIZE    512
+
+#define in_smallbin_range(sz)  \
+  ((unsigned long)(sz) < (unsigned long)MIN_LARGE_SIZE)
+
+#define smallbin_index(sz)     (((unsigned)(sz)) >> 3)
+
+#define largebin_index(sz)                                                   \
+(((((unsigned long)(sz)) >>  6) <= 32)?  56 + (((unsigned long)(sz)) >>  6): \
+ ((((unsigned long)(sz)) >>  9) <= 20)?  91 + (((unsigned long)(sz)) >>  9): \
+ ((((unsigned long)(sz)) >> 12) <= 10)? 110 + (((unsigned long)(sz)) >> 12): \
+ ((((unsigned long)(sz)) >> 15) <=  4)? 119 + (((unsigned long)(sz)) >> 15): \
+ ((((unsigned long)(sz)) >> 18) <=  2)? 124 + (((unsigned long)(sz)) >> 18): \
+                                        126)
+
+#define bin_index(sz) \
+ ((in_smallbin_range(sz)) ? smallbin_index(sz) : largebin_index(sz))
+
+/*
+  FIRST_SORTED_BIN_SIZE is the chunk size corresponding to the
+  first bin that is maintained in sorted order. This must
+  be the smallest size corresponding to a given bin.
+
+  Normally, this should be MIN_LARGE_SIZE. But you can weaken
+  best fit guarantees to sometimes speed up malloc by increasing value.
+  Doing this means that malloc may choose a chunk that is 
+  non-best-fitting by up to the width of the bin.
+
+  Some useful cutoff values:
+      512 - all bins sorted
+     2560 - leaves bins <=     64 bytes wide unsorted  
+    12288 - leaves bins <=    512 bytes wide unsorted
+    65536 - leaves bins <=   4096 bytes wide unsorted
+   262144 - leaves bins <=  32768 bytes wide unsorted
+       -1 - no bins sorted (not recommended!)
+*/
+
+#define FIRST_SORTED_BIN_SIZE MIN_LARGE_SIZE 
+/* #define FIRST_SORTED_BIN_SIZE 65536 */
+
+/*
+  Unsorted chunks
+
+    All remainders from chunk splits, as well as all returned chunks,
+    are first placed in the "unsorted" bin. They are then placed
+    in regular bins after malloc gives them ONE chance to be used before
+    binning. So, basically, the unsorted_chunks list acts as a queue,
+    with chunks being placed on it in free (and malloc_consolidate),
+    and taken off (to be either used or placed in bins) in malloc.
+
+    The NON_MAIN_ARENA flag is never set for unsorted chunks, so it
+    does not have to be taken into account in size comparisons.
+*/
+
+/* The otherwise unindexable 1-bin is used to hold unsorted chunks. */
+#define unsorted_chunks(M)          (bin_at(M, 1))
+
+/*
+  Top
+
+    The top-most available chunk (i.e., the one bordering the end of
+    available memory) is treated specially. It is never included in
+    any bin, is used only if no other chunk is available, and is
+    released back to the system if it is very large (see
+    M_TRIM_THRESHOLD).  Because top initially
+    points to its own bin with initial zero size, thus forcing
+    extension on the first malloc request, we avoid having any special
+    code in malloc to check whether it even exists yet. But we still
+    need to do so when getting memory from system, so we make
+    initial_top treat the bin as a legal but unusable chunk during the
+    interval between initialization and the first call to
+    sYSMALLOc. (This is somewhat delicate, since it relies on
+    the 2 preceding words to be zero during this interval as well.)
+*/
+
+/* Conveniently, the unsorted bin can be used as dummy top on first call */
+#define initial_top(M)              (unsorted_chunks(M))
+
+/*
+  Binmap
+
+    To help compensate for the large number of bins, a one-level index
+    structure is used for bin-by-bin searching.  `binmap' is a
+    bitvector recording whether bins are definitely empty so they can
+    be skipped over during during traversals.  The bits are NOT always
+    cleared as soon as bins are empty, but instead only
+    when they are noticed to be empty during traversal in malloc.
+*/
+
+/* Conservatively use 32 bits per map word, even if on 64bit system */
+#define BINMAPSHIFT      5
+#define BITSPERMAP       (1U << BINMAPSHIFT)
+#define BINMAPSIZE       (NBINS / BITSPERMAP)
+
+#define idx2block(i)     ((i) >> BINMAPSHIFT)
+#define idx2bit(i)       ((1U << ((i) & ((1U << BINMAPSHIFT)-1))))
+
+#define mark_bin(m,i)    ((m)->binmap[idx2block(i)] |=  idx2bit(i))
+#define unmark_bin(m,i)  ((m)->binmap[idx2block(i)] &= ~(idx2bit(i)))
+#define get_binmap(m,i)  ((m)->binmap[idx2block(i)] &   idx2bit(i))
+
+/*
+  Fastbins
+
+    An array of lists holding recently freed small chunks.  Fastbins
+    are not doubly linked.  It is faster to single-link them, and
+    since chunks are never removed from the middles of these lists,
+    double linking is not necessary. Also, unlike regular bins, they
+    are not even processed in FIFO order (they use faster LIFO) since
+    ordering doesn't much matter in the transient contexts in which
+    fastbins are normally used.
+
+    Chunks in fastbins keep their inuse bit set, so they cannot
+    be consolidated with other free chunks. malloc_consolidate
+    releases all chunks in fastbins and consolidates them with
+    other free chunks.
+*/
+
+typedef struct malloc_chunk* mfastbinptr;
+
+/* offset 2 to use otherwise unindexable first 2 bins */
+#define fastbin_index(sz)        ((int)((((unsigned int)(sz)) >> 3) - 2))
+
+/* The maximum fastbin request size we support */
+#define MAX_FAST_SIZE     80
+
+#define NFASTBINS  (fastbin_index(request2size(MAX_FAST_SIZE))+1)
+
+/*
+  FASTBIN_CONSOLIDATION_THRESHOLD is the size of a chunk in free()
+  that triggers automatic consolidation of possibly-surrounding
+  fastbin chunks. This is a heuristic, so the exact value should not
+  matter too much. It is defined at half the default trim threshold as a
+  compromise heuristic to only attempt consolidation if it is likely
+  to lead to trimming. However, it is not dynamically tunable, since
+  consolidation reduces fragmentation surrounding large chunks even
+  if trimming is not used.
+*/
+
+#define FASTBIN_CONSOLIDATION_THRESHOLD  (65536UL)
+
+/*
+  Since the lowest 2 bits in max_fast don't matter in size comparisons,
+  they are used as flags.
+*/
+
+/*
+  FASTCHUNKS_BIT held in max_fast indicates that there are probably
+  some fastbin chunks. It is set true on entering a chunk into any
+  fastbin, and cleared only in malloc_consolidate.
+
+  The truth value is inverted so that have_fastchunks will be true
+  upon startup (since statics are zero-filled), simplifying
+  initialization checks.
+*/
+
+#define FASTCHUNKS_BIT        (1U)
+
+#define have_fastchunks(M)     (((M)->max_fast &  FASTCHUNKS_BIT) == 0)
+#define clear_fastchunks(M)    ((M)->max_fast |=  FASTCHUNKS_BIT)
+#define set_fastchunks(M)      ((M)->max_fast &= ~FASTCHUNKS_BIT)
+
+/*
+  NONCONTIGUOUS_BIT indicates that MORECORE does not return contiguous
+  regions.  Otherwise, contiguity is exploited in merging together,
+  when possible, results from consecutive MORECORE calls.
+
+  The initial value comes from MORECORE_CONTIGUOUS, but is
+  changed dynamically if mmap is ever used as an sbrk substitute.
+*/
+
+#define NONCONTIGUOUS_BIT     (2U)
+
+#define contiguous(M)          (((M)->max_fast &  NONCONTIGUOUS_BIT) == 0)
+#define noncontiguous(M)       (((M)->max_fast &  NONCONTIGUOUS_BIT) != 0)
+#define set_noncontiguous(M)   ((M)->max_fast |=  NONCONTIGUOUS_BIT)
+#define set_contiguous(M)      ((M)->max_fast &= ~NONCONTIGUOUS_BIT)
+
+/*
+   Set value of max_fast.
+   Use impossibly small value if 0.
+   Precondition: there are no existing fastbin chunks.
+   Setting the value clears fastchunk bit but preserves noncontiguous bit.
+*/
+
+#define set_max_fast(M, s) \
+  (M)->max_fast = (((s) == 0)? SMALLBIN_WIDTH: request2size(s)) | \
+  FASTCHUNKS_BIT | \
+  ((M)->max_fast &  NONCONTIGUOUS_BIT)
+
+
+/*
+   ----------- Internal state representation and initialization -----------
+*/
+
+struct malloc_state {
+  /* Serialize access.  */
+  mutex_t mutex;
+
+  /* Statistics for locking.  Only used if THREAD_STATS is defined.  */
+  long stat_lock_direct, stat_lock_loop, stat_lock_wait;
+  long pad0_[1]; /* try to give the mutex its own cacheline */
+
+  /* The maximum chunk size to be eligible for fastbin */
+  INTERNAL_SIZE_T  max_fast;   /* low 2 bits used as flags */
+
+  /* Fastbins */
+  mfastbinptr      fastbins[NFASTBINS];
+
+  /* Base of the topmost chunk -- not otherwise kept in a bin */
+  mchunkptr        top;
+
+  /* The remainder from the most recent split of a small request */
+  mchunkptr        last_remainder;
+
+  /* Normal bins packed as described above */
+  mchunkptr        bins[NBINS * 2];
+
+  /* Bitmap of bins */
+  unsigned int     binmap[BINMAPSIZE];
+
+  /* Linked list */
+  struct malloc_state *next;
+
+  /* Memory allocated from the system in this arena.  */
+  INTERNAL_SIZE_T system_mem;
+  INTERNAL_SIZE_T max_system_mem;
+};
+
+struct malloc_par {
+  /* Tunable parameters */
+  unsigned long    trim_threshold;
+  INTERNAL_SIZE_T  top_pad;
+  INTERNAL_SIZE_T  mmap_threshold;
+
+  /* Memory map support */
+  int              n_mmaps;
+  int              n_mmaps_max;
+  int              max_n_mmaps;
+
+  /* Cache malloc_getpagesize */
+  unsigned int     pagesize;
+
+  /* Statistics */
+  INTERNAL_SIZE_T  mmapped_mem;
+  /*INTERNAL_SIZE_T  sbrked_mem;*/
+  /*INTERNAL_SIZE_T  max_sbrked_mem;*/
+  INTERNAL_SIZE_T  max_mmapped_mem;
+  INTERNAL_SIZE_T  max_total_mem; /* only kept for NO_THREADS */
+
+  /* First address handed out by MORECORE/sbrk.  */
+  char*            sbrk_base;
+};
+
+/* There are several instances of this struct ("arenas") in this
+   malloc.  If you are adapting this malloc in a way that does NOT use
+   a static or mmapped malloc_state, you MUST explicitly zero-fill it
+   before using. This malloc relies on the property that malloc_state
+   is initialized to all zeroes (as is true of C statics).  */
+
+
+
+/*
+  Initialize a malloc_state struct.
+
+  This is called only from within malloc_consolidate, which needs
+  be called in the same contexts anyway.  It is never called directly
+  outside of malloc_consolidate because some optimizing compilers try
+  to inline it at all call points, which turns out not to be an
+  optimization at all. (Inlining it in malloc_consolidate is fine though.)
+*/
+
+#if __STD_C
+static void malloc_init_state(mstate av)
+#else
+static void malloc_init_state(av) mstate av;
+#endif
+{
+  int     i;
+  mbinptr bin;
+
+  /* Establish circular links for normal bins */
+  for (i = 1; i < NBINS; ++i) {
+    bin = bin_at(av,i);
+    bin->fd = bin->bk = bin;
+  }
+
+  set_noncontiguous(av);
+
+  set_max_fast(av, DEFAULT_MXFAST);
+
+  av->top            = initial_top(av);
+}
+
+/*
+   Other internal utilities operating on mstates
+*/
+
+#if __STD_C
+static Void_t*  sYSMALLOc(INTERNAL_SIZE_T, mstate);
+static void     malloc_consolidate(mstate);
+//static Void_t** iALLOc(mstate, size_t, size_t*, int, Void_t**);
+#else
+static Void_t*  sYSMALLOc();
+static void     malloc_consolidate();
+static Void_t** iALLOc();
+#endif
+
+/* ------------------- Support for multiple arenas -------------------- */
+#include "arena.c"
+
+/*
+  Debugging support
+
+  These routines make a number of assertions about the states
+  of data structures that should be true at all times. If any
+  are not true, it's very likely that a user program has somehow
+  trashed memory. (It's also possible that there is a coding error
+  in malloc. In which case, please report it!)
+*/
+
+#if ! MALLOC_DEBUG
+
+#define check_chunk(A,P)
+#define check_free_chunk(A,P)
+#define check_inuse_chunk(A,P)
+#define check_remalloced_chunk(A,P,N)
+#define check_malloced_chunk(A,P,N)
+#define check_malloc_state(A)
+
+#else
+
+#define check_chunk(A,P)              do_check_chunk(A,P)
+#define check_free_chunk(A,P)         do_check_free_chunk(A,P)
+#define check_inuse_chunk(A,P)        do_check_inuse_chunk(A,P)
+#define check_remalloced_chunk(A,P,N) do_check_remalloced_chunk(A,P,N)
+#define check_malloced_chunk(A,P,N)   do_check_malloced_chunk(A,P,N)
+#define check_malloc_state(A)         do_check_malloc_state(A)
+
+/*
+  Properties of all chunks
+*/
+
+#if __STD_C
+static void do_check_chunk(mstate av, mchunkptr p)
+#else
+static void do_check_chunk(av, p) mstate av; mchunkptr p;
+#endif
+{
+  unsigned long sz = chunksize(p);
+  /* min and max possible addresses assuming contiguous allocation */
+  char* max_address = (char*)(av->top) + chunksize(av->top);
+  char* min_address = max_address - av->system_mem;
+
+  if (!chunk_is_mmapped(p)) {
+
+    /* Has legal address ... */
+    if (p != av->top) {
+      if (contiguous(av)) {
+        assert(((char*)p) >= min_address);
+        assert(((char*)p + sz) <= ((char*)(av->top)));
+      }
+    }
+    else {
+      /* top size is always at least MINSIZE */
+      assert((unsigned long)(sz) >= MINSIZE);
+      /* top predecessor always marked inuse */
+      assert(prev_inuse(p));
+    }
+
+  }
+  else {
+#if HAVE_MMAP
+    /* address is outside main heap  */
+    if (contiguous(av) && av->top != initial_top(av)) {
+      assert(((char*)p) < min_address || ((char*)p) > max_address);
+    }
+    /* chunk is page-aligned */
+    assert(((p->prev_size + sz) & (mp_.pagesize-1)) == 0);
+    /* mem is aligned */
+    assert(aligned_OK(chunk2mem(p)));
+#else
+    /* force an appropriate assert violation if debug set */
+    assert(!chunk_is_mmapped(p));
+#endif
+  }
+}
+
+/*
+  Properties of free chunks
+*/
+
+#if __STD_C
+static void do_check_free_chunk(mstate av, mchunkptr p)
+#else
+static void do_check_free_chunk(av, p) mstate av; mchunkptr p;
+#endif
+{
+  INTERNAL_SIZE_T sz = p->size & ~(PREV_INUSE);
+  mchunkptr next = chunk_at_offset(p, sz);
+
+  do_check_chunk(av, p);
+
+  /* Chunk must claim to be free ... */
+  assert(!inuse(p));
+  assert (!chunk_is_mmapped(p));
+
+  /* Unless a special marker, must have OK fields */
+  if ((unsigned long)(sz) >= MINSIZE)
+  {
+    assert((sz & MALLOC_ALIGN_MASK) == 0);
+    assert(aligned_OK(chunk2mem(p)));
+    /* ... matching footer field */
+    assert(next->prev_size == sz);
+    /* ... and is fully consolidated */
+    assert(prev_inuse(p));
+    assert (next == av->top || inuse(next));
+
+    /* ... and has minimally sane links */
+    assert(p->fd->bk == p);
+    assert(p->bk->fd == p);
+  }
+  else /* markers are always of size SIZE_SZ */
+    assert(sz == SIZE_SZ);
+}
+
+/*
+  Properties of inuse chunks
+*/
+
+#if __STD_C
+static void do_check_inuse_chunk(mstate av, mchunkptr p)
+#else
+static void do_check_inuse_chunk(av, p) mstate av; mchunkptr p;
+#endif
+{
+  mchunkptr next;
+
+  do_check_chunk(av, p);
+
+  assert(av == arena_for_chunk(p));
+  if (chunk_is_mmapped(p))
+    return; /* mmapped chunks have no next/prev */
+
+  /* Check whether it claims to be in use ... */
+  assert(inuse(p));
+
+  next = next_chunk(p);
+
+  /* ... and is surrounded by OK chunks.
+    Since more things can be checked with free chunks than inuse ones,
+    if an inuse chunk borders them and debug is on, it's worth doing them.
+  */
+  if (!prev_inuse(p))  {
+    /* Note that we cannot even look at prev unless it is not inuse */
+    mchunkptr prv = prev_chunk(p);
+    assert(next_chunk(prv) == p);
+    do_check_free_chunk(av, prv);
+  }
+
+  if (next == av->top) {
+    assert(prev_inuse(next));
+    assert(chunksize(next) >= MINSIZE);
+  }
+  else if (!inuse(next))
+    do_check_free_chunk(av, next);
+}
+
+/*
+  Properties of chunks recycled from fastbins
+*/
+
+#if __STD_C
+static void do_check_remalloced_chunk(mstate av, mchunkptr p, INTERNAL_SIZE_T s)
+#else
+static void do_check_remalloced_chunk(av, p, s)
+mstate av; mchunkptr p; INTERNAL_SIZE_T s;
+#endif
+{
+  INTERNAL_SIZE_T sz = p->size & ~(PREV_INUSE);
+
+  if (!chunk_is_mmapped(p)) {
+    assert(av == arena_for_chunk(p));
+  }
+
+  do_check_inuse_chunk(av, p);
+
+  /* Legal size ... */
+  assert((sz & MALLOC_ALIGN_MASK) == 0);
+  assert((unsigned long)(sz) >= MINSIZE);
+  /* ... and alignment */
+  assert(aligned_OK(chunk2mem(p)));
+  /* chunk is less than MINSIZE more than request */
+  assert((long)(sz) - (long)(s) >= 0);
+  assert((long)(sz) - (long)(s + MINSIZE) < 0);
+}
+
+/*
+  Properties of nonrecycled chunks at the point they are malloced
+*/
+
+#if __STD_C
+static void do_check_malloced_chunk(mstate av, mchunkptr p, INTERNAL_SIZE_T s)
+#else
+static void do_check_malloced_chunk(av, p, s)
+mstate av; mchunkptr p; INTERNAL_SIZE_T s;
+#endif
+{
+  /* same as recycled case ... */
+  do_check_remalloced_chunk(av, p, s);
+
+  /*
+    ... plus,  must obey implementation invariant that prev_inuse is
+    always true of any allocated chunk; i.e., that each allocated
+    chunk borders either a previously allocated and still in-use
+    chunk, or the base of its memory arena. This is ensured
+    by making all allocations from the the `lowest' part of any found
+    chunk.  This does not necessarily hold however for chunks
+    recycled via fastbins.
+  */
+
+  assert(prev_inuse(p));
+}
+
+
+/*
+  Properties of malloc_state.
+
+  This may be useful for debugging malloc, as well as detecting user
+  programmer errors that somehow write into malloc_state.
+
+  If you are extending or experimenting with this malloc, you can
+  probably figure out how to hack this routine to print out or
+  display chunk addresses, sizes, bins, and other instrumentation.
+*/
+
+static void do_check_malloc_state(mstate av)
+{
+  int i;
+  mchunkptr p;
+  mchunkptr q;
+  mbinptr b;
+  unsigned int binbit;
+  int empty;
+  unsigned int idx;
+  INTERNAL_SIZE_T size;
+  unsigned long total = 0;
+  int max_fast_bin;
+
+  /* internal size_t must be no wider than pointer type */
+  assert(sizeof(INTERNAL_SIZE_T) <= sizeof(char*));
+
+  /* alignment is a power of 2 */
+  assert((MALLOC_ALIGNMENT & (MALLOC_ALIGNMENT-1)) == 0);
+
+  /* cannot run remaining checks until fully initialized */
+  if (av->top == 0 || av->top == initial_top(av))
+    return;
+
+
+  /* properties of fastbins */
+
+  /* max_fast is in allowed range */
+  assert((av->max_fast & ~1) <= request2size(MAX_FAST_SIZE));
+
+  max_fast_bin = fastbin_index(av->max_fast);
+
+  for (i = 0; i < NFASTBINS; ++i) {
+    p = av->fastbins[i];
+
+    /* all bins past max_fast are empty */
+    if (i > max_fast_bin)
+      assert(p == 0);
+
+    while (p != 0) {
+      /* each chunk claims to be inuse */
+      do_check_inuse_chunk(av, p);
+      total += chunksize(p);
+      /* chunk belongs in this bin */
+      assert(fastbin_index(chunksize(p)) == i);
+      p = p->fd;
+    }
+  }
+
+  if (total != 0)
+    assert(have_fastchunks(av));
+  else if (!have_fastchunks(av))
+    assert(total == 0);
+
+  /* check normal bins */
+  for (i = 1; i < NBINS; ++i) {
+    b = bin_at(av,i);
+
+    /* binmap is accurate (except for bin 1 == unsorted_chunks) */
+    if (i >= 2) {
+      binbit = get_binmap(av,i);
+      empty = last(b) == b;
+      if (!binbit)
+        assert(empty);
+      else if (!empty)
+        assert(binbit);
+    }
+
+    for (p = last(b); p != b; p = p->bk) {
+      /* each chunk claims to be free */
+      do_check_free_chunk(av, p);
+      size = chunksize(p);
+      total += size;
+      if (i >= 2) {
+        /* chunk belongs in bin */
+        idx = bin_index(size);
+        assert(idx == (unsigned int)i);
+        /* lists are sorted */
+        if ((unsigned long) size >= (unsigned long)(FIRST_SORTED_BIN_SIZE)) {
+	  assert(p->bk == b ||
+		 (unsigned long)chunksize(p->bk) >=
+		 (unsigned long)chunksize(p));
+	}
+      }
+      /* chunk is followed by a legal chain of inuse chunks */
+      for (q = next_chunk(p);
+           (q != av->top && inuse(q) &&
+             (unsigned long)(chunksize(q)) >= MINSIZE);
+           q = next_chunk(q))
+        do_check_inuse_chunk(av, q);
+    }
+  }
+
+  /* top chunk is OK */
+  check_chunk(av, av->top);
+
+  /* sanity checks for statistics */
+
+
+  assert((unsigned long)(av->system_mem) <=
+         (unsigned long)(av->max_system_mem));
+
+
+}
+#endif
+
+
+
+/* ----------- Routines dealing with system allocation -------------- */
+
+/* No system allocation routines supported */
+
+
+/*------------------------ Public wrappers. --------------------------------*/
+
+
+
+#undef DEBUG_MALLOC
+Void_t*
+public_mALLOc(cvmx_arena_list_t arena_list, size_t bytes)
+{
+  mstate ar_ptr, orig_ar_ptr;
+  Void_t *victim = NULL;
+  static mstate debug_prev_ar;  // debug only!
+#ifdef DEBUG_MALLOC
+  int arena_cnt=0;
+#endif
+  
+  ar_ptr = arena_list;
+
+  if (!ar_ptr)
+  {
+     return(NULL);
+  }
+
+  if (debug_prev_ar != ar_ptr)
+  {
+      debug_printf("New arena: %p\n", ar_ptr);
+#ifdef CVMX_SPINLOCK_DEBUG
+      cvmx_dprintf("lock wait count for arena: %p is %ld\n", ar_ptr, ar_ptr->mutex.wait_cnt);
+#endif
+      debug_prev_ar = ar_ptr;
+  }
+  orig_ar_ptr = ar_ptr;
+
+  // try to get an arena without contention
+  do
+  {
+#ifdef DEBUG_MALLOC
+  arena_cnt++;
+#endif
+      if (!mutex_trylock(&ar_ptr->mutex))
+      {
+          // we locked it
+          victim = _int_malloc(ar_ptr, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(victim)
+          {
+              break;
+          }
+      }
+      ar_ptr = ar_ptr->next;
+  } while (ar_ptr != orig_ar_ptr);
+
+  // we couldn't get the memory without contention, so try all
+  // arenas.  SLOW!
+  if (!victim)
+  {
+      ar_ptr = orig_ar_ptr;
+      do
+      {
+#ifdef DEBUG_MALLOC
+  arena_cnt++;
+#endif
+          mutex_lock(&ar_ptr->mutex);
+          victim = _int_malloc(ar_ptr, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(victim)
+          {
+              break;
+          }
+          ar_ptr = ar_ptr->next;
+      } while (ar_ptr != orig_ar_ptr);
+  }
+
+
+  assert(!victim || chunk_is_mmapped(mem2chunk(victim)) ||
+	 ar_ptr == arena_for_chunk(mem2chunk(victim)));
+
+#ifdef DEBUG_MALLOC
+  if (!victim)
+  {
+     cvmx_dprintf("Malloc failed: size: %ld, arena_cnt: %d\n", bytes, arena_cnt);
+  }
+#endif
+
+  debug_printf("cvmx_malloc(%ld) = %p\n", bytes, victim);
+
+  // remember which arena we last used.....
+  tsd_setspecific(arena_key, (Void_t *)ar_ptr);
+  return victim;
+}
+
+
+
+void
+public_fREe(Void_t* mem)
+{
+  mstate ar_ptr;
+  mchunkptr p;                          /* chunk corresponding to mem */
+
+  debug_printf("cvmx_free(%p)\n", mem);
+
+
+  if (mem == 0)                              /* free(0) has no effect */
+    return;
+
+  p = mem2chunk(mem);
+
+
+  ar_ptr = arena_for_chunk(p);
+  assert(ar_ptr);
+#if THREAD_STATS
+  if(!mutex_trylock(&ar_ptr->mutex))
+    ++(ar_ptr->stat_lock_direct);
+  else {
+    (void)mutex_lock(&ar_ptr->mutex);
+    ++(ar_ptr->stat_lock_wait);
+  }
+#else
+  (void)mutex_lock(&ar_ptr->mutex);
+#endif
+  _int_free(ar_ptr, mem);
+  (void)mutex_unlock(&ar_ptr->mutex);
+}
+
+Void_t*
+public_rEALLOc(cvmx_arena_list_t arena_list, Void_t* oldmem, size_t bytes)
+{
+  mstate ar_ptr;
+  INTERNAL_SIZE_T    nb;      /* padded request size */
+
+  mchunkptr oldp;             /* chunk corresponding to oldmem */
+  INTERNAL_SIZE_T    oldsize; /* its size */
+
+  Void_t* newp;             /* chunk to return */
+
+
+#if REALLOC_ZERO_BYTES_FREES
+  if (bytes == 0 && oldmem != NULL) { public_fREe(oldmem); return 0; }
+#endif
+
+  /* realloc of null is supposed to be same as malloc */
+  if (oldmem == 0) return public_mALLOc(arena_list, bytes);
+
+  oldp    = mem2chunk(oldmem);
+  oldsize = chunksize(oldp);
+
+  checked_request2size(bytes, nb);
+
+
+  ar_ptr = arena_for_chunk(oldp);
+  (void)mutex_lock(&ar_ptr->mutex);
+
+
+  newp = _int_realloc(ar_ptr, oldmem, bytes);
+
+  (void)mutex_unlock(&ar_ptr->mutex);
+  assert(!newp || chunk_is_mmapped(mem2chunk(newp)) ||
+	 ar_ptr == arena_for_chunk(mem2chunk(newp)));
+  return newp;
+}
+
+#undef DEBUG_MEMALIGN
+Void_t*
+public_mEMALIGn(cvmx_arena_list_t arena_list, size_t alignment, size_t bytes)
+{
+  mstate ar_ptr, orig_ar_ptr;
+  Void_t *p = NULL;
+#ifdef DEBUG_MEMALIGN
+  int arena_cnt=0;
+#endif
+
+
+  /* If need less alignment than we give anyway, just relay to malloc */
+  if (alignment <= MALLOC_ALIGNMENT) return public_mALLOc(arena_list, bytes);
+
+  /* Otherwise, ensure that it is at least a minimum chunk size */
+  if (alignment <  MINSIZE) alignment = MINSIZE;
+
+
+  ar_ptr = arena_list;
+
+  if (!ar_ptr)
+  {
+     return(NULL);
+  }
+
+  orig_ar_ptr = ar_ptr;
+
+
+  // try to get an arena without contention
+  do
+  {
+
+#ifdef DEBUG_MEMALIGN
+   arena_cnt++;
+#endif
+      if (!mutex_trylock(&ar_ptr->mutex))
+      {
+          // we locked it
+          p = _int_memalign(ar_ptr, alignment, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(p)
+          {
+              break;
+          }
+      }
+      ar_ptr = ar_ptr->next;
+  } while (ar_ptr != orig_ar_ptr);
+
+
+  // we couldn't get the memory without contention, so try all
+  // arenas.  SLOW!
+  if (!p)
+  {
+#ifdef DEBUG_MEMALIGN
+   arena_cnt++;
+#endif
+      ar_ptr = orig_ar_ptr;
+      do
+      {
+          mutex_lock(&ar_ptr->mutex);
+          p = _int_memalign(ar_ptr, alignment, bytes);
+          (void)mutex_unlock(&ar_ptr->mutex);
+          if(p)
+          {
+              break;
+          }
+          ar_ptr = ar_ptr->next;
+      } while (ar_ptr != orig_ar_ptr);
+  }
+
+
+  if (p)
+  {
+     assert(ar_ptr == arena_for_chunk(mem2chunk(p)));
+  }
+  else
+  {
+#ifdef DEBUG_MEMALIGN
+     cvmx_dprintf("Memalign failed: align: 0x%x, size: %ld, arena_cnt: %ld\n", alignment, bytes, arena_cnt);
+#endif
+  }
+
+  assert(!p || ar_ptr == arena_for_chunk(mem2chunk(p)));
+  return p;
+}
+
+
+
+Void_t*
+public_cALLOc(cvmx_arena_list_t arena_list, size_t n, size_t elem_size)
+{
+  mstate av;
+  mchunkptr oldtop, p;
+  INTERNAL_SIZE_T sz, csz, oldtopsize;
+  Void_t* mem;
+  unsigned long clearsize;
+  unsigned long nclears;
+  INTERNAL_SIZE_T* d;
+
+
+  /* FIXME: check for overflow on multiplication.  */
+  sz = n * elem_size;
+
+  mem = public_mALLOc(arena_list, sz);
+  if (mem)
+  {
+     memset(mem, 0, sz);
+  }
+
+  return mem;
+}
+
+
+#ifndef _LIBC
+
+void
+public_cFREe(Void_t* m)
+{
+  public_fREe(m);
+}
+
+#endif /* _LIBC */
+
+/*
+  ------------------------------ malloc ------------------------------
+*/
+
+static Void_t*
+_int_malloc(mstate av, size_t bytes)
+{
+  INTERNAL_SIZE_T nb;               /* normalized request size */
+  unsigned int    idx;              /* associated bin index */
+  mbinptr         bin;              /* associated bin */
+  mfastbinptr*    fb;               /* associated fastbin */
+
+  mchunkptr       victim;           /* inspected/selected chunk */
+  INTERNAL_SIZE_T size;             /* its size */
+  int             victim_index;     /* its bin index */
+
+  mchunkptr       remainder;        /* remainder from a split */
+  unsigned long   remainder_size;   /* its size */
+
+  unsigned int    block;            /* bit map traverser */
+  unsigned int    bit;              /* bit map traverser */
+  unsigned int    map;              /* current word of binmap */
+
+  mchunkptr       fwd;              /* misc temp for linking */
+  mchunkptr       bck;              /* misc temp for linking */
+
+  /*
+    Convert request size to internal form by adding SIZE_SZ bytes
+    overhead plus possibly more to obtain necessary alignment and/or
+    to obtain a size of at least MINSIZE, the smallest allocatable
+    size. Also, checked_request2size traps (returning 0) request sizes
+    that are so large that they wrap around zero when padded and
+    aligned.
+  */
+
+
+  checked_request2size(bytes, nb);
+
+  /*
+    If the size qualifies as a fastbin, first check corresponding bin.
+    This code is safe to execute even if av is not yet initialized, so we
+    can try it without checking, which saves some time on this fast path.
+  */
+
+  if ((unsigned long)(nb) <= (unsigned long)(av->max_fast)) {
+    fb = &(av->fastbins[(fastbin_index(nb))]);
+    if ( (victim = *fb) != 0) {
+      *fb = victim->fd;
+      check_remalloced_chunk(av, victim, nb);
+      set_arena_for_chunk(victim, av);
+      return chunk2mem(victim);
+    }
+  }
+
+  /*
+    If a small request, check regular bin.  Since these "smallbins"
+    hold one size each, no searching within bins is necessary.
+    (For a large request, we need to wait until unsorted chunks are
+    processed to find best fit. But for small ones, fits are exact
+    anyway, so we can check now, which is faster.)
+  */
+
+  if (in_smallbin_range(nb)) {
+    idx = smallbin_index(nb);
+    bin = bin_at(av,idx);
+
+    if ( (victim = last(bin)) != bin) {
+      if (victim == 0) /* initialization check */
+        malloc_consolidate(av);
+      else {
+        bck = victim->bk;
+        set_inuse_bit_at_offset(victim, nb);
+        bin->bk = bck;
+        bck->fd = bin;
+
+        set_arena_for_chunk(victim, av);
+        check_malloced_chunk(av, victim, nb);
+        return chunk2mem(victim);
+      }
+    }
+  }
+
+  /*
+     If this is a large request, consolidate fastbins before continuing.
+     While it might look excessive to kill all fastbins before
+     even seeing if there is space available, this avoids
+     fragmentation problems normally associated with fastbins.
+     Also, in practice, programs tend to have runs of either small or
+     large requests, but less often mixtures, so consolidation is not
+     invoked all that often in most programs. And the programs that
+     it is called frequently in otherwise tend to fragment.
+  */
+
+  else {
+    idx = largebin_index(nb);
+    if (have_fastchunks(av))
+      malloc_consolidate(av);
+  }
+
+  /*
+    Process recently freed or remaindered chunks, taking one only if
+    it is exact fit, or, if this a small request, the chunk is remainder from
+    the most recent non-exact fit.  Place other traversed chunks in
+    bins.  Note that this step is the only place in any routine where
+    chunks are placed in bins.
+
+    The outer loop here is needed because we might not realize until
+    near the end of malloc that we should have consolidated, so must
+    do so and retry. This happens at most once, and only when we would
+    otherwise need to expand memory to service a "small" request.
+  */
+
+  for(;;) {
+
+    while ( (victim = unsorted_chunks(av)->bk) != unsorted_chunks(av)) {
+      bck = victim->bk;
+      size = chunksize(victim);
+
+      /*
+         If a small request, try to use last remainder if it is the
+         only chunk in unsorted bin.  This helps promote locality for
+         runs of consecutive small requests. This is the only
+         exception to best-fit, and applies only when there is
+         no exact fit for a small chunk.
+      */
+
+      if (in_smallbin_range(nb) &&
+          bck == unsorted_chunks(av) &&
+          victim == av->last_remainder &&
+          (unsigned long)(size) > (unsigned long)(nb + MINSIZE)) {
+
+        /* split and reattach remainder */
+        remainder_size = size - nb;
+        remainder = chunk_at_offset(victim, nb);
+        unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
+        av->last_remainder = remainder;
+        remainder->bk = remainder->fd = unsorted_chunks(av);
+
+        set_head(victim, nb | PREV_INUSE);
+        set_head(remainder, remainder_size | PREV_INUSE);
+        set_foot(remainder, remainder_size);
+
+        set_arena_for_chunk(victim, av);
+        check_malloced_chunk(av, victim, nb);
+        return chunk2mem(victim);
+      }
+
+      /* remove from unsorted list */
+      unsorted_chunks(av)->bk = bck;
+      bck->fd = unsorted_chunks(av);
+
+      /* Take now instead of binning if exact fit */
+
+      if (size == nb) {
+        set_inuse_bit_at_offset(victim, size);
+        set_arena_for_chunk(victim, av);
+        check_malloced_chunk(av, victim, nb);
+        return chunk2mem(victim);
+      }
+
+      /* place chunk in bin */
+
+      if (in_smallbin_range(size)) {
+        victim_index = smallbin_index(size);
+        bck = bin_at(av, victim_index);
+        fwd = bck->fd;
+      }
+      else {
+        victim_index = largebin_index(size);
+        bck = bin_at(av, victim_index);
+        fwd = bck->fd;
+
+        if (fwd != bck) {
+          /* if smaller than smallest, place first */
+          if ((unsigned long)(size) < (unsigned long)(bck->bk->size)) {
+            fwd = bck;
+            bck = bck->bk;
+          }
+          else if ((unsigned long)(size) >= 
+                   (unsigned long)(FIRST_SORTED_BIN_SIZE)) {
+
+            /* maintain large bins in sorted order */
+            size |= PREV_INUSE; /* Or with inuse bit to speed comparisons */
+            while ((unsigned long)(size) < (unsigned long)(fwd->size)) {
+              fwd = fwd->fd;
+	    }
+            bck = fwd->bk;
+          }
+        }
+      }
+
+      mark_bin(av, victim_index);
+      victim->bk = bck;
+      victim->fd = fwd;
+      fwd->bk = victim;
+      bck->fd = victim;
+    }
+
+    /*
+      If a large request, scan through the chunks of current bin in
+      sorted order to find smallest that fits.  This is the only step
+      where an unbounded number of chunks might be scanned without doing
+      anything useful with them. However the lists tend to be short.
+    */
+
+    if (!in_smallbin_range(nb)) {
+      bin = bin_at(av, idx);
+
+      for (victim = last(bin); victim != bin; victim = victim->bk) {
+	size = chunksize(victim);
+
+	if ((unsigned long)(size) >= (unsigned long)(nb)) {
+	  remainder_size = size - nb;
+	  unlink(victim, bck, fwd);
+
+	  /* Exhaust */
+	  if (remainder_size < MINSIZE)  {
+	    set_inuse_bit_at_offset(victim, size);
+        set_arena_for_chunk(victim, av);
+	    check_malloced_chunk(av, victim, nb);
+	    return chunk2mem(victim);
+	  }
+	  /* Split */
+	  else {
+	    remainder = chunk_at_offset(victim, nb);
+	    unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
+	    remainder->bk = remainder->fd = unsorted_chunks(av);
+	    set_head(victim, nb | PREV_INUSE);
+	    set_head(remainder, remainder_size | PREV_INUSE);
+	    set_foot(remainder, remainder_size);
+        set_arena_for_chunk(victim, av);
+	    check_malloced_chunk(av, victim, nb);
+	    return chunk2mem(victim);
+	  }
+	}
+      }
+    }
+
+    /*
+      Search for a chunk by scanning bins, starting with next largest
+      bin. This search is strictly by best-fit; i.e., the smallest
+      (with ties going to approximately the least recently used) chunk
+      that fits is selected.
+
+      The bitmap avoids needing to check that most blocks are nonempty.
+      The particular case of skipping all bins during warm-up phases
+      when no chunks have been returned yet is faster than it might look.
+    */
+
+    ++idx;
+    bin = bin_at(av,idx);
+    block = idx2block(idx);
+    map = av->binmap[block];
+    bit = idx2bit(idx);
+
+    for (;;) {
+
+      /* Skip rest of block if there are no more set bits in this block.  */
+      if (bit > map || bit == 0) {
+        do {
+          if (++block >= BINMAPSIZE)  /* out of bins */
+            goto use_top;
+        } while ( (map = av->binmap[block]) == 0);
+
+        bin = bin_at(av, (block << BINMAPSHIFT));
+        bit = 1;
+      }
+
+      /* Advance to bin with set bit. There must be one. */
+      while ((bit & map) == 0) {
+        bin = next_bin(bin);
+        bit <<= 1;
+        assert(bit != 0);
+      }
+
+      /* Inspect the bin. It is likely to be non-empty */
+      victim = last(bin);
+
+      /*  If a false alarm (empty bin), clear the bit. */
+      if (victim == bin) {
+        av->binmap[block] = map &= ~bit; /* Write through */
+        bin = next_bin(bin);
+        bit <<= 1;
+      }
+
+      else {
+        size = chunksize(victim);
+
+        /*  We know the first chunk in this bin is big enough to use. */
+        assert((unsigned long)(size) >= (unsigned long)(nb));
+
+        remainder_size = size - nb;
+
+        /* unlink */
+        bck = victim->bk;
+        bin->bk = bck;
+        bck->fd = bin;
+
+        /* Exhaust */
+        if (remainder_size < MINSIZE) {
+          set_inuse_bit_at_offset(victim, size);
+          set_arena_for_chunk(victim, av);
+          check_malloced_chunk(av, victim, nb);
+          return chunk2mem(victim);
+        }
+
+        /* Split */
+        else {
+          remainder = chunk_at_offset(victim, nb);
+
+          unsorted_chunks(av)->bk = unsorted_chunks(av)->fd = remainder;
+          remainder->bk = remainder->fd = unsorted_chunks(av);
+          /* advertise as last remainder */
+          if (in_smallbin_range(nb))
+            av->last_remainder = remainder;
+
+          set_head(victim, nb | PREV_INUSE);
+          set_head(remainder, remainder_size | PREV_INUSE);
+          set_foot(remainder, remainder_size);
+          set_arena_for_chunk(victim, av);
+          check_malloced_chunk(av, victim, nb);
+          return chunk2mem(victim);
+        }
+      }
+    }
+
+  use_top:
+    /*
+      If large enough, split off the chunk bordering the end of memory
+      (held in av->top). Note that this is in accord with the best-fit
+      search rule.  In effect, av->top is treated as larger (and thus
+      less well fitting) than any other available chunk since it can
+      be extended to be as large as necessary (up to system
+      limitations).
+
+      We require that av->top always exists (i.e., has size >=
+      MINSIZE) after initialization, so if it would otherwise be
+      exhuasted by current request, it is replenished. (The main
+      reason for ensuring it exists is that we may need MINSIZE space
+      to put in fenceposts in sysmalloc.)
+    */
+
+    victim = av->top;
+    size = chunksize(victim);
+
+    if ((unsigned long)(size) >= (unsigned long)(nb + MINSIZE)) {
+      remainder_size = size - nb;
+      remainder = chunk_at_offset(victim, nb);
+      av->top = remainder;
+      set_head(victim, nb | PREV_INUSE);
+      set_head(remainder, remainder_size | PREV_INUSE);
+
+      set_arena_for_chunk(victim, av);
+      check_malloced_chunk(av, victim, nb);
+      return chunk2mem(victim);
+    }
+
+    /*
+      If there is space available in fastbins, consolidate and retry,
+      to possibly avoid expanding memory. This can occur only if nb is
+      in smallbin range so we didn't consolidate upon entry.
+    */
+
+    else if (have_fastchunks(av)) {
+      assert(in_smallbin_range(nb));
+      malloc_consolidate(av);
+      idx = smallbin_index(nb); /* restore original bin index */
+    }
+
+    /*
+       Otherwise, relay to handle system-dependent cases
+    */
+    else
+      return(NULL); // sysmalloc not supported
+  }
+}
+
+/*
+  ------------------------------ free ------------------------------
+*/
+
+static void
+_int_free(mstate av, Void_t* mem)
+{
+  mchunkptr       p;           /* chunk corresponding to mem */
+  INTERNAL_SIZE_T size;        /* its size */
+  mfastbinptr*    fb;          /* associated fastbin */
+  mchunkptr       nextchunk;   /* next contiguous chunk */
+  INTERNAL_SIZE_T nextsize;    /* its size */
+  int             nextinuse;   /* true if nextchunk is used */
+  INTERNAL_SIZE_T prevsize;    /* size of previous contiguous chunk */
+  mchunkptr       bck;         /* misc temp for linking */
+  mchunkptr       fwd;         /* misc temp for linking */
+
+
+  /* free(0) has no effect */
+  if (mem != 0) {
+    p = mem2chunk(mem);
+    size = chunksize(p);
+
+    check_inuse_chunk(av, p);
+
+    /*
+      If eligible, place chunk on a fastbin so it can be found
+      and used quickly in malloc.
+    */
+
+    if ((unsigned long)(size) <= (unsigned long)(av->max_fast)
+
+#if TRIM_FASTBINS
+        /*
+           If TRIM_FASTBINS set, don't place chunks
+           bordering top into fastbins
+        */
+        && (chunk_at_offset(p, size) != av->top)
+#endif
+        ) {
+
+      set_fastchunks(av);
+      fb = &(av->fastbins[fastbin_index(size)]);
+      p->fd = *fb;
+      *fb = p;
+    }
+
+    /*
+       Consolidate other non-mmapped chunks as they arrive.
+    */
+
+    else if (!chunk_is_mmapped(p)) {
+      nextchunk = chunk_at_offset(p, size);
+      nextsize = chunksize(nextchunk);
+      assert(nextsize > 0);
+
+      /* consolidate backward */
+      if (!prev_inuse(p)) {
+        prevsize = p->prev_size;
+        size += prevsize;
+        p = chunk_at_offset(p, -((long) prevsize));
+        unlink(p, bck, fwd);
+      }
+
+      if (nextchunk != av->top) {
+        /* get and clear inuse bit */
+        nextinuse = inuse_bit_at_offset(nextchunk, nextsize);
+
+        /* consolidate forward */
+        if (!nextinuse) {
+          unlink(nextchunk, bck, fwd);
+          size += nextsize;
+        } else
+	  clear_inuse_bit_at_offset(nextchunk, 0);
+
+        /*
+          Place the chunk in unsorted chunk list. Chunks are
+          not placed into regular bins until after they have
+          been given one chance to be used in malloc.
+        */
+
+        bck = unsorted_chunks(av);
+        fwd = bck->fd;
+        p->bk = bck;
+        p->fd = fwd;
+        bck->fd = p;
+        fwd->bk = p;
+
+        set_head(p, size | PREV_INUSE);
+        set_foot(p, size);
+
+        check_free_chunk(av, p);
+      }
+
+      /*
+         If the chunk borders the current high end of memory,
+         consolidate into top
+      */
+
+      else {
+        size += nextsize;
+        set_head(p, size | PREV_INUSE);
+        av->top = p;
+        check_chunk(av, p);
+      }
+
+      /*
+        If freeing a large space, consolidate possibly-surrounding
+        chunks. Then, if the total unused topmost memory exceeds trim
+        threshold, ask malloc_trim to reduce top.
+
+        Unless max_fast is 0, we don't know if there are fastbins
+        bordering top, so we cannot tell for sure whether threshold
+        has been reached unless fastbins are consolidated.  But we
+        don't want to consolidate on each free.  As a compromise,
+        consolidation is performed if FASTBIN_CONSOLIDATION_THRESHOLD
+        is reached.
+      */
+
+      if ((unsigned long)(size) >= FASTBIN_CONSOLIDATION_THRESHOLD) {
+        if (have_fastchunks(av))
+          malloc_consolidate(av);
+      }
+    }
+  }
+}
+
+/*
+  ------------------------- malloc_consolidate -------------------------
+
+  malloc_consolidate is a specialized version of free() that tears
+  down chunks held in fastbins.  Free itself cannot be used for this
+  purpose since, among other things, it might place chunks back onto
+  fastbins.  So, instead, we need to use a minor variant of the same
+  code.
+
+  Also, because this routine needs to be called the first time through
+  malloc anyway, it turns out to be the perfect place to trigger
+  initialization code.
+*/
+
+#if __STD_C
+static void malloc_consolidate(mstate av)
+#else
+static void malloc_consolidate(av) mstate av;
+#endif
+{
+  mfastbinptr*    fb;                 /* current fastbin being consolidated */
+  mfastbinptr*    maxfb;              /* last fastbin (for loop control) */
+  mchunkptr       p;                  /* current chunk being consolidated */
+  mchunkptr       nextp;              /* next chunk to consolidate */
+  mchunkptr       unsorted_bin;       /* bin header */
+  mchunkptr       first_unsorted;     /* chunk to link to */
+
+  /* These have same use as in free() */
+  mchunkptr       nextchunk;
+  INTERNAL_SIZE_T size;
+  INTERNAL_SIZE_T nextsize;
+  INTERNAL_SIZE_T prevsize;
+  int             nextinuse;
+  mchunkptr       bck;
+  mchunkptr       fwd;
+
+  /*
+    If max_fast is 0, we know that av hasn't
+    yet been initialized, in which case do so below
+  */
+
+  if (av->max_fast != 0) {
+    clear_fastchunks(av);
+
+    unsorted_bin = unsorted_chunks(av);
+
+    /*
+      Remove each chunk from fast bin and consolidate it, placing it
+      then in unsorted bin. Among other reasons for doing this,
+      placing in unsorted bin avoids needing to calculate actual bins
+      until malloc is sure that chunks aren't immediately going to be
+      reused anyway.
+    */
+
+    maxfb = &(av->fastbins[fastbin_index(av->max_fast)]);
+    fb = &(av->fastbins[0]);
+    do {
+      if ( (p = *fb) != 0) {
+        *fb = 0;
+
+        do {
+          check_inuse_chunk(av, p);
+          nextp = p->fd;
+
+          /* Slightly streamlined version of consolidation code in free() */
+          size = p->size & ~(PREV_INUSE);
+          nextchunk = chunk_at_offset(p, size);
+          nextsize = chunksize(nextchunk);
+
+          if (!prev_inuse(p)) {
+            prevsize = p->prev_size;
+            size += prevsize;
+            p = chunk_at_offset(p, -((long) prevsize));
+            unlink(p, bck, fwd);
+          }
+
+          if (nextchunk != av->top) {
+            nextinuse = inuse_bit_at_offset(nextchunk, nextsize);
+
+            if (!nextinuse) {
+              size += nextsize;
+              unlink(nextchunk, bck, fwd);
+            } else
+	      clear_inuse_bit_at_offset(nextchunk, 0);
+
+            first_unsorted = unsorted_bin->fd;
+            unsorted_bin->fd = p;
+            first_unsorted->bk = p;
+
+            set_head(p, size | PREV_INUSE);
+            p->bk = unsorted_bin;
+            p->fd = first_unsorted;
+            set_foot(p, size);
+          }
+
+          else {
+            size += nextsize;
+            set_head(p, size | PREV_INUSE);
+            av->top = p;
+          }
+
+        } while ( (p = nextp) != 0);
+
+      }
+    } while (fb++ != maxfb);
+  }
+  else {
+    malloc_init_state(av);
+    check_malloc_state(av);
+  }
+}
+
+/*
+  ------------------------------ realloc ------------------------------
+*/
+
+static Void_t*
+_int_realloc(mstate av, Void_t* oldmem, size_t bytes)
+{
+  INTERNAL_SIZE_T  nb;              /* padded request size */
+
+  mchunkptr        oldp;            /* chunk corresponding to oldmem */
+  INTERNAL_SIZE_T  oldsize;         /* its size */
+
+  mchunkptr        newp;            /* chunk to return */
+  INTERNAL_SIZE_T  newsize;         /* its size */
+  Void_t*          newmem;          /* corresponding user mem */
+
+  mchunkptr        next;            /* next contiguous chunk after oldp */
+
+  mchunkptr        remainder;       /* extra space at end of newp */
+  unsigned long    remainder_size;  /* its size */
+
+  mchunkptr        bck;             /* misc temp for linking */
+  mchunkptr        fwd;             /* misc temp for linking */
+
+  unsigned long    copysize;        /* bytes to copy */
+  unsigned int     ncopies;         /* INTERNAL_SIZE_T words to copy */
+  INTERNAL_SIZE_T* s;               /* copy source */
+  INTERNAL_SIZE_T* d;               /* copy destination */
+
+
+#if REALLOC_ZERO_BYTES_FREES
+  if (bytes == 0) {
+    _int_free(av, oldmem);
+    return 0;
+  }
+#endif
+
+  /* realloc of null is supposed to be same as malloc */
+  if (oldmem == 0) return _int_malloc(av, bytes);
+
+  checked_request2size(bytes, nb);
+
+  oldp    = mem2chunk(oldmem);
+  oldsize = chunksize(oldp);
+
+  check_inuse_chunk(av, oldp);
+
+  // force to act like not mmapped
+  if (1) {
+
+    if ((unsigned long)(oldsize) >= (unsigned long)(nb)) {
+      /* already big enough; split below */
+      newp = oldp;
+      newsize = oldsize;
+    }
+
+    else {
+      next = chunk_at_offset(oldp, oldsize);
+
+      /* Try to expand forward into top */
+      if (next == av->top &&
+          (unsigned long)(newsize = oldsize + chunksize(next)) >=
+          (unsigned long)(nb + MINSIZE)) {
+        set_head_size(oldp, nb );
+        av->top = chunk_at_offset(oldp, nb);
+        set_head(av->top, (newsize - nb) | PREV_INUSE);
+    	check_inuse_chunk(av, oldp);
+        set_arena_for_chunk(oldp, av);
+        return chunk2mem(oldp);
+      }
+
+      /* Try to expand forward into next chunk;  split off remainder below */
+      else if (next != av->top &&
+               !inuse(next) &&
+               (unsigned long)(newsize = oldsize + chunksize(next)) >=
+               (unsigned long)(nb)) {
+        newp = oldp;
+        unlink(next, bck, fwd);
+      }
+
+      /* allocate, copy, free */
+      else {
+        newmem = _int_malloc(av, nb - MALLOC_ALIGN_MASK);
+        if (newmem == 0)
+          return 0; /* propagate failure */
+
+        newp = mem2chunk(newmem);
+        newsize = chunksize(newp);
+
+        /*
+          Avoid copy if newp is next chunk after oldp.
+        */
+        if (newp == next) {
+          newsize += oldsize;
+          newp = oldp;
+        }
+        else {
+          /*
+            Unroll copy of <= 36 bytes (72 if 8byte sizes)
+            We know that contents have an odd number of
+            INTERNAL_SIZE_T-sized words; minimally 3.
+          */
+
+          copysize = oldsize - SIZE_SZ;
+          s = (INTERNAL_SIZE_T*)(oldmem);
+          d = (INTERNAL_SIZE_T*)(newmem);
+          ncopies = copysize / sizeof(INTERNAL_SIZE_T);
+          assert(ncopies >= 3);
+
+          if (ncopies > 9)
+            MALLOC_COPY(d, s, copysize);
+
+          else {
+            *(d+0) = *(s+0);
+            *(d+1) = *(s+1);
+            *(d+2) = *(s+2);
+            if (ncopies > 4) {
+              *(d+3) = *(s+3);
+              *(d+4) = *(s+4);
+              if (ncopies > 6) {
+                *(d+5) = *(s+5);
+                *(d+6) = *(s+6);
+                if (ncopies > 8) {
+                  *(d+7) = *(s+7);
+                  *(d+8) = *(s+8);
+                }
+              }
+            }
+          }
+
+          _int_free(av, oldmem);
+          set_arena_for_chunk(newp, av);
+          check_inuse_chunk(av, newp);
+          return chunk2mem(newp);
+        }
+      }
+    }
+
+    /* If possible, free extra space in old or extended chunk */
+
+    assert((unsigned long)(newsize) >= (unsigned long)(nb));
+
+    remainder_size = newsize - nb;
+
+    if (remainder_size < MINSIZE) { /* not enough extra to split off */
+      set_head_size(newp, newsize);
+      set_inuse_bit_at_offset(newp, newsize);
+    }
+    else { /* split remainder */
+      remainder = chunk_at_offset(newp, nb);
+      set_head_size(newp, nb );
+      set_head(remainder, remainder_size | PREV_INUSE );
+      /* Mark remainder as inuse so free() won't complain */
+      set_inuse_bit_at_offset(remainder, remainder_size);
+      set_arena_for_chunk(remainder, av);
+      _int_free(av, chunk2mem(remainder));
+    }
+
+    set_arena_for_chunk(newp, av);
+    check_inuse_chunk(av, newp);
+    return chunk2mem(newp);
+  }
+
+  /*
+    Handle mmap cases
+  */
+
+  else {
+    /* If !HAVE_MMAP, but chunk_is_mmapped, user must have overwritten mem */
+    check_malloc_state(av);
+    MALLOC_FAILURE_ACTION;
+    return 0;
+  }
+}
+
+/*
+  ------------------------------ memalign ------------------------------
+*/
+
+static Void_t*
+_int_memalign(mstate av, size_t alignment, size_t bytes)
+{
+  INTERNAL_SIZE_T nb;             /* padded  request size */
+  char*           m;              /* memory returned by malloc call */
+  mchunkptr       p;              /* corresponding chunk */
+  char*           brk;            /* alignment point within p */
+  mchunkptr       newp;           /* chunk to return */
+  INTERNAL_SIZE_T newsize;        /* its size */
+  INTERNAL_SIZE_T leadsize;       /* leading space before alignment point */
+  mchunkptr       remainder;      /* spare room at end to split off */
+  unsigned long   remainder_size; /* its size */
+  INTERNAL_SIZE_T size;
+
+  /* If need less alignment than we give anyway, just relay to malloc */
+
+  if (alignment <= MALLOC_ALIGNMENT) return _int_malloc(av, bytes);
+
+  /* Otherwise, ensure that it is at least a minimum chunk size */
+
+  if (alignment <  MINSIZE) alignment = MINSIZE;
+
+  /* Make sure alignment is power of 2 (in case MINSIZE is not).  */
+  if ((alignment & (alignment - 1)) != 0) {
+    size_t a = MALLOC_ALIGNMENT * 2;
+    while ((unsigned long)a < (unsigned long)alignment) a <<= 1;
+    alignment = a;
+  }
+
+  checked_request2size(bytes, nb);
+
+  /*
+    Strategy: find a spot within that chunk that meets the alignment
+    request, and then possibly free the leading and trailing space.
+  */
+
+
+  /* Call malloc with worst case padding to hit alignment. */
+
+  m  = (char*)(_int_malloc(av, nb + alignment + MINSIZE));
+
+  if (m == 0) return 0; /* propagate failure */
+
+  p = mem2chunk(m);
+
+  if ((((unsigned long)(m)) % alignment) != 0) { /* misaligned */
+
+    /*
+      Find an aligned spot inside chunk.  Since we need to give back
+      leading space in a chunk of at least MINSIZE, if the first
+      calculation places us at a spot with less than MINSIZE leader,
+      we can move to the next aligned spot -- we've allocated enough
+      total room so that this is always possible.
+    */
+
+    brk = (char*)mem2chunk(((unsigned long)(m + alignment - 1)) &
+                           -((signed long) alignment));
+    if ((unsigned long)(brk - (char*)(p)) < MINSIZE)
+      brk += alignment;
+
+    newp = (mchunkptr)brk;
+    leadsize = brk - (char*)(p);
+    newsize = chunksize(p) - leadsize;
+
+    /* For mmapped chunks, just adjust offset */
+    if (chunk_is_mmapped(p)) {
+      newp->prev_size = p->prev_size + leadsize;
+      set_head(newp, newsize|IS_MMAPPED);
+      set_arena_for_chunk(newp, av);
+      return chunk2mem(newp);
+    }
+
+    /* Otherwise, give back leader, use the rest */
+    set_head(newp, newsize | PREV_INUSE );
+    set_inuse_bit_at_offset(newp, newsize);
+    set_head_size(p, leadsize);
+    set_arena_for_chunk(p, av);
+    _int_free(av, chunk2mem(p));
+    p = newp;
+
+    assert (newsize >= nb &&
+            (((unsigned long)(chunk2mem(p))) % alignment) == 0);
+  }
+
+  /* Also give back spare room at the end */
+  if (!chunk_is_mmapped(p)) {
+    size = chunksize(p);
+    if ((unsigned long)(size) > (unsigned long)(nb + MINSIZE)) {
+      remainder_size = size - nb;
+      remainder = chunk_at_offset(p, nb);
+      set_head(remainder, remainder_size | PREV_INUSE );
+      set_head_size(p, nb);
+      set_arena_for_chunk(remainder, av);
+      _int_free(av, chunk2mem(remainder));
+    }
+  }
+
+  set_arena_for_chunk(p, av);
+  check_inuse_chunk(av, p);
+  return chunk2mem(p);
+}
+
+#if 1
+/*
+  ------------------------------ calloc ------------------------------
+*/
+
+#if __STD_C
+Void_t* cALLOc(cvmx_arena_list_t arena_list, size_t n_elements, size_t elem_size)
+#else
+Void_t* cALLOc(n_elements, elem_size) size_t n_elements; size_t elem_size;
+#endif
+{
+  mchunkptr p;
+  unsigned long clearsize;
+  unsigned long nclears;
+  INTERNAL_SIZE_T* d;
+
+  Void_t* mem = public_mALLOc(arena_list, n_elements * elem_size);
+
+  if (mem != 0) {
+    p = mem2chunk(mem);
+
+    {
+      /*
+        Unroll clear of <= 36 bytes (72 if 8byte sizes)
+        We know that contents have an odd number of
+        INTERNAL_SIZE_T-sized words; minimally 3.
+      */
+
+      d = (INTERNAL_SIZE_T*)mem;
+      clearsize = chunksize(p) - SIZE_SZ;
+      nclears = clearsize / sizeof(INTERNAL_SIZE_T);
+      assert(nclears >= 3);
+
+      if (nclears > 9)
+        MALLOC_ZERO(d, clearsize);
+
+      else {
+        *(d+0) = 0;
+        *(d+1) = 0;
+        *(d+2) = 0;
+        if (nclears > 4) {
+          *(d+3) = 0;
+          *(d+4) = 0;
+          if (nclears > 6) {
+            *(d+5) = 0;
+            *(d+6) = 0;
+            if (nclears > 8) {
+              *(d+7) = 0;
+              *(d+8) = 0;
+            }
+          }
+        }
+      }
+    }
+  }
+  return mem;
+}
+#endif
+
+
+/*
+  ------------------------- malloc_usable_size -------------------------
+*/
+
+#if __STD_C
+size_t mUSABLe(Void_t* mem)
+#else
+size_t mUSABLe(mem) Void_t* mem;
+#endif
+{
+  mchunkptr p;
+  if (mem != 0) {
+    p = mem2chunk(mem);
+    if (chunk_is_mmapped(p))
+      return chunksize(p) - 3*SIZE_SZ; /* updated size for adding arena_ptr */
+    else if (inuse(p))
+      return chunksize(p) - 2*SIZE_SZ; /* updated size for adding arena_ptr */
+  }
+  return 0;
+}
+
+/*
+  ------------------------------ mallinfo ------------------------------
+*/
+
+struct mallinfo mALLINFo(mstate av)
+{
+  struct mallinfo mi;
+  int i;
+  mbinptr b;
+  mchunkptr p;
+  INTERNAL_SIZE_T avail;
+  INTERNAL_SIZE_T fastavail;
+  int nblocks;
+  int nfastblocks;
+
+  /* Ensure initialization */
+  if (av->top == 0)  malloc_consolidate(av);
+
+  check_malloc_state(av);
+
+  /* Account for top */
+  avail = chunksize(av->top);
+  nblocks = 1;  /* top always exists */
+
+  /* traverse fastbins */
+  nfastblocks = 0;
+  fastavail = 0;
+
+  for (i = 0; i < NFASTBINS; ++i) {
+    for (p = av->fastbins[i]; p != 0; p = p->fd) {
+      ++nfastblocks;
+      fastavail += chunksize(p);
+    }
+  }
+
+  avail += fastavail;
+
+  /* traverse regular bins */
+  for (i = 1; i < NBINS; ++i) {
+    b = bin_at(av, i);
+    for (p = last(b); p != b; p = p->bk) {
+      ++nblocks;
+      avail += chunksize(p);
+    }
+  }
+
+  mi.smblks = nfastblocks;
+  mi.ordblks = nblocks;
+  mi.fordblks = avail;
+  mi.uordblks = av->system_mem - avail;
+  mi.arena = av->system_mem;
+  mi.fsmblks = fastavail;
+  mi.keepcost = chunksize(av->top);
+  return mi;
+}
+
+/*
+  ------------------------------ malloc_stats ------------------------------
+*/
+
+void mSTATs()
+{
+}
+
+
+/*
+  ------------------------------ mallopt ------------------------------
+*/
+
+#if 0
+#if __STD_C
+int mALLOPt(int param_number, int value)
+#else
+int mALLOPt(param_number, value) int param_number; int value;
+#endif
+{
+}
+#endif
+
+
+/*
+  -------------------- Alternative MORECORE functions --------------------
+*/
+
+
+/*
+  General Requirements for MORECORE.
+
+  The MORECORE function must have the following properties:
+
+  If MORECORE_CONTIGUOUS is false:
+
+    * MORECORE must allocate in multiples of pagesize. It will
+      only be called with arguments that are multiples of pagesize.
+
+    * MORECORE(0) must return an address that is at least
+      MALLOC_ALIGNMENT aligned. (Page-aligning always suffices.)
+
+  else (i.e. If MORECORE_CONTIGUOUS is true):
+
+    * Consecutive calls to MORECORE with positive arguments
+      return increasing addresses, indicating that space has been
+      contiguously extended.
+
+    * MORECORE need not allocate in multiples of pagesize.
+      Calls to MORECORE need not have args of multiples of pagesize.
+
+    * MORECORE need not page-align.
+
+  In either case:
+
+    * MORECORE may allocate more memory than requested. (Or even less,
+      but this will generally result in a malloc failure.)
+
+    * MORECORE must not allocate memory when given argument zero, but
+      instead return one past the end address of memory from previous
+      nonzero call. This malloc does NOT call MORECORE(0)
+      until at least one call with positive arguments is made, so
+      the initial value returned is not important.
+
+    * Even though consecutive calls to MORECORE need not return contiguous
+      addresses, it must be OK for malloc'ed chunks to span multiple
+      regions in those cases where they do happen to be contiguous.
+
+    * MORECORE need not handle negative arguments -- it may instead
+      just return MORECORE_FAILURE when given negative arguments.
+      Negative arguments are always multiples of pagesize. MORECORE
+      must not misinterpret negative args as large positive unsigned
+      args. You can suppress all such calls from even occurring by defining
+      MORECORE_CANNOT_TRIM,
+
+  There is some variation across systems about the type of the
+  argument to sbrk/MORECORE. If size_t is unsigned, then it cannot
+  actually be size_t, because sbrk supports negative args, so it is
+  normally the signed type of the same width as size_t (sometimes
+  declared as "intptr_t", and sometimes "ptrdiff_t").  It doesn't much
+  matter though. Internally, we use "long" as arguments, which should
+  work across all reasonable possibilities.
+
+  Additionally, if MORECORE ever returns failure for a positive
+  request, and HAVE_MMAP is true, then mmap is used as a noncontiguous
+  system allocator. This is a useful backup strategy for systems with
+  holes in address spaces -- in this case sbrk cannot contiguously
+  expand the heap, but mmap may be able to map noncontiguous space.
+
+  If you'd like mmap to ALWAYS be used, you can define MORECORE to be
+  a function that always returns MORECORE_FAILURE.
+
+  If you are using this malloc with something other than sbrk (or its
+  emulation) to supply memory regions, you probably want to set
+  MORECORE_CONTIGUOUS as false.  As an example, here is a custom
+  allocator kindly contributed for pre-OSX macOS.  It uses virtually
+  but not necessarily physically contiguous non-paged memory (locked
+  in, present and won't get swapped out).  You can use it by
+  uncommenting this section, adding some #includes, and setting up the
+  appropriate defines above:
+
+      #define MORECORE osMoreCore
+      #define MORECORE_CONTIGUOUS 0
+
+  There is also a shutdown routine that should somehow be called for
+  cleanup upon program exit.
+
+  #define MAX_POOL_ENTRIES 100
+  #define MINIMUM_MORECORE_SIZE  (64 * 1024)
+  static int next_os_pool;
+  void *our_os_pools[MAX_POOL_ENTRIES];
+
+  void *osMoreCore(int size)
+  {
+    void *ptr = 0;
+    static void *sbrk_top = 0;
+
+    if (size > 0)
+    {
+      if (size < MINIMUM_MORECORE_SIZE)
+         size = MINIMUM_MORECORE_SIZE;
+      if (CurrentExecutionLevel() == kTaskLevel)
+         ptr = PoolAllocateResident(size + RM_PAGE_SIZE, 0);
+      if (ptr == 0)
+      {
+        return (void *) MORECORE_FAILURE;
+      }
+      // save ptrs so they can be freed during cleanup
+      our_os_pools[next_os_pool] = ptr;
+      next_os_pool++;
+      ptr = (void *) ((((unsigned long) ptr) + RM_PAGE_MASK) & ~RM_PAGE_MASK);
+      sbrk_top = (char *) ptr + size;
+      return ptr;
+    }
+    else if (size < 0)
+    {
+      // we don't currently support shrink behavior
+      return (void *) MORECORE_FAILURE;
+    }
+    else
+    {
+      return sbrk_top;
+    }
+  }
+
+  // cleanup any allocated memory pools
+  // called as last thing before shutting down driver
+
+  void osCleanupMem(void)
+  {
+    void **ptr;
+
+    for (ptr = our_os_pools; ptr < &our_os_pools[MAX_POOL_ENTRIES]; ptr++)
+      if (*ptr)
+      {
+         PoolDeallocate(*ptr);
+         *ptr = 0;
+      }
+  }
+
+*/
+
+
+
+/* ------------------------------------------------------------
+History:
+
+[see ftp://g.oswego.edu/pub/misc/malloc.c for the history of dlmalloc]
+
+*/
diff --git a/cvmx-malloc/malloc.h b/cvmx-malloc/malloc.h
new file mode 100644
index 0000000000000..6d6f6343f790d
--- /dev/null
+++ b/cvmx-malloc/malloc.h
@@ -0,0 +1,213 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+#ifndef _MALLOC_H
+#define _MALLOC_H 1
+
+#undef _LIBC
+#ifdef _LIBC
+#include <features.h>
+#endif
+
+/*
+  $Id: malloc.h 30481 2007-12-05 21:46:59Z rfranz $
+  `ptmalloc2', a malloc implementation for multiple threads without
+  lock contention, by Wolfram Gloger <wg@malloc.de>.
+
+  VERSION 2.7.0
+
+  This work is mainly derived from malloc-2.7.0 by Doug Lea
+  <dl@cs.oswego.edu>, which is available from:
+
+                 ftp://gee.cs.oswego.edu/pub/misc/malloc.c
+
+  This trimmed-down header file only provides function prototypes and
+  the exported data structures.  For more detailed function
+  descriptions and compile-time options, see the source file
+  `malloc.c'.
+*/
+
+#if 0
+# include <stddef.h>
+# define __malloc_ptr_t  void *
+# undef  size_t
+# define size_t          unsigned long
+# undef  ptrdiff_t
+# define ptrdiff_t       long
+#else
+# undef  Void_t
+# define Void_t       void
+# define __malloc_ptr_t  char *
+#endif
+
+#ifdef _LIBC
+/* Used by GNU libc internals. */
+# define __malloc_size_t size_t
+# define __malloc_ptrdiff_t ptrdiff_t
+#elif !defined __attribute_malloc__
+# define __attribute_malloc__
+#endif
+
+#ifdef __GNUC__
+
+/* GCC can always grok prototypes.  For C++ programs we add throw()
+   to help it optimize the function calls.  But this works only with
+   gcc 2.8.x and egcs.  */
+# if defined __cplusplus && (__GNUC__ >= 3 || __GNUC_MINOR__ >= 8)
+#  define __THROW	throw ()
+# else
+#  define __THROW
+# endif
+# define __MALLOC_P(args)	args __THROW
+/* This macro will be used for functions which might take C++ callback
+   functions.  */
+# define __MALLOC_PMT(args)	args
+
+#else	/* Not GCC.  */
+
+# define __THROW
+
+# if (defined __STDC__ && __STDC__) || defined __cplusplus
+
+#  define __MALLOC_P(args)	args
+#  define __MALLOC_PMT(args)	args
+
+# else	/* Not ANSI C or C++.  */
+
+#  define __MALLOC_P(args)	()	/* No prototypes.  */
+#  define __MALLOC_PMT(args)	()
+
+# endif	/* ANSI C or C++.  */
+
+#endif	/* GCC.  */
+
+#ifndef NULL
+# ifdef __cplusplus
+#  define NULL	0
+# else
+#  define NULL	((__malloc_ptr_t) 0)
+# endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Nonzero if the malloc is already initialized.  */
+#ifdef _LIBC
+/* In the GNU libc we rename the global variable
+   `__malloc_initialized' to `__libc_malloc_initialized'.  */
+# define __malloc_initialized __libc_malloc_initialized
+#endif
+extern int cvmx__malloc_initialized;
+
+
+/* SVID2/XPG mallinfo structure */
+
+struct mallinfo {
+  int arena;    /* non-mmapped space allocated from system */
+  int ordblks;  /* number of free chunks */
+  int smblks;   /* number of fastbin blocks */
+  int hblks;    /* number of mmapped regions */
+  int hblkhd;   /* space in mmapped regions */
+  int usmblks;  /* maximum total allocated space */
+  int fsmblks;  /* space available in freed fastbin blocks */
+  int uordblks; /* total allocated space */
+  int fordblks; /* total free space */
+  int keepcost; /* top-most, releasable (via malloc_trim) space */
+};
+
+/* Returns a copy of the updated current mallinfo. */
+extern struct mallinfo mallinfo __MALLOC_P ((void));
+
+/* SVID2/XPG mallopt options */
+#ifndef M_MXFAST
+# define M_MXFAST  1	/* maximum request size for "fastbins" */
+#endif
+#ifndef M_NLBLKS
+# define M_NLBLKS  2	/* UNUSED in this malloc */
+#endif
+#ifndef M_GRAIN
+# define M_GRAIN   3	/* UNUSED in this malloc */
+#endif
+#ifndef M_KEEP
+# define M_KEEP    4	/* UNUSED in this malloc */
+#endif
+
+/* mallopt options that actually do something */
+#define M_TRIM_THRESHOLD    -1
+#define M_TOP_PAD           -2
+#define M_MMAP_THRESHOLD    -3
+#define M_MMAP_MAX          -4
+#define M_CHECK_ACTION      -5
+
+/* General SVID/XPG interface to tunable parameters. */
+extern int mallopt __MALLOC_P ((int __param, int __val));
+
+/* Release all but __pad bytes of freed top-most memory back to the
+   system. Return 1 if successful, else 0. */
+extern int malloc_trim __MALLOC_P ((size_t __pad));
+
+/* Report the number of usable allocated bytes associated with allocated
+   chunk __ptr. */
+extern size_t malloc_usable_size __MALLOC_P ((__malloc_ptr_t __ptr));
+
+/* Prints brief summary statistics on stderr. */
+extern void malloc_stats __MALLOC_P ((void));
+
+/* Record the state of all malloc variables in an opaque data structure. */
+extern __malloc_ptr_t malloc_get_state __MALLOC_P ((void));
+
+/* Restore the state of all malloc variables from data obtained with
+   malloc_get_state(). */
+extern int malloc_set_state __MALLOC_P ((__malloc_ptr_t __ptr));
+
+/* Called once when malloc is initialized; redefining this variable in
+   the application provides the preferred way to set up the hook
+   pointers. */
+extern void (*cmvx__malloc_initialize_hook) __MALLOC_PMT ((void));
+/* Hooks for debugging and user-defined versions. */
+extern void (*cvmx__free_hook) __MALLOC_PMT ((__malloc_ptr_t __ptr,
+					__const __malloc_ptr_t));
+extern __malloc_ptr_t (*cvmx__malloc_hook) __MALLOC_PMT ((size_t __size,
+						    __const __malloc_ptr_t));
+extern __malloc_ptr_t (*cvmx__realloc_hook) __MALLOC_PMT ((__malloc_ptr_t __ptr,
+						     size_t __size,
+						     __const __malloc_ptr_t));
+extern __malloc_ptr_t (*cvmx__memalign_hook) __MALLOC_PMT ((size_t __alignment,
+						      size_t __size,
+						      __const __malloc_ptr_t));
+extern void (*__after_morecore_hook) __MALLOC_PMT ((void));
+
+/* Activate a standard set of debugging hooks. */
+extern void cvmx__malloc_check_init __MALLOC_P ((void));
+
+/* Internal routines, operating on "arenas".  */
+struct malloc_state;
+typedef struct malloc_state *mstate;
+#ifdef __cplusplus
+}; /* end of extern "C" */
+#endif
+
+
+#endif /* malloc.h */
diff --git a/cvmx-malloc/thread-m.h b/cvmx-malloc/thread-m.h
new file mode 100644
index 0000000000000..de9ba6c6553d0
--- /dev/null
+++ b/cvmx-malloc/thread-m.h
@@ -0,0 +1,73 @@
+/*
+Copyright (c) 2001 Wolfram Gloger
+Copyright (c) 2006 Cavium networks
+
+Permission to use, copy, modify, distribute, and sell this software
+and its documentation for any purpose is hereby granted without fee,
+provided that (i) the above copyright notices and this permission
+notice appear in all copies of the software and related documentation,
+and (ii) the name of Wolfram Gloger may not be used in any advertising
+or publicity relating to the software.
+
+THE SOFTWARE IS PROVIDED "AS-IS" AND WITHOUT WARRANTY OF ANY KIND,
+EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY
+WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
+
+IN NO EVENT SHALL WOLFRAM GLOGER BE LIABLE FOR ANY SPECIAL,
+INCIDENTAL, INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY
+DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER OR NOT ADVISED OF THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY
+OF LIABILITY, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
+*/
+
+/* $Id: thread-m.h 30481 2007-12-05 21:46:59Z rfranz $
+   One out of _LIBC, USE_PTHREADS, USE_THR or USE_SPROC should be
+   defined, otherwise the token NO_THREADS and dummy implementations
+   of the macros will be defined.  */
+
+#ifndef _THREAD_M_H
+#define _THREAD_M_H
+
+#undef thread_atfork_static
+
+
+#undef NO_THREADS /* No threads, provide dummy macros */
+
+typedef int thread_id;
+
+/* The mutex functions used to do absolutely nothing, i.e. lock,
+   trylock and unlock would always just return 0.  However, even
+   without any concurrently active threads, a mutex can be used
+   legitimately as an `in use' flag.  To make the code that is
+   protected by a mutex async-signal safe, these macros would have to
+   be based on atomic test-and-set operations, for example. */
+#ifdef __OCTEON__
+typedef cvmx_spinlock_t mutex_t;
+#define MUTEX_INITIALIZER          CMVX_SPINLOCK_UNLOCKED_VAL
+#define mutex_init(m)              cvmx_spinlock_init(m)
+#define mutex_lock(m)              cvmx_spinlock_lock(m)
+#define mutex_trylock(m)           (cvmx_spinlock_trylock(m))
+#define mutex_unlock(m)            cvmx_spinlock_unlock(m)
+#else
+
+typedef int mutex_t;
+
+#define MUTEX_INITIALIZER          0
+#define mutex_init(m)              (*(m) = 0)
+#define mutex_lock(m)              ((*(m) = 1), 0)
+#define mutex_trylock(m)           (*(m) ? 1 : ((*(m) = 1), 0))
+#define mutex_unlock(m)            (*(m) = 0)
+#endif
+
+
+
+typedef void *tsd_key_t;
+#define tsd_key_create(key, destr) do {} while(0)
+#define tsd_setspecific(key, data) ((key) = (data))
+#define tsd_getspecific(key, vptr) (vptr = (key))
+
+#define thread_atfork(prepare, parent, child) do {} while(0)
+
+
+#endif /* !defined(_THREAD_M_H) */
diff --git a/cvmx-mdio.h b/cvmx-mdio.h
new file mode 100644
index 0000000000000..e203ffe81c7d1
--- /dev/null
+++ b/cvmx-mdio.h
@@ -0,0 +1,559 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
+ * clause 22 and clause 45 operations.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_MIO_H__
+#define __CVMX_MIO_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * PHY register 0 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_CONTROL 0
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t reset : 1;
+        uint16_t loopback : 1;
+        uint16_t speed_lsb : 1;
+        uint16_t autoneg_enable : 1;
+        uint16_t power_down : 1;
+        uint16_t isolate : 1;
+        uint16_t restart_autoneg : 1;
+        uint16_t duplex : 1;
+        uint16_t collision_test : 1;
+        uint16_t speed_msb : 1;
+        uint16_t unidirectional_enable : 1;
+        uint16_t reserved_0_4 : 5;
+    } s;
+} cvmx_mdio_phy_reg_control_t;
+
+/**
+ * PHY register 1 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_STATUS 1
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t capable_100base_t4 : 1;
+        uint16_t capable_100base_x_full : 1;
+        uint16_t capable_100base_x_half : 1;
+        uint16_t capable_10_full : 1;
+        uint16_t capable_10_half : 1;
+        uint16_t capable_100base_t2_full : 1;
+        uint16_t capable_100base_t2_half : 1;
+        uint16_t capable_extended_status : 1;
+        uint16_t capable_unidirectional : 1;
+        uint16_t capable_mf_preamble_suppression : 1;
+        uint16_t autoneg_complete : 1;
+        uint16_t remote_fault : 1;
+        uint16_t capable_autoneg : 1;
+        uint16_t link_status : 1;
+        uint16_t jabber_detect : 1;
+        uint16_t capable_extended_registers : 1;
+
+    } s;
+} cvmx_mdio_phy_reg_status_t;
+
+/**
+ * PHY register 2 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_ID1 2
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t oui_bits_3_18;
+    } s;
+} cvmx_mdio_phy_reg_id1_t;
+
+/**
+ * PHY register 3 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_ID2 3
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t oui_bits_19_24 : 6;
+        uint16_t model : 6;
+        uint16_t revision : 4;
+    } s;
+} cvmx_mdio_phy_reg_id2_t;
+
+/**
+ * PHY register 4 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t next_page : 1;
+        uint16_t reserved_14 : 1;
+        uint16_t remote_fault : 1;
+        uint16_t reserved_12 : 1;
+        uint16_t asymmetric_pause : 1;
+        uint16_t pause : 1;
+        uint16_t advert_100base_t4 : 1;
+        uint16_t advert_100base_tx_full : 1;
+        uint16_t advert_100base_tx_half : 1;
+        uint16_t advert_10base_tx_full : 1;
+        uint16_t advert_10base_tx_half : 1;
+        uint16_t selector : 5;
+    } s;
+} cvmx_mdio_phy_reg_autoneg_adver_t;
+
+/**
+ * PHY register 5 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t next_page : 1;
+        uint16_t ack : 1;
+        uint16_t remote_fault : 1;
+        uint16_t reserved_12 : 1;
+        uint16_t asymmetric_pause : 1;
+        uint16_t pause : 1;
+        uint16_t advert_100base_t4 : 1;
+        uint16_t advert_100base_tx_full : 1;
+        uint16_t advert_100base_tx_half : 1;
+        uint16_t advert_10base_tx_full : 1;
+        uint16_t advert_10base_tx_half : 1;
+        uint16_t selector : 5;
+    } s;
+} cvmx_mdio_phy_reg_link_partner_ability_t;
+
+/**
+ * PHY register 6 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t reserved_5_15 : 11;
+        uint16_t parallel_detection_fault : 1;
+        uint16_t link_partner_next_page_capable : 1;
+        uint16_t local_next_page_capable : 1;
+        uint16_t page_received : 1;
+        uint16_t link_partner_autoneg_capable : 1;
+
+    } s;
+} cvmx_mdio_phy_reg_autoneg_expansion_t;
+
+/**
+ * PHY register 9 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t test_mode : 3;
+        uint16_t manual_master_slave : 1;
+        uint16_t master : 1;
+        uint16_t port_type : 1;
+        uint16_t advert_1000base_t_full : 1;
+        uint16_t advert_1000base_t_half : 1;
+        uint16_t reserved_0_7 : 8;
+    } s;
+} cvmx_mdio_phy_reg_control_1000_t;
+
+/**
+ * PHY register 10 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_STATUS_1000 10
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t master_slave_fault : 1;
+        uint16_t is_master : 1;
+        uint16_t local_receiver_ok : 1;
+        uint16_t remote_receiver_ok : 1;
+        uint16_t remote_capable_1000base_t_full : 1;
+        uint16_t remote_capable_1000base_t_half : 1;
+        uint16_t reserved_8_9 : 2;
+        uint16_t idle_error_count : 8;
+    } s;
+} cvmx_mdio_phy_reg_status_1000_t;
+
+/**
+ * PHY register 15 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t capable_1000base_x_full : 1;
+        uint16_t capable_1000base_x_half : 1;
+        uint16_t capable_1000base_t_full : 1;
+        uint16_t capable_1000base_t_half : 1;
+        uint16_t reserved_0_11 : 12;
+    } s;
+} cvmx_mdio_phy_reg_extended_status_t;
+
+
+/**
+ * PHY register 13 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t function : 2;
+        uint16_t reserved_5_13 : 9;
+        uint16_t devad : 5;
+    } s;
+} cvmx_mdio_phy_reg_mmd_control_t;
+
+/**
+ * PHY register 14 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
+typedef union
+{
+    uint16_t u16;
+    struct
+    {
+        uint16_t address_data : 16;
+    } s;
+} cvmx_mdio_phy_reg_mmd_address_data_t;
+
+/* Operating request encodings. */
+#define MDIO_CLAUSE_22_WRITE    0
+#define MDIO_CLAUSE_22_READ     1
+
+#define MDIO_CLAUSE_45_ADDRESS  0
+#define MDIO_CLAUSE_45_WRITE    1
+#define MDIO_CLAUSE_45_READ_INC 2
+#define MDIO_CLAUSE_45_READ     3
+
+/* MMD identifiers, mostly for accessing devices withing XENPAK modules. */
+#define CVMX_MMD_DEVICE_PMA_PMD      1
+#define CVMX_MMD_DEVICE_WIS          2
+#define CVMX_MMD_DEVICE_PCS          3
+#define CVMX_MMD_DEVICE_PHY_XS       4
+#define CVMX_MMD_DEVICE_DTS_XS       5
+#define CVMX_MMD_DEVICE_TC           6
+#define CVMX_MMD_DEVICE_CL22_EXT     29
+#define CVMX_MMD_DEVICE_VENDOR_1     30
+#define CVMX_MMD_DEVICE_VENDOR_2     31
+
+/* Helper function to put MDIO interface into clause 45 mode */
+static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
+{
+    cvmx_smix_clk_t smi_clk;
+    /* Put bus into clause 45 mode */
+    smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
+    smi_clk.s.mode = 1;
+    smi_clk.s.preamble = 1;
+    cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
+}
+/* Helper function to put MDIO interface into clause 22 mode */
+static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
+{
+    cvmx_smix_clk_t smi_clk;
+    /* Put bus into clause 22 mode */
+    smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
+    smi_clk.s.mode = 0;
+    cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
+}
+
+/**
+ * Perform an MII read. This function is used to read PHY
+ * registers controlling auto negotiation.
+ *
+ * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @param phy_id   The MII phy id
+ * @param location Register location to read
+ *
+ * @return Result from the read or -1 on failure
+ */
+static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
+{
+    cvmx_smix_cmd_t smi_cmd;
+    cvmx_smix_rd_dat_t smi_rd;
+    int timeout = 1000;
+
+    if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+        __cvmx_mdio_set_clause22_mode(bus_id);
+
+    smi_cmd.u64 = 0;
+    smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
+    smi_cmd.s.phy_adr = phy_id;
+    smi_cmd.s.reg_adr = location;
+    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+    do
+    {
+        cvmx_wait(1000);
+        smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
+    } while (smi_rd.s.pending && timeout--);
+
+    if (smi_rd.s.val)
+        return smi_rd.s.dat;
+    else
+        return -1;
+}
+
+
+/**
+ * Perform an MII write. This function is used to write PHY
+ * registers controlling auto negotiation.
+ *
+ * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @param phy_id   The MII phy id
+ * @param location Register location to write
+ * @param val      Value to write
+ *
+ * @return -1 on error
+ *         0 on success
+ */
+static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
+{
+    cvmx_smix_cmd_t smi_cmd;
+    cvmx_smix_wr_dat_t smi_wr;
+    int timeout = 1000;
+
+    if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+        __cvmx_mdio_set_clause22_mode(bus_id);
+
+    smi_wr.u64 = 0;
+    smi_wr.s.dat = val;
+    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+    smi_cmd.u64 = 0;
+    smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
+    smi_cmd.s.phy_adr = phy_id;
+    smi_cmd.s.reg_adr = location;
+    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+    do
+    {
+        cvmx_wait(1000);
+        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+    } while (smi_wr.s.pending && --timeout);
+    if (timeout <= 0)
+        return -1;
+
+    return 0;
+}
+
+/**
+ * Perform an IEEE 802.3 clause 45 MII read. This function is used to read PHY
+ * registers controlling auto negotiation.
+ *
+ * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @param phy_id   The MII phy id
+ * @param device   MDIO Managable Device (MMD) id
+ * @param location Register location to read
+ *
+ * @return Result from the read or -1 on failure
+ */
+
+static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, int location)
+{
+    cvmx_smix_cmd_t smi_cmd;
+    cvmx_smix_rd_dat_t smi_rd;
+    cvmx_smix_wr_dat_t smi_wr;
+    int timeout = 1000;
+
+    if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+        return -1;
+
+    __cvmx_mdio_set_clause45_mode(bus_id);
+
+    smi_wr.u64 = 0;
+    smi_wr.s.dat = location;
+    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+    smi_cmd.u64 = 0;
+    smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
+    smi_cmd.s.phy_adr = phy_id;
+    smi_cmd.s.reg_adr = device;
+    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+    do
+    {
+        cvmx_wait(1000);
+        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+    } while (smi_wr.s.pending && --timeout);
+    if (timeout <= 0)
+    {
+        cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(address)\n", bus_id, phy_id, device, location);
+        return -1;
+    }
+
+    smi_cmd.u64 = 0;
+    smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
+    smi_cmd.s.phy_adr = phy_id;
+    smi_cmd.s.reg_adr = device;
+    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+    do
+    {
+        cvmx_wait(1000);
+        smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
+    } while (smi_rd.s.pending && timeout--);
+
+    if(timeout <= 0)
+    {
+        cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(data)\n", bus_id, phy_id, device, location);
+        return -1;
+    }
+
+    if (smi_rd.s.val)
+        return smi_rd.s.dat;
+    else
+    {
+        cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   INVALID READ\n", bus_id, phy_id, device, location);
+        return -1;
+    }
+}
+
+/**
+ * Perform an IEEE 802.3 clause 45 MII write. This function is used to write PHY
+ * registers controlling auto negotiation.
+ *
+ * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @param phy_id   The MII phy id
+ * @param device   MDIO Managable Device (MMD) id
+ * @param location Register location to write
+ * @param val      Value to write
+ *
+ * @return -1 on error
+ *         0 on success
+ */
+static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int location,
+                                     int val)
+{
+    cvmx_smix_cmd_t smi_cmd;
+    cvmx_smix_wr_dat_t smi_wr;
+    int timeout = 1000;
+
+    if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+        return -1;
+
+    __cvmx_mdio_set_clause45_mode(bus_id);
+
+    smi_wr.u64 = 0;
+    smi_wr.s.dat = location;
+    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+    smi_cmd.u64 = 0;
+    smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
+    smi_cmd.s.phy_adr = phy_id;
+    smi_cmd.s.reg_adr = device;
+    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+    do
+    {
+        cvmx_wait(1000);
+        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+    } while (smi_wr.s.pending && --timeout);
+    if (timeout <= 0)
+        return -1;
+
+    smi_wr.u64 = 0;
+    smi_wr.s.dat = val;
+    cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+    smi_cmd.u64 = 0;
+    smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
+    smi_cmd.s.phy_adr = phy_id;
+    smi_cmd.s.reg_adr = device;
+    cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+    do
+    {
+        cvmx_wait(1000);
+        smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+    } while (smi_wr.s.pending && --timeout);
+    if (timeout <= 0)
+        return -1;
+
+    return 0;
+}
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-mgmt-port.c b/cvmx-mgmt-port.c
new file mode 100644
index 0000000000000..f40cb8ccaa8b7
--- /dev/null
+++ b/cvmx-mgmt-port.c
@@ -0,0 +1,759 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support functions for managing the MII management port
+ *
+ * <hr>$Revision: 42151 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-mdio.h"
+#include "cvmx-mgmt-port.h"
+#include "cvmx-sysinfo.h"
+
+/**
+ * Format of the TX/RX ring buffer entries
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    len             : 14;   /* Length of the buffer/packet in bytes */
+        uint64_t    code            : 8;    /* The RX error code */
+        uint64_t    addr            : 40;   /* Physical address of the buffer */
+    } s;
+} cvmx_mgmt_port_ring_entry_t;
+
+/**
+ * Per port state required for each mgmt port
+ */
+typedef struct
+{
+    cvmx_spinlock_t             lock;           /* Used for exclusive access to this structure */
+    int                         tx_write_index; /* Where the next TX will write in the tx_ring and tx_buffers */
+    int                         rx_read_index;  /* Where the next RX will be in the rx_ring and rx_buffers */
+    int                         phy_id;         /* The SMI/MDIO PHY address */
+    uint64_t                    mac;            /* Our MAC address */
+    cvmx_mgmt_port_ring_entry_t tx_ring[CVMX_MGMT_PORT_NUM_TX_BUFFERS];
+    cvmx_mgmt_port_ring_entry_t rx_ring[CVMX_MGMT_PORT_NUM_RX_BUFFERS];
+    char                        tx_buffers[CVMX_MGMT_PORT_NUM_TX_BUFFERS][CVMX_MGMT_PORT_TX_BUFFER_SIZE];
+    char                        rx_buffers[CVMX_MGMT_PORT_NUM_RX_BUFFERS][CVMX_MGMT_PORT_RX_BUFFER_SIZE];
+} cvmx_mgmt_port_state_t;
+
+/**
+ * Pointers to each mgmt port's state
+ */
+CVMX_SHARED cvmx_mgmt_port_state_t *cvmx_mgmt_port_state_ptr = NULL;
+
+
+/**
+ * Return the number of management ports supported by this chip
+ *
+ * @return Number of ports
+ */
+int __cvmx_mgmt_port_num_ports(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX))
+        return 1;
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        return 2;
+    else
+        return 0;
+}
+
+
+/**
+ * Called to initialize a management port for use. Multiple calls
+ * to this function accross applications is safe.
+ *
+ * @param port   Port to initialize
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port)
+{
+    char *alloc_name = "cvmx_mgmt_port";
+    cvmx_mixx_oring1_t oring1;
+    cvmx_mixx_ctl_t mix_ctl;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    cvmx_mgmt_port_state_ptr = cvmx_bootmem_alloc_named(CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t), 128, alloc_name);
+    if (cvmx_mgmt_port_state_ptr)
+    {
+        memset(cvmx_mgmt_port_state_ptr, 0, CVMX_MGMT_PORT_NUM_PORTS * sizeof(cvmx_mgmt_port_state_t));
+    }
+    else
+    {
+        cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(alloc_name);
+        if (block_desc)
+            cvmx_mgmt_port_state_ptr = cvmx_phys_to_ptr(block_desc->base_addr);
+        else
+        {
+            cvmx_dprintf("ERROR: cvmx_mgmt_port_initialize: Unable to get named block %s.\n", alloc_name);
+            return CVMX_MGMT_PORT_NO_MEMORY;
+        }
+    }
+
+    /* Reset the MIX block if the previous user had a different TX ring size, or if
+    ** we allocated a new (and blank) state structure. */
+    mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
+    if (!mix_ctl.s.reset)
+    {
+        oring1.u64 = cvmx_read_csr(CVMX_MIXX_ORING1(port));
+        if (oring1.s.osize != CVMX_MGMT_PORT_NUM_TX_BUFFERS || cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0)
+        {
+            mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
+            mix_ctl.s.en = 0;
+            cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
+            do
+            {
+                mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
+            } while (mix_ctl.s.busy);
+            mix_ctl.s.reset = 1;
+            cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
+            cvmx_read_csr(CVMX_MIXX_CTL(port));
+            memset(cvmx_mgmt_port_state_ptr + port, 0, sizeof(cvmx_mgmt_port_state_t));
+        }
+    }
+
+
+    if (cvmx_mgmt_port_state_ptr[port].tx_ring[0].u64 == 0)
+    {
+        cvmx_mgmt_port_state_t *state = cvmx_mgmt_port_state_ptr + port;
+        int i;
+        cvmx_mixx_bist_t mix_bist;
+        cvmx_agl_gmx_bist_t agl_gmx_bist;
+        cvmx_mixx_oring1_t oring1;
+        cvmx_mixx_iring1_t iring1;
+        cvmx_mixx_ctl_t mix_ctl;
+
+        /* Make sure BIST passed */
+        mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(port));
+        if (mix_bist.u64)
+            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port MIX failed BIST (0x%016llx)\n", CAST64(mix_bist.u64));
+
+        agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
+        if (agl_gmx_bist.u64)
+            cvmx_dprintf("WARNING: cvmx_mgmt_port_initialize: Managment port AGL failed BIST (0x%016llx)\n", CAST64(agl_gmx_bist.u64));
+
+        /* Clear all state information */
+        memset(state, 0, sizeof(*state));
+
+        /* Take the control logic out of reset */
+        mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
+        mix_ctl.s.reset = 0;
+        cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
+
+        /* Set the PHY address */
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+            state->phy_id = -1;
+        else
+            state->phy_id = port;  /* Will need to be change to match the board */
+
+        /* Create a default MAC address */
+        state->mac = 0x000000dead000000ull;
+        state->mac += 0xffffff & CAST64(state);
+
+        /* Setup the TX ring */
+        for (i=0; i<CVMX_MGMT_PORT_NUM_TX_BUFFERS; i++)
+        {
+            state->tx_ring[i].s.len = CVMX_MGMT_PORT_TX_BUFFER_SIZE;
+            state->tx_ring[i].s.addr = cvmx_ptr_to_phys(state->tx_buffers[i]);
+        }
+
+        /* Tell the HW where the TX ring is */
+        oring1.u64 = 0;
+        oring1.s.obase = cvmx_ptr_to_phys(state->tx_ring)>>3;
+        oring1.s.osize = CVMX_MGMT_PORT_NUM_TX_BUFFERS;
+        CVMX_SYNCWS;
+        cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
+
+        /* Setup the RX ring */
+        for (i=0; i<CVMX_MGMT_PORT_NUM_RX_BUFFERS; i++)
+        {
+            /* This size is -8 due to an errata for CN56XX pass 1 */
+            state->rx_ring[i].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8;
+            state->rx_ring[i].s.addr = cvmx_ptr_to_phys(state->rx_buffers[i]);
+        }
+
+        /* Tell the HW where the RX ring is */
+        iring1.u64 = 0;
+        iring1.s.ibase = cvmx_ptr_to_phys(state->rx_ring)>>3;
+        iring1.s.isize = CVMX_MGMT_PORT_NUM_RX_BUFFERS;
+        CVMX_SYNCWS;
+        cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
+        cvmx_write_csr(CVMX_MIXX_IRING2(port), CVMX_MGMT_PORT_NUM_RX_BUFFERS);
+
+        /* Disable the external input/output */
+        cvmx_mgmt_port_disable(port);
+
+        /* Set the MAC address filtering up */
+        cvmx_mgmt_port_set_mac(port, state->mac);
+
+        /* Set the default max size to an MTU of 1500 with L2 and VLAN */
+        cvmx_mgmt_port_set_max_packet_size(port, 1518);
+
+        /* Enable the port HW. Packets are not allowed until cvmx_mgmt_port_enable() is called */
+        mix_ctl.u64 = 0;
+        mix_ctl.s.crc_strip = 1;    /* Strip the ending CRC */
+        mix_ctl.s.en = 1;           /* Enable the port */
+        mix_ctl.s.nbtarb = 0;       /* Arbitration mode */
+        mix_ctl.s.mrq_hwm = 1;      /* MII CB-request FIFO programmable high watermark */
+        cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+        {
+            /* Force compensation values, as they are not determined properly by HW */
+            cvmx_agl_gmx_drv_ctl_t drv_ctl;
+
+            drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
+            if (port)
+            {
+                drv_ctl.s.byp_en1 = 1;
+                drv_ctl.s.nctl1 = 6;
+                drv_ctl.s.pctl1 = 6;
+            }
+            else
+            {
+                drv_ctl.s.byp_en = 1;
+                drv_ctl.s.nctl = 6;
+                drv_ctl.s.pctl = 6;
+            }
+            cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
+        }
+    }
+    return CVMX_MGMT_PORT_SUCCESS;
+}
+
+
+/**
+ * Shutdown a management port. This currently disables packet IO
+ * but leaves all hardware and buffers. Another application can then
+ * call initialize() without redoing the hardware setup.
+ *
+ * @param port   Management port
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+cvmx_mgmt_port_result_t cvmx_mgmt_port_shutdown(int port)
+{
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    /* Stop packets from comming in */
+    cvmx_mgmt_port_disable(port);
+
+    /* We don't free any memory so the next intialize can reuse the HW setup */
+    return CVMX_MGMT_PORT_SUCCESS;
+}
+
+
+/**
+ * Enable packet IO on a management port
+ *
+ * @param port   Management port
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+cvmx_mgmt_port_result_t cvmx_mgmt_port_enable(int port)
+{
+    cvmx_mgmt_port_state_t *state;
+    cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
+    cvmx_agl_gmx_inf_mode_t agl_gmx_inf_mode;
+    cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+
+    rxx_frm_ctl.u64 = 0;
+    rxx_frm_ctl.s.pre_align = 1;
+    rxx_frm_ctl.s.pad_len = 1;  /* When set, disables the length check for non-min sized pkts with padding in the client data */
+    rxx_frm_ctl.s.vlan_len = 1; /* When set, disables the length check for VLAN pkts */
+    rxx_frm_ctl.s.pre_free = 1; /* When set, PREAMBLE checking is  less strict */
+    rxx_frm_ctl.s.ctl_smac = 0; /* Control Pause Frames can match station SMAC */
+    rxx_frm_ctl.s.ctl_mcst = 1; /* Control Pause Frames can match globally assign Multicast address */
+    rxx_frm_ctl.s.ctl_bck = 1;  /* Forward pause information to TX block */
+    rxx_frm_ctl.s.ctl_drp = 1;  /* Drop Control Pause Frames */
+    rxx_frm_ctl.s.pre_strp = 1; /* Strip off the preamble */
+    rxx_frm_ctl.s.pre_chk = 1;  /* This port is configured to send PREAMBLE+SFD to begin every frame.  GMX checks that the PREAMBLE is sent correctly */
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
+
+    /* Enable the AGL block */
+    agl_gmx_inf_mode.u64 = 0;
+    agl_gmx_inf_mode.s.en = 1;
+    cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
+
+    /* Configure the port duplex and enables */
+    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
+    agl_gmx_prtx.s.tx_en = 1;
+    agl_gmx_prtx.s.rx_en = 1;
+    if (cvmx_mgmt_port_get_link(port) < 0)
+        agl_gmx_prtx.s.duplex = 0;
+    else
+        agl_gmx_prtx.s.duplex = 1;
+    agl_gmx_prtx.s.en = 1;
+    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+
+    cvmx_spinlock_unlock(&state->lock);
+    return CVMX_MGMT_PORT_SUCCESS;
+}
+
+
+/**
+ * Disable packet IO on a management port
+ *
+ * @param port   Management port
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+cvmx_mgmt_port_result_t cvmx_mgmt_port_disable(int port)
+{
+    cvmx_mgmt_port_state_t *state;
+    cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+
+    agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
+    agl_gmx_prtx.s.en = 0;
+    cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+
+    cvmx_spinlock_unlock(&state->lock);
+    return CVMX_MGMT_PORT_SUCCESS;
+}
+
+
+/**
+ * Send a packet out the management port. The packet is copied so
+ * the input buffer isn't used after this call.
+ *
+ * @param port       Management port
+ * @param packet_len Length of the packet to send. It does not include the final CRC
+ * @param buffer     Packet data
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+cvmx_mgmt_port_result_t cvmx_mgmt_port_send(int port, int packet_len, void *buffer)
+{
+    cvmx_mgmt_port_state_t *state;
+    cvmx_mixx_oring2_t mix_oring2;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    /* Max sure the packet size is valid */
+    if ((packet_len < 1) || (packet_len > CVMX_MGMT_PORT_TX_BUFFER_SIZE))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    if (buffer == NULL)
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+
+    mix_oring2.u64 = cvmx_read_csr(CVMX_MIXX_ORING2(port));
+    if (mix_oring2.s.odbell >= CVMX_MGMT_PORT_NUM_TX_BUFFERS - 1)
+    {
+        /* No room for another packet */
+        cvmx_spinlock_unlock(&state->lock);
+        return CVMX_MGMT_PORT_NO_MEMORY;
+    }
+    else
+    {
+        /* Copy the packet into the output buffer */
+        memcpy(state->tx_buffers[state->tx_write_index], buffer, packet_len);
+        /* Insert the source MAC */
+        memcpy(state->tx_buffers[state->tx_write_index] + 6, ((char*)&state->mac) + 2, 6);
+        /* Update the TX ring buffer entry size */
+        state->tx_ring[state->tx_write_index].s.len = packet_len;
+        /* Increment our TX index */
+        state->tx_write_index = (state->tx_write_index + 1) % CVMX_MGMT_PORT_NUM_TX_BUFFERS;
+        /* Ring the doorbell, send ing the packet */
+        CVMX_SYNCWS;
+        cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
+        if (cvmx_read_csr(CVMX_MIXX_ORCNT(port)))
+            cvmx_write_csr(CVMX_MIXX_ORCNT(port), cvmx_read_csr(CVMX_MIXX_ORCNT(port)));
+
+        cvmx_spinlock_unlock(&state->lock);
+        return CVMX_MGMT_PORT_SUCCESS;
+    }
+}
+
+
+/**
+ * Receive a packet from the management port.
+ *
+ * @param port       Management port
+ * @param buffer_len Size of the buffer to receive the packet into
+ * @param buffer     Buffer to receive the packet into
+ *
+ * @return The size of the packet, or a negative erorr code on failure. Zero
+ *         means that no packets were available.
+ */
+int cvmx_mgmt_port_receive(int port, int buffer_len, void *buffer)
+{
+    cvmx_mixx_ircnt_t mix_ircnt;
+    cvmx_mgmt_port_state_t *state;
+    int result;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    /* Max sure the buffer size is valid */
+    if (buffer_len < 1)
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    if (buffer == NULL)
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+
+    /* Find out how many RX packets are pending */
+    mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
+    if (mix_ircnt.s.ircnt)
+    {
+        void *source = state->rx_buffers[state->rx_read_index];
+        uint64_t *zero_check = source;
+        /* CN56XX pass 1 has an errata where packets might start 8 bytes
+            into the buffer instead of at their correct lcoation. If the
+            first 8 bytes is zero we assume this has happened */
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && (*zero_check == 0))
+            source += 8;
+        /* Start off with zero bytes received */
+        result = 0;
+        /* While the completion code signals more data, copy the buffers
+            into the user's data */
+        while (state->rx_ring[state->rx_read_index].s.code == 16)
+        {
+            /* Only copy what will fit in the user's buffer */
+            int length = state->rx_ring[state->rx_read_index].s.len;
+            if (length > buffer_len)
+                length = buffer_len;
+            memcpy(buffer, source, length);
+            /* Reduce the size of the buffer to the remaining space. If we run
+                out we will signal an error when the code 15 buffer doesn't fit */
+            buffer += length;
+            buffer_len -= length;
+            result += length;
+            /* Update this buffer for reuse in future receives. This size is
+                -8 due to an errata for CN56XX pass 1 */
+            state->rx_ring[state->rx_read_index].s.code = 0;
+            state->rx_ring[state->rx_read_index].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8;
+            state->rx_read_index = (state->rx_read_index + 1) % CVMX_MGMT_PORT_NUM_RX_BUFFERS;
+            /* Zero the beginning of the buffer for use by the errata check */
+            *zero_check = 0;
+            CVMX_SYNCWS;
+            /* Increment the number of RX buffers */
+            cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
+            source = state->rx_buffers[state->rx_read_index];
+            zero_check = source;
+        }
+
+        /* Check for the final good completion code */
+        if (state->rx_ring[state->rx_read_index].s.code == 15)
+        {
+            if (buffer_len >= state->rx_ring[state->rx_read_index].s.len)
+            {
+                int length = state->rx_ring[state->rx_read_index].s.len;
+                memcpy(buffer, source, length);
+                result += length;
+            }
+            else
+            {
+                /* Not enough room for the packet */
+                cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Packet (%d) larger than supplied buffer (%d)\n", state->rx_ring[state->rx_read_index].s.len, buffer_len);
+                result = CVMX_MGMT_PORT_NO_MEMORY;
+            }
+        }
+        else
+        {
+            cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
+            cvmx_dprintf("ERROR: cvmx_mgmt_port_receive: Receive error code %d. Packet dropped(Len %d), \n",
+                         state->rx_ring[state->rx_read_index].s.code, state->rx_ring[state->rx_read_index].s.len + result);
+            result = -state->rx_ring[state->rx_read_index].s.code;
+
+
+            /* Check to see if we need to change the duplex. */
+            agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
+            if (cvmx_mgmt_port_get_link(port) < 0)
+                agl_gmx_prtx.s.duplex = 0;
+            else
+                agl_gmx_prtx.s.duplex = 1;
+            cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+        }
+
+        /* Clean out the ring buffer entry. This size is -8 due to an errata
+            for CN56XX pass 1 */
+        state->rx_ring[state->rx_read_index].s.code = 0;
+        state->rx_ring[state->rx_read_index].s.len = CVMX_MGMT_PORT_RX_BUFFER_SIZE - 8;
+        state->rx_read_index = (state->rx_read_index + 1) % CVMX_MGMT_PORT_NUM_RX_BUFFERS;
+        /* Zero the beginning of the buffer for use by the errata check */
+        *zero_check = 0;
+        CVMX_SYNCWS;
+        /* Increment the number of RX buffers */
+        cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
+        /* Decrement the pending RX count */
+        cvmx_write_csr(CVMX_MIXX_IRCNT(port), 1);
+    }
+    else
+    {
+        /* No packets available */
+        result = 0;
+    }
+    cvmx_spinlock_unlock(&state->lock);
+    return result;
+}
+
+
+/**
+ * Get the management port link status:
+ * 100 = 100Mbps, full duplex
+ * 10 = 10Mbps, full duplex
+ * 0 = Link down
+ * -10 = 10Mpbs, half duplex
+ * -100 = 100Mbps, half duplex
+ *
+ * @param port   Management port
+ *
+ * @return
+ */
+int cvmx_mgmt_port_get_link(int port)
+{
+    cvmx_mgmt_port_state_t *state;
+    int phy_status;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    /* Assume 100Mbps if we don't know the PHY address */
+    if (state->phy_id == -1)
+        return 100;
+
+
+    /* read BCM phy MDIO aux status summary register */
+    phy_status = cvmx_mdio_read(state->phy_id >> 8, state->phy_id & 0xff,
+				    0x19);
+    /* check the link status first */
+    if ((phy_status & 0x8000) == 0)
+      return 0;
+
+    switch ((phy_status >> 8) & 0x7)
+      {
+      case 0:
+	/* link down */
+	return 0;
+      case 1:
+	/* 10 half */
+	return -10;
+      case 2:
+	/* 10 full */
+	return 10;
+      case 3:
+	/* 100 half */
+	return -100;
+      case 4:
+	/* 100 T4 */
+	return 100;
+      case 5:
+	/* 100 full */
+	return 100;
+      case 6:
+	/* 1000 half */
+	return -1000;
+      case 7:
+	/* 1000 full */
+	return 1000;
+      }
+    /* something's amiss if we get here... */
+    return 0;
+}
+
+
+/**
+ * Set the MAC address for a management port
+ *
+ * @param port   Management port
+ * @param mac    New MAC address. The lower 6 bytes are used.
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+cvmx_mgmt_port_result_t cvmx_mgmt_port_set_mac(int port, uint64_t mac)
+{
+    cvmx_mgmt_port_state_t *state;
+    cvmx_agl_gmx_rxx_adr_ctl_t agl_gmx_rxx_adr_ctl;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+
+    agl_gmx_rxx_adr_ctl.u64 = 0;
+    agl_gmx_rxx_adr_ctl.s.cam_mode = 1; /* Only accept matching MAC addresses */
+    agl_gmx_rxx_adr_ctl.s.mcst = 0;     /* Drop multicast */
+    agl_gmx_rxx_adr_ctl.s.bcst = 1;     /* Allow broadcast */
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), agl_gmx_rxx_adr_ctl.u64);
+
+    /* Only using one of the CAMs */
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), (mac >> 40) & 0xff);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), (mac >> 32) & 0xff);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), (mac >> 24) & 0xff);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), (mac >> 16) & 0xff);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), (mac >> 8) & 0xff);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), (mac >> 0) & 0xff);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1);
+    state->mac = mac;
+
+    cvmx_spinlock_unlock(&state->lock);
+    return CVMX_MGMT_PORT_SUCCESS;
+}
+
+
+/**
+ * Get the MAC address for a management port
+ *
+ * @param port   Management port
+ *
+ * @return MAC address
+ */
+uint64_t cvmx_mgmt_port_get_mac(int port)
+{
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return CVMX_MGMT_PORT_INVALID_PARAM;
+
+    return cvmx_mgmt_port_state_ptr[port].mac;
+}
+
+/**
+ * Set the multicast list.
+ *
+ * @param port   Management port
+ * @param flags  Interface flags
+ *
+ * @return
+ */
+void cvmx_mgmt_port_set_multicast_list(int port, int flags)
+{
+    cvmx_mgmt_port_state_t *state;
+    cvmx_agl_gmx_rxx_adr_ctl_t agl_gmx_rxx_adr_ctl;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+
+    agl_gmx_rxx_adr_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port));
+    
+    /* Allow broadcast MAC addresses */
+    if (!agl_gmx_rxx_adr_ctl.s.bcst)
+	agl_gmx_rxx_adr_ctl.s.bcst = 1;
+
+    if ((flags & CVMX_IFF_ALLMULTI) || (flags & CVMX_IFF_PROMISC))
+	agl_gmx_rxx_adr_ctl.s.mcst = 2; /* Force accept multicast packets */
+    else
+	agl_gmx_rxx_adr_ctl.s.mcst = 1; /* Force reject multicast packets */
+
+    if (flags & CVMX_IFF_PROMISC)
+	agl_gmx_rxx_adr_ctl.s.cam_mode = 0; /* Reject matches if promisc. Since CAM is shut off, should accept everything */
+    else
+	agl_gmx_rxx_adr_ctl.s.cam_mode = 1; /* Filter packets based on the CAM */
+
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), agl_gmx_rxx_adr_ctl.u64);
+
+    if (flags & CVMX_IFF_PROMISC)
+	cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 0);
+    else
+	cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), 1);
+    
+    cvmx_spinlock_unlock(&state->lock);
+}
+
+
+/**
+ * Set the maximum packet allowed in. Size is specified
+ * including L2 but without FCS. A normal MTU would corespond
+ * to 1514 assuming the standard 14 byte L2 header.
+ *
+ * @param port   Management port
+ * @param size_without_fcs
+ *               Size in bytes without FCS
+ */
+void cvmx_mgmt_port_set_max_packet_size(int port, int size_without_fcs)
+{
+    cvmx_mgmt_port_state_t *state;
+
+    if ((port < 0) || (port >= __cvmx_mgmt_port_num_ports()))
+        return;
+
+    state = cvmx_mgmt_port_state_ptr + port;
+
+    cvmx_spinlock_lock(&state->lock);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
+    cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), (size_without_fcs+7) & 0xfff8);
+    cvmx_spinlock_unlock(&state->lock);
+}
+
diff --git a/cvmx-mgmt-port.h b/cvmx-mgmt-port.h
new file mode 100644
index 0000000000000..6b78cf60cfa2b
--- /dev/null
+++ b/cvmx-mgmt-port.h
@@ -0,0 +1,193 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support functions for managing the MII management port
+ *
+ * <hr>$Revision: 42115 $<hr>
+ */
+
+#ifndef __CVMX_MGMT_PORT_H__
+#define __CVMX_MGMT_PORT_H__
+
+#define CVMX_MGMT_PORT_NUM_PORTS        2       /* Right now we only have one mgmt port */
+#define CVMX_MGMT_PORT_NUM_TX_BUFFERS   16      /* Number of TX ring buffer entries and buffers */
+#define CVMX_MGMT_PORT_NUM_RX_BUFFERS   128     /* Number of RX ring buffer entries and buffers */
+#define CVMX_MGMT_PORT_TX_BUFFER_SIZE   12288   /* Size of each TX/RX buffer */
+#define CVMX_MGMT_PORT_RX_BUFFER_SIZE   1536    /* Size of each TX/RX buffer */
+
+typedef enum
+{
+    CVMX_MGMT_PORT_SUCCESS = 0,
+    CVMX_MGMT_PORT_NO_MEMORY = -1,
+    CVMX_MGMT_PORT_INVALID_PARAM = -2,
+} cvmx_mgmt_port_result_t;
+
+
+/* Enumeration of Net Device interface flags. */
+typedef enum 
+{
+    CVMX_IFF_PROMISC = 0x100, 		/* receive all packets           */
+    CVMX_IFF_ALLMULTI = 0x200, 		/* receive all multicast packets */
+} cvmx_mgmt_port_netdevice_flags_t;
+
+/**
+ * Called to initialize a management port for use. Multiple calls
+ * to this function accross applications is safe.
+ *
+ * @param port   Port to initialize
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+extern cvmx_mgmt_port_result_t cvmx_mgmt_port_initialize(int port);
+
+/**
+ * Shutdown a management port. This currently disables packet IO
+ * but leaves all hardware and buffers. Another application can then
+ * call initialize() without redoing the hardware setup.
+ *
+ * @param port   Management port
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+extern cvmx_mgmt_port_result_t cvmx_mgmt_port_shutdown(int port);
+
+/**
+ * Enable packet IO on a management port
+ *
+ * @param port   Management port
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+extern cvmx_mgmt_port_result_t cvmx_mgmt_port_enable(int port);
+
+/**
+ * Disable packet IO on a management port
+ *
+ * @param port   Management port
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+extern cvmx_mgmt_port_result_t cvmx_mgmt_port_disable(int port);
+
+/**
+ * Send a packet out the management port. The packet is copied so
+ * the input buffer isn't used after this call.
+ *
+ * @param port       Management port
+ * @param packet_len Length of the packet to send. It does not include the final CRC
+ * @param buffer     Packet data
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+extern cvmx_mgmt_port_result_t cvmx_mgmt_port_send(int port, int packet_len, void *buffer);
+
+/**
+ * Receive a packet from the management port.
+ *
+ * @param port       Management port
+ * @param buffer_len Size of the buffer to receive the packet into
+ * @param buffer     Buffer to receive the packet into
+ *
+ * @return The size of the packet, or a negative erorr code on failure. Zero
+ *         means that no packets were available.
+ */
+extern int cvmx_mgmt_port_receive(int port, int buffer_len, void *buffer);
+
+/**
+ * Get the management port link status:
+ * 100 = 100Mbps, full duplex
+ * 10 = 10Mbps, full duplex
+ * 0 = Link down
+ * -10 = 10Mpbs, half duplex
+ * -100 = 100Mbps, half duplex
+ *
+ * @param port   Management port
+ *
+ * @return
+ */
+extern int cvmx_mgmt_port_get_link(int port);
+
+/**
+ * Set the MAC address for a management port
+ *
+ * @param port   Management port
+ * @param mac    New MAC address. The lower 6 bytes are used.
+ *
+ * @return CVMX_MGMT_PORT_SUCCESS or an error code
+ */
+extern cvmx_mgmt_port_result_t cvmx_mgmt_port_set_mac(int port, uint64_t mac);
+
+/**
+ * Get the MAC address for a management port
+ *
+ * @param port   Management port
+ *
+ * @return MAC address
+ */
+extern uint64_t cvmx_mgmt_port_get_mac(int port);
+
+/**
+ * Set the multicast list.
+ *
+ * @param port   Management port
+ * @param flags  Interface flags
+ *
+ * @return
+ */
+extern void cvmx_mgmt_port_set_multicast_list(int port, int flags);
+
+/**
+ * Set the maximum packet allowed in. Size is specified
+ * including L2 but without FCS. A normal MTU would corespond
+ * to 1514 assuming the standard 14 byte L2 header.
+ *
+ * @param port   Management port
+ * @param size_without_crc
+ *               Size in bytes without FCS
+ */
+extern void cvmx_mgmt_port_set_max_packet_size(int port, int size_without_fcs);
+
+#endif /* __CVMX_MGMT_PORT_H__ */
diff --git a/cvmx-mio.h b/cvmx-mio.h
new file mode 100644
index 0000000000000..ee85968fab31f
--- /dev/null
+++ b/cvmx-mio.h
@@ -0,0 +1,66 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the MIO hardware.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_MIO_H__
+#define __CVMX_MIO_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-nand.c b/cvmx-nand.c
new file mode 100644
index 0000000000000..30377ca3f4f55
--- /dev/null
+++ b/cvmx-nand.c
@@ -0,0 +1,1719 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Interface to the NAND flash controller.
+ * See cvmx-nand.h for usage documentation and notes.
+ *
+ * <hr>$Revision: 35726 $<hr>
+ */
+
+#include "cvmx.h"
+#include "cvmx-nand.h"
+#include "cvmx-swap.h"
+#include "cvmx-bootmem.h"
+
+#define NAND_COMMAND_READ_ID            0x90
+#define NAND_COMMAND_READ_PARAM_PAGE    0xec
+#define NAND_COMMAND_RESET              0xff
+#define NAND_COMMAND_STATUS             0x70
+#define NAND_COMMAND_READ               0x00
+#define NAND_COMMAND_READ_FIN           0x30
+#define NAND_COMMAND_ERASE              0x60
+#define NAND_COMMAND_ERASE_FIN          0xd0
+#define NAND_COMMAND_PROGRAM            0x80
+#define NAND_COMMAND_PROGRAM_FIN        0x10
+#define NAND_TIMEOUT_USECS              1000000
+
+#define CVMX_NAND_ROUNDUP(_Dividend, _Divisor) (((_Dividend)+(_Divisor-1))/(_Divisor))
+#undef min
+#define min(X, Y)                               \
+        ({ typeof (X) __x = (X), __y = (Y);     \
+                (__x < __y) ? __x : __y; })
+
+#undef max
+#define max(X, Y)                               \
+        ({ typeof (X) __x = (X), __y = (Y);     \
+                (__x > __y) ? __x : __y; })
+
+
+/* Structure to store the parameters that we care about that
+** describe the ONFI speed modes.  This is used to configure
+** the flash timing to match what is reported in the 
+** parameter page of the ONFI flash chip. */
+typedef struct
+{
+    int twp;
+    int twh;
+    int twc;
+    int tclh;
+    int tals;
+} onfi_speed_mode_desc_t;
+static const onfi_speed_mode_desc_t onfi_speed_modes[] =
+{
+
+    {50,30,100,20,50},  /* Mode 0 */
+    {25,15, 45,10,25},  /* Mode 1 */
+    {17,15, 35,10,15},  /* Mode 2 */
+    {15,10, 30, 5,10},  /* Mode 3 */
+    {12,10, 25, 5,10},  /* Mode 4, requires EDO timings */
+    {10, 7, 20, 5,10},  /* Mode 5, requries EDO timings */
+};
+
+/**
+ * Structure used to store data about the NAND devices hooked
+ * to the bootbus.
+ */
+typedef struct
+{
+    int page_size;
+    int oob_size;
+    int pages_per_block;
+    int blocks;
+    int tim_mult;
+    int tim_par[8];
+    int clen[4];
+    int alen[4];
+    int rdn[4];
+    int wrn[2];
+    int onfi_timing;
+} cvmx_nand_state_t;
+
+/**
+ * Array indexed by bootbus chip select with information
+ * about NAND devices.
+ */
+#if defined(CVMX_BUILD_FOR_UBOOT) && CONFIG_OCTEON_NAND_STAGE2
+/* For u-boot nand boot we need to play some tricks to be able
+** to use this early in boot.  We put them in a special section that is merged
+** with the text segment.  (Using the text segment directly results in an assembler warning.)
+*/
+#define USE_DATA_IN_TEXT
+#endif
+
+#ifdef USE_DATA_IN_TEXT
+static uint8_t cvmx_nand_buffer[4096] __attribute__((aligned(8)))  __attribute__ ((section (".data_in_text")));
+static cvmx_nand_state_t cvmx_nand_state[8] __attribute__ ((section (".data_in_text")));
+static cvmx_nand_initialize_flags_t cvmx_nand_flags __attribute__ ((section (".data_in_text")));
+static int debug_indent __attribute__ ((section (".data_in_text")));
+#else
+static CVMX_SHARED cvmx_nand_state_t cvmx_nand_state[8];
+static CVMX_SHARED cvmx_nand_initialize_flags_t cvmx_nand_flags;
+static CVMX_SHARED uint8_t *cvmx_nand_buffer = NULL;
+static int debug_indent = 0;
+#endif
+
+static CVMX_SHARED const char *cvmx_nand_opcode_labels[] =
+{
+    "NOP",                      /* 0 */
+    "Timing",                   /* 1 */
+    "Wait",                     /* 2 */
+    "Chip Enable / Disable",    /* 3 */
+    "CLE",                      /* 4 */
+    "ALE",                      /* 5 */
+    "6 - Unknown",              /* 6 */
+    "7 - Unknown",              /* 7 */
+    "Write",                    /* 8 */
+    "Read",                     /* 9 */
+    "Read EDO",                 /* 10 */
+    "Wait Status",              /* 11 */
+    "12 - Unknown",             /* 12 */
+    "13 - Unknown",             /* 13 */
+    "14 - Unknown",             /* 14 */
+    "Bus Aquire / Release"      /* 15 */
+};
+
+#define ULL unsigned long long
+/* This macro logs out whenever a function is called if debugging is on */
+#define CVMX_NAND_LOG_CALLED() \
+    if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG)) \
+        cvmx_dprintf("%*s%s: called\n", 2*debug_indent++, "", __FUNCTION__);
+
+/* This macro logs out each function parameter if debugging is on */
+#define CVMX_NAND_LOG_PARAM(format, param) \
+    if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG)) \
+        cvmx_dprintf("%*s%s: param %s = " format "\n", 2*debug_indent, "", __FUNCTION__, #param, param);
+
+/* This macro logs out when a function returns a value */
+#define CVMX_NAND_RETURN(v)                                              \
+    do {                                                                \
+        typeof(v) r = v;                                                \
+        if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))         \
+            cvmx_dprintf("%*s%s: returned %s(%d)\n", 2*--debug_indent, "", __FUNCTION__, #v, r); \
+        return r;                                                       \
+    } while (0);
+
+/* This macro logs out when a function doesn't return a value */
+#define CVMX_NAND_RETURN_NOTHING()                                      \
+    do {                                                                \
+        if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))         \
+            cvmx_dprintf("%*s%s: returned\n", 2*--debug_indent, "", __FUNCTION__); \
+        return;                                                         \
+    } while (0);
+
+
+
+
+
+
+/* Compute the CRC for the ONFI parameter page.  Adapted from sample code
+** in the specification.
+*/
+static uint16_t __onfi_parameter_crc_compute(uint8_t *data)
+{
+    const int order = 16;                     // Order of the CRC-16
+    unsigned long i, j, c, bit;
+    unsigned long crc = 0x4F4E;              // Initialize the shift register with 0x4F4E
+    unsigned long crcmask = ((((unsigned long)1<<(order-1))-1)<<1)|1;
+    unsigned long crchighbit = (unsigned long)1<<(order-1);
+
+    for (i = 0; i < 254; i++)
+    {
+        c = (unsigned long)data[i];
+        for (j = 0x80; j; j >>= 1) {
+              bit = crc & crchighbit;
+              crc <<= 1;
+              if (c & j)
+                  bit ^= crchighbit;
+              if (bit)
+                   crc ^= 0x8005;
+        }
+        crc &= crcmask;
+    }
+    return(crc);
+}
+
+
+/**
+ * Validate the ONFI parameter page and return a pointer to
+ * the config values.
+ *
+ * @param param_page Pointer to the raw NAND data returned after a parameter page read. It will
+ *                   contain at least 4 copies of the parameter structure.
+ *
+ * @return Pointer to a validated paramter page, or NULL if one couldn't be found.
+ */
+static cvmx_nand_onfi_param_page_t *__cvmx_nand_onfi_process(cvmx_nand_onfi_param_page_t param_page[4])
+{
+    int index;
+
+    for (index=0; index<4; index++)
+    {
+        uint16_t crc = __onfi_parameter_crc_compute((void *)&param_page[index]);
+        if (crc == cvmx_le16_to_cpu(param_page[index].crc))
+            break;
+        if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+            cvmx_dprintf("%s: Paramter page %d is corrupt. (Expected CRC: 0x%04x, computed: 0x%04x)\n",
+                          __FUNCTION__, index, cvmx_le16_to_cpu(param_page[index].crc), crc);
+    }
+
+    if (index == 4)
+    {
+        if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+            cvmx_dprintf("%s: All parameter pages fail CRC check.  Checking to see if any look sane.\n", __FUNCTION__);
+
+        if (!memcmp(param_page, param_page + 1, 256))
+        {
+            /* First and second copies match, now check some values */
+            if (param_page[0].pages_per_block != 0 && param_page[0].pages_per_block != 0xFFFFFFFF
+                && param_page[0].page_data_bytes != 0 && param_page[0].page_data_bytes != 0xFFFFFFFF
+                && param_page[0].page_spare_bytes != 0 && param_page[0].page_spare_bytes != 0xFFFF
+                && param_page[0].blocks_per_lun != 0 && param_page[0].blocks_per_lun != 0xFFFFFFFF
+                && param_page[0].timing_mode != 0 && param_page[0].timing_mode != 0xFFFF)
+            {
+                /* Looks like we have enough values to use */
+                if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                    cvmx_dprintf("%s: Page 0 looks sane, using even though CRC fails.\n", __FUNCTION__);
+                index = 0;
+            }
+        }
+    }
+
+    if (index == 4)
+    {
+        cvmx_dprintf("%s: No valid ONFI parameter pages found.\n", __FUNCTION__);
+        return NULL;
+    }
+
+    if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+    {
+        cvmx_dprintf("%*sONFI Information\n", 2*debug_indent, "");
+        debug_indent++;
+        cvmx_dprintf("%*sonfi = %c%c%c%c\n", 2*debug_indent, "", param_page[index].onfi[0], param_page[index].onfi[1],
+            param_page[index].onfi[2], param_page[index].onfi[3]);
+        cvmx_dprintf("%*srevision_number = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].revision_number));
+        cvmx_dprintf("%*sfeatures = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].features));
+        cvmx_dprintf("%*soptional_commands = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].optional_commands));
+
+        cvmx_dprintf("%*smanufacturer = %12.12s\n", 2*debug_indent, "", param_page[index].manufacturer);
+        cvmx_dprintf("%*smodel = %20.20s\n", 2*debug_indent, "", param_page[index].model);
+        cvmx_dprintf("%*sjedec_id = 0x%x\n", 2*debug_indent, "", param_page[index].jedec_id);
+        cvmx_dprintf("%*sdate_code = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].date_code));
+
+        cvmx_dprintf("%*spage_data_bytes = %u\n", 2*debug_indent, "", (int)cvmx_le32_to_cpu(param_page[index].page_data_bytes));
+        cvmx_dprintf("%*spage_spare_bytes = %u\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].page_spare_bytes));
+        cvmx_dprintf("%*spartial_page_data_bytes = %u\n", 2*debug_indent, "", (int)cvmx_le32_to_cpu(param_page[index].partial_page_data_bytes));
+        cvmx_dprintf("%*spartial_page_spare_bytes = %u\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].partial_page_spare_bytes));
+        cvmx_dprintf("%*spages_per_block = %u\n", 2*debug_indent, "", (int)cvmx_le32_to_cpu(param_page[index].pages_per_block));
+        cvmx_dprintf("%*sblocks_per_lun = %u\n", 2*debug_indent, "", (int)cvmx_le32_to_cpu(param_page[index].blocks_per_lun));
+        cvmx_dprintf("%*snumber_lun = %u\n", 2*debug_indent, "", param_page[index].number_lun);
+        cvmx_dprintf("%*saddress_cycles = 0x%x\n", 2*debug_indent, "", param_page[index].address_cycles);
+        cvmx_dprintf("%*sbits_per_cell = %u\n", 2*debug_indent, "", param_page[index].bits_per_cell);
+        cvmx_dprintf("%*sbad_block_per_lun = %u\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].bad_block_per_lun));
+        cvmx_dprintf("%*sblock_endurance = %u\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].block_endurance));
+        cvmx_dprintf("%*sgood_blocks = %u\n", 2*debug_indent, "", param_page[index].good_blocks);
+        cvmx_dprintf("%*sgood_block_endurance = %u\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].good_block_endurance));
+        cvmx_dprintf("%*sprograms_per_page = %u\n", 2*debug_indent, "", param_page[index].programs_per_page);
+        cvmx_dprintf("%*spartial_program_attrib = 0x%x\n", 2*debug_indent, "", param_page[index].partial_program_attrib);
+        cvmx_dprintf("%*sbits_ecc = %u\n", 2*debug_indent, "", param_page[index].bits_ecc);
+        cvmx_dprintf("%*sinterleaved_address_bits = 0x%x\n", 2*debug_indent, "", param_page[index].interleaved_address_bits);
+        cvmx_dprintf("%*sinterleaved_attrib = 0x%x\n", 2*debug_indent, "", param_page[index].interleaved_attrib);
+
+        cvmx_dprintf("%*spin_capacitance = %u\n", 2*debug_indent, "", param_page[index].pin_capacitance);
+        cvmx_dprintf("%*stiming_mode = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].timing_mode));
+        cvmx_dprintf("%*scache_timing_mode = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].cache_timing_mode));
+        cvmx_dprintf("%*st_prog = %d us\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].t_prog));
+        cvmx_dprintf("%*st_bers = %u us\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].t_bers));
+        cvmx_dprintf("%*st_r = %u us\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].t_r));
+        cvmx_dprintf("%*st_ccs = %u ns\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].t_ccs));
+        cvmx_dprintf("%*svendor_revision = 0x%x\n", 2*debug_indent, "", cvmx_le16_to_cpu(param_page[index].vendor_revision));
+        //uint8_t vendor_specific[88];    /**< Byte 166-253: Vendor specific */
+        cvmx_dprintf("%*scrc = 0x%x\n", 2*debug_indent, "", param_page[index].crc);
+        debug_indent--;
+    }
+    return param_page + index;
+}
+
+void __set_onfi_timing_mode(int *tim_par, int clocks_us, int mode)
+{
+    const onfi_speed_mode_desc_t *mp = &onfi_speed_modes[mode];  /* use shorter name to fill in timing array */
+    int margin;
+    int pulse_adjust;
+
+    if (mode > 5)
+    {
+        cvmx_dprintf("%s: invalid ONFI timing mode: %d\n", __FUNCTION__, mode);
+        return;
+    }
+
+    /* Adjust the read/write pulse duty cycle to make it more even.  The cycle time
+    ** requirement is longer than the sum of the high low times, so we exend both the high
+    ** and low times to meet the cycle time requirement.
+    */
+    pulse_adjust = ((mp->twc - mp->twh - mp->twp)/2 + 1) * clocks_us;
+
+    /* Add a small margin to all timings. */
+    margin = 2 * clocks_us;
+    /* Update timing parameters based on supported mode */
+    tim_par[1] = CVMX_NAND_ROUNDUP(mp->twp * clocks_us + margin + pulse_adjust, 1000); /* Twp, WE# pulse width */
+    tim_par[2] = CVMX_NAND_ROUNDUP(max(mp->twh, mp->twc - mp->twp) * clocks_us + margin + pulse_adjust, 1000); /* Tw, WE# pulse width high */
+    tim_par[3] = CVMX_NAND_ROUNDUP(mp->tclh * clocks_us + margin, 1000); /* Tclh, CLE hold time */
+    tim_par[4] = CVMX_NAND_ROUNDUP(mp->tals * clocks_us + margin, 1000); /* Tals, ALE setup time */
+    tim_par[5] = tim_par[3]; /* Talh, ALE hold time */
+    tim_par[6] = tim_par[1]; /* Trp, RE# pulse width*/
+    tim_par[7] = tim_par[2]; /* Treh, RE# high hold time */
+
+}
+
+/**
+ * Called to initialize the NAND controller for use. Note that
+ * you must be running out of L2 or memory and not NAND before
+ * calling this function.
+ *
+ * @param flags  Optional initialization flags
+ * @param active_chips
+ *               Each bit in this parameter represents a chip select that might
+ *               contain NAND flash. Any chip select present in this bitmask may
+ *               be connected to NAND. It is normally safe to pass 0xff here and
+ *               let the API probe all 8 chip selects.
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips)
+{
+    int chip;
+    int start_chip;
+    int stop_chip;
+    uint64_t clocks_us;
+    cvmx_ndf_misc_t ndf_misc;
+
+    cvmx_nand_flags = flags;
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("0x%x", flags);
+
+    memset(&cvmx_nand_state,  0,  sizeof(cvmx_nand_state));
+
+#ifndef USE_DATA_IN_TEXT
+    if (!cvmx_nand_buffer)
+        cvmx_nand_buffer = cvmx_bootmem_alloc(4096, 128);
+#endif
+    if (!cvmx_nand_buffer)
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Disable boot mode and reset the fifo */
+    ndf_misc.u64 = cvmx_read_csr(CVMX_NDF_MISC);
+    ndf_misc.s.rd_cmd = 0;
+    ndf_misc.s.bt_dma = 0;
+    ndf_misc.s.bt_dis = 1;
+    ndf_misc.s.ex_dis = 0;
+    ndf_misc.s.rst_ff = 1;
+    cvmx_write_csr(CVMX_NDF_MISC, ndf_misc.u64);
+    cvmx_read_csr(CVMX_NDF_MISC);
+
+    /* Bring the fifo out of reset */
+    cvmx_wait_usec(1);
+    ndf_misc.s.rst_ff = 0;
+    cvmx_write_csr(CVMX_NDF_MISC, ndf_misc.u64);
+    cvmx_read_csr(CVMX_NDF_MISC);
+    cvmx_wait_usec(1);
+
+    /* Clear the ECC counter */
+    //cvmx_write_csr(CVMX_NDF_ECC_CNT, cvmx_read_csr(CVMX_NDF_ECC_CNT));
+
+    /* Clear the interrupt state */
+    cvmx_write_csr(CVMX_NDF_INT, cvmx_read_csr(CVMX_NDF_INT));
+    cvmx_write_csr(CVMX_NDF_INT_EN, 0);
+    cvmx_write_csr(CVMX_MIO_NDF_DMA_INT, cvmx_read_csr(CVMX_MIO_NDF_DMA_INT));
+    cvmx_write_csr(CVMX_MIO_NDF_DMA_INT_EN, 0);
+
+    if (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE)
+        CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+
+    /* The simulator crashes if you access non existant devices. Assume
+        only chip select 1 is connected to NAND */
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+    {
+        start_chip = 1;
+        stop_chip = 2;
+    }
+    else
+    {
+        start_chip = 0;
+        stop_chip = 8;
+    }
+
+    /* Figure out how many clocks are in one microsecond, rounding up */
+    clocks_us = CVMX_NAND_ROUNDUP(cvmx_sysinfo_get()->cpu_clock_hz, 1000000);
+
+    /* Probe and see what NAND flash we can find */
+    for (chip=start_chip; chip<stop_chip; chip++)
+    {
+        cvmx_mio_boot_reg_cfgx_t mio_boot_reg_cfg;
+        cvmx_nand_onfi_param_page_t *onfi_param_page;
+
+        /* Skip chip selects that the caller didn't supply in the active chip bits */
+        if (((1<<chip) & active_chips) == 0)
+            continue;
+
+        mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(chip));
+        /* Enabled regions can't be connected to NAND flash */
+        if (mio_boot_reg_cfg.s.en)
+            continue;
+
+        /* Start out with some sane, but slow, defaults */
+        cvmx_nand_state[chip].page_size = 0;
+        cvmx_nand_state[chip].oob_size = 64;
+        cvmx_nand_state[chip].pages_per_block = 64;
+        cvmx_nand_state[chip].blocks = 100;
+        cvmx_nand_state[chip].tim_mult = 0; /* Don't use a multiplier. Values are in cycles */
+
+
+        /* Set timing mode to ONFI mode 0 for initial accesses */
+        __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, 0);
+
+        /* Put the index of which timing parameter to use.  The indexes are into the tim_par
+        ** which match the indexes of the 8 timing parameters that the hardware supports.
+        ** Index 0 is not software controlled, and is fixed by hardware. */
+        cvmx_nand_state[chip].clen[0] = 0; /* Command doesn't need to be held before WE */
+        cvmx_nand_state[chip].clen[1] = 1; /* Twp, WE# pulse width */
+        cvmx_nand_state[chip].clen[2] = 3; /* Tclh, CLE hold time */
+        cvmx_nand_state[chip].clen[3] = 1;
+
+        cvmx_nand_state[chip].alen[0] = 4; /* Tals, ALE setup time */
+        cvmx_nand_state[chip].alen[1] = 1; /* Twp, WE# pulse width */
+        cvmx_nand_state[chip].alen[2] = 2; /* Twh, WE# pulse width high */
+        cvmx_nand_state[chip].alen[3] = 5; /* Talh, ALE hold time */
+
+        cvmx_nand_state[chip].rdn[0] = 0;
+        cvmx_nand_state[chip].rdn[1] = 6; /* Trp, RE# pulse width*/
+        cvmx_nand_state[chip].rdn[2] = 7; /* Treh, RE# high hold time */
+        cvmx_nand_state[chip].rdn[3] = 0;
+
+        cvmx_nand_state[chip].wrn[0] = 1; /* Twp, WE# pulse width */
+        cvmx_nand_state[chip].wrn[1] = 2; /* Twh, WE# pulse width high */
+
+        /* Probe and see if we get an answer */
+        memset(cvmx_nand_buffer, 0xff, 8);
+        if (cvmx_nand_read_id(chip, 0x0, cvmx_ptr_to_phys(cvmx_nand_buffer), 8) < 4)
+        {
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
+            continue;
+        }
+        if (*(uint32_t*)cvmx_nand_buffer == 0xffffffff)
+        {
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Probe returned nothing for chip %d\n", __FUNCTION__, chip);
+            continue;
+        }
+
+        if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+            cvmx_dprintf("%s: NAND chip %d has ID 0x%08llx\n", __FUNCTION__, chip, (unsigned long long int)*(uint64_t*)cvmx_nand_buffer);
+
+        if (cvmx_nand_read_id(chip, 0x20, cvmx_ptr_to_phys(cvmx_nand_buffer), 4) < 4)
+        {
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Failed to probe chip %d\n", __FUNCTION__, chip);
+            continue;
+        }
+
+        if (!((cvmx_nand_buffer[0] == 'O') && (cvmx_nand_buffer[1] == 'N') &&
+            (cvmx_nand_buffer[2] == 'F') && (cvmx_nand_buffer[3] == 'I')))
+        {
+            /* FIXME: This is where non ONFI NAND devices need to be handled */
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Chip %d doesn't support ONFI, skipping\n", __FUNCTION__, chip);
+            continue;
+        }
+
+        cvmx_nand_read_param_page(chip, cvmx_ptr_to_phys(cvmx_nand_buffer), 1024);
+        onfi_param_page = __cvmx_nand_onfi_process((cvmx_nand_onfi_param_page_t *)cvmx_nand_buffer);
+        if (onfi_param_page)
+        {
+            /* ONFI NAND parts are described by a parameter page.  Here we extract the configuration values
+            ** from the parameter page that we need to access the chip. */
+            cvmx_nand_state[chip].page_size = cvmx_le32_to_cpu(onfi_param_page->page_data_bytes);
+            cvmx_nand_state[chip].oob_size = cvmx_le16_to_cpu(onfi_param_page->page_spare_bytes);
+            cvmx_nand_state[chip].pages_per_block = cvmx_le32_to_cpu(onfi_param_page->pages_per_block);
+            cvmx_nand_state[chip].blocks = cvmx_le32_to_cpu(onfi_param_page->blocks_per_lun) * onfi_param_page->number_lun;
+
+            if (cvmx_le16_to_cpu(onfi_param_page->timing_mode) <= 0x3f)
+            {
+                int mode_mask = cvmx_le16_to_cpu(onfi_param_page->timing_mode);
+                int mode = 0;
+                int i;
+                for (i = 0; i < 6;i++)
+                {
+                    if (mode_mask & (1 << i))
+                        mode = i;
+                }
+                cvmx_nand_state[chip].onfi_timing = mode;
+            }
+            else
+            {
+                cvmx_dprintf("%s: Invalid timing mode (%d) in ONFI parameter page, ignoring\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
+                cvmx_nand_state[chip].onfi_timing = 0;
+
+            }
+            if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+                cvmx_dprintf("%s: Using ONFI timing mode: %d\n", __FUNCTION__, cvmx_nand_state[chip].onfi_timing);
+            __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+        }
+        else
+        {
+            /* We did not find a valid parameter page in the FLASH part.  This means that the part
+            ** does not provide the parameter page that ONFI requires.  In this case, hard coded defaults
+            ** can be used, but they _must_ be updated to match the flash used.
+            */
+            /* Enable this code to force a configuration for NAND chip that doesn't have a proper parameter page.
+            ** ONFI requires a parameter page, so this should not be needed for compliant chips */
+
+            /* The default values below are for the Numonyx NAND08GW3B2CN6E part */
+#define NAND_SIZE_BITS  (8*1024*1024*1024ULL)
+            cvmx_nand_state[chip].page_size = 2048;  /* NAND page size in bytes */
+            cvmx_nand_state[chip].oob_size = 64;     /* NAND OOB (spare) size in bytes (per page) */
+            cvmx_nand_state[chip].pages_per_block = 64;
+            cvmx_nand_state[chip].blocks = (NAND_SIZE_BITS)/(8ULL*cvmx_nand_state[chip].page_size*cvmx_nand_state[chip].pages_per_block);
+            cvmx_nand_state[chip].onfi_timing = 2;
+            cvmx_dprintf("%s: WARNING: No valid ONFI parameter page found, using fixed defaults.\n", __FUNCTION__);
+            cvmx_dprintf("%s: Defaults: page size: %d, OOB size: %d, pages per block %d, part size: %d MBytes, timing mode: %d\n",
+                         __FUNCTION__, cvmx_nand_state[chip].page_size, cvmx_nand_state[chip].oob_size, cvmx_nand_state[chip].pages_per_block,
+                         (int)(NAND_SIZE_BITS/(8*1024*1024)), cvmx_nand_state[chip].onfi_timing);
+
+            __set_onfi_timing_mode(cvmx_nand_state[chip].tim_par, clocks_us, cvmx_nand_state[chip].onfi_timing);
+        }
+
+
+    }
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * Call to shutdown the NAND controller after all transactions
+ * are done. In most setups this will never be called.
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_shutdown(void)
+{
+    CVMX_NAND_LOG_CALLED();
+    memset(&cvmx_nand_state,  0,  sizeof(cvmx_nand_state));
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * Returns a bitmask representing the chip selects that are
+ * connected to NAND chips. This can be called after the
+ * initialize to determine the actual number of NAND chips
+ * found. Each bit in the response coresponds to a chip select.
+ *
+ * @return Zero if no NAND chips were found. Otherwise a bit is set for
+ *         each chip select (1<<chip).
+ */
+int cvmx_nand_get_active_chips(void)
+{
+    int chip;
+    int result = 0;
+    for (chip=0; chip<8; chip++)
+    {
+        if (cvmx_nand_state[chip].page_size)
+            result |= 1<<chip;
+    }
+    return result;
+}
+
+
+/**
+ * Override the timing parameters for a NAND chip
+ *
+ * @param chip     Chip select to override
+ * @param tim_mult
+ * @param tim_par
+ * @param clen
+ * @param alen
+ * @param rdn
+ * @param wrn
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[8], int clen[4], int alen[4], int rdn[4], int wrn[2])
+{
+    int i;
+    CVMX_NAND_LOG_CALLED();
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!cvmx_nand_state[chip].page_size)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    cvmx_nand_state[chip].tim_mult = tim_mult;
+    for (i=0;i<8;i++)
+        cvmx_nand_state[chip].tim_par[i] = tim_par[i];
+    for (i=0;i<4;i++)
+        cvmx_nand_state[chip].clen[i] = clen[i];
+    for (i=0;i<4;i++)
+        cvmx_nand_state[chip].alen[i] = alen[i];
+    for (i=0;i<4;i++)
+        cvmx_nand_state[chip].rdn[i] = rdn[i];
+    for (i=0;i<2;i++)
+        cvmx_nand_state[chip].wrn[i] = wrn[i];
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * @INTERNAL
+ * Get the number of free bytes in the NAND command queue
+ *
+ * @return Number of bytes in queue
+ */
+static inline int __cvmx_nand_get_free_cmd_bytes(void)
+{
+    cvmx_ndf_misc_t ndf_misc;
+    CVMX_NAND_LOG_CALLED();
+    ndf_misc.u64 = cvmx_read_csr(CVMX_NDF_MISC);
+    CVMX_NAND_RETURN((int)ndf_misc.s.fr_byt);
+}
+
+
+/**
+ * Submit a command to the NAND command queue. Generally this
+ * will not be used directly. Instead most programs will use the other
+ * higher level NAND functions.
+ *
+ * @param cmd    Command to submit
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd)
+{
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[0]);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[1]);
+    CVMX_NAND_LOG_PARAM("%s", cvmx_nand_opcode_labels[cmd.s.op_code]);
+    switch (cmd.s.op_code)
+    {
+        /* All these commands fit in one 64bit word */
+        case 0: /* NOP */
+        case 1: /* Timing */
+        case 2: /* WAIT */
+        case 3: /* Chip Enable/Disable */
+        case 4: /* CLE */
+        case 8: /* Write */
+        case 9: /* Read */
+        case 10: /* Read EDO */
+        case 15: /* Bus Aquire/Release */
+            if (__cvmx_nand_get_free_cmd_bytes() < 8)
+                CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+            cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
+            CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+
+        case 5: /* ALE commands take either one or two 64bit words */
+            if (cmd.ale.adr_byte_num < 5)
+            {
+                if (__cvmx_nand_get_free_cmd_bytes() < 8)
+                    CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+                cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
+                CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+            }
+            else
+            {
+                if (__cvmx_nand_get_free_cmd_bytes() < 16)
+                    CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+                cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
+                cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[0]);
+                CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+            }
+
+        case 11: /* Wait status commands take two 64bit words */
+            if (__cvmx_nand_get_free_cmd_bytes() < 16)
+                CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+            cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
+            cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[0]);
+            CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+
+        default:
+            CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Get the number of bits required to encode the column bits. This
+ * does not include padding to align on a byte boundary.
+ *
+ * @param chip   NAND chip to get data for
+ *
+ * @return Number of column bits
+ */
+static inline int __cvmx_nand_get_column_bits(int chip)
+{
+    return cvmx_pop(cvmx_nand_state[chip].page_size - 1);
+}
+
+
+/**
+ * @INTERNAL
+ * Get the number of bits required to encode the row bits. This
+ * does not include padding to align on a byte boundary.
+ *
+ * @param chip   NAND chip to get data for
+ *
+ * @return Number of row bits
+ */
+static inline int __cvmx_nand_get_row_bits(int chip)
+{
+    return cvmx_pop(cvmx_nand_state[chip].blocks-1) + cvmx_pop(cvmx_nand_state[chip].pages_per_block-1);
+}
+
+
+/**
+ * @INTERNAL
+ * Get the number of address cycles required for this NAND part.
+ * This include column bits, padding, page bits, and block bits.
+ *
+ * @param chip   NAND chip to get data for
+ *
+ * @return Number of address cycles on the bus
+ */
+static inline int __cvmx_nand_get_address_cycles(int chip)
+{
+    int address_bits = ((__cvmx_nand_get_column_bits(chip) + 7) >> 3) << 3;
+    address_bits += ((__cvmx_nand_get_row_bits(chip) + 7) >> 3) << 3;
+    return (address_bits + 7) >> 3;
+}
+
+
+/**
+ * @INTERNAL
+ * Build the set of command common to most transactions
+ * @param chip      NAND chip to program
+ * @param cmd_data  NAND comamnd for CLE cycle 1
+ * @param num_address_cycles
+ *                  Number of address cycles to put on the bus
+ * @param nand_address
+ *                  Data to be put on the bus. It is translated according to
+ *                  the rules in the file information section.
+ *
+ * @param cmd_data2 If non zero, adds a second CLE cycle used by a number of NAND
+ *                  transactions.
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+static inline cvmx_nand_status_t __cvmx_nand_build_pre_cmd(int chip, int cmd_data, int num_address_cycles, uint64_t nand_address, int cmd_data2)
+{
+    cvmx_nand_status_t result;
+    cvmx_nand_cmd_t cmd;
+
+    CVMX_NAND_LOG_CALLED();
+
+    /* Send timing parameters */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.set_tm_par.one = 1;
+    cmd.set_tm_par.tim_mult = cvmx_nand_state[chip].tim_mult;
+    /* tim_par[0] unused */
+    cmd.set_tm_par.tim_par1 = cvmx_nand_state[chip].tim_par[1];
+    cmd.set_tm_par.tim_par2 = cvmx_nand_state[chip].tim_par[2];
+    cmd.set_tm_par.tim_par3 = cvmx_nand_state[chip].tim_par[3];
+    cmd.set_tm_par.tim_par4 = cvmx_nand_state[chip].tim_par[4];
+    cmd.set_tm_par.tim_par5 = cvmx_nand_state[chip].tim_par[5];
+    cmd.set_tm_par.tim_par6 = cvmx_nand_state[chip].tim_par[6];
+    cmd.set_tm_par.tim_par7 = cvmx_nand_state[chip].tim_par[7];
+    result = cvmx_nand_submit(cmd);
+    if (result)
+        CVMX_NAND_RETURN(result);
+
+    /* Send bus select */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.bus_acq.fifteen = 15;
+    cmd.bus_acq.one = 1;
+    result = cvmx_nand_submit(cmd);
+    if (result)
+        CVMX_NAND_RETURN(result);
+
+    /* Send chip select */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.chip_en.chip = chip;
+    cmd.chip_en.one = 1;
+    cmd.chip_en.three = 3;
+    cmd.chip_en.width = (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_16BIT) ? 2 : 1;
+    result = cvmx_nand_submit(cmd);
+    if (result)
+        CVMX_NAND_RETURN(result);
+
+    /* Send wait, fixed time
+    ** This meets chip enable to command latch enable timing.
+    ** This is tCS - tCLS from the ONFI spec.
+    ** Use tWP as a proxy, as this is adequate for
+    ** all ONFI 1.0 timing modes. */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
+    cmd.wait.n = 1;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Send CLE */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.cle.cmd_data = cmd_data;
+    cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
+    cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
+    cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
+    cmd.cle.four = 4;
+    result = cvmx_nand_submit(cmd);
+    if (result)
+        CVMX_NAND_RETURN(result);
+
+    /* Send ALE */
+    if (num_address_cycles)
+    {
+        memset(&cmd,  0,  sizeof(cmd));
+        cmd.ale.adr_byte_num = num_address_cycles;
+        if (num_address_cycles < __cvmx_nand_get_address_cycles(chip))
+        {
+            cmd.ale.adr_bytes_l = nand_address;
+            cmd.ale.adr_bytes_h = nand_address >> 32;
+        }
+        else
+        {
+            int column_bits = __cvmx_nand_get_column_bits(chip);
+            int column_shift = ((column_bits + 7) >> 3) << 3;
+            int column = nand_address & (cvmx_nand_state[chip].page_size-1);
+            int row = nand_address >> column_bits;
+            cmd.ale.adr_bytes_l = column + (row << column_shift);
+            cmd.ale.adr_bytes_h = row >> (32 - column_shift);
+        }
+        cmd.ale.alen1 = cvmx_nand_state[chip].alen[0];
+        cmd.ale.alen2 = cvmx_nand_state[chip].alen[1];
+        cmd.ale.alen3 = cvmx_nand_state[chip].alen[2];
+        cmd.ale.alen4 = cvmx_nand_state[chip].alen[3];
+        cmd.ale.five = 5;
+        result = cvmx_nand_submit(cmd);
+        if (result)
+            CVMX_NAND_RETURN(result);
+    }
+
+    /* Send CLE 2 */
+    if (cmd_data2)
+    {
+        memset(&cmd,  0,  sizeof(cmd));
+        cmd.cle.cmd_data = cmd_data2;
+        cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
+        cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
+        cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
+        cmd.cle.four = 4;
+        result = cvmx_nand_submit(cmd);
+        if (result)
+            CVMX_NAND_RETURN(result);
+    }
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * @INTERNAL
+ * Build the set of command common to most transactions
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+static inline cvmx_nand_status_t __cvmx_nand_build_post_cmd(void)
+{
+    cvmx_nand_status_t result;
+    cvmx_nand_cmd_t cmd;
+
+    CVMX_NAND_LOG_CALLED();
+
+    /* Send chip deselect */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.chip_dis.three = 3;
+    result = cvmx_nand_submit(cmd);
+    if (result)
+        CVMX_NAND_RETURN(result);
+
+    /* Send bus release */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.bus_rel.fifteen = 15;
+    result = cvmx_nand_submit(cmd);
+    if (result)
+        CVMX_NAND_RETURN(result);
+
+    /* Ring the doorbell */
+    cvmx_write_csr(CVMX_NDF_DRBELL, 1);
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * @INTERNAL
+ * Setup the NAND DMA engine for a transfer
+ *
+ * @param chip     Chip select for NAND flash
+ * @param is_write Non zero if this is a write
+ * @param buffer_address
+ *                 Physical memory address to DMA to/from
+ * @param buffer_length
+ *                 Length of the DMA in bytes
+ */
+static inline void __cvmx_nand_setup_dma(int chip, int is_write, uint64_t buffer_address, int buffer_length)
+{
+    cvmx_mio_ndf_dma_cfg_t ndf_dma_cfg;
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("%d", is_write);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
+    CVMX_NAND_LOG_PARAM("%d", buffer_length);
+    ndf_dma_cfg.u64 = 0;
+    ndf_dma_cfg.s.en = 1;
+    ndf_dma_cfg.s.rw = is_write; /* One means DMA reads from memory and writes to flash */
+    ndf_dma_cfg.s.clr = 0;
+    ndf_dma_cfg.s.size = ((buffer_length + 7) >> 3) - 1;
+    ndf_dma_cfg.s.adr = buffer_address;
+    CVMX_SYNCWS;
+    cvmx_write_csr(CVMX_MIO_NDF_DMA_CFG, ndf_dma_cfg.u64);
+    CVMX_NAND_RETURN_NOTHING();
+}
+
+
+/**
+ * Dump a buffer out in hex for debug
+ *
+ * @param buffer_address
+ *               Starting physical address
+ * @param buffer_length
+ *               Number of bytes to display
+ */
+static void __cvmx_nand_hex_dump(uint64_t buffer_address, int buffer_length)
+{
+    uint8_t *buffer = cvmx_phys_to_ptr(buffer_address);
+    int offset = 0;
+    while (offset < buffer_length)
+    {
+        int i;
+        cvmx_dprintf("%*s%04x:",  2*debug_indent, "", offset);
+        for (i=0; i<32; i++)
+        {
+            if ((i&3) == 0)
+                cvmx_dprintf(" ");
+            if (offset+i < buffer_length)
+                cvmx_dprintf("%02x", 0xff & buffer[offset+i]);
+            else
+                cvmx_dprintf("  ");
+        }
+        cvmx_dprintf("\n");
+        offset += 32;
+    }
+}
+
+/**
+ * @INTERNAL
+ * Perform a low level NAND read command
+ *
+ * @param chip   Chip to read from
+ * @param nand_command1
+ *               First command cycle value
+ * @param address_cycles
+ *               Number of address cycles after comand 1
+ * @param nand_address
+ *               NAND address to use for address cycles
+ * @param nand_command2
+ *               NAND comamnd cycle 2 if not zero
+ * @param buffer_address
+ *               Physical address to DMA into
+ * @param buffer_length
+ *               Length of the transfer in bytes
+ *
+ * @return Number of bytes transfered or a negative error code
+ */
+static inline int __cvmx_nand_low_level_read(int chip, int nand_command1, int address_cycles, uint64_t nand_address, int nand_command2, uint64_t buffer_address, int buffer_length)
+{
+    cvmx_nand_cmd_t cmd;
+    cvmx_mio_ndf_dma_cfg_t ndf_dma_cfg;
+    int bytes;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("0x%x", nand_command1);
+    CVMX_NAND_LOG_PARAM("%d", address_cycles);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
+    CVMX_NAND_LOG_PARAM("0x%x", nand_command2);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
+    CVMX_NAND_LOG_PARAM("%d", buffer_length);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_address)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_address & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_length)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    /* Build the command and address cycles */
+    if (__cvmx_nand_build_pre_cmd(chip, nand_command1, address_cycles, nand_address, nand_command2))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Send WAIT.  This waits for some time, then
+    ** waits for busy to be de-asserted. */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
+    cmd.wait.r_b=1;
+    cmd.wait.n = 1;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Wait for tRR after busy de-asserts.
+    ** Use 2* tALS as proxy.  This is overkill in
+    ** the slow modes, but not bad in the faster ones. */
+    cmd.wait.r_b=0;
+    cmd.wait.n=4;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Send READ */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.rd.data_bytes = buffer_length;
+    if (cvmx_nand_state[chip].onfi_timing >= 4)
+        cmd.rd.nine = 10;  /* READ_EDO command is required for ONFI timing modes 4 and 5 */
+    else
+        cmd.rd.nine = 9;
+    cmd.rd.rdn1 = cvmx_nand_state[chip].rdn[0];
+    cmd.rd.rdn2 = cvmx_nand_state[chip].rdn[1];
+    cmd.rd.rdn3 = cvmx_nand_state[chip].rdn[2];
+    cmd.rd.rdn4 = cvmx_nand_state[chip].rdn[3];
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    __cvmx_nand_setup_dma(chip, 0, buffer_address, buffer_length);
+
+    if (__cvmx_nand_build_post_cmd())
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Wait for the DMA to complete */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_NDF_DMA_CFG, cvmx_mio_ndf_dma_cfg_t, en, ==, 0, NAND_TIMEOUT_USECS))
+        CVMX_NAND_RETURN(CVMX_NAND_TIMEOUT);
+
+    /* Return the number of bytes transfered */
+    ndf_dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_NDF_DMA_CFG);
+    bytes = ndf_dma_cfg.s.adr - buffer_address;
+
+    if (cvmx_unlikely(cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_DEBUG))
+        __cvmx_nand_hex_dump(buffer_address, bytes);
+
+    CVMX_NAND_RETURN(bytes);
+}
+
+
+/**
+ * Read a page from NAND. If the buffer has room, the out of band
+ * data will be included.
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               Location in NAND to read. See description in file comment
+ * @param buffer_address
+ *               Physical address to store the result at
+ * @param buffer_length
+ *               Number of bytes to read
+ *
+ * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
+{
+    int bytes;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
+    CVMX_NAND_LOG_PARAM("%d", buffer_length);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!cvmx_nand_state[chip].page_size)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_address)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_address & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_length)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ, __cvmx_nand_get_address_cycles(chip), nand_address, NAND_COMMAND_READ_FIN, buffer_address, buffer_length);
+    CVMX_NAND_RETURN(bytes);
+}
+
+
+/**
+ * Write a page to NAND. The buffer must contain the entire page
+ * including the out of band data.
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               Location in NAND to write. See description in file comment
+ * @param buffer_address
+ *               Physical address to read the data from
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address)
+{
+    cvmx_nand_cmd_t cmd;
+    int buffer_length;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!cvmx_nand_state[chip].page_size)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_address)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_address & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    buffer_length = cvmx_nand_state[chip].page_size + cvmx_nand_state[chip].oob_size;
+
+    /* Build the command and address cycles */
+    if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_PROGRAM, __cvmx_nand_get_address_cycles(chip), nand_address, 0))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Send WRITE */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wr.data_bytes = buffer_length;
+    cmd.wr.eight = 8;
+    cmd.wr.wrn1 = cvmx_nand_state[chip].wrn[0];
+    cmd.wr.wrn2 = cvmx_nand_state[chip].wrn[1];
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Send WRITE command */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.cle.cmd_data = NAND_COMMAND_PROGRAM_FIN;
+    cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
+    cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
+    cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
+    cmd.cle.four = 4;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    __cvmx_nand_setup_dma(chip, 1, buffer_address, buffer_length);
+
+    /* WAIT for R_B to signal program is complete  */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
+    cmd.wait.r_b=1;
+    cmd.wait.n = 1;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    if (__cvmx_nand_build_post_cmd())
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Wait for the DMA to complete */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_NDF_DMA_CFG, cvmx_mio_ndf_dma_cfg_t, en, ==, 0, NAND_TIMEOUT_USECS))
+        CVMX_NAND_RETURN(CVMX_NAND_TIMEOUT);
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * Erase a NAND block. A single block contains multiple pages.
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               Location in NAND to erase. See description in file comment
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address)
+{
+    cvmx_nand_cmd_t cmd;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!cvmx_nand_state[chip].page_size)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    /* Build the command and address cycles */
+    if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_ERASE,
+                                  (__cvmx_nand_get_row_bits(chip)+7) >> 3,
+                                  nand_address >> __cvmx_nand_get_column_bits(chip),
+                                  NAND_COMMAND_ERASE_FIN))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* WAIT for R_B to signal erase is complete  */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
+    cmd.wait.r_b=1;
+    cmd.wait.n = 1;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    if (__cvmx_nand_build_post_cmd())
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* Wait for the command queue to be idle, which means the wait is done */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_NDF_ST_REG, cvmx_ndf_st_reg_t, exe_idle, ==, 1, NAND_TIMEOUT_USECS))
+        CVMX_NAND_RETURN(CVMX_NAND_TIMEOUT);
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+/**
+ * Read the NAND ID information
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               NAND address to read ID from. Usually this is either 0x0 or 0x20.
+ * @param buffer_address
+ *               Physical address to store data in
+ * @param buffer_length
+ *               Length of the buffer. Usually this is 4 bytes
+ *
+ * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length)
+{
+    int bytes;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)nand_address);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
+    CVMX_NAND_LOG_PARAM("%d", buffer_length);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_address)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_address & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_length)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_ID, 1, nand_address, 0, buffer_address, buffer_length);
+    CVMX_NAND_RETURN(bytes);
+}
+
+
+/**
+ * Read the NAND parameter page
+ *
+ * @param chip   Chip select for NAND flash
+ * @param buffer_address
+ *               Physical address to store data in
+ * @param buffer_length
+ *               Length of the buffer. Usually this is 4 bytes
+ *
+ * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length)
+{
+    int bytes;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+    CVMX_NAND_LOG_PARAM("0x%llx", (ULL)buffer_address);
+    CVMX_NAND_LOG_PARAM("%d", buffer_length);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_address)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (buffer_address & 7)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!buffer_length)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    bytes = __cvmx_nand_low_level_read(chip, NAND_COMMAND_READ_PARAM_PAGE, 1, 0x0, 0, buffer_address, buffer_length);
+    CVMX_NAND_RETURN(bytes);
+}
+
+
+/**
+ * Get the status of the NAND flash
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return NAND status or a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_get_status(int chip)
+{
+    int status;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    *(uint8_t*)cvmx_nand_buffer = 0xff;
+    status = __cvmx_nand_low_level_read(chip, NAND_COMMAND_STATUS, 0, 0, 0, cvmx_ptr_to_phys(cvmx_nand_buffer), (cvmx_nand_flags & CVMX_NAND_INITIALIZE_FLAGS_16BIT) ? 2 : 1);
+    if (status > 0)
+        status = *(uint8_t*)cvmx_nand_buffer;
+
+    CVMX_NAND_RETURN(status);
+}
+
+
+/**
+ * Get the page size, excluding out of band data. This  function
+ * will return zero for chip selects not connected to NAND.
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Page size in bytes or a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_get_page_size(int chip)
+{
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    CVMX_NAND_RETURN(cvmx_nand_state[chip].page_size);
+}
+
+
+/**
+ * Get the OOB size.
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return OOB in bytes or a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_get_oob_size(int chip)
+{
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    CVMX_NAND_RETURN(cvmx_nand_state[chip].oob_size);
+}
+
+
+/**
+ * Get the number of pages per NAND block
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Number of pages in each block or a negative cvmx_nand_status_t error
+ *         code on failure
+ */
+int cvmx_nand_get_pages_per_block(int chip)
+{
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    CVMX_NAND_RETURN(cvmx_nand_state[chip].pages_per_block);
+}
+
+
+/**
+ * Get the number of blocks in the NAND flash
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Number of blocks or a negative cvmx_nand_status_t error code on failure
+ */
+int cvmx_nand_get_blocks(int chip)
+{
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    CVMX_NAND_RETURN(cvmx_nand_state[chip].blocks);
+}
+
+
+/**
+ * Reset the NAND flash
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+cvmx_nand_status_t cvmx_nand_reset(int chip)
+{
+    cvmx_nand_cmd_t cmd;
+
+    CVMX_NAND_LOG_CALLED();
+    CVMX_NAND_LOG_PARAM("%d", chip);
+
+    if ((chip < 0) || (chip > 7))
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+    if (!cvmx_nand_state[chip].page_size)
+        CVMX_NAND_RETURN(CVMX_NAND_INVALID_PARAM);
+
+    if (__cvmx_nand_build_pre_cmd(chip, NAND_COMMAND_RESET, 0, 0, 0))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    /* WAIT for R_B to signal reset is complete  */
+    memset(&cmd,  0,  sizeof(cmd));
+    cmd.wait.two = 2;
+    cmd.wait.r_b=1;
+    cmd.wait.n = 1;
+    if (cvmx_nand_submit(cmd))
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    if (__cvmx_nand_build_post_cmd())
+        CVMX_NAND_RETURN(CVMX_NAND_NO_MEMORY);
+
+    CVMX_NAND_RETURN(CVMX_NAND_SUCCESS);
+}
+
+
+
+
+/**
+ * This function computes the Octeon specific ECC data used by the NAND boot
+ * feature.
+ * 
+ * @param block  pointer to 256 bytes of data
+ * @param eccp   pointer to where 8 bytes of ECC data will be stored
+ */
+void cvmx_nand_compute_boot_ecc(unsigned char *block, unsigned char *eccp)
+{
+	unsigned char pd0, pd1, pd2;
+	int i, j;
+
+	pd0 = pd1 = pd2 = 0;
+
+	for (i = 0; i < 256; i++)	/* PD0<0> */
+		pd0 ^= (block[i] ^ (block[i] >> 2) ^ (block[i] >> 4) ^ (block[i] >> 6)) & 1;
+	for (i = 0; i < 256; i++)	/* PD0<1> */
+		pd0 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 4) ^ (block[i] >> 5)) & 1) << 1;
+	for (i = 0; i < 256; i++)	/* PD0<2> */
+		pd0 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 2) ^ (block[i] >> 3)) & 1) << 2;
+	for (i = 0; i < 128; i++)	/* PD0<3> */
+		pd0 ^= ((block[2*i] ^ (block[2*i] >> 1) ^ (block[2*i] >> 2) ^
+			(block[2*i] >> 3) ^ (block[2*i] >> 4) ^ (block[2*i] >> 5) ^
+			(block[2*i] >> 6) ^ (block[2*i] >> 7)) & 1) << 3;
+	for (i = 0; i < 64; i++)	/* PD0<4> */
+		for (j = 0; j < 2; j++)
+			pd0 ^= ((block[4*i+j] ^ (block[4*i+j] >> 1) ^ (block[4*i+j] >> 2) ^
+				(block[4*i+j] >> 3) ^ (block[4*i+j] >> 4) ^ (block[4*i+j] >> 5) ^
+				(block[4*i+j] >> 6) ^ (block[4*i+j] >> 7)) & 1) << 4;
+	for (i = 0; i < 32; i++)	/* PD0<5> */
+		for (j = 0; j < 4; j++)
+			pd0 ^= ((block[8*i+j] ^ (block[8*i+j] >> 1) ^ (block[8*i+j] >> 2) ^
+				(block[8*i+j] >> 3) ^ (block[8*i+j] >> 4) ^ (block[8*i+j] >> 5) ^
+				(block[8*i+j] >> 6) ^ (block[8*i+j] >> 7)) & 1) << 5;
+	for (i = 0; i < 16; i++)	/* PD0<6> */
+		for (j = 0; j < 8; j++)
+			pd0 ^= ((block[16*i+j] ^ (block[16*i+j] >> 1) ^ (block[16*i+j] >> 2) ^
+				(block[16*i+j] >> 3) ^ (block[16*i+j] >> 4) ^ (block[16*i+j] >> 5) ^
+				(block[16*i+j] >> 6) ^ (block[16*i+j] >> 7)) & 1) << 6;
+	for (i = 0; i < 8; i++)		/* PD0<7> */
+		for (j = 0; j < 16; j++)
+			pd0 ^= ((block[32*i+j] ^ (block[32*i+j] >> 1) ^ (block[32*i+j] >> 2) ^
+				(block[32*i+j] >> 3) ^ (block[32*i+j] >> 4) ^ (block[32*i+j] >> 5) ^
+				(block[32*i+j] >> 6) ^ (block[32*i+j] >> 7)) & 1) << 7;
+	for (i = 0; i < 4; i++)		/* PD1<0> */
+		for (j = 0; j < 32; j++)
+			pd1 ^= ((block[64*i+j] ^ (block[64*i+j] >> 1) ^ (block[64*i+j] >> 2) ^
+				(block[64*i+j] >> 3) ^ (block[64*i+j] >> 4) ^ (block[64*i+j] >> 5) ^
+				(block[64*i+j] >> 6) ^ (block[64*i+j] >> 7)) & 1) << 0;
+	for (i = 0; i < 2; i++)		/* PD1<1> */
+		for (j = 0; j < 64; j++)
+			pd1 ^= ((block[128*i+j] ^ (block[128*i+j] >> 1) ^ (block[128*i+j] >> 2) ^
+				(block[128*i+j] >> 3) ^ (block[128*i+j] >> 4) ^ (block[128*i+j] >> 5) ^
+				(block[128*i+j] >> 6) ^ (block[128*i+j] >> 7)) & 1) << 1;
+	for (i = 0; i < 128; i++)	/* PD1<2> */
+		pd1 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 2) ^
+			(block[i] >> 3) ^ (block[i] >> 4) ^ (block[i] >> 5) ^
+			(block[i] >> 6) ^ (block[i] >> 7)) & 1) << 2;
+	/* PD1<3> */
+	/* PD1<4> */
+	for (i = 0; i < 256; i++)	/* PD1<5> */
+		pd1 ^= (((block[i] >> 1) ^ (block[i] >> 3) ^ (block[i] >> 5) ^ (block[i] >> 7)) & 1) << 5;
+	for (i = 0; i < 256; i++)	/* PD1<6> */
+		pd1 ^= (((block[i] >> 2) ^ (block[i] >> 3) ^ (block[i] >> 6) ^ (block[i] >> 7)) & 1) << 6;
+	for (i = 0; i < 256; i++)	/* PD1<7> */
+		pd1 ^= (((block[i] >> 4) ^ (block[i] >> 5) ^ (block[i] >> 6) ^ (block[i] >> 7)) & 1) << 7;
+	for (i = 0; i < 128; i++)	/* PD2<0> */
+		pd2 ^= ((block[2*i+1] ^ (block[2*i+1] >> 1) ^ (block[2*i+1] >> 2) ^
+			(block[2*i+1] >> 3) ^ (block[2*i+1] >> 4) ^ (block[2*i+1] >> 5) ^
+			(block[2*i+1] >> 6) ^ (block[2*i+1] >> 7)) & 1) << 0;
+	for (i = 0; i < 64; i++)	/* PD2<1> */
+		for (j = 2; j < 4; j++)
+			pd2 ^= ((block[4*i+j] ^ (block[4*i+j] >> 1) ^ (block[4*i+j] >> 2) ^
+				(block[4*i+j] >> 3) ^ (block[4*i+j] >> 4) ^ (block[4*i+j] >> 5) ^
+				(block[4*i+j] >> 6) ^ (block[4*i+j] >> 7)) & 1) << 1;
+	for (i = 0; i < 32; i++)	/* PD2<2> */
+		for (j = 4; j < 8; j++)
+			pd2 ^= ((block[8*i+j] ^ (block[8*i+j] >> 1) ^ (block[8*i+j] >> 2) ^
+				(block[8*i+j] >> 3) ^ (block[8*i+j] >> 4) ^ (block[8*i+j] >> 5) ^
+				(block[8*i+j] >> 6) ^ (block[8*i+j] >> 7)) & 1) << 2;
+	for (i = 0; i < 16; i++)	/* PD2<3> */
+		for (j = 8; j < 16; j++)
+			pd2 ^= ((block[16*i+j] ^ (block[16*i+j] >> 1) ^ (block[16*i+j] >> 2) ^
+				(block[16*i+j] >> 3) ^ (block[16*i+j] >> 4) ^ (block[16*i+j] >> 5) ^
+				(block[16*i+j] >> 6) ^ (block[16*i+j] >> 7)) & 1) << 3;
+	for (i = 0; i < 8; i++)		/* PD2<4> */
+		for (j = 16; j < 32; j++)
+			pd2 ^= ((block[32*i+j] ^ (block[32*i+j] >> 1) ^ (block[32*i+j] >> 2) ^
+				(block[32*i+j] >> 3) ^ (block[32*i+j] >> 4) ^ (block[32*i+j] >> 5) ^
+				(block[32*i+j] >> 6) ^ (block[32*i+j] >> 7)) & 1) << 4;
+	for (i = 0; i < 4; i++)		/* PD2<5> */
+		for (j = 32; j < 64; j++)
+			pd2 ^= ((block[64*i+j] ^ (block[64*i+j] >> 1) ^ (block[64*i+j] >> 2) ^
+				(block[64*i+j] >> 3) ^ (block[64*i+j] >> 4) ^ (block[64*i+j] >> 5) ^
+				(block[64*i+j] >> 6) ^ (block[64*i+j] >> 7)) & 1) << 5;
+	for (i = 0; i < 2; i++)		/* PD2<6> */
+		for (j = 64; j < 128; j++)
+			pd2 ^= ((block[128*i+j] ^ (block[128*i+j] >> 1) ^ (block[128*i+j] >> 2) ^
+				(block[128*i+j] >> 3) ^ (block[128*i+j] >> 4) ^ (block[128*i+j] >> 5) ^
+				(block[128*i+j] >> 6) ^ (block[128*i+j] >> 7)) & 1) << 6;
+	for (i = 128; i < 256; i++)	/* PD2<7> */
+		pd2 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 2) ^
+			(block[i] >> 3) ^ (block[i] >> 4) ^ (block[i] >> 5) ^
+			(block[i] >> 6) ^ (block[i] >> 7)) & 1) << 7;
+
+	eccp[0] = pd0;
+	eccp[1] = pd1;
+	eccp[2] = pd2;
+}
+
+/**
+ * Check an Octeon ECC block, fixing errors if possible
+ *
+ * @param block  Pointer to block to check
+ *
+ * @return Zero if block has no errors, one if errors were corrected, two
+ *         if the errors could not be corrected.
+ */
+int cvmx_nand_correct_boot_ecc(uint8_t *block)
+{
+    unsigned char pd0, pd1, pd2;
+    int i, j;
+    unsigned char xorpd0, xorpd1, xorpd2;
+    int xor_num;
+    unsigned int check;
+
+    asm volatile ("pref 0,0(%0);pref 0,128(%0);pref 0,256(%0)\n" :: "r" (block));
+
+    pd0 = pd1 = pd2 = 0;
+
+    for (i = 0; i < 256; i++)   /* PD0<0> */
+        pd0 ^= (block[i] ^ (block[i] >> 2) ^ (block[i] >> 4) ^ (block[i] >> 6)) & 1;
+    for (i = 0; i < 256; i++)   /* PD0<1> */
+        pd0 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 4) ^ (block[i] >> 5)) & 1) << 1;
+    for (i = 0; i < 256; i++)   /* PD0<2> */
+        pd0 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 2) ^ (block[i] >> 3)) & 1) << 2;
+    for (i = 0; i < 128; i++)   /* PD0<3> */
+        pd0 ^= ((block[2*i] ^ (block[2*i] >> 1) ^ (block[2*i] >> 2) ^
+                 (block[2*i] >> 3) ^ (block[2*i] >> 4) ^ (block[2*i] >> 5) ^
+                 (block[2*i] >> 6) ^ (block[2*i] >> 7)) & 1) << 3;
+    for (i = 0; i < 64; i++)    /* PD0<4> */
+        for (j = 0; j < 2; j++)
+            pd0 ^= ((block[4*i+j] ^ (block[4*i+j] >> 1) ^ (block[4*i+j] >> 2) ^
+                     (block[4*i+j] >> 3) ^ (block[4*i+j] >> 4) ^ (block[4*i+j] >> 5) ^
+                     (block[4*i+j] >> 6) ^ (block[4*i+j] >> 7)) & 1) << 4;
+    for (i = 0; i < 32; i++)    /* PD0<5> */
+        for (j = 0; j < 4; j++)
+            pd0 ^= ((block[8*i+j] ^ (block[8*i+j] >> 1) ^ (block[8*i+j] >> 2) ^
+                     (block[8*i+j] >> 3) ^ (block[8*i+j] >> 4) ^ (block[8*i+j] >> 5) ^
+                     (block[8*i+j] >> 6) ^ (block[8*i+j] >> 7)) & 1) << 5;
+    for (i = 0; i < 16; i++)    /* PD0<6> */
+        for (j = 0; j < 8; j++)
+            pd0 ^= ((block[16*i+j] ^ (block[16*i+j] >> 1) ^ (block[16*i+j] >> 2) ^
+                     (block[16*i+j] >> 3) ^ (block[16*i+j] >> 4) ^ (block[16*i+j] >> 5) ^
+                     (block[16*i+j] >> 6) ^ (block[16*i+j] >> 7)) & 1) << 6;
+    for (i = 0; i < 8; i++)     /* PD0<7> */
+        for (j = 0; j < 16; j++)
+            pd0 ^= ((block[32*i+j] ^ (block[32*i+j] >> 1) ^ (block[32*i+j] >> 2) ^
+                     (block[32*i+j] >> 3) ^ (block[32*i+j] >> 4) ^ (block[32*i+j] >> 5) ^
+                     (block[32*i+j] >> 6) ^ (block[32*i+j] >> 7)) & 1) << 7;
+    for (i = 0; i < 4; i++)     /* PD1<0> */
+        for (j = 0; j < 32; j++)
+            pd1 ^= ((block[64*i+j] ^ (block[64*i+j] >> 1) ^ (block[64*i+j] >> 2) ^
+                     (block[64*i+j] >> 3) ^ (block[64*i+j] >> 4) ^ (block[64*i+j] >> 5) ^
+                     (block[64*i+j] >> 6) ^ (block[64*i+j] >> 7)) & 1) << 0;
+    for (i = 0; i < 2; i++)     /* PD1<1> */
+        for (j = 0; j < 64; j++)
+            pd1 ^= ((block[128*i+j] ^ (block[128*i+j] >> 1) ^ (block[128*i+j] >> 2) ^
+                     (block[128*i+j] >> 3) ^ (block[128*i+j] >> 4) ^ (block[128*i+j] >> 5) ^
+                     (block[128*i+j] >> 6) ^ (block[128*i+j] >> 7)) & 1) << 1;
+    for (i = 0; i < 128; i++)   /* PD1<2> */
+        pd1 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 2) ^
+                 (block[i] >> 3) ^ (block[i] >> 4) ^ (block[i] >> 5) ^
+                 (block[i] >> 6) ^ (block[i] >> 7)) & 1) << 2;
+    /* PD1<3> */
+    /* PD1<4> */
+    for (i = 0; i < 256; i++)   /* PD1<5> */
+        pd1 ^= (((block[i] >> 1) ^ (block[i] >> 3) ^ (block[i] >> 5) ^ (block[i] >> 7)) & 1) << 5;
+    for (i = 0; i < 256; i++)   /* PD1<6> */
+        pd1 ^= (((block[i] >> 2) ^ (block[i] >> 3) ^ (block[i] >> 6) ^ (block[i] >> 7)) & 1) << 6;
+    for (i = 0; i < 256; i++)   /* PD1<7> */
+        pd1 ^= (((block[i] >> 4) ^ (block[i] >> 5) ^ (block[i] >> 6) ^ (block[i] >> 7)) & 1) << 7;
+    for (i = 0; i < 128; i++)   /* PD2<0> */
+        pd2 ^= ((block[2*i+1] ^ (block[2*i+1] >> 1) ^ (block[2*i+1] >> 2) ^
+                 (block[2*i+1] >> 3) ^ (block[2*i+1] >> 4) ^ (block[2*i+1] >> 5) ^
+                 (block[2*i+1] >> 6) ^ (block[2*i+1] >> 7)) & 1) << 0;
+    for (i = 0; i < 64; i++)    /* PD2<1> */
+        for (j = 2; j < 4; j++)
+            pd2 ^= ((block[4*i+j] ^ (block[4*i+j] >> 1) ^ (block[4*i+j] >> 2) ^
+                     (block[4*i+j] >> 3) ^ (block[4*i+j] >> 4) ^ (block[4*i+j] >> 5) ^
+                     (block[4*i+j] >> 6) ^ (block[4*i+j] >> 7)) & 1) << 1;
+    for (i = 0; i < 32; i++)    /* PD2<2> */
+        for (j = 4; j < 8; j++)
+            pd2 ^= ((block[8*i+j] ^ (block[8*i+j] >> 1) ^ (block[8*i+j] >> 2) ^
+                     (block[8*i+j] >> 3) ^ (block[8*i+j] >> 4) ^ (block[8*i+j] >> 5) ^
+                     (block[8*i+j] >> 6) ^ (block[8*i+j] >> 7)) & 1) << 2;
+    for (i = 0; i < 16; i++)    /* PD2<3> */
+        for (j = 8; j < 16; j++)
+            pd2 ^= ((block[16*i+j] ^ (block[16*i+j] >> 1) ^ (block[16*i+j] >> 2) ^
+                     (block[16*i+j] >> 3) ^ (block[16*i+j] >> 4) ^ (block[16*i+j] >> 5) ^
+                     (block[16*i+j] >> 6) ^ (block[16*i+j] >> 7)) & 1) << 3;
+    for (i = 0; i < 8; i++)     /* PD2<4> */
+        for (j = 16; j < 32; j++)
+            pd2 ^= ((block[32*i+j] ^ (block[32*i+j] >> 1) ^ (block[32*i+j] >> 2) ^
+                     (block[32*i+j] >> 3) ^ (block[32*i+j] >> 4) ^ (block[32*i+j] >> 5) ^
+                     (block[32*i+j] >> 6) ^ (block[32*i+j] >> 7)) & 1) << 4;
+    for (i = 0; i < 4; i++)     /* PD2<5> */
+        for (j = 32; j < 64; j++)
+            pd2 ^= ((block[64*i+j] ^ (block[64*i+j] >> 1) ^ (block[64*i+j] >> 2) ^
+                     (block[64*i+j] >> 3) ^ (block[64*i+j] >> 4) ^ (block[64*i+j] >> 5) ^
+                     (block[64*i+j] >> 6) ^ (block[64*i+j] >> 7)) & 1) << 5;
+    for (i = 0; i < 2; i++)     /* PD2<6> */
+        for (j = 64; j < 128; j++)
+            pd2 ^= ((block[128*i+j] ^ (block[128*i+j] >> 1) ^ (block[128*i+j] >> 2) ^
+                     (block[128*i+j] >> 3) ^ (block[128*i+j] >> 4) ^ (block[128*i+j] >> 5) ^
+                     (block[128*i+j] >> 6) ^ (block[128*i+j] >> 7)) & 1) << 6;
+    for (i = 128; i < 256; i++) /* PD2<7> */
+        pd2 ^= ((block[i] ^ (block[i] >> 1) ^ (block[i] >> 2) ^
+                 (block[i] >> 3) ^ (block[i] >> 4) ^ (block[i] >> 5) ^
+                 (block[i] >> 6) ^ (block[i] >> 7)) & 1) << 7;
+
+    xorpd0 = pd0 ^ block[256];
+    xorpd1 = pd1 ^ block[257];
+    xorpd2 = pd2 ^ block[258];
+
+    xor_num = __builtin_popcount((xorpd0 << 16) | (xorpd1 << 8) | xorpd2);
+    check = (((xorpd1 & 7) << 8) | xorpd0) ^ ((xorpd2 << 3) | (xorpd1 >> 5));
+
+    if (xor_num == 0)
+        return 0;
+    else if ((xor_num > 1) && (check != 0x7FF))
+        return 2;
+
+    if (check == 0x7FF)
+    {
+        /* Correct the error */
+        block[xorpd2] ^= 1 << (xorpd1 >> 5);
+    }
+
+    return 1;
+}
diff --git a/cvmx-nand.h b/cvmx-nand.h
new file mode 100644
index 0000000000000..8ca4f9acca6d9
--- /dev/null
+++ b/cvmx-nand.h
@@ -0,0 +1,675 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This header defines the CVMX interface to the NAND flash controller. The
+ * basic operations common to all NAND devices are supported by this API, but
+ * many more advanced functions are not support. The low level hardware supports
+ * all types of transactions, but this API only implements the must commonly
+ * used operations. This API performs no locking, so it is the responsibility of
+ * the caller to make sure only one thread of execution is accessing the NAND
+ * controller at a time. Most applications should not use this API directly but
+ * instead use a flash logical layer supplied through a secondary system. For
+ * example, the Linux MTD layer provides a driver for running JFFS2 on top of
+ * NAND flash.
+ *
+ * <h2>Selecting the NAND Chip</h2>
+ *
+ * Octeon's NAND controller assumes a single NAND chip is connected to a boot
+ * bus chip select. Throughout this API, NAND chips are referred to by the chip
+ * select they are connected to (0-7). Chip select 0 will only be a NAND chip
+ * when you are booting from NAND flash.
+ *
+ * <h2>NAND Addressing</h2>
+ *
+ * Various functions in cvmx-nand use addresses to index into NAND flash. All
+ * functions us a uniform address translation scheme to map the passed address
+ * into a NAND block, page, and column. In NAND flash a page represents the
+ * basic unit of reads and writes. Each page contains a power of two number of
+ * bytes and some number of extra out of band (OOB) bytes. A fixed number of
+ * pages fit into each NAND block. Here is the mapping of bits in the cvmx-nand
+ * address to the NAND hardware:
+ * <pre>
+ * 63     56      48      40      32      24      16       8      0
+ * +-------+-------+-------+-------+-------+-------+-------+------+
+ * |                                 64 bit cvmx-nand nand_address|
+ * +------------------------------------------------+----+--------+
+ * |                                          block |page| column |
+ * +-------+-------+-------+-------+-------+--------+----+--------+
+ * 63     56      48      40      32      24      16       8      0
+ * </pre>
+ * Basically the block, page, and column addresses are packet together. Before
+ * being sent out the NAND pins for addressing the column is padded out to an
+ * even number of bytes. This means that column address are 2 bytes, or 2
+ * address cycles, for page sizes between 512 and 65536 bytes. Page sizes
+ * between 128KB and 16MB would use 3 column address cycles. NAND device
+ * normally either have 32 or 64 pages per block, needing either 5 or 6 address
+ * bits respectively. This means you have 10 bits for block address using 4
+ * address cycles, or 18 for 5 address cycles. Using the cvmx-nand addressing
+ * scheme, it is not possible to directly index the OOB data. Instead you can
+ * access it by reading or writing more data than the normal page size would
+ * allow. Logically the OOB data is appended onto the the page data. For
+ * example, this means that a read of 65 bytes from a column address of 0x7ff
+ * would yield byte 2047 of the page and then 64 bytes of OOB data.
+ *
+ * <hr>$Revision: 35726 $<hr>
+ */
+
+#ifndef __CVMX_NAND_H__
+#define __CVMX_NAND_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/* Block size for boot ECC */
+#define CVMX_NAND_BOOT_ECC_BLOCK_SIZE    (256)
+/* ECC bytes for each block */
+#define CVMX_NAND_BOOT_ECC_ECC_SIZE      (8)
+
+/**
+ * Flags to be passed to the initialize function
+ */
+typedef enum
+{
+    CVMX_NAND_INITIALIZE_FLAGS_16BIT = 1<<0,
+    CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE = 1<<1,
+    CVMX_NAND_INITIALIZE_FLAGS_DEBUG = 1<<15,
+} cvmx_nand_initialize_flags_t;
+
+/**
+ * Return codes from NAND functions
+ */
+typedef enum
+{
+    CVMX_NAND_SUCCESS = 0,
+    CVMX_NAND_NO_MEMORY = -1,
+    CVMX_NAND_BUSY = -2,
+    CVMX_NAND_INVALID_PARAM = -3,
+    CVMX_NAND_TIMEOUT = -4,
+} cvmx_nand_status_t;
+
+/**
+ * NAND NOP command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_4_63      : 60;
+    uint64_t zero               : 4;
+} cvmx_nand_cmd_nop_t;
+
+/**
+ * NAND SET_TM_PAR command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t tim_par7           : 8;
+    uint64_t tim_par6           : 8;
+    uint64_t tim_par5           : 8;
+    uint64_t tim_par4           : 8;
+    uint64_t tim_par3           : 8;
+    uint64_t tim_par2           : 8;
+    uint64_t tim_par1           : 8;
+    uint64_t tim_mult           : 4;
+    uint64_t one                : 4;
+} cvmx_nand_cmd_set_tm_par_t;
+
+/**
+ * NAND WAIT command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_11_63     : 53;
+    uint64_t n                  : 3;
+    uint64_t reserved_5_7       : 3;
+    uint64_t r_b                : 1;
+    uint64_t two                : 4;
+} cvmx_nand_cmd_wait_t;
+
+/**
+ * NAND CHIP_EN command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_10_63     : 54;
+    uint64_t width              : 2;
+    uint64_t one                : 1;
+    uint64_t chip               : 3;
+    uint64_t three              : 4;
+} cvmx_nand_cmd_chip_en_t;
+
+/**
+ * NAND CHIP_DIS command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_4_63      : 60;
+    uint64_t three              : 4;
+} cvmx_nand_cmd_chip_dis_t;
+
+/**
+ * NAND CLE command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_25_63     : 39;
+    uint64_t clen3              : 3;
+    uint64_t clen2              : 3;
+    uint64_t clen1              : 3;
+    uint64_t cmd_data           : 8;
+    uint64_t reserved_4_7       : 4;
+    uint64_t four               : 4;
+} cvmx_nand_cmd_cle_t;
+
+/**
+ * NAND ALE command definition
+ */
+typedef struct
+{
+    uint64_t reserved_96_127    : 32;
+    uint64_t adr_bytes_h        : 32;
+    uint64_t adr_bytes_l        : 32;
+    uint64_t reserved_28_31     : 4;
+    uint64_t alen4              : 3;
+    uint64_t alen3              : 3;
+    uint64_t alen2              : 3;
+    uint64_t alen1              : 3;
+    uint64_t reserved_12_15     : 4;
+    uint64_t adr_byte_num       : 4;
+    uint64_t reserved_4_7       : 4;
+    uint64_t five               : 4;
+} cvmx_nand_cmd_ale_t;
+
+/**
+ * NAND WR command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_31_63     : 34;
+    uint64_t wrn2               : 3;
+    uint64_t wrn1               : 3;
+    uint64_t reserved_20_24     : 4;
+    uint64_t data_bytes         : 16;
+    uint64_t eight              : 4;
+} cvmx_nand_cmd_wr_t;
+
+/**
+ * NAND RD command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_32_63     : 32;
+    uint64_t rdn4               : 3;
+    uint64_t rdn3               : 3;
+    uint64_t rdn2               : 3;
+    uint64_t rdn1               : 3;
+    uint64_t data_bytes         : 16;
+    uint64_t nine               : 4;
+} cvmx_nand_cmd_rd_t;
+
+/**
+ * NAND RD_EDO command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_32_63     : 32;
+    uint64_t rdn4               : 3;
+    uint64_t rdn3               : 3;
+    uint64_t rdn2               : 3;
+    uint64_t rdn1               : 3;
+    uint64_t data_bytes         : 16;
+    uint64_t ten                : 4;
+} cvmx_nand_cmd_rd_edo_t;
+
+/**
+ * NAND WAIT_STATUS command definition
+ */
+typedef struct
+{
+    uint64_t rdn4               : 3;
+    uint64_t rdn3               : 3;
+    uint64_t rdn2               : 3;
+    uint64_t rdn1               : 3;
+    uint64_t comp_byte          : 8;
+    uint64_t and_mask           : 8;
+    uint64_t nine               : 4;
+    uint64_t reserved_28_95     : 64;
+    uint64_t clen4              : 3;
+    uint64_t clen3              : 3;
+    uint64_t clen2              : 3;
+    uint64_t clen1              : 3;
+    uint64_t data               : 8;
+    uint64_t reserved_4_7       : 4;
+    uint64_t eleven             : 4;
+} cvmx_nand_cmd_wait_status_t;
+
+/**
+ * NAND WAIT_STATUS_ALE command definition
+ */
+typedef struct
+{
+    uint64_t rdn4               : 3;
+    uint64_t rdn3               : 3;
+    uint64_t rdn2               : 3;
+    uint64_t rdn1               : 3;
+    uint64_t comp_byte          : 8;
+    uint64_t and_mask           : 8;
+    uint64_t nine               : 4;
+    uint64_t adr_bytes          : 32;
+    uint64_t reserved_60_63     : 4;
+    uint64_t alen4              : 3;
+    uint64_t alen3              : 3;
+    uint64_t alen2              : 3;
+    uint64_t alen1              : 3;
+    uint64_t reserved_44_47     : 4;
+    uint64_t adr_byte_num       : 4;
+    uint64_t five               : 4;
+    uint64_t reserved_25_31     : 7;
+    uint64_t clen3              : 3;
+    uint64_t clen2              : 3;
+    uint64_t clen1              : 3;
+    uint64_t data               : 8;
+    uint64_t reserved_4_7       : 4;
+    uint64_t eleven             : 4;
+} cvmx_nand_cmd_wait_status_ale_t;
+
+/**
+ * NAND BUS_ACQ command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_8_63      : 56;
+    uint64_t one                : 4;
+    uint64_t fifteen            : 4;
+} cvmx_nand_cmd_bus_acq_t;
+
+/**
+ * NAND BUS_REL command definition
+ */
+typedef struct
+{
+    uint64_t reserved_64_127    : 64;
+    uint64_t reserved_8_63      : 56;
+    uint64_t zero               : 4;
+    uint64_t fifteen            : 4;
+} cvmx_nand_cmd_bus_rel_t;
+
+/**
+ * NAND command union of all possible commands
+ */
+typedef union
+{
+    uint64_t u64[2];
+    cvmx_nand_cmd_nop_t             nop;
+    cvmx_nand_cmd_set_tm_par_t      set_tm_par;
+    cvmx_nand_cmd_wait_t            wait;
+    cvmx_nand_cmd_chip_en_t         chip_en;
+    cvmx_nand_cmd_chip_dis_t        chip_dis;
+    cvmx_nand_cmd_cle_t             cle;
+    cvmx_nand_cmd_ale_t             ale;
+    cvmx_nand_cmd_rd_t              rd;
+    cvmx_nand_cmd_rd_edo_t          rd_edo;
+    cvmx_nand_cmd_wr_t              wr;
+    cvmx_nand_cmd_wait_status_t     wait_status;
+    cvmx_nand_cmd_wait_status_ale_t wait_status_ale;
+    cvmx_nand_cmd_bus_acq_t         bus_acq;
+    cvmx_nand_cmd_bus_rel_t         bus_rel;
+    struct
+    {
+        uint64_t reserved_64_127: 64;
+        uint64_t reserved_4_63  : 60;
+        uint64_t op_code        : 4;
+    } s;
+} cvmx_nand_cmd_t;
+
+
+typedef struct __attribute__ ((packed))
+{
+    char onfi[4];                   /**< Bytes 0-3: The ASCII characters 'O', 'N', 'F', 'I' */
+    uint16_t revision_number;       /**< Bytes 4-5: ONFI revision number
+                                        - 2-15 Reserved (0)
+                                        - 1    1 = supports ONFI version 1.0
+                                        - 0    Reserved (0) */
+    uint16_t features;              /**< Bytes 6-7: Features supported
+                                        - 5-15    Reserved (0)
+                                        - 4       1 = supports odd to even page Copyback
+                                        - 3       1 = supports interleaved operations
+                                        - 2       1 = supports non-sequential page programming
+                                        - 1       1 = supports multiple LUN operations
+                                        - 0       1 = supports 16-bit data bus width */
+    uint16_t optional_commands;     /**< Bytes 8-9: Optional commands supported
+                                        - 6-15   Reserved (0)
+                                        - 5      1 = supports Read Unique ID
+                                        - 4      1 = supports Copyback
+                                        - 3      1 = supports Read Status Enhanced
+                                        - 2      1 = supports Get Features and Set Features
+                                        - 1      1 = supports Read Cache commands
+                                        - 0      1 = supports Page Cache Program command */
+    uint8_t reserved_10_31[22];     /**< Bytes 10-31: Reserved */
+
+    char manufacturer[12];          /**< Bytes 32-43: Device manufacturer (12 ASCII characters) */
+    char model[20];                 /**< Bytes 40-63: Device model (20 ASCII characters) */
+    uint8_t jedec_id;               /**< Byte 64: JEDEC manufacturer ID */
+    uint16_t date_code;             /**< Byte 65-66: Date code */
+    uint8_t reserved_67_79[13];     /**< Bytes 67-79: Reserved */
+
+    uint32_t page_data_bytes;       /**< Bytes 80-83: Number of data bytes per page */
+    uint16_t page_spare_bytes;      /**< Bytes 84-85: Number of spare bytes per page */
+    uint32_t partial_page_data_bytes; /**< Bytes 86-89: Number of data bytes per partial page */
+    uint16_t partial_page_spare_bytes; /**< Bytes 90-91: Number of spare bytes per partial page */
+    uint32_t pages_per_block;       /**< Bytes 92-95: Number of pages per block */
+    uint32_t blocks_per_lun;        /**< Bytes 96-99: Number of blocks per logical unit (LUN) */
+    uint8_t number_lun;             /**< Byte 100: Number of logical units (LUNs) */
+    uint8_t address_cycles;         /**< Byte 101: Number of address cycles
+                                        - 4-7     Column address cycles
+                                        - 0-3     Row address cycles */
+    uint8_t bits_per_cell;          /**< Byte 102: Number of bits per cell */
+    uint16_t bad_block_per_lun;     /**< Bytes 103-104: Bad blocks maximum per LUN */
+    uint16_t block_endurance;       /**< Bytes 105-106: Block endurance */
+    uint8_t good_blocks;            /**< Byte 107: Guaranteed valid blocks at beginning of target */
+    uint16_t good_block_endurance;  /**< Bytes 108-109: Block endurance for guaranteed valid blocks */
+    uint8_t programs_per_page;      /**< Byte 110: Number of programs per page */
+    uint8_t partial_program_attrib; /**< Byte 111: Partial programming attributes
+                                        - 5-7    Reserved
+                                        - 4      1 = partial page layout is partial page data followed by partial page spare
+                                        - 1-3    Reserved
+                                        - 0      1 = partial page programming has constraints */
+    uint8_t bits_ecc;               /**< Byte 112: Number of bits ECC correctability */
+    uint8_t interleaved_address_bits;   /**< Byte 113: Number of interleaved address bits
+                                            - 4-7    Reserved (0)
+                                            - 0-3    Number of interleaved address bits */
+    uint8_t interleaved_attrib;     /**< Byte 114: Interleaved operation attributes
+                                        - 4-7    Reserved (0)
+                                        - 3      Address restrictions for program cache
+                                        - 2      1 = program cache supported
+                                        - 1      1 = no block address restrictions
+                                        - 0      Overlapped / concurrent interleaving support */
+    uint8_t reserved_115_127[13];   /**< Bytes 115-127: Reserved (0) */
+
+    uint8_t pin_capacitance;        /**< Byte 128: I/O pin capacitance */
+    uint16_t timing_mode;           /**< Byte 129-130: Timing mode support
+                                        - 6-15   Reserved (0)
+                                        - 5      1 = supports timing mode 5
+                                        - 4      1 = supports timing mode 4
+                                        - 3      1 = supports timing mode 3
+                                        - 2      1 = supports timing mode 2
+                                        - 1      1 = supports timing mode 1
+                                        - 0      1 = supports timing mode 0, shall be 1 */
+    uint16_t cache_timing_mode;     /**< Byte 131-132: Program cache timing mode support
+                                        - 6-15   Reserved (0)
+                                        - 5      1 = supports timing mode 5
+                                        - 4      1 = supports timing mode 4
+                                        - 3      1 = supports timing mode 3
+                                        - 2      1 = supports timing mode 2
+                                        - 1      1 = supports timing mode 1
+                                        - 0      1 = supports timing mode 0 */
+    uint16_t t_prog;                /**< Byte 133-134: Maximum page program time (us) */
+    uint16_t t_bers;                /**< Byte 135-136: Maximum block erase time (us) */
+    uint16_t t_r;                   /**< Byte 137-148: Maximum page read time (us) */
+    uint16_t t_ccs;                 /**< Byte 139-140: Minimum change column setup time (ns) */
+    uint8_t reserved_141_163[23];   /**< Byte 141-163: Reserved (0) */
+
+    uint16_t vendor_revision;       /**< Byte 164-165: Vendor specific Revision number */
+    uint8_t vendor_specific[88];    /**< Byte 166-253: Vendor specific */
+    uint16_t crc;                   /**< Byte 254-255: Integrity CRC */
+} cvmx_nand_onfi_param_page_t;
+
+
+/**
+ * Called to initialize the NAND controller for use. Note that
+ * you must be running out of L2 or memory and not NAND before
+ * calling this function.
+ *
+ * @param flags  Optional initialization flags
+ * @param active_chips
+ *               Each bit in this parameter represents a chip select that might
+ *               contain NAND flash. Any chip select present in this bitmask may
+ *               be connected to NAND. It is normally safe to pass 0xff here and
+ *               let the API probe all 8 chip selects.
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips);
+
+
+/**
+ * Call to shutdown the NAND controller after all transactions
+ * are done. In most setups this will never be called.
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_shutdown(void);
+
+
+/**
+ * Returns a bitmask representing the chip selects that are
+ * connected to NAND chips. This can be called after the
+ * initialize to determine the actual number of NAND chips
+ * found. Each bit in the response coresponds to a chip select.
+ *
+ * @return Zero if no NAND chips were found. Otherwise a bit is set for
+ *         each chip select (1<<chip).
+ */
+extern int cvmx_nand_get_active_chips(void);
+
+
+/**
+ * Override the timing parameters for a NAND chip
+ *
+ * @param chip     Chip select to override
+ * @param tim_mult
+ * @param tim_par
+ * @param clen
+ * @param alen
+ * @param rdn
+ * @param wrn
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[7], int clen[4], int alen[4], int rdn[4], int wrn[2]);
+
+
+/**
+ * Submit a command to the NAND command queue. Generally this
+ * will not be used directly. Instead most programs will use the other
+ * higher level NAND functions.
+ *
+ * @param cmd    Command to submit
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd);
+
+/**
+ * Read a page from NAND. If the buffer has room, the out of band
+ * data will be included.
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               Location in NAND to read. See description in file comment
+ * @param buffer_address
+ *               Physical address to store the result at
+ * @param buffer_length
+ *               Number of bytes to read
+ *
+ * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length);
+
+/**
+ * Write a page to NAND. The buffer must contain the entire page
+ * including the out of band data.
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               Location in NAND to write. See description in file comment
+ * @param buffer_address
+ *               Physical address to read the data from
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address);
+
+/**
+ * Erase a NAND block. A single block contains multiple pages.
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               Location in NAND to erase. See description in file comment
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address);
+
+/**
+ * Read the NAND ID information
+ *
+ * @param chip   Chip select for NAND flash
+ * @param nand_address
+ *               NAND address to read ID from. Usually this is either 0x0 or 0x20.
+ * @param buffer_address
+ *               Physical address to store data in
+ * @param buffer_length
+ *               Length of the buffer. Usually this is 4 bytes
+ *
+ * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length);
+
+/**
+ * Read the NAND parameter page
+ *
+ * @param chip   Chip select for NAND flash
+ * @param buffer_address
+ *               Physical address to store data in
+ * @param buffer_length
+ *               Length of the buffer. Usually this is 4 bytes
+ *
+ * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length);
+
+/**
+ * Get the status of the NAND flash
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return NAND status or a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_get_status(int chip);
+
+/**
+ * Get the page size, excluding out of band data. This  function
+ * will return zero for chip selects not connected to NAND.
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Page size in bytes or a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_get_page_size(int chip);
+
+/**
+ * Get the OOB size.
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return OOB in bytes or a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_get_oob_size(int chip);
+
+/**
+ * Get the number of pages per NAND block
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Numboer of pages in each block or a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_get_pages_per_block(int chip);
+
+/**
+ * Get the number of blocks in the NAND flash
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Number of blocks or a negative cvmx_nand_status_t error code on failure
+ */
+extern int cvmx_nand_get_blocks(int chip);
+
+/**
+ * Reset the NAND flash
+ *
+ * @param chip   Chip select for NAND flash
+ *
+ * @return Zero on success, a negative cvmx_nand_status_t error code on failure
+ */
+extern cvmx_nand_status_t cvmx_nand_reset(int chip);
+
+/**
+ * This function computes the Octeon specific ECC data used by the NAND boot
+ * feature.
+ * 
+ * @param block  pointer to 256 bytes of data
+ * @param eccp   pointer to where 8 bytes of ECC data will be stored
+ */
+extern void cvmx_nand_compute_boot_ecc(unsigned char *block, unsigned char *eccp);
+
+
+extern int cvmx_nand_correct_boot_ecc(uint8_t *block);
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_NAND_H__ */
diff --git a/cvmx-npi.h b/cvmx-npi.h
new file mode 100644
index 0000000000000..dc020060ab136
--- /dev/null
+++ b/cvmx-npi.h
@@ -0,0 +1,147 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * PCI / PCIe packet engine related structures.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_NPI_H__
+#define __CVMX_NPI_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * PCI / PCIe packet instruction header format
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t            r :     1;      /**< Packet is RAW */
+        uint64_t            g :     1;      /**< Gather list is used */
+        uint64_t            dlengsz : 14;   /**< Data length / Gather list size */
+        uint64_t            fsz     : 6;    /**< Front data size */
+        uint64_t            qos     : 3;    /**< POW QoS queue */
+        uint64_t            grp     : 4;    /**< POW Group */
+        uint64_t            rs      : 1;    /**< Real short */
+        cvmx_pow_tag_type_t tt      : 2;    /**< POW Tag type */
+        uint64_t            tag     : 32;   /**< POW 32 bit tag */
+#else
+	uint64_t            tag     : 32;
+	cvmx_pow_tag_type_t tt      : 2;
+	uint64_t            rs      : 1;
+	uint64_t            grp     : 4;
+	uint64_t            qos     : 3;
+	uint64_t            fsz     : 6;
+	uint64_t            dlengsz : 14;
+	uint64_t            g :     1;
+	uint64_t            r :     1;
+#endif
+    } s;
+} cvmx_npi_inst_hdr_t;
+
+/**
+ * PCI / PCIe packet data pointer formats 0-3
+ */
+typedef union
+{
+    uint64_t dptr0;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    es      : 2;    /**< Endian swap mode */
+        uint64_t    ns      : 1;    /**< No snoop */
+        uint64_t    ro      : 1;    /**< Relaxed ordering */
+        uint64_t    addr    : 60;   /**< PCI/PCIe address */
+#else
+        uint64_t    addr    : 60;
+        uint64_t    ro      : 1;
+        uint64_t    ns      : 1;
+        uint64_t    es      : 2;
+#endif
+    } dptr1;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    pm      : 2;    /**< Parse mode */
+        uint64_t    sl      : 7;    /**< Skip length */
+        uint64_t    addr    : 55;   /**< PCI/PCIe address */
+#else
+        uint64_t    addr    : 55;
+        uint64_t    sl      : 7;
+        uint64_t    pm      : 2;
+#endif
+    } dptr2;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    es      : 2;    /**< Endian swap mode */
+        uint64_t    ns      : 1;    /**< No snoop */
+        uint64_t    ro      : 1;    /**< Relaxed ordering */
+        uint64_t    pm      : 2;    /**< Parse mode */
+        uint64_t    sl      : 7;    /**< Skip length */
+        uint64_t    addr    : 51;   /**< PCI/PCIe address */
+#else
+        uint64_t    addr    : 51;
+        uint64_t    sl      : 7;
+        uint64_t    pm      : 2;
+        uint64_t    ro      : 1;
+        uint64_t    ns      : 1;
+        uint64_t    es      : 2;
+#endif
+    } dptr3;
+} cvmx_npi_dptr_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_NPI_H__ */
diff --git a/cvmx-packet.h b/cvmx-packet.h
new file mode 100644
index 0000000000000..f5c4f8c8df13d
--- /dev/null
+++ b/cvmx-packet.h
@@ -0,0 +1,84 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Packet buffer defines.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+#ifndef __CVMX_PACKET_H__
+#define __CVMX_PACKET_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * This structure defines a buffer pointer on Octeon
+ */
+typedef union
+{
+    void*           ptr;
+    uint64_t        u64;
+    struct
+    {
+        uint64_t    i    : 1; /**< if set, invert the "free" pick of the overall packet. HW always sets this bit to 0 on inbound packet */
+        uint64_t    back : 4; /**< Indicates the amount to back up to get to the buffer start in cache lines. In most cases
+                                this is less than one complete cache line, so the value is zero */
+        uint64_t    pool : 3; /**< The pool that the buffer came from / goes to */
+        uint64_t    size :16; /**< The size of the segment pointed to by addr (in bytes) */
+        uint64_t    addr :40; /**< Pointer to the first byte of the data, NOT buffer */
+    } s;
+} cvmx_buf_ptr_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /*  __CVMX_PACKET_H__ */
+
diff --git a/cvmx-pci.h b/cvmx-pci.h
new file mode 100644
index 0000000000000..710a656d86823
--- /dev/null
+++ b/cvmx-pci.h
@@ -0,0 +1,68 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * PCI related structures.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_PCI_H__
+#define __CVMX_PCI_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* The typedefs and enumerations for Octeon's PCI packet engines have been
+    removed from this file. The definitions in this file were out of date
+    and unused. For current definitions, refer to the Octeon PCI NIC
+    driver. OCTEON-PCI-NIC-*.rpm */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_PCI_H__ */
diff --git a/cvmx-pcie.c b/cvmx-pcie.c
new file mode 100644
index 0000000000000..21a9b87e31801
--- /dev/null
+++ b/cvmx-pcie.c
@@ -0,0 +1,1062 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to PCIe as a host(RC) or target(EP)
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-csr-db.h"
+#include "cvmx-pcie.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-swap.h"
+#include "cvmx-wqe.h"
+#include "cvmx-helper-errata.h"
+
+
+/**
+ * Return the Core virtual base address for PCIe IO access. IOs are
+ * read/written as an offset from this address.
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return 64bit Octeon IO base address for read/write
+ */
+uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
+{
+    cvmx_pcie_address_t pcie_addr;
+    pcie_addr.u64 = 0;
+    pcie_addr.io.upper = 0;
+    pcie_addr.io.io = 1;
+    pcie_addr.io.did = 3;
+    pcie_addr.io.subdid = 2;
+    pcie_addr.io.es = 1;
+    pcie_addr.io.port = pcie_port;
+    return pcie_addr.u64;
+}
+
+
+/**
+ * Size of the IO address region returned at address
+ * cvmx_pcie_get_io_base_address()
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return Size of the IO window
+ */
+uint64_t cvmx_pcie_get_io_size(int pcie_port)
+{
+    return 1ull<<32;
+}
+
+
+/**
+ * Return the Core virtual base address for PCIe MEM access. Memory is
+ * read/written as an offset from this address.
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return 64bit Octeon IO base address for read/write
+ */
+uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
+{
+    cvmx_pcie_address_t pcie_addr;
+    pcie_addr.u64 = 0;
+    pcie_addr.mem.upper = 0;
+    pcie_addr.mem.io = 1;
+    pcie_addr.mem.did = 3;
+    pcie_addr.mem.subdid = 3 + pcie_port;
+    return pcie_addr.u64;
+}
+
+
+/**
+ * Size of the Mem address region returned at address
+ * cvmx_pcie_get_mem_base_address()
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return Size of the Mem window
+ */
+uint64_t cvmx_pcie_get_mem_size(int pcie_port)
+{
+    return 1ull<<36;
+}
+
+
+/**
+ * @INTERNAL
+ * Initialize the RC config space CSRs
+ *
+ * @param pcie_port PCIe port to initialize
+ */
+static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
+{
+    /* Max Payload Size (PCIE*_CFG030[MPS]) */
+    /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
+    /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
+    /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
+    {
+        cvmx_pciercx_cfg030_t pciercx_cfg030;
+        pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
+        pciercx_cfg030.s.mps = 0; /* Max payload size = 128 bytes for best Octeon DMA performance */
+        pciercx_cfg030.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        pciercx_cfg030.s.ro_en = 1; /* Enable relaxed order processing. This will allow devices to affect read response ordering */
+        pciercx_cfg030.s.ns_en = 1; /* Enable no snoop processing. Not used by Octeon */
+        pciercx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
+        pciercx_cfg030.s.nfe_en = 1; /* Non-fatal error reporting enable. */
+        pciercx_cfg030.s.fe_en = 1; /* Fatal error reporting enable. */
+        pciercx_cfg030.s.ur_en = 1; /* Unsupported request reporting enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
+    }
+
+    /* Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match PCIE*_CFG030[MPS] */
+    /* Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
+    {
+        cvmx_npei_ctl_status2_t npei_ctl_status2;
+        npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
+        npei_ctl_status2.s.mps = 0; /* Max payload size = 128 bytes for best Octeon DMA performance */
+        npei_ctl_status2.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+    }
+
+    /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
+    {
+        cvmx_pciercx_cfg070_t pciercx_cfg070;
+        pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
+        pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
+        pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
+    }
+
+    /* Access Enables (PCIE*_CFG001[MSAE,ME]) */
+        /* ME and MSAE should always be set. */
+    /* Interrupt Disable (PCIE*_CFG001[I_DIS]) */
+    /* System Error Message Enable (PCIE*_CFG001[SEE]) */
+    {
+        cvmx_pciercx_cfg001_t pciercx_cfg001;
+        pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
+        pciercx_cfg001.s.msae = 1; /* Memory space enable. */
+        pciercx_cfg001.s.me = 1; /* Bus master enable. */
+        pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
+        pciercx_cfg001.s.see = 1; /* SERR# enable */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
+    }
+
+
+    /* Advanced Error Recovery Message Enables */
+    /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
+    /* Use CVMX_PCIERCX_CFG067 hardware default */
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
+
+
+    /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
+    {
+        cvmx_pciercx_cfg032_t pciercx_cfg032;
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
+    }
+
+    /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
+    // FIXME: Anything needed here?
+
+    /* Link Width Mode (PCIERCn_CFG452[LME]) - Set during cvmx_pcie_rc_initialize_link() */
+    /* Primary Bus Number (PCIERCn_CFG006[PBNUM]) */
+    {
+        /* We set the primary bus number to 1 so IDT bridges are happy. They don't like zero */
+        cvmx_pciercx_cfg006_t pciercx_cfg006;
+        pciercx_cfg006.u32 = 0;
+        pciercx_cfg006.s.pbnum = 1;
+        pciercx_cfg006.s.sbnum = 1;
+        pciercx_cfg006.s.subbnum = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
+    }
+
+    /* Memory-mapped I/O BAR (PCIERCn_CFG008) */
+    /* Most applications should disable the memory-mapped I/O BAR by */
+    /* setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR] */
+    {
+        cvmx_pciercx_cfg008_t pciercx_cfg008;
+        pciercx_cfg008.u32 = 0;
+        pciercx_cfg008.s.mb_addr = 0x100;
+        pciercx_cfg008.s.ml_addr = 0;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
+    }
+
+    /* Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) */
+    /* Most applications should disable the prefetchable BAR by setting */
+    /* PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < */
+    /* PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] */
+    {
+        cvmx_pciercx_cfg009_t pciercx_cfg009;
+        cvmx_pciercx_cfg010_t pciercx_cfg010;
+        cvmx_pciercx_cfg011_t pciercx_cfg011;
+        pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
+        pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
+        pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
+        pciercx_cfg009.s.lmem_base = 0x100;
+        pciercx_cfg009.s.lmem_limit = 0;
+        pciercx_cfg010.s.umem_base = 0x100;
+        pciercx_cfg011.s.umem_limit = 0;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
+    }
+
+    /* System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) */
+    /* PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) */
+    {
+        cvmx_pciercx_cfg035_t pciercx_cfg035;
+        pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
+        pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
+        pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
+        pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
+        pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
+    }
+
+    /* Advanced Error Recovery Interrupt Enables */
+    /* (PCIERCn_CFG075[CERE,NFERE,FERE]) */
+    {
+        cvmx_pciercx_cfg075_t pciercx_cfg075;
+        pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
+        pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
+        pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
+        pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
+    }
+
+    /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], */
+    /* PCIERCn_CFG034[DLLS_EN,CCINT_EN]) */
+    {
+        cvmx_pciercx_cfg034_t pciercx_cfg034;
+        pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
+        pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
+        pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
+        pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Initialize a host mode PCIe link. This function takes a PCIe
+ * port from reset to a link up state. Software can then begin
+ * configuring the rest of the link.
+ *
+ * @param pcie_port PCIe port to initialize
+ *
+ * @return Zero on success
+ */
+static int __cvmx_pcie_rc_initialize_link(int pcie_port)
+{
+    uint64_t start_cycle;
+    cvmx_pescx_ctl_status_t pescx_ctl_status;
+    cvmx_pciercx_cfg452_t pciercx_cfg452;
+    cvmx_pciercx_cfg032_t pciercx_cfg032;
+    cvmx_pciercx_cfg448_t pciercx_cfg448;
+
+    /* Set the lane width */
+    pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
+    pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
+    if (pescx_ctl_status.s.qlm_cfg == 0)
+    {
+        /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
+        pciercx_cfg452.s.lme = 0xf;
+    }
+    else
+    {
+        /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
+        pciercx_cfg452.s.lme = 0x7;
+    }
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
+
+    /* CN52XX pass 1.x has an errata where length mismatches on UR responses can
+        cause bus errors on 64bit memory reads. Turning off length error
+        checking fixes this */
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+    {
+        cvmx_pciercx_cfg455_t pciercx_cfg455;
+        pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
+        pciercx_cfg455.s.m_cpl_len_err = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
+    }
+
+    /* Lane swap needs to be manually enabled for CN52XX */
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1))
+    {
+      pescx_ctl_status.s.lane_swp = 1;
+      cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),pescx_ctl_status.u64);
+    }
+
+    /* Bring up the link */
+    pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
+    pescx_ctl_status.s.lnk_enb = 1;
+    cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
+
+    /* CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to be disabled */
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
+        __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
+
+    /* Wait for the link to come up */
+    start_cycle = cvmx_get_cycle();
+    do
+    {
+        if (cvmx_get_cycle() - start_cycle > 2*cvmx_sysinfo_get()->cpu_clock_hz)
+        {
+            cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
+            return -1;
+        }
+        cvmx_wait(10000);
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+    } while (pciercx_cfg032.s.dlla == 0);
+
+    /* Update the Replay Time Limit. Empirically, some PCIe devices take a
+        little longer to respond than expected under load. As a workaround for
+        this we configure the Replay Time Limit to the value expected for a 512
+        byte MPS instead of our actual 256 byte MPS. The numbers below are
+        directly from the PCIe spec table 3-4 */
+    pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+    switch (pciercx_cfg032.s.nlw)
+    {
+        case 1: /* 1 lane */
+            pciercx_cfg448.s.rtl = 1677;
+            break;
+        case 2: /* 2 lanes */
+            pciercx_cfg448.s.rtl = 867;
+            break;
+        case 4: /* 4 lanes */
+            pciercx_cfg448.s.rtl = 462;
+            break;
+        case 8: /* 8 lanes */
+            pciercx_cfg448.s.rtl = 258;
+            break;
+    }
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
+
+    return 0;
+}
+
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ *
+ * @param pcie_port PCIe port to initialize
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_rc_initialize(int pcie_port)
+{
+    int i;
+    cvmx_ciu_soft_prst_t ciu_soft_prst;
+    cvmx_pescx_bist_status_t pescx_bist_status;
+    cvmx_pescx_bist_status2_t pescx_bist_status2;
+    cvmx_npei_ctl_status_t npei_ctl_status;
+    cvmx_npei_mem_access_ctl_t npei_mem_access_ctl;
+    cvmx_npei_mem_access_subidx_t mem_access_subid;
+    cvmx_npei_dbg_data_t npei_dbg_data;
+    cvmx_pescx_ctl_status2_t pescx_ctl_status2;
+    cvmx_pciercx_cfg032_t pciercx_cfg032;
+
+retry:
+    /* Make sure we aren't trying to setup a target mode interface in host mode */
+    npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+    if ((pcie_port==0) && !npei_ctl_status.s.host_mode)
+    {
+        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port0, but port0 is not in host mode\n");
+        return -1;
+    }
+
+    /* Make sure a CN52XX isn't trying to bring up port 1 when it is disabled */
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+        if ((pcie_port==1) && npei_dbg_data.cn52xx.qlm0_link_width)
+        {
+            cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
+            return -1;
+        }
+    }
+
+    /* PCIe switch arbitration mode. '0' == fixed priority NPEI, PCIe0, then PCIe1. '1' == round robin. */
+    npei_ctl_status.s.arb = 1;
+    /* Allow up to 0x20 config retries */
+    npei_ctl_status.s.cfg_rtry = 0x20;
+    /* CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS don't reset */
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+    {
+        npei_ctl_status.s.p0_ntags = 0x20;
+        npei_ctl_status.s.p1_ntags = 0x20;
+    }
+    cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
+
+    /* Bring the PCIe out of reset */
+    if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200)
+    {
+        /* The EBH5200 board swapped the PCIe reset lines on the board. As a
+            workaround for this bug, we bring both PCIe ports out of reset at
+            the same time instead of on separate calls. So for port 0, we bring
+            both out of reset and do nothing on port 1 */
+        if (pcie_port == 0)
+        {
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+            /* After a chip reset the PCIe will also be in reset. If it isn't,
+                most likely someone is trying to init it again without a proper
+                PCIe reset */
+            if (ciu_soft_prst.s.soft_prst == 0)
+            {
+		/* Reset the ports */
+		ciu_soft_prst.s.soft_prst = 1;
+		cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+		ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+		ciu_soft_prst.s.soft_prst = 1;
+		cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+		/* Wait until pcie resets the ports. */
+		cvmx_wait_usec(2000);
+            }
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+            ciu_soft_prst.s.soft_prst = 0;
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+            ciu_soft_prst.s.soft_prst = 0;
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+        }
+    }
+    else
+    {
+        /* The normal case: The PCIe ports are completely separate and can be
+            brought out of reset independently */
+        if (pcie_port)
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        else
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        /* After a chip reset the PCIe will also be in reset. If it isn't,
+            most likely someone is trying to init it again without a proper
+            PCIe reset */
+        if (ciu_soft_prst.s.soft_prst == 0)
+        {
+	    /* Reset the port */
+	    ciu_soft_prst.s.soft_prst = 1;
+	    if (pcie_port)
+		cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+ 	    else
+		cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+	    /* Wait until pcie resets the ports. */
+	    cvmx_wait_usec(2000);
+        }
+        if (pcie_port)
+        {
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+            ciu_soft_prst.s.soft_prst = 0;
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+        }
+        else
+        {
+            ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+            ciu_soft_prst.s.soft_prst = 0;
+            cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+        }
+    }
+
+    /* Wait for PCIe reset to complete. Due to errata PCIE-700, we don't poll
+       PESCX_CTL_STATUS2[PCIERST], but simply wait a fixed number of cycles */
+    cvmx_wait(400000);
+
+    /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
+        CN52XX, so we only probe it on newer chips */
+    if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+    {
+        /* Clear PCLK_RUN so we can check if the clock is running */
+        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+        pescx_ctl_status2.s.pclk_run = 1;
+        cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
+        /* Now that we cleared PCLK_RUN, wait for it to be set again telling
+            us the clock is running */
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
+            cvmx_pescx_ctl_status2_t, pclk_run, ==, 1, 10000))
+        {
+            cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
+            return -1;
+        }
+    }
+
+    /* Check and make sure PCIe came out of reset. If it doesn't the board
+        probably hasn't wired the clocks up and the interface should be
+        skipped */
+    pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+    if (pescx_ctl_status2.s.pcierst)
+    {
+        cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
+        return -1;
+    }
+
+    /* Check BIST2 status. If any bits are set skip this interface. This
+        is an attempt to catch PCIE-813 on pass 1 parts */
+    pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
+    if (pescx_bist_status2.u64)
+    {
+        cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n", pcie_port);
+        return -1;
+    }
+
+    /* Check BIST status */
+    pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
+    if (pescx_bist_status.u64)
+        cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pescx_bist_status.u64));
+
+    /* Initialize the config space CSRs */
+    __cvmx_pcie_rc_initialize_config_space(pcie_port);
+
+    /* Bring the link up */
+    if (__cvmx_pcie_rc_initialize_link(pcie_port))
+    {
+        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
+        return -1;
+    }
+
+    /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+    npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
+    npei_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
+    npei_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
+    cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
+
+    /* Setup Mem access SubDIDs */
+    mem_access_subid.u64 = 0;
+    mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+    mem_access_subid.s.nmerge = 1;  /* Due to an errata on pass 1 chips, no merging is allowed. */
+    mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+    mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+    mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
+    mem_access_subid.s.nsw = 0;     /* Enable Snoop for Writes. */
+    mem_access_subid.s.ror = 0;     /* Disable Relaxed Ordering for Reads. */
+    mem_access_subid.s.row = 0;     /* Disable Relaxed Ordering for Writes. */
+    mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
+
+    /* Setup mem access 12-15 for port 0, 16-19 for port 1, supplying 36 bits of address space */
+    for (i=12 + pcie_port*4; i<16 + pcie_port*4; i++)
+    {
+        cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+        mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
+    }
+
+    /* Disable the peer to peer forwarding register. This must be setup
+        by the OS after it enumerates the bus and assigns addresses to the
+        PCIe busses */
+    for (i=0; i<4; i++)
+    {
+        cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
+        cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
+    }
+
+    /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
+    cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
+
+    /* Disable Octeon's BAR1. It isn't needed in RC mode since BAR2
+        maps all of memory. BAR2 also maps 256MB-512MB into the 2nd
+        256MB of memory */
+    cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
+
+    /* Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take precedence
+        where they overlap. It also overlaps with the device addresses, so
+        make sure the peer to peer forwarding is set right */
+    cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
+
+    /* Setup BAR2 attributes */
+    /* Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) */
+    /* ­ PTLP_RO,CTLP_RO should normally be set (except for debug). */
+    /* ­ WAIT_COM=0 will likely work for all applications. */
+    /* Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) */
+    if (pcie_port)
+    {
+        cvmx_npei_ctl_port1_t npei_ctl_port;
+        npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
+        npei_ctl_port.s.bar2_enb = 1;
+        npei_ctl_port.s.bar2_esx = 1;
+        npei_ctl_port.s.bar2_cax = 0;
+        npei_ctl_port.s.ptlp_ro = 1;
+        npei_ctl_port.s.ctlp_ro = 1;
+        npei_ctl_port.s.wait_com = 0;
+        npei_ctl_port.s.waitl_com = 0;
+        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
+    }
+    else
+    {
+        cvmx_npei_ctl_port0_t npei_ctl_port;
+        npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
+        npei_ctl_port.s.bar2_enb = 1;
+        npei_ctl_port.s.bar2_esx = 1;
+        npei_ctl_port.s.bar2_cax = 0;
+        npei_ctl_port.s.ptlp_ro = 1;
+        npei_ctl_port.s.ctlp_ro = 1;
+        npei_ctl_port.s.wait_com = 0;
+        npei_ctl_port.s.waitl_com = 0;
+        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
+    }
+
+    /* Both pass 1 and pass 2 of CN52XX and CN56XX have an errata that causes
+        TLP ordering to not be preserved after multiple PCIe port resets. This
+        code detects this fault and corrects it by aligning the TLP counters
+        properly. Another link reset is then performed. See PCIE-13340 */
+    if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
+        OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+    {
+        cvmx_npei_dbg_data_t dbg_data;
+        int old_in_fif_p_count;
+        int in_fif_p_count;
+        int out_p_count;
+        int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
+        int i;
+
+        /* Choose a write address of 1MB. It should be harmless as all bars
+            haven't been setup */
+        uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
+
+        /* Make sure at least in_p_offset have been executed before we try and
+            read in_fif_p_count */
+        i = in_p_offset;
+        while (i--)
+        {
+            cvmx_write64_uint32(write_address, 0);
+            cvmx_wait(10000);
+        }
+
+        /* Read the IN_FIF_P_COUNT from the debug select. IN_FIF_P_COUNT can be
+            unstable sometimes so read it twice with a write between the reads.
+            This way we can tell the value is good as it will increment by one
+            due to the write */
+        cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
+        cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+        do
+        {
+            dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+            old_in_fif_p_count = dbg_data.s.data & 0xff;
+            cvmx_write64_uint32(write_address, 0);
+            cvmx_wait(10000);
+            dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+            in_fif_p_count = dbg_data.s.data & 0xff;
+        } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
+
+        /* Update in_fif_p_count for it's offset with respect to out_p_count */
+        in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
+
+        /* Read the OUT_P_COUNT from the debug select */
+        cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
+        cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+        out_p_count = (dbg_data.s.data>>1) & 0xff;
+
+        /* Check that the two counters are aligned */
+        if (out_p_count != in_fif_p_count)
+        {
+            cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
+            while (in_fif_p_count != 0)
+            {
+                cvmx_write64_uint32(write_address, 0);
+                cvmx_wait(10000);
+                in_fif_p_count = (in_fif_p_count + 1) & 0xff;
+            }
+            /* The EBH5200 board swapped the PCIe reset lines on the board. This
+                means we must bring both links down and up, which will cause the
+                PCIe0 to need alignment again. Lots of messages will be displayed,
+                but everything should work */
+            if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
+                (pcie_port == 1))
+                cvmx_pcie_rc_initialize(0);
+            /* Rety bringing this port up */
+            goto retry;
+        }
+    }
+
+    /* Display the link status */
+    pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+    cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
+
+    return 0;
+}
+
+
+/**
+ * Shutdown a PCIe port and put it in reset
+ *
+ * @param pcie_port PCIe port to shutdown
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_rc_shutdown(int pcie_port)
+{
+    /* Wait for all pending operations to complete */
+    if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CPL_LUT_VALID(pcie_port), cvmx_pescx_cpl_lut_valid_t, tag, ==, 0, 2000))
+        cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
+
+    /* Force reset */
+    if (pcie_port)
+    {
+        cvmx_ciu_soft_prst_t ciu_soft_prst;
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        ciu_soft_prst.s.soft_prst = 1;
+        cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+    }
+    else
+    {
+        cvmx_ciu_soft_prst_t ciu_soft_prst;
+        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        ciu_soft_prst.s.soft_prst = 1;
+        cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+    }
+    return 0;
+}
+
+
+/**
+ * @INTERNAL
+ * Build a PCIe config space request address for a device
+ *
+ * @param pcie_port PCIe port to access
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return 64bit Octeon IO address
+ */
+static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, int dev, int fn, int reg)
+{
+    cvmx_pcie_address_t pcie_addr;
+    cvmx_pciercx_cfg006_t pciercx_cfg006;
+
+    pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
+    if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
+        return 0;
+
+    pcie_addr.u64 = 0;
+    pcie_addr.config.upper = 2;
+    pcie_addr.config.io = 1;
+    pcie_addr.config.did = 3;
+    pcie_addr.config.subdid = 1;
+    pcie_addr.config.es = 1;
+    pcie_addr.config.port = pcie_port;
+    pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
+    pcie_addr.config.bus = bus;
+    pcie_addr.config.dev = dev;
+    pcie_addr.config.func = fn;
+    pcie_addr.config.reg = reg;
+    return pcie_addr.u64;
+}
+
+
+/**
+ * Read 8bits from a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return Result of the read
+ */
+uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg)
+{
+    uint64_t address = __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+    if (address)
+        return cvmx_read64_uint8(address);
+    else
+        return 0xff;
+}
+
+
+/**
+ * Read 16bits from a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return Result of the read
+ */
+uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg)
+{
+    uint64_t address = __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+    if (address)
+        return cvmx_le16_to_cpu(cvmx_read64_uint16(address));
+    else
+        return 0xffff;
+}
+
+
+/**
+ * Read 32bits from a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return Result of the read
+ */
+uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg)
+{
+    uint64_t address = __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+    if (address)
+        return cvmx_le32_to_cpu(cvmx_read64_uint32(address));
+    else
+        return 0xffffffff;
+}
+
+
+/**
+ * Write 8bits to a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ * @param val       Value to write
+ */
+void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val)
+{
+    uint64_t address = __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+    if (address)
+        cvmx_write64_uint8(address, val);
+}
+
+
+/**
+ * Write 16bits to a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ * @param val       Value to write
+ */
+void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val)
+{
+    uint64_t address = __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+    if (address)
+        cvmx_write64_uint16(address, cvmx_cpu_to_le16(val));
+}
+
+
+/**
+ * Write 32bits to a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ * @param val       Value to write
+ */
+void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val)
+{
+    uint64_t address = __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+    if (address)
+        cvmx_write64_uint32(address, cvmx_cpu_to_le32(val));
+}
+
+
+/**
+ * Read a PCIe config space register indirectly. This is used for
+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
+ *
+ * @param pcie_port  PCIe port to read from
+ * @param cfg_offset Address to read
+ *
+ * @return Value read
+ */
+uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
+{
+    cvmx_pescx_cfg_rd_t pescx_cfg_rd;
+    pescx_cfg_rd.u64 = 0;
+    pescx_cfg_rd.s.addr = cfg_offset;
+    cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
+    pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
+    return pescx_cfg_rd.s.data;
+}
+
+
+/**
+ * Write a PCIe config space register indirectly. This is used for
+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
+ *
+ * @param pcie_port  PCIe port to write to
+ * @param cfg_offset Address to write
+ * @param val        Value to write
+ */
+void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
+{
+    cvmx_pescx_cfg_wr_t pescx_cfg_wr;
+    pescx_cfg_wr.u64 = 0;
+    pescx_cfg_wr.s.addr = cfg_offset;
+    pescx_cfg_wr.s.data = val;
+    cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+}
+
+
+/**
+ * Initialize a PCIe port for use in target(EP) mode.
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_ep_initialize(void)
+{
+    int pcie_port = 0;
+    cvmx_npei_ctl_status_t npei_ctl_status;
+
+    npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+    if (npei_ctl_status.s.host_mode)
+        return -1;
+
+    /* Enable bus master and memory */
+    cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEP_CFG001, 0x6);
+
+    /* Max Payload Size (PCIE*_CFG030[MPS]) */
+    /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
+    /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
+    /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
+    {
+        cvmx_pciercx_cfg030_t pciercx_cfg030;
+        pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
+        pciercx_cfg030.s.mps = 0; /* Max payload size = 128 bytes (Limit of most PCs) */
+        pciercx_cfg030.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        pciercx_cfg030.s.ro_en = 1; /* Enable relaxed ordering. */
+        pciercx_cfg030.s.ns_en = 1; /* Enable no snoop. */
+        pciercx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
+        pciercx_cfg030.s.nfe_en = 1; /* Non-fatal error reporting enable. */
+        pciercx_cfg030.s.fe_en = 1; /* Fatal error reporting enable. */
+        pciercx_cfg030.s.ur_en = 1; /* Unsupported request reporting enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
+    }
+
+    /* Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match PCIE*_CFG030[MPS] */
+    /* Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not exceed PCIE*_CFG030[MRRS] */
+    {
+        cvmx_npei_ctl_status2_t npei_ctl_status2;
+        npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
+        npei_ctl_status2.s.mps = 0; /* Max payload size = 128 bytes (Limit of most PCs) */
+        npei_ctl_status2.s.mrrs = 0; /* Max read request size = 128 bytes for best Octeon DMA performance */
+        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+    }
+
+    /* Setup Mem access SubDID 12 to access Host memory */
+    {
+        cvmx_npei_mem_access_subidx_t mem_access_subid;
+        mem_access_subid.u64 = 0;
+        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+        mem_access_subid.s.nmerge = 1;  /* Merging is allowed in this window. */
+        mem_access_subid.s.esr = 0;     /* Endian-swap for Reads. */
+        mem_access_subid.s.esw = 0;     /* Endian-swap for Writes. */
+        mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
+        mem_access_subid.s.nsw = 0;     /* Enable Snoop for Writes. */
+        mem_access_subid.s.ror = 0;     /* Disable Relaxed Ordering for Reads. */
+        mem_access_subid.s.row = 0;     /* Disable Relaxed Ordering for Writes. */
+        mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
+        cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(12), mem_access_subid.u64);
+    }
+    return 0;
+}
+
+
+/**
+ * Wait for posted PCIe read/writes to reach the other side of
+ * the internal PCIe switch. This will insure that core
+ * read/writes are posted before anything after this function
+ * is called. This may be necessary when writing to memory that
+ * will later be read using the DMA/PKT engines.
+ *
+ * @param pcie_port PCIe port to wait for
+ */
+void cvmx_pcie_wait_for_pending(int pcie_port)
+{
+    cvmx_npei_data_out_cnt_t npei_data_out_cnt;
+    int a;
+    int b;
+    int c;
+
+    /* See section 9.8, PCIe Core-initiated Requests, in the manual for a
+        description of how this code works */
+    npei_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DATA_OUT_CNT);
+    if (pcie_port)
+    {
+        if (!npei_data_out_cnt.s.p1_fcnt)
+            return;
+        a = npei_data_out_cnt.s.p1_ucnt;
+        b = (a + npei_data_out_cnt.s.p1_fcnt-1) & 0xffff;
+    }
+    else
+    {
+        if (!npei_data_out_cnt.s.p0_fcnt)
+            return;
+        a = npei_data_out_cnt.s.p0_ucnt;
+        b = (a + npei_data_out_cnt.s.p0_fcnt-1) & 0xffff;
+    }
+
+    while (1)
+    {
+        npei_data_out_cnt.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DATA_OUT_CNT);
+        c = (pcie_port) ? npei_data_out_cnt.s.p1_ucnt : npei_data_out_cnt.s.p0_ucnt;
+        if (a<=b)
+        {
+            if ((c<a) || (c>b))
+                return;
+        }
+        else
+        {
+            if ((c>b) && (c<a))
+                return;
+        }
+    }
+}
+
diff --git a/cvmx-pcie.h b/cvmx-pcie.h
new file mode 100644
index 0000000000000..56c108f4957fc
--- /dev/null
+++ b/cvmx-pcie.h
@@ -0,0 +1,304 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to PCIe as a host(RC) or target(EP)
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_PCIE_H__
+#define __CVMX_PCIE_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef union
+{
+    uint64_t    u64;
+    struct
+    {
+        uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
+        uint64_t    reserved_49_61  : 13;   /* Must be zero */
+        uint64_t    io              : 1;    /* 1 for IO space access */
+        uint64_t    did             : 5;    /* PCIe DID = 3 */
+        uint64_t    subdid          : 3;    /* PCIe SubDID = 1 */
+        uint64_t    reserved_36_39  : 4;    /* Must be zero */
+        uint64_t    es              : 2;    /* Endian swap = 1 */
+        uint64_t    port            : 2;    /* PCIe port 0,1 */
+        uint64_t    reserved_29_31  : 3;    /* Must be zero */
+        uint64_t    ty              : 1;    /* Selects the type of the configuration request (0 = type 0, 1 = type 1). */
+        uint64_t    bus             : 8;    /* Target bus number sent in the ID in the request. */
+        uint64_t    dev             : 5;    /* Target device number sent in the ID in the request. Note that Dev must be
+                                                zero for type 0 configuration requests. */
+        uint64_t    func            : 3;    /* Target function number sent in the ID in the request. */
+        uint64_t    reg             : 12;   /* Selects a register in the configuration space of the target. */
+    } config;
+    struct
+    {
+        uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
+        uint64_t    reserved_49_61  : 13;   /* Must be zero */
+        uint64_t    io              : 1;    /* 1 for IO space access */
+        uint64_t    did             : 5;    /* PCIe DID = 3 */
+        uint64_t    subdid          : 3;    /* PCIe SubDID = 2 */
+        uint64_t    reserved_36_39  : 4;    /* Must be zero */
+        uint64_t    es              : 2;    /* Endian swap = 1 */
+        uint64_t    port            : 2;    /* PCIe port 0,1 */
+        uint64_t    address         : 32;   /* PCIe IO address */
+    } io;
+    struct
+    {
+        uint64_t    upper           : 2;    /* Normally 2 for XKPHYS */
+        uint64_t    reserved_49_61  : 13;   /* Must be zero */
+        uint64_t    io              : 1;    /* 1 for IO space access */
+        uint64_t    did             : 5;    /* PCIe DID = 3 */
+        uint64_t    subdid          : 3;    /* PCIe SubDID = 3-6 */
+        uint64_t    reserved_36_39  : 4;    /* Must be zero */
+        uint64_t    address         : 36;   /* PCIe Mem address */
+    } mem;
+} cvmx_pcie_address_t;
+
+
+/**
+ * Return the Core virtual base address for PCIe IO access. IOs are
+ * read/written as an offset from this address.
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return 64bit Octeon IO base address for read/write
+ */
+uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
+
+/**
+ * Size of the IO address region returned at address
+ * cvmx_pcie_get_io_base_address()
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return Size of the IO window
+ */
+uint64_t cvmx_pcie_get_io_size(int pcie_port);
+
+/**
+ * Return the Core virtual base address for PCIe MEM access. Memory is
+ * read/written as an offset from this address.
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return 64bit Octeon IO base address for read/write
+ */
+uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
+
+/**
+ * Size of the Mem address region returned at address
+ * cvmx_pcie_get_mem_base_address()
+ *
+ * @param pcie_port PCIe port the IO is for
+ *
+ * @return Size of the Mem window
+ */
+uint64_t cvmx_pcie_get_mem_size(int pcie_port);
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ *
+ * @param pcie_port PCIe port to initialize
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_rc_initialize(int pcie_port);
+
+/**
+ * Shutdown a PCIe port and put it in reset
+ *
+ * @param pcie_port PCIe port to shutdown
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_rc_shutdown(int pcie_port);
+
+/**
+ * Read 8bits from a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return Result of the read
+ */
+uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg);
+
+/**
+ * Read 16bits from a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return Result of the read
+ */
+uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg);
+
+/**
+ * Read 32bits from a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ *
+ * @return Result of the read
+ */
+uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg);
+
+/**
+ * Write 8bits to a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ * @param val       Value to write
+ */
+void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val);
+
+/**
+ * Write 16bits to a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ * @param val       Value to write
+ */
+void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val);
+
+/**
+ * Write 32bits to a Device's config space
+ *
+ * @param pcie_port PCIe port the device is on
+ * @param bus       Sub bus
+ * @param dev       Device ID
+ * @param fn        Device sub function
+ * @param reg       Register to access
+ * @param val       Value to write
+ */
+void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val);
+
+/**
+ * Read a PCIe config space register indirectly. This is used for
+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
+ *
+ * @param pcie_port  PCIe port to read from
+ * @param cfg_offset Address to read
+ *
+ * @return Value read
+ */
+uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
+
+/**
+ * Write a PCIe config space register indirectly. This is used for
+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
+ *
+ * @param pcie_port  PCIe port to write to
+ * @param cfg_offset Address to write
+ * @param val        Value to write
+ */
+void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
+
+/**
+ * Write a 32bit value to the Octeon NPEI register space
+ *
+ * @param address Address to write to
+ * @param val     Value to write
+ */
+static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
+{
+	cvmx_write64_uint32(address ^ 4, val);
+	cvmx_read64_uint32(address ^ 4);
+}
+
+/**
+ * Read a 32bit value from the Octeon NPEI register space
+ *
+ * @param address Address to read
+ * @return The result
+ */
+static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
+{
+	return cvmx_read64_uint32(address ^ 4);
+}
+
+/**
+ * Initialize a PCIe port for use in target(EP) mode.
+ *
+ * @return Zero on success
+ */
+int cvmx_pcie_ep_initialize(void);
+
+/**
+ * Wait for posted PCIe read/writes to reach the other side of
+ * the internal PCIe switch. This will insure that core
+ * read/writes are posted before anything after this function
+ * is called. This may be necessary when writing to memory that
+ * will later be read using the DMA/PKT engines.
+ *
+ * @param pcie_port PCIe port to wait for
+ */
+void cvmx_pcie_wait_for_pending(int pcie_port);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
diff --git a/cvmx-pip.h b/cvmx-pip.h
new file mode 100644
index 0000000000000..8dabca79542dc
--- /dev/null
+++ b/cvmx-pip.h
@@ -0,0 +1,475 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Packet Input Processing unit.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+#ifndef __CVMX_PIP_H__
+#define __CVMX_PIP_H__
+
+#include "cvmx-wqe.h"
+#include "cvmx-fpa.h"
+#ifndef CVMX_DONT_INCLUDE_CONFIG
+#include "executive-config.h"
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_PIP_NUM_INPUT_PORTS                40
+#define CVMX_PIP_NUM_WATCHERS                   4
+
+
+
+
+
+
+
+//
+// Encodes the different error and exception codes
+//
+typedef enum
+{
+    CVMX_PIP_L4_NO_ERR       = 0ull,
+    //        1  = TCP (UDP) packet not long enough to cover TCP (UDP) header
+    CVMX_PIP_L4_MAL_ERR     = 1ull,
+    //        2  = TCP/UDP checksum failure
+    CVMX_PIP_CHK_ERR        = 2ull,
+    //        3  = TCP/UDP length check (TCP/UDP length does not match IP length)
+    CVMX_PIP_L4_LENGTH_ERR  = 3ull,
+    //        4  = illegal TCP/UDP port (either source or dest port is zero)
+    CVMX_PIP_BAD_PRT_ERR    = 4ull,
+    //        8  = TCP flags = FIN only
+    CVMX_PIP_TCP_FLG8_ERR   = 8ull,
+    //        9  = TCP flags = 0
+    CVMX_PIP_TCP_FLG9_ERR   = 9ull,
+    //        10 = TCP flags = FIN+RST+*
+    CVMX_PIP_TCP_FLG10_ERR  = 10ull,
+    //        11 = TCP flags = SYN+URG+*
+    CVMX_PIP_TCP_FLG11_ERR  = 11ull,
+    //        12 = TCP flags = SYN+RST+*
+    CVMX_PIP_TCP_FLG12_ERR  = 12ull,
+    //        13 = TCP flags = SYN+FIN+*
+    CVMX_PIP_TCP_FLG13_ERR  = 13ull
+} cvmx_pip_l4_err_t;
+
+typedef enum
+{
+
+    CVMX_PIP_IP_NO_ERR      = 0ull,
+    //        1 = not IPv4 or IPv6
+    CVMX_PIP_NOT_IP        = 1ull,
+    //        2 = IPv4 header checksum violation
+    CVMX_PIP_IPV4_HDR_CHK  = 2ull,
+    //        3 = malformed (packet not long enough to cover IP hdr)
+    CVMX_PIP_IP_MAL_HDR    = 3ull,
+    //        4 = malformed (packet not long enough to cover len in IP hdr)
+    CVMX_PIP_IP_MAL_PKT    = 4ull,
+    //        5 = TTL / hop count equal zero
+    CVMX_PIP_TTL_HOP       = 5ull,
+    //        6 = IPv4 options / IPv6 early extension headers
+    CVMX_PIP_OPTS          = 6ull
+} cvmx_pip_ip_exc_t;
+
+
+/**
+ * NOTES
+ *       late collision (data received before collision)
+ *            late collisions cannot be detected by the receiver
+ *            they would appear as JAM bits which would appear as bad FCS
+ *            or carrier extend error which is CVMX_PIP_EXTEND_ERR
+ */
+typedef enum
+{
+    /**
+     * No error
+     */
+    CVMX_PIP_RX_NO_ERR      = 0ull,
+
+    CVMX_PIP_PARTIAL_ERR   = 1ull,  // RGM+SPI            1 = partially received packet (buffering/bandwidth not adequate)
+    CVMX_PIP_JABBER_ERR    = 2ull,  // RGM+SPI            2 = receive packet too large and truncated
+    CVMX_PIP_OVER_FCS_ERR  = 3ull,  // RGM                3 = max frame error (pkt len > max frame len) (with FCS error)
+    CVMX_PIP_OVER_ERR      = 4ull,  // RGM+SPI            4 = max frame error (pkt len > max frame len)
+    CVMX_PIP_ALIGN_ERR     = 5ull,  // RGM                5 = nibble error (data not byte multiple - 100M and 10M only)
+    CVMX_PIP_UNDER_FCS_ERR = 6ull,  // RGM                6 = min frame error (pkt len < min frame len) (with FCS error)
+    CVMX_PIP_GMX_FCS_ERR   = 7ull,  // RGM                7 = FCS error
+    CVMX_PIP_UNDER_ERR     = 8ull,  // RGM+SPI            8 = min frame error (pkt len < min frame len)
+    CVMX_PIP_EXTEND_ERR    = 9ull,  // RGM                9 = Frame carrier extend error
+    CVMX_PIP_LENGTH_ERR    = 10ull, // RGM               10 = length mismatch (len did not match len in L2 length/type)
+    CVMX_PIP_DAT_ERR       = 11ull, // RGM               11 = Frame error (some or all data bits marked err)
+    CVMX_PIP_DIP_ERR       = 11ull, //     SPI           11 = DIP4 error
+    CVMX_PIP_SKIP_ERR      = 12ull, // RGM               12 = packet was not large enough to pass the skipper - no inspection could occur
+    CVMX_PIP_NIBBLE_ERR    = 13ull, // RGM               13 = studder error (data not repeated - 100M and 10M only)
+    CVMX_PIP_PIP_FCS       = 16L, // RGM+SPI           16 = FCS error
+    CVMX_PIP_PIP_SKIP_ERR  = 17L, // RGM+SPI+PCI       17 = packet was not large enough to pass the skipper - no inspection could occur
+    CVMX_PIP_PIP_L2_MAL_HDR= 18L  // RGM+SPI+PCI       18 = malformed l2 (packet not long enough to cover L2 hdr)
+    // NOTES
+                                              //       xx = late collision (data received before collision)
+                                              //            late collisions cannot be detected by the receiver
+                                              //            they would appear as JAM bits which would appear as bad FCS
+                                              //            or carrier extend error which is CVMX_PIP_EXTEND_ERR
+
+
+
+} cvmx_pip_rcv_err_t;
+
+/**
+ * This defines the err_code field errors in the work Q entry
+ */
+typedef union
+{
+    cvmx_pip_l4_err_t  l4_err;
+    cvmx_pip_ip_exc_t  ip_exc;
+    cvmx_pip_rcv_err_t rcv_err;
+} cvmx_pip_err_t;
+
+
+/**
+ * Status statistics for a port
+ */
+typedef struct
+{
+    uint32_t    dropped_octets;         /**< Inbound octets marked to be dropped by the IPD */
+    uint32_t    dropped_packets;        /**< Inbound packets marked to be dropped by the IPD */
+    uint32_t    pci_raw_packets;        /**< RAW PCI Packets received by PIP per port */
+    uint32_t    octets;                 /**< Number of octets processed by PIP */
+    uint32_t    packets;                /**< Number of packets processed by PIP */
+    uint32_t    multicast_packets;      /**< Number of indentified L2 multicast packets.
+                                            Does not include broadcast packets.
+                                            Only includes packets whose parse mode is
+                                            SKIP_TO_L2 */
+    uint32_t    broadcast_packets;      /**< Number of indentified L2 broadcast packets.
+                                            Does not include multicast packets.
+                                            Only includes packets whose parse mode is
+                                            SKIP_TO_L2 */
+    uint32_t    len_64_packets;         /**< Number of 64B packets */
+    uint32_t    len_65_127_packets;     /**< Number of 65-127B packets */
+    uint32_t    len_128_255_packets;    /**< Number of 128-255B packets */
+    uint32_t    len_256_511_packets;    /**< Number of 256-511B packets */
+    uint32_t    len_512_1023_packets;   /**< Number of 512-1023B packets */
+    uint32_t    len_1024_1518_packets;  /**< Number of 1024-1518B packets */
+    uint32_t    len_1519_max_packets;   /**< Number of 1519-max packets */
+    uint32_t    fcs_align_err_packets;  /**< Number of packets with FCS or Align opcode errors */
+    uint32_t    runt_packets;           /**< Number of packets with length < min */
+    uint32_t    runt_crc_packets;       /**< Number of packets with length < min and FCS error */
+    uint32_t    oversize_packets;       /**< Number of packets with length > max */
+    uint32_t    oversize_crc_packets;   /**< Number of packets with length > max and FCS error */
+    uint32_t    inb_packets;            /**< Number of packets without GMX/SPX/PCI errors received by PIP */
+    uint64_t    inb_octets;             /**< Total number of octets from all packets received by PIP, including CRC */
+    uint16_t    inb_errors;             /**< Number of packets with GMX/SPX/PCI errors received by PIP */
+} cvmx_pip_port_status_t;
+
+
+/**
+ * Definition of the PIP custom header that can be prepended
+ * to a packet by external hardware.
+ */
+typedef union
+{
+    uint64_t    u64;
+    struct
+    {
+        uint64_t                    rawfull     : 1;    /**< Documented as R - Set if the Packet is RAWFULL. If set,
+                                                            this header must be the full 8 bytes */
+        uint64_t                    reserved0   : 5;    /**< Must be zero */
+        cvmx_pip_port_parse_mode_t  parse_mode  : 2;    /**< PIP parse mode for this packet */
+        uint64_t                    reserved1   : 1;    /**< Must be zero */
+        uint64_t                    skip_len    : 7;    /**< Skip amount, including this header, to the beginning of the packet */
+        uint64_t                    reserved2   : 6;    /**< Must be zero */
+        uint64_t                    qos         : 3;    /**< POW input queue for this packet */
+        uint64_t                    grp         : 4;    /**< POW input group for this packet */
+        uint64_t                    rs          : 1;    /**< Flag to store this packet in the work queue entry, if possible */
+        cvmx_pow_tag_type_t         tag_type    : 2;    /**< POW input tag type */
+        uint64_t                    tag         : 32;   /**< POW input tag */
+    } s;
+} cvmx_pip_pkt_inst_hdr_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Configure an ethernet input port
+ *
+ * @param port_num Port number to configure
+ * @param port_cfg Port hardware configuration
+ * @param port_tag_cfg
+ *                 Port POW tagging configuration
+ */
+static inline void cvmx_pip_config_port(uint64_t port_num,
+                                        cvmx_pip_port_cfg_t port_cfg,
+                                        cvmx_pip_port_tag_cfg_t port_tag_cfg)
+{
+    cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
+    cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
+}
+
+
+/**
+ * @deprecated      This function is a thin wrapper around the Pass1 version
+ *                  of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
+ *                  setting the group that is incompatible with this function,
+ *                  the preferred upgrade path is to use the CSR directly.
+ *
+ * Configure the global QoS packet watchers. Each watcher is
+ * capable of matching a field in a packet to determine the
+ * QoS queue for scheduling.
+ *
+ * @param watcher    Watcher number to configure (0 - 3).
+ * @param match_type Watcher match type
+ * @param match_value
+ *                   Value the watcher will match against
+ * @param qos        QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_watcher(uint64_t watcher,
+                                           cvmx_pip_qos_watch_types match_type,
+                                           uint64_t match_value, uint64_t qos)
+{
+    cvmx_pip_port_watcher_cfg_t watcher_config;
+
+    watcher_config.u64 = 0;
+    watcher_config.s.match_type = match_type;
+    watcher_config.s.match_value = match_value;
+    watcher_config.s.qos = qos;
+
+    cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
+}
+
+
+/**
+ * Configure the VLAN priority to QoS queue mapping.
+ *
+ * @param vlan_priority
+ *               VLAN priority (0-7)
+ * @param qos    QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos)
+{
+    cvmx_pip_qos_vlanx_t pip_qos_vlanx;
+    pip_qos_vlanx.u64 = 0;
+    pip_qos_vlanx.s.qos = qos;
+    cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
+}
+
+
+/**
+ * Configure the Diffserv to QoS queue mapping.
+ *
+ * @param diffserv Diffserv field value (0-63)
+ * @param qos      QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
+{
+    cvmx_pip_qos_diffx_t pip_qos_diffx;
+    pip_qos_diffx.u64 = 0;
+    pip_qos_diffx.s.qos = qos;
+    cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
+}
+
+
+/**
+ * Get the status counters for a port.
+ *
+ * @param port_num Port number to get statistics for.
+ * @param clear    Set to 1 to clear the counters after they are read
+ * @param status   Where to put the results.
+ */
+static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pip_port_status_t *status)
+{
+    cvmx_pip_stat_ctl_t pip_stat_ctl;
+    cvmx_pip_stat0_prtx_t stat0;
+    cvmx_pip_stat1_prtx_t stat1;
+    cvmx_pip_stat2_prtx_t stat2;
+    cvmx_pip_stat3_prtx_t stat3;
+    cvmx_pip_stat4_prtx_t stat4;
+    cvmx_pip_stat5_prtx_t stat5;
+    cvmx_pip_stat6_prtx_t stat6;
+    cvmx_pip_stat7_prtx_t stat7;
+    cvmx_pip_stat8_prtx_t stat8;
+    cvmx_pip_stat9_prtx_t stat9;
+    cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
+    cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
+    cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
+
+    pip_stat_ctl.u64 = 0;
+    pip_stat_ctl.s.rdclr = clear;
+    cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
+
+    stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
+    stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
+    stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
+    stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
+    stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
+    stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
+    stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
+    stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
+    stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
+    stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+    pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
+    pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
+    pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
+
+    status->dropped_octets          = stat0.s.drp_octs;
+    status->dropped_packets         = stat0.s.drp_pkts;
+    status->octets                  = stat1.s.octs;
+    status->pci_raw_packets         = stat2.s.raw;
+    status->packets                 = stat2.s.pkts;
+    status->multicast_packets       = stat3.s.mcst;
+    status->broadcast_packets       = stat3.s.bcst;
+    status->len_64_packets          = stat4.s.h64;
+    status->len_65_127_packets      = stat4.s.h65to127;
+    status->len_128_255_packets     = stat5.s.h128to255;
+    status->len_256_511_packets     = stat5.s.h256to511;
+    status->len_512_1023_packets    = stat6.s.h512to1023;
+    status->len_1024_1518_packets   = stat6.s.h1024to1518;
+    status->len_1519_max_packets    = stat7.s.h1519;
+    status->fcs_align_err_packets   = stat7.s.fcs;
+    status->runt_packets            = stat8.s.undersz;
+    status->runt_crc_packets        = stat8.s.frag;
+    status->oversize_packets        = stat9.s.oversz;
+    status->oversize_crc_packets    = stat9.s.jabber;
+    status->inb_packets             = pip_stat_inb_pktsx.s.pkts;
+    status->inb_octets              = pip_stat_inb_octsx.s.octs;
+    status->inb_errors              = pip_stat_inb_errsx.s.errs;
+
+    if (cvmx_octeon_is_pass1())
+    {
+        /* Kludge to fix Octeon Pass 1 errata - Drop counts don't work */
+        if (status->inb_packets > status->packets)
+            status->dropped_packets = status->inb_packets - status->packets;
+        else
+            status->dropped_packets = 0;
+        if (status->inb_octets - status->inb_packets*4 > status->octets)
+            status->dropped_octets = status->inb_octets - status->inb_packets*4 - status->octets;
+        else
+            status->dropped_octets = 0;
+    }
+}
+
+
+/**
+ * Configure the hardware CRC engine
+ *
+ * @param interface Interface to configure (0 or 1)
+ * @param invert_result
+ *                 Invert the result of the CRC
+ * @param reflect  Reflect
+ * @param initialization_vector
+ *                 CRC initialization vector
+ */
+static inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, uint32_t initialization_vector)
+{
+    if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+    {
+        cvmx_pip_crc_ctlx_t config;
+        cvmx_pip_crc_ivx_t pip_crc_ivx;
+
+        config.u64 = 0;
+        config.s.invres = invert_result;
+        config.s.reflect = reflect;
+        cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
+
+        pip_crc_ivx.u64 = 0;
+        pip_crc_ivx.s.iv = initialization_vector;
+        cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
+    }
+}
+
+
+/**
+ * Clear all bits in a tag mask. This should be called on
+ * startup before any calls to cvmx_pip_tag_mask_set. Each bit
+ * set in the final mask represent a byte used in the packet for
+ * tag generation.
+ *
+ * @param mask_index Which tag mask to clear (0..3)
+ */
+static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
+{
+    uint64_t index;
+    cvmx_pip_tag_incx_t pip_tag_incx;
+    pip_tag_incx.u64 = 0;
+    pip_tag_incx.s.en = 0;
+    for (index=mask_index*16; index<(mask_index+1)*16; index++)
+        cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
+}
+
+
+/**
+ * Sets a range of bits in the tag mask. The tag mask is used
+ * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
+ * There are four separate masks that can be configured.
+ *
+ * @param mask_index Which tag mask to modify (0..3)
+ * @param offset     Offset into the bitmask to set bits at. Use the GCC macro
+ *                   offsetof() to determine the offsets into packet headers.
+ *                   For example, offsetof(ethhdr, protocol) returns the offset
+ *                   of the ethernet protocol field.  The bitmask selects which bytes
+ *                   to include the the tag, with bit offset X selecting byte at offset X
+ *                   from the beginning of the packet data.
+ * @param len        Number of bytes to include. Usually this is the sizeof()
+ *                   the field.
+ */
+static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len)
+{
+    while (len--)
+    {
+        cvmx_pip_tag_incx_t pip_tag_incx;
+        uint64_t index = mask_index*16 + offset/8;
+        pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
+        pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
+        cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
+        offset++;
+    }
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /*  __CVMX_PIP_H__ */
diff --git a/cvmx-pko.c b/cvmx-pko.c
new file mode 100644
index 0000000000000..cbdfa9fb8727c
--- /dev/null
+++ b/cvmx-pko.c
@@ -0,0 +1,466 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the hardware Packet Output unit.
+ *
+ * <hr>$Revision: 42150 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-pko.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-helper.h"
+
+/**
+ * Internal state of packet output
+ */
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+/**
+ * Call before any other calls to initialize the packet
+ * output system.  This does chip global config, and should only be
+ * done by one core.
+ */
+
+void cvmx_pko_initialize_global(void)
+{
+    int i;
+    uint64_t priority = 8;
+    cvmx_pko_pool_cfg_t config;
+
+    /* Set the size of the PKO command buffers to an odd number of 64bit
+        words. This allows the normal two word send to stay aligned and never
+        span a comamnd word buffer. */
+    config.u64 = 0;
+    config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
+    config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
+
+    cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
+
+    for (i=0; i<CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
+        cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, &priority);
+
+    /* If we aren't using all of the queues optimize PKO's internal memory */
+    if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+    {
+        int num_interfaces = cvmx_helper_get_number_of_interfaces();
+        int last_port = cvmx_helper_get_last_ipd_port(num_interfaces-1);
+        int max_queues = cvmx_pko_get_base_queue(last_port) + cvmx_pko_get_num_queues(last_port);
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+        {
+            if (max_queues <= 32)
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
+            else if (max_queues <= 64)
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
+        }
+        else
+        {
+            if (max_queues <= 64)
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
+            else if (max_queues <= 128)
+                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
+        }
+    }
+}
+
+/**
+ * This function does per-core initialization required by the PKO routines.
+ * This must be called on all cores that will do packet output, and must
+ * be called after the FPA has been initialized and filled with pages.
+ *
+ * @return 0 on success
+ *         !0 on failure
+ */
+int cvmx_pko_initialize_local(void)
+{
+    /* Nothing to do */
+    return 0;
+}
+#endif
+
+/**
+ * Enables the packet output hardware. It must already be
+ * configured.
+ */
+void cvmx_pko_enable(void)
+{
+    cvmx_pko_reg_flags_t flags;
+
+    flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
+    if (flags.s.ena_pko)
+        cvmx_dprintf("Warning: Enabling PKO when PKO already enabled.\n");
+
+    flags.s.ena_dwb = 1;
+    flags.s.ena_pko = 1;
+    flags.s.store_be =1;  /* always enable big endian for 3-word command. Does nothing for 2-word */ 
+    cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
+}
+
+
+/**
+ * Disables the packet output. Does not affect any configuration.
+ */
+void cvmx_pko_disable(void)
+{
+    cvmx_pko_reg_flags_t pko_reg_flags;
+    pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
+    pko_reg_flags.s.ena_pko = 0;
+    cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
+}
+
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/**
+ * @INTERNAL
+ * Reset the packet output.
+ */
+static void __cvmx_pko_reset(void)
+{
+    cvmx_pko_reg_flags_t pko_reg_flags;
+    pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
+    pko_reg_flags.s.reset = 1;
+    cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
+}
+
+
+/**
+ * Shutdown and free resources required by packet output.
+ */
+void cvmx_pko_shutdown(void)
+{
+    cvmx_pko_queue_cfg_t config;
+    int queue;
+
+    cvmx_pko_disable();
+
+    for (queue=0; queue<CVMX_PKO_MAX_OUTPUT_QUEUES; queue++)
+    {
+        config.u64          = 0;
+        config.s.tail       = 1;
+        config.s.index      = 0;
+        config.s.port       = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
+        config.s.queue      = queue & 0x7f;
+        config.s.qos_mask   = 0;
+        config.s.buf_ptr    = 0;
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        {
+            cvmx_pko_reg_queue_ptrs1_t config1;
+            config1.u64 = 0;
+            config1.s.qid7 = queue >> 7;
+            cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
+        }
+        cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
+        cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
+    }
+    __cvmx_pko_reset();
+}
+
+
+/**
+ * Configure a output port and the associated queues for use.
+ *
+ * @param port       Port to configure.
+ * @param base_queue First queue number to associate with this port.
+ * @param num_queues Number of queues to associate with this port
+ * @param priority   Array of priority levels for each queue. Values are
+ *                   allowed to be 0-8. A value of 8 get 8 times the traffic
+ *                   of a value of 1.  A value of 0 indicates that no rounds
+ *                   will be participated in. These priorities can be changed
+ *                   on the fly while the pko is enabled. A priority of 9
+ *                   indicates that static priority should be used.  If static
+ *                   priority is used all queues with static priority must be
+ *                   contiguous starting at the base_queue, and lower numbered
+ *                   queues have higher priority than higher numbered queues.
+ *                   There must be num_queues elements in the array.
+ */
+cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[])
+{
+    cvmx_pko_status_t          result_code;
+    uint64_t                   queue;
+    cvmx_pko_queue_cfg_t       config;
+    cvmx_pko_reg_queue_ptrs1_t config1;
+    int static_priority_base = -1;
+    int static_priority_end = -1;
+
+
+    if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID))
+    {
+        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", (unsigned long long)port);
+        return CVMX_PKO_INVALID_PORT;
+    }
+
+    if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES)
+    {
+        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", (unsigned long long)(base_queue + num_queues));
+        return CVMX_PKO_INVALID_QUEUE;
+    }
+
+    if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
+    {
+        /* Validate the static queue priority setup and set static_priority_base and static_priority_end
+        ** accordingly. */
+        for (queue = 0; queue < num_queues; queue++)
+        {
+            /* Find first queue of static priority */
+            if (static_priority_base == -1 && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
+                static_priority_base = queue;
+            /* Find last queue of static priority */
+            if (static_priority_base != -1 && static_priority_end == -1 && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY && queue)
+                static_priority_end = queue - 1;
+            else if (static_priority_base != -1 && static_priority_end == -1 && queue == num_queues - 1)
+                static_priority_end = queue;  /* all queues are static priority */
+            /* Check to make sure all static priority queues are contiguous.  Also catches some cases of
+            ** static priorites not starting at queue 0. */
+            if (static_priority_end != -1 && (int)queue > static_priority_end && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
+            {
+                cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d\n", (int)queue, static_priority_end);
+                return CVMX_PKO_INVALID_PRIORITY;
+            }
+        }
+        if (static_priority_base > 0)
+        {
+            cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues don't start at base queue. sq: %d\n", static_priority_base);
+            return CVMX_PKO_INVALID_PRIORITY;
+        }
+#if 0
+        cvmx_dprintf("Port %d: Static priority queue base: %d, end: %d\n", port, static_priority_base, static_priority_end);
+#endif
+    }
+    /* At this point, static_priority_base and static_priority_end are either both -1,
+    ** or are valid start/end queue numbers */
+
+    result_code = CVMX_PKO_SUCCESS;
+
+#ifdef PKO_DEBUG
+    cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
+#endif
+
+    for (queue = 0; queue < num_queues; queue++)
+    {
+        uint64_t  *buf_ptr = NULL;
+
+        config1.u64         = 0;
+        config1.s.idx3      = queue >> 3;
+        config1.s.qid7      = (base_queue + queue) >> 7;
+
+        config.u64          = 0;
+        config.s.tail       = queue == (num_queues - 1);
+        config.s.index      = queue;
+        config.s.port       = port;
+        config.s.queue      = base_queue + queue;
+
+        if (!cvmx_octeon_is_pass1())
+        {
+            config.s.static_p   = static_priority_base >= 0;
+            config.s.static_q   = (int)queue <= static_priority_end;
+            config.s.s_tail     = (int)queue == static_priority_end;
+        }
+        /* Convert the priority into an enable bit field. Try to space the bits
+            out evenly so the packet don't get grouped up */
+        switch ((int)priority[queue])
+        {
+            case 0: config.s.qos_mask = 0x00; break;
+            case 1: config.s.qos_mask = 0x01; break;
+            case 2: config.s.qos_mask = 0x11; break;
+            case 3: config.s.qos_mask = 0x49; break;
+            case 4: config.s.qos_mask = 0x55; break;
+            case 5: config.s.qos_mask = 0x57; break;
+            case 6: config.s.qos_mask = 0x77; break;
+            case 7: config.s.qos_mask = 0x7f; break;
+            case 8: config.s.qos_mask = 0xff; break;
+            case CVMX_PKO_QUEUE_STATIC_PRIORITY:
+                if (!cvmx_octeon_is_pass1()) /* Pass 1 will fall through to the error case */
+                {
+                    config.s.qos_mask = 0xff;
+                    break;
+                }
+            default:
+                cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n", (unsigned long long)priority[queue]);
+                config.s.qos_mask = 0xff;
+                result_code = CVMX_PKO_INVALID_PRIORITY;
+                break;
+        }
+
+        if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
+        {
+            cvmx_cmd_queue_result_t cmd_res = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO(base_queue + queue),
+                                                                        CVMX_PKO_MAX_QUEUE_DEPTH,
+                                                                        CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                                                        CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST*8);
+            if (cmd_res != CVMX_CMD_QUEUE_SUCCESS)
+            {
+	        switch (cmd_res) 
+		{
+		    case CVMX_CMD_QUEUE_NO_MEMORY:
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Unable to allocate output buffer.\n");
+                        return(CVMX_PKO_NO_MEMORY);
+		    case CVMX_CMD_QUEUE_ALREADY_SETUP:
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Port already setup.\n");
+                        return(CVMX_PKO_PORT_ALREADY_SETUP);
+		    case CVMX_CMD_QUEUE_INVALID_PARAM:
+		    default:
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
+                        return(CVMX_PKO_CMD_QUEUE_INIT_ERROR);
+		}
+            }
+
+            buf_ptr = (uint64_t*)cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO(base_queue + queue));
+            config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
+        }
+        else
+            config.s.buf_ptr = 0;
+
+        CVMX_SYNCWS;
+
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        {
+            cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
+        }
+        cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
+    }
+
+    return result_code;
+}
+
+#ifdef PKO_DEBUG
+/**
+ * Show map of ports -> queues for different cores.
+ */
+void cvmx_pko_show_queue_map()
+{
+    int core, port;
+    int pko_output_ports = 36;
+
+    cvmx_dprintf("port");
+    for(port=0; port<pko_output_ports; port++)
+        cvmx_dprintf("%3d ", port);
+    cvmx_dprintf("\n");
+
+    for(core=0; core<CVMX_MAX_CORES; core++)
+    {
+        cvmx_dprintf("\n%2d: ", core);
+        for(port=0; port<pko_output_ports; port++)
+        {
+            cvmx_dprintf("%3d ", cvmx_pko_get_base_queue_per_core(port, core));
+        }
+    }
+    cvmx_dprintf("\n");
+}
+#endif
+
+
+/**
+ * Rate limit a PKO port to a max packets/sec. This function is only
+ * supported on CN51XX and higher, excluding CN58XX.
+ *
+ * @param port      Port to rate limit
+ * @param packets_s Maximum packet/sec
+ * @param burst     Maximum number of packets to burst in a row before rate
+ *                  limiting cuts in.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
+{
+    cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
+    cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
+
+    pko_mem_port_rate0.u64 = 0;
+    pko_mem_port_rate0.s.pid = port;
+    pko_mem_port_rate0.s.rate_pkt = cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16;
+    /* No cost per word since we are limited by packets/sec, not bits/sec */
+    pko_mem_port_rate0.s.rate_word = 0;
+
+    pko_mem_port_rate1.u64 = 0;
+    pko_mem_port_rate1.s.pid = port;
+    pko_mem_port_rate1.s.rate_lim = ((uint64_t)pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
+
+    cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
+    cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
+    return 0;
+}
+
+
+/**
+ * Rate limit a PKO port to a max bits/sec. This function is only
+ * supported on CN51XX and higher, excluding CN58XX.
+ *
+ * @param port   Port to rate limit
+ * @param bits_s PKO rate limit in bits/sec
+ * @param burst  Maximum number of bits to burst before rate
+ *               limiting cuts in.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
+{
+    cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
+    cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
+    uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz;
+    uint64_t tokens_per_bit = clock_rate*16 / bits_s;
+
+    pko_mem_port_rate0.u64 = 0;
+    pko_mem_port_rate0.s.pid = port;
+    /* Each packet has a 12 bytes of interframe gap, an 8 byte preamble, and a
+        4 byte CRC. These are not included in the per word count. Multiply
+        by 8 to covert to bits and divide by 256 for limit granularity */
+    pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
+    /* Each 8 byte word has 64bits */
+    pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
+
+    pko_mem_port_rate1.u64 = 0;
+    pko_mem_port_rate1.s.pid = port;
+    pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
+
+    cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
+    cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
+    return 0;
+}
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
diff --git a/cvmx-pko.h b/cvmx-pko.h
new file mode 100644
index 0000000000000..906f0f877960a
--- /dev/null
+++ b/cvmx-pko.h
@@ -0,0 +1,564 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Packet Output unit.
+ *
+ * Starting with SDK 1.7.0, the PKO output functions now support
+ * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
+ * function similarly to previous SDKs by using POW atomic tags
+ * to preserve ordering and exclusivity. As a new option, you
+ * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
+ * memory based locking instead. This locking has the advantage
+ * of not affecting the tag state but doesn't preserve packet
+ * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
+ * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
+ * with hand tuned fast path code.
+ *
+ * Some of other SDK differences visible to the command command
+ * queuing:
+ * - PKO indexes are no longer stored in the FAU. A large
+ *   percentage of the FAU register block used to be tied up
+ *   maintaining PKO queue pointers. These are now stored in a
+ *   global named block.
+ * - The PKO <b>use_locking</b> parameter can now have a global
+ *   effect. Since all application use the same named block,
+ *   queue locking correctly applies across all operating
+ *   systems when using CVMX_PKO_LOCK_CMD_QUEUE.
+ * - PKO 3 word commands are now supported. Use
+ *   cvmx_pko_send_packet_finish3().
+ *
+ * <hr>$Revision: 42150 $<hr>
+ */
+
+
+#ifndef __CVMX_PKO_H__
+#define __CVMX_PKO_H__
+
+#ifndef CVMX_DONT_INCLUDE_CONFIG
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+#include "cvmx-config.h"
+#endif
+#endif
+
+#include "cvmx-cvmmem.h"
+#include "cvmx-fau.h"
+#include "cvmx-fpa.h"
+#include "cvmx-pow.h"
+#include "cvmx-cmd-queue.h"
+
+/* Adjust the command buffer size by 1 word so that in the case of using only
+** two word PKO commands no command words stradle buffers.  The useful values
+** for this are 0 and 1. */
+#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
+#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
+#define CVMX_PKO_NUM_OUTPUT_PORTS       40
+#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 // use this for queues that are not used
+#define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
+#define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
+#define CVMX_PKO_MAX_QUEUE_DEPTH 0
+
+typedef enum
+{
+    CVMX_PKO_SUCCESS,
+    CVMX_PKO_INVALID_PORT,
+    CVMX_PKO_INVALID_QUEUE,
+    CVMX_PKO_INVALID_PRIORITY,
+    CVMX_PKO_NO_MEMORY,
+    CVMX_PKO_PORT_ALREADY_SETUP,
+    CVMX_PKO_CMD_QUEUE_INIT_ERROR
+} cvmx_pko_status_t;
+
+/**
+ * This enumeration represents the differnet locking modes supported by PKO.
+ */
+typedef enum
+{
+    CVMX_PKO_LOCK_NONE = 0,         /**< PKO doesn't do any locking. It is the responsibility
+                                        of the application to make sure that no other core is
+                                        accessing the same queue at the smae time */
+    CVMX_PKO_LOCK_ATOMIC_TAG = 1,   /**< PKO performs an atomic tagswitch to insure exclusive
+                                        access to the output queue. This will maintain
+                                        packet ordering on output */
+    CVMX_PKO_LOCK_CMD_QUEUE = 2,    /**< PKO uses the common command queue locks to insure
+                                        exclusive access to the output queue. This is a memory
+                                        based ll/sc. This is the most portable locking
+                                        mechanism */
+} cvmx_pko_lock_t;
+
+typedef struct
+{
+    uint32_t    packets;
+    uint64_t    octets;
+  uint64_t doorbell;
+} cvmx_pko_port_status_t;
+
+/**
+ * This structure defines the address to use on a packet enqueue
+ */
+typedef union
+{
+    uint64_t                u64;
+    struct
+    {
+        cvmx_mips_space_t   mem_space   : 2;    /**< Must CVMX_IO_SEG */
+        uint64_t            reserved    :13;    /**< Must be zero */
+        uint64_t            is_io       : 1;    /**< Must be one */
+        uint64_t            did         : 8;    /**< The ID of the device on the non-coherent bus */
+        uint64_t            reserved2   : 4;    /**< Must be zero */
+        uint64_t            reserved3   :18;    /**< Must be zero */
+        uint64_t            port        : 6;    /**< The hardware likes to have the output port in addition to the output queue */
+        uint64_t            queue       : 9;    /**< The output queue to send the packet to (0-127 are legal) */
+        uint64_t            reserved4   : 3;    /**< Must be zero */
+   } s;
+} cvmx_pko_doorbell_address_t;
+
+/**
+ * Structure of the first packet output command word.
+ */
+typedef union
+{
+    uint64_t                u64;
+    struct
+    {
+        cvmx_fau_op_size_t  size1       : 2; /**< The size of the reg1 operation - could be 8, 16, 32, or 64 bits */
+        cvmx_fau_op_size_t  size0       : 2; /**< The size of the reg0 operation - could be 8, 16, 32, or 64 bits */
+        uint64_t            subone1     : 1; /**< If set, subtract 1, if clear, subtract packet size */
+        uint64_t            reg1        :11; /**< The register, subtract will be done if reg1 is non-zero */
+        uint64_t            subone0     : 1; /**< If set, subtract 1, if clear, subtract packet size */
+        uint64_t            reg0        :11; /**< The register, subtract will be done if reg0 is non-zero */
+        uint64_t            le          : 1; /**< When set, interpret segment pointer and segment bytes in little endian order */
+        uint64_t            n2          : 1; /**< When set, packet data not allocated in L2 cache by PKO */
+        uint64_t            wqp         : 1; /**< If set and rsp is set, word3 contains a pointer to a work queue entry */
+        uint64_t            rsp         : 1; /**< If set, the hardware will send a response when done */
+        uint64_t            gather      : 1; /**< If set, the supplied pkt_ptr is really a pointer to a list of pkt_ptr's */
+        uint64_t            ipoffp1     : 7; /**< If ipoffp1 is non zero, (ipoffp1-1) is the number of bytes to IP header,
+                                                and the hardware will calculate and insert the  UDP/TCP checksum */
+        uint64_t            ignore_i    : 1; /**< If set, ignore the I bit (force to zero) from all pointer structures */
+        uint64_t            dontfree    : 1; /**< If clear, the hardware will attempt to free the buffers containing the packet */
+        uint64_t            segs        : 6; /**< The total number of segs in the packet, if gather set, also gather list length */
+        uint64_t            total_bytes :16; /**< Including L2, but no trailing CRC */
+    } s;
+} cvmx_pko_command_word0_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Definition of internal state for Packet output processing
+ */
+typedef struct
+{
+    uint64_t *      start_ptr;          /**< ptr to start of buffer, offset kept in FAU reg */
+} cvmx_pko_state_elem_t;
+
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+/**
+ * Call before any other calls to initialize the packet
+ * output system.
+ */
+extern void cvmx_pko_initialize_global(void);
+extern int cvmx_pko_initialize_local(void);
+
+#endif
+
+
+/**
+ * Enables the packet output hardware. It must already be
+ * configured.
+ */
+extern void cvmx_pko_enable(void);
+
+
+/**
+ * Disables the packet output. Does not affect any configuration.
+ */
+extern void cvmx_pko_disable(void);
+
+
+/**
+ * Shutdown and free resources required by packet output.
+ */
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+extern void cvmx_pko_shutdown(void);
+#endif
+
+/**
+ * Configure a output port and the associated queues for use.
+ *
+ * @param port       Port to configure.
+ * @param base_queue First queue number to associate with this port.
+ * @param num_queues Number of queues t oassociate with this port
+ * @param priority   Array of priority levels for each queue. Values are
+ *                   allowed to be 1-8. A value of 8 get 8 times the traffic
+ *                   of a value of 1. There must be num_queues elements in the
+ *                   array.
+ */
+extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[]);
+
+
+/**
+ * Ring the packet output doorbell. This tells the packet
+ * output hardware that "len" command words have been added
+ * to its pending list.  This command includes the required
+ * CVMX_SYNCWS before the doorbell ring.
+ *
+ * @param port   Port the packet is for
+ * @param queue  Queue the packet is for
+ * @param len    Length of the command in 64 bit words
+ */
+static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, uint64_t len)
+{
+   cvmx_pko_doorbell_address_t ptr;
+
+   ptr.u64          = 0;
+   ptr.s.mem_space  = CVMX_IO_SEG;
+   ptr.s.did        = CVMX_OCT_DID_PKT_SEND;
+   ptr.s.is_io      = 1;
+   ptr.s.port       = port;
+   ptr.s.queue      = queue;
+   CVMX_SYNCWS;  /* Need to make sure output queue data is in DRAM before doorbell write */
+   cvmx_write_io(ptr.u64, len);
+}
+
+
+/**
+ * Prepare to send a packet.  This may initiate a tag switch to
+ * get exclusive access to the output queue structure, and
+ * performs other prep work for the packet send operation.
+ *
+ * cvmx_pko_send_packet_finish() MUST be called after this function is called,
+ * and must be called with the same port/queue/use_locking arguments.
+ *
+ * The use_locking parameter allows the caller to use three
+ * possible locking modes.
+ * - CVMX_PKO_LOCK_NONE
+ *      - PKO doesn't do any locking. It is the responsibility
+ *          of the application to make sure that no other core
+ *          is accessing the same queue at the smae time.
+ * - CVMX_PKO_LOCK_ATOMIC_TAG
+ *      - PKO performs an atomic tagswitch to insure exclusive
+ *          access to the output queue. This will maintain
+ *          packet ordering on output.
+ * - CVMX_PKO_LOCK_CMD_QUEUE
+ *      - PKO uses the common command queue locks to insure
+ *          exclusive access to the output queue. This is a
+ *          memory based ll/sc. This is the most portable
+ *          locking mechanism.
+ *
+ * NOTE: If atomic locking is used, the POW entry CANNOT be
+ * descheduled, as it does not contain a valid WQE pointer.
+ *
+ * @param port   Port to send it on
+ * @param queue  Queue to use
+ * @param use_locking
+ *               CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
+ */
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, cvmx_pko_lock_t use_locking)
+{
+    if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+    {
+        /* Must do a full switch here to handle all cases.  We use a fake WQE pointer, as the POW does
+        ** not access this memory.  The WQE pointer and group are only used if this work is descheduled,
+        ** which is not supported by the cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish combination.
+        ** Note that this is a special case in which these fake values can be used - this is not a general technique.
+        */
+        uint32_t tag = CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | CVMX_TAG_SUBGROUP_PKO  << CVMX_TAG_SUBGROUP_SHIFT | (CVMX_TAG_SUBGROUP_MASK & queue);
+        cvmx_pow_tag_sw_full((cvmx_wqe_t *)cvmx_phys_to_ptr(0x80), tag, CVMX_POW_TAG_TYPE_ATOMIC, 0);
+    }
+}
+
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
+ * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish().
+ *
+ * @param port   Port to send it on
+ * @param queue  Queue to use
+ * @param pko_command
+ *               PKO HW command word
+ * @param packet Packet to send
+ * @param use_locking
+ *               CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port, uint64_t queue,
+                                        cvmx_pko_command_word0_t pko_command,
+                                        cvmx_buf_ptr_t packet, cvmx_pko_lock_t use_locking)
+{
+    cvmx_cmd_queue_result_t result;
+    if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+        cvmx_pow_tag_sw_wait();
+    result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
+                                   (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                   pko_command.u64,
+                                   packet.u64);
+    if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
+    {
+        cvmx_pko_doorbell(port, queue, 2);
+        return CVMX_PKO_SUCCESS;
+    }
+    else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
+    {
+        return CVMX_PKO_NO_MEMORY;
+    }
+    else
+    {
+        return CVMX_PKO_INVALID_QUEUE;
+    }
+}
+
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be called exactly once before this,
+ * and the same parameters must be passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish().
+ *
+ * @param port   Port to send it on
+ * @param queue  Queue to use
+ * @param pko_command
+ *               PKO HW command word
+ * @param packet Packet to send
+ * @param addr   Plysical address of a work queue entry or physical address to zero on complete.
+ * @param use_locking
+ *               CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * @return returns CVMX_PKO_SUCCESS on success, or error code on failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(uint64_t port, uint64_t queue,
+                                        cvmx_pko_command_word0_t pko_command,
+                                        cvmx_buf_ptr_t packet, uint64_t addr, cvmx_pko_lock_t use_locking)
+{
+    cvmx_cmd_queue_result_t result;
+    if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+        cvmx_pow_tag_sw_wait();
+    result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
+                                   (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                   pko_command.u64,
+                                   packet.u64,
+                                   addr);
+    if (cvmx_likely(result == CVMX_CMD_QUEUE_SUCCESS))
+    {
+        cvmx_pko_doorbell(port, queue, 3);
+        return CVMX_PKO_SUCCESS;
+    }
+    else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) || (result == CVMX_CMD_QUEUE_FULL))
+    {
+        return CVMX_PKO_NO_MEMORY;
+    }
+    else
+    {
+        return CVMX_PKO_INVALID_QUEUE;
+    }
+}
+
+/**
+ * Return the pko output queue associated with a port and a specific core.
+ * In normal mode (PKO lockless operation is disabled), the value returned
+ * is the base queue.
+ *
+ * @param port   Port number
+ * @param core   Core to get queue for
+ *
+ * @return Core-specific output queue
+ */
+static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
+{
+#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+    #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
+#endif
+#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+    #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
+#endif
+    if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
+        return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
+    else if (port >=16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
+        return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+	       (port-16) * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
+    else if ((port >= 32) && (port < 36))
+        return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+               CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+               (port-32) * CVMX_PKO_QUEUES_PER_PORT_PCI;
+    else if ((port >= 36) && (port < 40))
+        return CVMX_PKO_MAX_PORTS_INTERFACE0 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+               CVMX_PKO_MAX_PORTS_INTERFACE1 * CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+               4 * CVMX_PKO_QUEUES_PER_PORT_PCI +
+               (port-36) * CVMX_PKO_QUEUES_PER_PORT_LOOP;
+    else
+        /* Given the limit on the number of ports we can map to
+         * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
+         * divided among all cores), the remaining unmapped ports
+         * are assigned an illegal queue number */
+        return CVMX_PKO_ILLEGAL_QUEUE;
+}
+
+/**
+ * For a given port number, return the base pko output queue
+ * for the port.
+ *
+ * @param port   Port number
+ * @return Base output queue
+ */
+static inline int cvmx_pko_get_base_queue(int port)
+{
+    return cvmx_pko_get_base_queue_per_core(port, 0);
+}
+
+/**
+ * For a given port number, return the number of pko output queues.
+ *
+ * @param port   Port number
+ * @return Number of output queues
+ */
+static inline int cvmx_pko_get_num_queues(int port)
+{
+    if (port < 16)
+        return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
+    else if (port<32)
+        return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
+    else if (port<36)
+        return CVMX_PKO_QUEUES_PER_PORT_PCI;
+    else if (port<40)
+        return CVMX_PKO_QUEUES_PER_PORT_LOOP;
+    else
+        return 0;
+}
+
+/**
+ * Get the status counters for a port.
+ *
+ * @param port_num Port number to get statistics for.
+ * @param clear    Set to 1 to clear the counters after they are read
+ * @param status   Where to put the results.
+ */
+static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pko_port_status_t *status)
+{
+    cvmx_pko_reg_read_idx_t pko_reg_read_idx;
+    cvmx_pko_mem_count0_t pko_mem_count0;
+    cvmx_pko_mem_count1_t pko_mem_count1;
+
+    pko_reg_read_idx.u64 = 0;
+    pko_reg_read_idx.s.index = port_num;
+    cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+
+    pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
+    status->packets = pko_mem_count0.s.count;
+    if (clear)
+    {
+        pko_mem_count0.s.count = port_num;
+        cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
+    }
+
+    pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
+    status->octets = pko_mem_count1.s.count;
+    if (clear)
+    {
+        pko_mem_count1.s.count = port_num;
+        cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
+    }
+
+    if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+    {
+        cvmx_pko_mem_debug9_t debug9;
+        pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+        debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
+        status->doorbell = debug9.cn38xx.doorbell;
+    }
+    else
+    {
+        cvmx_pko_mem_debug8_t debug8;
+        pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+        debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
+        status->doorbell = debug8.cn58xx.doorbell;
+    }
+}
+
+
+/**
+ * Rate limit a PKO port to a max packets/sec. This function is only
+ * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
+ *
+ * @param port      Port to rate limit
+ * @param packets_s Maximum packet/sec
+ * @param burst     Maximum number of packets to burst in a row before rate
+ *                  limiting cuts in.
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
+
+/**
+ * Rate limit a PKO port to a max bits/sec. This function is only
+ * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
+ *
+ * @param port   Port to rate limit
+ * @param bits_s PKO rate limit in bits/sec
+ * @param burst  Maximum number of bits to burst before rate
+ *               limiting cuts in.
+ *
+ * @return Zero on success, negative on failure
+ */
+extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
+
+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif   /* __CVMX_PKO_H__ */
diff --git a/cvmx-platform.h b/cvmx-platform.h
new file mode 100644
index 0000000000000..57519f52da08f
--- /dev/null
+++ b/cvmx-platform.h
@@ -0,0 +1,196 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file is resposible for including all system dependent
+ * headers for the cvmx-* files.
+ *
+ * <hr>$Revision: 41586 $<hr>
+*/
+
+#ifndef __CVMX_PLATFORM_H__
+#define __CVMX_PLATFORM_H__
+
+#include "cvmx-abi.h"
+
+#ifdef __cplusplus
+#define EXTERN_ASM extern "C"
+#else
+#define EXTERN_ASM extern
+#endif
+
+/* This file defines macros for use in determining the current
+    building environment. It defines a single CVMX_BUILD_FOR_*
+    macro representing the target of the build. The current
+    possibilities are:
+        CVMX_BUILD_FOR_UBOOT
+        CVMX_BUILD_FOR_LINUX_KERNEL
+        CVMX_BUILD_FOR_LINUX_USER
+        CVMX_BUILD_FOR_LINUX_HOST
+        CVMX_BUILD_FOR_VXWORKS
+        CVMX_BUILD_FOR_STANDALONE */
+#if defined(__U_BOOT__)
+    /* We are being used inside of Uboot */
+    #define CVMX_BUILD_FOR_UBOOT
+#elif defined(__linux__)
+    #if defined(__KERNEL__)
+        /* We are in the Linux kernel on Octeon */
+        #define CVMX_BUILD_FOR_LINUX_KERNEL
+    #elif !defined(__mips__)
+        /* We are being used under Linux but not on Octeon. Assume
+            we are on a Linux host with an Octeon target over PCI/PCIe */
+        #ifndef CVMX_BUILD_FOR_LINUX_HOST
+        #define CVMX_BUILD_FOR_LINUX_HOST
+        #endif
+    #else
+        #ifdef CVMX_BUILD_FOR_LINUX_HOST
+            /* This is a manual special case. The host PCI utilities can
+                be configured to run on Octeon. In this case it is impossible
+                to tell the difference between the normal userspace setup
+                and using cvmx_read/write_csr over the PCI bus. The host
+                utilites force this define to fix this */
+        #else
+            /* We are in the Linux userspace on Octeon */
+            #define CVMX_BUILD_FOR_LINUX_USER
+        #endif
+    #endif
+#elif defined(_WRS_KERNEL) || defined(VXWORKS_USER_MAPPINGS)
+    /* We are in VxWorks on Octeon */
+    #define CVMX_BUILD_FOR_VXWORKS
+#elif defined(_OCTEON_TOOLCHAIN_RUNTIME)
+    /* To build the simple exec toolchain runtime (newlib) library. We
+       should only use features available on all Octeon models.  */
+    #define CVMX_BUILD_FOR_TOOLCHAIN
+#else
+    /* We are building a simple exec standalone image for Octeon */
+    #define CVMX_BUILD_FOR_STANDALONE
+#endif
+
+
+/* To have a global variable be shared among all cores,
+ * declare with the CVMX_SHARED attribute.  Ex:
+ * CVMX_SHARED int myglobal;
+ * This will cause the variable to be placed in a special
+ * section that the loader will map as shared for all cores
+ * This is for data structures use by software ONLY,
+ * as it is not 1-1 VA-PA mapped.
+ */
+#define CVMX_SHARED __attribute__ ((cvmx_shared))
+
+
+#if defined(CVMX_BUILD_FOR_UBOOT)
+
+    #include <common.h>
+    #include "cvmx-sysinfo.h"
+
+#elif defined(CVMX_BUILD_FOR_LINUX_KERNEL)
+
+    #include <linux/kernel.h>
+    #include <linux/string.h>
+    #include <linux/types.h>
+    #include <stdarg.h>
+
+#elif defined(CVMX_BUILD_FOR_LINUX_USER)
+
+    #include <stddef.h>
+    #include <stdint.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <stdarg.h>
+    #include <string.h>
+    #include <assert.h>
+    #include <fcntl.h>
+    #include <sys/mman.h>
+    #include <unistd.h>
+
+#elif defined(CVMX_BUILD_FOR_LINUX_HOST)
+
+    #include <stddef.h>
+    #include <stdint.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <stdarg.h>
+    #include <string.h>
+    #include <assert.h>
+    #include <fcntl.h>
+    #include <sys/mman.h>
+    #include <unistd.h>
+
+#elif defined(CVMX_BUILD_FOR_VXWORKS)
+
+    #include <stdint.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <stdarg.h>
+    #include <string.h>
+    #include <assert.h>
+
+#elif defined(CVMX_BUILD_FOR_STANDALONE)
+
+    #include <stddef.h>
+    #include <stdint.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <stdarg.h>
+    #include <string.h>
+    #include <assert.h>
+
+#elif defined(CVMX_BUILD_FOR_TOOLCHAIN)
+
+    #include <stddef.h>
+    #include <stdint.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <stdarg.h>
+    #include <string.h>
+    #include <assert.h>
+
+#else
+
+    #error Unexpected CVMX_BUILD_FOR_* macro
+
+#endif
+
+#endif /* __CVMX_PLATFORM_H__ */
diff --git a/cvmx-pow.c b/cvmx-pow.c
new file mode 100644
index 0000000000000..2a0902a6f8a54
--- /dev/null
+++ b/cvmx-pow.c
@@ -0,0 +1,481 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Packet Order / Work unit.
+ *
+ * <hr>$Revision: 29727 $<hr>
+ */
+
+#include "cvmx.h"
+#include "cvmx-pow.h"
+
+/**
+ * @INTERNAL
+ * This structure stores the internal POW state captured by
+ * cvmx_pow_capture(). It is purposely not exposed to the user
+ * since the format may change without notice.
+ */
+typedef struct
+{
+    cvmx_pow_tag_load_resp_t sstatus[16][8];
+    cvmx_pow_tag_load_resp_t smemload[2048][3];
+    cvmx_pow_tag_load_resp_t sindexload[16][4];
+} __cvmx_pow_dump_t;
+
+typedef enum
+{
+    CVMX_POW_LIST_UNKNOWN=0,
+    CVMX_POW_LIST_FREE=1,
+    CVMX_POW_LIST_INPUT=2,
+    CVMX_POW_LIST_CORE=CVMX_POW_LIST_INPUT+8,
+    CVMX_POW_LIST_DESCHED=CVMX_POW_LIST_CORE+16,
+    CVMX_POW_LIST_NOSCHED=CVMX_POW_LIST_DESCHED+16,
+} __cvmx_pow_list_types_t;
+
+static const char *__cvmx_pow_list_names[] = {
+    "Unknown",
+    "Free List",
+    "Queue 0", "Queue 1", "Queue 2", "Queue 3",
+    "Queue 4", "Queue 5", "Queue 6", "Queue 7",
+    "Core 0", "Core 1", "Core 2", "Core 3",
+    "Core 4", "Core 5", "Core 6", "Core 7",
+    "Core 8", "Core 9", "Core 10", "Core 11",
+    "Core 12", "Core 13", "Core 14", "Core 15",
+    "Desched 0", "Desched 1", "Desched 2", "Desched 3",
+    "Desched 4", "Desched 5", "Desched 6", "Desched 7",
+    "Desched 8", "Desched 9", "Desched 10", "Desched 11",
+    "Desched 12", "Desched 13", "Desched 14", "Desched 15",
+    "Nosched 0", "Nosched 1", "Nosched 2", "Nosched 3",
+    "Nosched 4", "Nosched 5", "Nosched 6", "Nosched 7",
+    "Nosched 8", "Nosched 9", "Nosched 10", "Nosched 11",
+    "Nosched 12", "Nosched 13", "Nosched 14", "Nosched 15"
+};
+
+
+/**
+ * Return the number of POW entries supported by this chip
+ *
+ * @return Number of POW entries
+ */
+int cvmx_pow_get_num_entries(void)
+{
+    if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+        return 64;
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+        return 256;
+    else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        return 512;
+    else
+        return 2048;
+}
+
+
+/**
+ * Store the current POW internal state into the supplied
+ * buffer. It is recommended that you pass a buffer of at least
+ * 128KB. The format of the capture may change based on SDK
+ * version and Octeon chip.
+ *
+ * @param buffer Buffer to store capture into
+ * @param buffer_size
+ *               The size of the supplied buffer
+ *
+ * @return Zero on sucess, negative on failure
+ */
+int cvmx_pow_capture(void *buffer, int buffer_size)
+{
+    __cvmx_pow_dump_t *dump = (__cvmx_pow_dump_t*)buffer;
+    int num_cores;
+    int num_pow_entries = cvmx_pow_get_num_entries();
+    int core;
+    int index;
+    int bits;
+
+    if (buffer_size < (int)sizeof(__cvmx_pow_dump_t))
+    {
+        cvmx_dprintf("cvmx_pow_capture: Buffer too small\n");
+        return -1;
+    }
+
+    num_cores = cvmx_octeon_num_cores();
+
+    /* Read all core related state */
+    for (core=0; core<num_cores; core++)
+    {
+        cvmx_pow_load_addr_t load_addr;
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = core;
+        for (bits=0; bits<8; bits++)
+        {
+            load_addr.sstatus.get_rev = (bits & 1) != 0;
+            load_addr.sstatus.get_cur = (bits & 2) != 0;
+            load_addr.sstatus.get_wqp = (bits & 4) != 0;
+            if ((load_addr.sstatus.get_cur == 0) && load_addr.sstatus.get_rev)
+                dump->sstatus[core][bits].u64 = -1;
+            else
+                dump->sstatus[core][bits].u64 = cvmx_read_csr(load_addr.u64);
+        }
+    }
+
+    /* Read all internal POW entries */
+    for (index=0; index<num_pow_entries; index++)
+    {
+        cvmx_pow_load_addr_t load_addr;
+        load_addr.u64 = 0;
+        load_addr.smemload.mem_region = CVMX_IO_SEG;
+        load_addr.smemload.is_io = 1;
+        load_addr.smemload.did = CVMX_OCT_DID_TAG_TAG2;
+        load_addr.smemload.index = index;
+        for (bits=0; bits<3; bits++)
+        {
+            load_addr.smemload.get_des = (bits & 1) != 0;
+            load_addr.smemload.get_wqp = (bits & 2) != 0;
+            dump->smemload[index][bits].u64 = cvmx_read_csr(load_addr.u64);
+        }
+    }
+
+    /* Read all group and queue pointers */
+    for (index=0; index<16; index++)
+    {
+        cvmx_pow_load_addr_t load_addr;
+        load_addr.u64 = 0;
+        load_addr.sindexload.mem_region = CVMX_IO_SEG;
+        load_addr.sindexload.is_io = 1;
+        load_addr.sindexload.did = CVMX_OCT_DID_TAG_TAG3;
+        load_addr.sindexload.qosgrp = index;
+        for (bits=0; bits<4; bits++)
+        {
+            load_addr.sindexload.get_rmt =  (bits & 1) != 0;
+            load_addr.sindexload.get_des_get_tail =  (bits & 2) != 0;
+            /* The first pass only has 8 valid index values */
+            if ((load_addr.sindexload.get_rmt == 0) &&
+                (load_addr.sindexload.get_des_get_tail == 0) &&
+                (index >= 8))
+                dump->sindexload[index][bits].u64 = -1;
+            else
+                dump->sindexload[index][bits].u64 = cvmx_read_csr(load_addr.u64);
+        }
+    }
+    return 0;
+}
+
+
+/**
+ * Function to display a POW internal queue to the user
+ *
+ * @param name       User visible name for the queue
+ * @param name_param Parameter for printf in creating the name
+ * @param valid      Set if the queue contains any elements
+ * @param has_one    Set if the queue contains exactly one element
+ * @param head       The head pointer
+ * @param tail       The tail pointer
+ */
+static void __cvmx_pow_display_list(const char *name, int name_param, int valid, int has_one, uint64_t head, uint64_t tail)
+{
+    printf(name, name_param);
+    printf(": ");
+    if (valid)
+    {
+        if (has_one)
+            printf("One element index=%llu(0x%llx)\n", CAST64(head), CAST64(head));
+        else
+            printf("Multiple elements head=%llu(0x%llx) tail=%llu(0x%llx)\n", CAST64(head), CAST64(head), CAST64(tail), CAST64(tail));
+    }
+    else
+        printf("Empty\n");
+}
+
+
+/**
+ * Mark which list a POW entry is on. Print a warning message if the
+ * entry is already on a list. This happens if the POW changed while
+ * the capture was running.
+ *
+ * @param entry_num  Entry number to mark
+ * @param entry_type List type
+ * @param entry_list Array to store marks
+ *
+ * @return Zero on success, negative if already on a list
+ */
+static int __cvmx_pow_entry_mark_list(int entry_num, __cvmx_pow_list_types_t entry_type, uint8_t entry_list[])
+{
+    if (entry_list[entry_num] == 0)
+    {
+        entry_list[entry_num] = entry_type;
+        return 0;
+    }
+    else
+    {
+        printf("\nWARNING: Entry %d already on list %s, but we tried to add it to %s\n",
+               entry_num, __cvmx_pow_list_names[entry_list[entry_num]], __cvmx_pow_list_names[entry_type]);
+        return -1;
+    }
+}
+
+
+/**
+ * Display a list and mark all elements on the list as belonging to
+ * the list.
+ *
+ * @param entry_type Type of the list to display and mark
+ * @param dump       POW capture data
+ * @param entry_list Array to store marks in
+ * @param valid      Set if the queue contains any elements
+ * @param has_one    Set if the queue contains exactly one element
+ * @param head       The head pointer
+ * @param tail       The tail pointer
+ */
+static void __cvmx_pow_display_list_and_walk(__cvmx_pow_list_types_t entry_type,
+                                             __cvmx_pow_dump_t *dump, uint8_t entry_list[],
+                                             int valid, int has_one, uint64_t head, uint64_t tail)
+{
+    __cvmx_pow_display_list(__cvmx_pow_list_names[entry_type], 0, valid, has_one, head, tail);
+    if (valid)
+    {
+        if (has_one)
+            __cvmx_pow_entry_mark_list(head, entry_type, entry_list);
+        else
+        {
+            while (head != tail)
+            {
+                if (__cvmx_pow_entry_mark_list(head, entry_type, entry_list))
+                    break;
+                head = dump->smemload[head][0].s_smemload0.next_index;
+            }
+            __cvmx_pow_entry_mark_list(tail, entry_type, entry_list);
+        }
+    }
+}
+
+
+/**
+ * Dump a POW capture to the console in a human readable format.
+ *
+ * @param buffer POW capture from cvmx_pow_capture()
+ * @param buffer_size
+ *               Size of the buffer
+ */
+void cvmx_pow_display(void *buffer, int buffer_size)
+{
+    __cvmx_pow_dump_t *dump = (__cvmx_pow_dump_t*)buffer;
+    int num_pow_entries = cvmx_pow_get_num_entries();
+    int num_cores;
+    int core;
+    int index;
+    uint8_t entry_list[2048];
+
+    if (buffer_size < (int)sizeof(__cvmx_pow_dump_t))
+    {
+        cvmx_dprintf("cvmx_pow_dump: Buffer too small\n");
+        return;
+    }
+
+    memset(entry_list, 0, sizeof(entry_list));
+    num_cores = cvmx_octeon_num_cores();
+
+    printf("POW Display Start\n");
+
+    /* Print the free list info */
+    __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_FREE, dump, entry_list,
+                                     dump->sindexload[0][0].sindexload0.free_val,
+                                     dump->sindexload[0][0].sindexload0.free_one,
+                                     dump->sindexload[0][0].sindexload0.free_head,
+                                     dump->sindexload[0][0].sindexload0.free_tail);
+
+    /* Print the core state */
+    for (core=0; core<num_cores; core++)
+    {
+        const int bit_rev = 1;
+        const int bit_cur = 2;
+        const int bit_wqp = 4;
+        printf("Core %d State:  tag=%s,0x%08x", core,
+               OCT_TAG_TYPE_STRING(dump->sstatus[core][bit_cur].s_sstatus2.tag_type),
+               dump->sstatus[core][bit_cur].s_sstatus2.tag);
+        if (dump->sstatus[core][bit_cur].s_sstatus2.tag_type != CVMX_POW_TAG_TYPE_NULL_NULL)
+        {
+            __cvmx_pow_entry_mark_list(dump->sstatus[core][bit_cur].s_sstatus2.index, CVMX_POW_LIST_CORE + core, entry_list);
+            printf(" grp=%d",                   dump->sstatus[core][bit_cur].s_sstatus2.grp);
+            printf(" wqp=0x%016llx",            CAST64(dump->sstatus[core][bit_cur|bit_wqp].s_sstatus4.wqp));
+            printf(" index=%d",                 dump->sstatus[core][bit_cur].s_sstatus2.index);
+            if (dump->sstatus[core][bit_cur].s_sstatus2.head)
+                printf(" head");
+            else
+                printf(" prev=%d", dump->sstatus[core][bit_cur|bit_rev].s_sstatus3.revlink_index);
+            if (dump->sstatus[core][bit_cur].s_sstatus2.tail)
+                printf(" tail");
+            else
+                printf(" next=%d", dump->sstatus[core][bit_cur].s_sstatus2.link_index);
+        }
+
+        if (dump->sstatus[core][0].s_sstatus0.pend_switch)
+        {
+            printf(" pend_switch=%d",           dump->sstatus[core][0].s_sstatus0.pend_switch);
+            printf(" pend_switch_full=%d",      dump->sstatus[core][0].s_sstatus0.pend_switch_full);
+            printf(" pend_switch_null=%d",      dump->sstatus[core][0].s_sstatus0.pend_switch_null);
+        }
+
+        if (dump->sstatus[core][0].s_sstatus0.pend_desched)
+        {
+            printf(" pend_desched=%d",          dump->sstatus[core][0].s_sstatus0.pend_desched);
+            printf(" pend_desched_switch=%d",   dump->sstatus[core][0].s_sstatus0.pend_desched_switch);
+            printf(" pend_nosched=%d",          dump->sstatus[core][0].s_sstatus0.pend_nosched);
+            if (dump->sstatus[core][0].s_sstatus0.pend_desched_switch)
+                printf(" pend_grp=%d",              dump->sstatus[core][0].s_sstatus0.pend_grp);
+        }
+
+        if (dump->sstatus[core][0].s_sstatus0.pend_new_work)
+        {
+            if (dump->sstatus[core][0].s_sstatus0.pend_new_work_wait)
+                printf(" (Waiting for work)");
+            else
+                printf(" (Getting work)");
+        }
+        if (dump->sstatus[core][0].s_sstatus0.pend_null_rd)
+            printf(" pend_null_rd=%d",          dump->sstatus[core][0].s_sstatus0.pend_null_rd);
+        if (dump->sstatus[core][0].s_sstatus0.pend_nosched_clr)
+        {
+            printf(" pend_nosched_clr=%d",      dump->sstatus[core][0].s_sstatus0.pend_nosched_clr);
+            printf(" pend_index=%d",            dump->sstatus[core][0].s_sstatus0.pend_index);
+        }
+        if (dump->sstatus[core][0].s_sstatus0.pend_switch ||
+            (dump->sstatus[core][0].s_sstatus0.pend_desched &&
+            dump->sstatus[core][0].s_sstatus0.pend_desched_switch))
+        {
+            printf(" pending tag=%s,0x%08x",
+                   OCT_TAG_TYPE_STRING(dump->sstatus[core][0].s_sstatus0.pend_type),
+                   dump->sstatus[core][0].s_sstatus0.pend_tag);
+        }
+        if (dump->sstatus[core][0].s_sstatus0.pend_nosched_clr)
+            printf(" pend_wqp=0x%016llx\n",     CAST64(dump->sstatus[core][bit_wqp].s_sstatus1.pend_wqp));
+        printf("\n");
+    }
+
+    /* Print out the state of the 16 deschedule lists. Each group has two
+        lists. One for entries marked noshed, the other for normal
+        deschedules */
+    for (index=0; index<16; index++)
+    {
+        __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_NOSCHED + index, dump, entry_list,
+                                dump->sindexload[index][2].sindexload1.nosched_val,
+                                dump->sindexload[index][2].sindexload1.nosched_one,
+                                dump->sindexload[index][2].sindexload1.nosched_head,
+                                dump->sindexload[index][2].sindexload1.nosched_tail);
+        __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_DESCHED + index, dump, entry_list,
+                                dump->sindexload[index][2].sindexload1.des_val,
+                                dump->sindexload[index][2].sindexload1.des_one,
+                                dump->sindexload[index][2].sindexload1.des_head,
+                                dump->sindexload[index][2].sindexload1.des_tail);
+    }
+
+    /* Print out the state of the 8 internal input queues */
+    for (index=0; index<8; index++)
+    {
+        __cvmx_pow_display_list_and_walk(CVMX_POW_LIST_INPUT + index, dump, entry_list,
+                                dump->sindexload[index][0].sindexload0.loc_val,
+                                dump->sindexload[index][0].sindexload0.loc_one,
+                                dump->sindexload[index][0].sindexload0.loc_head,
+                                dump->sindexload[index][0].sindexload0.loc_tail);
+    }
+
+    /* Print out the state of the 16 memory queues */
+    for (index=0; index<8; index++)
+    {
+        const char *name;
+        if (dump->sindexload[index][1].sindexload2.rmt_is_head)
+            name = "Queue %da Memory (is head)";
+        else
+            name = "Queue %da Memory";
+        __cvmx_pow_display_list(name, index,
+                                dump->sindexload[index][1].sindexload2.rmt_val,
+                                dump->sindexload[index][1].sindexload2.rmt_one,
+                                dump->sindexload[index][1].sindexload2.rmt_head,
+                                dump->sindexload[index][3].sindexload3.rmt_tail);
+        if (dump->sindexload[index+8][1].sindexload2.rmt_is_head)
+            name = "Queue %db Memory (is head)";
+        else
+            name = "Queue %db Memory";
+        __cvmx_pow_display_list(name, index,
+                                dump->sindexload[index+8][1].sindexload2.rmt_val,
+                                dump->sindexload[index+8][1].sindexload2.rmt_one,
+                                dump->sindexload[index+8][1].sindexload2.rmt_head,
+                                dump->sindexload[index+8][3].sindexload3.rmt_tail);
+    }
+
+    /* Print out each of the internal POW entries. Each entry has a tag, group,
+        wqe, and possibly a next pointer. The next pointer is only valid if this
+        entry isn't make as a tail */
+    for (index=0; index<num_pow_entries; index++)
+    {
+        printf("Entry %d(%-10s): tag=%s,0x%08x grp=%d wqp=0x%016llx", index,
+               __cvmx_pow_list_names[entry_list[index]],
+               OCT_TAG_TYPE_STRING(dump->smemload[index][0].s_smemload0.tag_type),
+               dump->smemload[index][0].s_smemload0.tag,
+               dump->smemload[index][0].s_smemload0.grp,
+               CAST64(dump->smemload[index][2].s_smemload1.wqp));
+        if (dump->smemload[index][0].s_smemload0.tail)
+            printf(" tail");
+        else
+            printf(" next=%d", dump->smemload[index][0].s_smemload0.next_index);
+        if (entry_list[index] >= CVMX_POW_LIST_DESCHED)
+        {
+            printf(" prev=%d", dump->smemload[index][1].s_smemload2.fwd_index);
+            printf(" nosched=%d", dump->smemload[index][1].s_smemload2.nosched);
+            if (dump->smemload[index][1].s_smemload2.pend_switch)
+            {
+                printf(" pending tag=%s,0x%08x",
+                       OCT_TAG_TYPE_STRING(dump->smemload[index][1].s_smemload2.pend_type),
+                       dump->smemload[index][1].s_smemload2.pend_tag);
+            }
+        }
+        printf("\n");
+    }
+
+    printf("POW Display End\n");
+}
+
diff --git a/cvmx-pow.h b/cvmx-pow.h
new file mode 100644
index 0000000000000..dea56527f9394
--- /dev/null
+++ b/cvmx-pow.h
@@ -0,0 +1,1749 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware Packet Order / Work unit.
+ *
+ * New, starting with SDK 1.7.0, cvmx-pow supports a number of
+ * extended consistency checks. The define
+ * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
+ * internal state checks to find common programming errors. If
+ * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
+ * enabled. For example, cvmx-pow will check for the following
+ * program errors or POW state inconsistency.
+ * - Requesting a POW operation with an active tag switch in
+ *   progress.
+ * - Waiting for a tag switch to complete for an excessively
+ *   long period. This is normally a sign of an error in locking
+ *   causing deadlock.
+ * - Illegal tag switches from NULL_NULL.
+ * - Illegal tag switches from NULL.
+ * - Illegal deschedule request.
+ * - WQE pointer not matching the one attached to the core by
+ *   the POW.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_POW_H__
+#define __CVMX_POW_H__
+
+#include "cvmx-scratch.h"
+#include "cvmx-wqe.h"
+#include "cvmx-warn.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Default to having all POW constancy checks turned on */
+#ifndef CVMX_ENABLE_POW_CHECKS
+#define CVMX_ENABLE_POW_CHECKS 1
+#endif
+
+/**
+ * Wait flag values for pow functions.
+ */
+typedef enum
+{
+    CVMX_POW_WAIT = 1,
+    CVMX_POW_NO_WAIT = 0,
+} cvmx_pow_wait_t;
+
+/**
+ *  POW tag operations.  These are used in the data stored to the POW.
+ */
+typedef enum
+{
+    CVMX_POW_TAG_OP_SWTAG = 0L,         /**< switch the tag (only) for this PP
+                                            - the previous tag should be non-NULL in this case
+                                            - tag switch response required
+                                            - fields used: op, type, tag */
+    CVMX_POW_TAG_OP_SWTAG_FULL = 1L,    /**< switch the tag for this PP, with full information
+                                            - this should be used when the previous tag is NULL
+                                            - tag switch response required
+                                            - fields used: address, op, grp, type, tag */
+    CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,   /**< switch the tag (and/or group) for this PP and de-schedule
+                                            - OK to keep the tag the same and only change the group
+                                            - fields used: op, no_sched, grp, type, tag */
+    CVMX_POW_TAG_OP_DESCH = 3L,         /**< just de-schedule
+                                            - fields used: op, no_sched */
+    CVMX_POW_TAG_OP_ADDWQ = 4L,         /**< create an entirely new work queue entry
+                                            - fields used: address, op, qos, grp, type, tag */
+    CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,/**< just update the work queue pointer and grp for this PP
+                                            - fields used: address, op, grp */
+    CVMX_POW_TAG_OP_SET_NSCHED = 6L,    /**< set the no_sched bit on the de-schedule list
+                                            - does nothing if the selected entry is not on the de-schedule list
+                                            - does nothing if the stored work queue pointer does not match the address field
+                                            - fields used: address, index, op
+                                            Before issuing a *_NSCHED operation, SW must guarantee that all
+                                            prior deschedules and set/clr NSCHED operations are complete and all
+                                            prior switches are complete. The hardware provides the opsdone bit
+                                            and swdone bit for SW polling. After issuing a *_NSCHED operation,
+                                            SW must guarantee that the set/clr NSCHED is complete before
+                                            any subsequent operations. */
+    CVMX_POW_TAG_OP_CLR_NSCHED = 7L,    /**< clears the no_sched bit on the de-schedule list
+                                            - does nothing if the selected entry is not on the de-schedule list
+                                            - does nothing if the stored work queue pointer does not match the address field
+                                            - fields used: address, index, op
+                                            Before issuing a *_NSCHED operation, SW must guarantee that all
+                                            prior deschedules and set/clr NSCHED operations are complete and all
+                                            prior switches are complete. The hardware provides the opsdone bit
+                                            and swdone bit for SW polling. After issuing a *_NSCHED operation,
+                                            SW must guarantee that the set/clr NSCHED is complete before
+                                            any subsequent operations. */
+    CVMX_POW_TAG_OP_NOP = 15L           /**< do nothing */
+} cvmx_pow_tag_op_t;
+
+/**
+ * This structure defines the store data on a store to POW
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t              no_sched  : 1; /**< don't reschedule this entry. no_sched is used for CVMX_POW_TAG_OP_SWTAG_DESCH and CVMX_POW_TAG_OP_DESCH */
+        uint64_t                unused  : 2;
+        uint64_t                 index  :13; /**< contains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
+        cvmx_pow_tag_op_t          op   : 4; /**< the operation to perform */
+        uint64_t                unused2 : 2;
+        uint64_t                   qos  : 3; /**< the QOS level for the packet. qos is only used for CVMX_POW_TAG_OP_ADDWQ */
+        uint64_t                   grp  : 4; /**< the group that the work queue entry will be scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, CVMX_POW_TAG_OP_SWTAG_FULL, CVMX_POW_TAG_OP_SWTAG_DESCH, and CVMX_POW_TAG_OP_UPDATE_WQP_GRP */
+        cvmx_pow_tag_type_t        type : 3; /**< the type of the tag. type is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+        uint64_t                   tag  :32; /**< the actual tag. tag is used for everything except CVMX_POW_TAG_OP_DESCH, CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and CVMX_POW_TAG_OP_*_NSCHED */
+#else
+        uint64_t                   tag  :32;
+        cvmx_pow_tag_type_t        type : 3;
+        uint64_t                   grp  : 4;
+        uint64_t                   qos  : 3;
+        uint64_t                unused2 : 2;
+        cvmx_pow_tag_op_t          op   : 4;
+        uint64_t                 index  :13;
+        uint64_t                unused  : 2;
+        uint64_t              no_sched  : 1;
+#endif
+    } s;
+} cvmx_pow_tag_req_t;
+
+/**
+ * This structure describes the address to load stuff from POW
+ */
+typedef union
+{
+    uint64_t u64;
+
+    /**
+     * Address for new work request loads (did<2:0> == 0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of POW -- did<2:0> == 0 in this case */
+        uint64_t    reserved_4_39   : 36;   /**< Must be zero */
+        uint64_t    wait            : 1;    /**< If set, don't return load response until work is available */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    wait            : 1;
+        uint64_t    reserved_4_39   : 36;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } swork;
+
+    /**
+     * Address for loads to get POW internal status
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of POW -- did<2:0> == 1 in this case */
+        uint64_t    reserved_10_39  : 30;   /**< Must be zero */
+        uint64_t    coreid          : 4;    /**< The core id to get status for */
+        uint64_t    get_rev         : 1;    /**< If set and get_cur is set, return reverse tag-list pointer rather than forward tag-list pointer */
+        uint64_t    get_cur         : 1;    /**< If set, return current status rather than pending status */
+        uint64_t    get_wqp         : 1;    /**< If set, get the work-queue pointer rather than tag/type */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    get_wqp         : 1;
+        uint64_t    get_cur         : 1;
+        uint64_t    get_rev         : 1;
+        uint64_t    coreid          : 4;
+        uint64_t    reserved_10_39  : 30;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } sstatus;
+
+    /**
+     * Address for memory loads to get POW internal state
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of POW -- did<2:0> == 2 in this case */
+        uint64_t    reserved_16_39  : 24;   /**< Must be zero */
+        uint64_t    index           : 11;   /**< POW memory index */
+        uint64_t    get_des         : 1;    /**< If set, return deschedule information rather than the standard
+                                                response for work-queue index (invalid if the work-queue entry is not on the
+                                                deschedule list). */
+        uint64_t    get_wqp         : 1;    /**< If set, get the work-queue pointer rather than tag/type (no effect when get_des set). */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    get_wqp         : 1;
+        uint64_t    get_des         : 1;
+        uint64_t    index           : 11;
+        uint64_t    reserved_16_39  : 24;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } smemload;
+
+    /**
+     * Address for index/pointer loads
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of POW -- did<2:0> == 3 in this case */
+        uint64_t    reserved_9_39   : 31;   /**< Must be zero */
+        uint64_t    qosgrp          : 4;    /**< when {get_rmt ==0 AND get_des_get_tail == 0}, this field selects one of
+                                                eight POW internal-input queues (0-7), one per QOS level; values 8-15 are
+                                                illegal in this case;
+                                                when {get_rmt ==0 AND get_des_get_tail == 1}, this field selects one of
+                                                16 deschedule lists (per group);
+                                                when get_rmt ==1, this field selects one of 16 memory-input queue lists.
+                                                The two memory-input queue lists associated with each QOS level are:
+                                                - qosgrp = 0, qosgrp = 8:      QOS0
+                                                - qosgrp = 1, qosgrp = 9:      QOS1
+                                                - qosgrp = 2, qosgrp = 10:     QOS2
+                                                - qosgrp = 3, qosgrp = 11:     QOS3
+                                                - qosgrp = 4, qosgrp = 12:     QOS4
+                                                - qosgrp = 5, qosgrp = 13:     QOS5
+                                                - qosgrp = 6, qosgrp = 14:     QOS6
+                                                - qosgrp = 7, qosgrp = 15:     QOS7 */
+        uint64_t    get_des_get_tail: 1;    /**< If set and get_rmt is clear, return deschedule list indexes
+                                                rather than indexes for the specified qos level; if set and get_rmt is set, return
+                                                the tail pointer rather than the head pointer for the specified qos level. */
+        uint64_t    get_rmt         : 1;    /**< If set, return remote pointers rather than the local indexes for the specified qos level. */
+        uint64_t    reserved_0_2    : 3;    /**< Must be zero */
+#else
+        uint64_t    reserved_0_2    : 3;
+        uint64_t    get_rmt         : 1;
+        uint64_t    get_des_get_tail: 1;
+        uint64_t    qosgrp          : 4;
+        uint64_t    reserved_9_39   : 31;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } sindexload;
+
+    /**
+     * address for NULL_RD request (did<2:0> == 4)
+     * when this is read, HW attempts to change the state to NULL if it is NULL_NULL
+     * (the hardware cannot switch from NULL_NULL to NULL if a POW entry is not available -
+     * software may need to recover by finishing another piece of work before a POW
+     * entry can ever become available.)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    mem_region      : 2;    /**< Mips64 address region. Should be CVMX_IO_SEG */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< the ID of POW -- did<2:0> == 4 in this case */
+        uint64_t    reserved_0_39   : 40;   /**< Must be zero */
+#else
+        uint64_t    reserved_0_39   : 40;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_region      : 2;
+#endif
+    } snull_rd;
+} cvmx_pow_load_addr_t;
+
+/**
+ * This structure defines the response to a load/SENDSINGLE to POW (except CSR reads)
+ */
+typedef union
+{
+    uint64_t u64;
+
+    /**
+     * Response to new work request loads
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    no_work          : 1;   /**< Set when no new work queue entry was returned.
+                                                If there was de-scheduled work, the HW will definitely
+                                                return it. When this bit is set, it could mean
+                                                either mean:
+                                                - There was no work, or
+                                                - There was no work that the HW could find. This
+                                                    case can happen, regardless of the wait bit value
+                                                    in the original request, when there is work
+                                                    in the IQ's that is too deep down the list. */
+        uint64_t    reserved_40_62   : 23;  /**< Must be zero */
+        uint64_t    addr             : 40;  /**< 36 in O1 -- the work queue pointer */
+#else
+        uint64_t    addr             : 40;
+        uint64_t    reserved_40_62   : 23;
+        uint64_t    no_work          : 1;
+#endif
+    } s_work;
+
+    /**
+     * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-NULL SWTAG or
+                                                SWTAG_FULL, and the POW entry has not left the list for the original tag. */
+        uint64_t    pend_switch_full: 1;    /**< Set when SWTAG_FULL and pend_switch is set. */
+        uint64_t    pend_switch_null: 1;    /**< Set when there is a pending NULL SWTAG, or an implicit switch to NULL. */
+        uint64_t    pend_desched    : 1;    /**< Set when there is a pending DESCHED or SWTAG_DESCHED. */
+        uint64_t    pend_desched_switch: 1; /**< Set when there is a pending SWTAG_DESCHED and pend_desched is set. */
+        uint64_t    pend_nosched    : 1;    /**< Set when nosched is desired and pend_desched is set. */
+        uint64_t    pend_new_work   : 1;    /**< Set when there is a pending GET_WORK. */
+        uint64_t    pend_new_work_wait: 1;  /**< When pend_new_work is set, this bit indicates that the wait bit was set. */
+        uint64_t    pend_null_rd    : 1;    /**< Set when there is a pending NULL_RD. */
+        uint64_t    pend_nosched_clr: 1;    /**< Set when there is a pending CLR_NSCHED. */
+        uint64_t    reserved_51     : 1;
+        uint64_t    pend_index      : 11;   /**< This is the index when pend_nosched_clr is set. */
+        uint64_t    pend_grp        : 4;    /**< This is the new_grp when (pend_desched AND pend_desched_switch) is set. */
+        uint64_t    reserved_34_35  : 2;
+        uint64_t    pend_type       : 2;    /**< This is the tag type when pend_switch or (pend_desched AND pend_desched_switch) are set. */
+        uint64_t    pend_tag        : 32;   /**< - this is the tag when pend_switch or (pend_desched AND pend_desched_switch) are set. */
+#else
+        uint64_t    pend_tag        : 32;
+        uint64_t    pend_type       : 2;
+        uint64_t    reserved_34_35  : 2;
+        uint64_t    pend_grp        : 4;
+        uint64_t    pend_index      : 11;
+        uint64_t    reserved_51     : 1;
+        uint64_t    pend_nosched_clr: 1;
+        uint64_t    pend_null_rd    : 1;
+        uint64_t    pend_new_work_wait: 1;
+        uint64_t    pend_new_work   : 1;
+        uint64_t    pend_nosched    : 1;
+        uint64_t    pend_desched_switch: 1;
+        uint64_t    pend_desched    : 1;
+        uint64_t    pend_switch_null: 1;
+        uint64_t    pend_switch_full: 1;
+        uint64_t    pend_switch     : 1;
+        uint64_t    reserved_62_63  : 2;
+#endif
+    } s_sstatus0;
+
+    /**
+     * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    pend_switch     : 1;    /**< Set when there is a pending non-NULL SWTAG or
+                                                SWTAG_FULL, and the POW entry has not left the list for the original tag. */
+        uint64_t    pend_switch_full: 1;    /**< Set when SWTAG_FULL and pend_switch is set. */
+        uint64_t    pend_switch_null: 1;    /**< Set when there is a pending NULL SWTAG, or an implicit switch to NULL. */
+        uint64_t    pend_desched    : 1;    /**< Set when there is a pending DESCHED or SWTAG_DESCHED. */
+        uint64_t    pend_desched_switch: 1; /**< Set when there is a pending SWTAG_DESCHED and pend_desched is set. */
+        uint64_t    pend_nosched    : 1;    /**< Set when nosched is desired and pend_desched is set. */
+        uint64_t    pend_new_work   : 1;    /**< Set when there is a pending GET_WORK. */
+        uint64_t    pend_new_work_wait: 1;  /**< When pend_new_work is set, this bit indicates that the wait bit was set. */
+        uint64_t    pend_null_rd    : 1;    /**< Set when there is a pending NULL_RD. */
+        uint64_t    pend_nosched_clr: 1;    /**< Set when there is a pending CLR_NSCHED. */
+        uint64_t    reserved_51     : 1;
+        uint64_t    pend_index      : 11;   /**< This is the index when pend_nosched_clr is set. */
+        uint64_t    pend_grp        : 4;    /**< This is the new_grp when (pend_desched AND pend_desched_switch) is set. */
+        uint64_t    pend_wqp        : 36;   /**< This is the wqp when pend_nosched_clr is set. */
+#else
+        uint64_t    pend_wqp        : 36;
+        uint64_t    pend_grp        : 4;
+        uint64_t    pend_index      : 11;
+        uint64_t    reserved_51     : 1;
+        uint64_t    pend_nosched_clr: 1;
+        uint64_t    pend_null_rd    : 1;
+        uint64_t    pend_new_work_wait: 1;
+        uint64_t    pend_new_work   : 1;
+        uint64_t    pend_nosched    : 1;
+        uint64_t    pend_desched_switch: 1;
+        uint64_t    pend_desched    : 1;
+        uint64_t    pend_switch_null: 1;
+        uint64_t    pend_switch_full: 1;
+        uint64_t    pend_switch     : 1;
+        uint64_t    reserved_62_63  : 2;
+#endif
+    } s_sstatus1;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    link_index      : 11;    /**< Points to the next POW entry in the tag list when tail == 0 (and
+                                                tag_type is not NULL or NULL_NULL). */
+        uint64_t    index           : 11;   /**< The POW entry attached to the core. */
+        uint64_t    grp             : 4;    /**< The group attached to the core (updated when new tag list entered on SWTAG_FULL). */
+        uint64_t    head            : 1;    /**< Set when this POW entry is at the head of its tag list (also set when in
+                                                the NULL or NULL_NULL state). */
+        uint64_t    tail            : 1;    /**< Set when this POW entry is at the tail of its tag list (also set when in the
+                                                NULL or NULL_NULL state). */
+        uint64_t    tag_type        : 2;    /**< The tag type attached to the core (updated when new tag list
+                                                entered on SWTAG, SWTAG_FULL, or SWTAG_DESCHED). */
+        uint64_t    tag             : 32;   /**< The tag attached to the core (updated when new tag list entered on
+                                                SWTAG, SWTAG_FULL, or SWTAG_DESCHED). */
+#else
+        uint64_t    tag             : 32;
+        uint64_t    tag_type        : 2;
+        uint64_t    tail            : 1;
+        uint64_t    head            : 1;
+        uint64_t    grp             : 4;
+        uint64_t    index           : 11;
+        uint64_t    link_index      : 11;
+        uint64_t    reserved_62_63  : 2;
+#endif
+    } s_sstatus2;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    revlink_index   : 11;   /**< Points to the prior POW entry in the tag list when head == 0
+                                                (and tag_type is not NULL or NULL_NULL). This field is unpredictable
+                                                when the core's state is NULL or NULL_NULL. */
+        uint64_t    index           : 11;   /**< The POW entry attached to the core. */
+        uint64_t    grp             : 4;    /**< The group attached to the core (updated when new tag list entered on SWTAG_FULL). */
+        uint64_t    head            : 1;    /**< Set when this POW entry is at the head of its tag list (also set when in
+                                                the NULL or NULL_NULL state). */
+        uint64_t    tail            : 1;    /**< Set when this POW entry is at the tail of its tag list (also set when in the
+                                                NULL or NULL_NULL state). */
+        uint64_t    tag_type        : 2;    /**< The tag type attached to the core (updated when new tag list
+                                                entered on SWTAG, SWTAG_FULL, or SWTAG_DESCHED). */
+        uint64_t    tag             : 32;   /**< The tag attached to the core (updated when new tag list entered on
+                                                SWTAG, SWTAG_FULL, or SWTAG_DESCHED). */
+#else
+        uint64_t    tag             : 32;
+        uint64_t    tag_type        : 2;
+        uint64_t    tail            : 1;
+        uint64_t    head            : 1;
+        uint64_t    grp             : 4;
+        uint64_t    index           : 11;
+        uint64_t    revlink_index   : 11;
+        uint64_t    reserved_62_63  : 2;
+#endif
+    } s_sstatus3;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and get_rev==0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    link_index      : 11;    /**< Points to the next POW entry in the tag list when tail == 0 (and
+                                                tag_type is not NULL or NULL_NULL). */
+        uint64_t    index           : 11;   /**< The POW entry attached to the core. */
+        uint64_t    grp             : 4;    /**< The group attached to the core (updated when new tag list entered on SWTAG_FULL). */
+        uint64_t    wqp             : 36;   /**< The wqp attached to the core (updated when new tag list entered on SWTAG_FULL). */
+#else
+        uint64_t    wqp             : 36;
+        uint64_t    grp             : 4;
+        uint64_t    index           : 11;
+        uint64_t    link_index      : 11;
+        uint64_t    reserved_62_63  : 2;
+#endif
+    } s_sstatus4;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and get_rev==1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_62_63  : 2;
+        uint64_t    revlink_index   : 11;   /**< Points to the prior POW entry in the tag list when head == 0
+                                                (and tag_type is not NULL or NULL_NULL). This field is unpredictable
+                                                when the core's state is NULL or NULL_NULL. */
+        uint64_t    index           : 11;   /**< The POW entry attached to the core. */
+        uint64_t    grp             : 4;    /**< The group attached to the core (updated when new tag list entered on SWTAG_FULL). */
+        uint64_t    wqp             : 36;   /**< The wqp attached to the core (updated when new tag list entered on SWTAG_FULL). */
+#else
+        uint64_t    wqp             : 36;
+        uint64_t    grp             : 4;
+        uint64_t    index           : 11;
+        uint64_t    revlink_index   : 11;
+        uint64_t    reserved_62_63  : 2;
+#endif
+    } s_sstatus5;
+
+    /**
+     * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_51_63  : 13;
+        uint64_t    next_index      : 11;    /**< The next entry in the input, free, descheduled_head list
+                                                (unpredictable if entry is the tail of the list). */
+        uint64_t    grp             : 4;    /**< The group of the POW entry. */
+        uint64_t    reserved_35     : 1;
+        uint64_t    tail            : 1;    /**< Set when this POW entry is at the tail of its tag list (also set when in the
+                                                NULL or NULL_NULL state). */
+        uint64_t    tag_type        : 2;    /**< The tag type of the POW entry. */
+        uint64_t    tag             : 32;   /**< The tag of the POW entry. */
+#else
+        uint64_t    tag             : 32;
+        uint64_t    tag_type        : 2;
+        uint64_t    tail            : 1;
+        uint64_t    reserved_35     : 1;
+        uint64_t    grp             : 4;
+        uint64_t    next_index      : 11;
+        uint64_t    reserved_51_63  : 13;
+#endif
+    } s_smemload0;
+
+    /**
+     * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_51_63  : 13;
+        uint64_t    next_index      : 11;    /**< The next entry in the input, free, descheduled_head list
+                                                (unpredictable if entry is the tail of the list). */
+        uint64_t    grp             : 4;    /**< The group of the POW entry. */
+        uint64_t    wqp             : 36;   /**< The WQP held in the POW entry. */
+#else
+        uint64_t    wqp             : 36;
+        uint64_t    grp             : 4;
+        uint64_t    next_index      : 11;
+        uint64_t    reserved_51_63  : 13;
+#endif
+    } s_smemload1;
+
+    /**
+     * Result For POW Memory Load (get_des == 1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_51_63  : 13;
+        uint64_t    fwd_index       : 11;   /**< The next entry in the tag list connected to the descheduled head. */
+        uint64_t    grp             : 4;    /**< The group of the POW entry. */
+        uint64_t    nosched         : 1;    /**< The nosched bit for the POW entry. */
+        uint64_t    pend_switch     : 1;    /**< There is a pending tag switch */
+        uint64_t    pend_type       : 2;    /**< The next tag type for the new tag list when pend_switch is set. */
+        uint64_t    pend_tag        : 32;   /**< The next tag for the new tag list when pend_switch is set. */
+#else
+        uint64_t    pend_tag        : 32;
+        uint64_t    pend_type       : 2;
+        uint64_t    pend_switch     : 1;
+        uint64_t    nosched         : 1;
+        uint64_t    grp             : 4;
+        uint64_t    fwd_index       : 11;
+        uint64_t    reserved_51_63  : 13;
+#endif
+    } s_smemload2;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_52_63  : 12;
+        uint64_t    free_val        : 1;    /**< - set when there is one or more POW entries on the free list. */
+        uint64_t    free_one        : 1;    /**< - set when there is exactly one POW entry on the free list. */
+        uint64_t    reserved_49     : 1;
+        uint64_t    free_head       : 11;   /**< - when free_val is set, indicates the first entry on the free list. */
+        uint64_t    reserved_37     : 1;
+        uint64_t    free_tail       : 11;   /**< - when free_val is set, indicates the last entry on the free list. */
+        uint64_t    loc_val         : 1;    /**< - set when there is one or more POW entries on the input Q list selected by qosgrp. */
+        uint64_t    loc_one         : 1;    /**< - set when there is exactly one POW entry on the input Q list selected by qosgrp. */
+        uint64_t    reserved_23     : 1;
+        uint64_t    loc_head        : 11;   /**< - when loc_val is set, indicates the first entry on the input Q list selected by qosgrp. */
+        uint64_t    reserved_11     : 1;
+        uint64_t    loc_tail        : 11;   /**< - when loc_val is set, indicates the last entry on the input Q list selected by qosgrp. */
+#else
+        uint64_t    loc_tail        : 11;
+        uint64_t    reserved_11     : 1;
+        uint64_t    loc_head        : 11;
+        uint64_t    reserved_23     : 1;
+        uint64_t    loc_one         : 1;
+        uint64_t    loc_val         : 1;
+        uint64_t    free_tail       : 11;
+        uint64_t    reserved_37     : 1;
+        uint64_t    free_head       : 11;
+        uint64_t    reserved_49     : 1;
+        uint64_t    free_one        : 1;
+        uint64_t    free_val        : 1;
+        uint64_t    reserved_52_63  : 12;
+#endif
+    } sindexload0;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_52_63  : 12;
+        uint64_t    nosched_val     : 1;    /**< - set when there is one or more POW entries on the nosched list. */
+        uint64_t    nosched_one     : 1;    /**< - set when there is exactly one POW entry on the nosched list. */
+        uint64_t    reserved_49     : 1;
+        uint64_t    nosched_head    : 11;    /**< - when nosched_val is set, indicates the first entry on the nosched list. */
+        uint64_t    reserved_37     : 1;
+        uint64_t    nosched_tail    : 11;    /**< - when nosched_val is set, indicates the last entry on the nosched list. */
+        uint64_t    des_val         : 1;    /**< - set when there is one or more descheduled heads on the descheduled list selected by qosgrp. */
+        uint64_t    des_one         : 1;    /**< - set when there is exactly one descheduled head on the descheduled list selected by qosgrp. */
+        uint64_t    reserved_23     : 1;
+        uint64_t    des_head        : 11;    /**< - when des_val is set, indicates the first descheduled head on the descheduled list selected by qosgrp. */
+        uint64_t    reserved_11     : 1;
+        uint64_t    des_tail        : 11;    /**< - when des_val is set, indicates the last descheduled head on the descheduled list selected by qosgrp. */
+#else
+        uint64_t    des_tail        : 11;
+        uint64_t    reserved_11     : 1;
+        uint64_t    des_head        : 11;
+        uint64_t    reserved_23     : 1;
+        uint64_t    des_one         : 1;
+        uint64_t    des_val         : 1;
+        uint64_t    nosched_tail    : 11;
+        uint64_t    reserved_37     : 1;
+        uint64_t    nosched_head    : 11;
+        uint64_t    reserved_49     : 1;
+        uint64_t    nosched_one     : 1;
+        uint64_t    nosched_val     : 1;
+        uint64_t    reserved_52_63  : 12;
+#endif
+    } sindexload1;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_39_63  : 25;
+        uint64_t    rmt_is_head     : 1;    /**< Set when this DRAM list is the current head (i.e. is the next to
+                                                be reloaded when the POW hardware reloads a POW entry from DRAM). The
+                                                POW hardware alternates between the two DRAM lists associated with a QOS
+                                                level when it reloads work from DRAM into the POW unit. */
+        uint64_t    rmt_val         : 1;    /**< Set when the DRAM portion of the input Q list selected by qosgrp
+                                                contains one or more pieces of work. */
+        uint64_t    rmt_one         : 1;    /**< Set when the DRAM portion of the input Q list selected by qosgrp
+                                                contains exactly one piece of work. */
+        uint64_t    rmt_head        : 36;   /**< When rmt_val is set, indicates the first piece of work on the
+                                                DRAM input Q list selected by qosgrp. */
+#else
+        uint64_t    rmt_head        : 36;
+        uint64_t    rmt_one         : 1;
+        uint64_t    rmt_val         : 1;
+        uint64_t    rmt_is_head     : 1;
+        uint64_t    reserved_39_63  : 25;
+#endif
+    } sindexload2;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 1)
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    reserved_39_63  : 25;
+        uint64_t    rmt_is_head     : 1;    /**< - set when this DRAM list is the current head (i.e. is the next to
+                                                be reloaded when the POW hardware reloads a POW entry from DRAM). The
+                                                POW hardware alternates between the two DRAM lists associated with a QOS
+                                                level when it reloads work from DRAM into the POW unit. */
+        uint64_t    rmt_val         : 1;    /**< - set when the DRAM portion of the input Q list selected by qosgrp
+                                                contains one or more pieces of work. */
+        uint64_t    rmt_one         : 1;    /**< - set when the DRAM portion of the input Q list selected by qosgrp
+                                                contains exactly one piece of work. */
+        uint64_t    rmt_tail        : 36;   /**< - when rmt_val is set, indicates the last piece of work on the DRAM
+                                                input Q list selected by qosgrp. */
+#else
+        uint64_t    rmt_tail        : 36;
+        uint64_t    rmt_one         : 1;
+        uint64_t    rmt_val         : 1;
+        uint64_t    rmt_is_head     : 1;
+        uint64_t    reserved_39_63  : 25;
+#endif
+    } sindexload3;
+
+    /**
+     * Response to NULL_RD request loads
+     */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    unused  : 62;
+        uint64_t    state    : 2;  /**< of type cvmx_pow_tag_type_t. state is one of the following:
+                                        - CVMX_POW_TAG_TYPE_ORDERED
+                                        - CVMX_POW_TAG_TYPE_ATOMIC
+                                        - CVMX_POW_TAG_TYPE_NULL
+                                        - CVMX_POW_TAG_TYPE_NULL_NULL */
+#else
+        uint64_t    state    : 2;
+        uint64_t    unused  : 62;
+#endif
+    } s_null_rd;
+
+} cvmx_pow_tag_load_resp_t;
+
+/**
+ * This structure describes the address used for stores to the POW.
+ *  The store address is meaningful on stores to the POW.  The hardware assumes that an aligned
+ *  64-bit store was used for all these stores.
+ *  Note the assumption that the work queue entry is aligned on an 8-byte
+ *  boundary (since the low-order 3 address bits must be zero).
+ *  Note that not all fields are used by all operations.
+ *
+ *  NOTE: The following is the behavior of the pending switch bit at the PP
+ *       for POW stores (i.e. when did<7:3> == 0xc)
+ *     - did<2:0> == 0      => pending switch bit is set
+ *     - did<2:0> == 1      => no affect on the pending switch bit
+ *     - did<2:0> == 3      => pending switch bit is cleared
+ *     - did<2:0> == 7      => no affect on the pending switch bit
+ *     - did<2:0> == others => must not be used
+ *     - No other loads/stores have an affect on the pending switch bit
+ *     - The switch bus from POW can clear the pending switch bit
+ *
+ *  NOTE: did<2:0> == 2 is used by the HW for a special single-cycle ADDWQ command
+ *  that only contains the pointer). SW must never use did<2:0> == 2.
+ */
+typedef union
+{
+    /**
+     * Unsigned 64 bit integer representation of store address
+     */
+    uint64_t u64;
+
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    mem_reg         : 2;    /**< Memory region.  Should be CVMX_IO_SEG in most cases */
+        uint64_t    reserved_49_61  : 13;   /**< Must be zero */
+        uint64_t    is_io           : 1;    /**< Must be one */
+        uint64_t    did             : 8;    /**< Device ID of POW.  Note that different sub-dids are used. */
+        uint64_t    reserved_36_39  : 4;    /**< Must be zero */
+        uint64_t    addr            : 36;   /**< Address field. addr<2:0> must be zero */
+#else
+        uint64_t    addr            : 36;
+        uint64_t    reserved_36_39  : 4;
+        uint64_t    did             : 8;
+        uint64_t    is_io           : 1;
+        uint64_t    reserved_49_61  : 13;
+        uint64_t    mem_reg         : 2;
+#endif
+    } stag;
+} cvmx_pow_tag_store_addr_t;
+
+/**
+ * decode of the store data when an IOBDMA SENDSINGLE is sent to POW
+ */
+typedef union
+{
+    uint64_t u64;
+
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    scraddr : 8;    /**< the (64-bit word) location in scratchpad to write to (if len != 0) */
+        uint64_t    len     : 8;    /**< the number of words in the response (0 => no response) */
+        uint64_t    did     : 8;    /**< the ID of the device on the non-coherent bus */
+        uint64_t    unused  :36;
+        uint64_t    wait    : 1;    /**< if set, don't return load response until work is available */
+        uint64_t    unused2 : 3;
+#else
+        uint64_t    unused2 : 3;
+        uint64_t    wait    : 1;
+        uint64_t    unused  :36;
+        uint64_t    did     : 8;
+        uint64_t    len     : 8;
+        uint64_t    scraddr : 8;
+#endif
+    } s;
+
+} cvmx_pow_iobdma_store_t;
+
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Get the POW tag for this core. This returns the current
+ * tag type, tag, group, and POW entry index associated with
+ * this core. Index is only valid if the tag type isn't NULL_NULL.
+ * If a tag switch is pending this routine returns the tag before
+ * the tag switch, not after.
+ *
+ * @return Current tag
+ */
+static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
+{
+    cvmx_pow_load_addr_t load_addr;
+    cvmx_pow_tag_load_resp_t load_resp;
+    cvmx_pow_tag_req_t result;
+
+    load_addr.u64 = 0;
+    load_addr.sstatus.mem_region = CVMX_IO_SEG;
+    load_addr.sstatus.is_io = 1;
+    load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+    load_addr.sstatus.coreid = cvmx_get_core_num();
+    load_addr.sstatus.get_cur = 1;
+    load_resp.u64 = cvmx_read_csr(load_addr.u64);
+    result.u64 = 0;
+    result.s.grp = load_resp.s_sstatus2.grp;
+    result.s.index = load_resp.s_sstatus2.index;
+    result.s.type = (cvmx_pow_tag_type_t)load_resp.s_sstatus2.tag_type;
+    result.s.tag = load_resp.s_sstatus2.tag;
+    return result;
+}
+
+
+/**
+ * Get the POW WQE for this core. This returns the work queue
+ * entry currently associated with this core.
+ *
+ * @return WQE pointer
+ */
+static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
+{
+    cvmx_pow_load_addr_t load_addr;
+    cvmx_pow_tag_load_resp_t load_resp;
+
+    load_addr.u64 = 0;
+    load_addr.sstatus.mem_region = CVMX_IO_SEG;
+    load_addr.sstatus.is_io = 1;
+    load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+    load_addr.sstatus.coreid = cvmx_get_core_num();
+    load_addr.sstatus.get_cur = 1;
+    load_addr.sstatus.get_wqp = 1;
+    load_resp.u64 = cvmx_read_csr(load_addr.u64);
+    return (cvmx_wqe_t*)cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
+}
+
+
+/**
+ * @INTERNAL
+ * Print a warning if a tag switch is pending for this core
+ *
+ * @param function Function name checking for a pending tag switch
+ */
+static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
+{
+    uint64_t switch_complete;
+    CVMX_MF_CHORD(switch_complete);
+    cvmx_warn_if(!switch_complete, "%s called with tag switch in progress\n", function);
+}
+
+
+/**
+ * Waits for a tag switch to complete by polling the completion bit.
+ * Note that switches to NULL complete immediately and do not need
+ * to be waited for.
+ */
+static inline void cvmx_pow_tag_sw_wait(void)
+{
+    const uint64_t MAX_CYCLES = 1ull<<31;
+    uint64_t switch_complete;
+    uint64_t start_cycle = cvmx_get_cycle();
+    while (1)
+    {
+        CVMX_MF_CHORD(switch_complete);
+        if (cvmx_unlikely(switch_complete))
+            break;
+        if (cvmx_unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES))
+        {
+            cvmx_dprintf("WARNING: Tag switch is taking a long time, possible deadlock\n");
+            start_cycle = -MAX_CYCLES-1;
+        }
+    }
+}
+
+
+/**
+ * Synchronous work request.  Requests work from the POW.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that there is not a pending tag switch.
+ *
+ * @param wait   When set, call stalls until work becomes avaiable, or times out.
+ *               If not set, returns immediately.
+ *
+ * @return Returns the WQE pointer from POW. Returns NULL if no work was available.
+ */
+static inline cvmx_wqe_t * cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t wait)
+{
+    cvmx_pow_load_addr_t ptr;
+    cvmx_pow_tag_load_resp_t result;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    ptr.u64 = 0;
+    ptr.swork.mem_region = CVMX_IO_SEG;
+    ptr.swork.is_io = 1;
+    ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
+    ptr.swork.wait = wait;
+
+    result.u64 = cvmx_read_csr(ptr.u64);
+
+    if (result.s_work.no_work)
+        return NULL;
+    else
+        return (cvmx_wqe_t*)cvmx_phys_to_ptr(result.s_work.addr);
+}
+
+
+/**
+ * Synchronous work request.  Requests work from the POW.
+ * This function waits for any previous tag switch to complete before
+ * requesting the new work.
+ *
+ * @param wait   When set, call stalls until work becomes avaiable, or times out.
+ *               If not set, returns immediately.
+ *
+ * @return Returns the WQE pointer from POW. Returns NULL if no work was available.
+ */
+static inline cvmx_wqe_t * cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
+{
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Must not have a switch pending when requesting work */
+    cvmx_pow_tag_sw_wait();
+    return(cvmx_pow_work_request_sync_nocheck(wait));
+
+}
+
+
+/**
+ * Synchronous null_rd request.  Requests a switch out of NULL_NULL POW state.
+ * This function waits for any previous tag switch to complete before
+ * requesting the null_rd.
+ *
+ * @return Returns the POW state of type cvmx_pow_tag_type_t.
+ */
+static inline cvmx_pow_tag_type_t cvmx_pow_work_request_null_rd(void)
+{
+    cvmx_pow_load_addr_t ptr;
+    cvmx_pow_tag_load_resp_t result;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Must not have a switch pending when requesting work */
+    cvmx_pow_tag_sw_wait();
+
+    ptr.u64 = 0;
+    ptr.snull_rd.mem_region = CVMX_IO_SEG;
+    ptr.snull_rd.is_io = 1;
+    ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
+
+    result.u64 = cvmx_read_csr(ptr.u64);
+
+    return (cvmx_pow_tag_type_t)result.s_null_rd.state;
+}
+
+
+/**
+ * Asynchronous work request.  Work is requested from the POW unit, and should later
+ * be checked with function cvmx_pow_work_response_async.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that there is not a pending tag switch.
+ *
+ * @param scr_addr Scratch memory address that response will be returned to,
+ *                  which is either a valid WQE, or a response with the invalid bit set.
+ *                  Byte address, must be 8 byte aligned.
+ * @param wait      1 to cause response to wait for work to become available (or timeout)
+ *                  0 to cause response to return immediately
+ */
+static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, cvmx_pow_wait_t wait)
+{
+    cvmx_pow_iobdma_store_t data;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* scr_addr must be 8 byte aligned */
+    data.s.scraddr = scr_addr >> 3;
+    data.s.len = 1;
+    data.s.did = CVMX_OCT_DID_TAG_SWTAG;
+    data.s.wait = wait;
+    cvmx_send_single(data.u64);
+}
+/**
+ * Asynchronous work request.  Work is requested from the POW unit, and should later
+ * be checked with function cvmx_pow_work_response_async.
+ * This function waits for any previous tag switch to complete before
+ * requesting the new work.
+ *
+ * @param scr_addr Scratch memory address that response will be returned to,
+ *                  which is either a valid WQE, or a response with the invalid bit set.
+ *                  Byte address, must be 8 byte aligned.
+ * @param wait      1 to cause response to wait for work to become available (or timeout)
+ *                  0 to cause response to return immediately
+ */
+static inline void cvmx_pow_work_request_async(int scr_addr, cvmx_pow_wait_t wait)
+{
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Must not have a switch pending when requesting work */
+    cvmx_pow_tag_sw_wait();
+    cvmx_pow_work_request_async_nocheck(scr_addr, wait);
+}
+
+
+/**
+ * Gets result of asynchronous work request.  Performs a IOBDMA sync
+ * to wait for the response.
+ *
+ * @param scr_addr Scratch memory address to get result from
+ *                  Byte address, must be 8 byte aligned.
+ * @return Returns the WQE from the scratch register, or NULL if no work was available.
+ */
+static inline cvmx_wqe_t * cvmx_pow_work_response_async(int scr_addr)
+{
+    cvmx_pow_tag_load_resp_t result;
+
+    CVMX_SYNCIOBDMA;
+    result.u64 = cvmx_scratch_read64(scr_addr);
+
+    if (result.s_work.no_work)
+        return NULL;
+    else
+        return (cvmx_wqe_t*)cvmx_phys_to_ptr(result.s_work.addr);
+}
+
+
+/**
+ * Checks if a work queue entry pointer returned by a work
+ * request is valid.  It may be invalid due to no work
+ * being available or due to a timeout.
+ *
+ * @param wqe_ptr pointer to a work queue entry returned by the POW
+ *
+ * @return 0 if pointer is valid
+ *         1 if invalid (no work was returned)
+ */
+static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
+{
+    return (wqe_ptr == NULL);
+}
+
+
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.  Completion for
+ * the tag switch must be checked for separately.
+ * This function does NOT update the
+ * work queue entry in dram to match tag value and type, so the application must
+ * keep track of these if they are important to the application.
+ * This tag switch command must not be used for switches to NULL, as the tag
+ * switch pending bit will be set by the switch request, but never cleared by the
+ * hardware.
+ *
+ * NOTE: This should not be used when switching from a NULL tag.  Use
+ * cvmx_pow_tag_sw_full() instead.
+ *
+ * This function does no checks, so the caller must ensure that any previous tag
+ * switch has completed.
+ *
+ * @param tag      new tag value
+ * @param tag_type new tag type (ordered or atomic)
+ */
+static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, cvmx_pow_tag_type_t tag_type)
+{
+    cvmx_addr_t ptr;
+    cvmx_pow_tag_req_t tag_req;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+    {
+        cvmx_pow_tag_req_t current_tag;
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+        current_tag = cvmx_pow_get_current_tag();
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag\n", __FUNCTION__);
+        cvmx_warn_if((current_tag.s.type == tag_type) && (current_tag.s.tag == tag), "%s called to perform a tag switch to the same tag\n", __FUNCTION__);
+        cvmx_warn_if(tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n", __FUNCTION__);
+    }
+
+    /* Note that WQE in DRAM is not updated here, as the POW does not read from DRAM
+    ** once the WQE is in flight.  See hardware manual for complete details.
+    ** It is the application's responsibility to keep track of the current tag
+    ** value if that is important.
+    */
+
+
+    tag_req.u64 = 0;
+    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
+    tag_req.s.tag = tag;
+    tag_req.s.type = tag_type;
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region = CVMX_IO_SEG;
+    ptr.sio.is_io = 1;
+    ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
+
+    /* once this store arrives at POW, it will attempt the switch
+       software must wait for the switch to complete separately */
+    cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.  Completion for
+ * the tag switch must be checked for separately.
+ * This function does NOT update the
+ * work queue entry in dram to match tag value and type, so the application must
+ * keep track of these if they are important to the application.
+ * This tag switch command must not be used for switches to NULL, as the tag
+ * switch pending bit will be set by the switch request, but never cleared by the
+ * hardware.
+ *
+ * NOTE: This should not be used when switching from a NULL tag.  Use
+ * cvmx_pow_tag_sw_full() instead.
+ *
+ * This function waits for any previous tag switch to complete, and also
+ * displays an error on tag switches to NULL.
+ *
+ * @param tag      new tag value
+ * @param tag_type new tag type (ordered or atomic)
+ */
+static inline void cvmx_pow_tag_sw(uint32_t tag, cvmx_pow_tag_type_t tag_type)
+{
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Note that WQE in DRAM is not updated here, as the POW does not read from DRAM
+    ** once the WQE is in flight.  See hardware manual for complete details.
+    ** It is the application's responsibility to keep track of the current tag
+    ** value if that is important.
+    */
+
+    /* Ensure that there is not a pending tag switch, as a tag switch cannot be started
+    ** if a previous switch is still pending.  */
+    cvmx_pow_tag_sw_wait();
+    cvmx_pow_tag_sw_nocheck(tag, tag_type);
+}
+
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.  Completion for
+ * the tag switch must be checked for separately.
+ * This function does NOT update the
+ * work queue entry in dram to match tag value and type, so the application must
+ * keep track of these if they are important to the application.
+ * This tag switch command must not be used for switches to NULL, as the tag
+ * switch pending bit will be set by the switch request, but never cleared by the
+ * hardware.
+ *
+ * This function must be used for tag switches from NULL.
+ *
+ * This function does no checks, so the caller must ensure that any previous tag
+ * switch has completed.
+ *
+ * @param wqp      pointer to work queue entry to submit.  This entry is updated to match the other parameters
+ * @param tag      tag value to be assigned to work queue entry
+ * @param tag_type type of tag
+ * @param group      group value for the work queue entry.
+ */
+static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, cvmx_pow_tag_type_t tag_type, uint64_t group)
+{
+    cvmx_addr_t ptr;
+    cvmx_pow_tag_req_t tag_req;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+    {
+        cvmx_pow_tag_req_t current_tag;
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+        current_tag = cvmx_pow_get_current_tag();
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if((current_tag.s.type == tag_type) && (current_tag.s.tag == tag), "%s called to perform a tag switch to the same tag\n", __FUNCTION__);
+        cvmx_warn_if(tag_type == CVMX_POW_TAG_TYPE_NULL, "%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n", __FUNCTION__);
+        if (wqp != cvmx_phys_to_ptr(0x80))
+            cvmx_warn_if(wqp != cvmx_pow_get_current_wqp(), "%s passed WQE(%p) doesn't match the address in the POW(%p)\n", __FUNCTION__, wqp, cvmx_pow_get_current_wqp());
+    }
+
+    /* Note that WQE in DRAM is not updated here, as the POW does not read from DRAM
+    ** once the WQE is in flight.  See hardware manual for complete details.
+    ** It is the application's responsibility to keep track of the current tag
+    ** value if that is important.
+    */
+
+    tag_req.u64 = 0;
+    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
+    tag_req.s.tag = tag;
+    tag_req.s.type = tag_type;
+    tag_req.s.grp = group;
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region = CVMX_IO_SEG;
+    ptr.sio.is_io = 1;
+    ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
+    ptr.sio.offset = CAST64(wqp);
+
+    /* once this store arrives at POW, it will attempt the switch
+       software must wait for the switch to complete separately */
+    cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.  Completion for
+ * the tag switch must be checked for separately.
+ * This function does NOT update the
+ * work queue entry in dram to match tag value and type, so the application must
+ * keep track of these if they are important to the application.
+ * This tag switch command must not be used for switches to NULL, as the tag
+ * switch pending bit will be set by the switch request, but never cleared by the
+ * hardware.
+ *
+ * This function must be used for tag switches from NULL.
+ *
+ * This function waits for any pending tag switches to complete
+ * before requesting the tag switch.
+ *
+ * @param wqp      pointer to work queue entry to submit.  This entry is updated to match the other parameters
+ * @param tag      tag value to be assigned to work queue entry
+ * @param tag_type type of tag
+ * @param group      group value for the work queue entry.
+ */
+static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, cvmx_pow_tag_type_t tag_type, uint64_t group)
+{
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Ensure that there is not a pending tag switch, as a tag switch cannot be started
+    ** if a previous switch is still pending.  */
+    cvmx_pow_tag_sw_wait();
+    cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group);
+}
+
+
+/**
+ * Switch to a NULL tag, which ends any ordering or
+ * synchronization provided by the POW for the current
+ * work queue entry.  This operation completes immediatly,
+ * so completetion should not be waited for.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that any previous tag switches have completed.
+ */
+static inline void cvmx_pow_tag_sw_null_nocheck(void)
+{
+    cvmx_addr_t ptr;
+    cvmx_pow_tag_req_t tag_req;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+    {
+        cvmx_pow_tag_req_t current_tag;
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+        current_tag = cvmx_pow_get_current_tag();
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called when we already have a NULL tag\n", __FUNCTION__);
+    }
+
+    tag_req.u64 = 0;
+    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
+    tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
+
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region = CVMX_IO_SEG;
+    ptr.sio.is_io = 1;
+    ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
+
+
+    cvmx_write_io(ptr.u64, tag_req.u64);
+
+    /* switch to NULL completes immediately */
+}
+
+/**
+ * Switch to a NULL tag, which ends any ordering or
+ * synchronization provided by the POW for the current
+ * work queue entry.  This operation completes immediatly,
+ * so completetion should not be waited for.
+ * This function waits for any pending tag switches to complete
+ * before requesting the switch to NULL.
+ */
+static inline void cvmx_pow_tag_sw_null(void)
+{
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Ensure that there is not a pending tag switch, as a tag switch cannot be started
+    ** if a previous switch is still pending.  */
+    cvmx_pow_tag_sw_wait();
+    cvmx_pow_tag_sw_null_nocheck();
+
+    /* switch to NULL completes immediately */
+}
+
+
+
+/**
+ * Submits work to an input queue.  This function updates the work queue entry in DRAM to match
+ * the arguments given.
+ * Note that the tag provided is for the work queue entry submitted, and is unrelated to the tag that
+ * the core currently holds.
+ *
+ * @param wqp      pointer to work queue entry to submit.  This entry is updated to match the other parameters
+ * @param tag      tag value to be assigned to work queue entry
+ * @param tag_type type of tag
+ * @param qos      Input queue to add to.
+ * @param grp      group value for the work queue entry.
+ */
+static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, cvmx_pow_tag_type_t tag_type, uint64_t qos, uint64_t grp)
+{
+    cvmx_addr_t ptr;
+    cvmx_pow_tag_req_t tag_req;
+
+    wqp->qos = qos;
+    wqp->tag = tag;
+    wqp->tag_type = tag_type;
+    wqp->grp = grp;
+
+    tag_req.u64 = 0;
+    tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
+    tag_req.s.type = tag_type;
+    tag_req.s.tag = tag;
+    tag_req.s.qos = qos;
+    tag_req.s.grp = grp;
+
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region = CVMX_IO_SEG;
+    ptr.sio.is_io = 1;
+    ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
+    ptr.sio.offset = cvmx_ptr_to_phys(wqp);
+
+    /* SYNC write to memory before the work submit.  This is necessary
+    ** as POW may read values from DRAM at this time */
+    CVMX_SYNCWS;
+    cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+
+
+/**
+ * This function sets the group mask for a core.  The group mask
+ * indicates which groups each core will accept work from. There are
+ * 16 groups.
+ *
+ * @param core_num   core to apply mask to
+ * @param mask   Group mask. There are 16 groups, so only bits 0-15 are valid,
+ *               representing groups 0-15.
+ *               Each 1 bit in the mask enables the core to accept work from
+ *               the corresponding group.
+ */
+static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
+{
+    cvmx_pow_pp_grp_mskx_t grp_msk;
+
+    grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+    grp_msk.s.grp_msk = mask;
+    cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+}
+
+/**
+ * This function sets POW static priorities for a core. Each input queue has
+ * an associated priority value.
+ *
+ * @param core_num   core to apply priorities to
+ * @param priority   Vector of 8 priorities, one per POW Input Queue (0-7).
+ *                   Highest priority is 0 and lowest is 7. A priority value
+ *                   of 0xF instructs POW to skip the Input Queue when
+ *                   scheduling to this specific core.
+ *                   NOTE: priorities should not have gaps in values, meaning
+ *                         {0,1,1,1,1,1,1,1} is a valid configuration while
+ *                         {0,2,2,2,2,2,2,2} is not.
+ */
+static inline void cvmx_pow_set_priority(uint64_t core_num, const uint8_t priority[])
+{
+    /* POW priorities are supported on CN5xxx and later */
+    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+    {
+        cvmx_pow_pp_grp_mskx_t grp_msk;
+
+        grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+        grp_msk.s.qos0_pri = priority[0];
+        grp_msk.s.qos1_pri = priority[1];
+        grp_msk.s.qos2_pri = priority[2];
+        grp_msk.s.qos3_pri = priority[3];
+        grp_msk.s.qos4_pri = priority[4];
+        grp_msk.s.qos5_pri = priority[5];
+        grp_msk.s.qos6_pri = priority[6];
+        grp_msk.s.qos7_pri = priority[7];
+
+        /* Detect gaps between priorities and flag error */
+        {
+            int i;
+            uint32_t prio_mask = 0;
+
+            for(i=0; i<8; i++)
+               if (priority[i] != 0xF)
+		   prio_mask |= 1<<priority[i];
+
+            if ( prio_mask ^ ((1<<cvmx_pop(prio_mask)) - 1))
+            {
+                cvmx_dprintf("ERROR: POW static priorities should be contiguous (0x%llx)\n", (unsigned long long)prio_mask);
+                return;
+            }
+        }
+
+        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+    }
+}
+
+/**
+ * Performs a tag switch and then an immediate deschedule. This completes
+ * immediatly, so completion must not be waited for.  This function does NOT
+ * update the wqe in DRAM to match arguments.
+ *
+ * This function does NOT wait for any prior tag switches to complete, so the
+ * calling code must do this.
+ *
+ * Note the following CAVEAT of the Octeon HW behavior when
+ * re-scheduling DE-SCHEDULEd items whose (next) state is
+ * ORDERED:
+ *   - If there are no switches pending at the time that the
+ *     HW executes the de-schedule, the HW will only re-schedule
+ *     the head of the FIFO associated with the given tag. This
+ *     means that in many respects, the HW treats this ORDERED
+ *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
+ *     case (to an ORDERED tag), the HW will do the switch
+ *     before the deschedule whenever it is possible to do
+ *     the switch immediately, so it may often look like
+ *     this case.
+ *   - If there is a pending switch to ORDERED at the time
+ *     the HW executes the de-schedule, the HW will perform
+ *     the switch at the time it re-schedules, and will be
+ *     able to reschedule any/all of the entries with the
+ *     same tag.
+ * Due to this behavior, the RECOMMENDATION to software is
+ * that they have a (next) state of ATOMIC when they
+ * DE-SCHEDULE. If an ORDERED tag is what was really desired,
+ * SW can choose to immediately switch to an ORDERED tag
+ * after the work (that has an ATOMIC tag) is re-scheduled.
+ * Note that since there are never any tag switches pending
+ * when the HW re-schedules, this switch can be IMMEDIATE upon
+ * the reception of the pointer during the re-schedule.
+ *
+ * @param tag      New tag value
+ * @param tag_type New tag type
+ * @param group    New group value
+ * @param no_sched Control whether this work queue entry will be rescheduled.
+ *                 - 1 : don't schedule this work
+ *                 - 0 : allow this work to be scheduled.
+ */
+static inline void cvmx_pow_tag_sw_desched_nocheck(uint32_t tag, cvmx_pow_tag_type_t tag_type, uint64_t group, uint64_t no_sched)
+{
+    cvmx_addr_t ptr;
+    cvmx_pow_tag_req_t tag_req;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+    {
+        cvmx_pow_tag_req_t current_tag;
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+        current_tag = cvmx_pow_get_current_tag();
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag. Deschedule not allowed from NULL state\n", __FUNCTION__);
+        cvmx_warn_if((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC), "%s called where neither the before or after tag is ATOMIC\n", __FUNCTION__);
+    }
+
+    tag_req.u64 = 0;
+    tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
+    tag_req.s.tag = tag;
+    tag_req.s.type = tag_type;
+    tag_req.s.grp = group;
+    tag_req.s.no_sched = no_sched;
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region = CVMX_IO_SEG;
+    ptr.sio.is_io = 1;
+    ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
+
+    cvmx_write_io(ptr.u64, tag_req.u64); // since TAG3 is used, this store will clear the local pending switch bit
+}
+/**
+ * Performs a tag switch and then an immediate deschedule. This completes
+ * immediatly, so completion must not be waited for.  This function does NOT
+ * update the wqe in DRAM to match arguments.
+ *
+ * This function waits for any prior tag switches to complete, so the
+ * calling code may call this function with a pending tag switch.
+ *
+ * Note the following CAVEAT of the Octeon HW behavior when
+ * re-scheduling DE-SCHEDULEd items whose (next) state is
+ * ORDERED:
+ *   - If there are no switches pending at the time that the
+ *     HW executes the de-schedule, the HW will only re-schedule
+ *     the head of the FIFO associated with the given tag. This
+ *     means that in many respects, the HW treats this ORDERED
+ *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
+ *     case (to an ORDERED tag), the HW will do the switch
+ *     before the deschedule whenever it is possible to do
+ *     the switch immediately, so it may often look like
+ *     this case.
+ *   - If there is a pending switch to ORDERED at the time
+ *     the HW executes the de-schedule, the HW will perform
+ *     the switch at the time it re-schedules, and will be
+ *     able to reschedule any/all of the entries with the
+ *     same tag.
+ * Due to this behavior, the RECOMMENDATION to software is
+ * that they have a (next) state of ATOMIC when they
+ * DE-SCHEDULE. If an ORDERED tag is what was really desired,
+ * SW can choose to immediately switch to an ORDERED tag
+ * after the work (that has an ATOMIC tag) is re-scheduled.
+ * Note that since there are never any tag switches pending
+ * when the HW re-schedules, this switch can be IMMEDIATE upon
+ * the reception of the pointer during the re-schedule.
+ *
+ * @param tag      New tag value
+ * @param tag_type New tag type
+ * @param group    New group value
+ * @param no_sched Control whether this work queue entry will be rescheduled.
+ *                 - 1 : don't schedule this work
+ *                 - 0 : allow this work to be scheduled.
+ */
+static inline void cvmx_pow_tag_sw_desched(uint32_t tag, cvmx_pow_tag_type_t tag_type, uint64_t group, uint64_t no_sched)
+{
+    if (CVMX_ENABLE_POW_CHECKS)
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+
+    /* Need to make sure any writes to the work queue entry are complete */
+    CVMX_SYNCWS;
+    /* Ensure that there is not a pending tag switch, as a tag switch cannot be started
+    ** if a previous switch is still pending.  */
+    cvmx_pow_tag_sw_wait();
+    cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched);
+}
+
+
+
+
+
+/**
+ * Descchedules the current work queue entry.
+ *
+ * @param no_sched no schedule flag value to be set on the work queue entry.  If this is set
+ *                 the entry will not be rescheduled.
+ */
+static inline void cvmx_pow_desched(uint64_t no_sched)
+{
+    cvmx_addr_t ptr;
+    cvmx_pow_tag_req_t tag_req;
+
+    if (CVMX_ENABLE_POW_CHECKS)
+    {
+        cvmx_pow_tag_req_t current_tag;
+        __cvmx_pow_warn_if_pending_switch(__FUNCTION__);
+        current_tag = cvmx_pow_get_current_tag();
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL, "%s called with NULL_NULL tag\n", __FUNCTION__);
+        cvmx_warn_if(current_tag.s.type == CVMX_POW_TAG_TYPE_NULL, "%s called with NULL tag. Deschedule not expected from NULL state\n", __FUNCTION__);
+    }
+
+    /* Need to make sure any writes to the work queue entry are complete */
+    CVMX_SYNCWS;
+
+    tag_req.u64 = 0;
+    tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
+    tag_req.s.no_sched = no_sched;
+
+    ptr.u64 = 0;
+    ptr.sio.mem_region = CVMX_IO_SEG;
+    ptr.sio.is_io = 1;
+    ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
+
+    cvmx_write_io(ptr.u64, tag_req.u64); // since TAG3 is used, this store will clear the local pending switch bit
+}
+
+
+
+
+
+
+
+/***********************************************************************************************
+** Define usage of bits within the 32 bit tag values.
+***********************************************************************************************/
+
+/*
+ * Number of bits of the tag used by software.  The SW bits
+ * are always a contiguous block of the high starting at bit 31.
+ * The hardware bits are always the low bits.  By default, the top 8 bits
+ * of the tag are reserved for software, and the low 24 are set by the IPD unit.
+ */
+#define CVMX_TAG_SW_BITS    (8)
+#define CVMX_TAG_SW_SHIFT   (32 - CVMX_TAG_SW_BITS)
+
+/* Below is the list of values for the top 8 bits of the tag. */
+#define CVMX_TAG_SW_BITS_INTERNAL  0x1  /* Tag values with top byte of this value are reserved for internal executive uses */
+/* The executive divides the remaining 24 bits as follows:
+**  * the upper 8 bits (bits 23 - 16 of the tag) define a subgroup
+**  * the lower 16 bits (bits 15 - 0 of the tag) define are the value with the subgroup
+** Note that this section describes the format of tags generated by software - refer to the
+** hardware documentation for a description of the tags values generated by the packet input
+** hardware.
+** Subgroups are defined here */
+#define CVMX_TAG_SUBGROUP_MASK  0xFFFF /* Mask for the value portion of the tag */
+#define CVMX_TAG_SUBGROUP_SHIFT 16
+#define CVMX_TAG_SUBGROUP_PKO  0x1
+
+
+/* End of executive tag subgroup definitions */
+
+/* The remaining values software bit values 0x2 - 0xff are available for application use */
+
+
+
+/**
+ * This function creates a 32 bit tag value from the two values provided.
+ *
+ * @param sw_bits The upper bits (number depends on configuration) are set to this value.  The remainder of
+ *                bits are set by the hw_bits parameter.
+ * @param hw_bits The lower bits (number depends on configuration) are set to this value.  The remainder of
+ *                bits are set by the sw_bits parameter.
+ *
+ * @return 32 bit value of the combined hw and sw bits.
+ */
+static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits)
+{
+    return((((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) << CVMX_TAG_SW_SHIFT) | (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS))));
+}
+/**
+ * Extracts the bits allocated for software use from the tag
+ *
+ * @param tag    32 bit tag value
+ *
+ * @return N bit software tag value, where N is configurable with the CVMX_TAG_SW_BITS define
+ */
+static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag)
+{
+    return((tag >> (32 - CVMX_TAG_SW_BITS)) & cvmx_build_mask(CVMX_TAG_SW_BITS));
+}
+/**
+ *
+ * Extracts the bits allocated for hardware use from the tag
+ *
+ * @param tag    32 bit tag value
+ *
+ * @return (32 - N) bit software tag value, where N is configurable with the CVMX_TAG_SW_BITS define
+ */
+static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
+{
+    return(tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS));
+}
+
+/**
+ * Store the current POW internal state into the supplied
+ * buffer. It is recommended that you pass a buffer of at least
+ * 128KB. The format of the capture may change based on SDK
+ * version and Octeon chip.
+ *
+ * @param buffer Buffer to store capture into
+ * @param buffer_size
+ *               The size of the supplied buffer
+ *
+ * @return Zero on sucess, negative on failure
+ */
+extern int cvmx_pow_capture(void *buffer, int buffer_size);
+
+/**
+ * Dump a POW capture to the console in a human readable format.
+ *
+ * @param buffer POW capture from cvmx_pow_capture()
+ * @param buffer_size
+ *               Size of the buffer
+ */
+extern void cvmx_pow_display(void *buffer, int buffer_size);
+
+/**
+ * Return the number of POW entries supported by this chip
+ *
+ * @return Number of POW entries
+ */
+extern int cvmx_pow_get_num_entries(void);
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  // __CVMX_POW_H__
diff --git a/cvmx-raid.c b/cvmx-raid.c
new file mode 100644
index 0000000000000..9867f8ea98f3c
--- /dev/null
+++ b/cvmx-raid.c
@@ -0,0 +1,132 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to RAID block. This is not available on all chips.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-cmd-queue.h"
+#include "cvmx-raid.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+/**
+ * Initialize the RAID block
+ *
+ * @param polynomial Coefficients for the RAID polynomial
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_raid_initialize(cvmx_rad_reg_polynomial_t polynomial)
+{
+    cvmx_cmd_queue_result_t result;
+    cvmx_rad_reg_cmd_buf_t rad_reg_cmd_buf;
+
+    cvmx_write_csr(CVMX_RAD_REG_POLYNOMIAL, polynomial.u64);
+
+    result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_RAID, 0,
+                                       CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                       CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
+    if (result != CVMX_CMD_QUEUE_SUCCESS)
+        return -1;
+
+    rad_reg_cmd_buf.u64 = 0;
+    rad_reg_cmd_buf.s.dwb = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
+    rad_reg_cmd_buf.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
+    rad_reg_cmd_buf.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
+    rad_reg_cmd_buf.s.ptr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_RAID))>>7;
+    cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, rad_reg_cmd_buf.u64);
+    return 0;
+}
+
+
+/**
+ * Shutdown the RAID block. RAID must be idle when
+ * this function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_raid_shutdown(void)
+{
+    cvmx_rad_reg_ctl_t rad_reg_ctl;
+
+    if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_RAID))
+    {
+        cvmx_dprintf("ERROR: cvmx_raid_shutdown: RAID not idle.\n");
+        return -1;
+    }
+
+    rad_reg_ctl.u64 = cvmx_read_csr(CVMX_RAD_REG_CTL);
+    rad_reg_ctl.s.reset = 1;
+    cvmx_write_csr(CVMX_RAD_REG_CTL, rad_reg_ctl.u64);
+    cvmx_wait(100);
+
+    cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_RAID);
+    cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, 0);
+    return 0;
+}
+
+
+/**
+ * Submit a command to the RAID block
+ *
+ * @param num_words Number of command words to submit
+ * @param words     Command words
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_raid_submit(int num_words, cvmx_raid_word_t words[])
+{
+    cvmx_cmd_queue_result_t result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_RAID, 1, num_words, (uint64_t *)words);
+    if (result == CVMX_CMD_QUEUE_SUCCESS)
+        cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(14, 0)), num_words);
+    return result;
+}
+
+#endif
diff --git a/cvmx-raid.h b/cvmx-raid.h
new file mode 100644
index 0000000000000..88dde4feb662c
--- /dev/null
+++ b/cvmx-raid.h
@@ -0,0 +1,202 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to RAID block. This is not available on all chips.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_RAID_H__
+#define __CVMX_RAID_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * This structure defines the type of command words the RAID block
+ * will accept.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t    reserved_37_63  : 27;   /**< Must be zero */
+        uint64_t    q_cmp           :  1;   /**< Indicates whether the Q pipe is in normal mode (CWORD[Q_CMP]=0) or in non-zero
+                                                byte detect mode (CWORD[Q_CMP]=1).
+                                                In non-zero byte detect mode, the Q OWORD[PTR] result is the non-zero detect
+                                                result, which indicates the position of the first non-zero byte in the pipe result bytes.
+                                                CWORD[Q_CMP] must not be set when CWORD[QOUT]=0, and must not be set
+                                                when CWORD[Q_XOR] is set. */
+        uint64_t    p_cmp           :  1;   /**< Indicates whether the P pipe is in normal mode (CWORD[P_CMP]=0) or in non-zero
+                                                byte detect mode (CWORD[P_CMP]=1).
+                                                In non-zero byte detect mode, the P OWORD[PTR] result is the non-zero detect
+                                                result, which indicates the position of the first non-zero byte in the pipe result bytes.
+                                                CWORD[P_CMP] must not be set when CWORD[POUT]=0, and must not be set
+                                                when CWORD[P_XOR] is set. */
+        uint64_t    q_xor           :  1;   /**< Indicates whether the Q output buffer bytes are the normal Q pipe result or the
+                                                normal Q pipe result exclusive-OR'ed with the P pipe result.
+                                                When CWORD[Q_XOR]=0 (and CWORD[Q_CMP]=0), the Q output buffer bytes are
+                                                the normal Q pipe result, which does not include the P pipe result in any way.
+                                                When CWORD[Q_XOR]=1, the Q output buffer bytes are the normal Q pipe result
+                                                exclusive-OR'ed with the P pipe result, as if the P pipe result were another Q IWORD
+                                                for the Q pipe with QMULT=1.
+                                                CWORD[Q_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and
+                                                must not be set when CWORD[Q_CMP] is set. */
+        uint64_t    p_xor           :  1;   /**< Indicates whether the P output buffer bytes are the normal P pipe result or the
+                                                normal P pipe result exclusive-OR'ed with the Q pipe result.
+                                                When CWORD[P_XOR]=0 (and CWORD[P_CMP]=0), the P output buffer bytes are
+                                                the normal P pipe result, which does not include the Q pipe result in any way.
+                                                When CWORD[P_XOR]=1, the P output buffer bytes are the normal P pipe result
+                                                exclusive-OR'ed with the Q pipe result, as if the Q pipe result were another P
+                                                IWORD for the P pipe.
+                                                CWORD[P_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and
+                                                must not be set when CWORD[P_CMP] is set. */
+        uint64_t    wqe             :  1;   /**< Indicates whether RAD submits a work queue entry or writes an L2/DRAM byte to
+                                                zero after completing the instruction.
+                                                When CWORD[WQE] is set and RESP[PTR]!=0, RAD adds the work queue entry
+                                                indicated by RESP[PTR] to the selected POW input queue after completing the
+                                                instruction.
+                                                When CWORD[WQE] is clear and RESP[PTR]!=0, RAD writes the L2/DRAM byte
+                                                indicated by RESP[PTR] to zero after completing the instruction. */
+        uint64_t    qout            :  1;   /**< Indicates whether the Q pipe is used by this instruction.
+                                                If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD.
+                                                At least one of CWORD[QOUT,POUT] must be set. */
+        uint64_t    pout            :  1;   /**< Indicates whether the P pipe is used by this instruction.
+                                                If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD.
+                                                At least one of CWORD[QOUT,POUT] must be set. */
+        uint64_t    iword           :  6;   /**< Indicates the number of input buffers used.
+                                                1 <= CWORD[IWORD] <= 32. */
+        uint64_t    size            : 24;   /**< Indicates the size in bytes of all input buffers. When CWORD[Q_CMP,P_CMP]=0,
+                                                also indicates the size of the Q/P output buffers.
+                                                CWORD[SIZE] must be a multiple of 8B (i.e. <2:0> must be zero). */
+    } cword;
+    struct
+    {
+        uint64_t    reserved_58_63  :  6;   /**< Must be zero */
+        uint64_t    fw              :  1;   /**< When set, indicates that RAD can modify any byte in any (128B) cache line touched
+                                                by L2/DRAM addresses OWORD[PTR] through OWORD[PTR]+CWORD[SIZE]­1.
+                                                Setting OWORD[FW] can improve hardware performance, as some DRAM loads can
+                                                be avoided on L2 cache misses. The Q OWORD[FW] must not be set when
+                                                CWORD[Q_CMP] is set, and the P OWORD[FW] must not be set when
+                                                CWORD[P_CMP] is set. */
+        uint64_t    nc              :  1;   /**< When set, indicates that RAD should not allocate L2 cache space for the P/Q data on
+                                                L2 cache misses.
+                                                OWORD[NC] should typically be clear, though setting OWORD[NC] can improve
+                                                performance in some circumstances, as the L2 cache will not be polluted by P/Q data.
+                                                The Q OWORD[NC] must not be set when CWORD[Q_CMP] is set, and the P
+                                                OWORD[NC] must not be set when CWORD[P_CMP] is set. */
+        uint64_t    reserved_40_55  : 16;   /**< Must be zero */
+        uint64_t    addr            : 40;   /**< When CWORD[P_CMP,Q_CMP]=0, OWORD[PTR] indicates the starting address of
+                                                the L2/DRAM buffer that will receive the P/Q data. In the non-compare mode, the
+                                                output buffer receives all of the output buffer bytes.
+                                                When CWORD[P_CMP,Q_CMP]=1, the corresponding P/Q pipe is in compare mode,
+                                                and the only output of the pipe is the non-zero detect result. In this case,
+                                                OWORD[PTR] indicates the 8-byte location of the non-zero detect result. */
+    } oword;
+    struct
+    {
+        uint64_t    reserved_57_63  :  7;   /**< Must be zero */
+        uint64_t    nc              :  1;   /**< When set, indicates that RAD should not allocate L2 cache space for this input buffer
+                                                data on L2 cache misses.
+                                                Setting IWORD[NC] may improve performance in some circumstances, as the L2
+                                                cache may not be polluted with input buffer data. */
+        uint64_t    reserved_50_55  :  6;   /**< Must be zero */
+        uint64_t    qen             :  1;   /**< Indicates that this input buffer data should participate in the Q pipe result.
+                                                The Q pipe hardware multiplies each participating input byte by IWORD[QMULT]
+                                                before accumulating them by exclusive-OR'ing.
+                                                IWORD[QEN] must not be set when CWORD[QOUT] is not set.
+                                                If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. */
+        uint64_t    pen             :  1;   /**< Indicates that this input buffer data should participate in the P pipe result.
+                                                The P pipe hardware accumulates each participating input byte by bit-wise
+                                                exclusive-OR'ing it.
+                                                IWORD[PEN] must not be set when CWORD[POUT] is not set.
+                                                If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. */
+        uint64_t    qmult           :  8;   /**< The Q pipe multiplier for the input buffer. Section 26.1 above describes the GF(28)
+                                                multiplication algorithm.
+                                                IWORD[QMULT] must be zero when IWORD[QEN] is not set.
+                                                IWORD[QMULT] must not be zero when IWORD[QEN] is set.
+                                                When IWORD[QMULT] is 1, the multiplication simplifies to the identity function,
+                                                and the Q pipe performs the same XOR function as the P pipe. */
+        uint64_t    addr            : 40;   /**< The starting address of the input buffer in L2/DRAM.
+                                                IWORD[PTR] must be naturally-aligned on an 8 byte boundary (i.e. <2:0> must be
+                                                zero). */
+    } iword;
+} cvmx_raid_word_t;
+
+/**
+ * Initialize the RAID block
+ *
+ * @param polynomial Coefficients for the RAID polynomial
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_raid_initialize(cvmx_rad_reg_polynomial_t polynomial);
+
+/**
+ * Shutdown the RAID block. RAID must be idle when
+ * this function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_raid_shutdown(void);
+
+/**
+ * Submit a command to the RAID block
+ *
+ * @param num_words Number of command words to submit
+ * @param words     Command words
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_raid_submit(int num_words, cvmx_raid_word_t words[]);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif // __CVMX_CMD_QUEUE_H__
diff --git a/cvmx-resources.config b/cvmx-resources.config
new file mode 100644
index 0000000000000..3bd53f7d22184
--- /dev/null
+++ b/cvmx-resources.config
@@ -0,0 +1,172 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/*
+ * File version info: $Id: cvmx-resources.config 42150 2009-04-10 21:43:27Z pkapoor $
+ *
+ */
+#ifndef __CVMX_RESOURCES_CONFIG__
+#define __CVMX_RESOURCES_CONFIG__
+
+
+#if (CVMX_HELPER_FIRST_MBUFF_SKIP > 256)
+#error CVMX_HELPER_FIRST_MBUFF_SKIP is greater than the maximum of 256
+#endif
+
+#if (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP > 256)
+#error CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is greater than the maximum of 256
+#endif
+
+
+/* Content below this point is only used by the cvmx-config tool, and is
+** not used by any C files as CAVIUM_COMPONENT_REQUIREMENT is never
+defined.
+*/
+ #ifdef CAVIUM_COMPONENT_REQUIREMENT
+    /* Define the number of LLM ports (interfaces), can be 1 or 2 */
+    cvmxconfig
+    {
+    	#if CVMX_LLM_CONFIG_NUM_PORTS == 2
+            define CVMX_LLM_NUM_PORTS value = 2;
+	#else
+            define CVMX_LLM_NUM_PORTS value = 1;
+	#endif
+    }
+    /* Control the setting of Null pointer detection, default to enabled */
+    cvmxconfig {
+    	#ifdef CVMX_CONFIG_NULL_POINTER_PROTECT
+            define CVMX_NULL_POINTER_PROTECT value = CVMX_CONFIG_NULL_POINTER_PROTECT;
+	#else
+            define CVMX_NULL_POINTER_PROTECT value = 1;
+	#endif
+    }
+    /* Control Debug prints, default to enabled */
+    cvmxconfig {
+    	#ifdef CVMX_CONFIG_ENABLE_DEBUG_PRINTS
+            define CVMX_ENABLE_DEBUG_PRINTS value = CVMX_CONFIG_ENABLE_DEBUG_PRINTS;
+	#else
+            define CVMX_ENABLE_DEBUG_PRINTS value = 1;
+	#endif
+    }
+
+    /* Define CVMX_ENABLE_DFA_FUNCTIONS to allocate resources for the DFA functions */
+    #ifdef CVMX_ENABLE_DFA_FUNCTIONS
+        cvmxconfig
+        {
+        	fpa CVMX_FPA_DFA_POOL
+                    size        = 2
+                    protected   = 1
+                    description = "DFA command buffers";
+        	fau CVMX_FAU_DFA_STATE
+                    size        = 8
+                    count       = 1
+                    description = "FAU registers for the state of the DFA command queue";
+        }
+    #endif
+
+    /* Define CVMX_ENABLE_PKO_FUNCTIONS to allocate resources for the PKO functions */
+    #ifdef CVMX_ENABLE_PKO_FUNCTIONS
+        cvmxconfig
+        {
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0
+		    description = "PKO queues per port for interface 0 (ports 0-15)";
+		define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1
+		    value       = CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1
+		    description = "PKO queues per port for interface 1 (ports 16-31)";
+                define CVMX_PKO_MAX_PORTS_INTERFACE0
+                    value       = CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+                    description = "Limit on the number of PKO ports enabled for interface 0";
+                define CVMX_PKO_MAX_PORTS_INTERFACE1
+                    value       = CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+                    description = "Limit on the number of PKO ports enabled for interface 1";
+		define CVMX_PKO_QUEUES_PER_PORT_PCI
+		    value       = 1
+		    description = "PKO queues per port for PCI (ports 32-35)";
+		define CVMX_PKO_QUEUES_PER_PORT_LOOP
+		    value       = 1
+		    description = "PKO queues per port for Loop devices (ports 36-39)";
+        	fpa CVMX_FPA_PACKET_POOL
+                    pool        = 0
+                    size        = 16
+                    priority    = 1
+                    protected   = 1
+                    description = "Packet buffers";
+        	fpa CVMX_FPA_OUTPUT_BUFFER_POOL
+                    size        = 8
+                    protected   = 1
+                    description = "PKO queue command buffers";
+        	scratch CVMX_SCR_SCRATCH
+                    size        = 8
+                    iobdma      = true
+                    permanent   = false
+                    description = "Generic scratch iobdma area";
+        }
+    #endif
+
+    /* Define CVMX_ENABLE_HELPER_FUNCTIONS to allocate resources for the helper functions */
+    #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
+        cvmxconfig
+        {
+        	fpa CVMX_FPA_WQE_POOL
+                    size        = 1
+                    priority    = 1
+                    protected   = 1
+                    description = "Work queue entrys";
+        }
+    #endif
+
+    /* Define CVMX_ENABLE_TIMER_FUNCTIONS to allocate resources for the timer functions */
+    #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+        cvmxconfig
+        {
+        	fpa CVMX_FPA_TIMER_POOL
+                    size        = 8
+                    protected   = 1
+                    description = "TIM command buffers";
+        }
+    #endif
+
+#endif
+
+
+#endif  /* __CVMX_RESOURCES_CONFIG__ */
diff --git a/cvmx-rng.h b/cvmx-rng.h
new file mode 100644
index 0000000000000..a70888154e5d0
--- /dev/null
+++ b/cvmx-rng.h
@@ -0,0 +1,162 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Function and structure definitions for random number generator hardware
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+#ifndef __CMVX_RNG_H__
+#define __CMVX_RNG_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_RNG_LOAD_ADDRESS   CVMX_ADD_IO_SEG(cvmx_build_io_address(CVMX_OCT_DID_RNG, 0))
+
+/**
+ * Structure describing the data format used for IOBDMA stores to the RNG.
+ */
+typedef union
+{
+    uint64_t        u64;
+    struct {
+        uint64_t    scraddr : 8;    /**< the (64-bit word) location in scratchpad to write to (if len != 0) */
+        uint64_t    len     : 8;    /**< the number of words in the response (0 => no response) */
+        uint64_t    did     : 5;    /**< the ID of the device on the non-coherent bus */
+        uint64_t    subdid  : 3;    /**< the sub ID of the device on the non-coherent bus */
+        uint64_t    addr    :40;    /**< the address that will appear in the first tick on the NCB bus */
+    } s;
+} cvmx_rng_iobdma_data_t;
+
+/**
+ * Enables the random number generator. Must be called before RNG is used
+ */
+static inline void cvmx_rng_enable(void)
+{
+    cvmx_rnm_ctl_status_t rnm_ctl_status;
+    rnm_ctl_status.u64 = 0;
+    rnm_ctl_status.s.ent_en = 1;
+    rnm_ctl_status.s.rng_en = 1;
+    cvmx_write_csr(CVMX_RNM_CTL_STATUS, rnm_ctl_status.u64);
+}
+/**
+ * Reads 8 bits of random data from Random number generator
+ *
+ * @return random data
+ */
+static inline uint8_t cvmx_rng_get_random8(void)
+{
+    return cvmx_read64_uint8(CVMX_RNG_LOAD_ADDRESS);
+}
+
+/**
+ * Reads 16 bits of random data from Random number generator
+ *
+ * @return random data
+ */
+static inline uint16_t cvmx_rng_get_random16(void)
+{
+    return cvmx_read64_uint16(CVMX_RNG_LOAD_ADDRESS);
+}
+
+/**
+ * Reads 32 bits of random data from Random number generator
+ *
+ * @return random data
+ */
+static inline uint32_t cvmx_rng_get_random32(void)
+{
+    return cvmx_read64_uint32(CVMX_RNG_LOAD_ADDRESS);
+}
+
+/**
+ * Reads 64 bits of random data from Random number generator
+ *
+ * @return random data
+ */
+static inline uint64_t cvmx_rng_get_random64(void)
+{
+    return cvmx_read64_uint64(CVMX_RNG_LOAD_ADDRESS);
+}
+
+/**
+ * Requests random data from the RNG block asynchronously using and IOBDMA operation.
+ * The random data will be written into the cores
+ * local memory at the specified address.  A SYNCIOBDMA
+ * operation should be issued to stall for completion of the write.
+ *
+ * @param scr_addr  Address in scratch memory to put the result
+ *                  MUST be a multiple of 8 bytes
+ * @param num_bytes Number of bytes of random data to write at
+ *                  scr_addr
+ *                  MUST be a multiple of 8 bytes
+ *
+ * @return 0 on success
+ *         1 on error
+ */
+static inline int cvmx_rng_request_random_async(uint64_t scr_addr, uint64_t num_bytes)
+{
+    cvmx_rng_iobdma_data_t data;
+
+    if (num_bytes & 0x7 || scr_addr & 0x7)
+        return(1);
+
+    /* scr_addr must be 8 byte aligned */
+    data.s.scraddr = scr_addr >> 3;
+    data.s.len = num_bytes >> 3;
+    data.s.did = CVMX_OCT_DID_RNG;
+    cvmx_send_single(data.u64);
+    return(0);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /*  __CMVX_RNG_H__  */
diff --git a/cvmx-rtc.h b/cvmx-rtc.h
new file mode 100644
index 0000000000000..4908ca2d81372
--- /dev/null
+++ b/cvmx-rtc.h
@@ -0,0 +1,160 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides support for real time clocks on some boards
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+
+#ifndef __CVMX_RTC_H__
+#define __CVMX_RTC_H__
+
+#include "cvmx-sysinfo.h"
+#include "cvmx-thunder.h"
+#include "cvmx-cn3010-evb-hs5.h"
+
+/**
+ * Supported RTC options
+ */
+typedef enum
+{
+    CVMX_RTC_READ            = 0x1,  /**< Device supports read access */
+    CVMX_RTC_WRITE           = 0x2,  /**< Device supports write access */
+    CVMX_RTC_TIME_EPOCH      = 0x10, /**< Time stored as seconds from epoch */
+    CVMX_RTC_TIME_CAL        = 0x20, /**< Time stored as calendar */
+} cvmx_rtc_options_t;
+
+/**
+ * Return options supported by the RTC device
+ *
+ * @return Supported options, or 0 if RTC is not supported
+ */
+static inline cvmx_rtc_options_t cvmx_rtc_supported()
+{
+    static int supported = -1;
+
+    if (supported < 0) {
+	switch (cvmx_sysinfo_get()->board_type)
+	{
+	case CVMX_BOARD_TYPE_THUNDER:
+	    supported = CVMX_RTC_READ | CVMX_RTC_WRITE | CVMX_RTC_TIME_EPOCH;
+	    break;
+
+	case CVMX_BOARD_TYPE_EBH3000:
+	case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+	    supported = CVMX_RTC_READ | CVMX_RTC_WRITE | CVMX_RTC_TIME_CAL;
+	    break;
+
+	default:
+	    supported = 0;
+	    break;
+	}
+
+#ifdef CVMX_RTC_DEBUG
+	cvmx_dprintf("Board type: %s, RTC support: 0x%x\n",
+	       cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type),
+	       supported);
+#endif
+    }
+
+    return (cvmx_rtc_options_t) supported;
+}
+
+/**
+ * Read time from RTC device.
+ *
+ * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ *
+ * @return Time in seconds or 0 if RTC is not supported
+ */
+static inline uint32_t cvmx_rtc_read(void)
+{
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+    case CVMX_BOARD_TYPE_THUNDER:
+        return cvmx_rtc_ds1374_read();
+        break;
+
+    case CVMX_BOARD_TYPE_EBH3000:
+    case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+	return cvmx_rtc_ds1337_read();
+	break;
+
+    default:
+        return 0;
+        break;
+    }
+}
+
+/**
+ * Write time to the RTC device
+ *
+ * @param time    Number of seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ *
+ * @return Zero on success or device-specific error on failure.
+ */
+static inline uint32_t cvmx_rtc_write(uint32_t time)
+{
+    switch (cvmx_sysinfo_get()->board_type)
+    {
+    case CVMX_BOARD_TYPE_THUNDER:
+        return cvmx_rtc_ds1374_write(time);
+        break;
+
+    case CVMX_BOARD_TYPE_EBH3000:
+    case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+	return cvmx_rtc_ds1337_write(time);
+	break;
+
+    default:
+        return 0;
+        break;
+    }
+}
+
+#endif    /* __CVMX_RTC_H__  */
diff --git a/cvmx-rwlock.h b/cvmx-rwlock.h
new file mode 100644
index 0000000000000..08576e46864ef
--- /dev/null
+++ b/cvmx-rwlock.h
@@ -0,0 +1,169 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides reader/writer locks.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+
+#ifndef __CVMX_RWLOCK_H__
+#define __CVMX_RWLOCK_H__
+
+/* include to get atomic compare and store */
+#include "cvmx-atomic.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Flags for lock value in rw lock structure */
+#define CVMX_RWLOCK_WRITE_FLAG     0x1
+#define CVMX_RWLOCK_READ_INC       0x2
+
+
+/* Writer preference locks (wp).  Can be starved by writers.  When a writer
+ * is waiting, no readers are given the lock until all writers are done.
+ */
+typedef struct
+{
+    volatile uint32_t lock;
+    volatile uint32_t write_req;
+    volatile uint32_t write_comp;
+} cvmx_rwlock_wp_lock_t;
+
+/**
+ * Initialize a reader/writer lock.  This must be done
+ * by a single core before used.
+ *
+ * @param lock   pointer to rwlock structure
+ */
+static inline void cvmx_rwlock_wp_init(cvmx_rwlock_wp_lock_t *lock)
+{
+    lock->lock = 0;
+    lock->write_req = 0;
+    lock->write_comp = 0;
+}
+
+/**
+ * Perform a reader lock.  If a writer is pending, this
+ * will wait for that writer to complete before locking.
+ *
+ * NOTE: Each thread/process must only lock any rwlock
+ * once, or else a deadlock may result.
+ *
+ * @param lock   pointer to rwlock structure
+ */
+static inline void cvmx_rwlock_wp_read_lock(cvmx_rwlock_wp_lock_t *lock)
+{
+
+    /* Wait for outstanding write requests to be serviced */
+    while (lock->write_req != lock->write_comp)
+        ;
+    /* Add ourselves to interested reader count */
+    cvmx_atomic_add32_nosync((int32_t *)&(lock->lock), CVMX_RWLOCK_READ_INC);
+    /* Wait for writer to finish.  No writer will start again
+    ** until after we are done since we have already incremented
+    ** the reader count
+    */
+    while (lock->lock & CVMX_RWLOCK_WRITE_FLAG)
+        ;
+
+}
+
+/**
+ * Perform a reader unlock.
+ *
+ * @param lock   pointer to rwlock structure
+ */
+static inline void cvmx_rwlock_wp_read_unlock(cvmx_rwlock_wp_lock_t *lock)
+{
+    /* Remove ourselves to reader count */
+    cvmx_atomic_add32_nosync((int32_t *)&(lock->lock), -CVMX_RWLOCK_READ_INC);
+}
+
+/**
+ * Perform a writer lock.  Any readers that attempt
+ * to get a lock while there are any pending write locks
+ * will wait until all writers have completed.  Starvation
+ * of readers by writers is possible and must be avoided
+ * by the application.
+ *
+ * @param lock   pointer to rwlock structure
+ */
+static inline void cvmx_rwlock_wp_write_lock(cvmx_rwlock_wp_lock_t *lock)
+{
+    /* Get previous value of write requests */
+    uint32_t prev_writers = ((uint32_t)cvmx_atomic_fetch_and_add32((int32_t *)&(lock->write_req), 1));
+    /* Spin until our turn */
+    while (prev_writers != lock->write_comp)
+        ;
+    /* Spin until no other readers or writers, then set write flag */
+    while (!cvmx_atomic_compare_and_store32((uint32_t *)&(lock->lock), 0, CVMX_RWLOCK_WRITE_FLAG))
+        ;
+
+}
+/**
+ * Perform a writer unlock.
+ *
+ * @param lock   pointer to rwlock structure
+ */
+static inline void cvmx_rwlock_wp_write_unlock(cvmx_rwlock_wp_lock_t *lock)
+{
+    /* Remove our writer flag */
+    CVMX_SYNCWS;  /* Make sure all writes in protected region are visible before unlock */
+    cvmx_atomic_add32_nosync((int32_t *)&(lock->lock), -CVMX_RWLOCK_WRITE_FLAG);
+    cvmx_atomic_add32_nosync((int32_t *)&(lock->write_comp), 1);
+    CVMX_SYNCWS;  /* push unlock writes out, but don't stall */
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_RWLOCK_H__ */
diff --git a/cvmx-scratch.h b/cvmx-scratch.h
new file mode 100644
index 0000000000000..00fc5d21ea8a2
--- /dev/null
+++ b/cvmx-scratch.h
@@ -0,0 +1,161 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file provides support for the processor local scratch memory.
+ * Scratch memory is byte addressable - all addresses are byte addresses.
+ *
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+
+#ifndef __CVMX_SCRATCH_H__
+#define __CVMX_SCRATCH_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Note: This define must be a long, not a long long in order to compile
+        without warnings for both 32bit and 64bit. */
+#define CVMX_SCRATCH_BASE       (-32768l) /* 0xffffffffffff8000 */
+
+
+/**
+ * Reads an 8 bit value from the processor local scratchpad memory.
+ *
+ * @param address byte address to read from
+ *
+ * @return value read
+ */
+static inline uint8_t cvmx_scratch_read8(uint64_t address)
+{
+    return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);
+}
+/**
+ * Reads a 16 bit value from the processor local scratchpad memory.
+ *
+ * @param address byte address to read from
+ *
+ * @return value read
+ */
+static inline uint16_t cvmx_scratch_read16(uint64_t address)
+{
+    return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address);
+}
+/**
+ * Reads a 32 bit value from the processor local scratchpad memory.
+ *
+ * @param address byte address to read from
+ *
+ * @return value read
+ */
+static inline uint32_t cvmx_scratch_read32(uint64_t address)
+{
+    return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
+}
+/**
+ * Reads a 64 bit value from the processor local scratchpad memory.
+ *
+ * @param address byte address to read from
+ *
+ * @return value read
+ */
+static inline uint64_t cvmx_scratch_read64(uint64_t address)
+{
+    return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address);
+}
+
+
+
+/**
+ * Writes an 8 bit value to the processor local scratchpad memory.
+ *
+ * @param address byte address to write to
+ * @param value   value to write
+ */
+static inline void cvmx_scratch_write8(uint64_t address, uint64_t value)
+{
+    *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) = (uint8_t)value;
+}
+/**
+ * Writes a 32 bit value to the processor local scratchpad memory.
+ *
+ * @param address byte address to write to
+ * @param value   value to write
+ */
+static inline void cvmx_scratch_write16(uint64_t address, uint64_t value)
+{
+    *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) = (uint16_t)value;
+}
+/**
+ * Writes a 16 bit value to the processor local scratchpad memory.
+ *
+ * @param address byte address to write to
+ * @param value   value to write
+ */
+static inline void cvmx_scratch_write32(uint64_t address, uint64_t value)
+{
+    *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) = (uint32_t)value;
+}
+/**
+ * Writes a 64 bit value to the processor local scratchpad memory.
+ *
+ * @param address byte address to write to
+ * @param value   value to write
+ */
+static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
+{
+    *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value;
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_SCRATCH_H__ */
diff --git a/cvmx-shared-linux-n32.ld b/cvmx-shared-linux-n32.ld
new file mode 100644
index 0000000000000..04105f0a3f82e
--- /dev/null
+++ b/cvmx-shared-linux-n32.ld
@@ -0,0 +1,279 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/*
+ * This was created from a template supplied by GNU binutils.
+ * Copyright (C) 2005 Cavium Networks
+ */
+
+/**
+ * @file
+ * This linker script for use in building simple executive application to run
+ * under Linux in userspace. The important difference from a standard Linux
+ * binary is the addition of the ".cvmx_shared" memory section. This script
+ * adds two symbols __cvmx_shared_start and __cvmx_shared_end before and after
+ * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
+ * shared region across all application processes.
+ *
+ * The original template for this files was:
+ * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf32btsmipn32.x
+ */
+OUTPUT_FORMAT("elf32-ntradbigmips", "elf32-ntradbigmips",
+	      "elf32-ntradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x10000000); . = 0x10000000 + SIZEOF_HEADERS;
+  .interp         : { *(.interp) }
+  .MIPS.options : { *(.MIPS.options) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.init       : { *(.rel.init) }
+  .rela.init      : { *(.rela.init) }
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+  .rel.fini       : { *(.rel.fini) }
+  .rela.fini      : { *(.rela.fini) }
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+  .rel.ctors      : { *(.rel.ctors) }
+  .rela.ctors     : { *(.rela.ctors) }
+  .rel.dtors      : { *(.rel.dtors) }
+  .rela.dtors     : { *(.rela.dtors) }
+  .rel.got        : { *(.rel.got) }
+  .rela.got       : { *(.rela.got) }
+  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
+  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
+  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
+  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
+  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
+  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
+  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
+  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN (0x100000) - ((0x100000 - .) & (0x100000 - 1)); . = DATA_SEGMENT_ALIGN (0x100000, 0x1000);
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array     : { *(.preinit_array) }
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { *(.init_array) }
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { *(.fini_array) }
+  PROVIDE (__fini_array_end = .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .eh_frame       : { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : { *(.gcc_except_table) }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+  .srdata         : { *(.srdata) }
+
+  . = ALIGN (0x10000);
+  __cvmx_shared_start = .;
+  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
+  .cvmx_shared_bss : { *(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*) }
+  . = ALIGN (0x10000);
+  __cvmx_shared_end = .;
+
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  . = ALIGN(32M);    /* RBF added alignment of data */
+  .cvmx_shared : { *(.cvmx_shared) }
+  _end = .;
+  PROVIDE (end = .);
+  . = DATA_SEGMENT_END (.);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/cvmx-shared-linux-o32.ld b/cvmx-shared-linux-o32.ld
new file mode 100644
index 0000000000000..67c12c67d91b7
--- /dev/null
+++ b/cvmx-shared-linux-o32.ld
@@ -0,0 +1,277 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/*
+ * This was created from a template supplied by GNU binutils.
+ * Copyright (C) 2004 Cavium Networks
+ */
+
+/**
+ * @file
+ * This linker script for use in building simple executive application to run
+ * under Linux in userspace. The important difference from a standard Linux
+ * binary is the addition of the ".cvmx_shared" memory section. This script
+ * adds two symbols __cvmx_shared_start and __cvmx_sahred_end before and after
+ * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
+ * shared region across all application processes.
+ *
+ * The original template for this files was:
+ * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf32btsmip.x
+ */
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
+	      "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x10000000); . = 0x10000000 + SIZEOF_HEADERS;
+  .interp         : { *(.interp) }
+  .reginfo        : { *(.reginfo) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.init       : { *(.rel.init) }
+  .rela.init      : { *(.rela.init) }
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+  .rel.fini       : { *(.rel.fini) }
+  .rela.fini      : { *(.rela.fini) }
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+  .rel.ctors      : { *(.rel.ctors) }
+  .rela.ctors     : { *(.rela.ctors) }
+  .rel.dtors      : { *(.rel.dtors) }
+  .rela.dtors     : { *(.rela.dtors) }
+  .rel.got        : { *(.rel.got) }
+  .rela.got       : { *(.rela.got) }
+  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
+  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
+  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
+  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
+  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
+  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
+  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
+  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = 0x10000000;
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array     : { *(.preinit_array) }
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { *(.init_array) }
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { *(.fini_array) }
+  PROVIDE (__fini_array_end = .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .eh_frame       : { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : { *(.gcc_except_table) }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+
+  . = ALIGN (0x10000);
+  __cvmx_shared_start = .;
+  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
+  .cvmx_shared_bss : {*(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*)}
+  . = ALIGN (0x10000);
+  __cvmx_shared_end = .;
+
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  . = ALIGN(32M);    /* RBF added alignment of data */
+  .cvmx_shared : { *(.cvmx_shared) }
+  _end = .;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/cvmx-shared-linux.ld b/cvmx-shared-linux.ld
new file mode 100644
index 0000000000000..54f4d8289e39d
--- /dev/null
+++ b/cvmx-shared-linux.ld
@@ -0,0 +1,278 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/*
+ * This was created from a template supplied by GNU binutils.
+ * Copyright (C) 2004 Cavium Networks
+ */
+ 
+/**
+ * @file
+ * This linker script for use in building simple executive application to run
+ * under Linux in userspace. The important difference from a standard Linux 
+ * binary is the addition of the ".cvmx_shared" memory section. This script 
+ * adds two symbols __cvmx_shared_start and __cvmx_sahred_end before and after
+ * the CVMX_SHARED data. These are used by cvmx-app-init-linux.c to create a
+ * shared region across all application processes.
+ *
+ * The original template for this files was:
+ * ${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib/ldscripts/elf64btsmip.x
+ */
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips",
+	      "elf64-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("${OCTEON_ROOT}/tools/mips64-octeon-linux-gnu/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x120000000); . = 0x120000000 + SIZEOF_HEADERS;
+  .interp         : { *(.interp) }
+  .MIPS.options : { *(.MIPS.options) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.init       : { *(.rel.init) }
+  .rela.init      : { *(.rela.init) }
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+  .rel.fini       : { *(.rel.fini) }
+  .rela.fini      : { *(.rela.fini) }
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
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+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+  .rel.ctors      : { *(.rel.ctors) }
+  .rela.ctors     : { *(.rela.ctors) }
+  .rel.dtors      : { *(.rel.dtors) }
+  .rela.dtors     : { *(.rela.dtors) }
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+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(0x100000) + (. & (0x100000 - 1));
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(64 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array     : { *(.preinit_array) }
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { *(.init_array) }
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { *(.fini_array) }
+  PROVIDE (__fini_array_end = .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .eh_frame       : { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : { *(.gcc_except_table) }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+  .srdata         : { *(.srdata) }
+  
+  . = ALIGN (0x10000); 
+  __cvmx_shared_start = .;
+  .cvmx_shared : {*(.cvmx_shared .cvmx_shared.linkonce.*)}
+  .cvmx_shared_bss : { *(.cvmx_shared_bss .cvmx_shared_bss.linkonce.*) }
+  . = ALIGN (0x10000);
+  __cvmx_shared_end = .;
+  
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(64 / 8);
+  }
+  . = ALIGN(64 / 8);
+  . = ALIGN(32M);    /* RBF added alignment of data */
+  .cvmx_shared : { *(.cvmx_shared) }
+  _end = .;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
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+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/cvmx-spi.c b/cvmx-spi.c
new file mode 100644
index 0000000000000..bb0426bbdacc0
--- /dev/null
+++ b/cvmx-spi.c
@@ -0,0 +1,639 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the SPI
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-mio.h"
+#include "cvmx-pko.h"
+#include "cvmx-spi.h"
+#include "cvmx-sysinfo.h"
+
+#define INVOKE_CB(function_p, args...) \
+        do { \
+            if (function_p) { \
+                res = function_p(args); \
+                if (res) \
+                    return res; \
+            } \
+        } while (0)
+
+#if CVMX_ENABLE_DEBUG_PRINTS
+static const char *modes[] = {"UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex"};
+#endif
+
+/* Default callbacks, can be overridden
+ *  using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks
+ */
+static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
+  .reset_cb            = cvmx_spi_reset_cb,
+  .calendar_setup_cb   = cvmx_spi_calendar_setup_cb,
+  .clock_detect_cb     = cvmx_spi_clock_detect_cb,
+  .training_cb         = cvmx_spi_training_cb,
+  .calendar_sync_cb    = cvmx_spi_calendar_sync_cb,
+  .interface_up_cb     = cvmx_spi_interface_up_cb
+};
+
+/**
+ * Get current SPI4 initialization callbacks
+ *
+ * @param callbacks  Pointer to the callbacks structure.to fill
+ *
+ * @return Pointer to cvmx_spi_callbacks_t structure.
+ */
+void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t * callbacks)
+{
+    memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks));
+}
+
+/**
+ * Set new SPI4 initialization callbacks
+ *
+ * @param new_callbacks  Pointer to an updated callbacks structure.
+ */
+void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t * new_callbacks)
+{
+    memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks));
+}
+
+/**
+ * Initialize and start the SPI interface.
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for clock synchronization in seconds
+ * @param num_ports Number of SPI ports to configure
+ *
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, int num_ports)
+{
+    int res = -1;
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        return res;
+
+    // Callback to perform SPI4 reset
+    INVOKE_CB( cvmx_spi_callbacks.reset_cb, interface, mode);
+
+    // Callback to perform calendar setup
+    INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode, num_ports);
+
+    // Callback to perform clock detection
+    INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
+
+    // Callback to perform SPI4 link training
+    INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
+
+    // Callback to perform calendar sync
+    INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, timeout);
+
+    // Callback to handle interface coming up
+    INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
+
+    return res;
+}
+
+/**
+ * This routine restarts the SPI interface after it has lost synchronization
+ * with its correspondent system.
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for clock synchronization in seconds
+ * @return Zero on success, negative of failure.
+ */
+int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+    int res = -1;
+
+
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        return res;
+
+    cvmx_dprintf ("SPI%d: Restart %s\n", interface, modes[mode]);
+
+    // Callback to perform SPI4 reset
+    INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface,mode);
+
+    // NOTE: Calendar setup is not performed during restart
+    //       Refer to cvmx_spi_start_interface() for the full sequence
+
+    // Callback to perform clock detection
+    INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
+
+    // Callback to perform SPI4 link training
+    INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
+
+    // Callback to perform calendar sync
+    INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, timeout);
+
+    // Callback to handle interface coming up
+    INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
+
+    return res;
+}
+
+/**
+ * Callback to perform SPI4 reset
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
+{
+    cvmx_spxx_dbg_deskew_ctl_t spxx_dbg_deskew_ctl;
+    cvmx_spxx_clk_ctl_t spxx_clk_ctl;
+    cvmx_spxx_bist_stat_t spxx_bist_stat;
+    cvmx_spxx_int_msk_t spxx_int_msk;
+    cvmx_stxx_int_msk_t stxx_int_msk;
+    cvmx_spxx_trn4_ctl_t spxx_trn4_ctl;
+    int index;
+    uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+
+    /* Disable SPI error events while we run BIST */
+    spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
+    cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
+    stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
+    cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
+
+    /* Run BIST in the SPI interface */
+    cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);
+    cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0);
+    spxx_clk_ctl.u64 = 0;
+    spxx_clk_ctl.s.runbist = 1;
+    cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+    cvmx_wait (10 * MS);
+    spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
+    if (spxx_bist_stat.s.stat0)
+        cvmx_dprintf("ERROR SPI%d: BIST failed on receive datapath FIFO\n", interface);
+    if (spxx_bist_stat.s.stat1)
+        cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n", interface);
+    if (spxx_bist_stat.s.stat2)
+        cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n", interface);
+
+    /* Clear the calendar table after BIST to fix parity errors */
+    for (index=0; index<32; index++)
+    {
+        cvmx_srxx_spi4_calx_t srxx_spi4_calx;
+        cvmx_stxx_spi4_calx_t stxx_spi4_calx;
+
+        srxx_spi4_calx.u64 = 0;
+        srxx_spi4_calx.s.oddpar = 1;
+        cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), srxx_spi4_calx.u64);
+
+        stxx_spi4_calx.u64 = 0;
+        stxx_spi4_calx.s.oddpar = 1;
+        cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), stxx_spi4_calx.u64);
+    }
+
+    /* Re enable reporting of error interrupts */
+    cvmx_write_csr(CVMX_SPXX_INT_REG(interface), cvmx_read_csr(CVMX_SPXX_INT_REG(interface)));
+    cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
+    cvmx_write_csr(CVMX_STXX_INT_REG(interface), cvmx_read_csr(CVMX_STXX_INT_REG(interface)));
+    cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
+
+    // Setup the CLKDLY right in the middle
+    spxx_clk_ctl.u64 = 0;
+    spxx_clk_ctl.s.seetrn = 0;
+    spxx_clk_ctl.s.clkdly = 0x10;
+    spxx_clk_ctl.s.runbist = 0;
+    spxx_clk_ctl.s.statdrv = 0;
+    spxx_clk_ctl.s.statrcv = 1; /* This should always be on the opposite edge as statdrv */ 
+    spxx_clk_ctl.s.sndtrn = 0;
+    spxx_clk_ctl.s.drptrn = 0;
+    spxx_clk_ctl.s.rcvtrn = 0;
+    spxx_clk_ctl.s.srxdlck = 0;
+    cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+    cvmx_wait (100 * MS);
+
+    // Reset SRX0 DLL
+    spxx_clk_ctl.s.srxdlck = 1;
+    cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+
+    // Waiting for Inf0 Spi4 RX DLL to lock
+    cvmx_wait (100 * MS);
+
+    // Enable dynamic alignment
+    spxx_trn4_ctl.s.trntest = 0;
+    spxx_trn4_ctl.s.jitter = 1;
+    spxx_trn4_ctl.s.clr_boot = 1;
+    spxx_trn4_ctl.s.set_boot = 0;
+    if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+        spxx_trn4_ctl.s.maxdist = 3;
+    else
+        spxx_trn4_ctl.s.maxdist = 8;
+    spxx_trn4_ctl.s.macro_en = 1;
+    spxx_trn4_ctl.s.mux_en = 1;
+    cvmx_write_csr (CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
+
+    spxx_dbg_deskew_ctl.u64 = 0;
+    cvmx_write_csr (CVMX_SPXX_DBG_DESKEW_CTL(interface), spxx_dbg_deskew_ctl.u64);
+
+    return 0;
+}
+
+/**
+ * Callback to setup calendar and miscellaneous settings before clock detection
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param num_ports Number of ports to configure on SPI
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, int num_ports)
+{
+    int port;
+    int index;
+    if (mode & CVMX_SPI_MODE_RX_HALFPLEX)
+    {
+        cvmx_srxx_com_ctl_t srxx_com_ctl;
+        cvmx_srxx_spi4_stat_t srxx_spi4_stat;
+
+        // SRX0 number of Ports
+        srxx_com_ctl.u64 = 0;
+        srxx_com_ctl.s.prts = num_ports - 1;
+        srxx_com_ctl.s.st_en = 0;
+        srxx_com_ctl.s.inf_en = 0;
+        cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
+
+        // SRX0 Calendar Table. This round robbins through all ports
+        port = 0;
+        index = 0;
+        while (port < num_ports)
+        {
+            cvmx_srxx_spi4_calx_t srxx_spi4_calx;
+            srxx_spi4_calx.u64 = 0;
+            srxx_spi4_calx.s.prt0 = port++;
+            srxx_spi4_calx.s.prt1 = port++;
+            srxx_spi4_calx.s.prt2 = port++;
+            srxx_spi4_calx.s.prt3 = port++;
+            srxx_spi4_calx.s.oddpar = ~(cvmx_dpop(srxx_spi4_calx.u64) & 1);
+            cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), srxx_spi4_calx.u64);
+            index++;
+        }
+        srxx_spi4_stat.u64 = 0;
+        srxx_spi4_stat.s.len = num_ports;
+        srxx_spi4_stat.s.m = 1;
+        cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), srxx_spi4_stat.u64);
+    }
+
+    if (mode & CVMX_SPI_MODE_TX_HALFPLEX)
+    {
+        cvmx_stxx_arb_ctl_t stxx_arb_ctl;
+        cvmx_gmxx_tx_spi_max_t gmxx_tx_spi_max;
+        cvmx_gmxx_tx_spi_thresh_t gmxx_tx_spi_thresh;
+        cvmx_gmxx_tx_spi_ctl_t gmxx_tx_spi_ctl;
+        cvmx_stxx_spi4_stat_t stxx_spi4_stat;
+        cvmx_stxx_spi4_dat_t stxx_spi4_dat;
+
+        // STX0 Config
+        stxx_arb_ctl.u64 = 0;
+        stxx_arb_ctl.s.igntpa = 0;
+        stxx_arb_ctl.s.mintrn = 0;
+        cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);
+
+        gmxx_tx_spi_max.u64 = 0;
+        gmxx_tx_spi_max.s.max1 = 8;
+        gmxx_tx_spi_max.s.max2 = 4;
+        gmxx_tx_spi_max.s.slice = 0;
+        cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), gmxx_tx_spi_max.u64);
+
+        gmxx_tx_spi_thresh.u64 = 0;
+        gmxx_tx_spi_thresh.s.thresh = 4;
+        cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), gmxx_tx_spi_thresh.u64);
+
+        gmxx_tx_spi_ctl.u64 = 0;
+        gmxx_tx_spi_ctl.s.tpa_clr = 0;
+        gmxx_tx_spi_ctl.s.cont_pkt = 0;
+        cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), gmxx_tx_spi_ctl.u64);
+
+        // STX0 Training Control
+        stxx_spi4_dat.u64 = 0;
+        stxx_spi4_dat.s.alpha = 32;    /*Minimum needed by dynamic alignment*/
+        stxx_spi4_dat.s.max_t = 0xFFFF;  /*Minimum interval is 0x20*/
+        cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), stxx_spi4_dat.u64);
+
+        // STX0 Calendar Table. This round robbins through all ports
+        port = 0;
+        index = 0;
+        while (port < num_ports)
+        {
+            cvmx_stxx_spi4_calx_t stxx_spi4_calx;
+            stxx_spi4_calx.u64 = 0;
+            stxx_spi4_calx.s.prt0 = port++;
+            stxx_spi4_calx.s.prt1 = port++;
+            stxx_spi4_calx.s.prt2 = port++;
+            stxx_spi4_calx.s.prt3 = port++;
+            stxx_spi4_calx.s.oddpar = ~(cvmx_dpop(stxx_spi4_calx.u64) & 1);
+            cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), stxx_spi4_calx.u64);
+            index++;
+        }
+        stxx_spi4_stat.u64 = 0;
+        stxx_spi4_stat.s.len = num_ports;
+        stxx_spi4_stat.s.m = 1;
+        cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), stxx_spi4_stat.u64);
+    }
+
+    return 0;
+}
+
+/**
+ * Callback to perform clock detection
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for clock synchronization in seconds
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+    int                          clock_transitions;
+    cvmx_spxx_clk_stat_t         stat;
+    uint64_t                     timeout_time;
+    uint64_t                     MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+
+    /* Regardless of operating mode, both Tx and Rx clocks must be present
+        for the SPI interface to operate. */
+    cvmx_dprintf ("SPI%d: Waiting to see TsClk...\n", interface);
+    timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+    /* Require 100 clock transitions in order to avoid any noise in the
+        beginning  */
+    clock_transitions = 100;
+    do
+    {
+        stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
+        if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions)
+        {
+            /* We've seen a clock transition, so decrement the number we still
+                need */
+            clock_transitions--;
+            cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
+            stat.s.s4clk0 = 0;
+            stat.s.s4clk1 = 0;
+        }
+        if (cvmx_get_cycle() > timeout_time)
+        {
+            cvmx_dprintf ("SPI%d: Timeout\n", interface);
+            return -1;
+        }
+    } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
+
+    cvmx_dprintf ("SPI%d: Waiting to see RsClk...\n", interface);
+    timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+    /* Require 100 clock transitions in order to avoid any noise in the
+        beginning  */
+    clock_transitions = 100;
+    do
+    {
+        stat.u64 = cvmx_read_csr (CVMX_SPXX_CLK_STAT(interface));
+        if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions)
+        {
+            /* We've seen a clock transition, so decrement the number we still
+                need */
+            clock_transitions--;
+            cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
+            stat.s.d4clk0 = 0;
+            stat.s.d4clk1 = 0;
+        }
+        if (cvmx_get_cycle() > timeout_time)
+        {
+            cvmx_dprintf ("SPI%d: Timeout\n", interface);
+            return -1;
+        }
+    } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
+
+    return 0;
+}
+
+/**
+ * Callback to perform link training
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for link to be trained (in seconds)
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+    cvmx_spxx_trn4_ctl_t         spxx_trn4_ctl;
+    cvmx_spxx_clk_stat_t         stat;
+    uint64_t                     MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    uint64_t                     timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+    int                          rx_training_needed;
+
+    // SRX0 & STX0 Inf0 Links are configured - begin training
+    cvmx_spxx_clk_ctl_t spxx_clk_ctl;
+    spxx_clk_ctl.u64 = 0;
+    spxx_clk_ctl.s.seetrn = 0;
+    spxx_clk_ctl.s.clkdly = 0x10;
+    spxx_clk_ctl.s.runbist = 0;
+    spxx_clk_ctl.s.statdrv = 0;
+    spxx_clk_ctl.s.statrcv = 1; /* This should always be on the opposite edge as statdrv */ 
+    spxx_clk_ctl.s.sndtrn = 1;
+    spxx_clk_ctl.s.drptrn = 1;
+    spxx_clk_ctl.s.rcvtrn = 1;
+    spxx_clk_ctl.s.srxdlck = 1;
+    cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+    cvmx_wait (1000 * MS);
+
+    // SRX0 clear the boot bit
+    spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
+    spxx_trn4_ctl.s.clr_boot = 1;
+    cvmx_write_csr (CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
+
+    // Wait for the training sequence to complete
+    cvmx_dprintf ("SPI%d: Waiting for training\n", interface);
+    cvmx_wait (1000 * MS);
+    timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;  /* Wait a really long time here */
+    /* The HRM says we must wait for 34 + 16 * MAXDIST training sequences.
+        We'll be pessimistic and wait for a lot more */
+    rx_training_needed = 500;
+    do {
+        stat.u64 = cvmx_read_csr (CVMX_SPXX_CLK_STAT(interface));
+        if (stat.s.srxtrn && rx_training_needed)
+        {
+            rx_training_needed--;
+            cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
+            stat.s.srxtrn = 0;
+        }
+        if (cvmx_get_cycle() > timeout_time)
+        {
+            cvmx_dprintf ("SPI%d: Timeout\n", interface);
+            return -1;
+        }
+    } while (stat.s.srxtrn == 0);
+
+    return 0;
+}
+
+/**
+ * Callback to perform calendar data synchronization
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for calendar data in seconds
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+    uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
+        // SRX0 interface should be good, send calendar data
+        cvmx_srxx_com_ctl_t srxx_com_ctl;
+        cvmx_dprintf ("SPI%d: Rx is synchronized, start sending calendar data\n", interface);
+        srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
+        srxx_com_ctl.s.inf_en = 1;
+        srxx_com_ctl.s.st_en  = 1;
+        cvmx_write_csr (CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
+    }
+
+    if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
+        // STX0 has achieved sync
+        // The corespondant board should be sending calendar data
+        // Enable the STX0 STAT receiver.
+        cvmx_spxx_clk_stat_t stat;
+        uint64_t timeout_time;
+        cvmx_stxx_com_ctl_t stxx_com_ctl;
+        stxx_com_ctl.u64 = 0;
+        stxx_com_ctl.s.st_en = 1;
+        cvmx_write_csr (CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
+
+        // Waiting for calendar sync on STX0 STAT
+        cvmx_dprintf ("SPI%d: Waiting to sync on STX[%d] STAT\n", interface, interface);
+        timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+        // SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10)
+        do {
+            stat.u64 = cvmx_read_csr (CVMX_SPXX_CLK_STAT (interface));
+            if (cvmx_get_cycle() > timeout_time)
+            {
+                cvmx_dprintf ("SPI%d: Timeout\n", interface);
+                return -1;
+            }
+        } while (stat.s.stxcal == 0);
+    }
+
+    return 0;
+}
+
+/**
+ * Callback to handle interface up
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode)
+{
+    cvmx_gmxx_rxx_frm_min_t gmxx_rxx_frm_min;
+    cvmx_gmxx_rxx_frm_max_t gmxx_rxx_frm_max;
+    cvmx_gmxx_rxx_jabber_t gmxx_rxx_jabber;
+
+    if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
+        cvmx_srxx_com_ctl_t srxx_com_ctl;
+        srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
+        srxx_com_ctl.s.inf_en = 1;
+        cvmx_write_csr (CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
+        cvmx_dprintf ("SPI%d: Rx is now up\n", interface);
+    }
+
+    if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
+        cvmx_stxx_com_ctl_t stxx_com_ctl;
+        stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));
+        stxx_com_ctl.s.inf_en = 1;
+        cvmx_write_csr (CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
+        cvmx_dprintf ("SPI%d: Tx is now up\n", interface);
+    }
+
+    gmxx_rxx_frm_min.u64 = 0;
+    gmxx_rxx_frm_min.s.len = 64;
+    cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0,interface), gmxx_rxx_frm_min.u64);
+    gmxx_rxx_frm_max.u64 = 0;
+    gmxx_rxx_frm_max.s.len = 64*1024 - 4;
+    cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0,interface), gmxx_rxx_frm_max.u64);
+    gmxx_rxx_jabber.u64 = 0;
+    gmxx_rxx_jabber.s.cnt = 64*1024 - 4;
+    cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0,interface), gmxx_rxx_jabber.u64);
+
+    return 0;
+}
+
diff --git a/cvmx-spi.h b/cvmx-spi.h
new file mode 100644
index 0000000000000..0da6becc1c765
--- /dev/null
+++ b/cvmx-spi.h
@@ -0,0 +1,265 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This file contains defines for the SPI interface
+
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+#ifndef __CVMX_SPI_H__
+#define __CVMX_SPI_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+typedef enum
+{
+    CVMX_SPI_MODE_UNKNOWN = 0,
+    CVMX_SPI_MODE_TX_HALFPLEX = 1,
+    CVMX_SPI_MODE_RX_HALFPLEX = 2,
+    CVMX_SPI_MODE_DUPLEX = 3
+} cvmx_spi_mode_t;
+
+/** Callbacks structure to customize SPI4 initialization sequence */
+typedef struct
+{
+    /** Called to reset SPI4 DLL */
+    int (*reset_cb)(int interface, cvmx_spi_mode_t mode);
+
+    /** Called to setup calendar */
+    int (*calendar_setup_cb)(int interface, cvmx_spi_mode_t mode, int num_ports);
+
+    /** Called for Tx and Rx clock detection */
+    int (*clock_detect_cb)(int interface, cvmx_spi_mode_t mode, int timeout);
+
+    /** Called to perform link training */
+    int (*training_cb)(int interface, cvmx_spi_mode_t mode, int timeout);
+
+    /** Called for calendar data synchronization */
+    int (*calendar_sync_cb)(int interface, cvmx_spi_mode_t mode, int timeout);
+
+    /** Called when interface is up */
+    int (*interface_up_cb)(int interface, cvmx_spi_mode_t mode);
+
+} cvmx_spi_callbacks_t;
+
+
+/**
+ * Return true if the supplied interface is configured for SPI
+ *
+ * @param interface Interface to check
+ * @return True if interface is SPI
+ */
+static inline int cvmx_spi_is_spi_interface(int interface)
+{
+    uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+    return ((gmxState & 0x2) && (gmxState & 0x1));
+}
+
+/**
+ * Initialize and start the SPI interface.
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for clock synchronization in seconds
+ * @param num_ports Number of SPI ports to configure
+ *
+ * @return Zero on success, negative of failure.
+ */
+extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, int num_ports);
+
+/**
+ * This routine restarts the SPI interface after it has lost synchronization
+ * with its corespondant system.
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for clock synchronization in seconds
+ * @return Zero on success, negative of failure.
+ */
+extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout);
+
+/**
+ * Return non-zero if the SPI interface has a SPI4000 attached
+ *
+ * @param interface SPI interface the SPI4000 is connected to
+ *
+ * @return
+ */
+extern int cvmx_spi4000_is_present(int interface);
+
+/**
+ * Initialize the SPI4000 for use
+ *
+ * @param interface SPI interface the SPI4000 is connected to
+ */
+extern int cvmx_spi4000_initialize(int interface);
+
+/**
+ * Poll all the SPI4000 port and check its speed
+ *
+ * @param interface Interface the SPI4000 is on
+ * @param port      Port to poll (0-9)
+ * @return Status of the port. 0=down. All other values the port is up.
+ */
+extern cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port);
+
+/**
+ * Get current SPI4 initialization callbacks
+ *
+ * @param callbacks  Pointer to the callbacks structure.to fill
+ *
+ * @return Pointer to cvmx_spi_callbacks_t structure.
+ */
+extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t * callbacks);
+
+/**
+ * Set new SPI4 initialization callbacks
+ *
+ * @param new_callbacks  Pointer to an updated callbacks structure.
+ */
+extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t * new_callbacks);
+
+/**
+ * Callback to perform SPI4 reset
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
+
+/**
+ * Callback to setup calendar and miscellaneous settings before clock detection
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param num_ports Number of ports to configure on SPI
+ *
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, int num_ports);
+
+/**
+ * Callback to perform clock detection
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for clock synchronization in seconds
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout);
+
+/**
+ * Callback to perform link training
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for link to be trained (in seconds)
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout);
+
+/**
+ * Callback to perform calendar data synchronization
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @param timeout   Timeout to wait for calendar data in seconds
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout);
+
+/**
+ * Callback to handle interface up
+ *
+ * @param interface The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @param mode      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @return Zero on success, non-zero error code on failure (will cause SPI initialization to abort)
+ */
+extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_SPI_H__ */
diff --git a/cvmx-spi4000.c b/cvmx-spi4000.c
new file mode 100644
index 0000000000000..7358ff5cd55f2
--- /dev/null
+++ b/cvmx-spi4000.c
@@ -0,0 +1,520 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the SPI4000 card
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-mio.h"
+#include "cvmx-spi.h"
+#include "cvmx-twsi.h"
+
+/* If someone is using an old config, make the SPI4000 act like RGMII for backpressure */
+#ifndef CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE
+#ifndef CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
+#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
+#endif
+#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
+#endif
+
+#define SPI4000_READ_ADDRESS_HIGH   0xf0
+#define SPI4000_READ_ADDRESS_LOW    0xf1
+#define SPI4000_WRITE_ADDRESS_HIGH  0xf2
+#define SPI4000_WRITE_ADDRESS_LOW   0xf3
+#define SPI4000_READ_DATA0          0xf4    /* High byte */
+#define SPI4000_READ_DATA1          0xf5
+#define SPI4000_READ_DATA2          0xf6
+#define SPI4000_READ_DATA3          0xf7    /* Low byte */
+#define SPI4000_WRITE_DATA0         0xf8    /* High byte */
+#define SPI4000_WRITE_DATA1         0xf9
+#define SPI4000_WRITE_DATA2         0xfa
+#define SPI4000_WRITE_DATA3         0xfb    /* Low byte */
+#define SPI4000_DO_READ             0xfc    /* Issue a read, returns read status */
+#define SPI4000_GET_READ_STATUS     0xfd    /* 0xff: initial state, 2: Read failed, 1: Read pending, 0: Read success */
+#define SPI4000_DO_WRITE            0xfe    /* Issue a write, returns write status */
+#define SPI4000_GET_WRITE_STATUS    0xff    /* 0xff: initial state, 6: Write failed, 5: Write pending, 4: Write success */
+#define SPI4000_TWSI_ID(interface)  (0x66 + interface)
+
+/* MDI Single Command (register 0x680) */
+typedef union
+{
+    uint32_t u32;
+    struct
+    {
+        uint32_t    reserved_21_31  : 11;
+        uint32_t    mdi_command     : 1; /**< Performs an MDIO access. When set, this bit
+                                            self clears upon completion of the access. */
+        uint32_t    reserved_18_19  : 2;
+        uint32_t    op_code         : 2; /**< MDIO Op Code
+                                            00 = Reserved
+                                            01 = Write Access
+                                            10 = Read Access
+                                            11 = Reserved */
+        uint32_t    reserved_13_15  : 3;
+        uint32_t    phy_address     : 5; /**< Address of external PHY device */
+        uint32_t    reserved_5_7    : 3;
+        uint32_t    reg_address     : 5; /**< Address of register within external PHY */
+    } s;
+} mdio_single_command_t;
+
+
+static CVMX_SHARED int interface_is_spi4000[2] = {0,0};
+
+
+/**
+ * @INTERNAL
+ * Write data to the specified SPI4000 address
+ *
+ * @param interface Interface the SPI4000 is on. (0 or 1)
+ * @param address   Address to write to
+ * @param data      Data to write
+ */
+static void __cvmx_spi4000_write(int interface, int address, uint32_t data)
+{
+    int status;
+
+    cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 2, 1, address);
+    cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_WRITE_DATA0, 4, 1, data);
+
+    status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_WRITE);
+    while ((status == 5) || (status == 0xff))
+        status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_WRITE_STATUS);
+
+    if (status != 4)
+        cvmx_dprintf("SPI4000: write failed with status=0x%x\n", status);
+}
+
+
+/**
+ * @INTERNAL
+ * Read data from the SPI4000.
+ *
+ * @param interface Interface the SPI4000 is on. (0 or 1)
+ * @param address   Address to read from
+ *
+ * @return Value at the specified address
+ */
+static uint32_t __cvmx_spi4000_read(int interface, int address)
+{
+    int status;
+    uint64_t data;
+
+    cvmx_twsix_write_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_ADDRESS_HIGH, 2, 1, address);
+
+    status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_DO_READ);
+    while ((status == 1) || (status == 0xff))
+        status = cvmx_twsi_read8(SPI4000_TWSI_ID(interface), SPI4000_GET_READ_STATUS);
+
+    if (status)
+    {
+        cvmx_dprintf("SPI4000: read failed with %d\n", status);
+        return 0;
+    }
+
+    status = cvmx_twsix_read_ia(0, SPI4000_TWSI_ID(interface), SPI4000_READ_DATA0, 4, 1, &data);
+    if (status != 4)
+    {
+        cvmx_dprintf("SPI4000: read failed with %d\n", status);
+        return 0;
+    }
+
+    return data;
+}
+
+
+/**
+ * @INTERNAL
+ * Write to a PHY using MDIO on the SPI4000
+ *
+ * @param interface Interface the SPI4000 is on. (0 or 1)
+ * @param port      SPI4000 RGMII port to write to. (0-9)
+ * @param location  MDIO register to write
+ * @param val       Value to write
+ */
+static void __cvmx_spi4000_mdio_write(int interface, int port, int location, int val)
+{
+    static int last_value=-1;
+    mdio_single_command_t mdio;
+
+    mdio.u32 = 0;
+    mdio.s.mdi_command = 1;
+    mdio.s.op_code = 1;
+    mdio.s.phy_address = port;
+    mdio.s.reg_address = location;
+
+    /* Since the TWSI accesses are very slow, don't update the write value
+        if it is the same as the last value */
+    if (val != last_value)
+    {
+        last_value = val;
+        __cvmx_spi4000_write(interface, 0x0681, val);
+    }
+
+    __cvmx_spi4000_write(interface, 0x0680, mdio.u32);
+}
+
+
+/**
+ * @INTERNAL
+ * Read from a PHY using MDIO on the SPI4000
+ *
+ * @param interface Interface the SPI4000 is on. (0 or 1)
+ * @param port      SPI4000 RGMII port to read from. (0-9)
+ * @param location  MDIO register to read
+ * @return The MDI read result
+ */
+static int __cvmx_spi4000_mdio_read(int interface, int port, int location)
+{
+    mdio_single_command_t mdio;
+
+    mdio.u32 = 0;
+    mdio.s.mdi_command = 1;
+    mdio.s.op_code = 2;
+    mdio.s.phy_address = port;
+    mdio.s.reg_address = location;
+    __cvmx_spi4000_write(interface, 0x0680, mdio.u32);
+
+    do
+    {
+        mdio.u32 = __cvmx_spi4000_read(interface, 0x0680);
+    } while (mdio.s.mdi_command);
+
+    return __cvmx_spi4000_read(interface, 0x0681) >> 16;
+}
+
+
+/**
+ * @INTERNAL
+ * Configure the SPI4000 MACs
+ */
+static void __cvmx_spi4000_configure_mac(int interface)
+{
+    int port;
+    // IXF1010 configuration
+    // ---------------------
+    //
+    // Step 1: Apply soft reset to TxFIFO and MAC
+    //         MAC soft reset register. address=0x505
+    //         TxFIFO soft reset. address=0x620
+    __cvmx_spi4000_write(interface, 0x0505, 0x3ff);  // reset all the MACs
+    __cvmx_spi4000_write(interface, 0x0620, 0x3ff);  // reset the TX FIFOs
+
+    //         Global address and Configuration Register. address=0x500
+    //
+    // Step 2: Apply soft reset to RxFIFO and SPI.
+    __cvmx_spi4000_write(interface, 0x059e, 0x3ff);  // reset the RX FIFOs
+
+    // Step 3a: Take the MAC out of softreset
+    //          MAC soft reset register. address=0x505
+    __cvmx_spi4000_write(interface, 0x0505, 0x0);    // reset all the MACs
+
+    // Step 3b: De-assert port enables.
+    //          Global address and Configuration Register. address=0x500
+    __cvmx_spi4000_write(interface, 0x0500, 0x0);    // disable all ports
+
+    // Step 4: Assert Clock mode change En.
+    //         Clock and interface mode Change En. address=Serdes base + 0x14
+    //         Serdes (Serializer/de-serializer). address=0x780
+    //         [Can't find this one]
+
+    for (port=0; port < 10; port++)
+    {
+        int port_offset = port << 7;
+
+        // Step 5: Set MAC interface mode GMII speed.
+        //         MAC interface mode and RGMII speed register.
+        //             address=port_index+0x10
+        //
+        //         OUT port_index+0x10, 0x07     //RGMII 1000 Mbps operation.
+        __cvmx_spi4000_write(interface, port_offset | 0x0010, 0x3);
+
+        // Set the max packet size to 16383 bytes, including the CRC
+        __cvmx_spi4000_write(interface, port_offset | 0x000f, 0x3fff);
+
+        // Step 6: Change Interface to Copper mode
+        //         Interface mode register. address=0x501
+        //         [Can't find this]
+
+        // Step 7: MAC configuration
+        //         Station address configuration.
+        //         Source MAC address low register. Source MAC address 31-0.
+        //             address=port_index+0x00
+        //         Source MAC address high register. Source MAC address 47-32.
+        //             address=port_index+0x01
+        //         where Port index is 0x0 to 0x5.
+        //         This address is inserted in the source address filed when
+        //         transmitting pause frames, and is also used to compare against
+        //         unicast pause frames at the receiving side.
+        //
+        //         OUT port_index+0x00, source MAC address low.
+        __cvmx_spi4000_write(interface, port_offset | 0x0000, 0x0000);
+        //         OUT port_index+0x01, source MAC address high.
+        __cvmx_spi4000_write(interface, port_offset | 0x0001, 0x0000);
+
+        // Step 8: Set desired duplex mode
+        //         Desired duplex register. address=port_index+0x02
+        //         [Reserved]
+
+        // Step 9: Other configuration.
+        //         FC Enable Register.             address=port_index+0x12
+        //         Discard Unknown Control Frame.  address=port_index+0x15
+        //         Diverse config write register.  address=port_index+0x18
+        //         RX Packet Filter register.      address=port_index+0x19
+        //
+        // Step 9a: Tx FD FC Enabled / Rx FD FC Enabled
+        if (CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE)
+            __cvmx_spi4000_write(interface, port_offset | 0x0012, 0);
+        else
+            __cvmx_spi4000_write(interface, port_offset | 0x0012, 0x7);
+
+        // Step 9b: Discard unknown control frames
+        __cvmx_spi4000_write(interface, port_offset | 0x0015, 0x1);
+
+        // Step 9c: Enable auto-CRC and auto-padding
+        __cvmx_spi4000_write(interface, port_offset | 0x0018, 0x11cd); //??
+
+        // Step 9d: Drop bad CRC / Drop Pause / No DAF
+        __cvmx_spi4000_write(interface, port_offset | 0x0019, 0x00);
+    }
+
+    // Step 9d: Drop frames
+    __cvmx_spi4000_write(interface, 0x059f, 0x03ff);
+
+    for (port=0; port < 10; port++)
+    {
+        // Step 9e: Set the TX FIFO marks
+        __cvmx_spi4000_write(interface, port + 0x0600, 0x0900); // TXFIFO High watermark
+        __cvmx_spi4000_write(interface, port + 0x060a, 0x0800); // TXFIFO Low watermark
+        __cvmx_spi4000_write(interface, port + 0x0614, 0x0380); // TXFIFO threshold
+    }
+
+    // Step 12: De-assert RxFIFO and SPI Rx/Tx reset
+    __cvmx_spi4000_write(interface, 0x059e, 0x0);    // reset the RX FIFOs
+
+    // Step 13: De-assert TxFIFO and MAC reset
+    __cvmx_spi4000_write(interface, 0x0620, 0x0);    // reset the TX FIFOs
+
+    // Step 14: Assert port enable
+    //          Global address and Configuration Register. address=0x500
+    __cvmx_spi4000_write(interface, 0x0500, 0x03ff); // enable all ports
+
+    // Step 15: Disable loopback
+    //          [Can't find this one]
+}
+
+
+/**
+ * @INTERNAL
+ * Configure the SPI4000 PHYs
+ */
+static void __cvmx_spi4000_configure_phy(int interface)
+{
+    int port;
+
+    /* We use separate loops below since it allows us to save a write
+        to the SPI4000 for each repeated value. This adds up to a couple
+        of seconds */
+
+    /* Update the link state before resets. It takes a while for the links to
+        come back after the resets. Most likely they'll come back the same as
+        they are now */
+    for (port=0; port < 10; port++)
+        cvmx_spi4000_check_speed(interface, port);
+    /* Enable RGMII DELAYS for TX_CLK and RX_CLK (see spec) */
+    for (port=0; port < 10; port++)
+        __cvmx_spi4000_mdio_write(interface, port, 0x14, 0x00e2);
+    /* Advertise pause and 100 Full Duplex. Don't advertise half duplex or 10Mbpa */
+    for (port=0; port < 10; port++)
+        __cvmx_spi4000_mdio_write(interface, port, 0x4, 0x0d01);
+    /* Enable PHY reset */
+    for (port=0; port < 10; port++)
+        __cvmx_spi4000_mdio_write(interface, port, 0x0, 0x9140);
+}
+
+
+/**
+ * Poll all the SPI4000 port and check its speed
+ *
+ * @param interface Interface the SPI4000 is on
+ * @param port      Port to poll (0-9)
+ * @return Status of the port. 0=down. All other values the port is up.
+ */
+cvmx_gmxx_rxx_rx_inbnd_t cvmx_spi4000_check_speed(int interface, int port)
+{
+    static int phy_status[10] = {0,};
+    cvmx_gmxx_rxx_rx_inbnd_t link;
+    int read_status;
+
+    link.u64 = 0;
+
+    if (!interface_is_spi4000[interface])
+        return link;
+    if (port>=10)
+        return link;
+
+    /* Register 0x11: PHY Specific Status Register
+         Register   Function         Setting                     Mode   HW Rst SW Rst Notes
+                                                                 RO     00     Retain note
+         17.15:14   Speed            11 = Reserved
+                                                                                      17.a
+                                     10 = 1000 Mbps
+                                     01 = 100 Mbps
+                                     00 = 10 Mbps
+         17.13      Duplex           1 = Full-duplex             RO     0      Retain note
+                                     0 = Half-duplex                                  17.a
+         17.12      Page Received    1 = Page received           RO, LH 0      0
+                                     0 = Page not received
+                                     1 = Resolved                RO     0      0      note
+         17.11      Speed and
+                                     0 = Not resolved                                 17.a
+                    Duplex
+                    Resolved
+         17.10      Link (real time) 1 = Link up                 RO     0      0
+                                     0 = Link down
+                                                                 RO     000    000    note
+                                     000 = < 50m
+         17.9:7     Cable Length
+                                     001 = 50 - 80m                                   17.b
+                    (100/1000
+                                     010 = 80 - 110m
+                    modes only)
+                                     011 = 110 - 140m
+                                     100 = >140m
+         17.6       MDI Crossover    1 = MDIX                    RO     0      0      note
+                    Status           0 = MDI                                          17.a
+         17.5       Downshift Sta-   1 = Downshift               RO     0      0
+                    tus              0 = No Downshift
+         17.4       Energy Detect    1 = Sleep                   RO     0      0
+                    Status           0 = Active
+         17.3       Transmit Pause   1 = Transmit pause enabled  RO     0      0      note17.
+                    Enabled          0 = Transmit pause disabled                      a, 17.c
+         17.2       Receive Pause    1 = Receive pause enabled   RO     0      0      note17.
+                    Enabled          0 = Receive pause disabled                       a, 17.c
+         17.1       Polarity (real   1 = Reversed                RO     0      0
+                    time)            0 = Normal
+         17.0       Jabber (real     1 = Jabber                  RO     0      Retain
+                    time)            0 = No jabber
+    */
+    read_status = __cvmx_spi4000_mdio_read(interface, port, 0x11);
+    if ((read_status & (1<<10)) == 0)
+        read_status = 0; /* If the link is down, force zero */
+    else
+        read_status &= 0xe400; /* Strip off all the don't care bits */
+    if (read_status != phy_status[port])
+    {
+        phy_status[port] = read_status;
+        if (read_status & (1<<10))
+        {
+            /* If the link is up, we need to set the speed based on the PHY status */
+            if (read_status & (1<<15))
+                __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
+            else
+                __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x1); /* 100Mbps */
+        }
+        else
+        {
+            /* If the link is down, force 1Gbps so TX traffic dumps fast */
+            __cvmx_spi4000_write(interface, (port<<7) | 0x0010, 0x3); /* 1Gbps */
+        }
+    }
+
+    if (read_status & (1<<10))
+    {
+        link.s.status = 1; /* Link up */
+        if (read_status & (1<<15))
+            link.s.speed = 2;
+        else
+            link.s.speed = 1;
+    }
+    else
+    {
+        link.s.speed = 2; /* Use 1Gbps when down */
+        link.s.status = 0; /* Link Down */
+    }
+    link.s.duplex = ((read_status & (1<<13)) != 0);
+
+    return link;
+}
+
+
+/**
+ * Return non-zero if the SPI interface has a SPI4000 attached
+ *
+ * @param interface SPI interface the SPI4000 is connected to
+ *
+ * @return
+ */
+int cvmx_spi4000_is_present(int interface)
+{
+    if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+        return 0;
+    // Check for the presence of a SPI4000. If it isn't there,
+    // these writes will timeout.
+    if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_HIGH, 0))
+        return 0;
+    if (cvmx_twsi_write8(SPI4000_TWSI_ID(interface), SPI4000_WRITE_ADDRESS_LOW, 0))
+        return 0;
+    interface_is_spi4000[interface] = 1;
+    return 1;
+}
+
+
+/**
+ * Initialize the SPI4000 for use
+ *
+ * @param interface SPI interface the SPI4000 is connected to
+ */
+int cvmx_spi4000_initialize(int interface)
+{
+    if (!cvmx_spi4000_is_present(interface))
+        return -1;
+
+    __cvmx_spi4000_configure_mac(interface);
+    __cvmx_spi4000_configure_phy(interface);
+    return 0;
+}
+
diff --git a/cvmx-spinlock.h b/cvmx-spinlock.h
new file mode 100644
index 0000000000000..a0725d6a6d7a6
--- /dev/null
+++ b/cvmx-spinlock.h
@@ -0,0 +1,430 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Implementation of spinlocks.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+#ifndef __CVMX_SPINLOCK_H__
+#define __CVMX_SPINLOCK_H__
+
+#include "cvmx-asm.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* Spinlocks for Octeon */
+
+
+// define these to enable recursive spinlock debugging
+//#define CVMX_SPINLOCK_DEBUG
+
+
+/**
+ * Spinlocks for Octeon
+ */
+typedef struct {
+    volatile uint32_t value;
+} cvmx_spinlock_t;
+
+// note - macros not expanded in inline ASM, so values hardcoded
+#define  CVMX_SPINLOCK_UNLOCKED_VAL  0
+#define  CVMX_SPINLOCK_LOCKED_VAL    1
+
+
+#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER  {CVMX_SPINLOCK_UNLOCKED_VAL}
+
+
+/**
+ * Initialize a spinlock
+ *
+ * @param lock   Lock to initialize
+ */
+static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
+{
+    lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+
+/**
+ * Return non-zero if the spinlock is currently locked
+ *
+ * @param lock   Lock to check
+ * @return Non-zero if locked
+ */
+static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
+{
+    return (lock->value != CVMX_SPINLOCK_UNLOCKED_VAL);
+}
+
+
+/**
+ * Releases lock
+ *
+ * @param lock   pointer to lock structure
+ */
+static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
+{
+    CVMX_SYNCWS;
+    lock->value = 0;
+    CVMX_SYNCWS;
+}
+
+
+/**
+ * Attempts to take the lock, but does not spin if lock is not available.
+ * May take some time to acquire the lock even if it is available
+ * due to the ll/sc not succeeding.
+ *
+ * @param lock   pointer to lock structure
+ *
+ * @return 0: lock successfully taken
+ *         1: lock not taken, held by someone else
+ * These return values match the Linux semantics.
+ */
+
+static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
+{
+    unsigned int tmp;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: ll   %[tmp], %[val] \n"
+    "   bnez %[tmp], 2f     \n"  // if lock held, fail immediately
+    "   li   %[tmp], 1      \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   li   %[tmp], 0      \n"
+    "2:                     \n"
+    ".set reorder           \n"
+    : [val] "+m" (lock->value), [tmp] "=&r" (tmp)
+    :
+    : "memory");
+
+    return (!!tmp);  /* normalize to 0 or 1 */
+}
+
+/**
+ * Gets lock, spins until lock is taken
+ *
+ * @param lock   pointer to lock structure
+ */
+static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
+{
+    unsigned int tmp;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    "1: ll   %[tmp], %[val]  \n"
+    "   bnez %[tmp], 1b     \n"
+    "   li   %[tmp], 1      \n"
+    "   sc   %[tmp], %[val] \n"
+    "   beqz %[tmp], 1b     \n"
+    "   nop                \n"
+    ".set reorder           \n"
+    : [val] "+m" (lock->value), [tmp] "=&r" (tmp)
+    :
+    : "memory");
+
+}
+
+
+
+/** ********************************************************************
+ * Bit spinlocks
+ * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
+ * The rest of the bits in the word are left undisturbed.  This enables more
+ * compact data structures as only 1 bit is consumed for the lock.
+ *
+ */
+
+/**
+ * Gets lock, spins until lock is taken
+ * Preserves the low 31 bits of the 32 bit
+ * word used for the lock.
+ *
+ *
+ * @param word  word to lock bit 31 of
+ */
+static inline void cvmx_spinlock_bit_lock(uint32_t *word)
+{
+    unsigned int tmp;
+    unsigned int sav;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    ".set noat              \n"
+    "1: ll    %[tmp], %[val]  \n"
+    "   bbit1 %[tmp], 31, 1b    \n"
+    "   li    $at, 1      \n"
+    "   ins   %[tmp], $at, 31, 1  \n"
+    "   sc    %[tmp], %[val] \n"
+    "   beqz  %[tmp], 1b     \n"
+    "   nop                \n"
+    ".set at              \n"
+    ".set reorder           \n"
+    : [val] "+m" (*word), [tmp] "=&r" (tmp), [sav] "=&r" (sav)
+    :
+    : "memory");
+
+}
+
+/**
+ * Attempts to get lock, returns immediately with success/failure
+ * Preserves the low 31 bits of the 32 bit
+ * word used for the lock.
+ *
+ *
+ * @param word  word to lock bit 31 of
+ * @return 0: lock successfully taken
+ *         1: lock not taken, held by someone else
+ * These return values match the Linux semantics.
+ */
+static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
+{
+    unsigned int tmp;
+
+    __asm__ __volatile__(
+    ".set noreorder         \n"
+    ".set noat              \n"
+    "1: ll    %[tmp], %[val] \n"
+    "   bbit1 %[tmp], 31, 2f     \n"  // if lock held, fail immediately
+    "   li    $at, 1      \n"
+    "   ins   %[tmp], $at, 31, 1  \n"
+    "   sc    %[tmp], %[val] \n"
+    "   beqz  %[tmp], 1b     \n"
+    "   li    %[tmp], 0      \n"
+    "2:                     \n"
+    ".set at              \n"
+    ".set reorder           \n"
+    : [val] "+m" (*word), [tmp] "=&r" (tmp)
+    :
+    : "memory");
+
+    return (!!tmp);  /* normalize to 0 or 1 */
+}
+/**
+ * Releases bit lock
+ *
+ * Unconditionally clears bit 31 of the lock word.  Note that this is
+ * done non-atomically, as this implementation assumes that the rest
+ * of the bits in the word are protected by the lock.
+ *
+ * @param word  word to unlock bit 31 in
+ */
+static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
+{
+    CVMX_SYNCWS;
+    *word &= ~(1UL << 31) ;
+    CVMX_SYNCWS;
+}
+
+
+
+/** ********************************************************************
+ * Recursive spinlocks
+ */
+typedef struct {
+	volatile unsigned int value;
+	volatile unsigned int core_num;
+} cvmx_spinlock_rec_t;
+
+
+/**
+ * Initialize a recursive spinlock
+ *
+ * @param lock   Lock to initialize
+ */
+static inline void cvmx_spinlock_rec_init(cvmx_spinlock_rec_t *lock)
+{
+    lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
+}
+
+
+/**
+ * Return non-zero if the recursive spinlock is currently locked
+ *
+ * @param lock   Lock to check
+ * @return Non-zero if locked
+ */
+static inline int cvmx_spinlock_rec_locked(cvmx_spinlock_rec_t *lock)
+{
+    return (lock->value != CVMX_SPINLOCK_UNLOCKED_VAL);
+}
+
+
+/**
+* Unlocks one level of recursive spinlock.  Lock is not unlocked
+* unless this is the final unlock call for that spinlock
+*
+* @param lock   ptr to recursive spinlock structure
+*/
+static inline void cvmx_spinlock_rec_unlock(cvmx_spinlock_rec_t *lock);
+
+#ifdef CVMX_SPINLOCK_DEBUG
+#define cvmx_spinlock_rec_unlock(x)  _int_cvmx_spinlock_rec_unlock((x), __FILE__, __LINE__)
+static inline void _int_cvmx_spinlock_rec_unlock(cvmx_spinlock_rec_t *lock, char *filename, int linenum)
+#else
+static inline void cvmx_spinlock_rec_unlock(cvmx_spinlock_rec_t *lock)
+#endif
+{
+
+	unsigned int temp, result;
+    int core_num;
+    core_num = cvmx_get_core_num();
+
+#ifdef CVMX_SPINLOCK_DEBUG
+    {
+        if (lock->core_num != core_num)
+        {
+            cvmx_dprintf("ERROR: Recursive spinlock release attemped by non-owner! file: %s, line: %d\n", filename, linenum);
+            return;
+        }
+    }
+#endif
+
+	__asm__ __volatile__(
+		".set  noreorder                 \n"
+		"     addi  %[tmp], %[pid], 0x80 \n"
+		"     sw    %[tmp], %[lid]       # set lid to invalid value\n"
+                CVMX_SYNCWS_STR
+		"1:   ll    %[tmp], %[val]       \n"
+		"     addu  %[res], %[tmp], -1   # decrement lock count\n"
+		"     sc    %[res], %[val]       \n"
+		"     beqz  %[res], 1b           \n"
+		"     nop                        \n"
+		"     beq   %[tmp], %[res], 2f   # res is 1 on successful sc       \n"
+		"     nop                        \n"
+		"     sw   %[pid], %[lid]        # set lid to pid, only if lock still held\n"
+		"2:                         \n"
+                CVMX_SYNCWS_STR
+		".set  reorder                   \n"
+		: [res] "=&r" (result), [tmp] "=&r" (temp), [val] "+m" (lock->value), [lid] "+m" (lock->core_num)
+		: [pid] "r" (core_num)
+		: "memory");
+
+
+#ifdef CVMX_SPINLOCK_DEBUG
+    {
+        if (lock->value == ~0UL)
+        {
+            cvmx_dprintf("ERROR: Recursive spinlock released too many times! file: %s, line: %d\n", filename, linenum);
+        }
+    }
+#endif
+
+
+}
+
+/**
+ * Takes recursive spinlock for a given core.  A core can take the lock multiple
+ * times, and the lock is released only when the corresponding number of
+ * unlocks have taken place.
+ *
+ * NOTE: This assumes only one thread per core, and that the core ID is used as
+ * the lock 'key'.  (This implementation cannot be generalized to allow
+ * multiple threads to use the same key (core id) .)
+ *
+ * @param lock   address of recursive spinlock structure.  Note that this is
+ *               distinct from the standard spinlock
+ */
+static inline void cvmx_spinlock_rec_lock(cvmx_spinlock_rec_t *lock);
+
+#ifdef CVMX_SPINLOCK_DEBUG
+#define cvmx_spinlock_rec_lock(x)  _int_cvmx_spinlock_rec_lock((x), __FILE__, __LINE__)
+static inline void _int_cvmx_spinlock_rec_lock(cvmx_spinlock_rec_t *lock, char *filename, int linenum)
+#else
+static inline void cvmx_spinlock_rec_lock(cvmx_spinlock_rec_t *lock)
+#endif
+{
+
+
+	volatile unsigned int tmp;
+	volatile int core_num;
+
+	core_num = cvmx_get_core_num();
+
+
+	__asm__ __volatile__(
+		".set  noreorder              \n"
+		"1: ll   %[tmp], %[val]       # load the count\n"
+		"   bnez %[tmp], 2f           # if count!=zero branch to 2\n"
+		"   addu %[tmp], %[tmp], 1    \n"
+		"   sc   %[tmp], %[val]       \n"
+		"   beqz %[tmp], 1b           # go back if not success\n"
+		"   nop                       \n"
+		"   j    3f                   # go to write core_num \n"
+		"2: lw   %[tmp], %[lid]       # load the core_num \n"
+		"   bne  %[tmp], %[pid], 1b   # core_num no match, restart\n"
+		"   nop                       \n"
+		"   lw   %[tmp], %[val]       \n"
+		"   addu %[tmp], %[tmp], 1    \n"
+		"   sw   %[tmp], %[val]       # update the count\n"
+		"3: sw   %[pid], %[lid]       # store the core_num\n"
+                CVMX_SYNCWS_STR
+		".set  reorder                \n"
+		: [tmp] "=&r" (tmp), [val] "+m" (lock->value), [lid] "+m" (lock->core_num)
+		: [pid] "r" (core_num)
+		: "memory");
+
+#ifdef CVMX_SPINLOCK_DEBUG
+    if (lock->core_num != core_num)
+    {
+        cvmx_dprintf("cvmx_spinlock_rec_lock: lock taken, but core_num is incorrect. file: %s, line: %d\n", filename, linenum);
+    }
+#endif
+
+
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/cvmx-swap.h b/cvmx-swap.h
new file mode 100644
index 0000000000000..2678fd6d3e247
--- /dev/null
+++ b/cvmx-swap.h
@@ -0,0 +1,141 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Utility functions for endian swapping
+ *
+ * <hr>$Revision: 32636 $<hr>
+ */
+
+#ifndef __CVMX_SWAP_H__
+#define __CVMX_SWAP_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Byte swap a 16 bit number
+ *
+ * @param x      16 bit number
+ * @return Byte swapped result
+ */
+static inline uint16_t cvmx_swap16(uint16_t x)
+{
+    return ((uint16_t)((((uint16_t)(x) & (uint16_t)0x00ffU) << 8) |
+                       (((uint16_t)(x) & (uint16_t)0xff00U) >> 8) ));
+}
+
+
+/**
+ * Byte swap a 32 bit number
+ *
+ * @param x      32 bit number
+ * @return Byte swapped result
+ */
+static inline uint32_t cvmx_swap32(uint32_t x)
+{
+    return ((uint32_t)((((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |
+                       (((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |
+                       (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |
+                       (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24) ));
+}
+
+
+/**
+ * Byte swap a 64 bit number
+ *
+ * @param x      64 bit number
+ * @return Byte swapped result
+ */
+static inline uint64_t cvmx_swap64(uint64_t x)
+{
+    return ((x >> 56) |
+            (((x >> 48) & 0xfful) << 8) |
+            (((x >> 40) & 0xfful) << 16) |
+            (((x >> 32) & 0xfful) << 24) |
+            (((x >> 24) & 0xfful) << 32) |
+            (((x >> 16) & 0xfful) << 40) |
+            (((x >>  8) & 0xfful) << 48) |
+            (((x >>  0) & 0xfful) << 56));
+}
+
+
+#if __BYTE_ORDER == __BIG_ENDIAN
+
+#define cvmx_cpu_to_le16(x) cvmx_swap16(x)
+#define cvmx_cpu_to_le32(x) cvmx_swap32(x)
+#define cvmx_cpu_to_le64(x) cvmx_swap64(x)
+
+#define cvmx_cpu_to_be16(x) (x)
+#define cvmx_cpu_to_be32(x) (x)
+#define cvmx_cpu_to_be64(x) (x)
+
+#else
+
+#define cvmx_cpu_to_le16(x) (x)
+#define cvmx_cpu_to_le32(x) (x)
+#define cvmx_cpu_to_le64(x) (x)
+
+#define cvmx_cpu_to_be16(x) cvmx_swap16(x)
+#define cvmx_cpu_to_be32(x) cvmx_swap32(x)
+#define cvmx_cpu_to_be64(x) cvmx_swap64(x)
+
+#endif
+
+#define cvmx_le16_to_cpu(x) cvmx_cpu_to_le16(x)
+#define cvmx_le32_to_cpu(x) cvmx_cpu_to_le32(x)
+#define cvmx_le64_to_cpu(x) cvmx_cpu_to_le64(x)
+
+#define cvmx_be16_to_cpu(x) cvmx_cpu_to_be16(x)
+#define cvmx_be32_to_cpu(x) cvmx_cpu_to_be32(x)
+#define cvmx_be64_to_cpu(x) cvmx_cpu_to_be64(x)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_SWAP_H__ */
diff --git a/cvmx-sysinfo.c b/cvmx-sysinfo.c
new file mode 100644
index 0000000000000..8146ded1e8910
--- /dev/null
+++ b/cvmx-sysinfo.c
@@ -0,0 +1,220 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This module provides system/board/application information obtained by the bootloader.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-sysinfo.h"
+
+
+/**
+ * This structure defines the private state maintained by sysinfo module.
+ *
+ */
+#if defined(CVMX_BUILD_FOR_UBOOT) && CONFIG_OCTEON_NAND_STAGE2
+/* For u-boot, put this in the text section so that we can use this in early
+** boot when running from ram(or L2 cache).  This is primarily used for NAND
+** access during NAND boot.   The 'data_in_text' section is merged with the
+** text section by the linker script to avoid an assembler warning. */
+static struct {
+
+    cvmx_sysinfo_t   sysinfo;      /**< system information */
+    cvmx_spinlock_t  lock;         /**< mutex spinlock */
+
+} state __attribute__ ((section (".data_in_text"))) = {
+    .lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER
+};
+#else
+CVMX_SHARED static struct {
+
+    cvmx_sysinfo_t   sysinfo;      /**< system information */
+    cvmx_spinlock_t  lock;         /**< mutex spinlock */
+
+} state = {
+    .lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER
+};
+#endif
+
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+/* Global variable with the processor ID since we can't read it directly */
+CVMX_SHARED uint32_t cvmx_app_init_processor_id;
+#endif
+
+/* Global variables that define the min/max of the memory region set up for 32 bit userspace access */
+uint64_t linux_mem32_min = 0;
+uint64_t linux_mem32_max = 0;
+uint64_t linux_mem32_wired = 0;
+uint64_t linux_mem32_offset = 0;
+
+/**
+ * This function returns the application information as obtained
+ * by the bootloader.  This provides the core mask of the cores
+ * running the same application image, as well as the physical
+ * memory regions available to the core.
+ *
+ * @return  Pointer to the boot information structure
+ *
+ */
+cvmx_sysinfo_t * cvmx_sysinfo_get(void)
+{
+    return &(state.sysinfo);
+}
+
+
+/**
+ * This function is used in non-simple executive environments (such as Linux kernel, u-boot, etc.)
+ * to configure the minimal fields that are required to use
+ * simple executive files directly.
+ *
+ * Locking (if required) must be handled outside of this
+ * function
+ *
+ * @param phy_mem_desc_ptr
+ *                   Pointer to global physical memory descriptor (bootmem descriptor)
+ * @param board_type Octeon board type enumeration
+ *
+ * @param board_rev_major
+ *                   Board major revision
+ * @param board_rev_minor
+ *                   Board minor revision
+ * @param cpu_clock_hz
+ *                   CPU clock freqency in hertz
+ *
+ * @return 0: Failure
+ *         1: success
+ */
+int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type, uint8_t board_rev_major,
+                                    uint8_t board_rev_minor, uint32_t cpu_clock_hz)
+{
+
+
+    memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo));
+    state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr;
+    state.sysinfo.board_type = board_type;
+    state.sysinfo.board_rev_major = board_rev_major;
+    state.sysinfo.board_rev_minor = board_rev_minor;
+    state.sysinfo.cpu_clock_hz = cpu_clock_hz;
+
+    return(1);
+}
+
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+/**
+ * Initialize the sysinfo structure when running on
+ * Octeon under Linux userspace
+ */
+void cvmx_sysinfo_linux_userspace_initialize(void)
+{
+    cvmx_sysinfo_t *system_info = cvmx_sysinfo_get();
+    memset(system_info, 0, sizeof(cvmx_sysinfo_t));
+
+    system_info->core_mask = 0;
+    system_info->init_core = -1;
+
+    FILE *infile = fopen("/proc/octeon_info", "r");
+    if (infile == NULL)
+    {
+        perror("Error opening /proc/octeon_info");
+        exit(-1);
+    }
+
+    while (!feof(infile))
+    {
+        char buffer[80];
+        if (fgets(buffer, sizeof(buffer), infile))
+        {
+            const char *field = strtok(buffer, " ");
+            const char *valueS = strtok(NULL, " ");
+            if (field == NULL)
+                continue;
+            if (valueS == NULL)
+                continue;
+            unsigned long long value;
+            sscanf(valueS, "%lli", &value);
+
+            if (strcmp(field, "dram_size:") == 0)
+                system_info->system_dram_size = value;
+            else if (strcmp(field, "phy_mem_desc_addr:") == 0)
+                system_info->phy_mem_desc_ptr = cvmx_phys_to_ptr(value);
+            else if (strcmp(field, "eclock_hz:") == 0)
+                system_info->cpu_clock_hz = value;
+            else if (strcmp(field, "dclock_hz:") == 0)
+                system_info->dram_data_rate_hz = value * 2;
+            else if (strcmp(field, "board_type:") == 0)
+                system_info->board_type = value;
+            else if (strcmp(field, "board_rev_major:") == 0)
+                system_info->board_rev_major = value;
+            else if (strcmp(field, "board_rev_minor:") == 0)
+                system_info->board_rev_minor = value;
+            else if (strcmp(field, "board_serial_number:") == 0)
+                strncpy(system_info->board_serial_number, valueS, sizeof(system_info->board_serial_number));
+            else if (strcmp(field, "mac_addr_base:") == 0)
+            {
+                int i;
+                int m[6];
+                sscanf(valueS, "%02x:%02x:%02x:%02x:%02x:%02x", m+0, m+1, m+2, m+3, m+4, m+5);
+                for (i=0; i<6; i++)
+                    system_info->mac_addr_base[i] = m[i];
+            }
+            else if (strcmp(field, "mac_addr_count:") == 0)
+                system_info->mac_addr_count = value;
+            else if (strcmp(field, "32bit_shared_mem_base:") == 0)
+                linux_mem32_min = value;
+            else if (strcmp(field, "32bit_shared_mem_size:") == 0)
+                linux_mem32_max = linux_mem32_min + value - 1;
+            else if (strcmp(field, "processor_id:") == 0)
+                cvmx_app_init_processor_id = value;
+            else if (strcmp(field, "32bit_shared_mem_wired:") == 0)
+                linux_mem32_wired = value;
+        }
+    }
+}
+#endif
diff --git a/cvmx-sysinfo.h b/cvmx-sysinfo.h
new file mode 100644
index 0000000000000..199a48b0fae49
--- /dev/null
+++ b/cvmx-sysinfo.h
@@ -0,0 +1,166 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This module provides system/board information obtained by the bootloader.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+
+#ifndef __CVMX_SYSINFO_H__
+#define __CVMX_SYSINFO_H__
+
+#include "cvmx-app-init.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define OCTEON_SERIAL_LEN 20
+/**
+ * Structure describing application specific information.
+ * __cvmx_app_init() populates this from the cvmx boot descriptor.
+ * This structure is private to simple executive applications, so
+ * no versioning is required.
+ *
+ * This structure must be provided with some fields set in order to use
+ * simple executive functions in other applications (Linux kernel, u-boot, etc.)
+ * The cvmx_sysinfo_minimal_initialize() function is provided to set the required values
+ * in these cases.
+ *
+ *
+ */
+typedef struct {
+    /* System wide variables */
+    uint64_t system_dram_size;  /**< installed DRAM in system, in bytes */
+    void *phy_mem_desc_ptr;  /**< ptr to memory descriptor block */
+
+    /* Application image specific variables */
+    uint64_t stack_top;  /**< stack top address (virtual) */
+    uint64_t heap_base;  /**< heap base address (virtual) */
+    uint32_t stack_size; /**< stack size in bytes */
+    uint32_t heap_size;  /**< heap size in bytes */
+    uint32_t core_mask;  /**< coremask defining cores running application */
+    uint32_t init_core;  /**< Deprecated, use cvmx_coremask_first_core() to select init core */
+    uint64_t exception_base_addr;  /**< exception base address, as set by bootloader */
+    uint32_t cpu_clock_hz;     /**< cpu clock speed in hz */
+    uint32_t dram_data_rate_hz;  /**< dram data rate in hz (data rate = 2 * clock rate */
+
+    uint16_t board_type;
+    uint8_t  board_rev_major;
+    uint8_t  board_rev_minor;
+    uint8_t  mac_addr_base[6];
+    uint8_t  mac_addr_count;
+    char     board_serial_number[OCTEON_SERIAL_LEN];
+    /* Several boards support compact flash on the Octeon boot bus.  The CF
+    ** memory spaces may be mapped to different addresses on different boards.
+    ** These values will be 0 if CF is not present.
+    ** Note that these addresses are physical addresses, and it is up to the application
+    ** to use the proper addressing mode (XKPHYS, KSEG0, etc.)*/
+    uint64_t compact_flash_common_base_addr;
+    uint64_t compact_flash_attribute_base_addr;
+    /* Base address of the LED display (as on EBT3000 board)
+    ** This will be 0 if LED display not present.
+    ** Note that this address is a physical address, and it is up to the application
+    ** to use the proper addressing mode (XKPHYS, KSEG0, etc.)*/
+    uint64_t led_display_base_addr;
+    uint32_t dfa_ref_clock_hz;  /**< DFA reference clock in hz (if applicable)*/
+    uint32_t bootloader_config_flags;  /**< configuration flags from bootloader */
+    uint8_t  console_uart_num;         /** < Uart number used for console */
+} cvmx_sysinfo_t;
+
+
+/**
+ * This function returns the system/board information as obtained
+ * by the bootloader.
+ *
+ *
+ * @return  Pointer to the boot information structure
+ *
+ */
+
+extern cvmx_sysinfo_t * cvmx_sysinfo_get(void);
+
+
+/**
+ * This function is used in non-simple executive environments (such as Linux kernel, u-boot, etc.)
+ * to configure the minimal fields that are required to use
+ * simple executive files directly.
+ *
+ * Locking (if required) must be handled outside of this
+ * function
+ *
+ * @param phy_mem_desc_ptr
+ *                   Pointer to global physical memory descriptor (bootmem descriptor)
+ * @param board_type Octeon board type enumeration
+ *
+ * @param board_rev_major
+ *                   Board major revision
+ * @param board_rev_minor
+ *                   Board minor revision
+ * @param cpu_clock_hz
+ *                   CPU clock freqency in hertz
+ *
+ * @return 0: Failure
+ *         1: success
+ */
+extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, uint16_t board_type, uint8_t board_rev_major,
+                                    uint8_t board_rev_minor, uint32_t cpu_clock_hz);
+
+#ifdef CVMX_BUILD_FOR_LINUX_USER
+/**
+ * Initialize the sysinfo structure when running on
+ * Octeon under Linux userspace
+ */
+extern void cvmx_sysinfo_linux_userspace_initialize(void);
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_SYSINFO_H__ */
diff --git a/cvmx-thunder.c b/cvmx-thunder.c
new file mode 100644
index 0000000000000..4bafa1d29b494
--- /dev/null
+++ b/cvmx-thunder.c
@@ -0,0 +1,328 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the Thunder specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-thunder.h"
+#include "cvmx-gpio.h"
+#include "cvmx-twsi.h"
+
+
+static const int BYPASS_STATUS = 1<<5; /* GPIO 5 */
+static const int BYPASS_EN     = 1<<6; /* GPIO 6 */
+static const int WDT_BP_CLR    = 1<<7; /* GPIO 7 */
+
+static const int RTC_CTL_ADDR = 0x7;
+static const int RTC_CTL_BIT_EOSC   = 0x80;
+static const int RTC_CTL_BIT_WACE   = 0x40;
+static const int RTC_CTL_BIT_WD_ALM = 0x20;
+static const int RTC_CTL_BIT_WDSTR  = 0x8;
+static const int RTC_CTL_BIT_AIE    = 0x1;
+static const int RTC_WD_ALM_CNT_BYTE0_ADDR = 0x4;
+
+#define CVMX_LAN_BYPASS_MSG(...)  do {} while(0)
+
+/*
+ * Board-specifc RTC read
+ * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ */
+uint32_t cvmx_rtc_ds1374_read(void)
+{
+    int      retry;
+    uint8_t  sec;
+    uint32_t time;
+
+    for(retry=0; retry<2; retry++)
+    {
+        time = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0);
+        time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 8;
+        time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 16;
+        time |= (cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR) & 0xff) << 24;
+
+        sec = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0);
+        if (sec == (time & 0xff))
+            break; /* Time did not roll-over, value is correct */
+    }
+
+    return time;
+}
+
+/*
+ * Board-specific RTC write
+ * Time is expressed in seconds from epoch (Jan 1 1970 at 00:00:00 UTC)
+ */
+int cvmx_rtc_ds1374_write(uint32_t time)
+{
+    int      rc;
+    int      retry;
+    uint8_t  sec;
+
+    for(retry=0; retry<2; retry++)
+    {
+        rc  = cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x0, time & 0xff);
+        rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x1, (time >> 8) & 0xff);
+        rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x2, (time >> 16) & 0xff);
+        rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, 0x3, (time >> 24) & 0xff);
+        sec = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0);
+        if (sec == (time & 0xff))
+            break; /* Time did not roll-over, value is correct */
+    }
+
+    return (rc ? -1 : 0);
+}
+
+int cvmx_rtc_ds1374_alarm_config(int WD, int WDSTR, int AIE)
+{
+    int val;
+
+    val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR);
+    val = val & ~RTC_CTL_BIT_EOSC; /* Make sure that oscillator is running */
+    WD?(val = val | RTC_CTL_BIT_WD_ALM):(val = val & ~RTC_CTL_BIT_WD_ALM);
+    WDSTR?(val = val | RTC_CTL_BIT_WDSTR):(val = val & ~RTC_CTL_BIT_WDSTR);
+    AIE?(val = val | RTC_CTL_BIT_AIE):(val = val & ~RTC_CTL_BIT_AIE);
+    cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val);
+    return 0;
+}
+
+int cvmx_rtc_ds1374_alarm_set(int alarm_on)
+{
+    uint8_t val;
+
+    if (alarm_on)
+    {
+        val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR);
+        cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val | RTC_CTL_BIT_WACE);
+    }
+    else
+    {
+        val = cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR);
+        cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR,RTC_CTL_ADDR, val & ~RTC_CTL_BIT_WACE);
+    }
+    return 0;
+}
+
+
+int cvmx_rtc_ds1374_alarm_counter_set(uint32_t interval)
+{
+    int i;
+    int rc = 0;
+
+    for(i=0;i<3;i++)
+    {
+        rc |= cvmx_twsi_write8(CVMX_RTC_DS1374_ADDR, RTC_WD_ALM_CNT_BYTE0_ADDR+i, interval & 0xFF);
+        interval >>= 8;
+    }
+    return rc;
+}
+
+uint32_t cvmx_rtc_ds1374_alarm_counter_get(void)
+{
+    int i;
+    uint32_t interval = 0;
+
+    for(i=0;i<3;i++)
+    {
+        interval |= ( cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR,RTC_WD_ALM_CNT_BYTE0_ADDR+i) & 0xff) << (i*8);
+    }
+    return interval;
+}
+
+
+#ifdef CVMX_RTC_DEBUG
+
+void cvmx_rtc_ds1374_dump_state(void)
+{
+    int i = 0;
+
+    cvmx_dprintf("RTC:\n");
+    cvmx_dprintf("%d : %02X ", i, cvmx_twsi_read8(CVMX_RTC_DS1374_ADDR, 0x0));
+    for(i=1; i<10; i++)
+    {
+        cvmx_dprintf("%02X ", cvmx_twsi_read8_cur_addr(CVMX_RTC_DS1374_ADDR));
+    }
+    cvmx_dprintf("\n");
+}
+
+#endif /* CVMX_RTC_DEBUG */
+
+
+/*
+ *  LAN bypass functionality
+ */
+
+/* Private initialization function */
+static int cvmx_lan_bypass_init(void)
+{
+    const int CLR_PULSE = 100;  /* Longer than 100 ns (on CPUs up to 1 GHz) */
+
+    //Clear GPIO 6
+    cvmx_gpio_clear(BYPASS_EN);
+
+    //Disable WDT
+    cvmx_rtc_ds1374_alarm_set(0);
+
+    //GPIO(7) Send a low pulse
+    cvmx_gpio_clear(WDT_BP_CLR);
+    cvmx_wait(CLR_PULSE);
+    cvmx_gpio_set(WDT_BP_CLR);
+    return 0;
+}
+
+/**
+ * Set LAN bypass mode.
+ *
+ * Supported modes are:
+ * - CVMX_LAN_BYPASS_OFF
+ *     <br>LAN ports are connected ( port 0 <--> Octeon <--> port 1 )
+ *
+ * - CVMX_LAN_BYPASS_GPIO
+ *     <br>LAN bypass is controlled by software using cvmx_lan_bypass_force() function.
+ *     When transitioning to this mode, default is LAN bypass enabled
+ *     ( port 0 <--> port 1, -- Octeon ).
+ *
+ * - CVMX_LAN_BYPASS_WATCHDOG
+ *     <br>LAN bypass is inactive as long as a watchdog is kept alive.
+ *     The default expiration time is 1 second and the function to
+ *     call periodically to prevent watchdog expiration is
+ *     cvmx_lan_bypass_keep_alive().
+ *
+ * @param mode           LAN bypass mode
+ *
+ * @return Error code, or 0 in case of success
+ */
+int cvmx_lan_bypass_mode_set(cvmx_lan_bypass_mode_t mode)
+{
+    switch(mode)
+    {
+    case CVMX_LAN_BYPASS_GPIO:
+        /* make lan bypass enable */
+        cvmx_lan_bypass_init();
+        cvmx_gpio_set(BYPASS_EN);
+        CVMX_LAN_BYPASS_MSG("Enable LAN bypass by GPIO. \n");
+        break;
+
+    case CVMX_LAN_BYPASS_WATCHDOG:
+        /* make lan bypass enable */
+        cvmx_lan_bypass_init();
+        /* Set WDT parameters and turn it on */
+        cvmx_rtc_ds1374_alarm_counter_set(0x1000);    /* 4096 ticks = 1 sec */
+        cvmx_rtc_ds1374_alarm_config(1,1,1);
+        cvmx_rtc_ds1374_alarm_set(1);
+        CVMX_LAN_BYPASS_MSG("Enable LAN bypass by WDT. \n");
+        break;
+
+    case CVMX_LAN_BYPASS_OFF:
+        /* make lan bypass disable */
+        cvmx_lan_bypass_init();
+        CVMX_LAN_BYPASS_MSG("Disable LAN bypass. \n");
+        break;
+
+    default:
+        CVMX_LAN_BYPASS_MSG("%s: LAN bypass mode %d not supported\n", __FUNCTION__, mode);
+        break;
+    }
+    return 0;
+}
+
+/**
+ * Refresh watchdog timer.
+ *
+ * Call periodically (less than 1 second) to prevent triggering LAN bypass.
+ * The alternative cvmx_lan_bypass_keep_alive_ms() is provided for cases
+ * where a variable interval is required.
+ */
+void cvmx_lan_bypass_keep_alive(void)
+{
+    cvmx_rtc_ds1374_alarm_counter_set(0x1000);    /* 4096 ticks = 1 second */
+}
+
+/**
+ * Refresh watchdog timer, setting a specific expiration interval.
+ *
+ * @param interval_ms     Interval, in milliseconds, to next watchdog expiration.
+ */
+void cvmx_lan_bypass_keep_alive_ms(uint32_t interval_ms)
+{
+    cvmx_rtc_ds1374_alarm_counter_set((interval_ms * 0x1000) / 1000);
+}
+
+/**
+ * Control LAN bypass via software.
+ *
+ * @param force_bypass   Force LAN bypass to active (1) or inactive (0)
+ *
+ * @return Error code, or 0 in case of success
+ */
+int cvmx_lan_bypass_force(int force_bypass)
+{
+    if (force_bypass)
+    {
+        //Set GPIO 6
+        cvmx_gpio_set(BYPASS_EN);
+    }
+    else
+    {
+        cvmx_lan_bypass_init();
+    }
+    return 0;
+}
+
+/**
+ * Return status of LAN bypass circuit.
+ *
+ * @return 1 if ports are in LAN bypass, or 0 if normally connected
+ */
+int cvmx_lan_bypass_is_active(void)
+{
+    return !!(cvmx_gpio_read() & BYPASS_STATUS);
+}
diff --git a/cvmx-thunder.h b/cvmx-thunder.h
new file mode 100644
index 0000000000000..662dcfa97c693
--- /dev/null
+++ b/cvmx-thunder.h
@@ -0,0 +1,148 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+#ifndef __CVMX_THUNDER_H__
+#define __CVMX_THUNDER_H__
+
+/**
+ * @file
+ *
+ * Interface to the Thunder specific devices
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_RTC_DS1374_ADDR   (0x68)
+
+/*
+ * Read time-of-day counter.
+ * This function is called internally by cvmx-rtc functions.
+ */
+uint32_t cvmx_rtc_ds1374_read(void);
+
+/*
+ * Write time-of-day counter.
+ * This function is called internally by cvmx-rtc functions.
+ */
+int      cvmx_rtc_ds1374_write(uint32_t time);
+
+
+/**
+ * LAN bypass modes.
+ */
+typedef enum {
+    CVMX_LAN_BYPASS_OFF = 0,   /**< LAN bypass is disabled, port 0 and port 1
+                                    are always connected to Octeon */
+    CVMX_LAN_BYPASS_GPIO,      /**< LAN bypass controlled by GPIO only */
+    CVMX_LAN_BYPASS_WATCHDOG,  /**< LAN bypass controlled by watchdog (and GPIO) */
+    CVMX_LAN_BYPASS_LAST       /* Keep as last entry */
+} cvmx_lan_bypass_mode_t;
+
+
+/**
+ * Set LAN bypass mode.
+ *
+ * Supported modes are:
+ * - CVMX_LAN_BYPASS_OFF
+ *     <br>LAN ports are connected ( port 0 <--> Octeon <--> port 1 )
+ *
+ * - CVMX_LAN_BYPASS_GPIO
+ *     <br>LAN bypass is controlled by software using cvmx_lan_bypass_force() function.
+ *     When transitioning to this mode, default is LAN bypass enabled
+ *     ( port 0 <--> port 1, disconnected from Octeon ).
+ *
+ * - CVMX_LAN_BYPASS_WATCHDOG
+ *     <br>LAN bypass is inactive as long as the watchdog is kept alive.
+ *     The default expiration time is 1 second and the function to
+ *     call periodically to prevent watchdog expiration is
+ *     cvmx_lan_bypass_keep_alive().
+ *
+ * @param mode           LAN bypass mode
+ *
+ * @return Error code, or 0 in case of success
+ */
+int  cvmx_lan_bypass_mode_set(cvmx_lan_bypass_mode_t mode);
+
+/**
+ * Return status of LAN bypass circuit.
+ *
+ * @return 1 if ports are in LAN bypass, or 0 if normally connected
+ */
+int  cvmx_lan_bypass_is_active(void);
+
+/**
+ * Refresh watchdog timer.
+ *
+ * Call periodically (less than 1 second) to prevent triggering LAN bypass.
+ * The alternative cvmx_lan_bypass_keep_alive_ms() is provided for cases
+ * where a variable interval is required.
+ */
+void cvmx_lan_bypass_keep_alive(void);
+
+/**
+ * Refresh watchdog timer, setting a specific expiration interval.
+ *
+ * @param interval_ms     Interval, in milliseconds, to next watchdog expiration.
+ */
+void cvmx_lan_bypass_keep_alive_ms(uint32_t interval_ms);
+
+/**
+ * Control LAN bypass via software.
+ *
+ * @param force_bypass   Force LAN bypass to active (1) or inactive (0)
+ *
+ * @return Error code, or 0 in case of success
+ */
+int  cvmx_lan_bypass_force(int force_bypass);
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_THUNDER_H__ */
diff --git a/cvmx-tim.c b/cvmx-tim.c
new file mode 100644
index 0000000000000..57e9c75ce19a7
--- /dev/null
+++ b/cvmx-tim.c
@@ -0,0 +1,270 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the hardware work queue timers.
+ *
+ * <hr>$Revision: 42180 $<hr>
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-tim.h"
+#include "cvmx-bootmem.h"
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Global structure holding the state of all timers.
+ */
+CVMX_SHARED cvmx_tim_t cvmx_tim;
+
+
+#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+/**
+ * Setup a timer for use. Must be called before the timer
+ * can be used.
+ *
+ * @param tick      Time between each bucket in microseconds. This must not be
+ *                  smaller than 1024/(clock frequency in MHz).
+ * @param max_ticks The maximum number of ticks the timer must be able
+ *                  to schedule in the future. There are guaranteed to be enough
+ *                  timer buckets such that:
+ *                  number of buckets >= max_ticks.
+ * @return Zero on success. Negative on error. Failures are possible
+ *         if the number of buckets needed is too large or memory
+ *         allocation fails for creating the buckets.
+ */
+int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
+{
+    cvmx_tim_mem_ring0_t    config_ring0;
+    cvmx_tim_mem_ring1_t    config_ring1;
+    uint64_t                timer_id;
+    int                     error = -1;
+#if !(defined(__KERNEL__) && defined(linux))
+    cvmx_sysinfo_t         *sys_info_ptr = cvmx_sysinfo_get();
+    uint64_t                cpu_clock_hz = sys_info_ptr->cpu_clock_hz;
+#else
+    uint64_t                cpu_clock_hz = octeon_get_clock_rate();
+#endif
+    uint64_t                hw_tick_ns;
+    uint64_t                hw_tick_ns_allowed;
+    uint64_t                tick_ns = 1000 * tick;
+    int                     i;
+    uint32_t                temp;
+
+    /* for the simulator */
+    if (cpu_clock_hz == 0)
+      cpu_clock_hz = 333000000;
+
+    hw_tick_ns = 1024 * 1000000000ull / cpu_clock_hz;
+    /* 
+     * Doulbe the minmal allowed tick to 2* HW tick.  tick between
+     * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval 
+     * to zero, or 1024 cycles. This is not enough time for the timer unit
+     * to fetch the bucket data, Resulting in timer ring error interrupt 
+     * be always generated. Avoid such setting in software 
+     */
+    hw_tick_ns_allowed = hw_tick_ns *2;
+
+    /* Make sure the timers are stopped */
+    cvmx_tim_stop();
+
+    /* Reinitialize out timer state */
+    memset(&cvmx_tim, 0, sizeof(cvmx_tim));
+    
+
+    if ((tick_ns < (hw_tick_ns_allowed)) || (tick_ns > 4194304 * hw_tick_ns))
+      {
+	cvmx_dprintf("init: tick wrong size. Requested tick %lu(ns) is smaller than" 
+		     " the minimal ticks allowed by hardware %lu(ns)\n", 
+		     tick_ns, hw_tick_ns_allowed);
+	return error;
+      }
+
+    for (i=2; i<20; i++)
+    {
+      if (tick_ns < (hw_tick_ns << i))
+	break;
+    }
+
+    cvmx_tim.max_ticks = (uint32_t)max_ticks;
+    cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10);
+    cvmx_tim.tick_cycles = tick * cpu_clock_hz / 1000000;
+
+    temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift;
+
+    /* round up to nearest power of 2 */
+    temp -= 1;
+    temp = temp | (temp >> 1);
+    temp = temp | (temp >> 2);
+    temp = temp | (temp >> 4);
+    temp = temp | (temp >> 8);
+    temp = temp | (temp >> 16);
+    cvmx_tim.num_buckets = temp + 1;
+
+    /* ensure input params fall into permitted ranges */
+    if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576)
+      {
+	cvmx_dprintf("init: num_buckets out of range\n");
+	return error;
+      }
+
+    /* Allocate the timer buckets from hardware addressable memory */
+    cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets
+					 * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE);
+    if (cvmx_tim.bucket == NULL)
+      {
+	cvmx_dprintf("init: allocation problem\n");
+	return error;
+      }
+    memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t));
+
+    cvmx_tim.start_time = 0;
+
+    /* Loop through all timers */
+    for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
+    {
+        cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets;
+        /* Tell the hardware where about the bucket array */
+        config_ring0.u64 = 0;
+        config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
+        config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
+        config_ring0.s.ring = timer_id;
+        cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
+
+        /* Tell the hardware the size of each chunk block in pointers */
+        config_ring1.u64 = 0;
+        config_ring1.s.enable = 1;
+        config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
+        config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
+        config_ring1.s.interval = (1 << (cvmx_tim.bucket_shift - 10)) - 1;
+        config_ring1.s.ring = timer_id;
+        cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
+    }
+
+    return 0;
+}
+#endif
+
+/**
+ * Start the hardware timer processing
+ */
+void cvmx_tim_start(void)
+{
+    cvmx_tim_control_t control;
+
+    control.u64 = 0;
+    control.s.enable_dwb = 1;
+    control.s.enable_timers = 1;
+
+    /* Remember when we started the timers */
+    cvmx_tim.start_time = cvmx_get_cycle();
+    cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
+}
+
+
+/**
+ * Stop the hardware timer processing. Timers stay configured.
+ */
+void cvmx_tim_stop(void)
+{
+    cvmx_tim_control_t control;
+    control.u64 = 0;
+    control.s.enable_dwb = 0;
+    control.s.enable_timers = 0;
+    cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
+}
+
+
+/**
+ * Stop the timer. After this the timer must be setup again
+ * before use.
+ */
+#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+void cvmx_tim_shutdown(void)
+{
+    uint32_t                bucket;
+    uint64_t                timer_id;
+    uint64_t                entries_per_chunk;
+
+    /* Make sure the timers are stopped */
+    cvmx_tim_stop();
+
+    entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1;
+
+    /* Now walk all buckets freeing the chunks */
+    for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
+    {
+        for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++)
+        {
+            uint64_t chunk_addr;
+            uint64_t next_chunk_addr;
+            cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket;
+            CVMX_PREFETCH128(CAST64(bucket_ptr));  /* prefetch the next cacheline for future buckets */
+
+            /* Each bucket contains a list of chunks */
+            chunk_addr = bucket_ptr->first_chunk_addr;
+            while (bucket_ptr->num_entries)
+            {
+#ifdef DEBUG
+                cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr));
+#endif
+                /* Read next chunk pointer from end of the current chunk */
+                next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8));
+
+                cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0);
+                chunk_addr = next_chunk_addr;
+                if (bucket_ptr->num_entries > entries_per_chunk)
+                    bucket_ptr->num_entries -= entries_per_chunk;
+                else
+                    bucket_ptr->num_entries = 0;
+            }
+        }
+    }
+}
+
+#endif
diff --git a/cvmx-tim.h b/cvmx-tim.h
new file mode 100644
index 0000000000000..19a1c8aa02be3
--- /dev/null
+++ b/cvmx-tim.h
@@ -0,0 +1,333 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the hardware work queue timers.
+ *
+`* <hr>$Revision: 42186 $<hr>
+ */
+
+#ifndef __CVMX_TIM_H__
+#define __CVMX_TIM_H__
+
+#include "cvmx-fpa.h"
+#include "cvmx-wqe.h"
+
+#include "executive-config.h"
+#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+#include "cvmx-config.h"
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_TIM_NUM_TIMERS   16
+#define CVMX_TIM_NUM_BUCKETS  2048
+
+typedef enum
+{
+    CVMX_TIM_STATUS_SUCCESS = 0,
+    CVMX_TIM_STATUS_NO_MEMORY = -1,
+    CVMX_TIM_STATUS_TOO_FAR_AWAY = -2,
+    CVMX_TIM_STATUS_BUSY = -3
+} cvmx_tim_status_t;
+
+/**
+ * Each timer bucket contains a list of work queue entries to
+ * schedule when the timer fires. The list is implemented as
+ * a linked list of blocks. Each block contains an array of
+ * work queue entries followed by a next block pointer. Since
+ * these blocks are dynamically allocated off of a hardware
+ * memory pool, there actual size isn't known compile time.
+ * The next block pointer is stored in the last 8 bytes of
+ * the memory block.
+ */
+typedef struct cvmx_tim_entry_chunk
+{
+    volatile uint64_t entries[0];
+} cvmx_tim_entry_chunk_t;
+
+/**
+ * Each timer contains an array of buckets. Each bucket
+ * represents the list of work queue entries that should be
+ * scheduled when the timer fires.  The first 3 entries are used
+ * byt the hardware.
+ */
+typedef struct
+{
+   volatile uint64_t                first_chunk_addr;
+   volatile uint32_t                num_entries;    /**< Zeroed by HW after traversing list */
+   volatile uint32_t                chunk_remainder;/**< Zeroed by HW after traversing list */
+
+   // the remaining 16 bytes are not touched by hardware
+   volatile cvmx_tim_entry_chunk_t *last_chunk;
+   uint64_t                         pad;
+} cvmx_tim_bucket_entry_t;
+
+/**
+ * Structure representing an individual timer. Each timer has
+ * a timer period, a memory management pool, and a list of
+ * buckets.
+ */
+typedef struct
+{
+    cvmx_tim_bucket_entry_t*bucket;             /**< The timer buckets. Array of [CVMX_TIM_NUM_TIMERS][CVMX_TIM_NUM_BUCKETS] */
+    uint64_t                tick_cycles;        /**< How long a bucket represents */
+    uint64_t                start_time;         /**< Time the timer started in cycles */
+    uint32_t                bucket_shift;       /**< How long a bucket represents in ms */
+    uint32_t                num_buckets;        /**< How many buckets per wheel */
+    uint32_t                max_ticks;          /**< maximum number of ticks allowed for timer */
+} cvmx_tim_t;
+
+/**
+ * Structure used to store state information needed to delete
+ * an already scheduled timer entry. An instance of this
+ * structure must be passed to cvmx_tim_add_entry in order
+ * to be able to delete an entry later with
+ * cvmx_tim_delete_entry.
+ *
+ * NOTE: This structure should be considered opaque by the application,
+ * and the application should not access its members
+ */
+typedef struct
+{
+    uint64_t        commit_cycles;  /**< After this time the timer can't be changed */
+    uint64_t *      timer_entry_ptr;/**< Where the work entry is. Zero this
+                                            location to delete the entry */
+} cvmx_tim_delete_t;
+
+/**
+ * Global structure holding the state of all timers.
+ */
+extern cvmx_tim_t cvmx_tim;
+
+
+
+
+#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+/**
+ * Setup a timer for use. Must be called before the timer
+ * can be used.
+ *
+ * @param tick      Time between each bucket in microseconds. This must not be
+ *                  smaller than 1024/(clock frequency in MHz).
+ * @param max_ticks The maximum number of ticks the timer must be able
+ *                  to schedule in the future. There are guaranteed to be enough
+ *                  timer buckets such that:
+ *                  number of buckets >= max_ticks.
+ * @return Zero on success. Negative on error. Failures are possible
+ *         if the number of buckets needed is too large or memory
+ *         allocation fails for creating the buckets.
+ */
+int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks);
+#endif
+
+/**
+ * Start the hardware timer processing
+ */
+extern void cvmx_tim_start(void);
+
+
+/**
+ * Stop the hardware timer processing. Timers stay configured.
+ */
+extern void cvmx_tim_stop(void);
+
+
+/**
+ * Stop the timer. After this the timer must be setup again
+ * before use.
+ */
+#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+extern void cvmx_tim_shutdown(void);
+#endif
+
+#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
+/**
+ * Add a work queue entry to the timer.
+ *
+ * @param work_entry Work queue entry to add.
+ * @param ticks_from_now
+ * @param delete_info
+ *                   Optional pointer where to store information needed to
+ *                   delete the timer entry. If non NULL information needed
+ *                   to delete the timer entry before it fires is stored here.
+ *                   If you don't need to be able to delete the timer, pass
+ *                   NULL.
+ * @return Result return code
+ */
+static inline cvmx_tim_status_t cvmx_tim_add_entry(cvmx_wqe_t *work_entry, uint64_t ticks_from_now, cvmx_tim_delete_t *delete_info)
+{
+    cvmx_tim_bucket_entry_t*    work_bucket_ptr;
+    uint64_t                    current_bucket;
+    uint64_t                    work_bucket;
+    volatile uint64_t         * tim_entry_ptr;  /* pointer to wqe address in timer chunk */
+    uint64_t                    entries_per_chunk;
+
+    const uint64_t  cycles  = cvmx_get_cycle(); /* Get our reference time early for accuracy */
+    const uint64_t  core_num    = cvmx_get_core_num();  /* One timer per processor, so use this to select */
+
+    /* Make sure the specified time won't wrap our bucket list */
+    if (ticks_from_now > cvmx_tim.max_ticks)
+    {
+        cvmx_dprintf("cvmx_tim_add_entry: Tried to schedule work too far away.\n");
+        return CVMX_TIM_STATUS_TOO_FAR_AWAY;
+    }
+
+    /* Since we have no way to synchronize, we can't update a timer that is
+        being used by the hardware. Two buckets forward should be safe */
+    if (ticks_from_now < 2)
+    {
+        cvmx_dprintf("cvmx_tim_add_entry: Tried to schedule work too soon. Delaying it.\n");
+        ticks_from_now = 2;
+    }
+
+    /* Get the bucket this work queue entry should be in. Remember the bucket
+        array is circular */
+    current_bucket = ((cycles - cvmx_tim.start_time)
+		   >> cvmx_tim.bucket_shift);
+    work_bucket = (((ticks_from_now * cvmx_tim.tick_cycles) + cycles - cvmx_tim.start_time)
+		   >> cvmx_tim.bucket_shift);
+
+    work_bucket_ptr = cvmx_tim.bucket + core_num * cvmx_tim.num_buckets + (work_bucket & (cvmx_tim.num_buckets - 1));
+    entries_per_chunk = (CVMX_FPA_TIMER_POOL_SIZE/8 - 1);
+
+    /* Check if we have room to add this entry into the existing list */
+    if (work_bucket_ptr->chunk_remainder)
+    {
+        /* Adding the work entry to the end of the existing list */
+        tim_entry_ptr = &(work_bucket_ptr->last_chunk->entries[entries_per_chunk - work_bucket_ptr->chunk_remainder]);
+        *tim_entry_ptr = cvmx_ptr_to_phys(work_entry);
+        work_bucket_ptr->chunk_remainder--;
+        work_bucket_ptr->num_entries++;
+    }
+    else
+    {
+        /* Current list is either completely empty or completely full. We need
+            to allocate a new chunk for storing this work entry */
+        cvmx_tim_entry_chunk_t *new_chunk = (cvmx_tim_entry_chunk_t *)cvmx_fpa_alloc(CVMX_FPA_TIMER_POOL);
+        if (new_chunk == NULL)
+        {
+            cvmx_dprintf("cvmx_tim_add_entry: Failed to allocate memory for new chunk.\n");
+            return CVMX_TIM_STATUS_NO_MEMORY;
+        }
+
+        /* Does a chunk currently exist? We have to check num_entries since
+            the hardware doesn't NULL out the chunk pointers on free */
+        if (work_bucket_ptr->num_entries)
+        {
+            /* This chunk must be appended to an existing list by putting
+            ** its address in the last spot of the existing chunk. */
+            work_bucket_ptr->last_chunk->entries[entries_per_chunk] = cvmx_ptr_to_phys(new_chunk);
+            work_bucket_ptr->num_entries++;
+        }
+        else
+        {
+            /* This is the very first chunk. Add it */
+            work_bucket_ptr->first_chunk_addr = cvmx_ptr_to_phys(new_chunk);
+            work_bucket_ptr->num_entries = 1;
+        }
+        work_bucket_ptr->last_chunk = new_chunk;
+        work_bucket_ptr->chunk_remainder = entries_per_chunk - 1;
+        tim_entry_ptr = &(new_chunk->entries[0]);
+        *tim_entry_ptr = cvmx_ptr_to_phys(work_entry);
+    }
+
+    /* If the user supplied a delete info structure then fill it in */
+    if (delete_info)
+    {
+        /* It would be very bad to delete a timer entry after, or during the
+            timer's processing. During the processing could yield unpredicatable
+            results, but after would always be bad. Modifying the entry after
+            processing means we would be changing data in a buffer that has been
+            freed, and possible allocated again. For this reason we store a
+            commit cycle count in the delete structure. If we are after this
+            count we will refuse to delete the timer entry. */
+        delete_info->commit_cycles = cycles + (ticks_from_now - 2) * cvmx_tim.tick_cycles;
+        delete_info->timer_entry_ptr = (uint64_t *)tim_entry_ptr;  /* Cast to non-volatile type */
+    }
+
+    CVMX_SYNCWS; /* Make sure the hardware timer unit can access valid data from L2 */
+
+    return CVMX_TIM_STATUS_SUCCESS;
+}
+#endif
+
+
+/**
+ * Delete a timer entry scheduled using cvmx_tim_add_entry.
+ * Deleting a timer will fail if it has already triggered or
+ * might be in progress. The actual state of the work queue
+ * entry isn't changed. You need to dispose of it properly.
+ *
+ * @param delete_info
+ *               Structure passed to cvmx_tim_add_entry to store the
+ *               information needed to delete a timer entry.
+ * @return CVMX_TIM_STATUS_BUSY if the timer was not deleted, otherwise
+ *         CVMX_TIM_STATUS_SUCCESS.
+ */
+static inline cvmx_tim_status_t cvmx_tim_delete_entry(cvmx_tim_delete_t *delete_info)
+{
+    const uint64_t cycles = cvmx_get_cycle();
+
+    if ((int64_t)(cycles - delete_info->commit_cycles) < 0)
+    {
+        /* Timer is far enough away. Safe to delete */
+        *delete_info->timer_entry_ptr = 0;
+        return CVMX_TIM_STATUS_SUCCESS;
+    }
+    else
+    {
+        /* Timer is passed the commit time. It cannot be stopped */
+        return CVMX_TIM_STATUS_BUSY;
+    }
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif // __CVMX_TIM_H__
diff --git a/cvmx-tra.c b/cvmx-tra.c
new file mode 100644
index 0000000000000..02b1da2817b1c
--- /dev/null
+++ b/cvmx-tra.c
@@ -0,0 +1,322 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the Trace buffer hardware.
+ *
+ * <hr>$Revision: 30644 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-tra.h"
+
+static const char *TYPE_ARRAY[] = {
+    "DWB - Don't write back",
+    "PL2 - Prefetch into L2",
+    "PSL1 - Dcache fill, skip L2",
+    "LDD - Dcache fill",
+    "LDI - Icache/IO fill",
+    "LDT - Icache/IO fill, skip L2",
+    "STF - Store full",
+    "STC - Store conditional",
+    "STP - Store partial",
+    "STT - Store full, skip L2",
+    "IOBLD8 - IOB 8bit load",
+    "IOBLD16 - IOB 16bit load",
+    "IOBLD32 - IOB 32bit load",
+    "IOBLD64 - IOB 64bit load",
+    "IOBST - IOB store",
+    "IOBDMA - Async IOB",
+    "SAA - Store atomic add",
+    "RSVD17",
+    "RSVD18",
+    "RSVD19",
+    "RSVD20",
+    "RSVD21",
+    "RSVD22",
+    "RSVD23",
+    "RSVD24",
+    "RSVD25",
+    "RSVD26",
+    "RSVD27",
+    "RSVD28",
+    "RSVD29",
+    "RSVD30",
+    "RSVD31"
+};
+
+static const char *SOURCE_ARRAY[] = {
+    "PP0",
+    "PP1",
+    "PP2",
+    "PP3",
+    "PP4",
+    "PP5",
+    "PP6",
+    "PP7",
+    "PP8",
+    "PP9",
+    "PP10",
+    "PP11",
+    "PP12",
+    "PP13",
+    "PP14",
+    "PP15",
+    "PIP/IPD",
+    "PKO-R",
+    "FPA/TIM/DFA/PCI/ZIP/POW/PKO-W",
+    "DWB",
+    "RSVD20",
+    "RSVD21",
+    "RSVD22",
+    "RSVD23",
+    "RSVD24",
+    "RSVD25",
+    "RSVD26",
+    "RSVD27",
+    "RSVD28",
+    "RSVD29",
+    "RSVD30",
+    "RSVD31"
+};
+
+static const char *DEST_ARRAY[] = {
+    "CIU/GPIO",
+    "RSVD1",
+    "RSVD2",
+    "PCI/PCIe",
+    "KEY",
+    "FPA",
+    "DFA",
+    "ZIP",
+    "RNG",
+    "IPD",
+    "PKO",
+    "RSVD11",
+    "POW",
+    "RSVD13",
+    "RSVD14",
+    "RSVD15",
+    "RSVD16",
+    "RSVD17",
+    "RSVD18",
+    "RSVD19",
+    "RSVD20",
+    "RSVD21",
+    "RSVD22",
+    "RSVD23",
+    "RSVD24",
+    "RSVD25",
+    "RSVD26",
+    "RSVD27",
+    "RSVD28",
+    "RSVD29",
+    "RSVD30",
+    "RSVD31"
+};
+
+/**
+ * Setup the TRA buffer for use
+ *
+ * @param control TRA control setup
+ * @param filter  Which events to log
+ * @param source_filter
+ *                Source match
+ * @param dest_filter
+ *                Destination match
+ * @param address Address compare
+ * @param address_mask
+ *                Address mask
+ */
+void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
+                    cvmx_tra_filt_sid_t source_filter, cvmx_tra_filt_did_t dest_filter,
+                    uint64_t address, uint64_t address_mask)
+{
+    cvmx_write_csr(CVMX_TRA_CTL,            control.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_CMD,       filter.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_SID,       source_filter.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_DID,       dest_filter.u64);
+    cvmx_write_csr(CVMX_TRA_FILT_ADR_ADR,   address);
+    cvmx_write_csr(CVMX_TRA_FILT_ADR_MSK,   address_mask);
+}
+
+
+/**
+ * Setup a TRA trigger. How the triggers are used should be
+ * setup using cvmx_tra_setup.
+ *
+ * @param trigger Trigger to setup (0 or 1)
+ * @param filter  Which types of events to trigger on
+ * @param source_filter
+ *                Source trigger match
+ * @param dest_filter
+ *                Destination trigger match
+ * @param address Trigger address compare
+ * @param address_mask
+ *                Trigger address mask
+ */
+void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_cmd_t filter,
+                         cvmx_tra_filt_sid_t source_filter, cvmx_tra_trig0_did_t dest_filter,
+                         uint64_t address, uint64_t address_mask)
+{
+    cvmx_write_csr(CVMX_TRA_TRIG0_CMD + trigger * 64,       filter.u64);
+    cvmx_write_csr(CVMX_TRA_TRIG0_SID + trigger * 64,       source_filter.u64);
+    cvmx_write_csr(CVMX_TRA_TRIG0_DID + trigger * 64,       dest_filter.u64);
+    cvmx_write_csr(CVMX_TRA_TRIG0_ADR_ADR + trigger * 64,   address);
+    cvmx_write_csr(CVMX_TRA_TRIG0_ADR_MSK + trigger * 64,   address_mask);
+}
+
+
+/**
+ * Read an entry from the TRA buffer
+ *
+ * @return Value return. High bit will be zero if there wasn't any data
+ */
+cvmx_tra_data_t cvmx_tra_read(void)
+{
+    cvmx_tra_data_t result;
+    result.u64 = cvmx_read_csr(CVMX_TRA_READ_DAT);
+    return result;
+}
+
+
+/**
+ * Decode a TRA entry into human readable output
+ *
+ * @param tra_ctl Trace control setup
+ * @param data    Data to decode
+ */
+void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data)
+{
+    /* The type is a five bit field for some entries and 4 for other. The four
+        bit entries can be mis-typed if the top is set */
+    int type = data.cmn.type;
+    if (type >= 0x1a)
+        type &= 0xf;
+    switch (type)
+    {
+        case CVMX_TRA_DATA_DWB:
+        case CVMX_TRA_DATA_PL2:
+        case CVMX_TRA_DATA_PSL1:
+        case CVMX_TRA_DATA_LDD:
+        case CVMX_TRA_DATA_LDI:
+        case CVMX_TRA_DATA_LDT:
+            cvmx_dprintf("0x%016llx %c%+10d %s %s 0x%016llx\n",
+                   (unsigned long long)data.u64,
+                   (data.cmn.discontinuity) ? 'D' : ' ',
+                   data.cmn.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY[type],
+                   SOURCE_ARRAY[data.cmn.source],
+                   (unsigned long long)data.cmn.address);
+            break;
+        case CVMX_TRA_DATA_STC:
+        case CVMX_TRA_DATA_STF:
+        case CVMX_TRA_DATA_STP:
+        case CVMX_TRA_DATA_STT:
+        case CVMX_TRA_DATA_SAA:
+            cvmx_dprintf("0x%016llx %c%+10d %s %s mask=0x%02x 0x%016llx\n",
+                   (unsigned long long)data.u64,
+                   (data.cmn.discontinuity) ? 'D' : ' ',
+                   data.cmn.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY[type],
+                   SOURCE_ARRAY[data.store.source],
+                   (unsigned int)data.store.mask,
+                   (unsigned long long)data.store.address << 3);
+            break;
+        case CVMX_TRA_DATA_IOBLD8:
+        case CVMX_TRA_DATA_IOBLD16:
+        case CVMX_TRA_DATA_IOBLD32:
+        case CVMX_TRA_DATA_IOBLD64:
+        case CVMX_TRA_DATA_IOBST:
+            cvmx_dprintf("0x%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx\n",
+                   (unsigned long long)data.u64,
+                   (data.cmn.discontinuity) ? 'D' : ' ',
+                   data.cmn.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY[type],
+                   SOURCE_ARRAY[data.iobld.source],
+                   DEST_ARRAY[data.iobld.dest],
+                   (unsigned int)data.iobld.subid,
+                   (unsigned long long)data.iobld.address);
+            break;
+        case CVMX_TRA_DATA_IOBDMA:
+            cvmx_dprintf("0x%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx\n",
+                   (unsigned long long)data.u64,
+                   (data.cmn.discontinuity) ? 'D' : ' ',
+                   data.cmn.timestamp << (tra_ctl.s.time_grn*3),
+                   TYPE_ARRAY[type],
+                   SOURCE_ARRAY[data.iob.source],
+                   DEST_ARRAY[data.iob.dest],
+                   (unsigned int)data.iob.mask,
+                   (unsigned long long)data.iob.address << 3);
+            break;
+        default:
+            cvmx_dprintf("0x%016llx %c%+10d Unknown format\n",
+                   (unsigned long long)data.u64,
+                   (data.cmn.discontinuity) ? 'D' : ' ',
+                   data.cmn.timestamp << (tra_ctl.s.time_grn*3));
+            break;
+    }
+}
+
+
+/**
+ * Display the entire trace buffer. It is advised that you
+ * disable the trace buffer before calling this routine
+ * otherwise it could infinitely loop displaying trace data
+ * that it created.
+ */
+void cvmx_tra_display(void)
+{
+    cvmx_tra_ctl_t tra_ctl;
+    cvmx_tra_data_t data;
+
+    tra_ctl.u64 = cvmx_read_csr(CVMX_TRA_CTL);
+
+    do
+    {
+        data = cvmx_tra_read();
+        if (data.cmn.valid)
+            cvmx_tra_decode_text(tra_ctl, data);
+    } while (data.cmn.valid);
+}
+
diff --git a/cvmx-tra.h b/cvmx-tra.h
new file mode 100644
index 0000000000000..709fde87765e3
--- /dev/null
+++ b/cvmx-tra.h
@@ -0,0 +1,411 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the Trace buffer hardware.
+ *
+ * WRITING THE TRACE BUFFER
+ *
+ * When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once
+ * (no wrapping).  Additionally and independent of wrapping, tracing can be temporarily enabled and disabled
+ * by the tracing triggers.  All XMC commands can be traced except for IDLE and IOBRSP.  The subset of XMC
+ * commands that are traced is determined by the filter and the two triggers, each of which is comprised of
+ * masks for command, sid, did, and address).  If triggers are disabled, then only those commands matching
+ * the filter are traced.  If triggers are enabled, then only those commands matching the filter, the start
+ * trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger.
+ *
+ * For a given command, its XMC data is written immediately to the buffer.  If the command has XMD data,
+ * then that data comes in-order at some later time.  The XMD data is accumulated across all valid
+ * XMD cycles and written to the buffer or to a shallow fifo.  Data from the fifo is written to the buffer
+ * as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC
+ * data).  If the fifo overflows, it simply overwrites itself and the previous XMD data is lost.
+ *
+ *
+ * READING THE TRACE BUFFER
+ *
+ * Each entry of the trace buffer is read by a CSR read command.  The trace buffer services each read in order,
+ * as soon as it has access to the (single-ported) trace buffer.
+ *
+ *
+ * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS
+ *
+ * The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow
+ * conditions.  Each time a new trace is enabled, both pointers are reset to entry 0.  Normally, each write
+ * (traced event) increments the write pointer and each read increments the read pointer.  During the overflow
+ * condition, writing (tracing) is disabled.  Tracing will continue as soon as the overflow condition is
+ * resolved.  The first entry that is written immediately following the overflow condition may be marked to
+ * indicate that a tracing discontinuity has occurred before this entry.  During the underflow condition,
+ * reading does not increment the read pointer and the read data is marked to indicate that no read data is
+ * available.
+ *
+ * The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4).
+ * "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the
+ * absolute distance between the write pointer and entry 0).  When enabled, the full threshold event occurs
+ * every time the desired level of "fullness" is achieved.
+ *
+ *
+ * Trace buffer entry format
+ * @verbatim
+ *       6                   5                   4                   3                   2                   1                   0
+ * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id  |   0   | DWB   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id  |   0   | PL2   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id  |   0   | PSL1  | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id  |   0   | LDD   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id  |   0   | LDI   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id  |   0   | LDT   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          | * or 16B mask | src id  |   0   | STC   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          | * or 16B mask | src id  |   0   | STF   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          | * or 16B mask | src id  |   0   | STP   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          | * or 16B mask | src id  |   0   | STT   | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:0]                                |    0    | src id| dest id |IOBLD8 | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:1]                              |     0     | src id| dest id |IOBLD16| diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:2]                            |      0      | src id| dest id |IOBLD32| diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          |       0       | src id| dest id |IOBLD64| diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                          address[35:3]                          | * or 16B mask | src id| dest id |IOBST  | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |sta|                     * or address[35:3]                          | * or length   | src id| dest id |IOBDMA | diff timestamp|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ * notes:
+ * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time.  Note that the
+ * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'.
+ * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows:
+ * 0x0-0x1=not valid
+ * 0x2=valid, no discontinuity
+ * 0x3=valid,    discontinuity
+ * - commands are encoded as follows:
+ * 0x0=DWB
+ * 0x1=PL2
+ * 0x2=PSL1
+ * 0x3=LDD
+ * 0x4=LDI
+ * 0x5=LDT
+ * 0x6=STC
+ * 0x7=STF
+ * 0x8=STP
+ * 0x9=STT
+ * 0xa=IOBLD8
+ * 0xb=IOBLD16
+ * 0xc=IOBLD32
+ * 0xd=IOBLD64
+ * 0xe=IOBST
+ * 0xf=IOBDMA
+ * - For non IOB* commands
+ * - source id is encoded as follows:
+ * 0x00-0x0f=PP[n]
+ * 0x10=IOB(Packet)
+ * 0x11=IOB(PKO)
+ * 0x12=IOB(ReqLoad, ReqStore)
+ * 0x13=IOB(DWB)
+ * 0x14-0x1e=illegal
+ * 0x1f=IOB(generic)
+ * - dest   id is unused (can only be L2c)
+ * - For IOB* commands
+ * - source id is encoded as follows:
+ * 0x00-0x0f = PP[n]
+ * - dest   id is encoded as follows:
+ * 0x00-0x0f=PP[n]
+ * 0x10=IOB(Packet)
+ * 0x11=IOB(PKO)
+ * 0x12=IOB(ReqLoad, ReqStore)
+ * 0x13=IOB(DWB)
+ * 0x14-0x1e=illegal
+ * 0x1f=IOB(generic)
+ *
+ * Source of data for each command
+ * command source id    dest id      address                 length/mask
+ * -------+------------+------------+-----------------------+----------------------------------------------
+ * LDI     xmc_sid[8:3] x            xmc_adr[35:3]           x
+ * LDT     xmc_sid[8:3] x            xmc_adr[35:3]           x
+ * STF     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
+ * STC     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
+ * STP     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
+ * STT     xmc_sid[8:3] x            xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
+ * DWB     xmc_sid[8:3] x            xmc_adr[35:3]           x
+ * PL2     xmc_sid[8:3] x            xmc_adr[35:3]           x
+ * PSL1    xmc_sid[8:3] x            xmc_adr[35:3]           x
+ * IOBLD8  xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:0]           x
+ * IOBLD16 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:1]           x
+ * IOBLD32 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:2]           x
+ * IOBLD64 xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:3]           x
+ * IOBST   xmc_sid[8:3] xmc_did[8:3] xmc_adr[35:3]           16B mask(xmd_[wrval,eow,adr[6:4],wrmsk[15:0]])
+ * IOBDMA  xmc_sid[8:3] xmc_did[8:3] (xmd_[wrval,eow,dat[]]) length(xmd_[wrval,eow,dat[]])
+ * IOBRSP  not traced, but monitored to keep XMC and XMD data in sync.
+ * @endverbatim
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_TRA_H__
+#define __CVMX_TRA_H__
+
+#include "cvmx.h"
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Enumeration of the data types stored in cvmx_tra_data_t
+ */
+typedef enum
+{
+    CVMX_TRA_DATA_DWB       = 0x0,
+    CVMX_TRA_DATA_PL2       = 0x1,
+    CVMX_TRA_DATA_PSL1      = 0x2,
+    CVMX_TRA_DATA_LDD       = 0x3,
+    CVMX_TRA_DATA_LDI       = 0x4,
+    CVMX_TRA_DATA_LDT       = 0x5,
+    CVMX_TRA_DATA_STC       = 0x6,
+    CVMX_TRA_DATA_STF       = 0x7,
+    CVMX_TRA_DATA_STP       = 0x8,
+    CVMX_TRA_DATA_STT       = 0x9,
+    CVMX_TRA_DATA_IOBLD8    = 0xa,
+    CVMX_TRA_DATA_IOBLD16   = 0xb,
+    CVMX_TRA_DATA_IOBLD32   = 0xc,
+    CVMX_TRA_DATA_IOBLD64   = 0xd,
+    CVMX_TRA_DATA_IOBST     = 0xe,
+    CVMX_TRA_DATA_IOBDMA    = 0xf,
+    CVMX_TRA_DATA_SAA       = 0x10,
+} cvmx_tra_data_type_t;
+
+/**
+ * TRA data format definition. Use the type field to
+ * determine which union element to use.
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    address     : 36;
+        uint64_t    reserved    : 5;
+        uint64_t    source      : 5;
+        uint64_t    reserved2   : 3;
+        cvmx_tra_data_type_t type:5;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        cvmx_tra_data_type_t type:5;
+        uint64_t    reserved2   : 3;
+        uint64_t    source      : 5;
+        uint64_t    reserved    : 5;
+        uint64_t    address     : 36;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+#endif
+    } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    address     : 33;
+        uint64_t    mask        : 8;
+        uint64_t    source      : 5;
+        uint64_t    reserved2   : 3;
+        cvmx_tra_data_type_t type:5;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        cvmx_tra_data_type_t type:5;
+        uint64_t    reserved2   : 3;
+        uint64_t    source      : 5;
+        uint64_t    mask        : 8;
+        uint64_t    address     : 33;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+#endif
+    } store; /**< STC, STF, STP, STT */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    address     : 36;
+        uint64_t    reserved    : 2;
+        uint64_t    subid       : 3;
+        uint64_t    source      : 4;
+        uint64_t    dest        : 5;
+        uint64_t    type        : 4;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        uint64_t    type        : 4;
+        uint64_t    dest        : 5;
+        uint64_t    source      : 4;
+        uint64_t    subid       : 3;
+        uint64_t    reserved    : 2;
+        uint64_t    address     : 36;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+#endif
+    } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */
+    struct
+    {
+#if __BYTE_ORDER == __BIG_ENDIAN
+        uint64_t    valid       : 1;
+        uint64_t    discontinuity:1;
+        uint64_t    address     : 33;
+        uint64_t    mask        : 8;
+        uint64_t    source      : 4;
+        uint64_t    dest        : 5;
+        uint64_t    type        : 4;
+        uint64_t    timestamp   : 8;
+#else
+        uint64_t    timestamp   : 8;
+        uint64_t    type        : 4;
+        uint64_t    dest        : 5;
+        uint64_t    source      : 4;
+        uint64_t    mask        : 8;
+        uint64_t    address     : 33;
+        uint64_t    discontinuity:1;
+        uint64_t    valid       : 1;
+#endif
+    } iob; /**< for IOBDMA */
+} cvmx_tra_data_t;
+
+
+/**
+ * Setup the TRA buffer for use
+ *
+ * @param control TRA control setup
+ * @param filter  Which events to log
+ * @param source_filter
+ *                Source match
+ * @param dest_filter
+ *                Destination match
+ * @param address Address compare
+ * @param address_mask
+ *                Address mask
+ */
+extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_cmd_t filter,
+                           cvmx_tra_filt_sid_t source_filter, cvmx_tra_filt_did_t dest_filter,
+                           uint64_t address, uint64_t address_mask);
+
+/**
+ * Setup a TRA trigger. How the triggers are used should be
+ * setup using cvmx_tra_setup.
+ *
+ * @param trigger Trigger to setup (0 or 1)
+ * @param filter  Which types of events to trigger on
+ * @param source_filter
+ *                Source trigger match
+ * @param dest_filter
+ *                Destination trigger match
+ * @param address Trigger address compare
+ * @param address_mask
+ *                Trigger address mask
+ */
+extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_cmd_t filter,
+                                cvmx_tra_filt_sid_t source_filter, cvmx_tra_trig0_did_t dest_filter,
+                                uint64_t address, uint64_t address_mask);
+
+/**
+ * Read an entry from the TRA buffer
+ *
+ * @return Value return. High bit will be zero if there wasn't any data
+ */
+extern cvmx_tra_data_t cvmx_tra_read(void);
+
+/**
+ * Decode a TRA entry into human readable output
+ *
+ * @param tra_ctl Trace control setup
+ * @param data    Data to decode
+ */
+extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data);
+
+/**
+ * Display the entire trace buffer. It is advised that you
+ * disable the trace buffer before calling this routine
+ * otherwise it could infinitely loop displaying trace data
+ * that it created.
+ */
+extern void cvmx_tra_display(void);
+
+/**
+ * Enable or disable the TRA hardware
+ *
+ * @param enable 1=enable, 0=disable
+ */
+static inline void cvmx_tra_enable(int enable)
+{
+    cvmx_tra_ctl_t control;
+    control.u64 = cvmx_read_csr(CVMX_TRA_CTL);
+    control.s.ena = enable;
+    cvmx_write_csr(CVMX_TRA_CTL, control.u64);
+    cvmx_read_csr(CVMX_TRA_CTL);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cvmx-twsi-raw.c b/cvmx-twsi-raw.c
new file mode 100644
index 0000000000000..0b82325af4c00
--- /dev/null
+++ b/cvmx-twsi-raw.c
@@ -0,0 +1,464 @@
+/***********************license start***************
+ * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
+ *
+ * This software file (the "File") is owned and distributed by Cavium
+ * Networks ("Cavium") under the following dual licensing option: The dual
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+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+
+/*
+ * This code is an example of using twsi core in raw mode, bypasing High 
+ * Level Controller (HLC). It is recommended to use HLC if only possible as 
+ * it is more efficient and robust mechanism. 
+ * The example code shows use of twsi for generating long (more that 8 bytes HLC limit) 
+ * read - write transactions using 7-bit addressing. Different types of 
+ * transactions can be generated if needed. Make sure that commands written to twsi core 
+ * follow core state transitions outlinged in OCTEON documentation. The core state is 
+ * reported in stat register after the command colpletion. In each state core will accept
+ *  only the allowed commands.
+ */
+ 
+#include <stdio.h>
+#include <cvmx.h>
+#include <cvmx-csr-typedefs.h>
+#include "cvmx-twsi-raw.h"
+
+/*
+ * uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
+ * twsi core register read
+ * twsi_id - twsi core index
+ * reg 0 - 8-bit register
+ * returns 8-bit register contetn
+ */
+uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
+{
+    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+
+    sw_twsi_val.u64 = 0;
+    sw_twsi_val.s.v = 1;
+    sw_twsi_val.s.op = 6;
+    sw_twsi_val.s.eop_ia = reg;
+    sw_twsi_val.s.r = 1;
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+        ;
+    return sw_twsi_val.s.d ;
+}
+
+/*
+ * uint8_t cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
+ *
+ * twsi core register write
+ * twsi_id - twsi core index
+ * reg 0 - 8-bit register
+ * data - data to write
+ * returns 0;
+ */
+
+int cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
+{
+    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+
+    sw_twsi_val.u64 = 0;
+    sw_twsi_val.s.v = 1;
+    sw_twsi_val.s.op = 6;
+    sw_twsi_val.s.eop_ia = reg;
+    sw_twsi_val.s.d = data;
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+        ;
+
+    return 0;
+}
+
+/*
+ * cvmx_twsi_wait_iflg(int twsi_id)
+ * cvmx_twsi_wait_stop(int twsi_id)
+ *
+ * Helper functions. 
+ * Busy wait for interrupt flag or stop bit on control register. This implementation is for OS-less 
+ * application. With OS services available it could be implemented with semaphore
+ * block and interrupt wake up. 
+ * TWSI_WAIT for loop must be defined large enough to allow on-wire transaction to finish - that is 
+ * about 10 twsi clocks
+ */
+#define TWSI_WAIT 10000000
+static inline int cvmx_twsi_wait_iflg(int twsi_id)
+{
+    octeon_twsi_ctl_t ctl_reg;
+    int wait = TWSI_WAIT;
+    do{
+        ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
+    } while((ctl_reg.s.iflg ==0) && (wait-- >0));
+    if(wait == 0) return -1;
+    return 0;
+}
+
+static inline int cvmx_twsi_wait_stop(int twsi_id)
+{
+    octeon_twsi_ctl_t ctl_reg;
+    int wait = TWSI_WAIT;
+    do{
+        ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
+    } while((ctl_reg.s.stp ==1) && (wait-- >0));
+    if(wait == 0) return -1;
+    return 0;
+}
+
+
+/*
+ * uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack) 
+ * uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
+ *
+ * helper functions - read or write byte to data reg and reads the TWSI core status
+ */
+static uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
+{
+    octeon_twsi_ctl_t ctl_reg;
+    octeon_twsi_data_t data;
+    octeon_twsi_stat_t stat;
+
+    /* clear interrupt flag, set aak for requested ACK signal level */
+    ctl_reg.u8 =0;
+    ctl_reg.s.aak = (ack==0) ?0:1;
+    ctl_reg.s.enab =1;
+    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
+
+    /* wait for  twsi_ctl[iflg] to be set */
+    if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
+
+    /* read the byte */
+    data.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_DATA_REG);
+    *byte = data.s.data;
+error:
+    /* read the status */
+    stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
+    return stat.s.stat;
+}
+
+static uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
+{
+    octeon_twsi_ctl_t ctl_reg;
+    octeon_twsi_data_t data;
+    octeon_twsi_stat_t stat;
+
+    /* tx data byte - write to twsi_data reg, then clear twsi_ctl[iflg] */
+    data.s.data = byte;
+    cvmx_twsix_write_ctr(twsi_id, TWSI_DATA_REG, data.u8);
+
+    ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
+    ctl_reg.s.iflg =0;
+    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
+
+    /* wait for  twsi_ctl[iflg] to be set */
+    if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
+error:
+     /* read the status */
+     stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
+     return stat.s.stat;
+}
+
+/*
+ * int octeon_i2c_xfer_msg_raw(struct i2c_msg *msg)
+ *
+ * Send (read or write) a message with 7-bit address device over direct control of 
+ * TWSI core, bypassind HLC. Will try to finish the transaction on failure, so core state
+ * expected to be idle with HLC enabled on exit.
+ *
+ * dev - TWSI controller index (0 for cores with single controler)
+ * msg - message to transfer
+ * returns 0 on success, TWSI core state on error. Will try to finish the transaction on failure, so core state expected to be idle
+ */
+int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg)
+{
+    int i =0;
+    octeon_twsi_ctl_t ctl_reg;
+    octeon_twsi_addr_t addr;
+    octeon_twsi_stat_t stat;
+    int is_read = msg->flags & I2C_M_RD;
+    int ret =0;
+
+    /* check the core state, quit if not idle */
+    stat.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
+    if(stat.s.stat != TWSI_IDLE) {
+       msg->len =0; return stat.s.stat;
+    }
+
+    /* first send start - set twsi_ctl[sta] to 1 */
+    ctl_reg.u8 =0;
+    ctl_reg.s.enab =1;
+    ctl_reg.s.sta =1;
+    ctl_reg.s.iflg =0;
+    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
+    /* wait for  twsi_ctl[iflg] to be set */
+    if(cvmx_twsi_wait_iflg(twsi_id)) goto stop;
+
+    /* Write 7-bit addr to twsi_data; set read bit */
+    addr.s.slave_addr7 = msg->addr;
+    if(is_read) addr.s.r =1;
+    else addr.s.r =0;
+    stat.s.stat =octeon_twsi_write_byte(twsi_id, addr.u8);
+
+    /* Data read loop */
+    if( is_read) {
+    /* any status but ACK_RXED means failure - we try to send stop and go idle */
+      if(!(stat.s.stat == TWSI_ADDR_R_TX_ACK_RXED)) {
+      ret = stat.s.stat;
+      msg->len =0;
+      goto stop;
+     }
+     /* We read data from the buffer and send ACK back.
+       The last byte we read with negative ACK */
+      for(i =0; i<msg->len-1; i++)
+      {
+        stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 1);
+        if(stat.s.stat != TWSI_DATA_RX_ACK_TXED)
+           goto stop;
+      }
+      /* last read we send negACK */
+      stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 0);
+        if(stat.s.stat != TWSI_DATA_RX_NACK_TXED)
+             return stat.s.stat;
+    } /* read loop */
+
+    /* Data write loop */
+    else {
+    /* any status but ACK_RXED means failure - we try to send stop and go idle */
+      if(stat.s.stat != TWSI_ADDR_W_TX_ACK_RXED) {
+          ret = stat.s.stat;
+          msg->len =0;
+          goto stop;
+      }
+      /* We write data to the buffer and check for ACK. */
+      for(i =0; i<msg->len; i++)
+      {
+          stat.s.stat =octeon_twsi_write_byte(twsi_id, msg->buf[i]);
+          if(stat.s.stat == TWSI_DATA_TX_NACK_RXED) {
+              /* Negative ACK means slave can not RX more */
+              msg->len =i-1;
+              goto stop;
+          }
+          else if(stat.s.stat != TWSI_DATA_TX_ACK_RXED) {
+              /* lost arbitration? try to send stop and go idle. This current byte likely was not written */
+              msg->len = (i-2) >0? (i-2):0;
+              goto stop;
+          }
+      }
+    }  /* write loop */
+
+stop:
+    ctl_reg.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
+    ctl_reg.s.stp =1;
+    ctl_reg.s.iflg =0;
+    cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
+    /* wait for  twsi_ctl[stp] to clear */
+    cvmx_twsi_wait_stop(twsi_id);
+#if 0
+    stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
+    if(stat.s.stat == TWSI_IDLE)
+#endif
+    /* Leave TWSI core with HLC eabled */
+    {
+       ctl_reg.u8 =0;
+       ctl_reg.s.ce =1;
+       ctl_reg.s.enab =1;
+       ctl_reg.s.aak =1;
+       cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
+    }
+
+    return ret;
+}
+
diff --git a/cvmx-twsi-raw.h b/cvmx-twsi-raw.h
new file mode 100644
index 0000000000000..17fe39d3c595b
--- /dev/null
+++ b/cvmx-twsi-raw.h
@@ -0,0 +1,331 @@
+/***********************license start***************
+ * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
+ *
+ * This software file (the "File") is owned and distributed by Cavium
+ * Networks ("Cavium") under the following dual licensing option: The dual
+ * licensing option gives you, the licensee, the choice between the following
+ * alternative licensing terms.  Once you have made an election to use the
+ * File under one of the following alternative licensing terms (license
+ * types) you are bound by the respective terms and you may distribute the
+ * file (or any derivative thereof), to the extent allowed by the respective
+ * licensing term, only if you (i) delete this introductory statement
+ * regarding the dual licensing option from the file you will distribute,
+ * (ii) delete the licensing term that you have elected NOT to use from the
+ * file you will distribute and (iii) follow the respective licensing term
+ * that you have elected to use with respect to the correct attribution or
+ * licensing term that you have to include with your distribution.
+ *
+ * ***
+ * OCTEON SDK License Type 2:
+ *
+ * IMPORTANT: Read this Agreement carefully before clicking on the "I accept"
+ * button to download the Software and/or before using the Software.  This
+ * License Agreement (the "Agreement") is a legal agreement between you,
+ * either an individual or a single legal entity ("You" or "you"), and Cavium
+ * Networks ("Cavium").  This Agreement governs your use of the Cavium
+ * software that can be downloaded after accepting this Agreement and/or that
+ * is accompanied by this Agreement (the "Software").  You must accept the
+ * terms of this Agreement before downloading and/or using the Software.  By
+ * clicking on the "I accept" button to download and/or by using the
+ * Software, you are indicating that you have read and understood, and assent
+ * to be bound by, the terms of this Agreement.  If you do not agree to the
+ * terms of the Agreement, you are not granted any rights whatsoever in the
+ * Software.  If you are not willing to be bound by these terms and
+ * conditions, you should not use or cease all use of the Software.  This
+ * Software is the property of Cavium Networks and constitutes the
+ * proprietary information of Cavium Networks.  You agree to take reasonable
+ * steps to prevent the disclosure, unauthorized use or unauthorized
+ * distribution of the Software to any third party.
+ *
+ * License Grant.  Subject to the terms and conditions of this Agreement,
+ * Cavium grants you a nonexclusive, non-transferable, worldwide, fully-paid
+ * and royalty-free license to
+ *
+ * (a) install, reproduce, and execute the executable version of the Software
+ * solely for your internal use and only (a) on hardware manufactured by
+ * Cavium, or (b) software of Cavium that simulates Cavium hardware;
+*
+ * (b) create derivative works of any portions of the Software provided to
+ * you by Cavium in source code form, which portions enable features of the
+ * Cavium hardware products you or your licensees are entitled to use,
+ * provided that any such derivative works must be used only (a) on hardware
+ * manufactured by Cavium, or (b) software of Cavium that simulates Cavium
+ * hardware; and
+ *
+ * (c) distribute derivative works you created in accordance with clause (b)
+ * above, only in executable form and only if such distribution (i)
+ * reproduces the copyright notice that can be found at the very end of this
+ * Agreement and (ii) is pursuant to a binding license agreement that
+ * contains terms no less restrictive and no less protective of Cavium than
+ * this Agreement.  You will immediately notify Cavium if you become aware of
+ * any breach of any such license agreement.
+ *
+ * Restrictions.  The rights granted to you in this Agreement are subject to
+ * the following restrictions: Except as expressly set forth in this
+ * Agreement (a) you will not license, sell, rent, lease, transfer, assign,
+ * display, host, outsource, disclose or otherwise commercially exploit or
+ * make the Software, or any derivatives you create under this Agreement,
+ * available to any third party; (b) you will not modify or create derivative
+ * works of any part of the Software; (c) you will not access or use the
+ * Software in order to create similar or competitive products, components,
+ * or services; and (d), no part of the Software may be copied (except for
+ * the making of a single archival copy), reproduced, distributed,
+ * republished, downloaded, displayed, posted or transmitted in any form or
+ * by any means.
+ *
+ * Ownership.  You acknowledge and agree that, subject to the license grant
+ * contained in this Agreement and as between you and Cavium (a) Cavium owns
+ * all copies of and intellectual property rights to the Software, however
+ * made, and retains all rights in and to the Software, including all
+ * intellectual property rights therein, and (b) you own all the derivate
+ * works of the Software created by you under this Agreement, subject to
+ * Cavium's rights in the Software.  There are no implied licenses under this
+ * Agreement, and any rights not expressly granted to your hereunder are
+ * reserved by Cavium.  You will not, at any time, contest anywhere in the
+ * world Cavium's ownership of the intellectual property rights in and to the
+ * Software.
+ *
+ * Disclaimer of Warranties.  The Software is provided to you free of charge,
+ * and on an "As-Is" basis.  Cavium provides no technical support, warranties
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+* express, implied or statutory warranties relating to the Software,
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+ * Software, all such warranties are limited in duration to thirty (30) days
+ * from the date of download or first use, whichever comes first.
+ *
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+ * responsible or liable with respect to any subject matter of this Agreement
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+ * cost of procurement of substitute goods, services or technology, or (b)
+ * for any indirect, incidental or consequential damages including, but not
+ * limited to loss of revenues and loss of profits.  Cavium's aggregate
+ * cumulative liability hereunder shall not exceed the greater of Fifty U.S.
+ * Dollars (U.S.$50.00) or the amount paid by you for the Software that
+ * caused the damage.  Certain states and/or jurisdictions do not allow the
+ * exclusion of implied warranties or limitation of liability for incidental
+ * or consequential damages, so the exclusions set forth above may not apply
+ * to you.
+ *
+ * Basis of Bargain.  The warranty disclaimer and limitation of liability set
+ * forth above are fundamental elements of the basis of the agreement between
+ * Cavium and you.  Cavium would not provide the Software without such
+ * limitations.  The warranty disclaimer and limitation of liability inure to
+ * the benefit of Cavium and Cavium's suppliers.
+ *
+ * Term and Termination.  This Agreement and the licenses granted hereunder
+ * are effective on the date you accept the terms of this Agreement, download
+ * the Software, or use the Software, whichever comes first, and shall
+ * continue unless this Agreement is terminated pursuant to this section.
+ * This Agreement immediately terminates in the event that you materially
+ * breach any of the terms hereof.  You may terminate this Agreement at any
+ * time, with or without cause, by destroying any copies of the Software in
+ * your possession.  Upon termination, the license granted hereunder shall
+ * terminate but the Sections titled "Restrictions", "Ownership", "Disclaimer
+ * of Warranties", "Limitation of Liability", "Basis of Bargain", "Term and
+ * Termination", "Export", and "Miscellaneous" will remain in effect.
+ *
+ * Export.  The Software and related technology are subject to U.S.  export
+ * control laws and may be subject to export or import regulations in other
+ * countries.  You agree to strictly comply with all such laws and
+ * regulations and acknowledges that you have the responsibility to obtain
+ * authorization to export, re-export, or import the Software and related
+ * technology, as may be required.  You will indemnify and hold Cavium
+ * harmless from any and all claims, losses, liabilities, damages, fines,
+ * penalties, costs and expenses (including attorney's fees) arising from or
+ * relating to any breach by you of your obligations under this section.
+ * Your obligations under this section shall survive the expiration or
+ * termination of this Agreement.
+ *
+ * Miscellaneous.  Neither the rights nor the obligations arising under this
+ * Agreement are assignable by you, and any such attempted assignment or
+ * transfer shall be void and without effect.  This Agreement shall be
+ * governed by and construed in accordance with the laws of the State of
+ * California without regard to any conflicts of laws provisions that would
+ * require application of the laws of another jurisdiction.  Any action under
+ * or relating to this Agreement shall be brought in the state and federal
+ * courts located in California, with venue in the courts located in Santa
+ * Clara County and each party hereby submits to the personal jurisdiction of
+ * such courts; provided, however, that nothing herein will operate to
+ * prohibit or restrict Cavium from filing for and obtaining injunctive
+ * relief from any court of competent jurisdiction.  The United Nations
+ * Convention on Contracts for the International Sale of Goods shall not
+ * apply to this Agreement.  In the event that any provision of this
+ * Agreement is found to be contrary to law, then such provision shall be
+ * construed as nearly as possible to reflect the intention of the parties,
+ * with the other provisions remaining in full force and effect.  Any notice
+ * to you may be provided by email.  This Agreement constitutes the entire
+ * agreement between the parties and supersedes all prior or contemporaneous,
+ * agreements, understandings and communications between the parties, whether
+ * written or oral, pertaining to the subject matter hereof.  Any
+ * modifications of this Agreement must be in writing and agreed to by both
+ * parties.
+ *
+ * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
+ *
+ * ***
+ *
+ * OCTEON SDK License Type 4:
+ *
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+
+#ifndef __CVMX_TWSI_RAW_H__
+#define __CVMX_TWSI_RAW_H__
+
+/* Addresses for twsi 8-bit registers. Gets written to EOP_IA field of MIO_TWS_SW_TWSI reg
+*  when OP = 6 and SLONLY =0 */
+#define TWSI_SLAVE_ADD_REG      0
+#define TWSI_DATA_REG           1
+#define TWSI_CTL_REG            2
+#define TWSI_STAT_REG	        3 /* read only */
+#define TWSI_CLKCTL_REG 	3 /* write only */
+#define TWSI_SLAVE_EXTADD_REG   4       
+#define TWSI_RST_REG            7
+
+/* twsi core slave address reg */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t slave_addr7     : 7;
+        uint8_t gce    : 1;
+
+    }s;
+} octeon_twsi_slave_add_t;
+
+/* twsi core 10-bit slave address reg */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t slave_addr8     : 8;
+    }s;
+} octeon_twsi_slave_extadd_t;
+
+/* twsi core control register */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t ce     : 1;  /* enable HLC*/
+        uint8_t enab   : 1;  /* bus enable */
+        uint8_t sta    : 1;  /* start request */
+        uint8_t stp    : 1;  /* stop request */
+        uint8_t iflg   : 1;  /* interrupt flag - request completed (1) start new (0) */
+        uint8_t aak    : 1;  /* assert ack (1) -neg ack at end of Rx sequence */ 
+        uint8_t rsv    : 2;  /* not used */
+    }s;
+} octeon_twsi_ctl_t;
+
+/* clock dividers register */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t m_divider   : 4;
+        uint8_t n_divider   : 3;
+    }s;
+} octeon_twsi_clkctl_t;
+
+/* address of the remote slave + r/w bit */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t slave_addr7     : 7; 
+	uint8_t r		: 1; /* read (1) write (0) bit */
+    }s;
+} octeon_twsi_addr_t;
+
+/* core state reg */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t stat    : 8;
+    }s;
+} octeon_twsi_stat_t;
+
+ /* data byte reg */
+typedef union{
+    uint8_t u8;
+    struct{
+        uint8_t data    : 8;
+    }s;
+} octeon_twsi_data_t;
+
+/* twsi core states as reported in twsi core stat register */
+#define TWSI_BUS_ERROR 			0x00
+#define TWSI_START_TXED 		0x08
+#define TWSI_ADDR_W_TX_ACK_RXED 	0x18
+#define TWSI_ADDR_W_TX_NACK_RXED 	0x20
+
+#define TWSI_DATA_TX_ACK_RXED 		0x28
+#define TWSI_DATA_TX_NACK_RXED 	0x30
+#define TWSI_ARB_LOST			0x38
+#define TWSI_ADDR_R_TX_ACK_RXED		0x40
+
+#define TWSI_ADDR_R_TX_NACK_RXED	0x48
+#define TWSI_DATA_RX_ACK_TXED		0x50
+#define TWSI_DATA_RX_NACK_TXED		0x58
+#define TWSI_SLAVE_ADDR_RX_ACK_TXED	0x60
+
+#define TWSI_ARB_LOST_SLAVE_ADDR_RX	0x68
+#define TWSI_GEN_ADDR_RXED_ACK_TXED	0x70
+#define TWSI_ARB_LOST_GEN_ADDR_RXED	0x78
+#define TWSI_SLAVE_DATA_RX_ACK_TXED	0x80
+
+#define TWSI_SLAVE_DATA_RX_NACK_TXED	0x88
+#define TWSI_GEN_DATA_RX_ACK_TXED	0x90
+#define TWSI_GEN_DATA_RX_NACK_TXED	0x98
+#define TWSI_SLAVE_STOP_OR_START_RXED	0xa0
+
+#define TWSI_SLAVE_ADDR_R_RX_ACK_TXED	0xa8
+#define TWSI_ARB_LOST_SLAVE_ADDR_R_RX_ACK_TXED 0xb0
+#define TWSI_SLAVE_DATA_TX_ACK_RXED	0xb8
+#define TWSI_SLAVE_DATA_TX_NACK_RXED	0xc0
+
+#define TWSI_SLAVE_LAST_DATA_TX_ACK_RXED 0xc8
+#define TWSI_SECOND_ADDR_W_TX_ACK_RXED	0xd0
+#define TWSI_SECOND_ADDR_W_TX_NACK_RXED	0xd8
+#define TWSI_IDLE			0xf8
+
+#ifndef LINUX
+/* msg definition similar to Linux */
+struct i2c_msg {
+        uint16_t addr;     /* slave address                        */
+        uint16_t flags;
+        uint16_t len;              /* msg length                           */
+        uint8_t *buf;              /* pointer to msg data                  */
+};
+#define I2C_M_TEN       0x10    /* we have a ten bit chip address       */
+#define I2C_M_RD        0x01
+#endif
+
+int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg);
+
+#endif
diff --git a/cvmx-twsi.c b/cvmx-twsi.c
new file mode 100644
index 0000000000000..06daabb59647f
--- /dev/null
+++ b/cvmx-twsi.c
@@ -0,0 +1,285 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the TWSI / I2C bus
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#include "cvmx.h"
+#include "cvmx-twsi.h"
+
+
+
+
+
+/**
+ * Do a twsi read from a 7 bit device address using an (optional) internal address.
+ * Up to 8 bytes can be read at a time.
+ * 
+ * @param twsi_id   which Octeon TWSI bus to use
+ * @param dev_addr  Device address (7 bit)
+ * @param internal_addr
+ *                  Internal address.  Can be 0, 1 or 2 bytes in width
+ * @param num_bytes Number of data bytes to read
+ * @param ia_width_bytes
+ *                  Internal address size in bytes (0, 1, or 2)
+ * @param data      Pointer argument where the read data is returned.
+ * 
+ * @return read data returned in 'data' argument
+ *         Number of bytes read on success
+ *         -1 on failure
+ */
+int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data)
+{
+    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+    cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+
+    if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
+        return -1;
+
+    twsi_ext.u64 = 0;
+    sw_twsi_val.u64 = 0;
+    sw_twsi_val.s.v = 1;
+    sw_twsi_val.s.r = 1;
+    sw_twsi_val.s.sovr = 1;
+    sw_twsi_val.s.size = num_bytes - 1;
+    sw_twsi_val.s.a = dev_addr;
+
+    if (ia_width_bytes > 0)
+    {
+        sw_twsi_val.s.op = 1;
+        sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
+        sw_twsi_val.s.eop_ia = internal_addr & 0x7;
+    } 
+    if (ia_width_bytes == 2)
+    {
+        sw_twsi_val.s.eia = 1;
+        twsi_ext.s.ia = internal_addr >> 8;
+        cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+    }
+
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+        ;
+    if (!sw_twsi_val.s.r)
+        return -1;
+
+    *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
+    if (num_bytes > 4)
+    {
+        twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
+        *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
+
+    }
+    return num_bytes;
+}
+
+
+
+
+/**
+ * Read from a TWSI device (7 bit device address only) without generating any
+ * internal addresses.
+ * Read from 1-8 bytes and returns them in the data pointer.
+ * 
+ * @param twsi_id   TWSI interface on Octeon to use
+ * @param dev_addr  TWSI device address (7 bit only)
+ * @param num_bytes number of bytes to read
+ * @param data      Pointer to data read from TWSI device
+ * 
+ * @return Number of bytes read on success
+ *         -1 on error
+ */
+int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data)
+{
+    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+    cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+
+    if (num_bytes > 8 || num_bytes < 1)
+        return -1;
+
+    sw_twsi_val.u64 = 0;
+    sw_twsi_val.s.v = 1;
+    sw_twsi_val.s.r = 1;
+    sw_twsi_val.s.a = dev_addr;
+    sw_twsi_val.s.sovr = 1;
+    sw_twsi_val.s.size = num_bytes - 1;
+
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+        ;
+    if (!sw_twsi_val.s.r)
+        return -1;
+
+    *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
+    if (num_bytes > 4)
+    {
+        twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
+        *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
+
+    }
+    return num_bytes;
+}
+
+
+/**
+ * Perform a twsi write operation to a 7 bit device address.
+ * 
+ * Note that many eeprom devices have page restrictions regarding address boundaries
+ * that can be crossed in one write operation.  This is device dependent, and this routine
+ * does nothing in this regard.
+ * This command does not generate any internal addressess.
+ * 
+ * @param twsi_id   Octeon TWSI interface to use
+ * @param dev_addr  TWSI device address
+ * @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
+ * @param data      Data to write
+ * 
+ * @return 0 on success
+ *         -1 on failure
+ */
+int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data)
+{
+    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+
+    if (num_bytes > 8 || num_bytes < 1)
+        return -1;
+
+    sw_twsi_val.u64 = 0;
+    sw_twsi_val.s.v = 1;
+    sw_twsi_val.s.a = dev_addr;
+    sw_twsi_val.s.d = data & 0xffffffff;
+    sw_twsi_val.s.sovr = 1;
+    sw_twsi_val.s.size = num_bytes - 1;
+    if (num_bytes > 4)
+    {
+        /* Upper four bytes go into a separate register */
+        cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+        twsi_ext.u64 = 0;
+        twsi_ext.s.d = data >> 32;
+        cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+    }
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+        ;
+    if (!sw_twsi_val.s.r)
+        return -1;
+
+    return 0;
+}
+
+/**
+ * Write 1-8 bytes to a TWSI device using an internal address.
+ * 
+ * @param twsi_id   which TWSI interface on Octeon to use
+ * @param dev_addr  TWSI device address (7 bit only)
+ * @param internal_addr
+ *                  TWSI internal address (0, 8, or 16 bits)
+ * @param num_bytes Number of bytes to write (1-8)
+ * @param ia_width_bytes
+ *                  internal address width, in bytes (0, 1, 2)
+ * @param data      Data to write.  Data is written MSB first on the twsi bus, and only the lower
+ *                  num_bytes bytes of the argument are valid.  (If a 2 byte write is done, only
+ *                  the low 2 bytes of the argument is used.
+ * 
+ * @return Number of bytes read on success,
+ *         -1 on error
+ */
+int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
+{
+    cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
+    cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
+    int to;
+
+    if (num_bytes < 1 || num_bytes > 8 || ia_width_bytes < 0 || ia_width_bytes > 2)
+        return -1;
+
+    twsi_ext.u64 = 0;
+
+    sw_twsi_val.u64 = 0;
+    sw_twsi_val.s.v = 1;
+    sw_twsi_val.s.sovr = 1;
+    sw_twsi_val.s.size = num_bytes - 1;
+    sw_twsi_val.s.a = dev_addr;
+    sw_twsi_val.s.d = 0xFFFFFFFF & data;
+
+    if (ia_width_bytes > 0)
+    {
+        sw_twsi_val.s.op = 1;
+        sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
+        sw_twsi_val.s.eop_ia = internal_addr & 0x7;
+    } 
+    if (ia_width_bytes == 2)
+    {
+        sw_twsi_val.s.eia = 1;
+        twsi_ext.s.ia = internal_addr >> 8;
+        cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+    }
+    if (num_bytes > 4)
+        twsi_ext.s.d = data >> 32;
+
+
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
+    cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
+    while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
+        ;
+
+    /* Poll until reads succeed, or polling times out */
+    to = 100;
+    while (to-- > 0)
+    {
+        uint64_t data;
+        if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
+            break;
+    }
+    if (to <= 0)
+        return -1;
+
+    return num_bytes;
+}
+
diff --git a/cvmx-twsi.h b/cvmx-twsi.h
new file mode 100644
index 0000000000000..e2a4295062c7a
--- /dev/null
+++ b/cvmx-twsi.h
@@ -0,0 +1,313 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Interface to the TWSI / I2C bus
+ * 
+ * Note: Currently on 7 bit device addresses are supported
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_TWSI_H__
+#define __CVMX_TWSI_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * Do a twsi read from a 7 bit device address using an (optional) internal address.
+ * Up to 8 bytes can be read at a time.
+ * 
+ * @param twsi_id   which Octeon TWSI bus to use
+ * @param dev_addr  Device address (7 bit)
+ * @param internal_addr
+ *                  Internal address.  Can be 0, 1 or 2 bytes in width
+ * @param num_bytes Number of data bytes to read
+ * @param ia_width_bytes
+ *                  Internal address size in bytes (0, 1, or 2)
+ * @param data      Pointer argument where the read data is returned.
+ * 
+ * @return read data returned in 'data' argument
+ *         Number of bytes read on success
+ *         -1 on failure
+ */
+int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data);
+
+
+
+
+/**
+ * A convenience wrapper function around cvmx_twsix_read_ia() that
+ * only supports 8 bit internal addresses.
+ * Reads up to 7 bytes, and returns both the value read or error
+ * value in the return value
+ * 
+ * @param twsi_id   which Octeon TWSI bus to use
+ * @param dev_addr  Device address (7 bit only)
+ * @param internal_addr
+ *                  Internal address (8 bit only)
+ * @param num_bytes Number of bytes to read (0-7)
+ * 
+ * @return Value read from TWSI on success
+ *         -1 on error
+ */
+static inline int64_t cvmx_twsix_read_ia8(int twsi_id, uint8_t dev_addr, uint8_t internal_addr, int num_bytes)
+{
+    uint64_t data;
+    if (num_bytes < 1 || num_bytes > 7)
+        return -1;
+    if (cvmx_twsix_read_ia(twsi_id,dev_addr,internal_addr,num_bytes, 1, &data) < 0)
+        return -1;
+    return data;
+}
+
+/**
+ * A convenience wrapper function around cvmx_twsix_read_ia() that
+ * only supports 16 bit internal addresses.
+ * Reads up to 7 bytes, and returns both the value read or error
+ * value in the return value
+ * 
+ * @param twsi_id   which Octeon TWSI bus to use
+ * @param dev_addr  Device address (7 bit only)
+ * @param internal_addr
+ *                  Internal address (16 bit only)
+ * @param num_bytes Number of bytes to read (0-7)
+ * 
+ * @return Value read from TWSI on success
+ *         -1 on error
+ */
+static inline int64_t cvmx_twsix_read_ia16(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes)
+{
+    uint64_t data;
+    if (num_bytes < 1 || num_bytes > 7)
+        return -1;
+    if (cvmx_twsix_read_ia(twsi_id, dev_addr, internal_addr, num_bytes, 2, &data) < 0)
+        return -1;
+    return data;
+}
+
+
+
+/**
+ * Read from a TWSI device (7 bit device address only) without generating any
+ * internal addresses.
+ * Read from 1-8 bytes and returns them in the data pointer.
+ * 
+ * @param twsi_id   TWSI interface on Octeon to use
+ * @param dev_addr  TWSI device address (7 bit only)
+ * @param num_bytes number of bytes to read
+ * @param data      Pointer to data read from TWSI device
+ * 
+ * @return Number of bytes read on success
+ *         -1 on error
+ */
+int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data);
+
+
+
+/**
+ * Perform a twsi write operation to a 7 bit device address.
+ * 
+ * Note that many eeprom devices have page restrictions regarding address boundaries
+ * that can be crossed in one write operation.  This is device dependent, and this routine
+ * does nothing in this regard.
+ * This command does not generate any internal addressess.
+ * 
+ * @param twsi_id   Octeon TWSI interface to use
+ * @param dev_addr  TWSI device address
+ * @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
+ * @param data      Data to write
+ * 
+ * @return 0 on success
+ *         -1 on failure
+ */
+int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data);
+
+/**
+ * Write 1-8 bytes to a TWSI device using an internal address.
+ * 
+ * @param twsi_id   which TWSI interface on Octeon to use
+ * @param dev_addr  TWSI device address (7 bit only)
+ * @param internal_addr
+ *                  TWSI internal address (0, 8, or 16 bits)
+ * @param num_bytes Number of bytes to write (1-8)
+ * @param ia_width_bytes
+ *                  internal address width, in bytes (0, 1, 2)
+ * @param data      Data to write.  Data is written MSB first on the twsi bus, and only the lower
+ *                  num_bytes bytes of the argument are valid.  (If a 2 byte write is done, only
+ *                  the low 2 bytes of the argument is used.
+ * 
+ * @return Number of bytes read on success,
+ *         -1 on error
+ */
+int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data);
+
+/***********************************************************************
+** Functions below are deprecated, and not recomended for use.
+** They have been superceded by more flexible functions that are
+** now provided.
+************************************************************************/
+
+
+
+
+
+
+/**
+ * Read 8-bit from a device on the TWSI / I2C bus
+ *
+ * @param twsi_id  Which TWSI bus to use. CN3XXX, CN58XX, and CN50XX only
+ *                 support 0. CN56XX and CN57XX support 0-1.
+ * @param dev_addr I2C device address (7 bit)
+ * @param internal_addr
+ *                 Internal device address
+ *
+ * @return 8-bit data or < 0 in case of error
+ */
+static inline int cvmx_twsix_read8(int twsi_id, uint8_t dev_addr, uint8_t internal_addr)
+{
+    return cvmx_twsix_read_ia8(twsi_id, dev_addr, internal_addr, 1);
+}
+
+/**
+ * Read 8-bit from a device on the TWSI / I2C bus
+ *
+ * Uses current internal address
+ *
+ * @param twsi_id  Which TWSI bus to use. CN3XXX, CN58XX, and CN50XX only
+ *                 support 0. CN56XX and CN57XX support 0-1.
+ * @param dev_addr I2C device address (7 bit)
+ *
+ * @return 8-bit value or < 0 in case of error
+ */
+static inline int cvmx_twsix_read8_cur_addr(int twsi_id, uint8_t dev_addr)
+{
+    uint64_t data;
+
+    if (cvmx_twsix_read(twsi_id,dev_addr, 1, &data) < 0)
+        return -1;
+    return(data & 0xff);
+}
+
+/**
+ * Write 8-bit to a device on the TWSI / I2C bus
+ *
+ * @param twsi_id  Which TWSI bus to use. CN3XXX, CN58XX, and CN50XX only
+ *                 support 0. CN56XX and CN57XX support 0-1.
+ * @param dev_addr I2C device address (7 bit)
+ * @param internal_addr
+ *                 Internal device address
+ * @param data     Data to be written
+ *
+ * @return 0 on success and < 0 in case of error
+ */
+static inline int cvmx_twsix_write8(int twsi_id, uint8_t dev_addr, uint8_t internal_addr, uint8_t data)
+{
+    if (cvmx_twsix_write_ia(twsi_id,dev_addr,internal_addr, 1, 1,data) < 0)
+        return -1;
+    return 0;
+}
+
+/**
+ * Read 8-bit from a device on the TWSI / I2C bus zero.
+ *
+ * This function is for compatibility with SDK 1.6.0 and
+ * before which only supported a single TWSI bus.
+ *
+ * @param dev_addr I2C device address (7 bit)
+ * @param internal_addr
+ *                 Internal device address
+ *
+ * @return 8-bit data or < 0 in case of error
+ */
+static inline int cvmx_twsi_read8(uint8_t dev_addr, uint8_t internal_addr)
+{
+    return cvmx_twsix_read8(0, dev_addr, internal_addr);
+}
+
+/**
+ * Read 8-bit from a device on the TWSI / I2C bus zero.
+ *
+ * Uses current internal address
+ *
+ * This function is for compatibility with SDK 1.6.0 and
+ * before which only supported a single TWSI bus.
+ *
+ * @param dev_addr I2C device address (7 bit)
+ *
+ * @return 8-bit value or < 0 in case of error
+ */
+static inline int cvmx_twsi_read8_cur_addr(uint8_t dev_addr)
+{
+    return cvmx_twsix_read8_cur_addr(0, dev_addr);
+}
+
+/**
+ * Write 8-bit to a device on the TWSI / I2C bus zero.
+ * This function is for compatibility with SDK 1.6.0 and
+ * before which only supported a single TWSI bus.
+ *
+ * @param dev_addr I2C device address (7 bit)
+ * @param internal_addr
+ *                 Internal device address
+ * @param data     Data to be written
+ *
+ * @return 0 on success and < 0 in case of error
+ */
+static inline int cvmx_twsi_write8(uint8_t dev_addr, uint8_t internal_addr, uint8_t data)
+{
+    return cvmx_twsix_write8(0, dev_addr, internal_addr, data);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /*  __CVMX_TWSI_H__ */
diff --git a/cvmx-uart.h b/cvmx-uart.h
new file mode 100644
index 0000000000000..9c5a0affea15e
--- /dev/null
+++ b/cvmx-uart.h
@@ -0,0 +1,74 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * interface to the serial port UART hardware
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+
+#ifndef __CVMX_UART_H__
+#define __CVMX_UART_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define CVMX_UART_NUM_PORTS     2
+#define CVMX_UART_TX_FIFO_SIZE  64
+#define CVMX_UART_RX_FIFO_SIZE  64
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/* Defined in libc.  */
+unsigned __octeon_uart_trylock (void);
+void __octeon_uart_unlock (void);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /*  __CVM_UART_H__ */
diff --git a/cvmx-usb.c b/cvmx-usb.c
new file mode 100644
index 0000000000000..99a60605b3d9c
--- /dev/null
+++ b/cvmx-usb.c
@@ -0,0 +1,3650 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * "cvmx-usb.c" defines a set of low level USB functions to help
+ * developers create Octeon USB drivers for various operating
+ * systems. These functions provide a generic API to the Octeon
+ * USB blocks, hiding the internal hardware specific
+ * operations.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-sysinfo.h"
+#include "cvmx-usb.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+#include "cvmx-csr-db.h"
+#include "cvmx-swap.h"
+
+#define MAX_RETRIES         3   /* Maximum number of times to retry failed transactions */
+#define MAX_PIPES           32  /* Maximum number of pipes that can be open at once */
+#define MAX_TRANSACTIONS    256 /* Maximum number of outstanding transactions across all pipes */
+#define MAX_CHANNELS        8   /* Maximum number of hardware channels supported by the USB block */
+#define MAX_USB_ADDRESS     127 /* The highest valid USB device address */
+#define MAX_USB_ENDPOINT    15  /* The highest valid USB endpoint number */
+#define MAX_USB_HUB_PORT    15  /* The highest valid port number on a hub */
+#define ALLOW_CSR_DECODES   0   /* CSR decoding when CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS is set
+                                    enlarges the code a lot. This define overrides the ability to do CSR
+                                    decoding since it isn't necessary 99% of the time. Change this to a
+                                    one if you need CSR decoding */
+
+/* These defines disable the normal read and write csr. This is so I can add
+    extra debug stuff to the usb specific version and I won't use the normal
+    version by mistake */
+#define cvmx_read_csr use_cvmx_usb_read_csr64_instead_of_cvmx_read_csr
+#define cvmx_write_csr use_cvmx_usb_write_csr64_instead_of_cvmx_write_csr
+
+typedef enum
+{
+    __CVMX_USB_TRANSACTION_FLAGS_IN_USE = 1<<16,
+} cvmx_usb_transaction_flags_t;
+
+/**
+ * Logical transactions may take numerous low level
+ * transactions, especially when splits are concerned. This
+ * enum represents all of the possible stages a transaction can
+ * be in. Note that split completes are always even. This is so
+ * the NAK handler can backup to the previous low level
+ * transaction with a simple clearing of bit 0.
+ */
+typedef enum
+{
+    CVMX_USB_STAGE_NON_CONTROL,
+    CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
+    CVMX_USB_STAGE_SETUP,
+    CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
+    CVMX_USB_STAGE_DATA,
+    CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
+    CVMX_USB_STAGE_STATUS,
+    CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
+} cvmx_usb_stage_t;
+
+/**
+ * This structure describes each pending USB transaction
+ * regardless of type. These are linked together to form a list
+ * of pending requests for a pipe.
+ */
+typedef struct cvmx_usb_transaction
+{
+    struct cvmx_usb_transaction *prev;  /**< Transaction before this one in the pipe */
+    struct cvmx_usb_transaction *next;  /**< Transaction after this one in the pipe */
+    cvmx_usb_transfer_t type;           /**< Type of transaction, duplicated of the pipe */
+    cvmx_usb_transaction_flags_t flags; /**< State flags for this transaction */
+    uint64_t buffer;                    /**< User's physical buffer address to read/write */
+    int buffer_length;                  /**< Size of the user's buffer in bytes */
+    uint64_t control_header;            /**< For control transactions, physical address of the 8 byte standard header */
+    int iso_start_frame;                /**< For ISO transactions, the starting frame number */
+    int iso_number_packets;             /**< For ISO transactions, the number of packets in the request */
+    cvmx_usb_iso_packet_t *iso_packets; /**< For ISO transactions, the sub packets in the request */
+    int xfersize;
+    int pktcnt;
+    int retries;
+    int actual_bytes;                   /**< Actual bytes transfer for this transaction */
+    cvmx_usb_stage_t stage;             /**< For control transactions, the current stage */
+    cvmx_usb_callback_func_t callback;  /**< User's callback function when complete */
+    void *callback_data;                /**< User's data */
+} cvmx_usb_transaction_t;
+
+/**
+ * A pipe represents a virtual connection between Octeon and some
+ * USB device. It contains a list of pending request to the device.
+ */
+typedef struct cvmx_usb_pipe
+{
+    struct cvmx_usb_pipe *prev;         /**< Pipe before this one in the list */
+    struct cvmx_usb_pipe *next;         /**< Pipe after this one in the list */
+    cvmx_usb_transaction_t *head;       /**< The first pending transaction */
+    cvmx_usb_transaction_t *tail;       /**< The last pending transaction */
+    uint64_t interval;                  /**< For periodic pipes, the interval between packets in cycles */
+    uint64_t next_tx_cycle;             /**< The next cycle this pipe is allowed to transmit on */
+    cvmx_usb_pipe_flags_t flags;        /**< State flags for this pipe */
+    cvmx_usb_speed_t device_speed;      /**< Speed of device connected to this pipe */
+    cvmx_usb_transfer_t transfer_type;  /**< Type of transaction supported by this pipe */
+    cvmx_usb_direction_t transfer_dir;  /**< IN or OUT. Ignored for Control */
+    int multi_count;                    /**< Max packet in a row for the device */
+    uint16_t max_packet;                /**< The device's maximum packet size in bytes */
+    uint8_t device_addr;                /**< USB device address at other end of pipe */
+    uint8_t endpoint_num;               /**< USB endpoint number at other end of pipe */
+    uint8_t hub_device_addr;            /**< Hub address this device is connected to */
+    uint8_t hub_port;                   /**< Hub port this device is connected to */
+    uint8_t pid_toggle;                 /**< This toggles between 0/1 on every packet send to track the data pid needed */
+    uint8_t channel;                    /**< Hardware DMA channel for this pipe */
+    int8_t  split_sc_frame;             /**< The low order bits of the frame number the split complete should be sent on */
+} cvmx_usb_pipe_t;
+
+typedef struct
+{
+    cvmx_usb_pipe_t *head;              /**< Head of the list, or NULL if empty */
+    cvmx_usb_pipe_t *tail;              /**< Tail if the list, or NULL if empty */
+} cvmx_usb_pipe_list_t;
+
+/**
+ * The state of the USB block is stored in this structure
+ */
+typedef struct
+{
+    int init_flags;                     /**< Flags passed to initialize */
+    int index;                          /**< Which USB block this is for */
+    int idle_hardware_channels;         /**< Bit set for every idle hardware channel */
+    int active_transactions;            /**< Number of active transactions across all pipes */
+    cvmx_usbcx_hprt_t usbcx_hprt;       /**< Stored port status so we don't need to read a CSR to determine splits */
+    cvmx_usb_pipe_t *pipe_for_channel[MAX_CHANNELS];    /**< Map channels to pipes */
+    cvmx_usb_transaction_t *free_transaction_head;      /**< List of free transactions head */
+    cvmx_usb_transaction_t *free_transaction_tail;      /**< List of free transactions tail */
+    cvmx_usb_pipe_t pipe[MAX_PIPES];                    /**< Storage for pipes */
+    cvmx_usb_transaction_t transaction[MAX_TRANSACTIONS];       /**< Storage for transactions */
+    cvmx_usb_callback_func_t callback[__CVMX_USB_CALLBACK_END]; /**< User global callbacks */
+    void *callback_data[__CVMX_USB_CALLBACK_END];               /**< User data for each callback */
+    int indent;                         /**< Used by debug output to indent functions */
+    cvmx_usb_port_status_t port_status; /**< Last port status used for change notification */
+    cvmx_usb_pipe_list_t free_pipes;    /**< List of all pipes that are currently closed */
+    cvmx_usb_pipe_list_t idle_pipes;    /**< List of open pipes that have no transactions */
+    cvmx_usb_pipe_list_t active_pipes[4]; /**< Active pipes indexed by transfer type */
+} cvmx_usb_internal_state_t;
+
+/* This macro logs out whenever a function is called if debugging is on */
+#define CVMX_USB_LOG_CALLED() \
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLS)) \
+        cvmx_dprintf("%*s%s: called\n", 2*usb->indent++, "", __FUNCTION__);
+
+/* This macro logs out each function parameter if debugging is on */
+#define CVMX_USB_LOG_PARAM(format, param) \
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLS)) \
+        cvmx_dprintf("%*s%s: param %s = " format "\n", 2*usb->indent, "", __FUNCTION__, #param, param);
+
+/* This macro logs out when a function returns a value */
+#define CVMX_USB_RETURN(v)                                              \
+    do {                                                                \
+        typeof(v) r = v;                                                \
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLS))    \
+            cvmx_dprintf("%*s%s: returned %s(%d)\n", 2*--usb->indent, "", __FUNCTION__, #v, r); \
+        return r;                                                       \
+    } while (0);
+
+/* This macro logs out when a function doesn't return a value */
+#define CVMX_USB_RETURN_NOTHING()                                       \
+    do {                                                                \
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLS))    \
+            cvmx_dprintf("%*s%s: returned\n", 2*--usb->indent, "", __FUNCTION__); \
+        return;                                                         \
+    } while (0);
+
+/* This macro spins on a field waiting for it to reach a value */
+#define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
+    ({int result;                                                       \
+    do {                                                                \
+        uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec *     \
+                           cvmx_sysinfo_get()->cpu_clock_hz / 1000000;  \
+        type c;                                                         \
+        while (1)                                                       \
+        {                                                               \
+            c.u32 = __cvmx_usb_read_csr32(usb, address);                \
+            if (c.s.field op (value)) {                                 \
+                result = 0;                                             \
+                break;                                                  \
+            } else if (cvmx_get_cycle() > done) {                       \
+                result = -1;                                            \
+                break;                                                  \
+            } else                                                      \
+                cvmx_wait(100);                                         \
+        }                                                               \
+    } while (0);                                                        \
+    result;})
+
+/* This macro logically sets a single field in a CSR. It does the sequence
+    read, modify, and write */
+#define USB_SET_FIELD32(address, type, field, value)\
+    do {                                            \
+        type c;                                     \
+        c.u32 = __cvmx_usb_read_csr32(usb, address);\
+        c.s.field = value;                          \
+        __cvmx_usb_write_csr32(usb, address, c.u32);\
+    } while (0)
+
+
+/**
+ * @INTERNAL
+ * Read a USB 32bit CSR. It performs the necessary address swizzle
+ * for 32bit CSRs and logs the value in a readable format if
+ * debugging is on.
+ *
+ * @param usb     USB block this access is for
+ * @param address 64bit address to read
+ *
+ * @return Result of the read
+ */
+static inline uint32_t __cvmx_usb_read_csr32(cvmx_usb_internal_state_t *usb,
+                                             uint64_t address)
+{
+    uint32_t result = cvmx_read64_uint32(address ^ 4);
+#if ALLOW_CSR_DECODES
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS))
+    {
+        cvmx_dprintf("Read: ");
+        cvmx_csr_db_decode(cvmx_get_proc_id(), address, result);
+    }
+#endif
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Write a USB 32bit CSR. It performs the necessary address
+ * swizzle for 32bit CSRs and logs the value in a readable format
+ * if debugging is on.
+ *
+ * @param usb     USB block this access is for
+ * @param address 64bit address to write
+ * @param value   Value to write
+ */
+static inline void __cvmx_usb_write_csr32(cvmx_usb_internal_state_t *usb,
+                                          uint64_t address, uint32_t value)
+{
+#if ALLOW_CSR_DECODES
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS))
+    {
+        cvmx_dprintf("Write: ");
+        cvmx_csr_db_decode(cvmx_get_proc_id(), address, value);
+    }
+#endif
+    cvmx_write64_uint32(address ^ 4, value);
+}
+
+
+/**
+ * @INTERNAL
+ * Read a USB 64bit CSR. It logs the value in a readable format if
+ * debugging is on.
+ *
+ * @param usb     USB block this access is for
+ * @param address 64bit address to read
+ *
+ * @return Result of the read
+ */
+static inline uint64_t __cvmx_usb_read_csr64(cvmx_usb_internal_state_t *usb,
+                                             uint64_t address)
+{
+    uint64_t result = cvmx_read64_uint64(address);
+#if ALLOW_CSR_DECODES
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS))
+    {
+        cvmx_dprintf("Read: ");
+        cvmx_csr_db_decode(cvmx_get_proc_id(), address, result);
+    }
+#endif
+    return result;
+}
+
+
+/**
+ * @INTERNAL
+ * Write a USB 64bit CSR. It logs the value in a readable format
+ * if debugging is on.
+ *
+ * @param usb     USB block this access is for
+ * @param address 64bit address to write
+ * @param value   Value to write
+ */
+static inline void __cvmx_usb_write_csr64(cvmx_usb_internal_state_t *usb,
+                                          uint64_t address, uint64_t value)
+{
+#if ALLOW_CSR_DECODES
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS))
+    {
+        cvmx_dprintf("Write: ");
+        cvmx_csr_db_decode(cvmx_get_proc_id(), address, value);
+    }
+#endif
+    cvmx_write64_uint64(address, value);
+}
+
+
+/**
+ * @INTERNAL
+ * Uitility function to convert complete codes into strings
+ *
+ * @param complete_code
+ *               Code to convert
+ *
+ * @return Human readable string
+ */
+static const char *__cvmx_usb_complete_to_string(cvmx_usb_complete_t complete_code)
+{
+    switch (complete_code)
+    {
+        case CVMX_USB_COMPLETE_SUCCESS: return "SUCCESS";
+        case CVMX_USB_COMPLETE_SHORT:   return "SHORT";
+        case CVMX_USB_COMPLETE_CANCEL:  return "CANCEL";
+        case CVMX_USB_COMPLETE_ERROR:   return "ERROR";
+        case CVMX_USB_COMPLETE_STALL:   return "STALL";
+        case CVMX_USB_COMPLETE_XACTERR: return "XACTERR";
+        case CVMX_USB_COMPLETE_DATATGLERR: return "DATATGLERR";
+        case CVMX_USB_COMPLETE_BABBLEERR: return "BABBLEERR";
+        case CVMX_USB_COMPLETE_FRAMEERR: return "FRAMEERR";
+    }
+    return "Update __cvmx_usb_complete_to_string";
+}
+
+
+/**
+ * @INTERNAL
+ * Return non zero if this pipe connects to a non HIGH speed
+ * device through a high speed hub.
+ *
+ * @param usb    USB block this access is for
+ * @param pipe   Pipe to check
+ *
+ * @return Non zero if we need to do split transactions
+ */
+static inline int __cvmx_usb_pipe_needs_split(cvmx_usb_internal_state_t *usb, cvmx_usb_pipe_t *pipe)
+{
+    return ((pipe->device_speed != CVMX_USB_SPEED_HIGH) && (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH));
+}
+
+
+/**
+ * @INTERNAL
+ * Trivial utility function to return the correct PID for a pipe
+ *
+ * @param pipe   pipe to check
+ *
+ * @return PID for pipe
+ */
+static inline int __cvmx_usb_get_data_pid(cvmx_usb_pipe_t *pipe)
+{
+    if (pipe->pid_toggle)
+        return 2; /* Data1 */
+    else
+        return 0; /* Data0 */
+}
+
+
+/**
+ * Return the number of USB ports supported by this Octeon
+ * chip. If the chip doesn't support USB, or is not supported
+ * by this API, a zero will be returned. Most Octeon chips
+ * support one usb port, but some support two ports.
+ * cvmx_usb_initialize() must be called on independent
+ * cvmx_usb_state_t structures.
+ *
+ * This utilizes cvmx_helper_board_usb_get_num_ports()
+ * to get any board specific variatons.
+ *
+ * @return Number of port, zero if usb isn't supported
+ */
+int cvmx_usb_get_num_ports(void)
+{
+    int arch_ports = 0;
+
+    if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+        arch_ports = 2;
+    else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
+        arch_ports = 0; /* This chip has USB but it doesn't support DMA */
+    else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+        arch_ports = 0;
+    else
+        arch_ports = 1;
+
+    return __cvmx_helper_board_usb_get_num_ports(arch_ports);
+}
+
+
+/**
+ * @INTERNAL
+ * Allocate a usb transaction for use
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Transaction or NULL
+ */
+static inline cvmx_usb_transaction_t *__cvmx_usb_alloc_transaction(cvmx_usb_internal_state_t *usb)
+{
+    cvmx_usb_transaction_t *t;
+    t = usb->free_transaction_head;
+    if (t)
+    {
+        usb->free_transaction_head = t->next;
+        if (!usb->free_transaction_head)
+            usb->free_transaction_tail = NULL;
+    }
+    else if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+        cvmx_dprintf("%s: Failed to allocate a transaction\n", __FUNCTION__);
+    if (t)
+    {
+        memset(t, 0, sizeof(*t));
+        t->flags = __CVMX_USB_TRANSACTION_FLAGS_IN_USE;
+    }
+    return t;
+}
+
+
+/**
+ * @INTERNAL
+ * Free a usb transaction
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param transaction
+ *               Transaction to free
+ */
+static inline void __cvmx_usb_free_transaction(cvmx_usb_internal_state_t *usb,
+                                        cvmx_usb_transaction_t *transaction)
+{
+    transaction->flags = 0;
+    transaction->prev = NULL;
+    transaction->next = NULL;
+    if (usb->free_transaction_tail)
+        usb->free_transaction_tail->next = transaction;
+    else
+        usb->free_transaction_head = transaction;
+    usb->free_transaction_tail = transaction;
+}
+
+
+/**
+ * @INTERNAL
+ * Add a pipe to the tail of a list
+ * @param list   List to add pipe to
+ * @param pipe   Pipe to add
+ */
+static inline void __cvmx_usb_append_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_pipe_t *pipe)
+{
+    pipe->next = NULL;
+    pipe->prev = list->tail;
+    if (list->tail)
+        list->tail->next = pipe;
+    else
+        list->head = pipe;
+    list->tail = pipe;
+}
+
+
+/**
+ * @INTERNAL
+ * Remove a pipe from a list
+ * @param list   List to remove pipe from
+ * @param pipe   Pipe to remove
+ */
+static inline void __cvmx_usb_remove_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_pipe_t *pipe)
+{
+    if (list->head == pipe)
+    {
+        list->head = pipe->next;
+        pipe->next = NULL;
+        if (list->head)
+            list->head->prev = NULL;
+        else
+            list->tail = NULL;
+    }
+    else if (list->tail == pipe)
+    {
+        list->tail = pipe->prev;
+        list->tail->next = NULL;
+        pipe->prev = NULL;
+    }
+    else
+    {
+        pipe->prev->next = pipe->next;
+        pipe->next->prev = pipe->prev;
+        pipe->prev = NULL;
+        pipe->next = NULL;
+    }
+}
+
+
+/**
+ * @INTERNAL
+ * Perfrom USB device mode initialization after a reset completes.
+ * This should be called after USBC0/1_GINTSTS[USBRESET] and
+ * coresponds to section 22.6.1.1, "Initialization on USB Reset",
+ * in the manual.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+static cvmx_usb_status_t __cvmx_usb_device_reset_complete(cvmx_usb_internal_state_t *usb)
+{
+    cvmx_usbcx_ghwcfg3_t usbcx_ghwcfg3;
+    int i;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+
+    /* 1. Set USBC0/1_DOEPCTLn[SNAK] = 1 (for all OUT endpoints, n = 0-4). */
+    for (i=0; i<5; i++)
+    {
+        USB_SET_FIELD32(CVMX_USBCX_DOEPCTLX(i, usb->index),
+                        cvmx_usbcx_doepctlx_t, snak, 1);
+    }
+
+    /* 2. Unmask the following interrupt bits:
+        USBC0/1_DAINTMSK[INEPMSK] = 1 (control 0 IN endpoint)
+        USBC0/1_DAINTMSK[OUTEPMSK] = 1 (control 0 OUT endpoint)
+        USBC0/1_DOEPMSK[SETUPMSK] = 1
+        USBC0/1_DOEPMSK[XFERCOMPLMSK] = 1
+        USBC0/1_DIEPMSK[XFERCOMPLMSK] = 1
+        USBC0/1_DIEPMSK[TIMEOUTMSK] = 1 */
+    USB_SET_FIELD32(CVMX_USBCX_DAINTMSK(usb->index), cvmx_usbcx_daintmsk_t,
+                    inepmsk, 1);
+    USB_SET_FIELD32(CVMX_USBCX_DAINTMSK(usb->index), cvmx_usbcx_daintmsk_t,
+                    outepmsk, 1);
+    USB_SET_FIELD32(CVMX_USBCX_DOEPMSK(usb->index), cvmx_usbcx_doepmsk_t,
+                    setupmsk, 1);
+    USB_SET_FIELD32(CVMX_USBCX_DOEPMSK(usb->index), cvmx_usbcx_doepmsk_t,
+                    xfercomplmsk, 1);
+    USB_SET_FIELD32(CVMX_USBCX_DIEPMSK(usb->index), cvmx_usbcx_diepmsk_t,
+                    xfercomplmsk, 1);
+    USB_SET_FIELD32(CVMX_USBCX_DIEPMSK(usb->index), cvmx_usbcx_diepmsk_t,
+                    timeoutmsk, 1);
+
+    /* 3. To transmit or receive data, the device must initialize more
+        registers as specified in Section 22.6.1.7 */
+    /* Nothing needed */
+
+    /* 4. Set up the data FIFO RAM for each of the FIFOs:
+        Program USBC0/1_GRXFSIZ to be able to receive control OUT data and
+        SETUP data. This must equal at least one maximum packet size of
+        control endpoint 0 + 2 Dwords (for the status of the control OUT
+        data packet) + 10 Dwords (for SETUP packets).
+        Program USBC0/1_GNPTXFSIZ to be able to transmit control IN data. This
+        must equal at least one maximum packet size of control endpoint 0. */
+
+    /* Read the HWCFG3 register so we know how much space is in the FIFO */
+    usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
+
+    {
+        cvmx_usbcx_gnptxfsiz_t gnptxfsiz;
+        int fifo_space = usbcx_ghwcfg3.s.dfifodepth;
+        int i;
+
+        /* Start at the top of the FIFO and assign space for each periodic
+            fifo */
+        for (i=4;i>0;i--)
+        {
+            cvmx_usbcx_dptxfsizx_t siz;
+            siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DPTXFSIZX(i, usb->index));
+            fifo_space -= siz.s.dptxfsize;
+            siz.s.dptxfstaddr = fifo_space;
+            __cvmx_usb_write_csr32(usb, CVMX_USBCX_DPTXFSIZX(i, usb->index), siz.u32);
+        }
+
+        /* Assign half the leftover space to the non periodic tx fifo */
+        gnptxfsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
+        gnptxfsiz.s.nptxfdep = fifo_space / 2;
+        fifo_space -= gnptxfsiz.s.nptxfdep;
+        gnptxfsiz.s.nptxfstaddr = fifo_space;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), gnptxfsiz.u32);
+
+        /* Assign the remain space to the RX fifo */
+        USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz_t,
+                        rxfdep, fifo_space);
+    }
+
+    /* 5. Program the following fields in the endpoint-specific registers for
+        control OUT endpoint 0 to receive a SETUP packet
+        USBC0/1_DOEPTSIZ0[SUPCNT] = 0x3 (to receive up to three back-to-back
+        SETUP packets)
+        In DMA mode, USBC0/1_DOEPDMA0 register with a memory address to
+        store any SETUP packets received */
+    USB_SET_FIELD32(CVMX_USBCX_DOEPTSIZX(0, usb->index),
+                    cvmx_usbcx_doeptsizx_t, mc, 3);
+    // FIXME
+
+    /* At this point, all initialization required to receive SETUP packets is
+        done. */
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Initialize a USB port for use. This must be called before any
+ * other access to the Octeon USB port is made. The port starts
+ * off in the disabled state.
+ *
+ * @param state  Pointer to an empty cvmx_usb_state_t structure
+ *               that will be populated by the initialize call.
+ *               This structure is then passed to all other USB
+ *               functions.
+ * @param usb_port_number
+ *               Which Octeon USB port to initialize.
+ * @param flags  Flags to control hardware initialization. See
+ *               cvmx_usb_initialize_flags_t for the flag
+ *               definitions. Some flags are mandatory.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
+                                      int usb_port_number,
+                                      cvmx_usb_initialize_flags_t flags)
+{
+    cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
+    cvmx_usbnx_usbp_ctl_status_t usbn_usbp_ctl_status;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    usb->init_flags = flags;
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", usb_port_number);
+    CVMX_USB_LOG_PARAM("0x%x", flags);
+
+    /* Make sure that state is large enough to store the internal state */
+    if (sizeof(*state) < sizeof(*usb))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    /* At first allow 0-1 for the usb port number */
+    if ((usb_port_number < 0) || (usb_port_number > 1))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    /* For all chips except 52XX there is only one port */
+    if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    /* Try to determine clock type automatically */
+    if ((flags & (CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI |
+                  CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND)) == 0)
+    {
+        if (__cvmx_helper_board_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12)
+            flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;  /* Only 12 MHZ crystals are supported */
+        else
+            flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
+    }
+
+    if (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND)
+    {
+        /* Check for auto ref clock frequency */
+        if (!(flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK))
+            switch (__cvmx_helper_board_usb_get_clock_type())
+            {
+                case USB_CLOCK_TYPE_REF_12:
+                    flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
+                    break;
+                case USB_CLOCK_TYPE_REF_24:
+                    flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
+                    break;
+                case USB_CLOCK_TYPE_REF_48:
+                    flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
+                    break;
+                default:
+                    CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+                    break;
+            }
+    }
+
+    memset(usb, 0, sizeof(usb));
+    usb->init_flags = flags;
+
+    /* Initialize the USB state structure */
+    {
+        int i;
+        usb->index = usb_port_number;
+
+        /* Initialize the transaction double linked list */
+        usb->free_transaction_head = NULL;
+        usb->free_transaction_tail = NULL;
+        for (i=0; i<MAX_TRANSACTIONS; i++)
+            __cvmx_usb_free_transaction(usb, usb->transaction + i);
+        for (i=0; i<MAX_PIPES; i++)
+            __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
+    }
+
+    /* Power On Reset and PHY Initialization */
+
+    /* 1. Wait for DCOK to assert (nothing to do) */
+    /* 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
+        USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 */
+    usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
+    usbn_clk_ctl.s.por = 1;
+    usbn_clk_ctl.s.hrst = 0;
+    usbn_clk_ctl.s.prst = 0;
+    usbn_clk_ctl.s.hclk_rst = 0;
+    usbn_clk_ctl.s.enable = 0;
+    /* 2b. Select the USB reference clock/crystal parameters by writing
+        appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] */
+    if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND)
+    {
+        /* The USB port uses 12/24/48MHz 2.5V board clock
+            source at USB_XO. USB_XI should be tied to GND.
+            Most Octeon evaluation boards require this setting */
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        {
+            usbn_clk_ctl.cn31xx.p_rclk  = 1; /* From CN31XX,CN30XX manual */
+            usbn_clk_ctl.cn31xx.p_xenbn = 0;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+            usbn_clk_ctl.cn56xx.p_rtype = 2; /* From CN56XX,CN50XX manual */
+        else
+            usbn_clk_ctl.cn52xx.p_rtype = 1; /* From CN52XX manual */
+
+        switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK)
+        {
+            case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
+                usbn_clk_ctl.s.p_c_sel = 0;
+                break;
+            case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
+                usbn_clk_ctl.s.p_c_sel = 1;
+                break;
+            case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
+                usbn_clk_ctl.s.p_c_sel = 2;
+                break;
+        }
+    }
+    else
+    {
+        /* The USB port uses a 12MHz crystal as clock source
+            at USB_XO and USB_XI */
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
+        {
+            usbn_clk_ctl.cn31xx.p_rclk  = 1; /* From CN31XX,CN30XX manual */
+            usbn_clk_ctl.cn31xx.p_xenbn = 1;
+        }
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
+            usbn_clk_ctl.cn56xx.p_rtype = 0; /* From CN56XX,CN50XX manual */
+        else
+            usbn_clk_ctl.cn52xx.p_rtype = 0; /* From CN52XX manual */
+
+        usbn_clk_ctl.s.p_c_sel = 0;
+    }
+    /* 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
+        setting USBN0/1_CLK_CTL[ENABLE] = 1.  Divide the core clock down such
+        that USB is as close as possible to 125Mhz */
+    {
+        int divisor = (cvmx_sysinfo_get()->cpu_clock_hz+125000000-1)/125000000;
+        if (divisor < 4)  /* Lower than 4 doesn't seem to work properly */
+            divisor = 4;
+        usbn_clk_ctl.s.divide = divisor;
+        usbn_clk_ctl.s.divide2 = 0;
+    }
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
+    usbn_clk_ctl.s.hclk_rst = 1;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    /* 2e.  Wait 64 core-clock cycles for HCLK to stabilize */
+    cvmx_wait(64);
+    /* 3. Program the power-on reset field in the USBN clock-control register:
+        USBN_CLK_CTL[POR] = 0 */
+    usbn_clk_ctl.s.por = 0;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    /* 4. Wait 1 ms for PHY clock to start */
+    cvmx_wait_usec(1000);
+    /* 5. Program the Reset input from automatic test equipment field in the
+        USBP control and status register: USBN_USBP_CTL_STATUS[ATE_RESET] = 1 */
+    usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
+    usbn_usbp_ctl_status.s.ate_reset = 1;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
+                           usbn_usbp_ctl_status.u64);
+    /* 6. Wait 10 cycles */
+    cvmx_wait(10);
+    /* 7. Clear ATE_RESET field in the USBN clock-control register:
+        USBN_USBP_CTL_STATUS[ATE_RESET] = 0 */
+    usbn_usbp_ctl_status.s.ate_reset = 0;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
+                           usbn_usbp_ctl_status.u64);
+    /* 8. Program the PHY reset field in the USBN clock-control register:
+        USBN_CLK_CTL[PRST] = 1 */
+    usbn_clk_ctl.s.prst = 1;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    /* 9. Program the USBP control and status register to select host or
+        device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
+        device */
+    if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE)
+    {
+        usbn_usbp_ctl_status.s.hst_mode = 1;
+        usbn_usbp_ctl_status.s.dm_pulld = 0;
+        usbn_usbp_ctl_status.s.dp_pulld = 0;
+    }
+    else
+    {
+        usbn_usbp_ctl_status.s.hst_mode = 0;
+    }
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
+                           usbn_usbp_ctl_status.u64);
+    /* 10. Wait 1 µs */
+    cvmx_wait_usec(1);
+    /* 11. Program the hreset_n field in the USBN clock-control register:
+        USBN_CLK_CTL[HRST] = 1 */
+    usbn_clk_ctl.s.hrst = 1;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    /* 12. Proceed to USB core initialization */
+    usbn_clk_ctl.s.enable = 1;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    cvmx_wait_usec(1);
+
+    /* USB Core Initialization */
+
+    /* 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
+        determine USB core configuration parameters. */
+    /* Nothing needed */
+    /* 2. Program the following fields in the global AHB configuration
+        register (USBC_GAHBCFG)
+        DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
+        Burst length, USBC_GAHBCFG[HBSTLEN] = 0
+        Nonperiodic TxFIFO empty level (slave mode only),
+        USBC_GAHBCFG[NPTXFEMPLVL]
+        Periodic TxFIFO empty level (slave mode only),
+        USBC_GAHBCFG[PTXFEMPLVL]
+        Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 */
+    {
+        cvmx_usbcx_gahbcfg_t usbcx_gahbcfg;
+        usbcx_gahbcfg.u32 = 0;
+        usbcx_gahbcfg.s.dmaen = !OCTEON_IS_MODEL(OCTEON_CN31XX);
+        /* If we are using DMA, start off with 8 idle channels. Without
+            DMA we emulate a single channel */
+        if (usbcx_gahbcfg.s.dmaen)
+            usb->idle_hardware_channels = 0xff;
+        else
+            usb->idle_hardware_channels = 0x1;
+        usbcx_gahbcfg.s.hbstlen = 0;
+        usbcx_gahbcfg.s.nptxfemplvl = 1;
+        usbcx_gahbcfg.s.ptxfemplvl = 1;
+        usbcx_gahbcfg.s.glblintrmsk = 1;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
+                               usbcx_gahbcfg.u32);
+    }
+    /* 3. Program the following fields in USBC_GUSBCFG register.
+        HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
+        ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
+        USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
+        PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 */
+    {
+        cvmx_usbcx_gusbcfg_t usbcx_gusbcfg;
+        usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
+        usbcx_gusbcfg.s.toutcal = 0;
+        usbcx_gusbcfg.s.ddrsel = 0;
+        usbcx_gusbcfg.s.usbtrdtim = 0x5;
+        usbcx_gusbcfg.s.phylpwrclksel = 0;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
+                               usbcx_gusbcfg.u32);
+    }
+    /* 4. The software must unmask the following bits in the USBC_GINTMSK
+        register.
+        OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
+        Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 */
+    {
+        cvmx_usbcx_gintmsk_t usbcx_gintmsk;
+        cvmx_usbcx_hcintmskx_t usbc_hcintmsk;
+        cvmx_usbcx_haintmsk_t usbc_haintmsk;
+        int channel;
+
+        usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
+        usbcx_gintmsk.s.otgintmsk = 1;
+        usbcx_gintmsk.s.modemismsk = 1;
+        usbcx_gintmsk.s.hchintmsk = 1;
+        usbcx_gintmsk.s.sofmsk = 0;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
+                               usbcx_gintmsk.u32);
+
+        /* Enable the channel halt interrupt */
+        usbc_hcintmsk.u32 = 0;
+        usbc_hcintmsk.s.chhltdmsk = 1;
+        for (channel=0; channel<8; channel++)
+            if (usb->idle_hardware_channels & (1<<channel))
+                __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
+
+        /* Enable the channel interrupt to propagate */
+        usbc_haintmsk.u32 = 0;
+        usbc_haintmsk.s.haintmsk = usb->idle_hardware_channels;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
+    }
+
+    if ((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE) == 0)
+    {
+        /* Host Port Initialization */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: USB%d is in host mode\n", __FUNCTION__, usb->index);
+
+        /* 1. Program the host-port interrupt-mask field to unmask,
+            USBC_GINTMSK[PRTINT] = 1 */
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
+                        prtintmsk, 1);
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
+                        disconnintmsk, 1);
+        /* 2. Program the USBC_HCFG register to select full-speed host or
+            high-speed host. */
+        {
+            cvmx_usbcx_hcfg_t usbcx_hcfg;
+            usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
+            usbcx_hcfg.s.fslssupp = 0;
+            usbcx_hcfg.s.fslspclksel = 0;
+            __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
+        }
+        /* 3. Program the port power bit to drive VBUS on the USB,
+            USBC_HPRT[PRTPWR] = 1 */
+        USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtpwr, 1);
+
+        /* Steps 4-15 from the manual are done later in the port enable */
+    }
+    else
+    {
+        /* Device Port Initialization */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: USB%d is in device mode\n", __FUNCTION__, usb->index);
+
+        /* 1. Program the following fields in the USBC0/1_DCFG register:
+            Device speed, USBC0/1_DCFG[DEVSPD] = 0 (high speed)
+            Non-zero-length status OUT handshake, USBC0/1_DCFG[NZSTSOUTHSHK]=0
+            Periodic frame interval (if periodic endpoints are supported),
+            USBC0/1_DCFG[PERFRINT] = 1 */
+        USB_SET_FIELD32(CVMX_USBCX_DCFG(usb->index), cvmx_usbcx_dcfg_t,
+                        devspd, 0);
+        USB_SET_FIELD32(CVMX_USBCX_DCFG(usb->index), cvmx_usbcx_dcfg_t,
+                        nzstsouthshk, 0);
+        USB_SET_FIELD32(CVMX_USBCX_DCFG(usb->index), cvmx_usbcx_dcfg_t,
+                        perfrint, 1);
+
+        /* 2. Program the USBC0/1_GINTMSK register to unmask the following
+            interrupts:
+            USB Reset, USBC0/1_GINTMSK[USBRSTMSK] = 1
+            Enumeration done, USBC0/1_GINTMSK[ENUMDONEMSK] = 1
+            SOF, USBC0/1_GINTMSK[SOFMSK] = 1 */
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
+                        usbrstmsk, 1);
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
+                        enumdonemsk, 1);
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
+                        sofmsk, 1);
+
+        /* 3. Wait for the USBC0/1_GINTSTS[USBRESET] interrupt, which
+            indicates a reset has been detected on the USB and lasts for
+            about 10 ms. On receiving this interrupt, the application must
+            perform the steps listed in Section 22.6.1.1, "Initialization on
+            USB Reset". */
+        /* Handled in cvmx_poll() usbc_gintsts.s.usbrst processing */
+
+        /* 4. Wait for the USBC0/1_GINTSTS[ENUMERATIONDONE] interrupt, which
+            indicates the end of reset on the USB. On receiving this interrupt,
+            the application must read the USBC0/1_DSTS register to determine
+            the enumeration speed and perform the steps listed in Section
+            22.6.1.2, "Initialization on Enumeration Completion". */
+        /* Handled in cvmx_poll() usbc_gintsts.s.enumdone processing */
+    }
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Shutdown a USB port after a call to cvmx_usb_initialize().
+ * The port should be disabled with all pipes closed when this
+ * function is called.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_shutdown(cvmx_usb_state_t *state)
+{
+    cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+
+    /* Make sure all pipes are closed */
+    if (usb->idle_pipes.head ||
+        usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
+        usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
+        usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
+        usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
+        CVMX_USB_RETURN(CVMX_USB_BUSY);
+
+    /* Disable the clocks and put them in power on reset */
+    usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
+    usbn_clk_ctl.s.enable = 1;
+    usbn_clk_ctl.s.por = 1;
+    usbn_clk_ctl.s.hclk_rst = 1;
+    usbn_clk_ctl.s.prst = 0;
+    usbn_clk_ctl.s.hrst = 0;
+    __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
+                           usbn_clk_ctl.u64);
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Enable a USB port. After this call succeeds, the USB port is
+ * online and servicing requests.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_enable(cvmx_usb_state_t *state)
+{
+    cvmx_usbcx_ghwcfg3_t usbcx_ghwcfg3;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
+
+    /* If the port is already enabled the just return. We don't need to do
+        anything */
+    if (usb->usbcx_hprt.s.prtena)
+        CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+
+    /* If there is nothing plugged into the port then fail immediately */
+    if (!usb->usbcx_hprt.s.prtconnsts)
+    {
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: USB%d Nothing plugged into the port\n", __FUNCTION__, usb->index);
+        CVMX_USB_RETURN(CVMX_USB_TIMEOUT);
+    }
+
+    /* Program the port reset bit to start the reset process */
+    USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtrst, 1);
+
+    /* Wait at least 50ms (high speed), or 10ms (full speed) for the reset
+        process to complete. */
+    cvmx_wait_usec(50000);
+
+    /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
+    USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtrst, 0);
+
+    /* Wait for the USBC_HPRT[PRTENA]. */
+    if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t,
+                              prtena, ==, 1, 100000))
+    {
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: Timeout waiting for the port to finish reset\n",
+                         __FUNCTION__);
+        CVMX_USB_RETURN(CVMX_USB_TIMEOUT);
+    }
+
+    /* Read the port speed field to get the enumerated speed, USBC_HPRT[PRTSPD]. */
+    usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+        cvmx_dprintf("%s: USB%d is in %s speed mode\n", __FUNCTION__, usb->index,
+                     (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH) ? "high" :
+                     (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_FULL) ? "full" :
+                     "low");
+
+    usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
+
+    /* 13. Program the USBC_GRXFSIZ register to select the size of the receive
+        FIFO (25%). */
+    USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz_t,
+                    rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
+    /* 14. Program the USBC_GNPTXFSIZ register to select the size and the
+        start address of the non- periodic transmit FIFO for nonperiodic
+        transactions (50%). */
+    {
+        cvmx_usbcx_gnptxfsiz_t siz;
+        siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
+        siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
+        siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
+    }
+    /* 15. Program the USBC_HPTXFSIZ register to select the size and start
+        address of the periodic transmit FIFO for periodic transactions (25%). */
+    {
+        cvmx_usbcx_hptxfsiz_t siz;
+        siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
+        siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
+        siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
+    }
+    /* Flush all FIFOs */
+    USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, txfnum, 0x10);
+    USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, txfflsh, 1);
+    CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t,
+                          txfflsh, ==, 0, 100);
+    USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, rxfflsh, 1);
+    CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t,
+                          rxfflsh, ==, 0, 100);
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Disable a USB port. After this call the USB port will not
+ * generate data transfers and will not generate events.
+ * Transactions in process will fail and call their
+ * associated callbacks.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_disable(cvmx_usb_state_t *state)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    /* Disable the port */
+    USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtena, 1);
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Get the current state of the USB port. Use this call to
+ * determine if the usb port has anything connected, is enabled,
+ * or has some sort of error condition. The return value of this
+ * call has "changed" bits to signal of the value of some fields
+ * have changed between calls. These "changed" fields are based
+ * on the last call to cvmx_usb_set_status(). In order to clear
+ * them, you must update the status through cvmx_usb_set_status().
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Port status information
+ */
+cvmx_usb_port_status_t cvmx_usb_get_status(cvmx_usb_state_t *state)
+{
+    cvmx_usbcx_hprt_t usbc_hprt;
+    cvmx_usb_port_status_t result;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    memset(&result, 0, sizeof(result));
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+
+    usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
+    result.port_enabled = usbc_hprt.s.prtena;
+    result.port_over_current = usbc_hprt.s.prtovrcurract;
+    result.port_powered = usbc_hprt.s.prtpwr;
+    result.port_speed = usbc_hprt.s.prtspd;
+    result.connected = usbc_hprt.s.prtconnsts;
+    result.connect_change = (result.connected != usb->port_status.connected);
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLS))
+        cvmx_dprintf("%*s%s: returned port enabled=%d, over_current=%d, powered=%d, speed=%d, connected=%d, connect_change=%d\n",
+                     2*(--usb->indent), "", __FUNCTION__,
+                     result.port_enabled,
+                     result.port_over_current,
+                     result.port_powered,
+                     result.port_speed,
+                     result.connected,
+                     result.connect_change);
+    return result;
+}
+
+
+/**
+ * Set the current state of the USB port. The status is used as
+ * a reference for the "changed" bits returned by
+ * cvmx_usb_get_status(). Other than serving as a reference, the
+ * status passed to this function is not used. No fields can be
+ * changed through this call.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param port_status
+ *               Port status to set, most like returned by cvmx_usb_get_status()
+ */
+void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t port_status)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    usb->port_status = port_status;
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * @INTERNAL
+ * Convert a USB transaction into a handle
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param transaction
+ *               Transaction to get handle for
+ *
+ * @return Handle
+ */
+static inline int __cvmx_usb_get_submit_handle(cvmx_usb_internal_state_t *usb,
+                                        cvmx_usb_transaction_t *transaction)
+{
+    return ((unsigned long)transaction - (unsigned long)usb->transaction) /
+            sizeof(*transaction);
+}
+
+
+/**
+ * @INTERNAL
+ * Convert a USB pipe into a handle
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe   Pipe to get handle for
+ *
+ * @return Handle
+ */
+static inline int __cvmx_usb_get_pipe_handle(cvmx_usb_internal_state_t *usb,
+                                        cvmx_usb_pipe_t *pipe)
+{
+    return ((unsigned long)pipe - (unsigned long)usb->pipe) / sizeof(*pipe);
+}
+
+
+/**
+ * Open a virtual pipe between the host and a USB device. A pipe
+ * must be opened before data can be transferred between a device
+ * and Octeon.
+ *
+ * @param state      USB device state populated by
+ *                   cvmx_usb_initialize().
+ * @param flags      Optional pipe flags defined in
+ *                   cvmx_usb_pipe_flags_t.
+ * @param device_addr
+ *                   USB device address to open the pipe to
+ *                   (0-127).
+ * @param endpoint_num
+ *                   USB endpoint number to open the pipe to
+ *                   (0-15).
+ * @param device_speed
+ *                   The speed of the device the pipe is going
+ *                   to. This must match the device's speed,
+ *                   which may be different than the port speed.
+ * @param max_packet The maximum packet length the device can
+ *                   transmit/receive (low speed=0-8, full
+ *                   speed=0-1023, high speed=0-1024). This value
+ *                   comes from the stadnard endpoint descriptor
+ *                   field wMaxPacketSize bits <10:0>.
+ * @param transfer_type
+ *                   The type of transfer this pipe is for.
+ * @param transfer_dir
+ *                   The direction the pipe is in. This is not
+ *                   used for control pipes.
+ * @param interval   For ISOCHRONOUS and INTERRUPT transfers,
+ *                   this is how often the transfer is scheduled
+ *                   for. All other transfers should specify
+ *                   zero. The units are in frames (8000/sec at
+ *                   high speed, 1000/sec for full speed).
+ * @param multi_count
+ *                   For high speed devices, this is the maximum
+ *                   allowed number of packet per microframe.
+ *                   Specify zero for non high speed devices. This
+ *                   value comes from the stadnard endpoint descriptor
+ *                   field wMaxPacketSize bits <12:11>.
+ * @param hub_device_addr
+ *                   Hub device address this device is connected
+ *                   to. Devices connected directly to Octeon
+ *                   use zero. This is only used when the device
+ *                   is full/low speed behind a high speed hub.
+ *                   The address will be of the high speed hub,
+ *                   not and full speed hubs after it.
+ * @param hub_port   Which port on the hub the device is
+ *                   connected. Use zero for devices connected
+ *                   directly to Octeon. Like hub_device_addr,
+ *                   this is only used for full/low speed
+ *                   devices behind a high speed hub.
+ *
+ * @return A non negative value is a pipe handle. Negative
+ *         values are failure codes from cvmx_usb_status_t.
+ */
+int cvmx_usb_open_pipe(cvmx_usb_state_t *state, cvmx_usb_pipe_flags_t flags,
+                       int device_addr, int endpoint_num,
+                       cvmx_usb_speed_t device_speed, int max_packet,
+                       cvmx_usb_transfer_t transfer_type,
+                       cvmx_usb_direction_t transfer_dir, int interval,
+                       int multi_count, int hub_device_addr, int hub_port)
+{
+    cvmx_usb_pipe_t *pipe;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("0x%x", flags);
+    CVMX_USB_LOG_PARAM("%d", device_addr);
+    CVMX_USB_LOG_PARAM("%d", endpoint_num);
+    CVMX_USB_LOG_PARAM("%d", device_speed);
+    CVMX_USB_LOG_PARAM("%d", max_packet);
+    CVMX_USB_LOG_PARAM("%d", transfer_type);
+    CVMX_USB_LOG_PARAM("%d", transfer_dir);
+    CVMX_USB_LOG_PARAM("%d", interval);
+    CVMX_USB_LOG_PARAM("%d", multi_count);
+    CVMX_USB_LOG_PARAM("%d", hub_device_addr);
+    CVMX_USB_LOG_PARAM("%d", hub_port);
+
+    if (cvmx_unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(device_speed > CVMX_USB_SPEED_LOW))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((max_packet <= 0) || (max_packet > 1024)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
+        (transfer_dir != CVMX_USB_DIRECTION_IN)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(interval < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(multi_count < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
+        (multi_count != 0)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    /* Find a free pipe */
+    pipe = usb->free_pipes.head;
+    if (!pipe)
+        CVMX_USB_RETURN(CVMX_USB_NO_MEMORY);
+    __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
+    pipe->flags = flags | __CVMX_USB_PIPE_FLAGS_OPEN;
+    if ((device_speed == CVMX_USB_SPEED_HIGH) &&
+        (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
+        (transfer_type == CVMX_USB_TRANSFER_BULK))
+        pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
+    pipe->device_addr = device_addr;
+    pipe->endpoint_num = endpoint_num;
+    pipe->device_speed = device_speed;
+    pipe->max_packet = max_packet;
+    pipe->transfer_type = transfer_type;
+    pipe->transfer_dir = transfer_dir;
+    /* All pipes use interval to rate limit NAK processing. Force an interval
+        if one wasn't supplied */
+    if (!interval)
+        interval = 1;
+    if (device_speed == CVMX_USB_SPEED_HIGH)
+        pipe->interval = (uint64_t)interval * cvmx_sysinfo_get()->cpu_clock_hz / 8000;
+    else
+        pipe->interval = (uint64_t)interval * cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+    pipe->multi_count = multi_count;
+    pipe->hub_device_addr = hub_device_addr;
+    pipe->hub_port = hub_port;
+    pipe->pid_toggle = 0;
+    pipe->next_tx_cycle = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT) + pipe->interval;
+    pipe->split_sc_frame = -1;
+    __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
+
+    /* We don't need to tell the hardware about this pipe yet since
+        it doesn't have any submitted requests */
+
+    CVMX_USB_RETURN(__cvmx_usb_get_pipe_handle(usb, pipe));
+}
+
+
+/**
+ * @INTERNAL
+ * Perform channel specific setup for Control transactions. All
+ * the generic stuff will already have been done in
+ * __cvmx_usb_start_channel()
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usb_initialize().
+ * @param channel Channel to setup
+ * @param pipe    Pipe for control transaction
+ */
+static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
+                                             int channel,
+                                             cvmx_usb_pipe_t *pipe)
+{
+    cvmx_usb_transaction_t *transaction = pipe->head;
+    cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
+    int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
+    cvmx_usbcx_hctsizx_t usbc_hctsiz;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%d", channel);
+    CVMX_USB_LOG_PARAM("%p", pipe);
+
+    usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
+
+    switch (transaction->stage)
+    {
+        case CVMX_USB_STAGE_NON_CONTROL:
+        case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
+            cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
+            break;
+        case CVMX_USB_STAGE_SETUP:
+            usbc_hctsiz.s.pid = 3; /* Setup */
+            usbc_hctsiz.s.xfersize = sizeof(*header);
+            /* All Control operations start with a setup going OUT */
+            USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
+            /* Setup send the control header instead of the buffer data. The
+                buffer data will be used in the next stage */
+            __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
+            break;
+        case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
+            usbc_hctsiz.s.pid = 3; /* Setup */
+            usbc_hctsiz.s.xfersize = 0;
+            /* All Control operations start with a setup going OUT */
+            USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
+            USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
+            break;
+        case CVMX_USB_STAGE_DATA:
+            usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
+            if (__cvmx_usb_pipe_needs_split(usb, pipe))
+            {
+                usbc_hctsiz.s.xfersize = (header->s.request_type & 0x80) ? 0 : bytes_to_transfer;
+                if (usbc_hctsiz.s.xfersize > pipe->max_packet)
+                    usbc_hctsiz.s.xfersize = pipe->max_packet;
+            }
+            else
+                usbc_hctsiz.s.xfersize = bytes_to_transfer;
+            USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
+                            cvmx_usbcx_hccharx_t, epdir,
+                            ((header->s.request_type & 0x80) ?
+                             CVMX_USB_DIRECTION_IN :
+                             CVMX_USB_DIRECTION_OUT));
+            break;
+        case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
+            usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
+            usbc_hctsiz.s.xfersize = (header->s.request_type & 0x80) ? bytes_to_transfer : 0;
+            USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
+                            cvmx_usbcx_hccharx_t, epdir,
+                            ((header->s.request_type & 0x80) ?
+                             CVMX_USB_DIRECTION_IN :
+                             CVMX_USB_DIRECTION_OUT));
+            USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
+            break;
+        case CVMX_USB_STAGE_STATUS:
+            usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
+            usbc_hctsiz.s.xfersize = 0;
+            USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
+                            ((header->s.request_type & 0x80) ?
+                             CVMX_USB_DIRECTION_OUT :
+                             CVMX_USB_DIRECTION_IN));
+            break;
+        case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
+            usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
+            usbc_hctsiz.s.xfersize = 0;
+            USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
+                            ((header->s.request_type & 0x80) ?
+                             CVMX_USB_DIRECTION_OUT :
+                             CVMX_USB_DIRECTION_IN));
+            USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
+            break;
+    }
+
+    /* Set the number of packets needed for this transfer */
+    usbc_hctsiz.s.pktcnt = (usbc_hctsiz.s.xfersize + pipe->max_packet - 1) / pipe->max_packet;
+    if (!usbc_hctsiz.s.pktcnt)
+        usbc_hctsiz.s.pktcnt = 1;
+
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * @INTERNAL
+ * Start a channel to perform the pipe's head transaction
+ *
+ * @param usb     USB device state populated by
+ *                cvmx_usb_initialize().
+ * @param channel Channel to setup
+ * @param pipe    Pipe to start
+ */
+static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
+                                     int channel,
+                                     cvmx_usb_pipe_t *pipe)
+{
+    cvmx_usb_transaction_t *transaction = pipe->head;
+    cvmx_usbcx_hfnum_t usbc_hfnum;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%d", channel);
+    CVMX_USB_LOG_PARAM("%p", pipe);
+
+    if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS) ||
+        (pipe->flags & CVMX_USB_PIPE_FLAGS_DEBUG_TRANSFERS)))
+        cvmx_dprintf("%s: Channel %d started. Pipe %d transaction %d stage %d\n",
+                     __FUNCTION__, channel, __cvmx_usb_get_pipe_handle(usb, pipe),
+                     __cvmx_usb_get_submit_handle(usb, transaction),
+                     transaction->stage);
+
+    /* Make sure all writes to the DMA region get flushed */
+    CVMX_SYNCW;
+
+    /* Read the current frame number for use with split, INTERRUPT,  and ISO
+        transactions */
+    usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
+
+    /* Attach the channel to the pipe */
+    usb->pipe_for_channel[channel] = pipe;
+    pipe->channel = channel;
+    pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
+
+    /* Mark this channel as in use */
+    usb->idle_hardware_channels &= ~(1<<channel);
+
+    /* Enable the channel interrupt bits */
+    {
+        cvmx_usbcx_hcintx_t usbc_hcint;
+
+        /* Clear all channel status bits */
+        usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
+    }
+
+    /* Setup the locations the DMA engines use  */
+    {
+        uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
+        if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
+            dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
+        __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
+        __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
+    }
+
+    /* Setup both the size of the transfer and the SPLIT characteristics */
+    {
+        cvmx_usbcx_hcspltx_t usbc_hcsplt = {.u32 = 0};
+        cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = 0};
+        int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
+
+        /* ISOCHRONOUS transactions store each individual transfer size in the
+            packet structure, not the global buffer_length */
+        if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
+            bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
+
+        /* We need to do split transactions when we are talking to non high
+            speed devices that are behind a high speed hub */
+        if (__cvmx_usb_pipe_needs_split(usb, pipe))
+        {
+            /* On the start split phase (stage is even) record the frame number we
+                will need to send the split complete. We only store the lower two bits
+                since the time ahead can only be two frames */
+            if ((transaction->stage&1) == 0)
+            {
+                if (transaction->type == CVMX_USB_TRANSFER_BULK)
+                    pipe->split_sc_frame = (usbc_hfnum.s.frnum + 1) & 0x7f;
+                else
+                    pipe->split_sc_frame = (usbc_hfnum.s.frnum + 2) & 0x7f;
+            }
+            else
+                pipe->split_sc_frame = -1;
+
+            usbc_hcsplt.s.spltena = 1;
+            usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
+            usbc_hcsplt.s.prtaddr = pipe->hub_port;
+            usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
+
+            /* SPLIT transactions can only ever transmit one data packet so
+                limit the transfer size to the max packet size */
+            if (bytes_to_transfer > pipe->max_packet)
+                bytes_to_transfer = pipe->max_packet;
+
+            /* ISOCHRONOUS OUT splits are unique in that they limit
+                data transfers to 188 byte chunks representing the
+                begin/middle/end of the data or all */
+            if (!usbc_hcsplt.s.compsplt &&
+                (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
+                (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS))
+            {
+                /* See if we've started this tranfer and sent data */
+                if (transaction->actual_bytes == 0)
+                {
+                    /* Nothing sent yet, this is either a begin or the
+                        entire payload */
+                    if (bytes_to_transfer <= 188)
+                        usbc_hcsplt.s.xactpos = 3; /* Entire payload in one go */
+                    else
+                        usbc_hcsplt.s.xactpos = 2; /* First part of payload */
+                }
+                else
+                {
+                    /* Continuing the previous data, we must either be
+                        in the middle or at the end */
+                    if (bytes_to_transfer <= 188)
+                        usbc_hcsplt.s.xactpos = 1; /* End of payload */
+                    else
+                        usbc_hcsplt.s.xactpos = 0; /* Middle of payload */
+                }
+                /* Again, the transfer size is limited to 188 bytes */
+                if (bytes_to_transfer > 188)
+                    bytes_to_transfer = 188;
+            }
+        }
+
+        usbc_hctsiz.s.xfersize = bytes_to_transfer;
+        usbc_hctsiz.s.pktcnt = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
+        if (!usbc_hctsiz.s.pktcnt)
+            usbc_hctsiz.s.pktcnt = 1;
+
+        /* Update the DATA0/DATA1 toggle */
+        usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
+        /* High speed pipes may need a hardware ping before they start */
+        if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
+            usbc_hctsiz.s.dopng = 1;
+
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
+    }
+
+    /* Setup the Host Channel Characteristics Register */
+    {
+        cvmx_usbcx_hccharx_t usbc_hcchar = {.u32 = 0};
+
+        /* Make all transfers start on the next frame and not this one. This
+            way the time we spend processing doesn't affect USB timing */
+        usbc_hcchar.s.oddfrm = !(usbc_hfnum.s.frnum&1);
+
+        /* Set the number of back to back packets allowed by this endpoint.
+            Split transactions interpret "ec" as the number of immediate
+            retries of failure. These retries happen too quickly, so we
+            disable these entirely for splits */
+        if (__cvmx_usb_pipe_needs_split(usb, pipe))
+            usbc_hcchar.s.ec = 1;
+        else if (pipe->multi_count < 1)
+            usbc_hcchar.s.ec = 1;
+        else if (pipe->multi_count > 3)
+            usbc_hcchar.s.ec = 3;
+        else
+            usbc_hcchar.s.ec = pipe->multi_count;
+
+        /* Set the rest of the endpoint specific settings */
+        usbc_hcchar.s.devaddr = pipe->device_addr;
+        usbc_hcchar.s.eptype = transaction->type;
+        usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
+        usbc_hcchar.s.epdir = pipe->transfer_dir;
+        usbc_hcchar.s.epnum = pipe->endpoint_num;
+        usbc_hcchar.s.mps = pipe->max_packet;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
+    }
+
+    /* Do transaction type specific fixups as needed */
+    switch (transaction->type)
+    {
+        case CVMX_USB_TRANSFER_CONTROL:
+            __cvmx_usb_start_channel_control(usb, channel, pipe);
+            break;
+        case CVMX_USB_TRANSFER_BULK:
+        case CVMX_USB_TRANSFER_INTERRUPT:
+            break;
+        case CVMX_USB_TRANSFER_ISOCHRONOUS:
+            if (!__cvmx_usb_pipe_needs_split(usb, pipe))
+            {
+                /* ISO transactions require differnet PIDs depending on direction
+                    and how many packets are needed */
+                if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)
+                {
+                    if (pipe->multi_count < 2) /* Need DATA0 */
+                        USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), cvmx_usbcx_hctsizx_t, pid, 0);
+                    else /* Need MDATA */
+                        USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), cvmx_usbcx_hctsizx_t, pid, 3);
+                }
+            }
+            break;
+    }
+    {
+        cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
+        transaction->xfersize = usbc_hctsiz.s.xfersize;
+        transaction->pktcnt = usbc_hctsiz.s.pktcnt;
+    }
+    USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, chena, 1);
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * @INTERNAL
+ * Find a pipe that is ready to be scheduled to hardware.
+ *
+ * @param list       Pipe list to search
+ * @param usbc_hfnum Current USB frame number
+ * @param current_cycle
+ *                   Cycle counter to use as a time reference.
+ *
+ * @return Pipe or NULL if none are ready
+ */
+static cvmx_usb_pipe_t *__cvmx_usb_find_ready_pipe(cvmx_usb_pipe_list_t *list, cvmx_usbcx_hfnum_t usbc_hfnum, uint64_t current_cycle)
+{
+    cvmx_usb_pipe_t *pipe = list->head;
+    while (pipe)
+    {
+        if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
+            (pipe->next_tx_cycle <= current_cycle) &&
+            ((pipe->split_sc_frame == -1) || ((((int)usbc_hfnum.s.frnum - (int)pipe->split_sc_frame) & 0x7f) < 0x40)))
+        {
+            CVMX_PREFETCH(pipe, 128);
+            CVMX_PREFETCH(pipe->head, 0);
+            return pipe;
+        }
+        pipe = pipe->next;
+    }
+    return NULL;
+}
+
+
+/**
+ * @INTERNAL
+ * Called whenever a pipe might need to be scheduled to the
+ * hardware.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param is_sof True if this schedule was called on a SOF interrupt.
+ */
+static void __cvmx_usb_schedule(cvmx_usb_internal_state_t *usb, int is_sof)
+{
+    int channel;
+    cvmx_usb_pipe_t *pipe;
+    cvmx_usbcx_hfnum_t usbc_hfnum;
+    uint64_t current_cycle = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+
+    usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
+
+    while (usb->idle_hardware_channels)
+    {
+        /* Find an idle channel */
+        CVMX_CLZ(channel, usb->idle_hardware_channels);
+        channel = 31 - channel;
+        if (cvmx_unlikely(channel > 7))
+        {
+            if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+                cvmx_dprintf("%s: Idle hardware channels has a channel higher than 7. This is wrong\n", __FUNCTION__);
+            break;
+        }
+
+        /* Find a pipe needing service */
+        pipe = NULL;
+        if (is_sof)
+        {
+            /* Only process periodic pipes on SOF interrupts. This way we are
+                sure that the periodic data is sent in the beginning of the
+                frame */
+            pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usbc_hfnum, current_cycle);
+            if (cvmx_likely(!pipe))
+                pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usbc_hfnum, current_cycle);
+        }
+        if (cvmx_likely(!pipe))
+        {
+            pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usbc_hfnum, current_cycle);
+            if (cvmx_likely(!pipe))
+                pipe = __cvmx_usb_find_ready_pipe(usb->active_pipes + CVMX_USB_TRANSFER_BULK, usbc_hfnum, current_cycle);
+        }
+        if (!pipe)
+            break;
+
+        CVMX_USB_LOG_PARAM("%d", channel);
+        CVMX_USB_LOG_PARAM("%p", pipe);
+
+        if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS) ||
+            (pipe->flags & CVMX_USB_PIPE_FLAGS_DEBUG_TRANSFERS)))
+        {
+            cvmx_usb_transaction_t *transaction = pipe->head;
+            const cvmx_usb_control_header_t *header = (transaction->control_header) ? cvmx_phys_to_ptr(transaction->control_header) : NULL;
+            const char *dir = (pipe->transfer_dir == CVMX_USB_DIRECTION_IN) ? "IN" : "OUT";
+            const char *type;
+            switch (pipe->transfer_type)
+            {
+                case CVMX_USB_TRANSFER_CONTROL:
+                    type = "SETUP";
+                    dir = (header->s.request_type & 0x80) ? "IN" : "OUT";
+                    break;
+                case CVMX_USB_TRANSFER_ISOCHRONOUS:
+                    type = "ISOCHRONOUS";
+                    break;
+                case CVMX_USB_TRANSFER_BULK:
+                    type = "BULK";
+                    break;
+                default: /* CVMX_USB_TRANSFER_INTERRUPT */
+                    type = "INTERRUPT";
+                    break;
+            }
+            cvmx_dprintf("%s: Starting pipe %d, transaction %d on channel %d. %s %s len=%d header=0x%llx\n",
+                         __FUNCTION__, __cvmx_usb_get_pipe_handle(usb, pipe),
+                         __cvmx_usb_get_submit_handle(usb, transaction),
+                         channel, type, dir,
+                         transaction->buffer_length,
+                         (header) ? (unsigned long long)header->u64 : 0ull);
+        }
+        __cvmx_usb_start_channel(usb, channel, pipe);
+    }
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * @INTERNAL
+ * Call a user's callback for a specific reason.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe   Pipe the callback is for or NULL
+ * @param transaction
+ *               Transaction the callback is for or NULL
+ * @param reason Reason this callback is being called
+ * @param complete_code
+ *               Completion code for the transaction, if any
+ */
+static void __cvmx_usb_perform_callback(cvmx_usb_internal_state_t *usb,
+                                        cvmx_usb_pipe_t *pipe,
+                                        cvmx_usb_transaction_t *transaction,
+                                        cvmx_usb_callback_t reason,
+                                        cvmx_usb_complete_t complete_code)
+{
+    cvmx_usb_callback_func_t callback = usb->callback[reason];
+    void *user_data = usb->callback_data[reason];
+    int submit_handle = -1;
+    int pipe_handle = -1;
+    int bytes_transferred = 0;
+
+    if (pipe)
+        pipe_handle = __cvmx_usb_get_pipe_handle(usb, pipe);
+
+    if (transaction)
+    {
+        submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
+        bytes_transferred = transaction->actual_bytes;
+        /* Transactions are allowed to override the default callback */
+        if ((reason == CVMX_USB_CALLBACK_TRANSFER_COMPLETE) && transaction->callback)
+        {
+            callback = transaction->callback;
+            user_data = transaction->callback_data;
+        }
+    }
+
+    if (!callback)
+        return;
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLBACKS))
+        cvmx_dprintf("%*s%s: calling callback %p(usb=%p, complete_code=%s, "
+                     "pipe_handle=%d, submit_handle=%d, bytes_transferred=%d, user_data=%p);\n",
+                     2*usb->indent, "", __FUNCTION__, callback, usb,
+                     __cvmx_usb_complete_to_string(complete_code),
+                     pipe_handle, submit_handle, bytes_transferred, user_data);
+
+    callback((cvmx_usb_state_t *)usb, reason, complete_code, pipe_handle, submit_handle,
+             bytes_transferred, user_data);
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLBACKS))
+        cvmx_dprintf("%*s%s: callback %p complete\n", 2*usb->indent, "",
+                      __FUNCTION__, callback);
+}
+
+
+/**
+ * @INTERNAL
+ * Signal the completion of a transaction and free it. The
+ * transaction will be removed from the pipe transaction list.
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe   Pipe the transaction is on
+ * @param transaction
+ *               Transaction that completed
+ * @param complete_code
+ *               Completion code
+ */
+static void __cvmx_usb_perform_complete(cvmx_usb_internal_state_t * usb,
+                                        cvmx_usb_pipe_t *pipe,
+                                        cvmx_usb_transaction_t *transaction,
+                                        cvmx_usb_complete_t complete_code)
+{
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%p", pipe);
+    CVMX_USB_LOG_PARAM("%p", transaction);
+    CVMX_USB_LOG_PARAM("%d", complete_code);
+
+    /* Isochronous transactions need extra processing as they might not be done
+        after a single data transfer */
+    if (cvmx_unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS))
+    {
+        /* Update the number of bytes transfered in this ISO packet */
+        transaction->iso_packets[0].length = transaction->actual_bytes;
+        transaction->iso_packets[0].status = complete_code;
+
+        /* If there are more ISOs pending and we suceeded, schedule the next
+            one */
+        if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS))
+        {
+            transaction->actual_bytes = 0;      /* No bytes transfered for this packet as of yet */
+            transaction->iso_number_packets--;  /* One less ISO waiting to transfer */
+            transaction->iso_packets++;         /* Increment to the next location in our packet array */
+            transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
+            goto done;
+        }
+    }
+
+    /* Remove the transaction from the pipe list */
+    if (transaction->next)
+        transaction->next->prev = transaction->prev;
+    else
+        pipe->tail = transaction->prev;
+    if (transaction->prev)
+        transaction->prev->next = transaction->next;
+    else
+        pipe->head = transaction->next;
+    if (!pipe->head)
+    {
+        __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
+        __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
+
+    }
+    __cvmx_usb_perform_callback(usb, pipe, transaction,
+                                CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
+                                complete_code);
+    __cvmx_usb_free_transaction(usb, transaction);
+    /* Disable SOF interrupts if we don't have any pending transactions */
+    usb->active_transactions--;
+    if (usb->active_transactions == 0)
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, 0);
+done:
+    CVMX_USB_RETURN_NOTHING();
+}
+
+
+/**
+ * @INTERNAL
+ * Submit a usb transaction to a pipe. Called for all types
+ * of transactions.
+ *
+ * @param usb
+ * @param pipe_handle
+ *                  Which pipe to submit to. Will be validated in this function.
+ * @param type      Transaction type
+ * @param flags     Flags for the transaction
+ * @param buffer    User buffer for the transaction
+ * @param buffer_length
+ *                  User buffer's length in bytes
+ * @param control_header
+ *                  For control transactions, the 8 byte standard header
+ * @param iso_start_frame
+ *                  For ISO transactiosn, the start frame
+ * @param iso_number_packets
+ *                  For ISO, the number of packet in the transaction.
+ * @param iso_packets
+ *                  A description of each ISO packet
+ * @param callback  User callback to call when the transaction completes
+ * @param user_data User's data for the callback
+ *
+ * @return Submit handle or negative on failure. Matches the result
+ *         in the external API.
+ */
+static int __cvmx_usb_submit_transaction(cvmx_usb_internal_state_t *usb,
+                                         int pipe_handle,
+                                         cvmx_usb_transfer_t type,
+                                         int flags,
+                                         uint64_t buffer,
+                                         int buffer_length,
+                                         uint64_t control_header,
+                                         int iso_start_frame,
+                                         int iso_number_packets,
+                                         cvmx_usb_iso_packet_t *iso_packets,
+                                         cvmx_usb_callback_func_t callback,
+                                         void *user_data)
+{
+    int submit_handle;
+    cvmx_usb_transaction_t *transaction;
+    cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
+
+    CVMX_USB_LOG_CALLED();
+    if (cvmx_unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    /* Fail if the pipe isn't open */
+    if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(pipe->transfer_type != type))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+
+    transaction = __cvmx_usb_alloc_transaction(usb);
+    if (cvmx_unlikely(!transaction))
+        CVMX_USB_RETURN(CVMX_USB_NO_MEMORY);
+
+    /* Enable SOF interrupts now that we have pending transactions */
+    if (usb->active_transactions == 0)
+        USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, 1);
+    usb->active_transactions++;
+
+    transaction->type = type;
+    transaction->flags |= flags;
+    transaction->buffer = buffer;
+    transaction->buffer_length = buffer_length;
+    transaction->control_header = control_header;
+    transaction->iso_start_frame = iso_start_frame; // FIXME: This is not used, implement it
+    transaction->iso_number_packets = iso_number_packets;
+    transaction->iso_packets = iso_packets;
+    transaction->callback = callback;
+    transaction->callback_data = user_data;
+    if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
+        transaction->stage = CVMX_USB_STAGE_SETUP;
+    else
+        transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
+
+    transaction->next = NULL;
+    if (pipe->tail)
+    {
+        transaction->prev = pipe->tail;
+        transaction->prev->next = transaction;
+    }
+    else
+    {
+        transaction->prev = NULL;
+        pipe->head = transaction;
+        __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
+        __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
+    }
+    pipe->tail = transaction;
+
+    submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
+
+    /* We may need to schedule the pipe if this was the head of the pipe */
+    if (!transaction->prev)
+        __cvmx_usb_schedule(usb, 0);
+
+    CVMX_USB_RETURN(submit_handle);
+}
+
+
+/**
+ * Call to submit a USB Bulk transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+int cvmx_usb_submit_bulk(cvmx_usb_state_t *state, int pipe_handle,
+                                uint64_t buffer, int buffer_length,
+                                cvmx_usb_callback_func_t callback,
+                                void *user_data)
+{
+    int submit_handle;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)buffer);
+    CVMX_USB_LOG_PARAM("%d", buffer_length);
+
+    /* Pipe handle checking is done later in a common place */
+    if (cvmx_unlikely(!buffer))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(buffer_length < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
+                                         CVMX_USB_TRANSFER_BULK,
+                                         0, /* flags */
+                                         buffer,
+                                         buffer_length,
+                                         0, /* control_header */
+                                         0, /* iso_start_frame */
+                                         0, /* iso_number_packets */
+                                         NULL, /* iso_packets */
+                                         callback,
+                                         user_data);
+    CVMX_USB_RETURN(submit_handle);
+}
+
+
+/**
+ * Call to submit a USB Interrupt transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+int cvmx_usb_submit_interrupt(cvmx_usb_state_t *state, int pipe_handle,
+                              uint64_t buffer, int buffer_length,
+                              cvmx_usb_callback_func_t callback,
+                              void *user_data)
+{
+    int submit_handle;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)buffer);
+    CVMX_USB_LOG_PARAM("%d", buffer_length);
+
+    /* Pipe handle checking is done later in a common place */
+    if (cvmx_unlikely(!buffer))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(buffer_length < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
+                                         CVMX_USB_TRANSFER_INTERRUPT,
+                                         0, /* flags */
+                                         buffer,
+                                         buffer_length,
+                                         0, /* control_header */
+                                         0, /* iso_start_frame */
+                                         0, /* iso_number_packets */
+                                         NULL, /* iso_packets */
+                                         callback,
+                                         user_data);
+    CVMX_USB_RETURN(submit_handle);
+}
+
+
+/**
+ * Call to submit a USB Control transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param control_header
+ *                  USB 8 byte control header physical address.
+ *                  Note that this is NOT A POINTER, but the
+ *                  full 64bit physical address of the buffer.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+int cvmx_usb_submit_control(cvmx_usb_state_t *state, int pipe_handle,
+                            uint64_t control_header,
+                            uint64_t buffer, int buffer_length,
+                            cvmx_usb_callback_func_t callback,
+                            void *user_data)
+{
+    int submit_handle;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+    cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(control_header);
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)control_header);
+    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)buffer);
+    CVMX_USB_LOG_PARAM("%d", buffer_length);
+
+    /* Pipe handle checking is done later in a common place */
+    if (cvmx_unlikely(!control_header))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    /* Some drivers send a buffer with a zero length. God only knows why */
+    if (cvmx_unlikely(buffer && (buffer_length < 0)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(!buffer && (buffer_length != 0)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+    if ((header->s.request_type & 0x80) == 0)
+        buffer_length = cvmx_le16_to_cpu(header->s.length);
+
+    submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
+                                         CVMX_USB_TRANSFER_CONTROL,
+                                         0, /* flags */
+                                         buffer,
+                                         buffer_length,
+                                         control_header,
+                                         0, /* iso_start_frame */
+                                         0, /* iso_number_packets */
+                                         NULL, /* iso_packets */
+                                         callback,
+                                         user_data);
+    CVMX_USB_RETURN(submit_handle);
+}
+
+
+/**
+ * Call to submit a USB Isochronous transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param start_frame
+ *                  Number of frames into the future to schedule
+ *                  this transaction.
+ * @param flags     Flags to control the transfer. See
+ *                  cvmx_usb_isochronous_flags_t for the flag
+ *                  definitions.
+ * @param number_packets
+ *                  Number of sequential packets to transfer.
+ *                  "packets" is a pointer to an array of this
+ *                  many packet structures.
+ * @param packets   Description of each transfer packet as
+ *                  defined by cvmx_usb_iso_packet_t. The array
+ *                  pointed to here must stay valid until the
+ *                  complete callback is called.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+int cvmx_usb_submit_isochronous(cvmx_usb_state_t *state, int pipe_handle,
+                                int start_frame, int flags,
+                                int number_packets,
+                                cvmx_usb_iso_packet_t packets[],
+                                uint64_t buffer, int buffer_length,
+                                cvmx_usb_callback_func_t callback,
+                                void *user_data)
+{
+    int submit_handle;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    CVMX_USB_LOG_PARAM("%d", start_frame);
+    CVMX_USB_LOG_PARAM("0x%x", flags);
+    CVMX_USB_LOG_PARAM("%d", number_packets);
+    CVMX_USB_LOG_PARAM("%p", packets);
+    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)buffer);
+    CVMX_USB_LOG_PARAM("%d", buffer_length);
+
+    /* Pipe handle checking is done later in a common place */
+    if (cvmx_unlikely(start_frame < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(flags & ~(CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT | CVMX_USB_ISOCHRONOUS_FLAGS_ASAP)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(number_packets < 1))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(!packets))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(!buffer))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(buffer_length < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
+                                         CVMX_USB_TRANSFER_ISOCHRONOUS,
+                                         flags,
+                                         buffer,
+                                         buffer_length,
+                                         0, /* control_header */
+                                         start_frame,
+                                         number_packets,
+                                         packets,
+                                         callback,
+                                         user_data);
+    CVMX_USB_RETURN(submit_handle);
+}
+
+
+/**
+ * Cancel one outstanding request in a pipe. Canceling a request
+ * can fail if the transaction has already completed before cancel
+ * is called. Even after a successful cancel call, it may take
+ * a frame or two for the cvmx_usb_poll() function to call the
+ * associated callback.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe_handle
+ *               Pipe handle to cancel requests in.
+ * @param submit_handle
+ *               Handle to transaction to cancel, returned by the submit function.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_cancel(cvmx_usb_state_t *state, int pipe_handle,
+                                  int submit_handle)
+{
+    cvmx_usb_transaction_t *transaction;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+    cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    CVMX_USB_LOG_PARAM("%d", submit_handle);
+
+    if (cvmx_unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    /* Fail if the pipe isn't open */
+    if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+
+    transaction = usb->transaction + submit_handle;
+
+    /* Fail if this transaction already completed */
+    if (cvmx_unlikely((transaction->flags & __CVMX_USB_TRANSACTION_FLAGS_IN_USE) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+
+    /* If the transaction is the HEAD of the queue and scheduled. We need to
+        treat it special */
+    if ((pipe->head == transaction) &&
+        (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED))
+    {
+        cvmx_usbcx_hccharx_t usbc_hcchar;
+
+        usb->pipe_for_channel[pipe->channel] = NULL;
+        pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
+
+        CVMX_SYNCW;
+
+        usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
+        /* If the channel isn't enabled then the transaction already completed */
+        if (usbc_hcchar.s.chena)
+        {
+            usbc_hcchar.s.chdis = 1;
+            __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
+        }
+    }
+    __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Cancel all outstanding requests in a pipe. Logically all this
+ * does is call cvmx_usb_cancel() in a loop.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe_handle
+ *               Pipe handle to cancel requests in.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_cancel_all(cvmx_usb_state_t *state, int pipe_handle)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+    cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    if (cvmx_unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    /* Fail if the pipe isn't open */
+    if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+
+    /* Simply loop through and attempt to cancel each transaction */
+    while (pipe->head)
+    {
+        cvmx_usb_status_t result = cvmx_usb_cancel(state, pipe_handle,
+            __cvmx_usb_get_submit_handle(usb, pipe->head));
+        if (cvmx_unlikely(result != CVMX_USB_SUCCESS))
+            CVMX_USB_RETURN(result);
+    }
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Close a pipe created with cvmx_usb_open_pipe().
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe_handle
+ *               Pipe handle to close.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t. CVMX_USB_BUSY is returned if the
+ *         pipe has outstanding transfers.
+ */
+cvmx_usb_status_t cvmx_usb_close_pipe(cvmx_usb_state_t *state, int pipe_handle)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+    cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", pipe_handle);
+    if (cvmx_unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    /* Fail if the pipe isn't open */
+    if (cvmx_unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+
+    /* Fail if the pipe has pending transactions */
+    if (cvmx_unlikely(pipe->head))
+        CVMX_USB_RETURN(CVMX_USB_BUSY);
+
+    pipe->flags = 0;
+    __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
+    __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Register a function to be called when various USB events occur.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param reason    Which event to register for.
+ * @param callback  Function to call when the event occurs.
+ * @param user_data User data parameter to the function.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_register_callback(cvmx_usb_state_t *state,
+                                             cvmx_usb_callback_t reason,
+                                             cvmx_usb_callback_func_t callback,
+                                             void *user_data)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", reason);
+    CVMX_USB_LOG_PARAM("%p", callback);
+    CVMX_USB_LOG_PARAM("%p", user_data);
+    if (cvmx_unlikely(reason >= __CVMX_USB_CALLBACK_END))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(!callback))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+
+    usb->callback[reason] = callback;
+    usb->callback_data[reason] = user_data;
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Get the current USB protocol level frame number. The frame
+ * number is always in the range of 0-0x7ff.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return USB frame number
+ */
+int cvmx_usb_get_frame_number(cvmx_usb_state_t *state)
+{
+    int frame_number;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+
+    if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE))
+    {
+        cvmx_usbcx_dsts_t usbc_dsts;
+        usbc_dsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DSTS(usb->index));
+        frame_number = usbc_dsts.s.soffn;
+    }
+    else
+    {
+        cvmx_usbcx_hfnum_t usbc_hfnum;
+        usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
+        frame_number = usbc_hfnum.s.frnum;
+    }
+
+    CVMX_USB_RETURN(frame_number);
+}
+
+
+/**
+ * @INTERNAL
+ * Poll a channel for status
+ *
+ * @param usb     USB device
+ * @param channel Channel to poll
+ *
+ * @return Zero on success
+ */
+static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
+{
+    cvmx_usbcx_hcintx_t usbc_hcint;
+    cvmx_usbcx_hctsizx_t usbc_hctsiz;
+    cvmx_usbcx_hccharx_t usbc_hcchar;
+    cvmx_usb_pipe_t *pipe;
+    cvmx_usb_transaction_t *transaction;
+    int bytes_this_transfer;
+    int bytes_in_last_packet;
+    int packets_processed;
+    int buffer_space_left;
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%d", channel);
+
+    /* Read the interrupt status bits for the channel */
+    usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
+
+    /* We ignore any interrupts where the channel hasn't halted yet. These
+        should be impossible since we don't enable any interrupts except for
+        channel halted */
+    if (!usbc_hcint.s.chhltd)
+        CVMX_USB_RETURN(0);
+
+    /* Now that the channel has halted, clear all status bits before
+        processing. This way we don't have any race conditions caused by the
+        channel starting up and finishing before we clear the bits */
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
+    //cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
+
+    usb->idle_hardware_channels |= (1<<channel);
+
+    /* Make sure this channel is tied to a valid pipe */
+    pipe = usb->pipe_for_channel[channel];
+    CVMX_PREFETCH(pipe, 0);
+    CVMX_PREFETCH(pipe, 128);
+    if (!pipe)
+        CVMX_USB_RETURN(0);
+    transaction = pipe->head;
+    CVMX_PREFETCH0(transaction);
+
+    /* Disconnect this pipe from the HW channel. Later the schedule function will
+        figure out which pipe needs to go */
+    usb->pipe_for_channel[channel] = NULL;
+    pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
+
+    /* Read the channel config info so we can figure out how much data
+        transfered */
+    usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
+    usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
+
+    /* Calculating the number of bytes successfully transfered is dependent on
+        the transfer direction */
+    packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
+    if (usbc_hcchar.s.epdir)
+    {
+        /* IN transactions are easy. For every byte received the hardware
+            decrements xfersize. All we need to do is subtract the current
+            value of xfersize from its starting value and we know how many
+            bytes were written to the buffer */
+        bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
+    }
+    else
+    {
+        /* OUT transaction don't decrement xfersize. Instead pktcnt is
+            decremented on every successful packet send. The hardware does
+            this when it receives an ACK, or NYET. If it doesn't
+            receive one of these responses pktcnt doesn't change */
+        bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
+        /* The last packet may not be a full transfer if we didn't have
+            enough data */
+        if (bytes_this_transfer > transaction->xfersize)
+            bytes_this_transfer = transaction->xfersize;
+    }
+    /* Figure out how many bytes were in the last packet of the transfer */
+    if (packets_processed)
+        bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
+    else
+        bytes_in_last_packet = bytes_this_transfer;
+
+    /* As a special case, setup transactions output the setup header, not
+        the user's data. For this reason we don't count setup data as bytes
+        transfered */
+    if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
+        (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
+        bytes_this_transfer = 0;
+
+    /* Optional debug output */
+    if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS) ||
+        (pipe->flags & CVMX_USB_PIPE_FLAGS_DEBUG_TRANSFERS)))
+        cvmx_dprintf("%s: Channel %d halted. Pipe %d transaction %d stage %d bytes=%d\n",
+                     __FUNCTION__, channel,
+                     __cvmx_usb_get_pipe_handle(usb, pipe),
+                     __cvmx_usb_get_submit_handle(usb, transaction),
+                     transaction->stage, bytes_this_transfer);
+
+    /* Add the bytes transfered to the running total. It is important that
+        bytes_this_transfer doesn't count any data that needs to be
+        retransmitted */
+    transaction->actual_bytes += bytes_this_transfer;
+    if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
+        buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
+    else
+        buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
+
+    /* We need to remember the PID toggle state for the next transaction. The
+        hardware already updated it for the next transaction */
+    pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
+
+    /* For high speed bulk out, assume the next transaction will need to do a
+        ping before proceeding. If this isn't true the ACK processing below
+        will clear this flag */
+    if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
+        (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
+        (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
+        pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
+
+    if (usbc_hcint.s.stall)
+    {
+        /* STALL as a response means this transaction cannot be completed
+            because the device can't process transactions. Tell the user. Any
+            data that was transfered will be counted on the actual bytes
+            transfered */
+        pipe->pid_toggle = 0;
+        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
+    }
+    else if (0 && usbc_hcint.s.xfercompl)
+    {
+        /* XferCompl is only useful in non DMA mode */
+    }
+    else if (usbc_hcint.s.xacterr)
+    {
+        /* We know at least one packet worked if we get a ACK or NAK. Reset the retry counter */
+        if (usbc_hcint.s.nak || usbc_hcint.s.ack)
+            transaction->retries = 0;
+        transaction->retries++;
+        if (transaction->retries > MAX_RETRIES)
+        {
+            /* XactErr as a response means the device signaled something wrong with
+                the transfer. For example, PID toggle errors cause these */
+            __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
+        }
+        else
+        {
+            /* Rewind to the beginning of the transaction by anding off the
+                split complete bit */
+            transaction->stage &= ~1;
+            pipe->split_sc_frame = -1;
+            pipe->next_tx_cycle = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT) + pipe->interval;
+        }
+    }
+    else if (0 && usbc_hcint.s.datatglerr)
+    {
+        /* The hardware automatically handles Data Toggle Errors for us */
+    }
+    else if (usbc_hcint.s.bblerr)
+    {
+        /* Babble Error (BblErr) */
+        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
+    }
+    else if (usbc_hcint.s.frmovrun)
+    {
+        /* Frame Overrun (FrmOvrun) */
+        /* Rewind to the beginning of the transaction by anding off the
+            split complete bit */
+        transaction->stage &= ~1;
+        pipe->split_sc_frame = -1;
+    }
+    else if (usbc_hcint.s.nyet)
+    {
+        /* NYET as a response is only allowed in three cases: as a response to
+            a ping, as a response to a split transaction, and as a response to
+            a bulk out. The ping case is handled by hardware, so we only have
+            splits and bulk out */
+        if (!__cvmx_usb_pipe_needs_split(usb, pipe))
+        {
+            transaction->retries = 0;
+            /* If there is more data to go then we need to try again. Otherwise
+                this transaction is complete */
+            if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
+                __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+        }
+        else
+        {
+            /* Split transactions retry the split complete 4 times then rewind
+                to the start split and do the entire transactions again */
+            transaction->retries++;
+            if ((transaction->retries & 0x3) == 0)
+            {
+                /* Rewind to the beginning of the transaction by anding off the
+                    split complete bit */
+                transaction->stage &= ~1;
+                pipe->split_sc_frame = -1;
+            }
+        }
+    }
+    else if (usbc_hcint.s.ack)
+    {
+        transaction->retries = 0;
+        /* The ACK bit can only be checked after the other error bits. This is
+            because a multi packet transfer may succeed in a number of packets
+            and then get a different response on the last packet. In this case
+            both ACK and the last response bit will be set. If none of the
+            other response bits is set, then the last packet must have been an
+            ACK */
+
+        /* Since we got an ACK, we know we don't need to do a ping on this
+            pipe */
+        pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
+
+        switch (transaction->type)
+        {
+            case CVMX_USB_TRANSFER_CONTROL:
+                switch (transaction->stage)
+                {
+                    case CVMX_USB_STAGE_NON_CONTROL:
+                    case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
+                        /* This should be impossible */
+                        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
+                        break;
+                    case CVMX_USB_STAGE_SETUP:
+                        pipe->pid_toggle = 1;
+                        if (__cvmx_usb_pipe_needs_split(usb, pipe))
+                            transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
+                        else
+                        {
+                            cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
+                            if (header->s.length)
+                                transaction->stage = CVMX_USB_STAGE_DATA;
+                            else
+                                transaction->stage = CVMX_USB_STAGE_STATUS;
+                        }
+                        break;
+                    case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
+                        {
+                            cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
+                            if (header->s.length)
+                                transaction->stage = CVMX_USB_STAGE_DATA;
+                            else
+                                transaction->stage = CVMX_USB_STAGE_STATUS;
+                        }
+                        break;
+                    case CVMX_USB_STAGE_DATA:
+                        if (__cvmx_usb_pipe_needs_split(usb, pipe))
+                            transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
+                        else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
+                        {
+                            pipe->pid_toggle = 1;
+                            transaction->stage = CVMX_USB_STAGE_STATUS;
+                        }
+                        break;
+                    case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
+                        if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
+                        {
+                            pipe->pid_toggle = 1;
+                            transaction->stage = CVMX_USB_STAGE_STATUS;
+                        }
+                        else
+                        {
+                            transaction->stage = CVMX_USB_STAGE_DATA;
+                        }
+                        break;
+                    case CVMX_USB_STAGE_STATUS:
+                        if (__cvmx_usb_pipe_needs_split(usb, pipe))
+                            transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
+                        else
+                            __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                        break;
+                    case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
+                        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                        break;
+                }
+                break;
+            case CVMX_USB_TRANSFER_BULK:
+            case CVMX_USB_TRANSFER_INTERRUPT:
+                /* The only time a bulk transfer isn't complete when
+                    it finishes with an ACK is during a split transaction. For
+                    splits we need to continue the transfer if more data is
+                    needed */
+                if (__cvmx_usb_pipe_needs_split(usb, pipe))
+                {
+                    if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
+                        transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
+                    else
+                    {
+                        if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
+                            transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
+                        else
+                        {
+                            if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
+                                pipe->next_tx_cycle += pipe->interval;
+                            __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                        }
+                    }
+                }
+                else
+                {
+                    if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
+                        (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
+                        (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
+                        (usbc_hcint.s.nak))
+                        pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
+                    if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet))
+                    {
+                        if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
+                            pipe->next_tx_cycle += pipe->interval;
+                        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                    }
+                }
+                break;
+            case CVMX_USB_TRANSFER_ISOCHRONOUS:
+                if (__cvmx_usb_pipe_needs_split(usb, pipe))
+                {
+                    /* ISOCHRONOUS OUT splits don't require a complete split stage.
+                        Instead they use a sequence of begin OUT splits to transfer
+                        the data 188 bytes at a time. Once the transfer is complete,
+                        the pipe sleeps until the next schedule interval */
+                    if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT)
+                    {
+                        pipe->next_tx_cycle += pipe->interval;
+                        /* If no space left or this wasn't a max size packet then
+                            this transfer is complete. Otherwise start it again
+                            to send the next 188 bytes */
+                        if (!buffer_space_left || (bytes_this_transfer < 188))
+                            __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                    }
+                    else
+                    {
+                        if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE)
+                        {
+                            /* We are in the incomming data phase. Keep getting
+                                data until we run out of space or get a small
+                                packet */
+                            if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
+                            {
+                                pipe->next_tx_cycle += pipe->interval;
+                                __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                            }
+                        }
+                        else
+                            transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
+                    }
+                }
+                else
+                {
+                    pipe->next_tx_cycle += pipe->interval;
+                    __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
+                }
+                break;
+        }
+    }
+    else if (usbc_hcint.s.nak)
+    {
+        uint64_t ipd_clk_count;
+        /* NAK as a response means the device couldn't accept the transaction,
+            but it should be retried in the future. Rewind to the beginning of
+            the transaction by anding off the split complete bit. Retry in the
+            next interval */
+        transaction->retries = 0;
+        transaction->stage &= ~1;
+        pipe->next_tx_cycle += pipe->interval;
+        ipd_clk_count = cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
+        if (pipe->next_tx_cycle < ipd_clk_count)
+            pipe->next_tx_cycle = ipd_clk_count + pipe->interval;
+    }
+    else
+    {
+        /* We get channel halted interrupts with no result bits sets when the
+            cable is unplugged */
+        __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
+    }
+    CVMX_USB_RETURN(0);
+}
+
+
+/**
+ * Poll a device mode endpoint for status
+ *
+ * @param usb    USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param endpoint_num
+ *               Endpoint to poll
+ *
+ * @return Zero on success
+ */
+static int __cvmx_usb_poll_endpoint(cvmx_usb_internal_state_t *usb, int endpoint_num)
+{
+    cvmx_usbcx_diepintx_t usbc_diepint;
+    cvmx_usbcx_doepintx_t usbc_doepint;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+    CVMX_USB_LOG_PARAM("%d", endpoint_num);
+
+    usbc_diepint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index));
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_DIEPINTX(endpoint_num, usb->index), usbc_diepint.u32);
+    //cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_USBCX_DIEPINTX(endpoint_num, usb->index), usbc_diepint.u32);
+    if (usbc_diepint.s.inepnakeff)
+    {
+        /* IN Endpoint NAK Effective (INEPNakEff)
+            Applies to periodic IN endpoints only.
+            Indicates that the IN endpoint NAK bit set by the application has
+            taken effect in the core. This bit can be cleared when the
+            application clears the IN endpoint NAK by writing to
+            DIEPCTLn.CNAK.
+            This interrupt indicates that the core has sampled the NAK bit
+            set (either by the application or by the core).
+            This interrupt does not necessarily mean that a NAK handshake
+            is sent on the USB. A STALL bit takes priority over a NAK bit. */
+        /* Nothing to do */
+    }
+    if (usbc_diepint.s.intknepmis)
+    {
+        /* IN Token Received with EP Mismatch (INTknEPMis)
+            Applies to non-periodic IN endpoints only.
+            Indicates that the data in the top of the non-periodic TxFIFO
+            belongs to an endpoint other than the one for which the IN
+            token was received. This interrupt is asserted on the endpoint
+            for which the IN token was received. */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: Endpoint %d mismatch\n", __FUNCTION__, endpoint_num);
+    }
+    if (usbc_diepint.s.intkntxfemp)
+    {
+        /* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
+            Applies only to non-periodic IN endpoints.
+            Indicates that an IN token was received when the associated
+            TxFIFO (periodic/non-periodic) was empty. This interrupt is
+            asserted on the endpoint for which the IN token was received. */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: Received IN token on endpoint %d without data\n", __FUNCTION__, endpoint_num);
+    }
+    if (usbc_diepint.s.timeout)
+    {
+        /* Timeout Condition (TimeOUT)
+            Applies to non-isochronous IN endpoints only.
+            Indicates that the core has detected a timeout condition on the
+            USB for the last IN token on this endpoint. */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: Received timeout on endpoint %d\n", __FUNCTION__, endpoint_num);
+    }
+    if (usbc_diepint.s.ahberr)
+    {
+        /* AHB Error (AHBErr)
+            This is generated only in Internal DMA mode when there is an
+            AHB error during an AHB read/write. The application can read
+            the corresponding endpoint DMA address register to get the
+            error address. */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: AHB error on endpoint %d\n", __FUNCTION__, endpoint_num);
+    }
+    if (usbc_diepint.s.epdisbld)
+    {
+        /* Endpoint Disabled Interrupt (EPDisbld)
+            This bit indicates that the endpoint is disabled per the
+            application's request. */
+        /* Nothing to do */
+    }
+    if (usbc_diepint.s.xfercompl)
+    {
+        /* Transfer Completed Interrupt (XferCompl)
+            Indicates that the programmed transfer is complete on the AHB
+            as well as on the USB, for this endpoint. */
+        __cvmx_usb_perform_callback(usb, usb->pipe + endpoint_num, NULL,
+                                    CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
+                                    CVMX_USB_COMPLETE_SUCCESS);
+    }
+
+    usbc_doepint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index));
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_DOEPINTX(endpoint_num, usb->index), usbc_doepint.u32);
+    //cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_USBCX_DOEPINTX(endpoint_num, usb->index), usbc_doepint.u32);
+    if (usbc_doepint.s.outtknepdis)
+    {
+        /* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
+            Applies only to control OUT endpoints.
+            Indicates that an OUT token was received when the endpoint
+            was not yet enabled. This interrupt is asserted on the endpoint
+            for which the OUT token was received. */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: Received OUT token on disabled endpoint %d\n", __FUNCTION__, endpoint_num);
+    }
+    if (usbc_doepint.s.setup)
+    {
+        /* SETUP Phase Done (SetUp)
+            Applies to control OUT endpoints only.
+            Indicates that the SETUP phase for the control endpoint is
+            complete and no more back-to-back SETUP packets were
+            received for the current control transfer. On this interrupt, the
+            application can decode the received SETUP data packet. */
+        __cvmx_usb_perform_callback(usb, usb->pipe + endpoint_num, NULL,
+                                    CVMX_USB_CALLBACK_DEVICE_SETUP,
+                                    CVMX_USB_COMPLETE_SUCCESS);
+    }
+    if (usbc_doepint.s.ahberr)
+    {
+        /* AHB Error (AHBErr)
+            This is generated only in Internal DMA mode when there is an
+            AHB error during an AHB read/write. The application can read
+            the corresponding endpoint DMA address register to get the
+            error address. */
+        if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+            cvmx_dprintf("%s: AHB error on endpoint %d\n", __FUNCTION__, endpoint_num);
+    }
+    if (usbc_doepint.s.epdisbld)
+    {
+        /* Endpoint Disabled Interrupt (EPDisbld)
+            This bit indicates that the endpoint is disabled per the
+            application's request. */
+        /* Nothing to do */
+    }
+    if (usbc_doepint.s.xfercompl)
+    {
+        /* Transfer Completed Interrupt (XferCompl)
+            Indicates that the programmed transfer is complete on the AHB
+            as well as on the USB, for this endpoint. */
+        __cvmx_usb_perform_callback(usb, usb->pipe + endpoint_num, NULL,
+                                    CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
+                                    CVMX_USB_COMPLETE_SUCCESS);
+    }
+
+    CVMX_USB_RETURN(0);
+}
+
+
+/**
+ * Poll the device mode endpoints for status
+ *
+ * @param usb  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Zero on success
+ */
+static int __cvmx_usb_poll_endpoints(cvmx_usb_internal_state_t *usb)
+{
+    cvmx_usbcx_daint_t usbc_daint;
+    int active_endpoints;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", usb);
+
+    usbc_daint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DAINT(usb->index));
+    active_endpoints = usbc_daint.s.inepint | usbc_daint.s.outepint;
+
+    while (active_endpoints)
+    {
+        int endpoint;
+        CVMX_CLZ(endpoint, active_endpoints);
+        endpoint = 31 - endpoint;
+        __cvmx_usb_poll_endpoint(usb, endpoint);
+        active_endpoints ^= 1<<endpoint;
+    }
+
+    CVMX_USB_RETURN(0);
+}
+
+
+/**
+ * Poll the USB block for status and call all needed callback
+ * handlers. This function is meant to be called in the interrupt
+ * handler for the USB controller. It can also be called
+ * periodically in a loop for non-interrupt based operation.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state)
+{
+    cvmx_usbcx_gintsts_t usbc_gintsts;
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_PREFETCH(usb, 0);
+    CVMX_PREFETCH(usb, 1*128);
+    CVMX_PREFETCH(usb, 2*128);
+    CVMX_PREFETCH(usb, 3*128);
+    CVMX_PREFETCH(usb, 4*128);
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+
+    /* Read the pending interrupts */
+    usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
+
+    if (usbc_gintsts.s.wkupint)
+    {
+        /* Resume/Remote Wakeup Detected Interrupt (WkUpInt)
+            In Device mode, this interrupt is asserted when a resume is
+            detected on the USB. In Host mode, this interrupt is asserted
+            when a remote wakeup is detected on the USB. */
+        /* Octeon doesn't support suspend / resume */
+    }
+    if (usbc_gintsts.s.sessreqint)
+    {
+        /* Session Request/New Session Detected Interrupt (SessReqInt)
+            In Host mode, this interrupt is asserted when a session request
+            is detected from the device. In Device mode, this interrupt is
+            asserted when the utmiotg_bvalid signal goes high. */
+        /* Octeon doesn't support OTG */
+    }
+    if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint)
+    {
+        cvmx_usbcx_hprt_t usbc_hprt;
+        /* Disconnect Detected Interrupt (DisconnInt)
+            Asserted when a device disconnect is detected. */
+
+        /* Host Port Interrupt (PrtInt)
+            The core sets this bit to indicate a change in port status of one
+            of the O2P USB core ports in Host mode. The application must
+            read the Host Port Control and Status (HPRT) register to
+            determine the exact event that caused this interrupt. The
+            application must clear the appropriate status bit in the Host Port
+            Control and Status register to clear this bit. */
+
+        /* Call the user's port callback */
+        __cvmx_usb_perform_callback(usb, NULL, NULL,
+                                    CVMX_USB_CALLBACK_PORT_CHANGED,
+                                    CVMX_USB_COMPLETE_SUCCESS);
+        /* Clear the port change bits */
+        usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
+        usbc_hprt.s.prtena = 0;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
+    }
+    if (usbc_gintsts.s.conidstschng)
+    {
+        /* Connector ID Status Change (ConIDStsChng)
+            The core sets this bit when there is a change in connector ID
+            status. */
+        /* The USB core currently doesn't support dynamically changing from
+            host to device mode */
+    }
+    if (usbc_gintsts.s.ptxfemp)
+    {
+        /* Periodic TxFIFO Empty (PTxFEmp)
+            Asserted when the Periodic Transmit FIFO is either half or
+            completely empty and there is space for at least one entry to be
+            written in the Periodic Request Queue. The half or completely
+            empty status is determined by the Periodic TxFIFO Empty Level
+            bit in the Core AHB Configuration register
+            (GAHBCFG.PTxFEmpLvl). */
+        /* In DMA mode we don't care */
+    }
+    if (usbc_gintsts.s.hchint)
+    {
+        /* Host Channels Interrupt (HChInt)
+            The core sets this bit to indicate that an interrupt is pending on
+            one of the channels of the core (in Host mode). The application
+            must read the Host All Channels Interrupt (HAINT) register to
+            determine the exact number of the channel on which the
+            interrupt occurred, and then read the corresponding Host
+            Channel-n Interrupt (HCINTn) register to determine the exact
+            cause of the interrupt. The application must clear the
+            appropriate status bit in the HCINTn register to clear this bit. */
+        cvmx_usbcx_haint_t usbc_haint;
+        usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
+        while (usbc_haint.u32)
+        {
+            int channel;
+            CVMX_CLZ(channel, usbc_haint.u32);
+            channel = 31 - channel;
+            __cvmx_usb_poll_channel(usb, channel);
+            usbc_haint.u32 ^= 1<<channel;
+        }
+    }
+    if (usbc_gintsts.s.fetsusp)
+    {
+        /* Data Fetch Suspended (FetSusp)
+            This interrupt is valid only in DMA mode. This interrupt indicates
+            that the core has stopped fetching data for IN endpoints due to
+            the unavailability of TxFIFO space or Request Queue space.
+            This interrupt is used by the application for an endpoint
+            mismatch algorithm. */
+        // FIXME
+    }
+    if (usbc_gintsts.s.incomplp)
+    {
+        /* Incomplete Periodic Transfer (incomplP)
+            In Host mode, the core sets this interrupt bit when there are
+            incomplete periodic transactions still pending which are
+            scheduled for the current microframe.
+            Incomplete Isochronous OUT Transfer (incompISOOUT)
+            The Device mode, the core sets this interrupt to indicate that
+            there is at least one isochronous OUT endpoint on which the
+            transfer is not completed in the current microframe. This
+            interrupt is asserted along with the End of Periodic Frame
+            Interrupt (EOPF) bit in this register. */
+        // FIXME
+    }
+    if (usbc_gintsts.s.incompisoin)
+    {
+        /* Incomplete Isochronous IN Transfer (incompISOIN)
+            The core sets this interrupt to indicate that there is at least one
+            isochronous IN endpoint on which the transfer is not completed
+            in the current microframe. This interrupt is asserted along with
+            the End of Periodic Frame Interrupt (EOPF) bit in this register. */
+        // FIXME
+    }
+    if (usbc_gintsts.s.oepint)
+    {
+        /* OUT Endpoints Interrupt (OEPInt)
+            The core sets this bit to indicate that an interrupt is pending on
+            one of the OUT endpoints of the core (in Device mode). The
+            application must read the Device All Endpoints Interrupt
+            (DAINT) register to determine the exact number of the OUT
+            endpoint on which the interrupt occurred, and then read the
+            corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
+            register to determine the exact cause of the interrupt. The
+            application must clear the appropriate status bit in the
+            corresponding DOEPINTn register to clear this bit. */
+        __cvmx_usb_poll_endpoints(usb);
+    }
+    if (usbc_gintsts.s.iepint)
+    {
+        /* IN Endpoints Interrupt (IEPInt)
+            The core sets this bit to indicate that an interrupt is pending on
+            one of the IN endpoints of the core (in Device mode). The
+            application must read the Device All Endpoints Interrupt
+            (DAINT) register to determine the exact number of the IN
+            endpoint on which the interrupt occurred, and then read the
+            corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
+            register to determine the exact cause of the interrupt. The
+            application must clear the appropriate status bit in the
+            corresponding DIEPINTn register to clear this bit. */
+        __cvmx_usb_poll_endpoints(usb);
+    }
+    if (usbc_gintsts.s.epmis)
+    {
+        /* Endpoint Mismatch Interrupt (EPMis)
+            Indicates that an IN token has been received for a non-periodic
+            endpoint, but the data for another endpoint is present in the top
+            of the Non-Periodic Transmit FIFO and the IN endpoint
+            mismatch count programmed by the application has expired. */
+        // FIXME
+    }
+    if (usbc_gintsts.s.eopf)
+    {
+        /* End of Periodic Frame Interrupt (EOPF)
+            Indicates that the period specified in the Periodic Frame Interval
+            field of the Device Configuration register (DCFG.PerFrInt) has
+            been reached in the current microframe. */
+        // FIXME
+    }
+    if (usbc_gintsts.s.isooutdrop)
+    {
+        /* Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
+            The core sets this bit when it fails to write an isochronous OUT
+            packet into the RxFIFO because the RxFIFO doesn't have
+            enough space to accommodate a maximum packet size packet
+            for the isochronous OUT endpoint. */
+        // FIXME
+    }
+    if (usbc_gintsts.s.enumdone)
+    {
+        /* Enumeration Done (EnumDone)
+            The core sets this bit to indicate that speed enumeration is
+            complete. The application must read the Device Status (DSTS)
+            register to obtain the enumerated speed. */
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE)
+        {
+            cvmx_usbcx_dsts_t usbc_dsts;
+            usbc_dsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_DSTS(usb->index));
+            if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+                cvmx_dprintf("%s: USB%d Enumeration complete with %s speed\n",
+                             __FUNCTION__, usb->index,
+                             (usbc_dsts.s.enumspd == CVMX_USB_SPEED_HIGH) ? "high" :
+                             (usbc_dsts.s.enumspd == CVMX_USB_SPEED_FULL) ? "full" :
+                             "low");
+            USB_SET_FIELD32(CVMX_USBCX_DIEPCTLX(0, usb->index),
+                            cvmx_usbcx_diepctlx_t, mps,
+                            (usbc_dsts.s.enumspd == CVMX_USB_SPEED_LOW) ? 3 : 0);
+            USB_SET_FIELD32(CVMX_USBCX_DOEPCTLX(0, usb->index),
+                            cvmx_usbcx_doepctlx_t, epena, 1);
+        }
+    }
+    if (usbc_gintsts.s.usbrst)
+    {
+        /* USB Reset (USBRst)
+            The core sets this bit to indicate that a reset is
+            detected on the USB. */
+        if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE)
+        {
+            if (cvmx_unlikely(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO))
+                cvmx_dprintf("%s: USB%d Reset complete\n", __FUNCTION__, usb->index);
+            __cvmx_usb_device_reset_complete(usb);
+        }
+    }
+    if (usbc_gintsts.s.nptxfemp)
+    {
+        /* Non-Periodic TxFIFO Empty (NPTxFEmp)
+            This interrupt is asserted when the Non-Periodic TxFIFO is
+            either half or completely empty, and there is space for at least
+            one entry to be written to the Non-Periodic Transmit Request
+            Queue. The half or completely empty status is determined by
+            the Non-Periodic TxFIFO Empty Level bit in the Core AHB
+            Configuration register (GAHBCFG.NPTxFEmpLvl). */
+        /* In DMA mode this is handled by hardware */
+    }
+    if (usbc_gintsts.s.rxflvl)
+    {
+        /* RxFIFO Non-Empty (RxFLvl)
+            Indicates that there is at least one packet pending to be read
+            from the RxFIFO. */
+        /* In DMA mode this is handled by hardware */
+    }
+    if (usbc_gintsts.s.sof)
+    {
+        /* Start of (micro)Frame (Sof)
+            In Host mode, the core sets this bit to indicate that an SOF
+            (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
+            USB. The application must write a 1 to this bit to clear the
+            interrupt.
+            In Device mode, in the core sets this bit to indicate that an SOF
+            token has been received on the USB. The application can read
+            the Device Status register to get the current (micro)frame
+            number. This interrupt is seen only when the core is operating
+            at either HS or FS. */
+    }
+    if (usbc_gintsts.s.otgint)
+    {
+        /* OTG Interrupt (OTGInt)
+            The core sets this bit to indicate an OTG protocol event. The
+            application must read the OTG Interrupt Status (GOTGINT)
+            register to determine the exact event that caused this interrupt.
+            The application must clear the appropriate status bit in the
+            GOTGINT register to clear this bit. */
+        /* Octeon doesn't support OTG, so ignore */
+    }
+    if (usbc_gintsts.s.modemis)
+    {
+        /* Mode Mismatch Interrupt (ModeMis)
+            The core sets this bit when the application is trying to access:
+            * A Host mode register, when the core is operating in Device
+            mode
+            * A Device mode register, when the core is operating in Host
+            mode
+            The register access is completed on the AHB with an OKAY
+            response, but is ignored by the core internally and doesn't
+            affect the operation of the core. */
+        /* Ignored for now */
+    }
+
+    __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
+
+    /* Clear the interrupts now that we know about them */
+    __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Enable an endpoint for use in device mode. After this call
+ * transactions will be allowed over the endpoint. This must be
+ * called after every usb reset.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param endpoint_num
+ *               The endpoint number to enable (0-4)
+ * @param transfer_type
+ *               USB transfer type of this endpoint
+ * @param transfer_dir
+ *               Direction of transfer relative to Octeon
+ * @param max_packet_size
+ *               Maximum packet size support by this endpoint
+ * @param buffer Buffer to send/receive
+ * @param buffer_length
+ *               Length of the buffer in bytes
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_device_enable_endpoint(cvmx_usb_state_t *state,
+                                                  int endpoint_num,
+                                                  cvmx_usb_transfer_t transfer_type,
+                                                  cvmx_usb_direction_t transfer_dir,
+                                                  int max_packet_size,
+                                                  uint64_t buffer,
+                                                  int buffer_length)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", endpoint_num);
+    CVMX_USB_LOG_PARAM("%d", transfer_type);
+    CVMX_USB_LOG_PARAM("%d", transfer_dir);
+    CVMX_USB_LOG_PARAM("%d", max_packet_size);
+    CVMX_USB_LOG_PARAM("0x%llx", (unsigned long long)buffer);
+    CVMX_USB_LOG_PARAM("%d", buffer_length);
+
+    if (cvmx_unlikely((endpoint_num < 0) || (endpoint_num > 4)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
+        (transfer_dir != CVMX_USB_DIRECTION_IN)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((max_packet_size < 0) || (max_packet_size > 512)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(!buffer))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely(buffer_length < 0))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    if (transfer_dir == CVMX_USB_DIRECTION_IN)
+    {
+        cvmx_usbcx_doepctlx_t usbc_doepctl;
+        cvmx_usbcx_doeptsizx_t usbc_doeptsiz;
+
+        /* Setup the locations the DMA engines use  */
+        __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + endpoint_num*8, buffer);
+        usbc_doeptsiz.u32 = 0;
+        usbc_doeptsiz.s.mc = 1; // FIXME
+        usbc_doeptsiz.s.pktcnt = (buffer_length + max_packet_size - 1) / max_packet_size;
+        if (usbc_doeptsiz.s.pktcnt == 0)
+            usbc_doeptsiz.s.pktcnt = 1;
+        usbc_doeptsiz.s.xfersize = buffer_length;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DOEPTSIZX(endpoint_num, usb->index), usbc_doeptsiz.u32);
+
+        usbc_doepctl.u32 = 0;
+        usbc_doepctl.s.epena = 1;
+        usbc_doepctl.s.setd1pid = 0; // FIXME
+        usbc_doepctl.s.setd0pid = 0; // FIXME
+        usbc_doepctl.s.cnak = 1;
+        usbc_doepctl.s.eptype = transfer_type;
+        usbc_doepctl.s.usbactep = 1;
+        usbc_doepctl.s.mps = max_packet_size;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index), usbc_doepctl.u32);
+    }
+    else
+    {
+        cvmx_usbcx_diepctlx_t usbc_diepctl;
+        cvmx_usbcx_dieptsizx_t usbc_dieptsiz;
+
+        /* Setup the locations the DMA engines use  */
+        __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + endpoint_num*8, buffer);
+        usbc_dieptsiz.u32 = 0;
+        usbc_dieptsiz.s.mc = 1; // FIXME
+        usbc_dieptsiz.s.pktcnt = (buffer_length + max_packet_size - 1) / max_packet_size;
+        if (usbc_dieptsiz.s.pktcnt == 0)
+            usbc_dieptsiz.s.pktcnt = 1;
+        usbc_dieptsiz.s.xfersize = buffer_length;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DIEPTSIZX(endpoint_num, usb->index), usbc_dieptsiz.u32);
+
+        usbc_diepctl.u32 = 0;
+        usbc_diepctl.s.epena = 1;
+        usbc_diepctl.s.setd1pid = 0; // FIXME
+        usbc_diepctl.s.setd0pid = 0; // FIXME
+        usbc_diepctl.s.cnak = 1;
+        if ((transfer_type == CVMX_USB_TRANSFER_INTERRUPT) ||
+            (transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS))
+            usbc_diepctl.s.txfnum = endpoint_num; // FIXME
+        else
+            usbc_diepctl.s.txfnum = 0;
+        usbc_diepctl.s.eptype = transfer_type;
+        usbc_diepctl.s.usbactep = 1;
+        usbc_diepctl.s.nextep = endpoint_num - 1; // FIXME
+        usbc_diepctl.s.mps = max_packet_size;
+        __cvmx_usb_write_csr32(usb, CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index), usbc_diepctl.u32);
+    }
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
+
+/**
+ * Disable an endpoint in device mode.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param endpoint_num
+ *               The endpoint number to disable (0-4)
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+cvmx_usb_status_t cvmx_usb_device_disable_endpoint(cvmx_usb_state_t *state,
+                                                   int endpoint_num)
+{
+    cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
+
+    CVMX_USB_LOG_CALLED();
+    CVMX_USB_LOG_PARAM("%p", state);
+    CVMX_USB_LOG_PARAM("%d", endpoint_num);
+
+    if (cvmx_unlikely((endpoint_num < 0) || (endpoint_num > 4)))
+        CVMX_USB_RETURN(CVMX_USB_INVALID_PARAM);
+    if (cvmx_unlikely((usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE) == 0))
+        CVMX_USB_RETURN(CVMX_USB_INCORRECT_MODE);
+
+    USB_SET_FIELD32(CVMX_USBCX_DOEPCTLX(endpoint_num, usb->index),
+                    cvmx_usbcx_doepctlx_t, epdis, 1);
+    USB_SET_FIELD32(CVMX_USBCX_DIEPCTLX(endpoint_num, usb->index),
+                    cvmx_usbcx_diepctlx_t, epdis, 1);
+
+    CVMX_USB_RETURN(CVMX_USB_SUCCESS);
+}
+
diff --git a/cvmx-usb.h b/cvmx-usb.h
new file mode 100644
index 0000000000000..825fdb465640e
--- /dev/null
+++ b/cvmx-usb.h
@@ -0,0 +1,1129 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * "cvmx-usb.h" defines a set of low level USB functions to help
+ * developers create Octeon USB drivers for various operating
+ * systems. These functions provide a generic API to the Octeon
+ * USB blocks, hiding the internal hardware specific
+ * operations.
+ *
+ * At a high level the device driver needs to:
+ *
+ * -# Call cvmx_usb_get_num_ports() to get the number of
+ *  supported ports.
+ * -# Call cvmx_usb_initialize() for each Octeon USB port.
+ * -# Enable the port using cvmx_usb_enable().
+ * -# Either periodically, or in an interrupt handler, call
+ *  cvmx_usb_poll() to service USB events.
+ * -# Manage pipes using cvmx_usb_open_pipe() and
+ *  cvmx_usb_close_pipe().
+ * -# Manage transfers using cvmx_usb_submit_*() and
+ *  cvmx_usb_cancel*().
+ * -# Shutdown USB on unload using cvmx_usb_shutdown().
+ *
+ * To monitor USB status changes, the device driver must use
+ * cvmx_usb_register_callback() to register for events that it
+ * is interested in. Below are a few hints on successfully
+ * implementing a driver on top of this API.
+ *
+ * <h2>Initialization</h2>
+ *
+ * When a driver is first loaded, it is normally not necessary
+ * to bring up the USB port completely. Most operating systems
+ * expect to initialize and enable the port in two independent
+ * steps. Normally an operating system will probe hardware,
+ * initialize anything found, and then enable the hardware.
+ *
+ * In the probe phase you should:
+ * -# Use cvmx_usb_get_num_ports() to determine the number of
+ *  USB port to be supported.
+ * -# Allocate space for a cvmx_usb_state_t structure for each
+ *  port.
+ * -# Tell the operating system about each port
+ *
+ * In the initialization phase you should:
+ * -# Use cvmx_usb_initialize() on each port.
+ * -# Do not call cvmx_usb_enable(). This leaves the USB port in
+ *  the disabled state until the operating system is ready.
+ *
+ * Finally, in the enable phase you should:
+ * -# Call cvmx_usb_enable() on the appropriate port.
+ * -# Note that some operating system use a RESET instead of an
+ *  enable call. To implement RESET, you should call
+ *  cvmx_usb_disable() followed by cvmx_usb_enable().
+ *
+ * <h2>Locking</h2>
+ *
+ * All of the functions in the cvmx-usb API assume exclusive
+ * access to the USB hardware and internal data structures. This
+ * means that the driver must provide locking as necessary.
+ *
+ * In the single CPU state it is normally enough to disable
+ * interrupts before every call to cvmx_usb*() and enable them
+ * again after the call is complete. Keep in mind that it is
+ * very common for the callback handlers to make additional
+ * calls into cvmx-usb, so the disable/enable must be protected
+ * against recursion. As an example, the Linux kernel
+ * local_irq_save() and local_irq_restore() are perfect for this
+ * in the non SMP case.
+ *
+ * In the SMP case, locking is more complicated. For SMP you not
+ * only need to disable interrupts on the local core, but also
+ * take a lock to make sure that another core cannot call
+ * cvmx-usb.
+ *
+ * <h2>Port callback</h2>
+ *
+ * The port callback prototype needs to look as follows:
+ *
+ * void port_callback(cvmx_usb_state_t *usb,
+ *                    cvmx_usb_callback_t reason,
+ *                    cvmx_usb_complete_t status,
+ *                    int pipe_handle,
+ *                    int submit_handle,
+ *                    int bytes_transferred,
+ *                    void *user_data);
+ * - @b usb is the cvmx_usb_state_t for the port.
+ * - @b reason will always be
+ *   CVMX_USB_CALLBACK_PORT_CHANGED.
+ * - @b status will always be CVMX_USB_COMPLETE_SUCCESS.
+ * - @b pipe_handle will always be -1.
+ * - @b submit_handle will always be -1.
+ * - @b bytes_transferred will always be 0.
+ * - @b user_data is the void pointer originally passed along
+ *   with the callback. Use this for any state information you
+ *   need.
+ *
+ * The port callback will be called whenever the user plugs /
+ * unplugs a device from the port. It will not be called when a
+ * device is plugged / unplugged from a hub connected to the
+ * root port. Normally all the callback needs to do is tell the
+ * operating system to poll the root hub for status. Under
+ * Linux, this is performed by calling usb_hcd_poll_rh_status().
+ * In the Linux driver we use @b user_data. to pass around the
+ * Linux "hcd" structure. Once the port callback completes,
+ * Linux automatically calls octeon_usb_hub_status_data() which
+ * uses cvmx_usb_get_status() to determine the root port status.
+ *
+ * <h2>Complete callback</h2>
+ *
+ * The completion callback prototype needs to look as follows:
+ *
+ * void complete_callback(cvmx_usb_state_t *usb,
+ *                        cvmx_usb_callback_t reason,
+ *                        cvmx_usb_complete_t status,
+ *                        int pipe_handle,
+ *                        int submit_handle,
+ *                        int bytes_transferred,
+ *                        void *user_data);
+ * - @b usb is the cvmx_usb_state_t for the port.
+ * - @b reason will always be
+ *   CVMX_USB_CALLBACK_TRANSFER_COMPLETE.
+ * - @b status will be one of the cvmx_usb_complete_t
+ *   enumerations.
+ * - @b pipe_handle is the handle to the pipe the transaction
+ *   was originally submitted on.
+ * - @b submit_handle is the handle returned by the original
+ *   cvmx_usb_submit_* call.
+ * - @b bytes_transferred is the number of bytes successfully
+ *   transferred in the transaction. This will be zero on most
+ *   error conditions.
+ * - @b user_data is the void pointer originally passed along
+ *   with the callback. Use this for any state information you
+ *   need. For example, the Linux "urb" is stored in here in the
+ *   Linux driver.
+ *
+ * In general your callback handler should use @b status and @b
+ * bytes_transferred to tell the operating system the how the
+ * transaction completed. Normally the pipe is not changed in
+ * this callback.
+ *
+ * <h2>Canceling transactions</h2>
+ *
+ * When a transaction is cancelled using cvmx_usb_cancel*(), the
+ * actual length of time until the complete callback is called
+ * can vary greatly. It may be called before cvmx_usb_cancel*()
+ * returns, or it may be called a number of usb frames in the
+ * future once the hardware frees the transaction. In either of
+ * these cases, the complete handler will receive
+ * CVMX_USB_COMPLETE_CANCEL.
+ *
+ * <h2>Handling pipes</h2>
+ *
+ * USB "pipes" is a software construct created by this API to
+ * enable the ordering of usb transactions to a device endpoint.
+ * Octeon's underlying hardware doesn't have any concept
+ * equivalent to "pipes". The hardware instead has eight
+ * channels that can be used simultaneously to have up to eight
+ * transaction in process at the same time. In order to maintain
+ * ordering in a pipe, the transactions for a pipe will only be
+ * active in one hardware channel at a time. From an API user's
+ * perspective, this doesn't matter but it can be helpful to
+ * keep this in mind when you are probing hardware while
+ * debugging.
+ *
+ * Also keep in mind that usb transactions contain state
+ * information about the previous transaction to the same
+ * endpoint. Each transaction has a PID toggle that changes 0/1
+ * between each sub packet. This is maintained in the pipe data
+ * structures. For this reason, you generally cannot create and
+ * destroy a pipe for every transaction. A sequence of
+ * transaction to the same endpoint must use the same pipe.
+ *
+ * <h2>Root Hub</h2>
+ *
+ * Some operating systems view the usb root port as a normal usb
+ * hub. These systems attempt to control the root hub with
+ * messages similar to the usb 2.0 spec for hub control and
+ * status. For these systems it may be necessary to write
+ * function to decode standard usb control messages into
+ * equivalent cvmx-usb API calls. As an example, the following
+ * code is used under Linux for some of the basic hub control
+ * messages.
+ *
+ * @code
+ * static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
+ * {
+ *     cvmx_usb_state_t *usb = (cvmx_usb_state_t *)hcd->hcd_priv;
+ *     cvmx_usb_port_status_t usb_port_status;
+ *     int port_status;
+ *     struct usb_hub_descriptor *desc;
+ *     unsigned long flags;
+ *
+ *     switch (typeReq)
+ *     {
+ *         case ClearHubFeature:
+ *             DEBUG_ROOT_HUB("OcteonUSB: ClearHubFeature\n");
+ *             switch (wValue)
+ *             {
+ *                 case C_HUB_LOCAL_POWER:
+ *                 case C_HUB_OVER_CURRENT:
+ *                     // Nothing required here
+ *                     break;
+ *                 default:
+ *                     return -EINVAL;
+ *             }
+ *             break;
+ *         case ClearPortFeature:
+ *             DEBUG_ROOT_HUB("OcteonUSB: ClearPortFeature");
+ *             if (wIndex != 1)
+ *             {
+ *                 DEBUG_ROOT_HUB(" INVALID\n");
+ *                 return -EINVAL;
+ *             }
+ *
+ *             switch (wValue)
+ *             {
+ *                 case USB_PORT_FEAT_ENABLE:
+ *                     DEBUG_ROOT_HUB(" ENABLE");
+ *                     local_irq_save(flags);
+ *                     cvmx_usb_disable(usb);
+ *                     local_irq_restore(flags);
+ *                     break;
+ *                 case USB_PORT_FEAT_SUSPEND:
+ *                     DEBUG_ROOT_HUB(" SUSPEND");
+ *                     // Not supported on Octeon
+ *                     break;
+ *                 case USB_PORT_FEAT_POWER:
+ *                     DEBUG_ROOT_HUB(" POWER");
+ *                     // Not supported on Octeon
+ *                     break;
+ *                 case USB_PORT_FEAT_INDICATOR:
+ *                     DEBUG_ROOT_HUB(" INDICATOR");
+ *                     // Port inidicator not supported
+ *                     break;
+ *                 case USB_PORT_FEAT_C_CONNECTION:
+ *                     DEBUG_ROOT_HUB(" C_CONNECTION");
+ *                     // Clears drivers internal connect status change flag
+ *                     cvmx_usb_set_status(usb, cvmx_usb_get_status(usb));
+ *                     break;
+ *                 case USB_PORT_FEAT_C_RESET:
+ *                     DEBUG_ROOT_HUB(" C_RESET");
+ *                     // Clears the driver's internal Port Reset Change flag
+ *                     cvmx_usb_set_status(usb, cvmx_usb_get_status(usb));
+ *                     break;
+ *                 case USB_PORT_FEAT_C_ENABLE:
+ *                     DEBUG_ROOT_HUB(" C_ENABLE");
+ *                     // Clears the driver's internal Port Enable/Disable Change flag
+ *                     cvmx_usb_set_status(usb, cvmx_usb_get_status(usb));
+ *                     break;
+ *                 case USB_PORT_FEAT_C_SUSPEND:
+ *                     DEBUG_ROOT_HUB(" C_SUSPEND");
+ *                     // Clears the driver's internal Port Suspend Change flag,
+ *                         which is set when resume signaling on the host port is
+ *                         complete
+ *                     break;
+ *                 case USB_PORT_FEAT_C_OVER_CURRENT:
+ *                     DEBUG_ROOT_HUB(" C_OVER_CURRENT");
+ *                     // Clears the driver's overcurrent Change flag
+ *                     cvmx_usb_set_status(usb, cvmx_usb_get_status(usb));
+ *                     break;
+ *                 default:
+ *                     DEBUG_ROOT_HUB(" UNKNOWN\n");
+ *                     return -EINVAL;
+ *             }
+ *             DEBUG_ROOT_HUB("\n");
+ *             break;
+ *         case GetHubDescriptor:
+ *             DEBUG_ROOT_HUB("OcteonUSB: GetHubDescriptor\n");
+ *             desc = (struct usb_hub_descriptor *)buf;
+ *             desc->bDescLength = 9;
+ *             desc->bDescriptorType = 0x29;
+ *             desc->bNbrPorts = 1;
+ *             desc->wHubCharacteristics = 0x08;
+ *             desc->bPwrOn2PwrGood = 1;
+ *             desc->bHubContrCurrent = 0;
+ *             desc->bitmap[0] = 0;
+ *             desc->bitmap[1] = 0xff;
+ *             break;
+ *         case GetHubStatus:
+ *             DEBUG_ROOT_HUB("OcteonUSB: GetHubStatus\n");
+ *             *(__le32 *)buf = 0;
+ *             break;
+ *         case GetPortStatus:
+ *             DEBUG_ROOT_HUB("OcteonUSB: GetPortStatus");
+ *             if (wIndex != 1)
+ *             {
+ *                 DEBUG_ROOT_HUB(" INVALID\n");
+ *                 return -EINVAL;
+ *             }
+ *
+ *             usb_port_status = cvmx_usb_get_status(usb);
+ *             port_status = 0;
+ *
+ *             if (usb_port_status.connect_change)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
+ *                 DEBUG_ROOT_HUB(" C_CONNECTION");
+ *             }
+ *
+ *             if (usb_port_status.port_enabled)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
+ *                 DEBUG_ROOT_HUB(" C_ENABLE");
+ *             }
+ *
+ *             if (usb_port_status.connected)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
+ *                 DEBUG_ROOT_HUB(" CONNECTION");
+ *             }
+ *
+ *             if (usb_port_status.port_enabled)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_ENABLE);
+ *                 DEBUG_ROOT_HUB(" ENABLE");
+ *             }
+ *
+ *             if (usb_port_status.port_over_current)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
+ *                 DEBUG_ROOT_HUB(" OVER_CURRENT");
+ *             }
+ *
+ *             if (usb_port_status.port_powered)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_POWER);
+ *                 DEBUG_ROOT_HUB(" POWER");
+ *             }
+ *
+ *             if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
+ *                 DEBUG_ROOT_HUB(" HIGHSPEED");
+ *             }
+ *             else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW)
+ *             {
+ *                 port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
+ *                 DEBUG_ROOT_HUB(" LOWSPEED");
+ *             }
+ *
+ *             *((__le32 *)buf) = cpu_to_le32(port_status);
+ *             DEBUG_ROOT_HUB("\n");
+ *             break;
+ *         case SetHubFeature:
+ *             DEBUG_ROOT_HUB("OcteonUSB: SetHubFeature\n");
+ *             // No HUB features supported
+ *             break;
+ *         case SetPortFeature:
+ *             DEBUG_ROOT_HUB("OcteonUSB: SetPortFeature");
+ *             if (wIndex != 1)
+ *             {
+ *                 DEBUG_ROOT_HUB(" INVALID\n");
+ *                 return -EINVAL;
+ *             }
+ *
+ *             switch (wValue)
+ *             {
+ *                 case USB_PORT_FEAT_SUSPEND:
+ *                     DEBUG_ROOT_HUB(" SUSPEND\n");
+ *                     return -EINVAL;
+ *                 case USB_PORT_FEAT_POWER:
+ *                     DEBUG_ROOT_HUB(" POWER\n");
+ *                     return -EINVAL;
+ *                 case USB_PORT_FEAT_RESET:
+ *                     DEBUG_ROOT_HUB(" RESET\n");
+ *                     local_irq_save(flags);
+ *                     cvmx_usb_disable(usb);
+ *                     if (cvmx_usb_enable(usb))
+ *                         DEBUG_ERROR("Failed to enable the port\n");
+ *                     local_irq_restore(flags);
+ *                     return 0;
+ *                 case USB_PORT_FEAT_INDICATOR:
+ *                     DEBUG_ROOT_HUB(" INDICATOR\n");
+ *                     // Not supported
+ *                     break;
+ *                 default:
+ *                     DEBUG_ROOT_HUB(" UNKNOWN\n");
+ *                     return -EINVAL;
+ *             }
+ *             break;
+ *         default:
+ *             DEBUG_ROOT_HUB("OcteonUSB: Unknown root hub request\n");
+ *             return -EINVAL;
+ *     }
+ *     return 0;
+ * }
+ * @endcode
+ *
+ * <h2>Interrupts</h2>
+ *
+ * If you plan on using usb interrupts, cvmx_usb_poll() must be
+ * called on every usb interrupt. It will read the usb state,
+ * call any needed callbacks, and schedule transactions as
+ * needed. Your device driver needs only to hookup an interrupt
+ * handler and call cvmx_usb_poll(). Octeon's usb port 0 causes
+ * CIU bit CIU_INT*_SUM0[USB] to be set (bit 56). For port 1,
+ * CIU bit CIU_INT_SUM1[USB1] is set (bit 17). How these bits
+ * are turned into interrupt numbers is operating system
+ * specific. For Linux, there are the convenient defines
+ * OCTEON_IRQ_USB0 and OCTEON_IRQ_USB1 for the IRQ numbers.
+ *
+ * If you aren't using interrupts, simple call cvmx_usb_poll()
+ * in your main processing loop.
+ *
+ * <hr>$Revision: 32636 $<hr>
+ */
+
+#ifndef __CVMX_USB_H__
+#define __CVMX_USB_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumerations representing the status of function calls.
+ */
+typedef enum
+{
+    CVMX_USB_SUCCESS = 0,           /**< There were no errors */
+    CVMX_USB_INVALID_PARAM = -1,    /**< A parameter to the function was invalid */
+    CVMX_USB_NO_MEMORY = -2,        /**< Insufficient resources were available for the request */
+    CVMX_USB_BUSY = -3,             /**< The resource is busy and cannot service the request */
+    CVMX_USB_TIMEOUT = -4,          /**< Waiting for an action timed out */
+    CVMX_USB_INCORRECT_MODE = -5,   /**< The function call doesn't work in the current USB
+                                         mode. This happens when host only functions are
+                                         called in device mode or vice versa */
+} cvmx_usb_status_t;
+
+/**
+ * Enumerations representing the possible USB device speeds
+ */
+typedef enum
+{
+    CVMX_USB_SPEED_HIGH = 0,        /**< Device is operation at 480Mbps */
+    CVMX_USB_SPEED_FULL = 1,        /**< Device is operation at 12Mbps */
+    CVMX_USB_SPEED_LOW = 2,         /**< Device is operation at 1.5Mbps */
+} cvmx_usb_speed_t;
+
+/**
+ * Enumeration representing the possible USB transfer types.
+ */
+typedef enum
+{
+    CVMX_USB_TRANSFER_CONTROL = 0,      /**< USB transfer type control for hub and status transfers */
+    CVMX_USB_TRANSFER_ISOCHRONOUS = 1,  /**< USB transfer type isochronous for low priority periodic transfers */
+    CVMX_USB_TRANSFER_BULK = 2,         /**< USB transfer type bulk for large low priority transfers */
+    CVMX_USB_TRANSFER_INTERRUPT = 3,    /**< USB transfer type interrupt for high priority periodic transfers */
+} cvmx_usb_transfer_t;
+
+/**
+ * Enumeration of the transfer directions
+ */
+typedef enum
+{
+    CVMX_USB_DIRECTION_OUT,         /**< Data is transferring from Octeon to the device/host */
+    CVMX_USB_DIRECTION_IN,          /**< Data is transferring from the device/host to Octeon */
+} cvmx_usb_direction_t;
+
+/**
+ * Enumeration of all possible status codes passed to callback
+ * functions.
+ */
+typedef enum
+{
+    CVMX_USB_COMPLETE_SUCCESS,      /**< The transaction / operation finished without any errors */
+    CVMX_USB_COMPLETE_SHORT,        /**< FIXME: This is currently not implemented */
+    CVMX_USB_COMPLETE_CANCEL,       /**< The transaction was canceled while in flight by a user call to cvmx_usb_cancel* */
+    CVMX_USB_COMPLETE_ERROR,        /**< The transaction aborted with an unexpected error status */
+    CVMX_USB_COMPLETE_STALL,        /**< The transaction received a USB STALL response from the device */
+    CVMX_USB_COMPLETE_XACTERR,      /**< The transaction failed with an error from the device even after a number of retries */
+    CVMX_USB_COMPLETE_DATATGLERR,   /**< The transaction failed with a data toggle error even after a number of retries */
+    CVMX_USB_COMPLETE_BABBLEERR,    /**< The transaction failed with a babble error */
+    CVMX_USB_COMPLETE_FRAMEERR,     /**< The transaction failed with a frame error even after a number of retries */
+} cvmx_usb_complete_t;
+
+/**
+ * Structure returned containing the USB port status information.
+ */
+typedef struct
+{
+    uint32_t reserved           : 25;
+    uint32_t port_enabled       : 1; /**< 1 = Usb port is enabled, 0 = disabled */
+    uint32_t port_over_current  : 1; /**< 1 = Over current detected, 0 = Over current not detected. Octeon doesn't support over current detection */
+    uint32_t port_powered       : 1; /**< 1 = Port power is being supplied to the device, 0 = power is off. Octeon doesn't support turning port power off */
+    cvmx_usb_speed_t port_speed : 2; /**< Current port speed */
+    uint32_t connected          : 1; /**< 1 = A device is connected to the port, 0 = No device is connected */
+    uint32_t connect_change     : 1; /**< 1 = Device connected state changed since the last set status call */
+} cvmx_usb_port_status_t;
+
+/**
+ * This is the structure of a Control packet header
+ */
+typedef union
+{
+    uint64_t u64;
+    struct
+    {
+        uint64_t request_type   : 8;  /**< Bit 7 tells the direction: 1=IN, 0=OUT */
+        uint64_t request        : 8;  /**< The standard usb request to make */
+        uint64_t value          : 16; /**< Value parameter for the request in little endian format */
+        uint64_t index          : 16; /**< Index for the request in little endian format */
+        uint64_t length         : 16; /**< Length of the data associated with this request in little endian format */
+    } s;
+} cvmx_usb_control_header_t;
+
+/**
+ * Descriptor for Isochronous packets
+ */
+typedef struct
+{
+    int offset;                     /**< This is the offset in bytes into the main buffer where this data is stored */
+    int length;                     /**< This is the length in bytes of the data */
+    cvmx_usb_complete_t status;     /**< This is the status of this individual packet transfer */
+} cvmx_usb_iso_packet_t;
+
+/**
+ * Possible callback reasons for the USB API.
+ */
+typedef enum
+{
+    CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
+                                    /**< A callback of this type is called when a submitted transfer
+                                        completes. The completion callback will be called even if the
+                                        transfer fails or is canceled. The status parameter will
+                                        contain details of why he callback was called. */
+    CVMX_USB_CALLBACK_PORT_CHANGED, /**< The status of the port changed. For example, someone may have
+                                        plugged a device in. The status parameter contains
+                                        CVMX_USB_COMPLETE_SUCCESS. Use cvmx_usb_get_status() to get
+                                        the new port status. */
+    CVMX_USB_CALLBACK_DEVICE_SETUP, /**< This is called in device mode when a control channels receives
+                                        a setup header */
+    __CVMX_USB_CALLBACK_END         /**< Do not use. Used internally for array bounds */
+} cvmx_usb_callback_t;
+
+/**
+ * USB state internal data. The contents of this structure
+ * may change in future SDKs. No data in it should be referenced
+ * by user's of this API.
+ */
+typedef struct
+{
+    char data[65536];
+} cvmx_usb_state_t;
+
+/**
+ * USB callback functions are always of the following type.
+ * The parameters are as follows:
+ *      - state = USB device state populated by
+ *        cvmx_usb_initialize().
+ *      - reason = The cvmx_usb_callback_t used to register
+ *        the callback.
+ *      - status = The cvmx_usb_complete_t representing the
+ *        status code of a transaction.
+ *      - pipe_handle = The Pipe that caused this callback, or
+ *        -1 if this callback wasn't associated with a pipe.
+ *      - submit_handle = Transfer submit handle causing this
+ *        callback, or -1 if this callback wasn't associated
+ *        with a transfer.
+ *      - Actual number of bytes transfer.
+ *      - user_data = The user pointer supplied to the
+ *        function cvmx_usb_submit() or
+ *        cvmx_usb_register_callback() */
+typedef void (*cvmx_usb_callback_func_t)(cvmx_usb_state_t *state,
+                                         cvmx_usb_callback_t reason,
+                                         cvmx_usb_complete_t status,
+                                         int pipe_handle, int submit_handle,
+                                         int bytes_transferred, void *user_data);
+
+/**
+ * Flags to pass the initialization function.
+ */
+typedef enum
+{
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1<<0,       /**< The USB port uses a 12MHz crystal as clock source
+                                                            at USB_XO and USB_XI. */
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1<<1,      /**< The USB port uses 12/24/48MHz 2.5V board clock
+                                                            source at USB_XO. USB_XI should be tied to GND.*/
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_AUTO = 0,           /**< Automatically determine clock type based on function
+                                                             in cvmx-helper-board.c. */
+    CVMX_USB_INITIALIZE_FLAGS_DEVICE_MODE = 1<<2,       /**< Program the USB port for device mode instead of host mode */
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK  = 3<<3,       /**< Mask for clock speed field */
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1<<3,       /**< Speed of reference clock or crystal */
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2<<3,       /**< Speed of reference clock */
+    CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3<<3,       /**< Speed of reference clock */
+    /* Bits 3-4 used to encode the clock frequency */
+    CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS = 1<<16,  /**< Enable extra console output for debugging USB transfers */
+    CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLBACKS = 1<<17,  /**< Enable extra console output for debugging USB callbacks */
+    CVMX_USB_INITIALIZE_FLAGS_DEBUG_INFO = 1<<18,       /**< Enable extra console output for USB informational data */
+    CVMX_USB_INITIALIZE_FLAGS_DEBUG_CALLS = 1<<19,      /**< Enable extra console output for every function call */
+    CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS = 1<<20,       /**< Enable extra console output for every CSR access */
+    CVMX_USB_INITIALIZE_FLAGS_DEBUG_ALL = ((CVMX_USB_INITIALIZE_FLAGS_DEBUG_CSRS<<1)-1) - (CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS-1),
+} cvmx_usb_initialize_flags_t;
+
+/**
+ * Flags for passing when a pipe is created. Currently no flags
+ * need to be passed.
+ */
+typedef enum
+{
+    CVMX_USB_PIPE_FLAGS_DEBUG_TRANSFERS = 1<<15,/**< Used to display CVMX_USB_INITIALIZE_FLAGS_DEBUG_TRANSFERS for a specific pipe only */
+    __CVMX_USB_PIPE_FLAGS_OPEN = 1<<16,         /**< Used internally to determine if a pipe is open. Do not use */
+    __CVMX_USB_PIPE_FLAGS_SCHEDULED = 1<<17,    /**< Used internally to determine if a pipe is actively using hardware. Do not use */
+    __CVMX_USB_PIPE_FLAGS_NEED_PING = 1<<18,    /**< Used internally to determine if a high speed pipe is in the ping state. Do not use */
+} cvmx_usb_pipe_flags_t;
+
+/**
+ * Return the number of USB ports supported by this Octeon
+ * chip. If the chip doesn't support USB, or is not supported
+ * by this API, a zero will be returned. Most Octeon chips
+ * support one usb port, but some support two ports.
+ * cvmx_usb_initialize() must be called on independent
+ * cvmx_usb_state_t structures.
+ *
+ * @return Number of port, zero if usb isn't supported
+ */
+extern int cvmx_usb_get_num_ports(void);
+
+/**
+ * Initialize a USB port for use. This must be called before any
+ * other access to the Octeon USB port is made. The port starts
+ * off in the disabled state.
+ *
+ * @param state  Pointer to an empty cvmx_usb_state_t structure
+ *               that will be populated by the initialize call.
+ *               This structure is then passed to all other USB
+ *               functions.
+ * @param usb_port_number
+ *               Which Octeon USB port to initialize.
+ * @param flags  Flags to control hardware initialization. See
+ *               cvmx_usb_initialize_flags_t for the flag
+ *               definitions. Some flags are mandatory.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_initialize(cvmx_usb_state_t *state,
+                                             int usb_port_number,
+                                             cvmx_usb_initialize_flags_t flags);
+
+/**
+ * Shutdown a USB port after a call to cvmx_usb_initialize().
+ * The port should be disabled with all pipes closed when this
+ * function is called.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_shutdown(cvmx_usb_state_t *state);
+
+/**
+ * Enable a USB port. After this call succeeds, the USB port is
+ * online and servicing requests.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_enable(cvmx_usb_state_t *state);
+
+/**
+ * Disable a USB port. After this call the USB port will not
+ * generate data transfers and will not generate events.
+ * Transactions in process will fail and call their
+ * associated callbacks.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_disable(cvmx_usb_state_t *state);
+
+/**
+ * Get the current state of the USB port. Use this call to
+ * determine if the usb port has anything connected, is enabled,
+ * or has some sort of error condition. The return value of this
+ * call has "changed" bits to signal of the value of some fields
+ * have changed between calls. These "changed" fields are based
+ * on the last call to cvmx_usb_set_status(). In order to clear
+ * them, you must update the status through cvmx_usb_set_status().
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return Port status information
+ */
+extern cvmx_usb_port_status_t cvmx_usb_get_status(cvmx_usb_state_t *state);
+
+/**
+ * Set the current state of the USB port. The status is used as
+ * a reference for the "changed" bits returned by
+ * cvmx_usb_get_status(). Other than serving as a reference, the
+ * status passed to this function is not used. No fields can be
+ * changed through this call.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param port_status
+ *               Port status to set, most like returned by cvmx_usb_get_status()
+ */
+extern void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t port_status);
+
+/**
+ * Open a virtual pipe between the host and a USB device. A pipe
+ * must be opened before data can be transferred between a device
+ * and Octeon.
+ *
+ * @param state      USB device state populated by
+ *                   cvmx_usb_initialize().
+ * @param flags      Optional pipe flags defined in
+ *                   cvmx_usb_pipe_flags_t.
+ * @param device_addr
+ *                   USB device address to open the pipe to
+ *                   (0-127).
+ * @param endpoint_num
+ *                   USB endpoint number to open the pipe to
+ *                   (0-15).
+ * @param device_speed
+ *                   The speed of the device the pipe is going
+ *                   to. This must match the device's speed,
+ *                   which may be different than the port speed.
+ * @param max_packet The maximum packet length the device can
+ *                   transmit/receive (low speed=0-8, full
+ *                   speed=0-1023, high speed=0-1024). This value
+ *                   comes from the stadnard endpoint descriptor
+ *                   field wMaxPacketSize bits <10:0>.
+ * @param transfer_type
+ *                   The type of transfer this pipe is for.
+ * @param transfer_dir
+ *                   The direction the pipe is in. This is not
+ *                   used for control pipes.
+ * @param interval   For ISOCHRONOUS and INTERRUPT transfers,
+ *                   this is how often the transfer is scheduled
+ *                   for. All other transfers should specify
+ *                   zero. The units are in frames (8000/sec at
+ *                   high speed, 1000/sec for full speed).
+ * @param multi_count
+ *                   For high speed devices, this is the maximum
+ *                   allowed number of packet per microframe.
+ *                   Specify zero for non high speed devices. This
+ *                   value comes from the stadnard endpoint descriptor
+ *                   field wMaxPacketSize bits <12:11>.
+ * @param hub_device_addr
+ *                   Hub device address this device is connected
+ *                   to. Devices connected directly to Octeon
+ *                   use zero. This is only used when the device
+ *                   is full/low speed behind a high speed hub.
+ *                   The address will be of the high speed hub,
+ *                   not and full speed hubs after it.
+ * @param hub_port   Which port on the hub the device is
+ *                   connected. Use zero for devices connected
+ *                   directly to Octeon. Like hub_device_addr,
+ *                   this is only used for full/low speed
+ *                   devices behind a high speed hub.
+ *
+ * @return A non negative value is a pipe handle. Negative
+ *         values are failure codes from cvmx_usb_status_t.
+ */
+extern int cvmx_usb_open_pipe(cvmx_usb_state_t *state,
+                              cvmx_usb_pipe_flags_t flags,
+                              int device_addr, int endpoint_num,
+                              cvmx_usb_speed_t device_speed, int max_packet,
+                              cvmx_usb_transfer_t transfer_type,
+                              cvmx_usb_direction_t transfer_dir, int interval,
+                              int multi_count, int hub_device_addr,
+                              int hub_port);
+
+/**
+ * Call to submit a USB Bulk transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+extern int cvmx_usb_submit_bulk(cvmx_usb_state_t *state, int pipe_handle,
+                                uint64_t buffer, int buffer_length,
+                                cvmx_usb_callback_func_t callback,
+                                void *user_data);
+
+/**
+ * Call to submit a USB Interrupt transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+extern int cvmx_usb_submit_interrupt(cvmx_usb_state_t *state, int pipe_handle,
+                                     uint64_t buffer, int buffer_length,
+                                     cvmx_usb_callback_func_t callback,
+                                     void *user_data);
+
+/**
+ * Call to submit a USB Control transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param control_header
+ *                  USB 8 byte control header physical address.
+ *                  Note that this is NOT A POINTER, but the
+ *                  full 64bit physical address of the buffer.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+extern int cvmx_usb_submit_control(cvmx_usb_state_t *state, int pipe_handle,
+                                   uint64_t control_header,
+                                   uint64_t buffer, int buffer_length,
+                                   cvmx_usb_callback_func_t callback,
+                                   void *user_data);
+
+/**
+ * Flags to pass the cvmx_usb_submit_isochronous() function.
+ */
+typedef enum
+{
+    CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT = 1<<0,  /**< Do not return an error if a transfer is less than the maximum packet size of the device */
+    CVMX_USB_ISOCHRONOUS_FLAGS_ASAP = 1<<1,         /**< Schedule the transaction as soon as possible */
+} cvmx_usb_isochronous_flags_t;
+
+/**
+ * Call to submit a USB Isochronous transfer to a pipe.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param pipe_handle
+ *                  Handle to the pipe for the transfer.
+ * @param start_frame
+ *                  Number of frames into the future to schedule
+ *                  this transaction.
+ * @param flags     Flags to control the transfer. See
+ *                  cvmx_usb_isochronous_flags_t for the flag
+ *                  definitions.
+ * @param number_packets
+ *                  Number of sequential packets to transfer.
+ *                  "packets" is a pointer to an array of this
+ *                  many packet structures.
+ * @param packets   Description of each transfer packet as
+ *                  defined by cvmx_usb_iso_packet_t. The array
+ *                  pointed to here must stay valid until the
+ *                  complete callback is called.
+ * @param buffer    Physical address of the data buffer in
+ *                  memory. Note that this is NOT A POINTER, but
+ *                  the full 64bit physical address of the
+ *                  buffer. This may be zero if buffer_length is
+ *                  zero.
+ * @param buffer_length
+ *                  Length of buffer in bytes.
+ * @param callback  Function to call when this transaction
+ *                  completes. If the return value of this
+ *                  function isn't an error, then this function
+ *                  is guaranteed to be called when the
+ *                  transaction completes. If this parameter is
+ *                  NULL, then the generic callback registered
+ *                  through cvmx_usb_register_callback is
+ *                  called. If both are NULL, then there is no
+ *                  way to know when a transaction completes.
+ * @param user_data User supplied data returned when the
+ *                  callback is called. This is only used if
+ *                  callback in not NULL.
+ *
+ * @return A submitted transaction handle or negative on
+ *         failure. Negative values are failure codes from
+ *         cvmx_usb_status_t.
+ */
+extern int cvmx_usb_submit_isochronous(cvmx_usb_state_t *state, int pipe_handle,
+                                       int start_frame, int flags,
+                                       int number_packets,
+                                       cvmx_usb_iso_packet_t packets[],
+                                       uint64_t buffer, int buffer_length,
+                                       cvmx_usb_callback_func_t callback,
+                                       void *user_data);
+
+/**
+ * Cancel one outstanding request in a pipe. Canceling a request
+ * can fail if the transaction has already completed before cancel
+ * is called. Even after a successful cancel call, it may take
+ * a frame or two for the cvmx_usb_poll() function to call the
+ * associated callback.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe_handle
+ *               Pipe handle to cancel requests in.
+ * @param submit_handle
+ *               Handle to transaction to cancel, returned by the submit function.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_cancel(cvmx_usb_state_t *state,
+                                         int pipe_handle, int submit_handle);
+
+
+/**
+ * Cancel all outstanding requests in a pipe. Logically all this
+ * does is call cvmx_usb_cancel() in a loop.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe_handle
+ *               Pipe handle to cancel requests in.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_cancel_all(cvmx_usb_state_t *state,
+                                             int pipe_handle);
+
+/**
+ * Close a pipe created with cvmx_usb_open_pipe().
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param pipe_handle
+ *               Pipe handle to close.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t. CVMX_USB_BUSY is returned if the
+ *         pipe has outstanding transfers.
+ */
+extern cvmx_usb_status_t cvmx_usb_close_pipe(cvmx_usb_state_t *state,
+                                             int pipe_handle);
+
+/**
+ * Register a function to be called when various USB events occur.
+ *
+ * @param state     USB device state populated by
+ *                  cvmx_usb_initialize().
+ * @param reason    Which event to register for.
+ * @param callback  Function to call when the event occurs.
+ * @param user_data User data parameter to the function.
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_register_callback(cvmx_usb_state_t *state,
+                                                    cvmx_usb_callback_t reason,
+                                                    cvmx_usb_callback_func_t callback,
+                                                    void *user_data);
+
+/**
+ * Get the current USB protocol level frame number. The frame
+ * number is always in the range of 0-0x7ff.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return USB frame number
+ */
+extern int cvmx_usb_get_frame_number(cvmx_usb_state_t *state);
+
+/**
+ * Poll the USB block for status and call all needed callback
+ * handlers. This function is meant to be called in the interrupt
+ * handler for the USB controller. It can also be called
+ * periodically in a loop for non-interrupt based operation.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_poll(cvmx_usb_state_t *state);
+
+/**
+ * Enable an endpoint for use in device mode. After this call
+ * transactions will be allowed over the endpoint. This must be
+ * called after every usb reset.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param endpoint_num
+ *               The endpoint number to enable (0-4)
+ * @param transfer_type
+ *               USB transfer type of this endpoint
+ * @param transfer_dir
+ *               Direction of transfer relative to Octeon
+ * @param max_packet_size
+ *               Maximum packet size support by this endpoint
+ * @param buffer Buffer to send/receive
+ * @param buffer_length
+ *               Length of the buffer in bytes
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_device_enable_endpoint(cvmx_usb_state_t *state,
+                                                  int endpoint_num,
+                                                  cvmx_usb_transfer_t transfer_type,
+                                                  cvmx_usb_direction_t transfer_dir,
+                                                  int max_packet_size,
+                                                  uint64_t buffer,
+                                                  int buffer_length);
+
+/**
+ * Disable an endpoint in device mode.
+ *
+ * @param state  USB device state populated by
+ *               cvmx_usb_initialize().
+ * @param endpoint_num
+ *               The endpoint number to disable (0-4)
+ *
+ * @return CVMX_USB_SUCCESS or a negative error code defined in
+ *         cvmx_usb_status_t.
+ */
+extern cvmx_usb_status_t cvmx_usb_device_disable_endpoint(cvmx_usb_state_t *state,
+                                                          int endpoint_num);
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_USB_H__ */
diff --git a/cvmx-utils.h b/cvmx-utils.h
new file mode 100644
index 0000000000000..32d87a180f54b
--- /dev/null
+++ b/cvmx-utils.h
@@ -0,0 +1,283 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+/**
+ * @file
+ * Small utility functions and macros to ease programming of Octeon.
+ *
+ * <hr>$Revision: 38306 $<hr>
+*/
+#ifndef __CVMX_UTILS_H__
+#define __CVMX_UTILS_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifndef TRUE
+#define FALSE   0
+#define TRUE    (!(FALSE))
+#endif
+
+/*
+ * The macros cvmx_likely and cvmx_unlikely use the
+ * __builtin_expect GCC operation to control branch
+ * probabilities for a conditional. For example, an "if"
+ * statement in the code that will almost always be
+ * executed should be written as "if (cvmx_likely(...))".
+ * If the "else" section of an if statement is more
+ * probable, use "if (cvmx_unlikey(...))".
+ */
+#define cvmx_likely(x)      __builtin_expect(!!(x), 1)
+#define cvmx_unlikely(x)    __builtin_expect(!!(x), 0)
+
+#if CVMX_ENABLE_DEBUG_PRINTS
+    #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+        #define cvmx_dprintf        printk
+    #else
+        #define cvmx_dprintf        printf
+    #endif
+#else
+    static inline void cvmx_dprintf(const char *format, ...) __attribute__ ((format(printf, 1, 2)));
+    static inline void cvmx_dprintf(const char *format, ...)
+    {
+        /* Prints are disbled, do nothing */
+    }
+#endif
+
+#define CAST64(v) ((long long)(long)(v))
+#define CASTPTR(type, v) ((type *)(long)(v))
+#define CVMX_MAX_CORES          (16)
+#define CVMX_CACHE_LINE_SIZE    (128)   // In bytes
+#define CVMX_CACHE_LINE_MASK    (CVMX_CACHE_LINE_SIZE - 1)   // In bytes
+#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned (CVMX_CACHE_LINE_SIZE)))
+
+/**
+ * This macro spins on a field waiting for it to reach a value. It
+ * is common in code to need to wait for a specific field in a CSR
+ * to match a specific value. Conceptually this macro expands to:
+ *
+ * 1) read csr at "address" with a csr typedef of "type"
+ * 2) Check if ("type".s."field" "op" "value")
+ * 3) If #2 isn't true loop to #1 unless too much time has passed.
+ */
+#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
+    ({int result;                                                       \
+    do {                                                                \
+        uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec *     \
+                           cvmx_sysinfo_get()->cpu_clock_hz / 1000000;  \
+        type c;                                                         \
+        while (1)                                                       \
+        {                                                               \
+            c.u64 = cvmx_read_csr(address);                             \
+            if ((c.s.field) op (value)) {                               \
+                result = 0;                                             \
+                break;                                                  \
+            } else if (cvmx_get_cycle() > done) {                       \
+                result = -1;                                            \
+                break;                                                  \
+            } else                                                      \
+                cvmx_wait(100);                                         \
+        }                                                               \
+    } while (0);                                                        \
+    result;})
+
+/**
+ * Builds a bit mask given the required size in bits.
+ *
+ * @param bits   Number of bits in the mask
+ * @return The mask
+ */
+static inline uint64_t cvmx_build_mask(uint64_t bits)
+{
+    return ~((~0x0ull) << bits);
+}
+
+
+/**
+ * Builds a memory address for I/O based on the Major and Sub DID.
+ *
+ * @param major_did 5 bit major did
+ * @param sub_did   3 bit sub did
+ * @return I/O base address
+ */
+static inline uint64_t cvmx_build_io_address(uint64_t major_did, uint64_t sub_did)
+{
+    return ((0x1ull << 48) | (major_did << 43) | (sub_did << 40));
+}
+
+
+/**
+ * Perform mask and shift to place the supplied value into
+ * the supplied bit rage.
+ *
+ * Example: cvmx_build_bits(39,24,value)
+ * <pre>
+ * 6       5       4       3       3       2       1
+ * 3       5       7       9       1       3       5       7      0
+ * +-------+-------+-------+-------+-------+-------+-------+------+
+ * 000000000000000000000000___________value000000000000000000000000
+ * </pre>
+ *
+ * @param high_bit Highest bit value can occupy (inclusive) 0-63
+ * @param low_bit  Lowest bit value can occupy inclusive 0-high_bit
+ * @param value    Value to use
+ * @return Value masked and shifted
+ */
+static inline uint64_t cvmx_build_bits(uint64_t high_bit, uint64_t low_bit, uint64_t value)
+{
+    return ((value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit);
+}
+
+
+/**
+ * Return the number of cores available in the chip
+ *
+ * @return
+ */
+static inline uint32_t cvmx_octeon_num_cores(void)
+{
+    uint32_t ciu_fuse = (uint32_t)cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
+    return cvmx_pop(ciu_fuse);
+}
+
+
+/**
+ * Return true if Octeon is CN38XX pass 1
+ *
+ * @return
+ */
+static inline int cvmx_octeon_is_pass1(void)
+{
+    return OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1);
+}
+
+
+/**
+ * Return true if Octeon is CN36XX
+ *
+ * @return
+ */
+static inline int cvmx_octeon_model_CN36XX(void)
+{
+    return(OCTEON_IS_MODEL(OCTEON_CN38XX)
+           && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
+           &&cvmx_fuse_read(264));
+}
+
+
+/**
+ * @deprecated
+ * Determine if Octeon supports the DFA state machines. This function is
+ * deprecated, use octeon_has_feature(OCTEON_FEATURE_DFA) instead.
+ *
+ * @return Non zero if DFA is supported
+ */
+static inline int cvmx_octeon_dfa_present(void) __attribute__((deprecated));
+static inline int cvmx_octeon_dfa_present(void)
+{
+    return octeon_has_feature(OCTEON_FEATURE_DFA);
+}
+
+
+/**
+ * @deprecated
+ * Determine if Octeon supports ZIP. This function is deprecated, use
+ * octeon_has_feature(OCTEON_FEATURE_ZIP) instead.
+ *
+ * @return Non zero if DFA is supported
+ */
+static inline int cvmx_octeon_zip_present(void) __attribute__((deprecated));
+static inline int cvmx_octeon_zip_present(void)
+{
+    return octeon_has_feature(OCTEON_FEATURE_ZIP);
+}
+
+
+/**
+ * @deprecated
+ * Determine if Octeon supports Crypto acceleration. This function is
+ * deprecated, use octeon_has_feature(OCTEON_FEATURE_CRYPTO) instead.
+ *
+ * @return Non zero if DFA is supported
+ */
+static inline int cvmx_octeon_crypto_present(void) __attribute__((deprecated));
+static inline int cvmx_octeon_crypto_present(void)
+{
+    return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
+}
+
+
+/**
+ * @deprecated
+ * This function is a trival wrapper around cvmx_read64_uint64(). Use
+ * cvmx_read64_uint64() instead as this function is deprecated.
+ *
+ * @param address
+ *
+ * @return
+ */
+static inline uint64_t cvmx_read64(uint64_t address) __attribute__((deprecated));
+static inline uint64_t cvmx_read64(uint64_t address)
+{
+    return cvmx_read64_uint64(address);
+}
+
+
+/**
+ * @deprecated
+ * This function is a trival wrapper around cvmx_write64_uint64(). Use
+ * cvmx_write64_uint64() instead as this function is deprecated.
+ *
+ * @param address Location to write ro
+ * @param value Value to write
+ *
+ * @return
+ */
+static inline void cvmx_write64(uint64_t address, uint64_t value) __attribute__((deprecated));
+static inline void cvmx_write64(uint64_t address, uint64_t value)
+{
+    cvmx_write64_uint64(address, value);
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_UTILS_H__ */
+
diff --git a/cvmx-version.h b/cvmx-version.h
new file mode 100644
index 0000000000000..292d29186c560
--- /dev/null
+++ b/cvmx-version.h
@@ -0,0 +1,12 @@
+/* Version information is made available at compile time in two forms:
+** 1) a version string for printing
+** 2) a combined SDK version and build number, suitable for comparisons
+**    to determine what SDK version is being used.
+**    SDK 1.2.3 build 567 => 102030567
+**    Note that 2 digits are used for each version number, so that:
+**     1.9.0  == 01.09.00 < 01.10.00 == 1.10.0 
+**     10.9.0 == 10.09.00 > 09.10.00 == 9.10.0 
+** 
+*/ 
+#define OCTEON_SDK_VERSION_NUM  109000312ull
+#define OCTEON_SDK_VERSION_STRING   "Cavium Networks Octeon SDK version 1.9.0, build 312"
diff --git a/cvmx-warn.c b/cvmx-warn.c
new file mode 100644
index 0000000000000..a450d13551232
--- /dev/null
+++ b/cvmx-warn.c
@@ -0,0 +1,79 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for warning users about errors and such.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#include "cvmx.h"
+#include "cvmx-warn.h"
+
+void cvmx_warn(const char *format, ...)
+{
+#ifdef CVMX_BUILD_FOR_UBOOT
+    DECLARE_GLOBAL_DATA_PTR;
+    if (!gd->have_console)
+    {
+        /* If the serial port is not set up yet,
+        ** save pointer to error message (most likely a constant in flash)
+        ** to print out once we can. */
+        gd->err_msg = (void *)format;
+        return;
+    }
+#endif
+    va_list args;
+    va_start(args, format);
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    printk("WARNING:");
+    vprintk(format, args);
+#else
+    printf("WARNING:\n");
+    vprintf(format, args);
+#endif
+    va_end(args);
+}
+
diff --git a/cvmx-warn.h b/cvmx-warn.h
new file mode 100644
index 0000000000000..57fa14a31d07b
--- /dev/null
+++ b/cvmx-warn.h
@@ -0,0 +1,72 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Functions for warning users about errors and such.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ */
+#ifndef __CVMX_WARN_H__
+#define __CVMX_WARN_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#ifdef printf
+extern void cvmx_warn(const char *format, ...);
+#else
+extern void cvmx_warn(const char *format, ...) __attribute__ ((format(printf, 1, 2)));
+#endif
+
+#define cvmx_warn_if(expression, format, ...) if (expression) cvmx_warn(format, ##__VA_ARGS__)
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_WARN_H__ */
+
diff --git a/cvmx-wqe.h b/cvmx-wqe.h
new file mode 100644
index 0000000000000..98c7e10549c54
--- /dev/null
+++ b/cvmx-wqe.h
@@ -0,0 +1,315 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * This header file defines the work queue entry (wqe) data structure.
+ * Since this is a commonly used structure that depends on structures
+ * from several hardware blocks, those definitions have been placed
+ * in this file to create a single point of definition of the wqe
+ * format.
+ * Data structures are still named according to the block that they
+ * relate to.
+ *
+ * This file must not depend on any other header files, except for cvmx.h!!!
+ *
+ *
+ * <hr>$Revision: 41586 $<hr>
+ *
+ *
+ */
+
+
+#ifndef __CVMX_WQE_H__
+#define __CVMX_WQE_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#define OCT_TAG_TYPE_STRING(x) (((x) == CVMX_POW_TAG_TYPE_ORDERED) ?  "ORDERED" : \
+                                (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ?  "ATOMIC" : \
+                                (((x) == CVMX_POW_TAG_TYPE_NULL) ?  "NULL" : \
+                                "NULL_NULL")))
+
+
+/**
+ * HW decode / err_code in work queue entry
+ */
+typedef union
+{
+    uint64_t                 u64;
+
+    /** Use this struct if the hardware determines that the packet is IP */
+    struct
+    {
+        uint64_t               bufs          : 8; /**< HW sets this to the number of buffers used by this packet */
+        uint64_t               ip_offset     : 8; /**< HW sets to the number of L2 bytes prior to the IP */
+        uint64_t               vlan_valid    : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
+        uint64_t               vlan_stacked  : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
+        uint64_t               unassigned    : 1;
+        uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+        uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+        uint64_t               pr            : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
+        uint64_t               unassigned2   : 8;
+        uint64_t               dec_ipcomp    : 1; /**< the packet needs to be decompressed */
+        uint64_t               tcp_or_udp    : 1; /**< the packet is either TCP or UDP */
+        uint64_t               dec_ipsec     : 1; /**< the packet needs to be decrypted (ESP or AH) */
+        uint64_t               is_v6         : 1; /**< the packet is IPv6 */
+
+        // (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.)
+
+        uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
+        // exceptional conditions below
+        uint64_t               L4_error      : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
+                                                    (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
+                                                    failure indicated in err_code below, decode:
+                                                    - 1 = Malformed L4
+                                                    - 2 = L4 Checksum Error: the L4 checksum value is
+                                                    - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
+                                                        remains in the IP packet (as defined by the IP header length field).
+                                                    - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
+                                                    - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
+                                                    - 9 = TCP No Flags: the packet is TCP and no flags are set.
+                                                    - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
+                                                    - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
+                                                    - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
+                                                    - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
+
+
+
+        uint64_t               is_frag       : 1; /**< set if the packet is a fragment */
+        uint64_t               IP_exc        : 1; /**< the receive interface hardware detected an IP error / exception
+                                                    (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
+                                                    - 1 = Not IP: the IP version field is neither 4 nor 6.
+                                                    - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
+                                                    - 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
+                                                    - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
+                                                        header. Pad is allowed.
+                                                    - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
+                                                    - 6 = IP Options */
+
+        uint64_t               is_bcast      : 1; /**< set if the hardware determined that the packet is a broadcast */
+        uint64_t               is_mcast      : 1; /**< set if the hardware determined that the packet is a multi-cast */
+        uint64_t               not_IP        : 1; /**< set if the packet may not be IP (must be zero in this case) */
+        uint64_t               rcv_error     : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
+        /* lower err_code = first-level descriptor of the work */
+        /* zero for packet submitted by hardware that isn't on the slow path */
+
+        uint64_t               err_code      : 8; /**< type is cvmx_pip_err_t */
+    } s;
+
+    /**< use this to get at the 16 vlan bits */
+    struct
+    {
+        uint64_t               unused1       :16;
+        uint64_t               vlan          :16;
+        uint64_t               unused2       :32;
+    } svlan;
+
+    /**< use this struct if the hardware could not determine that the packet is ip */
+    struct
+    {
+        uint64_t               bufs          : 8; /**< HW sets this to the number of buffers used by this packet */
+        uint64_t               unused        : 8;
+        uint64_t               vlan_valid    : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
+        uint64_t               vlan_stacked  : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
+        uint64_t               unassigned    : 1;
+        uint64_t               vlan_cfi      : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+        uint64_t               vlan_id       :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+        uint64_t               pr            : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
+        uint64_t               unassigned2   :12;
+        uint64_t               software      : 1; /**< reserved for software use, hardware will clear on packet creation */
+        uint64_t               unassigned3   : 1;
+        uint64_t               is_rarp       : 1; /**< set if the hardware determined that the packet is rarp */
+        uint64_t               is_arp        : 1; /**< set if the hardware determined that the packet is arp */
+        uint64_t               is_bcast      : 1; /**< set if the hardware determined that the packet is a broadcast */
+        uint64_t               is_mcast      : 1; /**< set if the hardware determined that the packet is a multi-cast */
+        uint64_t               not_IP        : 1; /**< set if the packet may not be IP (must be one in this case) */
+        uint64_t               rcv_error     : 1; /**< the receive interface hardware detected a receive error.
+                                                    Failure indicated in err_code below, decode:
+                                                    - 1 = partial error: a packet was partially received, but internal
+                                                        buffering / bandwidth was not adequate to receive the entire packet.
+                                                    - 2 = jabber error: the RGMII packet was too large and is truncated.
+                                                    - 3 = overrun error: the RGMII packet is longer than allowed and had
+                                                        an FCS error.
+                                                    - 4 = oversize error: the RGMII packet is longer than allowed.
+                                                    - 5 = alignment error: the RGMII packet is not an integer number of bytes
+                                                        and had an FCS error (100M and 10M only).
+                                                    - 6 = fragment error: the RGMII packet is shorter than allowed and had an
+                                                        FCS error.
+                                                    - 7 = GMX FCS error: the RGMII packet had an FCS error.
+                                                    - 8 = undersize error: the RGMII packet is shorter than allowed.
+                                                    - 9 = extend error: the RGMII packet had an extend error.
+                                                    - 10 = length mismatch error: the RGMII packet had a length that did not
+                                                        match the length field in the L2 HDR.
+                                                    - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
+                                                        data reception errors (RXERR) or the SPI4 packet had one or more DIP4
+                                                        errors.
+                                                    - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
+                                                        enough to cover the skipped bytes or the SPI4 packet was terminated
+                                                        with an About EOPS.
+                                                    - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
+                                                        studder error (data not repeated - 10/100M only) or the SPI4 packet
+                                                        was sent to an NXA.
+                                                    - 16 = FCS error: a SPI4.2 packet had an FCS error.
+                                                    - 17 = Skip error: a packet was not large enough to cover the skipped bytes.
+                                                    - 18 = L2 header malformed: the packet is not long enough to contain the L2 */
+
+
+        /* lower err_code = first-level descriptor of the work */
+        /* zero for packet submitted by hardware that isn't on the slow path */
+        uint64_t               err_code       : 8; // type is cvmx_pip_err_t (union, so can't use directly
+    } snoip;
+
+} cvmx_pip_wqe_word2;
+
+
+
+
+
+
+
+
+/**
+ * Work queue entry format
+ *
+ * must be 8-byte aligned
+ */
+typedef struct
+{
+
+    /*****************************************************************
+     * WORD 0
+     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     */
+
+    /**
+     * raw chksum result generated by the HW
+     */
+    uint16_t                   hw_chksum;
+    /**
+     * Field unused by hardware - available for software
+     */
+    uint8_t                    unused;
+    /**
+     * Next pointer used by hardware for list maintenance.
+     * May be written/read by HW before the work queue
+     *           entry is scheduled to a PP
+     * (Only 36 bits used in Octeon 1)
+     */
+    uint64_t                   next_ptr      : 40;
+
+
+    /*****************************************************************
+     * WORD 1
+     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     */
+
+    /**
+     * HW sets to the total number of bytes in the packet
+     */
+    uint64_t                   len           :16;
+    /**
+     * HW sets this to input physical port
+     */
+    uint64_t                   ipprt         : 6;
+
+    /**
+     * HW sets this to what it thought the priority of the input packet was
+     */
+    uint64_t                   qos           : 3;
+
+    /**
+     * the group that the work queue entry will be scheduled to
+     */
+    uint64_t                   grp           : 4;
+    /**
+     * the type of the tag (ORDERED, ATOMIC, NULL)
+     */
+    cvmx_pow_tag_type_t        tag_type      : 3;
+    /**
+     * the synchronization/ordering tag
+     */
+    uint64_t                   tag           :32;
+
+    /**
+     * WORD 2
+     *   HW WRITE: the following 64-bits are filled in by hardware when a packet arrives
+     *   This indicates a variety of status and error conditions.
+     */
+    cvmx_pip_wqe_word2       word2;
+
+    /**
+     * Pointer to the first segment of the packet.
+     */
+    cvmx_buf_ptr_t             packet_ptr;
+
+    /**
+     *   HW WRITE: octeon will fill in a programmable amount from the
+     *             packet, up to (at most, but perhaps less) the amount
+     *             needed to fill the work queue entry to 128 bytes
+     *   If the packet is recognized to be IP, the hardware starts (except that
+     *   the IPv4 header is padded for appropriate alignment) writing here where
+     *   the IP header starts.
+     *   If the packet is not recognized to be IP, the hardware starts writing
+     *   the beginning of the packet here.
+     */
+    uint8_t packet_data[96];
+
+
+    /**
+     * If desired, SW can make the work Q entry any length. For the
+     * purposes of discussion here, Assume 128B always, as this is all that
+     * the hardware deals with.
+     *
+     */
+
+}  CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* __CVMX_WQE_H__ */
diff --git a/cvmx-zip.c b/cvmx-zip.c
new file mode 100644
index 0000000000000..a80c54bdb391f
--- /dev/null
+++ b/cvmx-zip.c
@@ -0,0 +1,127 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Source file for the zip (deflate) block
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-cmd-queue.h"
+#include "cvmx-zip.h"
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+
+/**
+ * Initialize the ZIP block
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_initialize(void)
+{
+    cvmx_zip_cmd_buf_t zip_cmd_buf;
+    cvmx_cmd_queue_result_t result;
+    result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_ZIP, 0,
+                                       CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                       CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
+    if (result != CVMX_CMD_QUEUE_SUCCESS)
+        return -1;
+
+    zip_cmd_buf.u64 = 0;
+    zip_cmd_buf.s.dwb = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
+    zip_cmd_buf.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
+    zip_cmd_buf.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
+    zip_cmd_buf.s.ptr =  cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_ZIP))>>7;
+    cvmx_write_csr(CVMX_ZIP_CMD_BUF, zip_cmd_buf.u64);
+    cvmx_write_csr(CVMX_ZIP_ERROR, 1);
+    cvmx_read_csr(CVMX_ZIP_CMD_BUF); /* Read to make sure setup is complete */
+    return 0;
+}
+
+/**
+ * Shutdown the ZIP block. ZIP must be idle when
+ * this function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_shutdown(void)
+{
+    cvmx_zip_cmd_ctl_t zip_cmd_ctl;
+
+    if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_ZIP))
+    {
+        cvmx_dprintf("ERROR: cvmx_zip_shutdown: ZIP not idle.\n");
+        return -1;
+    }
+
+    zip_cmd_ctl.u64 = cvmx_read_csr(CVMX_ZIP_CMD_CTL);
+    zip_cmd_ctl.s.reset = 1;
+    cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64);
+    cvmx_wait(100);
+
+    cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_ZIP);
+    return 0;
+}
+
+/**
+ * Submit a command to the ZIP block
+ *
+ * @param command Zip command to submit
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_submit(cvmx_zip_command_t *command)
+{
+    cvmx_cmd_queue_result_t result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_ZIP, 1, 8, command->u64);
+    if (result == CVMX_CMD_QUEUE_SUCCESS)
+        cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(7, 0)), 8);
+    return result;
+}
+
+#endif
+
diff --git a/cvmx-zip.h b/cvmx-zip.h
new file mode 100644
index 0000000000000..0a7d876a0d4cf
--- /dev/null
+++ b/cvmx-zip.h
@@ -0,0 +1,247 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Header file for the zip (deflate) block
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __CVMX_ZIP_H__
+#define __CVMX_ZIP_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef union {
+   uint64_t u64;
+   struct {
+#if __BYTE_ORDER == __BIG_ENDIAN
+      uint64_t unused              :  5;
+      uint64_t full_block_write    :  1;
+      uint64_t no_l2_alloc         :  1;
+      uint64_t little_endian       :  1;
+      uint64_t length              : 16;
+      uint64_t ptr                 : 40;
+#else
+      uint64_t ptr                 : 40;
+      uint64_t length              : 16;
+      uint64_t little_endian       :  1;
+      uint64_t no_l2_alloc         :  1;
+      uint64_t full_block_write    :  1;
+      uint64_t unused              :  5;
+#endif
+   } s;
+} cvmx_zip_ptr_t;
+#define CVMX_ZIP_PTR_MAX_LEN    ((1 << 16) - 1)
+
+
+typedef enum {
+   CVMX_ZIP_COMPLETION_NOTDONE  = 0,
+   CVMX_ZIP_COMPLETION_SUCCESS  = 1,
+   CVMX_ZIP_COMPLETION_OTRUNC   = 2,
+   CVMX_ZIP_COMPLETION_STOP     = 3,
+   CVMX_ZIP_COMPLETION_ITRUNC   = 4,
+   CVMX_ZIP_COMPLETION_RBLOCK   = 5,
+   CVMX_ZIP_COMPLETION_NLEN     = 6,
+   CVMX_ZIP_COMPLETION_BADCODE  = 7,
+   CVMX_ZIP_COMPLETION_BADCODE2 = 8,
+   CVMX_ZIP_COMPLETION_ZERO_LEN = 9,
+   CVMX_ZIP_COMPLETION_PARITY   = 10
+} cvmx_zip_completion_code_t;
+
+typedef union {
+   uint64_t u64[3];
+   struct {
+
+      // WORD 0
+#if __BYTE_ORDER == __BIG_ENDIAN
+      uint64_t crc32               : 32;
+      uint64_t adler               : 32;
+#else
+      uint64_t adler               : 32;
+      uint64_t crc32               : 32;
+#endif
+
+      // WORD 1
+#if __BYTE_ORDER == __BIG_ENDIAN
+      uint64_t totalbyteswritten   : 32;
+      uint64_t totalbytesread      : 32;
+#else
+      uint64_t totalbytesread      : 32;
+      uint64_t totalbyteswritten   : 32;
+#endif
+
+      // WORD 2
+#if __BYTE_ORDER == __BIG_ENDIAN
+      uint64_t                      totalbitsprocessed  : 32; // decompression only
+      uint64_t                      unused20            :  5;
+      uint64_t                      exnum               :  3; // compression only
+      uint64_t                      unused21            :  1;
+      uint64_t                      exbits              :  7; // compression only
+      uint64_t                      unused22            :  7;
+      uint64_t                      eof                 :  1; // decompression only
+      cvmx_zip_completion_code_t    completioncode      :  8; // If polling, SW should set this to zero and wait for non-zero
+#else
+      cvmx_zip_completion_code_t    completioncode      :  8; // If polling, SW should set this to zero and wait for non-zero
+      uint64_t                      eof                 :  1; // decompression only
+      uint64_t                      unused22            :  7;
+      uint64_t                      exbits              :  7; // compression only
+      uint64_t                      unused21            :  1;
+      uint64_t                      exnum               :  3; // compression only
+      uint64_t                      unused20            :  5;
+      uint64_t                      totalbitsprocessed  : 32; // decompression only
+#endif
+   } s;
+} cvmx_zip_result_t;
+
+typedef union {
+   uint64_t u64[8];
+   struct {
+
+      // WORD 0
+#if __BYTE_ORDER == __BIG_ENDIAN
+      uint64_t unused00            :  8;
+      uint64_t totaloutputlength   : 24;
+      uint64_t unused01            :  5;
+      uint64_t exnum               :  3;
+      uint64_t unused02            :  1;
+      uint64_t exbits              :  7;
+      uint64_t unused03            :  6;
+      uint64_t speed               :  1;
+      uint64_t forcefixed          :  1;
+      uint64_t forcedynamic        :  1;
+      uint64_t eof                 :  1;
+      uint64_t bof                 :  1;
+      uint64_t compress            :  1;
+      uint64_t unused04            :  1;
+      uint64_t dscatter            :  1;
+      uint64_t dgather             :  1;
+      uint64_t hgather             :  1;
+#else
+      uint64_t hgather             :  1;
+      uint64_t dgather             :  1;
+      uint64_t dscatter            :  1;
+      uint64_t unused04            :  1;
+      uint64_t compress            :  1;
+      uint64_t bof                 :  1;
+      uint64_t eof                 :  1;
+      uint64_t forcedynamic        :  1;
+      uint64_t forcefixed          :  1;
+      uint64_t speed               :  1;
+      uint64_t unused03            :  6;
+      uint64_t exbits              :  7;
+      uint64_t unused02            :  1;
+      uint64_t exnum               :  3;
+      uint64_t unused01            :  5;
+      uint64_t totaloutputlength   : 24;
+      uint64_t unused00            :  8;
+#endif
+
+      // WORD 1
+#if __BYTE_ORDER == __BIG_ENDIAN
+      uint64_t historylength       : 16;
+      uint64_t unused10            : 16;
+      uint64_t adler32             : 32;
+#else
+      uint64_t adler32             : 32;
+      uint64_t unused10            : 16;
+      uint64_t historylength       : 16;
+#endif
+
+      // WORD 2
+      cvmx_zip_ptr_t ctx_ptr;
+
+      // WORD 3
+      cvmx_zip_ptr_t hist_ptr;
+
+      // WORD 4
+      cvmx_zip_ptr_t in_ptr;
+
+      // WORD 5
+      cvmx_zip_ptr_t out_ptr;
+
+      // WORD 6
+      cvmx_zip_ptr_t result_ptr;
+
+      // WORD 7
+      cvmx_zip_ptr_t wq_ptr;
+
+   } s;
+} cvmx_zip_command_t;
+
+
+/**
+ * Initialize the ZIP block
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_initialize(void);
+
+/**
+ * Shutdown the ZIP block. ZIP must be idle when
+ * this function is called.
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_shutdown(void);
+
+/**
+ * Submit a command to the ZIP block
+ *
+ * @param command Zip command to submit
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_zip_submit(cvmx_zip_command_t *command);
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /* __CVMX_ZIP_H__ */
diff --git a/cvmx-zone.c b/cvmx-zone.c
new file mode 100644
index 0000000000000..932cde2864700
--- /dev/null
+++ b/cvmx-zone.c
@@ -0,0 +1,169 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * Support library for the Zone Allocator.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#include "cvmx-malloc.h"
+
+
+
+
+cvmx_zone_t cvmx_zone_create_from_addr(char *name, uint32_t elem_size, uint32_t num_elem,
+                             void* mem_ptr, uint64_t mem_size, uint32_t flags)
+{
+    cvmx_zone_t zone;
+    unsigned int i;
+
+    if ((unsigned long)mem_ptr & (sizeof(void *) -1))
+    {
+        return(NULL);  //invalid alignment
+    }
+    if (mem_size  < sizeof(struct cvmx_zone) + elem_size * num_elem)
+    {
+        return(NULL);  // not enough room
+    }
+
+    zone = (cvmx_zone_t) ((char *)mem_ptr + elem_size * num_elem);
+    zone->elem_size = elem_size;
+    zone->num_elem = num_elem;
+    zone->name = name;
+    zone->align = 0;  // not used
+    zone->baseptr = NULL;
+    zone->freelist = NULL;
+    zone->lock.value = CVMX_SPINLOCK_UNLOCKED_VAL;
+
+    zone->baseptr = (char *)mem_ptr;
+
+    for(i=0;i<num_elem;i++)
+    {
+        *(void **)(zone->baseptr + (i*elem_size)) = zone->freelist;
+        zone->freelist = (void *)(zone->baseptr + (i*elem_size));
+    }
+
+    return(zone);
+
+}
+
+cvmx_zone_t cvmx_zone_create_from_arena(char *name, uint32_t elem_size, uint32_t num_elem, uint32_t align, cvmx_arena_list_t arena_list, uint32_t flags)
+{
+    unsigned int i;
+    cvmx_zone_t zone;
+
+    zone = (cvmx_zone_t)cvmx_malloc(arena_list, sizeof(struct cvmx_zone));
+
+    if (NULL == zone)
+    {
+        return(NULL);
+    }
+    zone->elem_size = elem_size;
+    zone->num_elem = num_elem;
+    zone->name = name;
+    zone->align = align;
+    zone->baseptr = NULL;
+    zone->freelist = NULL;
+    zone->lock.value = CVMX_SPINLOCK_UNLOCKED_VAL;
+
+    zone->baseptr = (char *)cvmx_memalign(arena_list, align, num_elem * elem_size);
+    if (NULL == zone->baseptr)
+    {
+        return(NULL);
+    }
+
+    for(i=0;i<num_elem;i++)
+    {
+        *(void **)(zone->baseptr + (i*elem_size)) = zone->freelist;
+        zone->freelist = (void *)(zone->baseptr + (i*elem_size));
+    }
+
+    return(zone);
+
+}
+
+
+
+void * cvmx_zone_alloc(cvmx_zone_t zone, uint32_t flags)
+{
+    cvmx_zone_t item;
+
+    assert(zone != NULL);
+    assert(zone->baseptr != NULL);
+    cvmx_spinlock_lock(&zone->lock);
+
+	item = (cvmx_zone_t)zone->freelist;
+	if(item != NULL)
+	{
+		zone->freelist = *(void **)item;
+	}
+	else
+	{
+//		cvmx_dprintf("No more elements in zone %s\n", zone->name);
+	}
+
+    cvmx_spinlock_unlock(&zone->lock);
+    return(item);
+}
+
+void cvmx_zone_free(cvmx_zone_t zone, void *ptr)
+{
+
+    assert(zone != NULL);
+    assert(zone->baseptr != NULL);
+    assert((unsigned long)ptr - (unsigned long)zone->baseptr < zone->num_elem * zone->elem_size);
+
+    cvmx_spinlock_lock(&zone->lock);
+	*(void **)ptr = zone->freelist;
+	zone->freelist = ptr;
+    cvmx_spinlock_unlock(&zone->lock);
+}
+
+
diff --git a/cvmx.h b/cvmx.h
new file mode 100644
index 0000000000000..f696a7a685a8f
--- /dev/null
+++ b/cvmx.h
@@ -0,0 +1,90 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+/**
+ * @file
+ *
+ * Main Octeon executive header file (This should be the second header
+ * file included by an application).
+ *
+ * <hr>$Revision: 41586 $<hr>
+*/
+#ifndef __CVMX_H__
+#define __CVMX_H__
+
+/* Control whether simple executive applications use 1-1 TLB mappings to access physical
+** memory addresses.  This must be disabled to allow large programs that use more than
+** the 0x10000000 - 0x20000000 virtual address range.
+*/
+#ifndef CVMX_USE_1_TO_1_TLB_MAPPINGS
+#define CVMX_USE_1_TO_1_TLB_MAPPINGS 1
+#endif
+
+#ifndef CVMX_ENABLE_PARAMETER_CHECKING
+#define CVMX_ENABLE_PARAMETER_CHECKING 1
+#endif
+
+#ifndef CVMX_ENABLE_DEBUG_PRINTS
+#define CVMX_ENABLE_DEBUG_PRINTS 1
+#endif
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#include "cvmx-platform.h"
+#include "cvmx-access.h"
+#include "cvmx-address.h"
+#include "cvmx-asm.h"
+#include "cvmx-packet.h"
+#include "cvmx-warn.h"
+#include "cvmx-sysinfo.h"
+#include "octeon-model.h"
+#include "cvmx-csr.h"
+#include "cvmx-utils.h"
+
+#if defined(__mips__) && !defined(CVMX_BUILD_FOR_LINUX_HOST)
+#include "cvmx-access-native.h"
+#endif
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif  /*  __CVMX_H__  */
diff --git a/cvmx.mk b/cvmx.mk
new file mode 100644
index 0000000000000..becb04fdf35c3
--- /dev/null
+++ b/cvmx.mk
@@ -0,0 +1,144 @@
+#/***********************license start***************
+# Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
+# reserved.
+#
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#
+#     * Neither the name of Cavium Networks nor the names of
+#       its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written
+#       permission.
+#
+# TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+# AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+# OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+# RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+# REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+# DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+# OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+# PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+# POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+# OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+#
+#
+# For any questions regarding licensing please contact marketing@caviumnetworks.com
+#
+# ***********************license end**************************************/
+
+#
+#  component Makefile fragment
+#
+
+#  standard component Makefile header
+sp              :=  $(sp).x
+dirstack_$(sp)  :=  $(d)
+d               :=  $(dir)
+
+#  component specification
+
+LIBRARY := $(OBJ_DIR)/libcvmx.a
+
+OBJS_$(d)  :=  \
+	$(OBJ_DIR)/cvmx-bootmem.o \
+	$(OBJ_DIR)/cvmx-cn3010-evb-hs5.o \
+	$(OBJ_DIR)/cvmx-core.o \
+	$(OBJ_DIR)/cvmx-coremask.o \
+	$(OBJ_DIR)/cvmx-cmd-queue.o \
+	$(OBJ_DIR)/cvmx-csr-db.o \
+	$(OBJ_DIR)/cvmx-csr-db-support.o \
+	$(OBJ_DIR)/cvmx-dfa.o \
+	$(OBJ_DIR)/cvmx-dma-engine.o \
+	$(OBJ_DIR)/cvmx-ebt3000.o \
+	$(OBJ_DIR)/cvmx-flash.o \
+	$(OBJ_DIR)/cvmx-fpa.o \
+	$(OBJ_DIR)/cvmx-helper-board.o \
+	$(OBJ_DIR)/cvmx-helper-errata.o \
+	$(OBJ_DIR)/cvmx-helper-fpa.o \
+	$(OBJ_DIR)/cvmx-helper-loop.o \
+	$(OBJ_DIR)/cvmx-helper-npi.o \
+	$(OBJ_DIR)/cvmx-helper-rgmii.o \
+	$(OBJ_DIR)/cvmx-helper-sgmii.o \
+	$(OBJ_DIR)/cvmx-helper-spi.o \
+	$(OBJ_DIR)/cvmx-helper-util.o \
+	$(OBJ_DIR)/cvmx-helper-xaui.o \
+	$(OBJ_DIR)/cvmx-helper.o \
+	$(OBJ_DIR)/cvmx-interrupt-rsl.o \
+	$(OBJ_DIR)/cvmx-interrupt-decodes.o \
+	$(OBJ_DIR)/cvmx-l2c.o \
+	$(OBJ_DIR)/cvmx-llm.o \
+	$(OBJ_DIR)/cvmx-log-arc.o \
+	$(OBJ_DIR)/cvmx-log.o \
+	$(OBJ_DIR)/cvmx-mgmt-port.o \
+	$(OBJ_DIR)/cvmx-nand.o \
+	$(OBJ_DIR)/cvmx-pcie.o \
+	$(OBJ_DIR)/cvmx-pko.o \
+	$(OBJ_DIR)/cvmx-pow.o \
+	$(OBJ_DIR)/cvmx-raid.o \
+	$(OBJ_DIR)/cvmx-spi.o \
+	$(OBJ_DIR)/cvmx-spi4000.o \
+	$(OBJ_DIR)/cvmx-sysinfo.o \
+	$(OBJ_DIR)/cvmx-thunder.o \
+	$(OBJ_DIR)/cvmx-tim.o \
+	$(OBJ_DIR)/cvmx-tra.o \
+	$(OBJ_DIR)/cvmx-twsi.o \
+	$(OBJ_DIR)/cvmx-usb.o \
+	$(OBJ_DIR)/cvmx-warn.o \
+	$(OBJ_DIR)/cvmx-zip.o \
+	$(OBJ_DIR)/cvmx-zone.o \
+	$(OBJ_DIR)/octeon-model.o \
+	$(OBJ_DIR)/octeon-pci-console.o
+ifeq (linux,$(findstring linux,$(OCTEON_TARGET)))
+OBJS_$(d)  +=  \
+	$(OBJ_DIR)/cvmx-app-init-linux.o
+else
+OBJS_$(d)  +=  \
+	$(OBJ_DIR)/cvmx-interrupt.o \
+	$(OBJ_DIR)/cvmx-interrupt-handler.o \
+	$(OBJ_DIR)/cvmx-app-init.o \
+	$(OBJ_DIR)/cvmx-malloc.o
+endif
+
+$(OBJS_$(d)):  CFLAGS_LOCAL := -I$(d) -O2 -g -W -Wall -Wno-unused-parameter -Wundef
+
+#  standard component Makefile rules
+
+DEPS_$(d)   :=  $(OBJS_$(d):.o=.d)
+
+LIBS_LIST   :=  $(LIBS_LIST) $(LIBRARY)
+
+CLEAN_LIST  :=  $(CLEAN_LIST) $(OBJS_$(d)) $(DEPS_$(d)) $(LIBRARY)
+
+-include $(DEPS_$(d))
+
+$(LIBRARY): $(OBJS_$(d))
+	$(AR) -cr $@ $^
+
+$(OBJ_DIR)/%.o:	$(d)/%.c
+	$(COMPILE)
+
+$(OBJ_DIR)/%.o:	$(d)/%.S
+	$(ASSEMBLE)
+
+$(OBJ_DIR)/cvmx-app-init-linux.o: $(d)/cvmx-app-init-linux.c
+	$(CC) $(CFLAGS_GLOBAL) $(CFLAGS_LOCAL) -MD -c -Umain -o $@ $<
+
+CFLAGS_SPECIAL := -I$(d) -I$(d)/cvmx-malloc -O2 -g -DUSE_CVM_THREADS=1 -D_REENTRANT
+
+$(OBJ_DIR)/cvmx-malloc.o: $(d)/cvmx-malloc/malloc.c
+	$(CC) $(CFLAGS_GLOBAL) $(CFLAGS_SPECIAL) -MD -c -o $@ $<
+
+#  standard component Makefile footer
+
+d   :=  $(dirstack_$(sp))
+sp  :=  $(basename $(sp))
diff --git a/executive-config.h.template b/executive-config.h.template
new file mode 100644
index 0000000000000..d44c9c7fd717a
--- /dev/null
+++ b/executive-config.h.template
@@ -0,0 +1,180 @@
+/***********************license start***************
+ * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *
+ *     * Neither the name of Cavium Networks nor the names of
+ *       its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written
+ *       permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+/*! 
+ * @file executive-config.h.template
+ *
+ * This file is a template for the executive-config.h file that each
+ * application that uses the simple exec must provide.  Each application
+ * should have an executive-config.h file in a directory named 'config'.
+ * If the application uses other components, config files for those
+ * components should be placed in the config directory as well.  The 
+ * macros defined in this file control the configuration and functionality
+ * provided by the simple executive.  Available macros are commented out
+ * and documented in this file.
+ */
+
+/*
+ * File version info: $Id: executive-config.h.template 41588 2009-03-19 19:41:00Z vmalov $
+ *
+ */
+#ifndef __EXECUTIVE_CONFIG_H__
+#define __EXECUTIVE_CONFIG_H__
+
+/* Define to enable the use of simple executive DFA functions */
+//#define CVMX_ENABLE_DFA_FUNCTIONS
+
+/* Define to enable the use of simple executive packet output functions.
+** For packet I/O setup enable the helper functions below. 
+*/ 
+//#define CVMX_ENABLE_PKO_FUNCTIONS
+
+/* Define to enable the use of simple executive timer bucket functions. 
+** Refer to cvmx-tim.[ch] for more information
+*/
+//#define CVMX_ENABLE_TIMER_FUNCTIONS
+
+/* Define to enable the use of simple executive helper functions. These
+** include many harware setup functions.  See cvmx-helper.[ch] for
+** details.
+*/
+//#define CVMX_ENABLE_HELPER_FUNCTIONS
+
+/* CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve before
+** the beginning of the packet. If necessary, override the default  
+** here.  See the IPD section of the hardware manual for MBUFF SKIP 
+** details.*/ 
+#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
+
+/* CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve in each
+** chained packet element. If necessary, override the default here */
+#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
+
+/* CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is enabled
+** for all input ports. This controls if IPD sends backpressure to all ports if
+** Octeon's FPA pools don't have enough packet or work queue entries. Even when
+** this is off, it is still possible to get backpressure from individual
+** hardware ports. When configuring backpressure, also check
+** CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override the default
+** here */
+#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
+
+/* CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
+**  function. Once it is enabled the hardware starts accepting packets. You
+**  might want to skip the IPD enable if configuration changes are need
+**  from the default helper setup. If necessary, override the default here */
+#define CVMX_HELPER_ENABLE_IPD 1
+
+/* CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
+** to incoming packets. */
+#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
+
+/* The following select which fields are used by the PIP to generate
+** the tag on INPUT
+** 0: don't include
+** 1: include */
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP   	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP   	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 	0
+#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL	0
+#define CVMX_HELPER_INPUT_TAG_INPUT_PORT	1
+
+/* Select skip mode for input ports */
+#define CVMX_HELPER_INPUT_PORT_SKIP_MODE	CVMX_PIP_PORT_CFG_MODE_SKIPL2
+
+/* Define the number of queues per output port */
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE0	1
+#define CVMX_HELPER_PKO_QUEUES_PER_PORT_INTERFACE1	1
+
+/* Configure PKO to use per-core queues (PKO lockless operation). 
+** Please see the related SDK documentation for PKO that illustrates 
+** how to enable and configure this option. */
+//#define CVMX_ENABLE_PKO_LOCKLESS_OPERATION 1
+//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 8
+//#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 8
+
+/* Force backpressure to be disabled.  This overrides all other
+** backpressure configuration */
+#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 1
+
+/* Disable the SPI4000's processing of backpressure packets and backpressure
+** generation. When this is 1, the SPI4000 will not stop sending packets when
+** receiving backpressure. It will also not generate backpressure packets when
+** its internal FIFOs are full. */
+#define CVMX_HELPER_DISABLE_SPI4000_BACKPRESSURE 1
+
+/* CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI initialization
+** routines wait for SPI training. You can override the value using
+** executive-config.h if necessary */
+#define CVMX_HELPER_SPI_TIMEOUT 10
+
+/* Select the number of low latency memory ports (interfaces) that
+** will be configured.  Valid values are 1 and 2.
+*/
+#define CVMX_LLM_CONFIG_NUM_PORTS 2
+
+/* Enable the fix for PKI-100 errata ("Size field is 8 too large in WQE and next
+** pointers"). If CVMX_ENABLE_LEN_M8_FIX is set to 0, the fix for this errata will 
+** not be enabled. 
+** 0: Fix is not enabled
+** 1: Fix is enabled, if supported by hardware
+*/
+#define CVMX_ENABLE_LEN_M8_FIX  1
+
+#if defined(CVMX_ENABLE_HELPER_FUNCTIONS) && !defined(CVMX_ENABLE_PKO_FUNCTIONS)
+#define CVMX_ENABLE_PKO_FUNCTIONS
+#endif
+
+/* Enable setting up of TLB entries to trap NULL pointer references */
+#define CVMX_CONFIG_NULL_POINTER_PROTECT	1
+
+/* Enable debug and informational printfs */
+#define CVMX_CONFIG_ENABLE_DEBUG_PRINTS 	1
+
+/* Executive resource descriptions provided in cvmx-resources.config */
+#include "cvmx-resources.config"
+
+#endif
diff --git a/octeon-feature.h b/octeon-feature.h
new file mode 100644
index 0000000000000..6e46f778e0bc2
--- /dev/null
+++ b/octeon-feature.h
@@ -0,0 +1,140 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ *
+ * File defining checks for different Octeon features.
+ *
+ * <hr>$Revision: 30468 $<hr>
+ */
+
+#ifndef __OCTEON_FEATURE_H__
+#define __OCTEON_FEATURE_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    OCTEON_FEATURE_SAAD,        /* Octeon models in the CN5XXX family and higher support atomic add instructions to memory (saa/saad) */
+    OCTEON_FEATURE_ZIP,         /* Does this Octeon support the ZIP offload engine? */
+    OCTEON_FEATURE_CRYPTO,      /* Does this Octeon support crypto acceleration using COP2? */
+    OCTEON_FEATURE_PCIE,        /* Does this Octeon support PCI express? */
+    OCTEON_FEATURE_KEY_MEMORY,  /* Some Octeon models support internal memory for storing cryptographic keys */
+    OCTEON_FEATURE_LED_CONTROLLER, /* Octeon has a LED controller for banks of external LEDs */
+    OCTEON_FEATURE_TRA,         /* Octeon has a trace buffer */
+    OCTEON_FEATURE_MGMT_PORT,   /* Octeon has a management port */
+    OCTEON_FEATURE_RAID,        /* Octeon has a raid unit */
+    OCTEON_FEATURE_USB,         /* Octeon has a builtin USB */
+    OCTEON_FEATURE_NO_WPTR,     /* Octeon IPD can run without using work queue entries */
+    OCTEON_FEATURE_DFA,         /* Octeon has DFA state machines */
+    OCTEON_FEATURE_MDIO_CLAUSE_45,     /* Octeon MDIO block supports clause 45 transactions for 10 Gig support */
+} octeon_feature_t;
+
+/**
+ * Determine if the current Octeon supports a specific feature. These
+ * checks have been optimized to be fairly quick, but they should still
+ * be kept out of fast path code.
+ *
+ * @param feature Feature to check for. This should always be a constant so the
+ *                compiler can remove the switch statement through optimization.
+ *
+ * @return Non zero if the feature exists. Zero if the feature does not
+ *         exist.
+ */
+static inline int octeon_has_feature(octeon_feature_t feature)
+{
+    switch (feature)
+    {
+        case OCTEON_FEATURE_SAAD:
+            return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
+
+        case OCTEON_FEATURE_ZIP:
+            if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+                return 0;
+            else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+                return 1;
+            else
+                return (!cvmx_fuse_read(121));
+
+        case OCTEON_FEATURE_CRYPTO:
+            return (!cvmx_fuse_read(90));
+
+        case OCTEON_FEATURE_PCIE:
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+
+        case OCTEON_FEATURE_KEY_MEMORY:
+        case OCTEON_FEATURE_LED_CONTROLLER:
+            return (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX));
+        case OCTEON_FEATURE_TRA:
+            return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX));
+        case OCTEON_FEATURE_MGMT_PORT:
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+        case OCTEON_FEATURE_RAID:
+            return (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX));
+        case OCTEON_FEATURE_USB:
+            return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX));
+        case OCTEON_FEATURE_NO_WPTR:
+            return ((OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) &&
+                    !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X));
+        case OCTEON_FEATURE_DFA:
+            if (!OCTEON_IS_MODEL(OCTEON_CN38XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN58XX))
+                return 0;
+            else if (OCTEON_IS_MODEL(OCTEON_CN3020))
+                return 0;
+            else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+                return 1;
+            else
+                return(!cvmx_fuse_read(120));
+        case OCTEON_FEATURE_MDIO_CLAUSE_45:
+            return (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)));
+    }
+    return 0;
+}
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif    /* __OCTEON_FEATURE_H__ */
diff --git a/octeon-model.c b/octeon-model.c
new file mode 100644
index 0000000000000..9a4dd3626279a
--- /dev/null
+++ b/octeon-model.c
@@ -0,0 +1,393 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+/**
+ * @file
+ *
+ * File defining functions for working with different Octeon
+ * models.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+#include "cvmx.h"
+#include "cvmx-pow.h"
+#include "cvmx-warn.h"
+
+#if defined(CVMX_BUILD_FOR_LINUX_USER) || defined(CVMX_BUILD_FOR_STANDALONE)
+#include <octeon-app-init.h>
+#include "cvmx-sysinfo.h"
+
+/**
+ * This function checks to see if the software is compatible with the
+ * chip it is running on.  This is called in the application startup code
+ * and does not need to be called directly by the application.
+ * Does not return if software is incompatible.
+ *
+ * @param chip_id chip id that the software is being run on.
+ *
+ * @return 0: runtime checking or exact version match
+ *         1: chip is newer revision than compiled for, but software will run properly.
+ */
+int octeon_model_version_check(uint32_t chip_id)
+{
+    //printf("Model Number: %s\n", octeon_model_get_string(chip_id));
+#if OCTEON_IS_COMMON_BINARY()
+    if (chip_id == OCTEON_CN38XX_PASS1)
+    {
+        printf("Runtime Octeon Model checking binaries do not support OCTEON_CN38XX_PASS1 chips\n");
+#ifdef CVMX_BUILD_FOR_STANDALONE
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+            CVMX_BREAK;
+        while (1);
+#else
+        exit(-1);
+#endif
+    }
+#else
+    /* Check for special case of mismarked 3005 samples, and adjust cpuid */
+    if (chip_id == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
+        chip_id |= 0x10;
+
+    if ((OCTEON_MODEL & 0xffffff) != chip_id)
+    {
+        if (!OCTEON_IS_MODEL((OM_IGNORE_REVISION | chip_id)) || (OCTEON_MODEL & 0xffffff) > chip_id || (((OCTEON_MODEL & 0xffffff) ^ chip_id) & 0x10))
+        {
+            printf("ERROR: Software not configured for this chip\n"
+                   "         Expecting ID=0x%08x, Chip is 0x%08x\n", (OCTEON_MODEL & 0xffffff), (unsigned int)chip_id);
+            if ((OCTEON_MODEL & 0xffffff) > chip_id)
+                printf("Refusing to run on older revision than program was compiled for.\n");
+#ifdef CVMX_BUILD_FOR_STANDALONE
+            if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+                CVMX_BREAK;
+            while (1);
+#else
+            exit(-1);
+#endif
+        }
+        else
+        {
+            printf("\n###################################################\n");
+            printf("WARNING: Software configured for older revision than running on.\n"
+                   "         Compiled for ID=0x%08x, Chip is 0x%08x\n", (OCTEON_MODEL & 0xffffff), (unsigned int)chip_id);
+            printf("###################################################\n\n");
+            return(1);
+        }
+    }
+#endif
+
+    cvmx_warn_if(CVMX_ENABLE_PARAMETER_CHECKING, "Parameter checks are enabled. Expect some performance loss due to the extra checking\n");
+    cvmx_warn_if(CVMX_ENABLE_CSR_ADDRESS_CHECKING, "CSR address checks are enabled. Expect some performance loss due to the extra checking\n");
+    cvmx_warn_if(CVMX_ENABLE_POW_CHECKS, "POW state checks are enabled. Expect some performance loss due to the extra checking\n");
+
+    return(0);
+}
+
+#endif
+/**
+ * Given the chip processor ID from COP0, this function returns a
+ * string representing the chip model number. The string is of the
+ * form CNXXXXpX.X-FREQ-SUFFIX.
+ * - XXXX = The chip model number
+ * - X.X = Chip pass number
+ * - FREQ = Current frequency in Mhz
+ * - SUFFIX = NSP, EXP, SCP, SSP, or CP
+ *
+ * @param chip_id Chip ID
+ *
+ * @return Model string
+ */
+const char *octeon_model_get_string(uint32_t chip_id)
+{
+    static char         buffer[32];
+    return octeon_model_get_string_buffer(chip_id,buffer);
+}
+
+/* Version of octeon_model_get_string() that takes buffer as argument, as
+** running early in u-boot static/global variables don't work when running from
+** flash
+*/
+const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer)
+{
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    extern uint64_t octeon_get_clock_rate(void);
+#endif
+    const char *        family;
+    const char *        core_model;
+    char                pass[4];
+    int                 clock_mhz;
+    const char *        suffix;
+    cvmx_l2d_fus3_t     fus3;
+    int                 num_cores;
+    cvmx_mio_fus_dat2_t fus_dat2;
+    cvmx_mio_fus_dat3_t fus_dat3;
+    char fuse_model[10];
+    uint32_t fuse_data = 0;
+
+    fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+    fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+    fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+    num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
+
+    /* Make sure the non existant devices look disabled */
+    switch ((chip_id >> 8) & 0xff)
+    {
+        case 6: /* CN50XX */
+        case 2: /* CN30XX */
+            fus_dat3.s.nodfa_dte = 1;
+            fus_dat3.s.nozip = 1;
+            break;
+        case 4: /* CN57XX or CN56XX */
+            fus_dat3.s.nodfa_dte = 1;
+            break;
+        default:
+            break;
+    }
+
+    /* Make a guess at the suffix */
+    /* NSP = everything */
+    /* EXP = No crypto */
+    /* SCP = No DFA, No zip */
+    /* CP = No DFA, No crypto, No zip */
+    if (fus_dat3.s.nodfa_dte)
+    {
+        if (fus_dat2.s.nocrypto)
+            suffix = "CP";
+        else
+            suffix = "SCP";
+    }
+    else if (fus_dat2.s.nocrypto)
+        suffix = "EXP";
+    else
+        suffix = "NSP";
+
+    /* Assume pass number is encoded using <5:3><2:0>. Exceptions will be
+        fixed later */
+    sprintf(pass, "%d.%d", (int)((chip_id>>3)&7)+1, (int)chip_id&7);
+
+    /* Use the number of cores to determine the last 2 digits of the model
+        number. There are some exceptions that are fixed later */
+    switch (num_cores)
+    {
+        case 16: core_model = "60"; break;
+        case 15: core_model = "58"; break;
+        case 14: core_model = "55"; break;
+        case 13: core_model = "52"; break;
+        case 12: core_model = "50"; break;
+        case 11: core_model = "48"; break;
+        case 10: core_model = "45"; break;
+        case  9: core_model = "42"; break;
+        case  8: core_model = "40"; break;
+        case  7: core_model = "38"; break;
+        case  6: core_model = "34"; break;
+        case  5: core_model = "32"; break;
+        case  4: core_model = "30"; break;
+        case  3: core_model = "25"; break;
+        case  2: core_model = "20"; break;
+        case  1: core_model = "10"; break;
+        default: core_model = "XX"; break;
+    }
+
+    /* Now figure out the family, the first two digits */
+    switch ((chip_id >> 8) & 0xff)
+    {
+        case 0: /* CN38XX, CN37XX or CN36XX */
+            if (fus3.cn38xx.crip_512k)
+            {
+                /* For some unknown reason, the 16 core one is called 37 instead of 36 */
+                if (num_cores >= 16)
+                    family = "37";
+                else
+                    family = "36";
+            }
+            else
+                family = "38";
+            /* This series of chips didn't follow the standard pass numbering */
+            switch (chip_id & 0xf)
+            {
+                case 0: strcpy(pass, "1.X"); break;
+                case 1: strcpy(pass, "2.X"); break;
+                case 3: strcpy(pass, "3.X"); break;
+                default:strcpy(pass, "X.X"); break;
+            }
+            break;
+        case 1: /* CN31XX or CN3020 */
+            if ((chip_id & 0x10) || fus3.cn31xx.crip_128k)
+                family = "30";
+            else
+                family = "31";
+            /* This series of chips didn't follow the standard pass numbering */
+            switch (chip_id & 0xf)
+            {
+                case 0: strcpy(pass, "1.0"); break;
+                case 2: strcpy(pass, "1.1"); break;
+                default:strcpy(pass, "X.X"); break;
+            }
+            break;
+        case 2: /* CN3010 or CN3005 */
+            family = "30";
+            /* A chip with half cache is an 05 */
+            if (fus3.cn30xx.crip_64k)
+                core_model = "05";
+            /* This series of chips didn't follow the standard pass numbering */
+            switch (chip_id & 0xf)
+            {
+                case 0: strcpy(pass, "1.0"); break;
+                case 2: strcpy(pass, "1.1"); break;
+                default:strcpy(pass, "X.X"); break;
+            }
+            break;
+        case 3: /* CN58XX */
+            family = "58";
+            /* Special case. 4 core, no crypto */
+            if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
+                core_model = "29";
+
+            /* Pass 1 uses different encodings for pass numbers */
+            if ((chip_id & 0xFF)< 0x8)
+            {
+                switch (chip_id & 0x3)
+                {
+                    case 0: strcpy(pass, "1.0"); break;
+                    case 1: strcpy(pass, "1.1"); break;
+                    case 3: strcpy(pass, "1.2"); break;
+                    default:strcpy(pass, "1.X"); break;
+                }
+            }
+            break;
+        case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
+            if (fus_dat2.cn56xx.raid_en)
+            {
+                if (fus3.cn56xx.crip_1024k)
+                    family = "55";
+                else
+                    family = "57";
+                if (fus_dat2.cn56xx.nocrypto)
+                    suffix = "SP";
+                else
+                    suffix = "SSP";
+            }
+            else 
+            {
+                if (fus_dat2.cn56xx.nocrypto)
+                    suffix = "CP";
+                else
+                {
+                    suffix = "NSP";
+                    if (fus_dat3.s.nozip)
+                        suffix = "SCP";
+                }
+                if (fus3.cn56xx.crip_1024k)
+                    family = "54";
+                else
+                    family = "56";
+            }
+            break;
+        case 6: /* CN50XX */
+            family = "50";
+            break;
+        case 7: /* CN52XX */
+            if (fus3.cn52xx.crip_256k)
+                family = "51";
+            else
+                family = "52";
+            break;
+        default:
+            family = "XX";
+            core_model = "XX";
+            strcpy(pass, "X.X");
+            suffix = "XXX";
+            break;
+    }
+
+#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
+    clock_mhz = octeon_get_clock_rate() / 1000000;
+#elif defined(CVMX_BUILD_FOR_LINUX_HOST)
+    clock_mhz = 0;
+#else
+    if (cvmx_sysinfo_get())
+        clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+    else
+        clock_mhz = 0;
+#endif
+
+    if (family[0] != '3')
+    {
+        /* Check for model in fuses, overrides normal decode */
+        /* This is _not_ valid for Octeon CN3XXX models */
+        fuse_data |= cvmx_fuse_read_byte(51);
+        fuse_data = fuse_data << 8;
+        fuse_data |= cvmx_fuse_read_byte(50);
+        fuse_data = fuse_data << 8;
+        fuse_data |= cvmx_fuse_read_byte(49);
+        fuse_data = fuse_data << 8;
+        fuse_data |= cvmx_fuse_read_byte(48);
+        if (fuse_data & 0x7ffff)
+        {
+            int model = fuse_data & 0x3fff;
+            int suffix = (fuse_data >> 14) & 0x1f;
+            if (suffix && model)  /* Have both number and suffix in fuses, so both */
+            {
+                sprintf(fuse_model, "%d%c",model, 'A' + suffix - 1);
+                core_model = "";
+                family = fuse_model;
+            }
+            else if (suffix && !model)   /* Only have suffix, so add suffix to 'normal' model number */
+            {
+                sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
+                core_model = fuse_model;
+            }
+            else /* Don't have suffix, so just use model from fuses */
+            {
+                sprintf(fuse_model, "%d",model);
+                core_model = "";
+                family = fuse_model;
+            }
+        }
+    }
+#ifdef CVMX_BUILD_FOR_UBOOT
+    sprintf(buffer, "CN%s%s-%s pass %s", family, core_model, suffix, pass);
+#else
+    sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
+#endif
+    return buffer;
+}
diff --git a/octeon-model.h b/octeon-model.h
new file mode 100644
index 0000000000000..3191ea421beaf
--- /dev/null
+++ b/octeon-model.h
@@ -0,0 +1,307 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+/**
+ * @file
+ *
+ * File defining different Octeon model IDs and macros to
+ * compare them.
+ *
+ * <hr>$Revision: 41586 $<hr>
+ */
+
+#ifndef __OCTEON_MODEL_H__
+#define __OCTEON_MODEL_H__
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+
+/* NOTE: These must match what is checked in common-config.mk */
+/* Defines to represent the different versions of Octeon.  */
+
+
+/* IMPORTANT: When the default pass is updated for an Octeon Model,
+** the corresponding change must also be made in the oct-sim script. */
+
+
+/* The defines below should be used with the OCTEON_IS_MODEL() macro to
+** determine what model of chip the software is running on.  Models ending
+** in 'XX' match multiple models (families), while specific models match only
+** that model.  If a pass (revision) is specified, then only that revision
+** will be matched.  Care should be taken when checking for both specific
+** models and families that the specific models are checked for first.
+** While these defines are similar to the processor ID, they are not intended
+** to be used by anything other that the OCTEON_IS_MODEL framework, and
+** the values are subject to change at anytime without notice.
+**
+** NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* macros
+** should be used outside of this file.  All other macros are for internal
+** use only, and may change without notice.
+*/
+
+
+/* Flag bits in top byte */
+#define OM_IGNORE_REVISION        0x01000000      /* Ignores revision in model checks */
+#define OM_CHECK_SUBMODEL         0x02000000      /* Check submodels */
+#define OM_MATCH_PREVIOUS_MODELS  0x04000000      /* Match all models previous than the one specified */
+#define OM_IGNORE_MINOR_REVISION  0x08000000      /* Ignores the minor revison on newer parts */
+#define OM_FLAG_MASK              0xff000000
+
+/*
+ * CN5XXX models with new revision encoding
+ */
+#define OCTEON_CN58XX_PASS1_0   0x000d0300
+#define OCTEON_CN58XX_PASS1_1   0x000d0301
+#define OCTEON_CN58XX_PASS1_2   0x000d0303
+#define OCTEON_CN58XX_PASS2_0   0x000d0308
+#define OCTEON_CN58XX_PASS2_1   0x000d0309
+#define OCTEON_CN58XX_PASS2_2   0x000d030a
+#define OCTEON_CN58XX_PASS2_3   0x000d030b
+
+#define OCTEON_CN58XX           (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS1     OCTEON_CN58XX_PASS1_X
+#define OCTEON_CN58XX_PASS2     OCTEON_CN58XX_PASS2_X
+
+#define OCTEON_CN56XX_PASS1_0   0x000d0400
+#define OCTEON_CN56XX_PASS1_1   0x000d0401
+#define OCTEON_CN56XX_PASS2_0   0x000d0408
+#define OCTEON_CN56XX_PASS2_1   0x000d0409
+
+#define OCTEON_CN56XX           (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS1     OCTEON_CN56XX_PASS1_X
+#define OCTEON_CN56XX_PASS2     OCTEON_CN56XX_PASS2_X
+
+#define OCTEON_CN57XX           OCTEON_CN56XX
+#define OCTEON_CN57XX_PASS1     OCTEON_CN56XX_PASS1
+#define OCTEON_CN57XX_PASS2     OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN55XX           OCTEON_CN56XX
+#define OCTEON_CN55XX_PASS1     OCTEON_CN56XX_PASS1
+#define OCTEON_CN55XX_PASS2     OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN54XX           OCTEON_CN56XX
+#define OCTEON_CN54XX_PASS1     OCTEON_CN56XX_PASS1
+#define OCTEON_CN54XX_PASS2     OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN50XX_PASS1_0   0x000d0600
+
+#define OCTEON_CN50XX           (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN50XX_PASS1     OCTEON_CN50XX_PASS1_X
+
+/* NOTE: Octeon CN5000F model is not identifiable using the OCTEON_IS_MODEL()
+    functions, but are treated as CN50XX */
+
+#define OCTEON_CN52XX_PASS1_0   0x000d0700
+#define OCTEON_CN52XX_PASS2_0   0x000d0708
+
+#define OCTEON_CN52XX           (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
+#define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
+
+/* 
+ * CN3XXX models with old revision enconding
+ */
+#define OCTEON_CN38XX_PASS1     0x000d0000
+#define OCTEON_CN38XX_PASS2     0x000d0001
+#define OCTEON_CN38XX_PASS3     0x000d0003
+#define OCTEON_CN38XX           (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
+
+#define OCTEON_CN36XX           OCTEON_CN38XX
+#define OCTEON_CN36XX_PASS2     OCTEON_CN38XX_PASS2
+#define OCTEON_CN36XX_PASS3     OCTEON_CN38XX_PASS3
+
+/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
+#define OCTEON_CN31XX_PASS1     0x000d0100
+#define OCTEON_CN31XX_PASS1_1   0x000d0102
+#define OCTEON_CN31XX           (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
+
+/* This model is only used for internal checks, it
+** is not a valid model for the OCTEON_MODEL environment variable.
+** This matches the CN3010 and CN3005 but NOT the CN3020*/
+#define OCTEON_CN30XX_PASS1     0x000d0200
+#define OCTEON_CN30XX_PASS1_1   0x000d0202
+#define OCTEON_CN30XX           (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
+
+#define OCTEON_CN3005_PASS1     (0x000d0210 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1_0   (0x000d0210 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1_1   (0x000d0212 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+
+#define OCTEON_CN3010_PASS1     (0x000d0200 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1_0   (0x000d0200 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1_1   (0x000d0202 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+
+#define OCTEON_CN3020_PASS1     (0x000d0110 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1_0   (0x000d0110 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1_1   (0x000d0112 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+
+
+
+/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
+#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
+
+/* The revision byte (low byte) has two different encodings.
+** CN3XXX:
+** 
+**     bits
+**     <7:5>: reserved (0)
+**     <4>:   alternate package
+**     <3:0>: revision
+**     
+** CN5XXX:
+** 
+**     bits
+**     <7>:   reserved (0)
+**     <6>:   alternate package
+**     <5:3>: major revision
+**     <2:0>: minor revision
+** 
+*/ 
+
+/* Masks used for the various types of model/family/revision matching */
+#define OCTEON_38XX_FAMILY_MASK      0x00ffff00
+#define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f
+#define OCTEON_38XX_MODEL_MASK       0x00ffff10
+#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
+
+/* CN5XXX and later use different layout of bits in the revision ID field */
+#define OCTEON_58XX_FAMILY_MASK      OCTEON_38XX_FAMILY_MASK
+#define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f
+#define OCTEON_58XX_MODEL_MASK       0x00ffffc0
+#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
+#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
+
+
+#define __OCTEON_MATCH_MASK__(x,y,z) (((x) & (z)) == ((y) & (z)))
+
+
+/* NOTE: This for internal use only!!!!! */
+#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
+    ((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && (\
+     ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == 0) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
+     ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+       && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
+    )) || \
+    (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && (\
+     ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == 0) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
+     ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
+       && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
+     ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+       && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
+    )))
+
+#if defined(USE_RUNTIME_MODEL_CHECKS) || defined(__U_BOOT__) || (defined(__linux__) && defined(__KERNEL__))
+
+/* NOTE: This for internal use only!!!!! */
+static inline int __octeon_is_model_runtime__(uint32_t model)
+{
+    uint32_t cpuid = cvmx_get_proc_id();
+
+    /* Check for special case of mismarked 3005 samples. We only need to check
+        if the sub model isn't being ignored */
+    if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL)
+    {
+        if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
+            cpuid |= 0x10;
+    }
+    return(__OCTEON_IS_MODEL_COMPILE__(model, cpuid));
+}
+
+/* The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
+** in a program.
+** This should be kept runtime if at all possible  and must be conditionalized
+** with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
+**
+** Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
+** is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
+** I.e.:
+**  #if OCTEON_IS_MODEL(OCTEON_CN56XX)  ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
+*/
+#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
+#define OCTEON_IS_COMMON_BINARY() 1
+#undef OCTEON_MODEL
+#else
+#define CVMX_COMPILED_FOR(x) __OCTEON_IS_MODEL_COMPILE__(x, OCTEON_MODEL)
+
+#define OCTEON_IS_MODEL(x) \
+    (((x & (OM_IGNORE_REVISION | OM_IGNORE_MINOR_REVISION)) != 0) \
+    ? __OCTEON_IS_MODEL_COMPILE__(x, OCTEON_MODEL) \
+    : __OCTEON_IS_MODEL_COMPILE__(x, cvmx_get_proc_id()))
+
+#define OCTEON_IS_COMMON_BINARY() 0
+#endif
+
+const char *octeon_model_get_string(uint32_t chip_id);
+const char *octeon_model_get_string_buffer(uint32_t chip_id, char * buffer);
+
+#include "octeon-feature.h"
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif    /* __OCTEON_MODEL_H__ */
diff --git a/octeon-pci-console.c b/octeon-pci-console.c
new file mode 100644
index 0000000000000..7f4e5ab5e0547
--- /dev/null
+++ b/octeon-pci-console.c
@@ -0,0 +1,480 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+#define CVMX_USE_1_TO_1_TLB_MAPPINGS 0
+
+#include "cvmx-platform.h"
+
+#include "cvmx.h"
+#include "cvmx-spinlock.h"
+#define	MIN(a,b) (((a)<(b))?(a):(b))
+
+#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL)
+#include "cvmx-bootmem.h"
+#endif
+
+#include "octeon-pci-console.h"
+
+#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
+#include "octeon-pci.h"
+#endif
+
+
+/* The following code is only used in standalone CVMX applications. It does
+    not apply for kernel or Linux programming */
+#if defined(OCTEON_TARGET) && !defined(__linux__)
+
+static int cvmx_pci_console_num = 0;
+static int per_core_pci_consoles = 0;
+static uint64_t pci_console_desc_addr = 0;
+/* This function for simple executive internal use only - do not use in any application */
+int  __cvmx_pci_console_write (int fd, char *buf, int nbytes)
+{
+    int console_num;
+    if (fd >= 0x10000000)
+    {
+        console_num = fd & 0xFFFF;
+    }
+    else if (per_core_pci_consoles)
+    {
+        console_num = cvmx_get_core_num();
+    }
+    else
+        console_num = cvmx_pci_console_num;
+
+    if (!pci_console_desc_addr)
+    {
+        cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
+        pci_console_desc_addr = block_desc->base_addr;
+    }
+
+
+    return octeon_pci_console_write(pci_console_desc_addr, console_num, buf, nbytes, 0);
+
+}
+
+#endif
+
+
+#if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE))
+int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
+{
+    if (rd_idx >= buffer_size || wr_idx >= buffer_size)
+        return -1;
+
+    return (((buffer_size -1) - (wr_idx - rd_idx))%buffer_size);
+}
+int octeon_pci_console_buffer_avail_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
+{
+    if (rd_idx >= buffer_size || wr_idx >= buffer_size)
+        return -1;
+
+    return (buffer_size - 1 - octeon_pci_console_buffer_free_bytes(buffer_size, wr_idx, rd_idx));
+}
+#endif
+
+
+
+/* The following code is only used under Linux userspace when you are using
+    CVMX */
+#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
+int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags)
+{
+    if (!console_desc_addr)
+        return -1;
+
+    /* Get global pci console information and look up specific console structure. */
+    uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
+//    printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
+    if (console_num >= num_consoles)
+    {
+        printf("ERROR: attempting to read non-existant console: %d\n", console_num);
+        return(-1);
+    }
+    uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
+//    printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
+
+    uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
+    /* Check to see if any data is available */
+    uint32_t rd_idx, wr_idx;
+    uint64_t base_addr;
+
+    base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
+    rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
+    wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
+
+//    printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
+    int bytes_to_write = octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
+    if (bytes_to_write <= 0)
+        return bytes_to_write;
+    bytes_to_write = MIN(bytes_to_write, write_reqest_size);
+    /* Check to see if what we want to write is not contiguous, and limit ourselves to the contiguous block*/
+    if (wr_idx + bytes_to_write >= console_buffer_size)
+        bytes_to_write = console_buffer_size - wr_idx;
+
+//    printf("Attempting to write %d bytes, (buf size: %d)\n", bytes_to_write, write_reqest_size);
+
+    octeon_pci_write_mem(base_addr + wr_idx, buffer, bytes_to_write, OCTEON_PCI_ENDIAN_64BIT_SWAP);
+    octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index), (wr_idx + bytes_to_write)%console_buffer_size);
+
+    return bytes_to_write;
+
+}
+
+int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags)
+{
+    if (!console_desc_addr)
+        return -1;
+
+    /* Get global pci console information and look up specific console structure. */
+    uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
+//    printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
+    if (console_num >= num_consoles)
+    {
+        printf("ERROR: attempting to read non-existant console: %d\n", console_num);
+        return(-1);
+    }
+    uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
+    uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
+//    printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
+
+    /* Check to see if any data is available */
+    uint32_t rd_idx, wr_idx;
+    uint64_t base_addr;
+
+    base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
+    rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
+    wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
+
+//    printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
+    int bytes_to_read = octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
+    if (bytes_to_read <= 0)
+        return bytes_to_read;
+
+
+    bytes_to_read = MIN(bytes_to_read, buf_size);
+    /* Check to see if what we want to read is not contiguous, and limit ourselves to the contiguous block*/
+    if (rd_idx + bytes_to_read >= console_buffer_size)
+        bytes_to_read = console_buffer_size - rd_idx;
+
+
+    octeon_pci_read_mem(buffer, base_addr + rd_idx, bytes_to_read,OCTEON_PCI_ENDIAN_64BIT_SWAP);
+    octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index), (rd_idx + bytes_to_read)%console_buffer_size);
+
+    return bytes_to_read;
+}
+
+
+int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num)
+{
+    if (!console_desc_addr)
+        return -1;
+
+    /* Get global pci console information and look up specific console structure. */
+    uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
+//    printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
+    if (console_num >= num_consoles)
+    {
+        printf("ERROR: attempting to read non-existant console: %d\n", console_num);
+        return -1;
+    }
+    uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
+//    printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
+
+    uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
+    /* Check to see if any data is available */
+    uint32_t rd_idx, wr_idx;
+    uint64_t base_addr;
+
+    base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
+    rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
+    wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
+
+//    printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
+    return octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
+}
+
+
+int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num)
+{
+    if (!console_desc_addr)
+        return -1;
+
+    /* Get global pci console information and look up specific console structure. */
+    uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
+//    printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
+    if (console_num >= num_consoles)
+    {
+        printf("ERROR: attempting to read non-existant console: %d\n", console_num);
+        return(-1);
+    }
+    uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
+    uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
+//    printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
+
+    /* Check to see if any data is available */
+    uint32_t rd_idx, wr_idx;
+    uint64_t base_addr;
+
+    base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
+    rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
+    wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
+
+//    printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
+    return octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
+}
+
+
+#endif /* TARGET_HOST */
+
+
+
+
+
+
+/* This code is only available in a kernel or CVMX standalone. It can't be used
+    from userspace */
+#if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE))
+
+static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num)
+{
+    octeon_pci_console_desc_t *cons_desc_ptr;
+
+    if (!console_desc_addr)
+        return NULL;
+
+    cons_desc_ptr = (octeon_pci_console_desc_t *)cvmx_phys_to_ptr(console_desc_addr);
+    if (console_num >= cons_desc_ptr->num_consoles)
+        return NULL;
+
+    return (octeon_pci_console_t *)cvmx_phys_to_ptr(cons_desc_ptr->console_addr_array[console_num]);
+}
+
+
+int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags)
+{
+    octeon_pci_console_t *cons_ptr;
+    cvmx_spinlock_t *lock;
+    int bytes_available;
+    char *buf_ptr;
+    int bytes_written;
+
+    cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
+    if (!cons_ptr)
+        return -1;
+
+    lock = (cvmx_spinlock_t *)&cons_ptr->lock;
+
+    buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
+    bytes_written = 0;
+    cvmx_spinlock_lock(lock);
+    while (bytes_to_write > 0)
+    {
+        bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->output_write_index, cons_ptr->output_read_index);
+//        printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
+        if (bytes_available > 0)
+        {
+            int write_size = MIN(bytes_available, bytes_to_write);
+            /* Limit ourselves to what we can output in a contiguous block */
+            if (cons_ptr->output_write_index + write_size >= cons_ptr->buf_size)
+                write_size = cons_ptr->buf_size - cons_ptr->output_write_index;
+
+            memcpy(buf_ptr + cons_ptr->output_write_index, buffer + bytes_written, write_size);
+            CVMX_SYNCW;  /* Make sure data is visible before changing write index */
+            cons_ptr->output_write_index = (cons_ptr->output_write_index + write_size)%cons_ptr->buf_size;
+            bytes_to_write -= write_size;
+            bytes_written += write_size;
+        }
+        else if (bytes_available == 0)
+        {
+            /* Check to see if we should wait for room, or return after a partial write */
+            if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
+                goto done;
+
+            cvmx_wait(1000000);  /* Delay if we are spinning */
+        }
+        else
+        {
+            bytes_written = -1;
+            goto done;
+        }
+    }
+
+done:
+    cvmx_spinlock_unlock(lock);
+    return(bytes_written);
+}
+
+int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags)
+{
+    int bytes_available;
+    char *buf_ptr;
+    cvmx_spinlock_t *lock;
+    int bytes_read;
+    int read_size;
+    octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
+    if (!cons_ptr)
+        return -1;
+
+    buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
+
+    bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
+    if (bytes_available < 0)
+        return bytes_available;
+
+    lock = (cvmx_spinlock_t *)&cons_ptr->lock;
+    cvmx_spinlock_lock(lock);
+
+    if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK))
+    {
+        /* Wait for some data to be available */
+        while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index)))
+            cvmx_wait(1000000);
+    }
+
+    bytes_read = 0;
+//        printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
+
+    /* Don't overflow the buffer passed to us */
+    read_size = MIN(bytes_available, buffer_size);
+
+    /* Limit ourselves to what we can input in a contiguous block */
+    if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
+        read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
+
+    memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
+    cons_ptr->input_read_index = (cons_ptr->input_read_index + read_size)%cons_ptr->buf_size;
+    bytes_read += read_size;
+
+    cvmx_spinlock_unlock(lock);
+    return(bytes_read);
+}
+
+
+int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num)
+{
+    int bytes_available;
+    octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
+    if (!cons_ptr)
+        return -1;
+
+    bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
+    if (bytes_available >= 0)
+        return(bytes_available);
+    else
+        return 0;
+}
+
+
+int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num)
+{
+    int bytes_available;
+    octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
+    if (!cons_ptr)
+        return -1;
+
+    bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
+    if (bytes_available >= 0)
+        return(bytes_available);
+    else
+        return 0;
+}
+
+#endif
+
+
+/* This code can only be used in the bootloader */
+#if defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE)
+#define DDR0_TOP        0x10000000
+#define DDR2_BASE       0x20000000
+uint64_t  octeon_pci_console_init(int num_consoles, int buffer_size)
+{
+    octeon_pci_console_desc_t *cons_desc_ptr;
+    octeon_pci_console_t *cons_ptr;
+
+    /* Compute size required for pci console structure */
+    int alloc_size = num_consoles * (buffer_size * 2 + sizeof(octeon_pci_console_t) + sizeof(uint64_t)) + sizeof(octeon_pci_console_desc_t);
+
+    /* Allocate memory for the consoles.  This must be in the range addresssible by the bootloader.
+    ** Try to do so in a manner which minimizes fragmentation.  We try to put it at the top of DDR0 or bottom of
+    ** DDR2 first, and only do generic allocation if those fail */
+    int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR0_TOP - alloc_size - 128, DDR0_TOP, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
+    if (console_block_addr < 0)
+        console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR2_BASE + 1, DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
+    if (console_block_addr < 0)
+        console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
+    if (console_block_addr < 0)
+        return 0;
+
+    cons_desc_ptr = (void *)(uint32_t)console_block_addr;
+
+    memset(cons_desc_ptr, 0, alloc_size);  /* Clear entire alloc'ed memory */
+
+    cons_desc_ptr->lock = 1; /* initialize as locked until we are done */
+    CVMX_SYNCW;
+    cons_desc_ptr->num_consoles = num_consoles;
+    cons_desc_ptr->flags = 0;
+    cons_desc_ptr->major_version = OCTEON_PCI_CONSOLE_MAJOR_VERSION;
+    cons_desc_ptr->minor_version = OCTEON_PCI_CONSOLE_MINOR_VERSION;
+
+    int i;
+    uint64_t avail_addr = console_block_addr + sizeof(octeon_pci_console_desc_t) + num_consoles * sizeof(uint64_t);
+    for (i = 0; i < num_consoles;i++)
+    {
+        cons_desc_ptr->console_addr_array[i] = avail_addr;
+        cons_ptr = (void *)(uint32_t)cons_desc_ptr->console_addr_array[i];
+        avail_addr += sizeof(octeon_pci_console_t);
+        cons_ptr->input_base_addr = avail_addr;
+        avail_addr += buffer_size;
+        cons_ptr->output_base_addr = avail_addr;
+        avail_addr += buffer_size;
+        cons_ptr->buf_size = buffer_size;
+    }
+    CVMX_SYNCW;
+    cons_desc_ptr->lock = 0;
+
+    return console_block_addr;
+
+
+}
+#endif
diff --git a/octeon-pci-console.h b/octeon-pci-console.h
new file mode 100644
index 0000000000000..d5f06154d5f8f
--- /dev/null
+++ b/octeon-pci-console.h
@@ -0,0 +1,138 @@
+/***********************license start***************
+ *  Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
+ *  reserved.
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are
+ *  met:
+ *
+ *      * Redistributions of source code must retain the above copyright
+ *        notice, this list of conditions and the following disclaimer.
+ *
+ *      * Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials provided
+ *        with the distribution.
+ *
+ *      * Neither the name of Cavium Networks nor the names of
+ *        its contributors may be used to endorse or promote products
+ *        derived from this software without specific prior written
+ *        permission.
+ *
+ *  TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ *  AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ *  OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ *  RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ *  REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ *  DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ *  OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ *  PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ *  POSSESSION OR CORRESPONDENCE TO DESCRIPTION.  THE ENTIRE RISK ARISING OUT
+ *  OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ *  For any questions regarding licensing please contact marketing@caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+
+
+
+
+
+
+#ifndef __OCTEON_PCI_CONSOLE_H__
+#define __OCTEON_PCI_CONSOLE_H__
+
+#include "cvmx-platform.h"
+
+/* Current versions */
+#define OCTEON_PCI_CONSOLE_MAJOR_VERSION    1
+#define OCTEON_PCI_CONSOLE_MINOR_VERSION    0
+
+#define OCTEON_PCI_CONSOLE_BLOCK_NAME   "__pci_console"
+
+
+/* Structure that defines a single console.
+
+
+* Note: when read_index == write_index, the buffer is empty.  The actual usable size
+*       of each console is console_buf_size -1;
+*/
+typedef struct {
+    uint64_t input_base_addr;
+    uint32_t input_read_index;
+    uint32_t input_write_index;
+    uint64_t output_base_addr;
+    uint32_t output_read_index;
+    uint32_t output_write_index;
+    uint32_t lock;
+    uint32_t buf_size;
+} octeon_pci_console_t;
+
+
+/* This is the main container structure that contains all the information
+about all PCI consoles.  The address of this structure is passed to various
+routines that operation on PCI consoles.
+*/
+typedef struct {
+    uint32_t major_version;
+    uint32_t minor_version;
+    uint32_t lock;
+    uint32_t flags;
+    uint32_t num_consoles;
+    uint32_t pad;
+    /* must be 64 bit aligned here... */
+    uint64_t console_addr_array[0];  /* Array of addresses of octeon_pci_console_t structures */
+    /* Implicit storage for console_addr_array */
+} octeon_pci_console_desc_t;
+
+
+/* Flag definitions for octeon_pci_console_desc_t */
+enum {
+    OCT_PCI_CON_DESC_FLAG_PERCPU = 1 << 0,  /* If set, output from core N will be sent to console N */
+};
+
+#if defined(OCTEON_TARGET) && !defined(__linux__)
+/**
+ * This is an internal-only function that is called from within the simple executive
+ * C library, and is not intended for any other use.
+ *
+ * @param fd
+ * @param buf
+ * @param nbytes
+ *
+ * @return
+ */
+int  __cvmx_pci_console_write (int fd, char *buf, int nbytes);
+#endif
+
+
+#ifdef CVMX_BUILD_FOR_UBOOT
+uint64_t octeon_pci_console_init(int num_consoles, int buffer_size);
+#endif
+
+/* Flag definitions for read/write functions */
+enum {
+    OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,  /* If set, read/write functions won't block waiting for space or data.
+                                          * For reads, 0 bytes may be read, and for writes not all of the
+                                          * supplied data may be written.*/
+};
+
+#if !defined(__linux__) || defined(__KERNEL__)
+int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags);
+int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num);
+
+int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags);
+int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num);
+#endif
+
+#if !defined(OCTEON_TARGET) && defined(__linux__) && !defined(__KERNEL__)
+int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags);
+int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num);
+
+int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags);
+int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num);
+#endif
+#endif
diff --git a/perfzilla_screen.png b/perfzilla_screen.png
new file mode 100644
index 0000000000000..512310c3b0994
--- /dev/null
+++ b/perfzilla_screen.png